On Thursday 19 December 2013 12:49 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 12:37 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Thursday 19 December 2013 12:24 PM, Jagan Teki wrote:
On Mon, Nov 25, 2013 at 4:28 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Thursday 14
On Thu, Dec 19, 2013 at 2:17 PM, Sourav Poddar sourav.pod...@ti.com wrote:
On Thursday 19 December 2013 12:49 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 12:37 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Thursday 19 December 2013 12:24 PM, Jagan Teki wrote:
On Mon, Nov 25, 2013 at
On Thursday 19 December 2013 02:21 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 2:17 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Thursday 19 December 2013 12:49 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 12:37 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Thursday 19 December 2013
On Thu, Dec 19, 2013 at 2:28 PM, Sourav Poddar sourav.pod...@ti.com wrote:
On Thursday 19 December 2013 02:21 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 2:17 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Thursday 19 December 2013 12:49 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at
On Thu, Dec 19, 2013 at 2:28 PM, Sourav Poddar sourav.pod...@ti.com wrote:
On Thursday 19 December 2013 02:21 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 2:17 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Thursday 19 December 2013 12:49 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at
On Thursday 19 December 2013 02:50 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 2:28 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Thursday 19 December 2013 02:21 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 2:17 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Thursday 19 December 2013
Hi Benoît, hi Fabio,
On 17/12/2013 22:18, Benoît Thébaudeau wrote:
Hi Fabio,
On Tuesday, December 17, 2013 9:03:40 PM, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
When using the fuse API in U-boot user must calculate the 'bank' and 'word'
values.
Provide a real
On 12/18/2013 04:29 PM, Jagannadha Sutradharudu Teki wrote:
Zynq qspi controller driver supports single bus
with singe chipselect.
here is typo.
This should go to the mainline through your tree that's why please
remove it from this series.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng),
Commit 164d98466103a46b7c881149e92ec2a28a6375be breaks
board with SATA support, because sata is not compiled.
Signed-off-by: Stefano Babic sba...@denx.de
---
arch/arm/imx-common/Makefile |2 +-
arch/arm/imx-common/sata.c |1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git
On 12/18/2013 08:07 PM, Jagan Teki wrote:
On Wed, Dec 18, 2013 at 9:07 PM, Marek Vasut ma...@denx.de wrote:
On Wednesday, December 18, 2013 at 04:30:08 PM, Jagannadha Sutradharudu Teki
wrote:
Added support for Zynq Nand controller driver.
Signed-off-by: Jagannadha Sutradharudu Teki
Hi Otavio,
one minor point.
On 16/12/2013 23:43, Otavio Salvador wrote:
+int board_video_skip(void)
+{
+ int i;
+ int ret;
+ int detected = 0;
+ char const *panel = getenv(panel);
+ if (!panel) {
+ for (i = 0; i ARRAY_SIZE(displays); i++) {
+
Hi Otavio,
On 16/12/2013 23:44, Otavio Salvador wrote:
The macro allows easy setting in per-pin, as for example:
,
| imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION);
`
The IOMUX_CONFIG_SION allows for reading PAD value from PSR register.
The following quote
Hello Hyungwon,
On 12/19/2013 06:40 AM, 황형원 wrote:
Hi, Marczak.
Is this logo image what I sent you before?
It's a little different what we use,
and also the logo image is not aligned center horizontally.
Best regards,
Hyungwon Hwang
This is not a logo which you sent me. Your logo
On 16/12/2013 23:44, Otavio Salvador wrote:
Using 512k for fdt partition allow it to be aligned with the other
small partitions and 512k erase block size.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
Changes in v3: None
Changes in v2: None
include/configs/mx28evk.h | 2 +-
CC Fabio:
On 16/12/2013 23:44, Otavio Salvador wrote:
This reads the kernel, ftd and boot into ubifs filesystem. While on
that, the SD firmware filename definition has been moved next to the
other SD related commands.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
Changes in
Hi Otavio,
On 16/12/2013 23:44, Otavio Salvador wrote:
This patch fixes allow for the DeviceTree and initrd relocation fixing
the boot of FSL 3.10.9-1.0.0-alpha kernel.
This changes following boards:
- mx6sabreauto
- mx6sabresd
- wandboard
- udoo
- nitrogen6x
- cgtqmx6eval
Hi Otavio,
On 16/12/2013 23:44, Otavio Salvador wrote:
The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.
Signed-off-by: Otavio
On Mon, Dec 16, 2013 at 8:44 PM, Otavio Salvador
ota...@ossystems.com.br wrote:
This reads the kernel, ftd and boot into ubifs filesystem. While on
that, the SD firmware filename definition has been moved next to the
other SD related commands.
Signed-off-by: Otavio Salvador
On Thursday 19 December 2013 02:50 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 2:28 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Thursday 19 December 2013 02:21 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 2:17 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Thursday 19 December 2013
Hi,
I needed to be able to uncompress lzma files. I did this command
based on unzip command and propose it if it could help. Hopping the
patch is correctly done...
Best regards.
Patrice
Signed-off-by: Patrice Bouchand pbfwdlist_gmail_com
---
common/Makefile | 3 +++
when creating the hashtable, for each environmentvariable
getenv(ENV_CALLBACK_VAR) and getenv(ENV_FLAGS_VAR) is called,
which costs at this point a lot of time. So call this two
getenv() calls only once.
Boottime on the ids8313 board without this patch:
2013-12-19 13:38:22,894: NAND: 128 MiB
Tom
On 12/18/2013 02:07 PM, Tom Rini wrote:
Hey,
The following changes since commit d2c7074b9593d822e2359a09c21747248fdf5fac:
ARM: OMAP5: clocks: Update MPU settings for OPP_NOM (2013-12-12 17:43:39
-0500)
are available in the git repository at:
git://git.denx.de/u-boot-ti.git
On Wed, Dec 18, 2013 at 14:05 -0600, Chin Liang See wrote:
To add the Cadence SPI driver support for Altera SOCFPGA. It
required information such as clocks and timing from platform's
configuration header file within include/configs folder
Signed-off-by: Chin Liang See cl...@altera.com
Cc:
This patch add uuid disk to defualt partions necessary to
restore gpt partitions and fixes mmcdev environmental variable.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
include/configs/trats2.h |3 ++-
1 file changed, 2
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 12/19/2013 08:14 AM, Dan Murphy wrote:
Tom
On 12/18/2013 02:07 PM, Tom Rini wrote:
Hey,
The following changes since commit d2c7074b9593d822e2359a09c21747248fdf5fac:
ARM: OMAP5: clocks: Update MPU settings for OPP_NOM (2013-12-12
On Sat, Dec 14, 2013 at 9:17 AM, feng...@phytium.com.cn wrote:
From: David Feng feng...@phytium.com.cn
Signed-off-by: David Feng feng...@phytium.com.cn
---
common/cmd_pxe.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_pxe.c
Hi Gerhard,
On Thu, 2013-12-19 at 14:50 +0100, Gerhard Sittig wrote:
On Wed, Dec 18, 2013 at 14:05 -0600, Chin Liang See wrote:
To add the Cadence SPI driver support for Altera SOCFPGA. It
required information such as clocks and timing from platform's
configuration header file within
This patch introduces an alternative method for resetting HSIC-attached USB
devices on OMAP4/5, needed for working around the fail to connect with some
types. The solution implemented by Dan Murphy for the OMAP5432 uEVM (reset via
a callback in the board file, invoked from within usb_hub.c) does
Add option for individual reset of HSIC-connected USB devices by the
ehci-hcd.c driver upon applying port power, with per-device configurable
reset hold and delay times. This may replace the reset functionality via
usb_hub.c and board file (which does not work on some boards).
Make HSIC work on
This patch demonstrates the usage of the alternative method for HSIC
devices reset (via the ehci-hcd and omap-ehci drivers, where this
method is implemented through a separate patch; must be applied prior
to this one). Board functionality is not altered; a minor improvement
is the removal of the
All prerequisites are already available, so why not enable 8-bit
access - it is a matter of a define in the board file only.
Signed-off-by: Lubomir Popov l-po...@ti.com
---
include/configs/omap5_uevm.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/omap5_uevm.h
Dear Minkyu Kang,
-Original Message-
From: Piotr Wilczek [mailto:p.wilc...@samsung.com]
Sent: Wednesday, December 18, 2013 3:44 PM
To: u-boot@lists.denx.de
Cc: Minkyu Kang; Kyungmin Park; Piotr Wilczek; Lukasz Majewski
Subject: [PATCH] board:trats1:trats2: fix adapter number
This
Add option for individual reset of HSIC-connected USB devices by the
ehci-hcd.c driver upon applying port power, with per-device configurable
reset hold and delay times. This may replace the reset functionality via
usb_hub.c and board file (which does not work on some boards).
Make HSIC work on
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Masahiro Yamada yamad...@jp.panasonic.com
---
drivers/mtd/spi/Makefile | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 26483a2..fd8f8a4
Thanks for your patch.
Please see the typical driver code suggestions on below thread.
http://u-boot.10912.n7.nabble.com/Suggestions-for-SPI-driver-pusher-td161008.html
Try to avoid the header files make sure to code everything in single .c file.
Also add some documents as well as test log on
Add option for individual reset of HSIC-connected USB devices by the
ehci-hcd.c driver upon applying port power, with per-device configurable
reset hold and delay times. This may replace the reset functionality via
usb_hub.c and board file (which does not work on some boards).
Make HSIC work on
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 12/19/2013 10:57 AM, Jagannadha Sutradharudu Teki wrote:
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Masahiro Yamada yamad...@jp.panasonic.com
---
drivers/mtd/spi/Makefile | 11 +--
1 file changed, 9
Hi Jagan,
On Thu, 2013-12-19 at 21:39 +0530, Jagan Teki wrote:
Thanks for your patch.
Please see the typical driver code suggestions on below thread.
http://u-boot.10912.n7.nabble.com/Suggestions-for-SPI-driver-pusher-td161008.html
Try to avoid the header files make sure to code
Hi Masahiro,
On 19 December 2013 00:19, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Hello Simon
Since buildman does incremental builds by default, if nothing changes
in the the build, that Makefile rule may not be invoked. It is
possible that commits 03 to 15 don't update anything
On Wed, Dec 18, 2013 at 03:07:47PM -0500, Tom Rini wrote:
On Tue, Dec 10, 2013 at 03:02:10PM +0530, Lokesh Vutla wrote:
This Patch series updates support for AM4372 EPOS and GP EVM boards.
AM4372 is a low cost Cortex-A9 based application processor targeted at
existing
ARM9/ARM11 base
Hey,
The following changes since commit d627eefcd5e72db00889718ca9ee1dcb4d026fc9:
Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'
(2013-12-18 22:19:02 +0100)
are available in the git repository at:
git://git.denx.de/u-boot-ti.git master
for you to fetch changes
On Thu, Dec 19, 2013 at 10:06 PM, Tom Rini tr...@ti.com wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 12/19/2013 10:57 AM, Jagannadha Sutradharudu Teki wrote:
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Masahiro Yamada yamad...@jp.panasonic.com
---
Hi Masahiro,
On 28 November 2013 17:37, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Hello Simon.
Add a simple LCD driver which uses SDL to display the image. We update the
image regularly, while still providing for reasonable performance.
Adjust the common lcd code to support sandbox.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 12/19/2013 12:26 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 10:06 PM, Tom Rini tr...@ti.com wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 12/19/2013 10:57 AM, Jagannadha Sutradharudu Teki wrote:
Signed-off-by: Jagannadha
On Mon, Dec 16, 2013 at 03:27:23PM +0800, Bo Shen wrote:
Fix the typo error for mrproper from mkproper.
Signed-off-by: Bo Shen voice.s...@atmel.com
Acked-by: Simon Glass s...@chromium.org
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
On Wed, Dec 18, 2013 at 07:54:24PM +0100, Marek Vasut wrote:
The following changes since commit f3bf212abc4139f12b472e97c1992ab32671b609:
serial_sh: add support for SH7753 (2013-12-18 16:50:00 +0900)
are available in the git repository at:
git://git.denx.de/u-boot-usb.git master
On Wed, Dec 18, 2013 at 07:00:51PM +0900, Masahiro Yamada wrote:
Before this commit, a broken pipe error sometimes happened
when building lcd4_lwmon5 board with Buildman.
This commit re-writes build rules of
u-boot.spr and u-boot-img-spl-at-end.bin
more simply without using a pipe.
On Wed, Dec 18, 2013 at 05:10:00PM -0600, Scott Wood wrote:
Note that as discussed at http://patchwork.ozlabs.org/patch/296730/
the cosmetic patch is fixing a significant readability regression --
the current indentation is misleading as to the code flow.
The following changes since commit
On Thu, Dec 19, 2013 at 11:09 PM, Tom Rini tr...@ti.com wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 12/19/2013 12:26 PM, Jagan Teki wrote:
On Thu, Dec 19, 2013 at 10:06 PM, Tom Rini tr...@ti.com wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 12/19/2013 10:57 AM,
On Thursday 19 December 2013 10:30 PM, Tom Rini wrote:
On Wed, Dec 18, 2013 at 03:07:47PM -0500, Tom Rini wrote:
On Tue, Dec 10, 2013 at 03:02:10PM +0530, Lokesh Vutla wrote:
This Patch series updates support for AM4372 EPOS and GP EVM boards.
AM4372 is a low cost Cortex-A9 based application
Cleanup on memory configuration options:
- Add comment
- Re-order configs
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq.h | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git
Enabled fit_format_{error,warning}()
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 82ec826..6019c4a 100644
---
This enabled Boot FreeBSD/vxWorks from an ELF image support
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index
Changed Env. Sector size from 0x1 to 128Kb
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq-common.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
This patch provides a basic fdt support for zynq u-boot.
zynq-7000.dtsi- initial arch dts file
zynq-zed.dts - initial zed board dts file
more devices should be added in subsequent patches.
u-boot build: once configuring of a board done
for building dtb with zynq-zed.dts as an input
zynq-uboot
MicroZed is a low-cost development board based on
the Xilinx Zynq-7000 All Programmable SoC.
APSOC:
- XC7Z010-1CLG400C
Memory:
- 1 GB of DDR3 SDRAM
- 128Mb of QSPI flash(S25FL128SAGBHI200)
- Micro SD card interface
Communication:
- 10/100/1000 Ethernet
- USB 2.0
- USB-UART
User I/O:
- 100 User
ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013
ZC770 XM010:
- 1Gb DDR3
- 1Mb SST SPI flash
- 128 Mb Quad-SPI Flash
- 8 Mb SST SI flash
- Full size
These changes are from u-boot-xlnx.git repo from git.xilinx.com
This repo is well tested on xilinx zynq platform, hence pushing
the same on upstream.
Excluded qspi and nand changes from previous series.
--
Thanks,
Jagan.
Jagannadha Sutradharudu Teki (29):
zynq: Enable CONFIG_FIT_VERBOSE
Defined default env. for autoboot FIT image from
respective boot devices.
Default settings:
fit_image=fit.itb
load_addr=0x200
fit_size=0x80
flash_off=0x10
nor_flash_off=0xE210
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
Zynq uart controller support two serial ports like
CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
enabled both so-that the respective board will define
these macros based on their usage.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
CONFIG_FIT_SIGNATURE - signature node support in FIT image
CONFIG_RSA - RSA lib support
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq-common.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs/zynq-common.h
Updated doc/README.zynq to current status.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: Updated acc to current status
V2: none
doc/README.zynq | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/doc/README.zynq
GPIO dummy routines are required for fdt build, may be removed
these dependencies once the u-boot fdt is fully optimized.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
arch/arm/include/asm/arch-zynq/gpio.h | 25 +
1 file changed, 25
Zynq ethernet controller support two GEM's like
CONFIG_ZYNQ_GEM0 and CONFIG_ZYNQ_GEM1 enabled
both so-that the respective board will define
these macros based on their usage.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq.h | 16
- Enable cache command
- Turn-off L2 cache
- Turn-on D-cache
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index
CONFIG_SYS_SDRAM_SIZE is specific to a board hence moved
to specific pre-config board files.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq-common.h | 1 -
include/configs/zynq_zc70x.h | 2 ++
include/configs/zynq_zed.h| 2 ++
3
Defined TEXT_BASE for u-boot starts from 0x400
w.r.t zynq memory-map.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq-common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/zynq-common.h
Defined CONFIG_ENV_OVERWRITE, which allow to
overwrite serial baudrate and ethaddr.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq-common.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/configs/zynq-common.h
Information on zynq u-boot about
- zynq boards
- mainline status
- TODO
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
doc/README.zynq | 60 +
1 file changed, 60 insertions(+)
create mode 100644
The Zynq-7000 APSOC zc702 and zc706 enabled complte embedded
processing includes ASIC and FPGA design.
ZC702-:
APSOC:
- XC7Z020-CLG484-1
Memory:
- DDR3 Component Memory 1GB
- 16MB Quad SPI Flash
- IIC - 1 KB EEPROM
Connectivity:
- Gigabit Ethernet GMII, RGMII and SGMII.
- USB OTG - Host USB
-
Zed is a complete development board based on the
Xilinx Zynq-7000 All Programmable SoC.
APSOC:
- XC7Z020-CLG484-1
Memory:
- 512 MB DDR3
- 256 Mb Quad-SPI Flash(
- Full size SD/MMC card cage
Connectivity:
- 10/100/1000 Ethernet
- USB OTG (Device/Host/OTG)
- USB-UART
Expansion:
- FMC (Low Pin
Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.
Added this functionality on board_late_init as it's not
needed for normal initializtion part.
Signed-off-by: Jagannadha Sutradharudu Teki
This patch adds initial dts support for supported
zynq boards.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: Removed zynq-zc770-xm011.dts file
V2: none
board/xilinx/dts/zynq-microzed.dts| 14 ++
board/xilinx/dts/zynq-zc702.dts | 14 ++
ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013
ZC770 XM013:
- 1GB DDR3
- 128 Mb Quad-SPI Flash(dual parallel)
- USB-UART
Signed-off-by: Jagannadha
zynq.h - zynq-common.h, zynq-common is Common
configuration options for all Zynq boards.
zynq.h is no longer exists hense removed from boards.cfg
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
boards.cfg| 2 --
Adds configurations for Catalyst 24WC08 EEPROM, which
is present on the zynq boards.
Enable EEPROM support for zc70x boards.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq-common.h | 10 ++
include/configs/zynq_zc70x.h | 1 +
Last 128Kb sector of 1Mb flash is defined as u-boot
environment partition.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq-common.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git
ZC770 is a complete development board based on the Xilinx Zynq-7000
All Programmable SoC, similar to ZC70x board but which has four
different daughter cards, like XM010, XM011, XM012 and XM013
ZC770 XM012:
- 1GB DDR3
- 64MiB Numonyx NOR flash
- USB-UART
Signed-off-by: Jagannadha Sutradharudu
Cleanups mostly on:
- Add comments
- Re-order configs
- Remove #define CONFIG_ZYNQ_SDHCI
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: none
include/configs/zynq.h | 76 ++
1 file changed, 39 insertions(+), 37
Hi Tom,
Small PR - addons on one spi driver, others and few fixes.
Thanks,
Jagan.
The following changes since commit f3bf212abc4139f12b472e97c1992ab32671b609:
serial_sh: add support for SH7753 (2013-12-18 16:50:00 +0900)
are available in the git repository at:
Hi Tom and Albert,
Can you look into this series.
On Thu, Dec 19, 2013 at 11:38 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
These changes are from u-boot-xlnx.git repo from git.xilinx.com
This repo is well tested on xilinx zynq platform, hence pushing
the
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.
NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would
Hi Kuo-Jung Su,
Please check this v7 and try to add the test log if you have.
On Fri, Dec 20, 2013 at 12:34 AM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTSSP010 is a multi-function controller
which
Cleanup on miscellaneous configurable options:
- Rename SYS_PROMPT as zynq-uboot
- Add comment
- Re-order configs
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
V3: none
V2: Removed CONFIG_SYS_PROMPT_HUSH_PS2
include/configs/zynq.h | 19 ++-
1 file changed,
Dear Ben Collins,
In message 293c5061-60b5-458b-b586-d66b0ed36...@servergy.com you wrote:
(Note, I am not subscribed to the list, so please make sure to keep me
in Cc)
No, please subscribe if you plan to submit patches.
I am working on a p4080 based system (Freescale 32-bit Power). In
On Thu, Dec 19, 2013 at 08:46 -0600, Chin Liang See wrote:
Hi Gerhard,
On Thu, 2013-12-19 at 14:50 +0100, Gerhard Sittig wrote:
On Wed, Dec 18, 2013 at 14:05 -0600, Chin Liang See wrote:
To add the Cadence SPI driver support for Altera SOCFPGA. It
required information such as
On Thu, Dec 19, 2013 at 18:26 +0200, Lubomir Popov wrote:
---
V1 and V2 got garbled during transmission. V3 is just a resend (again).
Just a hint: The problem is with your MUA, sticking with it just
repeats the mangling (it's a builtin feature). Consider using
'git send-email' for patch
On 12 November 2013 05:27, Ajay Kumar ajaykumar...@samsung.com wrote:
RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
arch/arm/cpu/armv7/exynos/clock_init.h | 3 +++
On 12 November 2013 05:27, Ajay Kumar ajaykumar...@samsung.com wrote:
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on
On 12 November 2013 05:27, Ajay Kumar ajaykumar...@samsung.com wrote:
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
Hi Ajay,
On 12 November 2013 05:27, Ajay Kumar ajaykumar...@samsung.com wrote:
On Exynos5420 and newer versions, the FIMD sysmmus are in
on state by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables
Hi Ajay,
On 12 November 2013 05:27, Ajay Kumar ajaykumar...@samsung.com wrote:
Add callbacks to set up DP-HPD, backlight and LCD power
on SMDK5420.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
board/samsung/smdk5420/smdk5420.c | 102
+++---
1
Hi Ajay,
On 12 November 2013 05:27, Ajay Kumar ajaykumar...@samsung.com wrote:
Enabling VDD_28IO_DP via LDO38 for SMDK5420.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
board/samsung/common/board.c | 3 +++
include/power/s2mps11_pmic.h | 3 +++
2 files changed, 6 insertions(+)
On 12 November 2013 05:27, Ajay Kumar ajaykumar...@samsung.com wrote:
Enable FIMD and DP drivers on SMDK5420 so that we get to
see the LCD console on eDP panel.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
include/configs/smdk5420.h | 8
Hi Gerhard,
On Thu, 2013-12-19 at 21:03 +0100, Gerhard Sittig wrote:
On Thu, Dec 19, 2013 at 08:46 -0600, Chin Liang See wrote:
Hi Gerhard,
On Thu, 2013-12-19 at 14:50 +0100, Gerhard Sittig wrote:
On Wed, Dec 18, 2013 at 14:05 -0600, Chin Liang See wrote:
To add the Cadence
On 16 December 2013 01:42, Rajeshwari S Shinde rajeshwar...@samsung.com wrote:
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.
exynos_init function is provided for platform specific code.
Signed-off-by: Rajeshwari S Shinde
On 16 December 2013 01:42, Rajeshwari S Shinde rajeshwar...@samsung.com wrote:
Add structure for power register for Exynos5420
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
___
U-Boot mailing list
On 16 December 2013 01:42, Rajeshwari S Shinde rajeshwar...@samsung.com wrote:
Add dmc and phy_control register structure for 5420.
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
___
U-Boot mailing
On 16 December 2013 01:42, Rajeshwari S Shinde rajeshwar...@samsung.com wrote:
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Signed-off-by: Akshay Saraswat
Hi Rajeshwari,
On 16 December 2013 01:42, Rajeshwari S Shinde rajeshwar...@samsung.com wrote:
This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
---
Changes in V2:
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