[U-Boot] Policy for porting drivers from Linux
Hi List, This has probably come up before but I did a quick search and couldn't find anything. If it exists please point me at it. So at $dayjob we're looking at adding support for the BCM5718 Ethernet chipset to u-boot. We've actually got things working and I'm looking at preparing the code for submission. Naturally I'm getting a bunch of checkpatch errors that I need to work through. And I wonder how this type of porting _should_ be done? Some of the checkpatch errors things that exist in the upstream kernel. Others are because of subtle differences in the internal apis between linux an u-boot. For example pci_read_config_word() under u-boot takes a pci_dev_t (usually these are declared deviceno) as it's first argument while under linux it takes a struct pci_dev* (usually called pdev). Because of the difference in naming there are a bunch of lines 80 chars. Obviously I could fix this by changing deviceno to pdev but I actually think that'd be more confusing. Then there's also code that won't be used under u-boot (e.g. firmware loading, smp, locking). Some of this we've deleted other parts we've #if 0'd out. This is mostly because 2 poeple were doing the work and made arbitrary choices. I personally think the latter is better because it makes taking fixes from Linux easier but is that something we actually should care about? I think I've seen one instance on this mailing list of taking the Linux code verbatim as patch 1/2 then the porting/cleanup as patch 2/2. This seems like a good idea but it may still lose the ability to take fixes. Any comments/suggestions? Thanks, Chris ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 1/2] usb: dfu: add config option to use in dfu mode fullspeed only
Hello Bin Liu, Am 09.09.2014 16:42, schrieb Bin Liu: Heiko, On 09/09/2014 09:37 AM, Heiko Schocher wrote: Hello Bin Liu, Am 09.09.2014 16:09, schrieb Bin Liu: Heiko, On 09/09/2014 07:37 AM, Heiko Schocher wrote: add the new config option CONFIG_DFU_FULLSPEED. With this option enabled, DFU uses fullspeed only. Can we not introduce the new config option but check the gadget driver speed in runtime as what the ether gadget driver does? I don't want two config options (CONFIG_USB_GADGET_DUALSPEED and CONFIG_DFU_FULLSPEED) to control one feature, as in your patch 2/2. Hmm.. I am not sure, if I understand you correct. I could use CONFIG_USB_GADGET_DUALSPEED instead the new config option for setting config-fullspeed = 1; in g_dnl_config_register() If you mean this, yes, thats would be a good change... No, I did not mean this build time macro, but was thinking you can check g-speed at the same place in runtime. I think you can refer to ether.c, which supports full-speed but does not use any macro. Yep, you are right, I can get rid completely of this new define! The speed selection is done in drivers/usb/gadget/composite.c I removed it, do some tests, and send a v2. Thanks! bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] arm: am335x: siemens board use in DFU mode fullspeed only
Siemens boards are now using DFU in fullspeed only. For this CONFIG_USB_GADGET_DUALSPEED is undefined. Signed-off-by: Heiko Schocher h...@denx.de Cc: Tom Rini tr...@ti.com Cc: Lukasz Majewski l.majew...@samsung.com Cc: Marek Vasut ma...@denx.de Cc: Liu Bin b-...@ti.com Cc: Lukas Stockmann lukas.stockm...@siemens.com --- On the siemens board this is needed because of a protection circuit. The device is 24V AC powered, if someone uses a non galvanically isolated transformer and misswires it, it could burn down the USB host. That's why we have a protection on the USB side which limits the speed to 12Mbit/sec. - changes for v2: - get rid of config option CONFIG_DFU_FULLSPEED as Bin Liu suggested. --- include/configs/siemens-am33x-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index b8fb77e..4dcd690 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -233,7 +233,7 @@ #define CONFIG_MUSB_GADGET #define CONFIG_MUSB_PIO_ONLY #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT -#define CONFIG_USB_GADGET_DUALSPEED +#undef CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW2 #define CONFIG_MUSB_HOST -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] usb: dfu: add fullspeed support for DFU
DFU now can use also fullspeed.
Signed-off-by: Heiko Schocher h...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Liu Bin b-...@ti.com
Cc: Lukas Stockmann lukas.stockm...@siemens.com
---
- changes for v2:
- get rid of config option CONFIG_DFU_FULLSPEED as Bin Liu
suggested.
---
drivers/usb/gadget/f_dfu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 1145aab..dfa9f3b 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -238,6 +238,7 @@ static inline void to_dfu_mode(struct f_dfu *f_dfu)
{
f_dfu-usb_function.strings = dfu_strings;
f_dfu-usb_function.hs_descriptors = f_dfu-function;
+ f_dfu-usb_function.descriptors = f_dfu-function;
f_dfu-dfu_state = DFU_STATE_dfuIDLE;
}
@@ -245,6 +246,7 @@ static inline void to_runtime_mode(struct f_dfu *f_dfu)
{
f_dfu-usb_function.strings = NULL;
f_dfu-usb_function.hs_descriptors = dfu_runtime_descs;
+ f_dfu-usb_function.descriptors = dfu_runtime_descs;
}
static int handle_upload(struct usb_request *req, u16 len)
@@ -809,6 +811,7 @@ static int dfu_bind_config(struct usb_configuration *c)
return -ENOMEM;
f_dfu-usb_function.name = dfu;
f_dfu-usb_function.hs_descriptors = dfu_runtime_descs;
+ f_dfu-usb_function.descriptors = dfu_runtime_descs;
f_dfu-usb_function.bind = dfu_bind;
f_dfu-usb_function.unbind = dfu_unbind;
f_dfu-usb_function.set_alt = dfu_set_alt;
--
1.8.3.1
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[U-Boot] [PATCH v2 0/2] usb: dfu: am335x: allow dfu in fullspeed mode only
This patchserie allows fullspeed for DFU, and configures the siemens boards to use fullspeed only. - changes for v2: - get rid of config option CONFIG_DFU_FULLSPEED as Bin Liu suggested. Cc: Tom Rini tr...@ti.com Cc: Lukasz Majewski l.majew...@samsung.com Cc: Marek Vasut ma...@denx.de Cc: Liu Bin b-...@ti.com Cc: Lukas Stockmann lukas.stockm...@siemens.com Heiko Schocher (2): usb: dfu: add fullspeed support for DFU arm: am335x: siemens board use in DFU mode fullspeed only drivers/usb/gadget/f_dfu.c | 3 +++ include/configs/siemens-am33x-common.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arch/arm: Add individual TLB size support.
Hi Albert, Subject: Re: [PATCH] arch/arm: Add individual TLB size support. Hi Xiubo, On Mon, 7 Jul 2014 13:19:11 +0800, Xiubo Li li.xi...@freescale.com wrote: This adds CONFIG_TLB_SIZE for individual board, whose TLB size maybe larger than PGTABLE_SIZE. Signed-off-by: Xiubo Li li.xi...@freescale.com --- arch/arm/lib/board.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index dc34190..b7327ce 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -353,7 +353,11 @@ void board_init_f(ulong bootflag) #if !(defined(CONFIG_SYS_ICACHE_OFF) defined(CONFIG_SYS_DCACHE_OFF)) /* reserve TLB table */ +#ifdef CONFIG_TLB_SIZE + gd-arch.tlb_size = CONFIG_TLB_SIZE; +#else gd-arch.tlb_size = PGTABLE_SIZE; +#endif addr -= gd-arch.tlb_size; /* round down to next 64 kB limit */ There is no code in current mainline which defines CONFIG_TLB_SIZE; that makes the patch a dead code addition. Yes, this will be used by our LS1 SoC first, and it is still doing The upstream. Besides, what's the point of this as opposed to, e.g., just defining the right PGTABLE_SIZE, or renaming PGTABLE_SIZE as CONFIG_TLB_SIZE? We'll add the LPAE support in uboot and need more space for tlb. Thanks very much, BRs Xiubo ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 0/2] usb: dfu: am335x: allow dfu in fullspeed mode only
Hi all -Ursprüngliche Nachricht- Von: Heiko Schocher [mailto:h...@denx.de] Gesendet: Dienstag, 9. September 2014 16:22 An: Lukasz Majewski Cc: u-boot@lists.denx.de; Tom Rini; Marek Vasut; Liu Bin; Stockmann, Lukas Betreff: Re: [PATCH v1 0/2] usb: dfu: am335x: allow dfu in fullspeed mode only Hello Lukasz, Am 09.09.2014 15:43, schrieb Lukasz Majewski: Hi Heiko, This patchserie adds the new config option CONFIG_DFU_FULLSPEED. Is there any special reason to support Full Speed (12 Mbit/sec - USB 1.1) and not rely solely on the High Speed (USB 2.0) as we do now? If this is enabled DFU uses fullspeed only. This is used on the siemens boards. Is there any DFU problem with the mentioned Siemens board, that we must use USB 1.1? I'd also appreciate more verbose rationale for this patch series - why this change is needed? What is the expected improvement? They have a USB HW protection circuit and therefore they only allowed to use fullspeed ... @Lukas Stockman: Maybe you could answer this better than me? Yes, it's because of a protection circuit. Our device is 24V AC powered, if someone uses a non galvanically isolated transformer and misswires it, it could burn down the USB host. That's why we have a protection on the USB side which limits the speed to 12Mbit/sec. Regards, Lukas ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] QSPI: Enable QSPI AHB read for MX6SX
From: Peng Fan van.free...@gmail.com
There are two different ways to read out the data from the flash:
the IP Command Read and the AHB Command Read.
The IC guy suggests we use the AHB Command Read which is faster
then the IP Command Read. (What's more is that there is a bug in
the IP Command Read in the Vybrid.)
After we set up the registers for the AHB Command Read, we can use
the memcpy to read the data directly. A missed access to the buffer
causes the controller to clear the buffer, and use the sequence pointed
by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
Signed-off-by: Peng Fan van.free...@gmail.com
---
drivers/spi/fsl_qspi.c | 81 ++
drivers/spi/fsl_qspi.h | 11 +++
2 files changed, 92 insertions(+)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index b1d75e7..95b36f0 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -215,6 +215,52 @@ void spi_init()
/* do nothing */
}
+#ifdef CONFIG_MX6SX
+static void qspi_ahb_read(struct fsl_qspi *qspi, u8 *rxbuf, u32 len)
+{
+ struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
+ u32 mcr_reg;
+ u32 to_or_from;
+
+ to_or_from = qspi-sf_addr + qspi-amba_base;
+
+ mcr_reg = qspi_read32(regs-mcr);
+ qspi_write32(regs-mcr, QSPI_MCR_CLR_RXF_MASK |
+QSPI_MCR_CLR_TXF_MASK | QSPI_MCR_RESERVED_MASK |
+QSPI_MCR_END_CFD_LE_64);
+
+ /* Read out the data directly from the AHB buffer.*/
+ memcpy(rxbuf, (u8 *)to_or_from, len);
+
+ qspi_write32(regs-mcr, mcr_reg);
+}
+
+/*
+ * If we have changed the content of the flash by writing or erasing,
+ * we need to invalidate the AHB buffer. If we do not do so, we may read out
+ * the wrong data. The spec tells us reset the AHB domain and Serial Flash
+ * domain at the same time.
+ */
+static inline void qspi_invalid_buf(struct fsl_qspi *qspi)
+{
+ struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
+ u32 mcr_reg;
+
+ mcr_reg = qspi_read32(regs-mcr);
+ mcr_reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
+ qspi_write32(regs-mcr, mcr_reg);
+
+ /*
+* The minimum delay : 1 AHB + 2 SFCK clocks.
+* Delay 1 us is enough.
+*/
+ udelay(1);
+
+ mcr_reg = ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
+ qspi_write32(regs-mcr, mcr_reg);
+}
+#endif
+
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
@@ -266,9 +312,30 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
smpr_val = qspi_read32(regs-smpr);
smpr_val = ~QSPI_SMPR_DDRSMP_MASK;
qspi_write32(regs-smpr, smpr_val);
+
+#ifdef CONFIG_MX6SX
+ qspi_write32(regs-mcr, QSPI_MCR_RESERVED_MASK |
+QSPI_MCR_END_CFD_LE QSPI_MCR_END_CFD_SHIFT);
+#else
qspi_write32(regs-mcr, QSPI_MCR_RESERVED_MASK);
+#endif
+#ifdef CONFIG_MX6SX
+ /* AHB configuration for access buffer 0/1/2 */
+ qspi_write32(regs-buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
+ qspi_write32(regs-buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
+ qspi_write32(regs-buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
+ qspi_write32(regs-buf3cr, QSPI_BUF3CR_ALLMST_MASK |
+(0x80 QSPI_BUF3CR_ADATSZ_SHIFT));
+
+ qspi_write32(regs-buf0ind, 0);
+ qspi_write32(regs-buf1ind, 0);
+ qspi_write32(regs-buf2ind, 0);
+
+ seq_id = SEQID_FAST_READ;
+#else
seq_id = 0;
+#endif
reg_val = qspi_read32(regs-bfgencr);
reg_val = ~QSPI_BFGENCR_SEQID_MASK;
reg_val |= (seq_id QSPI_BFGENCR_SEQID_SHIFT);
@@ -324,6 +391,7 @@ static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf,
u32 len)
qspi_write32(regs-mcr, mcr_reg);
}
+#ifndef CONFIG_MX6SX
static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
{
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
@@ -367,6 +435,7 @@ static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf,
u32 len)
qspi_write32(regs-mcr, mcr_reg);
}
+#endif
static void qspi_op_wrr(struct fsl_qspi *qspi, u8 *txbuf, u32 len)
{
@@ -470,6 +539,10 @@ static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf,
u32 len)
;
qspi_write32(regs-mcr, mcr_reg);
+
+#ifdef CONFIG_MX6SX
+ qspi_invalid_buf(qspi);
+#endif
}
static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf)
@@ -529,6 +602,10 @@ static void qspi_op_se(struct fsl_qspi *qspi)
;
qspi_write32(regs-mcr, mcr_reg);
+
+#ifdef CONFIG_MX6SX
+ qspi_invalid_buf(qspi);
+#endif
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
@@ -567,7 +644,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
if (din) {
if (qspi-cur_seqid == OPCODE_FAST_READ)
+#ifdef CONFIG_MX6SX
[U-Boot] [PATCH 0/3] Add QSPI support for mx6sxsabresd board
From: Peng Fan van.free...@gmail.com This patch set is to support QSPI for mx6sxsabresd board. And register read/write is implmented. AHB read is also supported to improve flash read performance. All the three patches have been tested on mx6sxsabresd board. Peng Fan (3): ARM:MX6SX Add QuadSPI support for mx6sxsabresd QSPI: Enable write device registers QSPI: Enable QSPI AHB read for MX6SX arch/arm/cpu/armv7/mx6/clock.c | 50 arch/arm/include/asm/arch-mx6/clock.h | 3 + board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 ++ drivers/spi/fsl_qspi.c | 188 +++- drivers/spi/fsl_qspi.h | 11 ++ include/configs/mx6sxsabresd.h | 14 +++ 6 files changed, 303 insertions(+), 3 deletions(-) -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/BSC9131RDB: add mtdparts suppport
Use mtdparts to create partitions dynamically rather than using static partitions in device tree Signed-off-by: Ashish Kumar ashish.ku...@freescale.com --- include/configs/BSC9131RDB.h | 15 +++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 56a3e94..5c7b64e 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -393,6 +393,21 @@ extern unsigned long get_sdram_size(void); #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT nand0=ff80.flash, \ + spi0=SPIFLASH0 +#define MTDPARTS_DEFAULT mtdparts=ff80.flash:3m(uboot), \ + 8m(kernel),1m(dtb),-(user);SPIFLASH0: \ + 1m(uboot),4m(kernel),512k(dtb),11m(fs),-(user) +#endif + +/* * Environment Configuration */ -- 1.7.6.GIT ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] ARM:MX6SX Add QuadSPI support for mx6sxsabresd
From: Peng Fan van.free...@gmail.com
Add QuadSPI support for mx6sxsabresd board.
There are two 16MB S25FL128S flashes on board. They are connected to
QSPI2 interface. i.MX6SX supports two QuadSPI interfaces, QSPI1/2.
The two flash devices are connected to A1/B1 of QSPI2.
Signed-off-by: Peng Fan van.free...@gmail.com
---
arch/arm/cpu/armv7/mx6/clock.c | 50 +
arch/arm/include/asm/arch-mx6/clock.h | 3 ++
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +++
drivers/spi/fsl_qspi.c | 30 +
include/configs/mx6sxsabresd.h | 14
5 files changed, 137 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 820b8d5..8caa61d 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -340,6 +340,56 @@ static u32 get_mmdc_ch0_clk(void)
}
#endif
+#ifdef CONFIG_MX6SX
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+ u32 reg = 0;
+ /* Enable QuadSPI clock */
+ switch (qspi_num) {
+ case 0:
+ /* disable the clock gate */
+ clrbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(imx_ccm-cscmr1);
+ reg = ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+ reg |= ((1 MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+ (2 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+ writel(reg, imx_ccm-cscmr1);
+
+ /* enable the clock gate */
+ setbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+ break;
+ case 1:
+ /*
+* disable the clock gate
+* QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+* disable both of them.
+*/
+ clrbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(imx_ccm-cs2cdr);
+ reg = ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+ reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+ writel(reg, imx_ccm-cs2cdr);
+
+ /*enable the clock gate*/
+ setbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+ break;
+ default:
+ break;
+ }
+}
+#endif
+
#ifdef CONFIG_FEC_MXC
int enable_fec_anatop_clock(enum enet_freq freq)
{
diff --git a/arch/arm/include/asm/arch-mx6/clock.h
b/arch/arm/include/asm/arch-mx6/clock.h
index 339c789..9d0ba7a 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -60,4 +60,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
+#ifdef CONFIG_MX6SX
+void enable_qspi_clk(int qspi_num);
+#endif
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 5eaec1b..f9cad5a 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
}
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+ MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA07__QSPI2_A_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
[U-Boot] [PATCH] powerpc/BSC9132qds: add mtdparts suppport
Use mtdparts to create partitions dynamically rather than using static partitions in device tree Signed-off-by: Ashish Kumar ashish.ku...@freescale.com --- include/configs/BSC9132QDS.h | 16 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index aeded6d..9015b76 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -630,6 +630,22 @@ combinations. this should be removed later #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT nor0=8800.nor,nand0=ff80.flash, \ + spi0=spiff707000.0 +#define MTDPARTS_DEFAULT mtdparts=8800.nor:128k(dtb),1m(uboot), \ + 7m(kernel),55m(fs);ff80.flash:3m(uboot), \ + 8m(kernel),1m(dtb),-(user);spiff707000.0: \ + 1m(uboot),4m(kernel),512k(dtb),8m(fs),-(user) +#endif + +/* * Environment Configuration */ -- 1.7.6.GIT ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] QSPI: Enable write device registers
From: Peng Fan van.free...@gmail.com
Add qspi_op_wrr to support status and configuration register write in
flash devices.
Signed-off-by: Peng Fan van.free...@gmail.com
---
drivers/spi/fsl_qspi.c | 77 --
1 file changed, 74 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 7e8d07e..b1d75e7 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -32,12 +32,16 @@
#define SEQID_CHIP_ERASE 5
#define SEQID_PP 6
#define SEQID_RDID 7
+#define SEQID_WRR 8
+#define SEQID_RDCR 9
/* Flash opcodes */
+#define OPCODE_WRR 0x01/* Write status/config register */
#define OPCODE_PP 0x02/* Page program (up to 256 bytes) */
#define OPCODE_RDSR0x05/* Read status register */
#define OPCODE_WREN0x06/* Write enable */
#define OPCODE_FAST_READ 0x0b/* Read data bytes (high frequency) */
+#define OPCODE_RDCR0x35/* Read configuration register */
#define OPCODE_CHIP_ERASE 0xc7/* Erase whole flash chip */
#define OPCODE_SE 0xd8/* Sector erase (usually 64KiB) */
#define OPCODE_RDID0x9f/* Read JEDEC ID */
@@ -189,6 +193,18 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
qspi_write32(regs-lut[lut_base + 2], 0);
qspi_write32(regs-lut[lut_base + 3], 0);
+ /* Write Register */
+ lut_base = SEQID_WRR * 4;
+ qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_WRR) |
+PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(LUT_WRITE) |
+PAD1(LUT_PAD1) | INSTR1(0x2));
+
+ /* Read Configuration Register */
+ lut_base = SEQID_RDCR * 4;
+ qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_RDCR) |
+PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(LUT_READ) |
+PAD1(LUT_PAD1) | INSTR1(0x1));
+
/* Lock the LUT */
qspi_write32(regs-lutkey, LUT_KEY_VALUE);
qspi_write32(regs-lckcr, QSPI_LCKCR_LOCK);
@@ -352,6 +368,55 @@ static void qspi_op_read(struct fsl_qspi *qspi, u32
*rxbuf, u32 len)
qspi_write32(regs-mcr, mcr_reg);
}
+static void qspi_op_wrr(struct fsl_qspi *qspi, u8 *txbuf, u32 len)
+{
+ struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
+ u32 mcr_reg, data, reg, status_reg;
+ u32 to_or_from;
+
+ mcr_reg = qspi_read32(regs-mcr);
+ qspi_write32(regs-mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
+QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+ qspi_write32(regs-rbct, QSPI_RBCT_RXBRD_USEIPS);
+
+ status_reg = 0;
+ while ((status_reg FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
+ qspi_write32(regs-ipcr,
+(SEQID_WREN QSPI_IPCR_SEQID_SHIFT) | 0);
+ while (qspi_read32(regs-sr) QSPI_SR_BUSY_MASK)
+ ;
+
+ qspi_write32(regs-ipcr,
+(SEQID_RDSR QSPI_IPCR_SEQID_SHIFT) | 1);
+ while (qspi_read32(regs-sr) QSPI_SR_BUSY_MASK)
+ ;
+
+ reg = qspi_read32(regs-rbsr);
+ if (reg QSPI_RBSR_RDBFL_MASK) {
+ status_reg = qspi_read32(regs-rbdr[0]);
+ status_reg = qspi_endian_xchg(status_reg);
+ }
+ qspi_write32(regs-mcr,
+qspi_read32(regs-mcr) | QSPI_MCR_CLR_RXF_MASK);
+ }
+
+ to_or_from = qspi-amba_base;
+ qspi_write32(regs-sfar, to_or_from);
+
+ /* The max len is 2 for OPCODE_WRR */
+ data = 0;
+ memcpy(data, txbuf, len);
+ data = qspi_endian_xchg(data);
+ qspi_write32(regs-tbdr, data);
+
+ qspi_write32(regs-ipcr,
+(SEQID_WRR QSPI_IPCR_SEQID_SHIFT) | len);
+ while (qspi_read32(regs-sr) QSPI_SR_BUSY_MASK)
+ ;
+
+ qspi_write32(regs-mcr, mcr_reg);
+}
+
static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf, u32 len)
{
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
@@ -476,11 +541,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
if (dout) {
memcpy(txbuf, dout, 4);
- qspi-cur_seqid = *(u8 *)dout;
+ /* extract cmd when SPI_XFER_BEGIN is set */
+ if (flags SPI_XFER_BEGIN)
+ qspi-cur_seqid = *(u8 *)dout;
if (flags == SPI_XFER_END) {
- qspi-sf_addr = pp_sfaddr;
- qspi_op_pp(qspi, (u32 *)dout, bytes);
+ if (qspi-cur_seqid == OPCODE_WRR) {
+ qspi_op_wrr(qspi, (u8 *)dout, bytes);
+ } else if (qspi-cur_seqid == OPCODE_PP) {
+ qspi-sf_addr = pp_sfaddr;
+
[U-Boot] [GIT PULL] microblaze fixes
Hi Tom, please add these two patch to your tree. Thanks, Michal The following changes since commit 0b703dbcee7103f07804d0a4328d1593355c4324: patman: Fix detection of git version (2014-09-05 13:40:43 -0600) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master for you to fetch changes up to 1a7ae2585410cdd6d88713bcd941463370aacd2e: microblaze: remove #ident directive to fix build error (2014-09-10 10:26:58 +0200) Masahiro Yamada (1): microblaze: remove #ident directive to fix build error Vasili Galka (1): microblaze: Fix printf size_t format related warnings (again...) arch/microblaze/include/asm/posix_types.h | 4 include/systemace.h | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] kconfig: add sanity checks for SPL configuration
For the SPL configuration, make dir/target is used.
Here,
dir is either spl or tpl
target is one of config, menuconfig, xconfig, etc.
This commit adds two checks:
[1] If dir is given an unsupported subimage, the configuration
should error out like this:
$ make qpl/menuconfig
***
*** make qpl/menuconfig is not supported.
***
[2] Make sure that CONFIG_SPL is enabled in the .config before
running make spl/menuconfig. Otherwise, the SPL image
is not built at all. Having spl/.config makes no sense.
In such a case, the configuration should exit with a message:
$ make spl/menuconfig
***
*** Create .config with CONFIG_SPL enabled
*** before make spl/menuconfig.
***
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Suggested-by: Simon Glass s...@chromium.org
---
This check was proposed by Simon in his review
before getting the Kconfig series in.
scripts/multiconfig.sh | 30 ++
1 file changed, 30 insertions(+)
diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh
index 49fcfad..a9e2b96 100644
--- a/scripts/multiconfig.sh
+++ b/scripts/multiconfig.sh
@@ -252,6 +252,35 @@ do_savedefconfig () {
IFS=$save_IFS
}
+# Some sanity checks before running make objdir/target,
+# where objdir should be either spl or tpl.
+# Doing make spl/menuconfig etc. on a non-SPL board makes no sense.
+# It should be allowed only when .config exists and CONFIG_SPL is enabled.
+#
+# Usage:
+# check_enabled_sumbimage objdir/target objdir
+check_enabled_subimage () {
+
+ case $objdir in
+ spl|tpl) ;;
+ *)
+ echo 2 ***
+ echo 2 *** \make $1\ is not supported.
+ echo 2 ***
+ exit 1
+ ;;
+ esac
+ test -r $KCONFIG_CONFIG get_enabled_subimages | grep -q $2 || {
+ config=CONFIG_$(echo $2 | tr '[a-z]' '[A-Z]')
+
+ echo 2 ***
+ echo 2 *** Create \$KCONFIG_CONFIG\ with \$config\
enabled
+ echo 2 *** before \make $1\.
+ echo 2 ***
+ exit 1
+ }
+}
+
# Usage:
# do_others objdir/target
# The field objdir/ is typically empy, spl/, tpl/ for Normal, SPL, TPL,
@@ -265,6 +294,7 @@ do_others () {
objdir=
else
objdir=${1%/*}
+ check_enabled_subimage $1 $objdir
fi
run_make_config $target $objdir
--
1.9.1
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[U-Boot] [PATCH 1/4] imx: mx6slevk: Add I2C1 support
Add I2C1 pin and pad settings, and enable the MXC I2C driver.
Signed-off-by: Ye.Li b37...@freescale.com
---
arch/arm/include/asm/arch-mx6/mx6sl_pins.h |5 +
board/freescale/mx6slevk/mx6slevk.c| 26 ++
include/configs/mx6slevk.h |6 ++
3 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 045ccc4..ac84270 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -34,5 +34,10 @@ enum {
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT=
IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
MX6_PAD_FEC_RX_ER__GPIO_4_19=
IOMUX_PAD(0x0428, 0x0138, 5, 0x, 0, 0),
MX6_PAD_FEC_TX_CLK__GPIO_4_21 =
IOMUX_PAD(0x0434, 0x0144, 5, 0x, 0, 0),
+
+ MX6_PAD_I2C1_SDA__I2C1_SDA =
IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
+ MX6_PAD_I2C1_SDA__GPIO_3_13 =
IOMUX_PAD(0x0450, 0x0160, 5, 0x, 0, 0),
+ MX6_PAD_I2C1_SCL__I2C1_SCL =
IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
+ MX6_PAD_I2C1_SCL__GPIO_3_12 =
IOMUX_PAD(0x044C, 0x015C, 5, 0x, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index a990b4c..fedd5c3 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -13,12 +13,14 @@
#include asm/arch/sys_proto.h
#include asm/gpio.h
#include asm/imx-common/iomux-v3.h
+#include asm/imx-common/mxc_i2c.h
#include asm/io.h
#include linux/sizes.h
#include common.h
#include fsl_esdhc.h
#include mmc.h
#include netdev.h
+#include i2c.h
DECLARE_GLOBAL_DATA_PTR;
@@ -37,8 +39,29 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE |\
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info0 = {
+ .sda = {
+ .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+ .gp = IMX_GPIO_NR(3, 13),
+ },
+ .scl = {
+ .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+ .gp = IMX_GPIO_NR(3, 12),
+ },
+};
+
int dram_init(void)
{
gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -162,6 +185,9 @@ int board_init(void)
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info0);
+
return 0;
}
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 3d05a64..bf5066f 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -60,6 +60,12 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 10
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
--
1.7.4.1
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[U-Boot] [PATCH 3/4] imx: mx6sabresd: Add clear print for pfuze200
Add clear print log to show pfuze200 or pfuze100 found on mx6sabresd. Signed-off-by: Ye.Li b37...@freescale.com --- board/freescale/mx6sabresd/mx6sabresd.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 5f65f1b..72d6562 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -472,7 +472,8 @@ static int pfuze_init(void) return ret; pmic_reg_read(p, PFUZE100_DEVICEID, reg); - printf(PMIC: PFUZE100 ID=0x%02x\n, reg); + printf(PMIC: PFUZE%s ID=0x%02x\n, + ((reg 0xf) == 0) ? 100 : 200, reg); /* Increase VGEN3 from 2.5 to 2.8V */ pmic_reg_read(p, PFUZE100_VGEN3VOL, reg); -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] imx: mx6slevk: Add PMIC Pfuze support
Initialize the Pfuze on I2C1 at board late init. The mx6slevk board
has Pfuze100 or Pfuze200, print the chip type by parsing the ID.
Signed-off-by: Ye.Li b37...@freescale.com
---
board/freescale/mx6slevk/mx6slevk.c | 57 +++
include/configs/mx6slevk.h |7
2 files changed, 64 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index fedd5c3..8b6a79c 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -21,6 +21,8 @@
#include mmc.h
#include netdev.h
#include i2c.h
+#include power/pmic.h
+#include power/pfuze100_pmic.h
DECLARE_GLOBAL_DATA_PTR;
@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define I2C_PMIC 0
+
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info0 = {
.sda = {
@@ -191,6 +195,59 @@ int board_init(void)
return 0;
}
+static int pfuze_init(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg;
+
+ ret = power_pfuze100_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get(PFUZE100);
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, reg);
+ printf(PMIC: PFUZE%s ID=0x%02x\n,
+ ((reg 0xf) == 0) ? 100 : 200, reg);
+
+ /* Set SW1AB stanby volage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1ABSTBY, reg);
+ reg = ~0x3f;
+ reg |= 0x1b;
+ pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PUZE_100_SW1ABCONF, reg);
+ reg = ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+ /* Set SW1C standby voltage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1CSTBY, reg);
+ reg = ~0x3f;
+ reg |= 0x1b;
+ pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE100_SW1CCONF, reg);
+ reg = ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ pfuze_init();
+
+ return 0;
+}
+
u32 get_board_rev(void)
{
return get_cpu_rev();
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index bf5066f..09d0896 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -30,6 +30,7 @@
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
@@ -66,6 +67,12 @@
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 10
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
--
1.7.4.1
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[U-Boot] [PATCH v2] kconfig: add sanity checks for SPL configuration
For the SPL configuration, make dir/target is used.
Here,
dir is either spl or tpl
target is one of config, menuconfig, xconfig, etc.
This commit adds two checks:
[1] If dir is given an unsupported subimage, the configuration
should error out like this:
$ make qpl/menuconfig
***
*** make qpl/menuconfig is not supported.
***
[2] Make sure that CONFIG_SPL is enabled in the .config before
running make spl/menuconfig. Otherwise, the SPL image
is not built at all. Having spl/.config makes no sense.
In such a case, the configuration should exit with a message:
$ make spl/menuconfig
***
*** Create .config with CONFIG_SPL enabled
*** before make spl/menuconfig.
***
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Suggested-by: Simon Glass s...@chromium.org
---
This check was proposed by Simon in his review
before getting the Kconfig series in.
Changes in v2:
- Replace $objdir with $2 in check_enabled_subimage()
scripts/multiconfig.sh | 30 ++
1 file changed, 30 insertions(+)
diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh
index 49fcfad..4a8737f 100644
--- a/scripts/multiconfig.sh
+++ b/scripts/multiconfig.sh
@@ -252,6 +252,35 @@ do_savedefconfig () {
IFS=$save_IFS
}
+# Some sanity checks before running make objdir/target,
+# where objdir should be either spl or tpl.
+# Doing make spl/menuconfig etc. on a non-SPL board makes no sense.
+# It should be allowed only when .config exists and CONFIG_SPL is enabled.
+#
+# Usage:
+# check_enabled_sumbimage objdir/target objdir
+check_enabled_subimage () {
+
+ case $2 in
+ spl|tpl) ;;
+ *)
+ echo 2 ***
+ echo 2 *** \make $1\ is not supported.
+ echo 2 ***
+ exit 1
+ ;;
+ esac
+ test -r $KCONFIG_CONFIG get_enabled_subimages | grep -q $2 || {
+ config=CONFIG_$(echo $2 | tr '[a-z]' '[A-Z]')
+
+ echo 2 ***
+ echo 2 *** Create \$KCONFIG_CONFIG\ with \$config\
enabled
+ echo 2 *** before \make $1\.
+ echo 2 ***
+ exit 1
+ }
+}
+
# Usage:
# do_others objdir/target
# The field objdir/ is typically empy, spl/, tpl/ for Normal, SPL, TPL,
@@ -265,6 +294,7 @@ do_others () {
objdir=
else
objdir=${1%/*}
+ check_enabled_subimage $1 $objdir
fi
run_make_config $target $objdir
--
1.9.1
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[U-Boot] [PATCH 4/4] imx: mx6: Set Pfuze mode to decrease power number for DSM
Set all switches APS mode in normal and PFM mode in standby. So when
mx6 entering DSM mode, the power number can be decreased. There is
no impact for mx6 in run mode.
Changes for boards:
-mx6 sabreauto
-mx6 sabresd
-mx6slevk
-mx6sxsabresd
Signed-off-by: Ye.Li b37...@freescale.com
---
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 36 +
board/freescale/mx6sabresd/mx6sabresd.c | 36 +
board/freescale/mx6slevk/mx6slevk.c | 36 +
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 36 +
4 files changed, 144 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 76b024b..9e79915 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -263,6 +263,37 @@ int board_init(void)
return 0;
}
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+ unsigned char offset, i, switch_num, value;
+
+ if (!chip) {
+ /* pfuze100 */
+ switch_num = 6;
+ offset = 0x31;
+ } else {
+ /* pfuze200 */
+ switch_num = 4;
+ offset = 0x38;
+ }
+
+ value = 0xc;
+ if (pmic_reg_write(p, 0x23, value)) {
+ printf(Set SW1AB mode error!\n);
+ return -1;
+ }
+
+ for (i = 0; i switch_num - 1; i++) {
+ if (pmic_reg_write(p, offset + i * 7, value)) {
+ printf(Set switch%x mode error!\n, offset);
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
static int pfuze_init(void)
{
struct pmic *p;
@@ -281,6 +312,11 @@ static int pfuze_init(void)
pmic_reg_read(p, PFUZE100_DEVICEID, reg);
printf(PMIC: PFUZE100 ID=0x%02x\n, reg);
+ if (pfuze_setup_mode(p, (reg 0xf))) {
+ printf(setup pfuze mode error!\n);
+ return -1;
+ }
+
/* Set SW1AB stanby volage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, reg);
reg = ~0x3f;
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
b/board/freescale/mx6sabresd/mx6sabresd.c
index 72d6562..810fe13 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -456,6 +456,37 @@ int board_init(void)
return 0;
}
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+ unsigned char offset, i, switch_num, value;
+
+ if (!chip) {
+ /* pfuze100 */
+ switch_num = 6;
+ offset = 0x31;
+ } else {
+ /* pfuze200 */
+ switch_num = 4;
+ offset = 0x38;
+ }
+
+ value = 0xc;
+ if (pmic_reg_write(p, 0x23, value)) {
+ printf(Set SW1AB mode error!\n);
+ return -1;
+ }
+
+ for (i = 0; i switch_num - 1; i++) {
+ if (pmic_reg_write(p, offset + i * 7, value)) {
+ printf(Set switch%x mode error!\n, offset);
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
static int pfuze_init(void)
{
struct pmic *p;
@@ -475,6 +506,11 @@ static int pfuze_init(void)
printf(PMIC: PFUZE%s ID=0x%02x\n,
((reg 0xf) == 0) ? 100 : 200, reg);
+ if (pfuze_setup_mode(p, (reg 0xf))) {
+ printf(setup pfuze mode error!\n);
+ return -1;
+ }
+
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, reg);
reg = ~0xf;
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index 8b6a79c..fe5e37d 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -195,6 +195,37 @@ int board_init(void)
return 0;
}
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+ unsigned char offset, i, switch_num, value;
+
+ if (!chip) {
+ /* pfuze100 */
+ switch_num = 6;
+ offset = 0x31;
+ } else {
+ /* pfuze200 */
+ switch_num = 4;
+ offset = 0x38;
+ }
+
+ value = 0xc;
+ if (pmic_reg_write(p, 0x23, value)) {
+ printf(Set SW1AB mode error!\n);
+ return -1;
+ }
+
+ for (i = 0; i switch_num - 1; i++) {
+ if (pmic_reg_write(p, offset + i * 7, value)) {
+ printf(Set switch%x mode error!\n, offset);
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
static int pfuze_init(void)
{
struct pmic *p;
@@
Re: [U-Boot] [PATCH v2 1/2] usb: eth: add ASIX AX88179 DRIVER
Am 09.09.2014 16:34, schrieb Marek Vasut:
On Wednesday, September 03, 2014 at 04:31:20 PM, Rene Griessl wrote:
changes in v2:
-added usb_ether.h to change list
-added 2nd patch to enable driver for arndale board
Signed-off-by: Rene Griessl rgrie...@cit-ec.uni-bielefeld.de
I see that in Linux, there is asix_common.c stuff. Can this driver share any
parts with drivers/net/ax88* ?
The asix_common.c includes asix.h. There you see that the common driver
supports following devices:
AX88172
AX88772
AX88178
but it is not supporting AX88179 and AX88178a, they have a separate
driver called ax88179_178a.c
These two have a different style in accessing MAC registers and PHY
---
drivers/usb/eth/Makefile| 3 +
drivers/usb/eth/asix88179.c | 641
drivers/usb/eth/usb_ether.c |
7 +
include/usb_ether.h | 6 +
4 files changed, 657 insertions(+)
create mode 100644 drivers/usb/eth/asix88179.c
diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile
index 94551c4..fad4acd 100644
--- a/drivers/usb/eth/Makefile
+++ b/drivers/usb/eth/Makefile
@@ -8,5 +8,8 @@ obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
ifdef CONFIG_USB_ETHER_ASIX
obj-y += asix.o
endif
+ifdef CONFIG_USB_ETHER_ASIX_88179
+obj-y += asix88179.o
+endif
This should be obj-$(CONFIG) as seen below. Fix the asix one in a separate
patch please.
[...]
OK
+/* ASIX AX88179 based USB 3.0 Ethernet Devices */
+#define AX88179_PHY_ID 0x03
+#define AX_EEPROM_LEN 0x100
+#define AX88179_EEPROM_MAGIC 0x17900b95
+#define AX_MCAST_FLTSIZE 8
+#define AX_MAX_MCAST 64
+#define AX_INT_PPLS_LINK ((u32)BIT(16))
The u32 cast is not needed. Also, please drop the BIT() macro, it's just
obfuscating the code, just use (1 16) instead. Please fix globally.
OK (was just copy'n'paste from the linux driver)
+#define AX_RXHDR_L4_TYPE_MASK 0x1c
+#define AX_RXHDR_L4_TYPE_UDP 4
+#define AX_RXHDR_L4_TYPE_TCP 16
+#define AX_RXHDR_L3CSUM_ERR2
+#define AX_RXHDR_L4CSUM_ERR1
+#define AX_RXHDR_CRC_ERR ((u32)BIT(29))
+#define AX_RXHDR_DROP_ERR ((u32)BIT(31))
+#define AX_ACCESS_MAC 0x01
+#define AX_ACCESS_PHY 0x02
+#define AX_ACCESS_EEPROM 0x04
+#define AX_ACCESS_EFUS 0x05
+#define AX_PAUSE_WATERLVL_HIGH 0x54
+#define AX_PAUSE_WATERLVL_LOW 0x55
[...]
+static inline int asix_get_phy_addr(struct ueth_data *dev)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);
+ int ret = -1;
+ if (dev-pusb_dev-descriptor.idProduct == 0x1790) {
+ ret = asix_read_cmd(dev, AX_ACCESS_MAC, 0x10, 6, 6, buf);
+ debug(asix_get_phy_addr() returning
0x%02x%02x%02x%02x%02x%02x\n,
+ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ }
+ else {
+ }
Uh, this check needs some rework, right ? Also, you want to lint your patches
with ./scripts/checkpatch.pl tool before resubmitting.
was OK for ./scripts/checkpatch.pl
but I can change that
+ return ret;
+}
+
+
+static int asix_read_mac(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth-priv;
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
+
+ if (dev-pusb_dev-descriptor.idProduct == 0x1790) {
+ asix_read_cmd(dev, AX_ACCESS_MAC, 0x10, 6, 6, buf);
+ debug(asix_read_mac() returning 0x%02x%02x%02x%02x%02x%02x\n,
+ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ memcpy(eth-enetaddr, buf, ETH_ALEN);
+ }
+ return 0;
+}
+
+
+
+static int asix_basic_reset(struct ueth_data *dev)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 6);
Why does the buffer need to be aligned here ? It's just a buffer that is not
used for DMA, no ?
+ u16 *tmp16;
Is it because you were getting unaligned accesses , since when the buffer itself
was not aligned and you did cast it to u16, the CPU triggered unaligned access ?
Thats right, if I do not align I get unaligned accesses during USB
communication.
Is there a smarter solution for that?
+ u8 *tmp;
[...]
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Re: [U-Boot] [PATCH v2 7/8] Makefile: default to cc for host compiler
Hello Albert, On 09-09-14 21:59, Albert ARIBAUD wrote: Hi Jeroen, On Tue, 09 Sep 2014 19:34:44 +0200, Jeroen Hofstee jer...@myspectrum.nl wrote: I've tried building rpi_b as per the README, but I keep getting /usr/bin/as: unrecognized option '-mfloat-abi=soft' clang: error: assembler command failed with exit code 1 (use -v to see invocation) Shouldn't rpi_b build properly since it is the one given as an example for Debian-based building? ok, this turns out to be a simple issue. The gas for arm is not found since CROSS_COMPILE has a trailing dash. When it is removed the correct as is picked up (and libs is found automagically as well). Both the 3.4 and 3.5 binary packages from Ubuntu are able to compile u-boot with this change, so the README should be updated. Regards, Jeroen This should work: make HOSTCC=clang CC=clang -target arm-linux-gnueabi -mllvm -arm-use-movt=0 -no-integrated-as V=1 all ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH v1] powerpc: add --bss-plt to LDFLAGS
Chris Packham judge.pack...@gmail.com wrote on 2014/09/10 06:03:10: With some versions of gcc (that we know of 4.6.3 and 4.8.2 are affected) it is necessary to specify --bss-plt to get the final blrl in the _GOT2_TABLE_. Without this the last symbol does not get it's address relocated. For the P2041RDB board this ended up being NetArpWaitTimerStart which caused the ARP packets to timeout immediately. Helped-by: Joakim Tjernlund joakim.tjernl...@transmode.se Signed-off-by: Chris Packham judge.pack...@gmail.com The commit text is a bit misleading, it is binutils(ld) which has changed default so now one have to specify --bss-plt to get what u-boot needs. Works fine with binutils 2.21.1 Acked-by: Joakim Tjernlund joakim.tjernl...@transmode.se One could possibly argue that --secure-plt should have a NULL word there like the other 3 reserved words around _GLOBAL_OFFSET_TABLE_ to preserve compatibility. PS. -mbss-plt is the gcc option while --bss-plt is the ld option. u-boot invokes ld directly so --bss-plt is appropriate --- Technically this is v2 of http://lists.denx.de/pipermail/u-boot/2014-September/188365.html but the solution is so different that I'm treating it as a new patch series. arch/powerpc/config.mk |1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 6329b6c..fec02f2 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -11,6 +11,7 @@ endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x4 LDFLAGS_FINAL += --gc-sections +LDFLAGS_FINAL += --bss-plt PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections \ -meabi PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] imx: Fix build of mx6sxsabresd
Commit 224beb833e544b802f08765271cec07667d39669 add clock
enabling function for FEC, but the masks are not available
for SX processor and the mx6sxsabresd cannot be built clean.
Signed-off-by: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
CC: Nikita Kiryanov nik...@compulab.co.il
---
arch/arm/cpu/armv7/mx6/clock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 52136f7..336e557 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -78,7 +78,7 @@ void enable_usboh3_clk(unsigned char enable)
}
-#ifdef CONFIG_FEC_MXC
+#if defined(CONFIG_FEC_MXC) !defined(CONFIG_MX6SX)
void enable_enet_clk(unsigned char enable)
{
u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
--
1.9.1
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Re: [U-Boot] [PATCH 4/4] imx: mx6: Set Pfuze mode to decrease power number for DSM
On Wed, Sep 10, 2014 at 6:08 AM, Ye.Li b37...@freescale.com wrote:
+ value = 0xc;
+ if (pmic_reg_write(p, 0x23, value)) {
+ printf(Set SW1AB mode error!\n);
+ return -1;
+ }
-1 is not a proper return code here.
You could do this instead:
ret = pmic_reg_write(p, 0x23, value)
if (ret) {
printf(Set SW1AB mode error: %d\n, ret);
return ret;
}
Same applies for other parts.
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Re: [U-Boot] Please pull u-boot-fsl-qoriq
On Mon, Sep 08, 2014 at 10:45:59AM -0700, York Sun wrote: Tom, This is the first pull request from u-boot-fsl-qoriq repository. In this set, I have v6 patches for Freescale Layerscape 1 SoC LS102xA with ARMv7 cores. These patches have been verified on the boards and compiled with the latest buildman ./tools/buildman/buildman -b u-boot-fsl-qoriq powerpc 'arm freescale'. The following changes since commit d6c1ffc7d23f4fe4ae8c91101861055b8e1501b6: Prepare v2014.10-rc2 (2014-09-02 16:58:29 -0400) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git master for you to fetch changes up to b4ecc8c6f8c85d25f72933af23531728069a5b0f: ls102xa: dcu: Add platform support for DCU on LS1021ATWR board (2014-09-08 10:30:36 -0700) Alison Wang (2): net: mdio: Use mb() to be compatible for both ARM and PowerPC ls102xa: etsec: Add etsec support for LS102xA Claudiu Manoil (2): net: Merge asm/fsl_enet.h into fsl_mdio.h net: tsec: Remove tx snooping support from LS1 Jingchang Lu (1): serial: lpuart: add 32-bit registers lpuart support Wang Huan (9): arm: ls102xa: Add Freescale LS102xA SoC support ls102xa: i2c: Add i2c support for LS102xA esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macros ls102xa: esdhc: Add esdhc support for LS102xA arm: ls102xa: Add basic support for LS1021AQDS board arm: ls102xa: Add basic support for LS1021ATWR board video: dcu: Add DCU driver support video: dcu: Add Sii9022A HDMI Transmitter support ls102xa: dcu: Add platform support for DCU on LS1021ATWR board York Sun (3): driver/ddr/freescale: Add support of accumulate ECC driver/ddr/freescale: Fix DDR3 driver for ARM driver/ddr/fsl: Add support of overriding chip select write leveling arch/arm/Kconfig |8 + arch/arm/cpu/armv7/ls102xa/Makefile | 12 + arch/arm/cpu/armv7/ls102xa/clock.c| 130 ++ arch/arm/cpu/armv7/ls102xa/cpu.c | 103 + arch/arm/cpu/armv7/ls102xa/fdt.c | 136 ++ arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 120 + arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h | 12 + arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c | 41 ++ arch/arm/cpu/armv7/ls102xa/timer.c| 127 ++ arch/arm/include/asm/arch-ls102xa/clock.h | 23 + arch/arm/include/asm/arch-ls102xa/config.h| 78 arch/arm/include/asm/arch-ls102xa/fsl_serdes.h| 33 ++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 493 + arch/arm/include/asm/arch-ls102xa/imx-regs.h | 53 +++ arch/arm/include/asm/config.h |4 + arch/arm/include/asm/io.h |8 +- arch/powerpc/include/asm/fsl_enet.h | 24 - board/freescale/common/Makefile |2 + board/freescale/common/dcu_sii9022a.c | 153 +++ board/freescale/common/dcu_sii9022a.h | 13 + board/freescale/ls1021aqds/Kconfig| 23 + board/freescale/ls1021aqds/MAINTAINERS|6 + board/freescale/ls1021aqds/Makefile |9 + board/freescale/ls1021aqds/README | 112 + board/freescale/ls1021aqds/ddr.c | 159 +++ board/freescale/ls1021aqds/ddr.h | 49 ++ board/freescale/ls1021aqds/eth.c | 186 board/freescale/ls1021aqds/ls1021aqds.c | 255 +++ board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 ++ board/freescale/ls1021atwr/Kconfig| 23 + board/freescale/ls1021atwr/MAINTAINERS|6 + board/freescale/ls1021atwr/Makefile |8 + board/freescale/ls1021atwr/README | 109 + board/freescale/ls1021atwr/dcu.c | 47 ++ board/freescale/ls1021atwr/ls1021atwr.c | 488 board/freescale/mpc8360emds/mpc8360emds.c |2 +- board/freescale/mpc837xemds/mpc837xemds.c |1 - configs/ls1021aqds_nor_defconfig |2 + configs/ls1021atwr_nor_defconfig |2 + doc/README.fsl-esdhc |5 + drivers/ddr/fsl/arm_ddr_gen3.c|2 +- drivers/ddr/fsl/ctrl_regs.c |8 + drivers/ddr/fsl/interactive.c |2 + drivers/i2c/mxc_i2c.c |4 +- drivers/mmc/fsl_esdhc.c |4 +- drivers/net/fm/dtsec.c|1 - drivers/net/fm/fm.h |2 +- drivers/net/fm/init.c |1 +
Re: [U-Boot] Please pull u-boot-x86.git branch 'buildman'
On Tue, Sep 09, 2014 at 04:52:18PM -0600, Simon Glass wrote: Hi Tom, Here are all the pending changes for patman/buildman. Mostly these add tests but there are also several fixes, some found by the tests. I believe it is worth applying these now, to make it easier to find other issues that might come up. Branch is 'buildman'. The following changes since commit 0b703dbcee7103f07804d0a4328d1593355c4324: patman: Fix detection of git version (2014-09-05 13:40:43 -0600) are available in the git repository at: git://git.denx.de/u-boot-x86.git for you to fetch changes up to d0ea61d9caf85e4285d5c2da508db9fac70e4aba: buildman: fix typos of --dry-run help message (2014-09-09 16:48:06 -0600) Masahiro Yamada (1): buildman: fix typos of --dry-run help message Simon Glass (18): patman: Add a way of recording terminal output for testing buildman: Send builder output through a function for testing buildman: Enhance basic test to check summary output patman: RunPipe() should not pipe stdout/stderr unless asked buildman: Move the command line code into its own file buildman: Move full help code into the control module patman: Provide a way to intercept commands for testing buildman: Add a functional test buildman: Set up bsettings outside the control module buildman: Avoid looking at config file or toolchains in tests buildman: Allow tests to have their own boards buildman: Correct counting of build failures on retry buildman: Provide an internal option to clean the outpur dir patman: Start with a clean series when needed buildman: Add additional functional tests buildman: Expand output test to cover directory prefixes buildman: Permit branch names with an embedded '/' buildman: Ignore conflicting tags Thierry Reding (1): buildman: Create parent directories as necessary Vadim Bendebury (1): patman: make run results better visible tools/buildman/bsettings.py | 15 ++- tools/buildman/builder.py | 60 +- tools/buildman/builderthread.py | 22 ++-- tools/buildman/buildman.py | 98 ++-- tools/buildman/cmdline.py | 85 ++ tools/buildman/control.py | 73 tools/buildman/func_test.py | 519 +++ tools/buildman/test.py | 153 +++-- tools/buildman/toolchain.py | 4 +- tools/patman/command.py | 22 tools/patman/gitutil.py | 8 +- tools/patman/patchstream.py | 6 +- tools/patman/patman.py | 7 +- tools/patman/terminal.py| 72 14 files changed, 972 insertions(+), 172 deletions(-) create mode 100644 tools/buildman/cmdline.py create mode 100644 tools/buildman/func_test.py Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [GIT PULL] microblaze fixes
On Wed, Sep 10, 2014 at 10:28:03AM +0200, Michal Simek wrote: Hi Tom, please add these two patch to your tree. Thanks, Michal The following changes since commit 0b703dbcee7103f07804d0a4328d1593355c4324: patman: Fix detection of git version (2014-09-05 13:40:43 -0600) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master for you to fetch changes up to 1a7ae2585410cdd6d88713bcd941463370aacd2e: microblaze: remove #ident directive to fix build error (2014-09-10 10:26:58 +0200) Masahiro Yamada (1): microblaze: remove #ident directive to fix build error Vasili Galka (1): microblaze: Fix printf size_t format related warnings (again...) arch/microblaze/include/asm/posix_types.h | 4 include/systemace.h | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] ARM:MX6SX Add QuadSPI support for mx6sxsabresd
On Wed, Sep 10, 2014 at 3:16 AM, Peng Fan peng@freescale.com wrote: From: Peng Fan van.free...@gmail.com Add QuadSPI support for mx6sxsabresd board. There are two 16MB S25FL128S flashes on board. They are connected to QSPI2 interface. i.MX6SX supports two QuadSPI interfaces, QSPI1/2. The two flash devices are connected to A1/B1 of QSPI2. Signed-off-by: Peng Fan van.free...@gmail.com --- arch/arm/cpu/armv7/mx6/clock.c | 50 + arch/arm/include/asm/arch-mx6/clock.h | 3 ++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +++ drivers/spi/fsl_qspi.c | 30 + include/configs/mx6sxsabresd.h | 14 I would split this in two patches: one that adds qspi support for the mx6solox SoC and another one that adds qspi support to the mx6sxsabresd board. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v2] ARM: keystone: ddr3: workaround for ddr3a/3b memory issue
From: Murali Karicheri m-kariche...@ti.com
This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.
Signed-off-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Keegan Garcia kgar...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
Based on
[U-boot] [Patch v2 0/6] keystone2: add k2l SoC and k2l_evm board support
https://www.mail-archive.com/u-boot@lists.denx.de/msg146721.html
v2..v1
Moved ddr3_err_reset_workaround() under CONFIG_SOC_K2HK
No functional changes
arch/arm/cpu/armv7/keystone/ddr3.c| 75 +++
arch/arm/include/asm/arch-keystone/ddr3.h | 1 +
arch/arm/include/asm/arch-keystone/hardware.h | 2 +
board/ti/ks2_evm/ddr3_k2hk.c | 4 ++
4 files changed, 82 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c
b/arch/arm/cpu/armv7/keystone/ddr3.c
index 2391e79..2eabec1 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -10,6 +10,7 @@
#include asm/io.h
#include common.h
#include asm/arch/ddr3.h
+#include asm/arch/psc_defs.h
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
@@ -86,3 +87,77 @@ void ddr3_reset_ddrphy(void)
tmp = ~KS2_DDR3_PLLCTRL_PHY_RESET;
__raw_writel(tmp, KS2_DDR3APLLCTL1);
}
+
+#ifdef CONFIG_SOC_K2HK
+/**
+ * ddr3_reset_workaround - reset workaround in case if leveling error
+ * detected for PG 1.0 and 1.1 k2hk SoCs
+ */
+void ddr3_err_reset_workaround(void)
+{
+ unsigned int tmp;
+ unsigned int tmp_a;
+ unsigned int tmp_b;
+
+ /*
+* Check for PGSR0 error bits of DDR3 PHY.
+* Check for WLERR, QSGERR, WLAERR,
+* RDERR, WDERR, REERR, WEERR error to see if they are set or not
+*/
+ tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
+ tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
+
+ if (((tmp_a 0x0FE0) != 0) || ((tmp_b 0x0FE0) != 0)) {
+ printf(DDR Leveling Error Detected!\n);
+ printf(DDR3A PGSR0 = 0x%x\n, tmp_a);
+ printf(DDR3B PGSR0 = 0x%x\n, tmp_b);
+
+ /*
+* Write Keys to KICK registers to enable writes to registers
+* in boot config space
+*/
+ __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
+ __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
+
+ /*
+* Move DDR3A Module out of reset isolation by setting
+* MDCTL23[12] = 0
+*/
+ tmp_a = __raw_readl(KS2_PSC_BASE +
+ PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
+
+ tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
+ __raw_writel(tmp_a, KS2_PSC_BASE +
+PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
+
+ /*
+* Move DDR3B Module out of reset isolation by setting
+* MDCTL24[12] = 0
+*/
+ tmp_b = __raw_readl(KS2_PSC_BASE +
+ PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
+ tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
+ __raw_writel(tmp_b, KS2_PSC_BASE +
+PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
+
+ /*
+* Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
+* to RSTCTRL and RSTCFG
+*/
+ tmp = __raw_readl(KS2_RSTCTRL);
+ tmp = KS2_RSTCTRL_MASK;
+ tmp |= KS2_RSTCTRL_KEY;
+ __raw_writel(tmp, KS2_RSTCTRL);
+
+ /*
+* Set PLL Controller to drive hard reset on SW trigger by
+* setting RSTCFG[13] = 0
+*/
+ tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
+ tmp = ~KS2_RSTYPE_PLL_SOFT;
+ __raw_writel(tmp, KS2_RSTCTRL_RSCFG);
+
+ reset_cpu(0);
+ }
+}
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h
b/arch/arm/include/asm/arch-keystone/ddr3.h
index 4d229a2..6bf35d3 100644
--- a/arch/arm/include/asm/arch-keystone/ddr3.h
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -50,6 +50,7 @@ struct ddr3_emif_config {
void ddr3_init(void);
void ddr3_reset_ddrphy(void);
+void ddr3_err_reset_workaround(void);
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index 2eec4e7..29f7bf1 100644
---
Re: [U-Boot] [PATCH 1/3] ARM:MX6SX Add QuadSPI support for mx6sxsabresd
On 09/10/2014 08:40 PM, Fabio Estevam wrote: On Wed, Sep 10, 2014 at 3:16 AM, Peng Fan peng@freescale.com wrote: From: Peng Fan van.free...@gmail.com Add QuadSPI support for mx6sxsabresd board. There are two 16MB S25FL128S flashes on board. They are connected to QSPI2 interface. i.MX6SX supports two QuadSPI interfaces, QSPI1/2. The two flash devices are connected to A1/B1 of QSPI2. Signed-off-by: Peng Fan van.free...@gmail.com --- arch/arm/cpu/armv7/mx6/clock.c | 50 + arch/arm/include/asm/arch-mx6/clock.h | 3 ++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +++ drivers/spi/fsl_qspi.c | 30 + include/configs/mx6sxsabresd.h | 14 I would split this in two patches: one that adds qspi support for the mx6solox SoC and another one that adds qspi support to the mx6sxsabresd board. ok. I'll correct this. Thanks for reviewing. Regards, Peng. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] usb: dfu: add fullspeed support for DFU
Heiko,
On 09/10/2014 01:55 AM, Heiko Schocher wrote:
DFU now can use also fullspeed.
Signed-off-by: Heiko Schocher h...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Liu Bin b-...@ti.com
My first name is Bin.
Other than that, feel free to add
Reviewed by: Bin Liu b-...@ti.com
Regards,
-Bin.
Cc: Lukas Stockmann lukas.stockm...@siemens.com
---
- changes for v2:
- get rid of config option CONFIG_DFU_FULLSPEED as Bin Liu
suggested.
---
drivers/usb/gadget/f_dfu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 1145aab..dfa9f3b 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -238,6 +238,7 @@ static inline void to_dfu_mode(struct f_dfu *f_dfu)
{
f_dfu-usb_function.strings = dfu_strings;
f_dfu-usb_function.hs_descriptors = f_dfu-function;
+ f_dfu-usb_function.descriptors = f_dfu-function;
f_dfu-dfu_state = DFU_STATE_dfuIDLE;
}
@@ -245,6 +246,7 @@ static inline void to_runtime_mode(struct f_dfu *f_dfu)
{
f_dfu-usb_function.strings = NULL;
f_dfu-usb_function.hs_descriptors = dfu_runtime_descs;
+ f_dfu-usb_function.descriptors = dfu_runtime_descs;
}
static int handle_upload(struct usb_request *req, u16 len)
@@ -809,6 +811,7 @@ static int dfu_bind_config(struct usb_configuration *c)
return -ENOMEM;
f_dfu-usb_function.name = dfu;
f_dfu-usb_function.hs_descriptors = dfu_runtime_descs;
+ f_dfu-usb_function.descriptors = dfu_runtime_descs;
f_dfu-usb_function.bind = dfu_bind;
f_dfu-usb_function.unbind = dfu_unbind;
f_dfu-usb_function.set_alt = dfu_set_alt;
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Re: [U-Boot] commit 83e359adf9f578a58f20daf2e4425a754defac7b breaks mmc
On 09/09/2014 12:27 PM, Felipe Balbi wrote: Hi, On Tue, Sep 09, 2014 at 12:09:02PM -0500, Felipe Balbi wrote: Hi, commit 83e359a (am335x_evm: Enable CONFIG_SPL_ENV_SUPPORT on EMMC_BOOT) breaks MMC on some boards. I believe it only breaks if EMMC has no partition on it, so that would point out to a bug on spl env support itself and this has only exposed it. Here's a bisection log anyway: git bisect start # good: [524123a70761110c5cf3ccc5f52f6d4da071b959] Prepare v2014.07 git bisect good 524123a70761110c5cf3ccc5f52f6d4da071b959 # bad: [0b703dbcee7103f07804d0a4328d1593355c4324] patman: Fix detection of git version git bisect bad 0b703dbcee7103f07804d0a4328d1593355c4324 # good: [63b85adcecdd019f049cbbebf10119cea45d3645] imx: ventana: set dynamic env var for flash layout git bisect good 63b85adcecdd019f049cbbebf10119cea45d3645 # good: [63b85adcecdd019f049cbbebf10119cea45d3645] imx: ventana: set dynamic env var for flash layout git bisect good 63b85adcecdd019f049cbbebf10119cea45d3645 # good: [04b43f32731c1171877541050bb3f2bfeb100e3d] tools/genboardscfg.py: ignore defconfigs starting with a dot git bisect good 04b43f32731c1171877541050bb3f2bfeb100e3d # bad: [6defdc0b5552ab1af4a66a8abac8196cbb6b9e15] Merge branch 'master' of git://git.denx.de/u-boot-ti git bisect bad 6defdc0b5552ab1af4a66a8abac8196cbb6b9e15 # good: [6af857c50df4e62ec08e51ad73c96f63f1480386] Merge branch 'master' of http://git.denx.de/u-boot-sunxi git bisect good 6af857c50df4e62ec08e51ad73c96f63f1480386 # good: [7f14fb20f895016fb38d30ce71aeb4d441b5bcb8] Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze git bisect good 7f14fb20f895016fb38d30ce71aeb4d441b5bcb8 # bad: [61f66fd5a81b97478e9d14326c1059baa6626680] keystone2: use EFUSE_BOOTROM information to configure PLLs git bisect bad 61f66fd5a81b97478e9d14326c1059baa6626680 # bad: [fea9543f1bd1d068a372ef378f624941c25989a8] board/ti/am335x: update configs for parallel NAND git bisect bad fea9543f1bd1d068a372ef378f624941c25989a8 # good: [e017fd61c5a89e32db682d94d8d669df1709edbb] tseries: Set CONFIG_ENV_IS_NOWHERE for SPL+NAND git bisect good e017fd61c5a89e32db682d94d8d669df1709edbb # bad: [83e359adf9f578a58f20daf2e4425a754defac7b] am335x_evm: Enable CONFIG_SPL_ENV_SUPPORT on EMMC_BOOT git bisect bad 83e359adf9f578a58f20daf2e4425a754defac7b # good: [00e385325fce36fa13d48091d73b1b3428394b6b] common/Makefile: Consolidate SPL ENV options, correct inclusion git bisect good 00e385325fce36fa13d48091d73b1b3428394b6b # first bad commit: [83e359adf9f578a58f20daf2e4425a754defac7b] am335x_evm: Enable CONFIG_SPL_ENV_SUPPORT on EMMC_BOOT Revert that commit also makes it work, btw. On a further dig into this, it looks like when enabling CONFIG_SPL_ENV_SUPPORT, somehow MMC numbering changes and u-boot ends up trying to read environment from a non-formatted EMMC. forgot to mention, this is all on BBB and affects only am335x-based boards, of course. I believe this is the problem that https://patchwork.ozlabs.org/patch/385354/ is intended to fix. See also discussion at http://www.mail-archive.com/u-boot@lists.denx.de/msg146396.html Peter ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] usb: eth: add ASIX AX88179 DRIVER
On Wednesday, September 10, 2014 at 12:00:29 PM, René Griessl wrote:
Am 09.09.2014 16:34, schrieb Marek Vasut:
On Wednesday, September 03, 2014 at 04:31:20 PM, Rene Griessl wrote:
changes in v2:
-added usb_ether.h to change list
-added 2nd patch to enable driver for arndale board
Signed-off-by: Rene Griessl rgrie...@cit-ec.uni-bielefeld.de
I see that in Linux, there is asix_common.c stuff. Can this driver share
any parts with drivers/net/ax88* ?
The asix_common.c includes asix.h. There you see that the common driver
supports following devices:
AX88172
AX88772
AX88178
but it is not supporting AX88179 and AX88178a, they have a separate
driver called ax88179_178a.c
These two have a different style in accessing MAC registers and PHY
I didn't look deep enough. The 88179 driver is a completely separate driver,
not
sharing any code what-so-ever with the other ASIX driver, yes ?
[...]
+buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ }
+ else {
+ }
Uh, this check needs some rework, right ? Also, you want to lint your
patches with ./scripts/checkpatch.pl tool before resubmitting.
was OK for ./scripts/checkpatch.pl
but I can change that
This is rather surprising, but you're right. Please fix this up, the else can
be
dropped and the trailing } can be indented just under the if () clause.
+ return ret;
+}
+
+
+static int asix_read_mac(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth-priv;
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
+
+ if (dev-pusb_dev-descriptor.idProduct == 0x1790) {
+ asix_read_cmd(dev, AX_ACCESS_MAC, 0x10, 6, 6, buf);
+ debug(asix_read_mac() returning 0x%02x%02x%02x%02x%02x%02x\n,
+buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ memcpy(eth-enetaddr, buf, ETH_ALEN);
+ }
Same here.
+ return 0;
+}
+
+
+
+static int asix_basic_reset(struct ueth_data *dev)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 6);
Why does the buffer need to be aligned here ? It's just a buffer that is
not used for DMA, no ?
+ u16 *tmp16;
Is it because you were getting unaligned accesses , since when the buffer
itself was not aligned and you did cast it to u16, the CPU triggered
unaligned access ?
Thats right, if I do not align I get unaligned accesses during USB
communication.
Is there a smarter solution for that?
Oh I see. The smart solution would be to add bounce buffer into the USB stack,
but unless you want to dive into this, this solution would be OK here.
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Re: [U-Boot] [PATCH] common: fix include guards for CONFIG_MP
On 09/03/2014 01:57 PM, Gabriel Huau wrote: This was breaking the build for some boards: MPC8536DS MPC8536DS_36BIT MPC8536DS_SDCARD MPC8536DS_SPIFLASH qemu-ppce500 Include only these features for some PPC boards if the configuration for MultiProcessor is enabled. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr Cc: Tom Rini tr...@ti.com Cc: York Sun york...@freescale.com --- common/board_f.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/board_f.c b/common/board_f.c index 4ece2b6..deea9ca 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -34,7 +34,7 @@ #ifdef CONFIG_MPC5xxx #include mpc5xxx.h #endif -#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#if defined(CONFIG_MP) (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) #include asm/mp.h #endif @@ -392,7 +392,7 @@ static int setup_dest_addr(void) gd-ram_top = board_get_usable_ram_top(gd-mon_len); gd-relocaddr = gd-ram_top; debug(Ram top: %08lX\n, (ulong)gd-ram_top); -#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#if defined(CONFIG_MP) (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) /* * We need to make sure the location we intend to put secondary core * boot code is reserved and not used by any part of u-boot Acked-by: York Sun york...@freescale.com York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 7/8] Makefile: default to cc for host compiler
Since the host compiler might not be gcc but e.g. clang default to cc/c++ to invoke it. cc: Masahiro Yamada yamad...@jp.panasonic.com cc: Tom Rini tr...@ti.com Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index fdda3ec..42263e4 100644 --- a/Makefile +++ b/Makefile @@ -197,8 +197,8 @@ CONFIG_SHELL := $(shell if [ -x $$BASH ]; then echo $$BASH; \ else if [ -x /bin/bash ]; then echo /bin/bash; \ else echo sh; fi ; fi) -HOSTCC = gcc -HOSTCXX = g++ +HOSTCC = cc +HOSTCXX = c++ HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer HOSTCXXFLAGS = -O2 -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 0/8] add clang support for some ARM boards
Changes since v2: - As Albert pointed out the clang instructions don't work with Debian based binary packages. While I was aware of that it is for a different reason then I thought, it is not that ARM is not enabled as a backend but older versions are a bit more picky on the target argument and don't tolerate a trailing dash to it as used for CROSS_COMPILE etc. The README is updated accordingly. As a side note clang3.5-svn as shipped in Ubuntu is not the 3.5 release but an snapshot of some svn commit and hence explain why the recompiled 3.5 can behave different then the ubuntu clang-3.5. Since it misses some patches, the clang3.5-svn can build less boards then 3.4 or an actual 3.5 release. - While add it, include Masahiro suggestion to also use c++ instead of g++. - Drop dependencies from the cover-letter as they are merged. - only patch 7/8 and 8/8 are reposted. 1..6 are the same as v2. Changes since v1 (RFC): - Update the commit message for -Werror when polling for cc-options. As pointed out by Masahiro this is not needed for all arguments, but only for warning options. - drop SOC specific patch from this patchset, I will post it seperately. - Do implement get_gd for AARCH64. - Drop the memset patch for clearing gd / not reassinging gd and use Simon his version. - Drop the patch for using gnu inline version, since targets using the generic board no longer need it. - Limit update gd in board_init_r to ARM / ARM64, since powerpc does need it. - change __inline to inline and drop volatile from get_gd to make checkpatch happy. - add patch workaround for generated constants - add patch default to cc for host compiler - update README.clang - add SOB / cc Jeroen Hofstee (8): board_r: ARM[64] do not set gd again ARM: SPL: do not set gd again cc-option: also detect unsupported warnings options ARM: make gd a function for clang eabi_compat: add __aeabi_memcpy __aeabi_memset clang: workaround for generated constants Makefile: default to cc for host compiler README.clang: build command with clang Kbuild | 3 +- Makefile | 4 +-- arch/arm/include/asm/global_data.h | 25 + arch/arm/lib/eabi_compat.c | 15 -- arch/arm/lib/spl.c | 3 -- common/board_r.c | 2 +- doc/README.clang | 56 ++ include/linux/kbuild.h | 6 ++-- scripts/Kbuild.include | 4 +-- 9 files changed, 104 insertions(+), 14 deletions(-) create mode 100644 doc/README.clang -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 8/8] README.clang: build command with clang
Cc: Albert ARIBAUD albert.u.b...@aribaud.net Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl --- doc/README.clang | 56 1 file changed, 56 insertions(+) create mode 100644 doc/README.clang diff --git a/doc/README.clang b/doc/README.clang new file mode 100644 index 000..9ad689f --- /dev/null +++ b/doc/README.clang @@ -0,0 +1,56 @@ +The biggest problem when trying to compile U-boot with clang is that +almost all archs rely on storing gd in a global register and clang user +manual states: clang does not support global register variables; this +is unlikely to be implemented soon because it requires additional LLVM +backend support. + +Since version 3.4 the ARM backend can be instructed to leave r9 alone. +Global registers themselves are not supported so some inline assembly is +used to get its value. This does lead to larger code then strictly +necessary, but at least works. + +NOTE: target compilation only work for _some_ ARM boards at the moment. +Also Aarch64 is not supported: Most notably boards which aren't using +the generic board will fail to compile, but since those are expected +to be converted this will solve itself. Boards which reassign gd in c +will also fail to compile, but there is in no strict reason to do so +in the ARM world, since crt0.S takes care of this. These assignments +can be avoided by changing the init calls but this is not in mainline yet. + +NOTE: without the -mllvm -arm-use-movt=0 flags u-boot will compile +fine, but llvm might hardcode addresses in movw / movt pairs, which +cannot be relocated and u-boot will fail at runtime. + +Debian (based) +-- +Binary packages can be installed as usual, e.g.: +sudo apt-get install clang + +To compile U-Boot with clang on linux without IAS use e.g.: +export TRIPLET=arm-linux-gnueabi export CROSS_COMPILE=$TRIPLET- +make HOSTCC=clang CC=clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as rpi_b_defconfig +make HOSTCC=clang CC=clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrated-as all V=1 -j8 + +FreeBSD 11 (Current): + +Since llvm 3.4 is currently in the base system, the integrated as is +incapable of building U-Boot. Therefore gas from devel/arm-eabi-binutils +is used instead. It needs a symlinks to be picked up correctly though: + +ln -s /usr/local/bin/arm-eabi-as /usr/bin/arm-freebsd-eabi-as + +# The following commands compile U-Boot using the clang xdev toolchain. +# NOTE: CROSS_COMPILE and target differ on purpose! +export CROSS_COMPILE=arm-eabi- +gmake CC=clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0 rpi_b_defconfig +gmake CC=clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0 -j8 + +Given that u-boot will default to gcc, above commands can be +simplified with a simple wrapper script, listed below. + +/usr/local/bin/arm-eabi-gcc +--- +#!/bin/sh + +exec clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0 $@ + -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 01/18] patman: Add a way of recording terminal output for testing
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Re: [U-Boot] [PATCH v3 02/18] buildman: Send builder output through a function for testing
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Re: [U-Boot] [PATCH v3 03/18] buildman: Enhance basic test to check summary output
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Re: [U-Boot] [PATCH v3 04/18] patman: RunPipe() should not pipe stdout/stderr unless asked
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Re: [U-Boot] [PATCH v3 05/18] buildman: Move the command line code into its own file
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Re: [U-Boot] [PATCH v3 06/18] buildman: Move full help code into the control module
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Re: [U-Boot] [PATCH v3 08/18] buildman: Add a functional test
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Re: [U-Boot] [PATCH v3 07/18] patman: Provide a way to intercept commands for testing
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Re: [U-Boot] [PATCH v3 09/18] buildman: Set up bsettings outside the control module
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Re: [U-Boot] [PATCH v3 10/18] buildman: Avoid looking at config file or toolchains in tests
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Re: [U-Boot] [PATCH v3 11/18] buildman: Allow tests to have their own boards
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Re: [U-Boot] [PATCH v3 12/18] buildman: Correct counting of build failures on retry
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Re: [U-Boot] [PATCH v3 15/18] buildman: Add additional functional tests
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Re: [U-Boot] [PATCH v3 14/18] patman: Start with a clean series when needed
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Re: [U-Boot] [PATCH v3 13/18] buildman: Provide an internal option to clean the outpur dir
Applied to u-boot-x86/buildman.
Fixed up to avoid removing the tree when it doesn't exist.
On 5 September 2014 19:00, Simon Glass s...@chromium.org wrote:
For testing it is useful to clean the output directory before running a
test. This avoids a test interfering with the results of a subsequent
test by leaving data around.
Add this feature as an optional parameter to the control logic.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
tools/buildman/control.py | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index fb15ae8..2f51249 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -5,6 +5,7 @@
import multiprocessing
import os
+import shutil
import sys
import board
@@ -78,7 +79,8 @@ def ShowActions(series, why_selected, boards_selected,
builder, options):
print ('Total boards to build for each commit: %d\n' %
why_selected['all'])
-def DoBuildman(options, args, toolchains=None, make_func=None, boards=None):
+def DoBuildman(options, args, toolchains=None, make_func=None, boards=None,
+ clean_dir=False):
The main control code for buildman
Args:
@@ -93,6 +95,8 @@ def DoBuildman(options, args, toolchains=None,
make_func=None, boards=None):
board: Boards() object to use, containing a list of available
boards. If this is None it will be created and scanned.
+global builder
+
if options.full_help:
pager = os.getenv('PAGER')
if not pager:
@@ -209,6 +213,8 @@ def DoBuildman(options, args, toolchains=None,
make_func=None, boards=None):
else:
dirname = 'current'
output_dir = os.path.join(options.output_dir, dirname)
+if clean_dir:
+shutil.rmtree(output_dir)
builder = Builder(toolchains, output_dir, options.git_dir,
options.threads, options.jobs, gnu_make=gnu_make, checkout=True,
show_unknown=options.show_unknown, step=options.step)
@@ -230,6 +236,9 @@ def DoBuildman(options, args, toolchains=None,
make_func=None, boards=None):
if series:
commits = series.commits
+# Number the commits for test purposes
+for commit in range(len(commits)):
+commits[commit].sequence = commit
else:
commits = None
--
2.1.0.rc2.206.gedb03e5
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Re: [U-Boot] [PATCH v3 17/18] buildman: Permit branch names with an embedded '/'
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Re: [U-Boot] [PATCH v3 18/18] buildman: Ignore conflicting tags
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Re: [U-Boot] [PATCH v3 16/18] buildman: Expand output test to cover directory prefixes
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Re: [U-Boot] [PATCH v2] patman: make run results better visible
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Re: [U-Boot] [U-Boot, v2] buildman: Create parent directories as necessary
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Re: [U-Boot] [PATCH v2] buildman: fix typos of --dry-run help message
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[U-Boot] Please pull u-boot-dm.git
Hi Tom, This pull includes driver model implementations for serial (uclass, sandbox and Tegra) as well as GPIO for Tegra, I've held off on exynos until we resolve some questions there. I'm not 100% sure it will make the release. The following changes since commit b7a809957bcd72c2efa49ce733774b1e28878585: Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze (2014-09-10 06:59:49 -0400) are available in the git repository at: git://git.denx.de/u-boot-dm.git for you to fetch changes up to 858530a8c0a7ce7e573e513934804a00d6676813: dm: tegra: Enable driver model for serial (2014-09-10 13:00:02 -0600) Simon Glass (17): dm: Move pre-reloc init earlier to cope with board_early_init_f() Set up stdio earlier when using driver model dm: Make driver model available before board_init() dm: tegra: Set up a pre-reloc malloc() tegra: Convert tegra GPIO driver to use driver model serial: Set up the 'priv' pointer when creating a serial device dm: fdt: Add a function to look up a chosen node dm: Adjust lists_bind_fdt() to return the bound device dm: Add a uclass for serial devices sandbox: Convert serial driver to use driver model sandbox: serial: Support a coloured console sandbox: dts: Add a serial console node dm: serial: Move baud rate calculation to ns16550.c dm: serial: Collect common baud rate code in ns16550 dm: serial: Add driver model support for ns16550 tegra: dts: Add serial port details dm: tegra: Enable driver model for serial arch/arm/dts/tegra114-dalmore.dts | 4 + arch/arm/dts/tegra114.dtsi | 53 + arch/arm/dts/tegra124-jetson-tk1.dts | 4 + arch/arm/dts/tegra124-venice2.dts | 4 + arch/arm/dts/tegra124.dtsi | 66 + arch/arm/dts/tegra20-colibri_t20_iris.dts | 4 + arch/arm/dts/tegra20-harmony.dts | 4 + arch/arm/dts/tegra20-medcom-wide.dts | 4 + arch/arm/dts/tegra20-paz00.dts | 4 + arch/arm/dts/tegra20-plutux.dts| 4 + arch/arm/dts/tegra20-seaboard.dts | 4 + arch/arm/dts/tegra20-tec.dts | 4 + arch/arm/dts/tegra20-trimslice.dts | 4 + arch/arm/dts/tegra20-ventana.dts | 4 + arch/arm/dts/tegra20-whistler.dts | 4 + arch/arm/dts/tegra20.dtsi | 51 ++--- arch/arm/dts/tegra30-beaver.dts| 4 + arch/arm/dts/tegra30-cardhu.dts| 4 + arch/arm/dts/tegra30-tamonten.dtsi | 4 + arch/arm/dts/tegra30.dtsi | 66 + arch/arm/include/asm/arch-tegra/gpio.h | 15 ++-- arch/sandbox/dts/sandbox.dts | 10 +++ board/nvidia/seaboard/seaboard.c | 2 +- common/board_f.c | 4 +- common/board_r.c | 19 +++-- common/stdio.c | 18 - doc/device-tree-bindings/serial/ns16550.txt| 10 +++ doc/device-tree-bindings/serial/sandbox-serial.txt | 13 drivers/core/lists.c | 10 ++- drivers/core/root.c| 2 +- drivers/gpio/tegra_gpio.c | 327 ++-- drivers/serial/Makefile| 7 +- drivers/serial/ns16550.c | 203 -- drivers/serial/sandbox.c | 140 +++--- drivers/serial/serial-uclass.c | 213 drivers/serial/serial.c| 1 + drivers/serial/serial_ns16550.c| 14 +--- drivers/serial/serial_tegra.c | 38 ++ include/configs/sandbox.h | 3 + include/configs/tegra-common.h | 11 ++- include/dm/lists.h | 6 +- include/dm/uclass-id.h | 1 + include/dt-bindings/clock/tegra114-car.h | 342 include/dt-bindings/clock/tegra124-car.h | 342 include/dt-bindings/clock/tegra20-car.h| 158 +++ include/dt-bindings/clock/tegra30-car.h| 273 +++ include/fdtdec.h
Re: [U-Boot] [PATCH] e1000: add i211 and unprogrammed i210/i211 support
On Mon, 2014-09-08 at 04:07 +0200, Marek Vasut wrote:
Does the network really work with an i21x with unprogrammed iNVM ?
Yes, it actually does work quite nicely. However I currently still have
to patch it additionally as follows:
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index ce19173..5f9c606 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -1128,7 +1128,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw,
uint16_t mask)
if (!timeout) {
DEBUGOUT(Driver can't access resource, SW_FW_SYNC
timeout.\n);
- return -E1000_ERR_SWFW_SYNC;
+// return -E1000_ERR_SWFW_SYNC;
}
swfw_sync |= swmask;
@@ -4378,7 +4378,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
if (!timeout) {
DEBUGOUT(MNG configuration cycle has not
completed.\n);
- return -E1000_ERR_RESET;
+// return -E1000_ERR_RESET;
}
break;
}
Without doing the above it fails as follows (enabled E1000_DEBUG):
U-Boot SPL 2014.10-rc2-00043-g80a3caa-dirty (Sep 08 2014 - 12:26:27)
U-Boot 2014.10-rc2-00043-g80a3caa-dirty (Sep 08 2014 - 12:26:27)
TEGRA30
Board: Toradex Apalis T30
I2C: ready
DRAM: 1 GiB
MMC: Tegra SD/MMC: 0, Tegra SD/MMC: 1, Tegra SD/MMC: 2
tegra-pcie: PCI regions:
tegra-pcie: I/O: 0x200-0x201
tegra-pcie: non-prefetchable memory: 0x2000-0x3000
tegra-pcie: prefetchable memory: 0x3000-0x4000
tegra-pcie: 4x1, 1x2 configuration
tegra-pcie: probing port 2, using 1 lanes
In:serial
Out: serial
Err: serial
Net: e1000_initialize
e1000: e1000#0: DEBUG: iobase 0x2000
e1000_set_mac_type
e1000_set_media_type
copper interface
e1000_reset_hw
Masking off all interrupts
Issuing a global reset to MAC
PF OK
EEC OK
Masking off all interrupts
e1000: no NVM
e1000#0
Error: e1000#0 address not set.
Hit any key to stop autoboot: 0
Apalis T30 # setenv ethaddr 00:14:2d:27:35:8f
Apalis T30 # dhcp
e1000_reset_hw
Masking off all interrupts
Issuing a global reset to MAC
PF OK
EEC OK
Masking off all interrupts
e1000_init_hw
e1000_set_media_type
Initializing the IEEE VLAN
e1000_init_rx_addrs
Programming MAC Address into RAR[0]
Clearing RAR[1-15]
Zeroing the MTA
e1000_setup_link
After fix-ups FlowControl is now = 3
e1000_setup_copper_link
e1000_copper_link_preconfig
e1000_detect_gig_phy
e1000_set_phy_type
PHY ID 0x1410C00 detected
Phy ID = 1410c00
e1000_copper_link_mgp_setup
e1000_phy_reset
e1000_phy_hw_reset
Resetting Phy...
e1000_swfw_sync_acquire
Driver can't access resource, SW_FW_SYNC timeout.
Unable to acquire swfw sync
Error Resetting the PHY
e1000: e1000#0: ERROR: Hardware Initialization Failed
This is both with programmed (iNVM only, haven't tried external serial
PROM possible on i210) as well as unprogrammed i210 as well as i211
chips on our Apalis T30 modules.
Have you ever seen any such issue? Wondering whether this is a Tegra
PCIe related issue. May I ask about your specific platform you tried
this on? Could you send some output of a working session with
E1000_DEBUG enabled? I plan to try it on a Boundary Devices Nitrogen6X
as well as our Apalis iMX6 module as well.
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[U-Boot] arm kirkwood pending patches
Hi, I have noticed that there are 3 pending kirkwood patches that I've sent a while back. It seems that there has been no action since then. Patches have been ACKed... Can we get some progress on these: http://patchwork.ozlabs.org/patch/366225/ http://patchwork.ozlabs.org/patch/366226/ http://patchwork.ozlabs.org/patch/366227/ Thanks. Regards, Luka ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] u-boot-socfpga repository
Hello, I'd be interested in maintaining u-boot-socfpga repository. So far, we don't have a repo for this platform and there is a large flurry of patches flying around without any kind of central point for them. I'd like to get your formal consent for starting this and if you agree, I'd start sending PR to Albert once the repo is in place. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] arm:mx6sx add QSPI support
Add QSPI support for mx6solox.
Signed-off-by: Peng Fan peng@freescale.com
---
Changelog v2:
Take Fabio's suggestion, split soc code and board code into two patches.
arch/arm/cpu/armv7/mx6/clock.c| 50 +++
arch/arm/include/asm/arch-mx6/clock.h | 3 +++
drivers/spi/fsl_qspi.c| 29
3 files changed, 82 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 820b8d5..8caa61d 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -340,6 +340,56 @@ static u32 get_mmdc_ch0_clk(void)
}
#endif
+#ifdef CONFIG_MX6SX
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+ u32 reg = 0;
+ /* Enable QuadSPI clock */
+ switch (qspi_num) {
+ case 0:
+ /* disable the clock gate */
+ clrbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(imx_ccm-cscmr1);
+ reg = ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+ reg |= ((1 MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+ (2 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+ writel(reg, imx_ccm-cscmr1);
+
+ /* enable the clock gate */
+ setbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+ break;
+ case 1:
+ /*
+* disable the clock gate
+* QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+* disable both of them.
+*/
+ clrbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(imx_ccm-cs2cdr);
+ reg = ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+ reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+ writel(reg, imx_ccm-cs2cdr);
+
+ /*enable the clock gate*/
+ setbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+ break;
+ default:
+ break;
+ }
+}
+#endif
+
#ifdef CONFIG_FEC_MXC
int enable_fec_anatop_clock(enum enet_freq freq)
{
diff --git a/arch/arm/include/asm/arch-mx6/clock.h
b/arch/arm/include/asm/arch-mx6/clock.h
index 339c789..9d0ba7a 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -60,4 +60,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
+#ifdef CONFIG_MX6SX
+void enable_qspi_clk(int qspi_num);
+#endif
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index ba20bef..7c8d065 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,7 +14,11 @@
#include fsl_qspi.h
#define RX_BUFFER_SIZE 0x80
+#ifdef CONFIG_MX6SX
+#define TX_BUFFER_SIZE 0x200
+#else
#define TX_BUFFER_SIZE 0x40
+#endif
#define OFFSET_BITS_MASK 0x00ff
@@ -52,11 +56,19 @@
#endif
static unsigned long spi_bases[] = {
+#ifdef CONFIG_MX6SX
+ CONFIG_QSPI_BASE,
+#else
QSPI0_BASE_ADDR,
+#endif
};
static unsigned long amba_bases[] = {
+#ifdef CONFIG_MX6SX
+ CONFIG_QSPI_MEMMAP_BASE,
+#else
QSPI0_AMBA_BASE,
+#endif
};
struct fsl_qspi {
@@ -157,8 +169,14 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_PP_4B) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+#ifdef CONFIG_MX6SX
+ /* Use IDATSZ in IPCR to determine the size */
+ qspi_write32(regs-lut[lut_base + 1], OPRND0(0) |
+ PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+#else
qspi_write32(regs-lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+#endif
qspi_write32(regs-lut[lut_base + 2], 0);
qspi_write32(regs-lut[lut_base + 3], 0);
@@ -192,6 +210,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
if (bus = ARRAY_SIZE(spi_bases))
return NULL;
+#ifdef CONFIG_MX6SX
+ /* cs should be 0 - (FSL_QSPI_FLASH_NUM - 1) */
+ if (cs = FSL_QSPI_FLASH_NUM)
+ return NULL;
+#endif
+
qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
[U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support
Configure the pad setting and enable qspi clock to support qspi
flashes access.
This patch has been tested on mx6sxsabresd board.
Signed-off-by: Peng Fan peng@freescale.com
---
Changelog v2:
Take Fabio's suggestion, split soc code and board code into two patches.
This patch needs 'ARM:MX6SX Add QSPI support' patch.
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +
include/configs/mx6sxsabresd.h | 14 ++
2 files changed, 54 insertions(+)
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 5eaec1b..f9cad5a 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
}
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+ MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA07__QSPI2_A_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA05__QSPI2_B_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+ /* Set the iomux */
+ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ARRAY_SIZE(quadspi_pads));
+
+ /* Set the clock */
+ enable_qspi_clk(1);
+
+ return 0;
+}
+#endif
+
int board_init(void)
{
/* Address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_FSL_QSPI
+ board_qspi_init();
+#endif
+
return 0;
}
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 1eda65e..00031ec 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -201,6 +201,20 @@
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_FSL_QSPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_FSL_QSPI_LE
+#define CONFIG_QSPI_BASE QSPI2_BASE_ADDR
+#define CONFIG_QSPI_MEMMAP_BASEQSPI2_ARB_BASE_ADDR
+#define FSL_QSPI_FLASH_SIZESZ_16M
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+
#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_SIZESZ_8K
#define CONFIG_ENV_IS_IN_MMC
--
1.8.4
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Re: [U-Boot] [PATCH] dw_mmc: cleanups
Hi, Pavel.
It looks good to me.
If you're ok, can i suggest one thing?
On 09/05/2014 07:49 PM, Pavel Machek wrote:
dw_mmc driver was responding to errors with debug(). Change that to
prinf so that any errors are immediately obvious. Also adjust english
in comments.
Signed-off-by: Pavel Machek pa...@denx.de
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 0df30bc..4c16e7f 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -177,14 +177,16 @@ static int dwmci_send_cmd(struct mmc *mmc, struct
mmc_cmd *cmd,
}
}
- if (i == retry)
+ if (i == retry) {
+ printf(dwmci_send_cmd: timeout..\n);
return TIMEOUT;
+ }
if (mask DWMCI_INTMSK_RTO) {
- debug(Response Timeout..\n);
+ printf(dwmci_send_cmd: Response Timeout..\n);
return TIMEOUT;
} else if (mask DWMCI_INTMSK_RE) {
- debug(Response Error..\n);
+ printf(dwmci_send_cmd: Response Error..\n);
return -1;
}
@@ -204,7 +206,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
*cmd,
do {
mask = dwmci_readl(host, DWMCI_RINTSTS);
if (mask (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
- debug(DATA ERROR!\n);
+ printf(dwmci_send_cmd: DATA ERROR!\n);
return -1;
}
} while (!(mask DWMCI_INTMSK_DTO));
@@ -232,16 +234,16 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
if ((freq == host-clock) || (freq == 0))
return 0;
/*
- * If host-get_mmc_clk didn't define,
+ * If host-get_mmc_clk isn't defined,
* then assume that host-bus_hz is source clock value.
- * host-bus_hz should be set from user.
+ * host-bus_hz should be set by user.
*/
if (host-get_mmc_clk)
sclk = host-get_mmc_clk(host);
else if (host-bus_hz)
sclk = host-bus_hz;
else {
- printf(Didn't get source clock value..\n);
+ printf(dwmci_setup_bus: Didn't get source clock value..\n);
return -EINVAL;
}
@@ -260,7 +262,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
do {
status = dwmci_readl(host, DWMCI_CMD);
if (timeout-- 0) {
- printf(TIMEOUT error!!\n);
+ printf(dwmci_setup_bus: timeout!\n);
return -ETIMEDOUT;
}
} while (status DWMCI_CMD_START);
@@ -275,7 +277,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
do {
status = dwmci_readl(host, DWMCI_CMD);
if (timeout-- 0) {
- printf(TIMEOUT error!!\n);
+ printf(dwmci_setup_bus: timeout!\n);
According to your the main purpose, this patch is goal that noticed where/what
error is occurred.
Then i think good that add the __LINE__.
Because there are same message like dwmci_setup_bus: tiemout!\n at some place.
Then i think we don't need to discuss about this patch with Marek. :)
Best Regards,
Jaehoon Chung
return -ETIMEDOUT;
}
} while (status DWMCI_CMD_START);
@@ -290,7 +292,7 @@ static void dwmci_set_ios(struct mmc *mmc)
struct dwmci_host *host = (struct dwmci_host *)mmc-priv;
u32 ctype, regs;
- debug(Buswidth = %d, clock: %d\n,mmc-bus_width, mmc-clock);
+ debug(Buswidth = %d, clock: %d\n, mmc-bus_width, mmc-clock);
dwmci_setup_bus(host, mmc-clock);
switch (mmc-bus_width) {
@@ -329,7 +331,7 @@ static int dwmci_init(struct mmc *mmc)
dwmci_writel(host, DWMCI_PWREN, 1);
if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
- debug(%s[%d] Fail-reset!!\n,__func__,__LINE__);
+ printf(%s[%d] Fail-reset!!\n, __func__, __LINE__);
return -1;
}
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[U-Boot] [PATCH v2 1/4] imx: mx6slevk: Add I2C1 support
Add I2C1 pin and pad settings, and enable the MXC I2C driver.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
arch/arm/include/asm/arch-mx6/mx6sl_pins.h |5 +
board/freescale/mx6slevk/mx6slevk.c| 26 ++
include/configs/mx6slevk.h |6 ++
3 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 045ccc4..ac84270 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -34,5 +34,10 @@ enum {
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT=
IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
MX6_PAD_FEC_RX_ER__GPIO_4_19=
IOMUX_PAD(0x0428, 0x0138, 5, 0x, 0, 0),
MX6_PAD_FEC_TX_CLK__GPIO_4_21 =
IOMUX_PAD(0x0434, 0x0144, 5, 0x, 0, 0),
+
+ MX6_PAD_I2C1_SDA__I2C1_SDA =
IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
+ MX6_PAD_I2C1_SDA__GPIO_3_13 =
IOMUX_PAD(0x0450, 0x0160, 5, 0x, 0, 0),
+ MX6_PAD_I2C1_SCL__I2C1_SCL =
IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
+ MX6_PAD_I2C1_SCL__GPIO_3_12 =
IOMUX_PAD(0x044C, 0x015C, 5, 0x, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index a990b4c..fedd5c3 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -13,12 +13,14 @@
#include asm/arch/sys_proto.h
#include asm/gpio.h
#include asm/imx-common/iomux-v3.h
+#include asm/imx-common/mxc_i2c.h
#include asm/io.h
#include linux/sizes.h
#include common.h
#include fsl_esdhc.h
#include mmc.h
#include netdev.h
+#include i2c.h
DECLARE_GLOBAL_DATA_PTR;
@@ -37,8 +39,29 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE |\
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info0 = {
+ .sda = {
+ .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+ .gp = IMX_GPIO_NR(3, 13),
+ },
+ .scl = {
+ .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+ .gp = IMX_GPIO_NR(3, 12),
+ },
+};
+
int dram_init(void)
{
gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -162,6 +185,9 @@ int board_init(void)
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info0);
+
return 0;
}
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 3d05a64..bf5066f 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -60,6 +60,12 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 10
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
--
1.7.4.1
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[U-Boot] [PATCH v2 2/4] imx: mx6slevk: Add PMIC Pfuze support
Initialize the Pfuze on I2C1 at board late init. The mx6slevk board
has Pfuze100 or Pfuze200, print the chip type by parsing the ID.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
board/freescale/mx6slevk/mx6slevk.c | 57 +++
include/configs/mx6slevk.h |7
2 files changed, 64 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index fedd5c3..8b6a79c 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -21,6 +21,8 @@
#include mmc.h
#include netdev.h
#include i2c.h
+#include power/pmic.h
+#include power/pfuze100_pmic.h
DECLARE_GLOBAL_DATA_PTR;
@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define I2C_PMIC 0
+
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info0 = {
.sda = {
@@ -191,6 +195,59 @@ int board_init(void)
return 0;
}
+static int pfuze_init(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg;
+
+ ret = power_pfuze100_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get(PFUZE100);
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, reg);
+ printf(PMIC: PFUZE%s ID=0x%02x\n,
+ ((reg 0xf) == 0) ? 100 : 200, reg);
+
+ /* Set SW1AB stanby volage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1ABSTBY, reg);
+ reg = ~0x3f;
+ reg |= 0x1b;
+ pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PUZE_100_SW1ABCONF, reg);
+ reg = ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+ /* Set SW1C standby voltage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1CSTBY, reg);
+ reg = ~0x3f;
+ reg |= 0x1b;
+ pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE100_SW1CCONF, reg);
+ reg = ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ pfuze_init();
+
+ return 0;
+}
+
u32 get_board_rev(void)
{
return get_cpu_rev();
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index bf5066f..09d0896 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -30,6 +30,7 @@
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
@@ -66,6 +67,12 @@
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 10
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
--
1.7.4.1
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[U-Boot] [PATCH v2 4/4] imx: mx6: Set Pfuze mode to decrease power number for DSM
Set all switches APS mode in normal and PFM mode in standby. So when
mx6 entering DSM mode, the power number can be decreased. There is
no impact for mx6 in run mode.
Changes for boards:
-mx6 sabreauto
-mx6 sabresd
-mx6slevk
-mx6sxsabresd
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- Correct the return code per Fabio's comments.
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 36 +
board/freescale/mx6sabresd/mx6sabresd.c | 36 +
board/freescale/mx6slevk/mx6slevk.c | 36 +
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 36 +
4 files changed, 144 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 76b024b..9e79915 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -263,6 +263,37 @@ int board_init(void)
return 0;
}
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+ unsigned char offset, i, switch_num, value;
+
+ if (!chip) {
+ /* pfuze100 */
+ switch_num = 6;
+ offset = 0x31;
+ } else {
+ /* pfuze200 */
+ switch_num = 4;
+ offset = 0x38;
+ }
+
+ value = 0xc;
+ if (pmic_reg_write(p, 0x23, value)) {
+ printf(Set SW1AB mode error!\n);
+ return -1;
+ }
+
+ for (i = 0; i switch_num - 1; i++) {
+ if (pmic_reg_write(p, offset + i * 7, value)) {
+ printf(Set switch%x mode error!\n, offset);
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
static int pfuze_init(void)
{
struct pmic *p;
@@ -281,6 +312,11 @@ static int pfuze_init(void)
pmic_reg_read(p, PFUZE100_DEVICEID, reg);
printf(PMIC: PFUZE100 ID=0x%02x\n, reg);
+ if (pfuze_setup_mode(p, (reg 0xf))) {
+ printf(setup pfuze mode error!\n);
+ return -1;
+ }
+
/* Set SW1AB stanby volage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, reg);
reg = ~0x3f;
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
b/board/freescale/mx6sabresd/mx6sabresd.c
index 72d6562..810fe13 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -456,6 +456,37 @@ int board_init(void)
return 0;
}
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+ unsigned char offset, i, switch_num, value;
+
+ if (!chip) {
+ /* pfuze100 */
+ switch_num = 6;
+ offset = 0x31;
+ } else {
+ /* pfuze200 */
+ switch_num = 4;
+ offset = 0x38;
+ }
+
+ value = 0xc;
+ if (pmic_reg_write(p, 0x23, value)) {
+ printf(Set SW1AB mode error!\n);
+ return -1;
+ }
+
+ for (i = 0; i switch_num - 1; i++) {
+ if (pmic_reg_write(p, offset + i * 7, value)) {
+ printf(Set switch%x mode error!\n, offset);
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
static int pfuze_init(void)
{
struct pmic *p;
@@ -475,6 +506,11 @@ static int pfuze_init(void)
printf(PMIC: PFUZE%s ID=0x%02x\n,
((reg 0xf) == 0) ? 100 : 200, reg);
+ if (pfuze_setup_mode(p, (reg 0xf))) {
+ printf(setup pfuze mode error!\n);
+ return -1;
+ }
+
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, reg);
reg = ~0xf;
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index 8b6a79c..fe5e37d 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -195,6 +195,37 @@ int board_init(void)
return 0;
}
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+ unsigned char offset, i, switch_num, value;
+
+ if (!chip) {
+ /* pfuze100 */
+ switch_num = 6;
+ offset = 0x31;
+ } else {
+ /* pfuze200 */
+ switch_num = 4;
+ offset = 0x38;
+ }
+
+ value = 0xc;
+ if (pmic_reg_write(p, 0x23, value)) {
+ printf(Set SW1AB mode error!\n);
+ return -1;
+ }
+
+ for (i = 0; i switch_num - 1; i++) {
+ if (pmic_reg_write(p, offset + i * 7, value)) {
+ printf(Set switch%x mode error!\n, offset);
+ return -1;
+ }
+ }
+
+ return 0;
[U-Boot] [PATCH v2 3/4] imx: mx6sabresd: Add clear print for pfuze200
Add clear print log to show pfuze200 or pfuze100 found on mx6sabresd. Signed-off-by: Ye.Li b37...@freescale.com --- Changes since v1: - None board/freescale/mx6sabresd/mx6sabresd.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 5f65f1b..72d6562 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -472,7 +472,8 @@ static int pfuze_init(void) return ret; pmic_reg_read(p, PFUZE100_DEVICEID, reg); - printf(PMIC: PFUZE100 ID=0x%02x\n, reg); + printf(PMIC: PFUZE%s ID=0x%02x\n, + ((reg 0xf) == 0) ? 100 : 200, reg); /* Increase VGEN3 from 2.5 to 2.8V */ pmic_reg_read(p, PFUZE100_VGEN3VOL, reg); -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 4/4] imx: mx6: Set Pfuze mode to decrease power number for DSM
On Wed, Sep 10, 2014 at 11:25 PM, Ye.Li b37...@freescale.com wrote: Set all switches APS mode in normal and PFM mode in standby. So when mx6 entering DSM mode, the power number can be decreased. There is no impact for mx6 in run mode. Changes for boards: -mx6 sabreauto -mx6 sabresd -mx6slevk -mx6sxsabresd Signed-off-by: Ye.Li b37...@freescale.com --- Changes since v1: - Correct the return code per Fabio's comments. Are you sure about that? I still see a lot of return -1 in this patch ;-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support
Just CC Stefano Babic sba...@denx.de
Regards,
Peng.
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On
Behalf Of Peng Fan
Sent: Thursday, September 11, 2014 9:56 AM
To: Estevam Fabio-R49496; Li Ye-B37916
Cc: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support
Configure the pad setting and enable qspi clock to support qspi flashes access.
This patch has been tested on mx6sxsabresd board.
Signed-off-by: Peng Fan peng@freescale.com
---
Changelog v2:
Take Fabio's suggestion, split soc code and board code into two patches.
This patch needs 'ARM:MX6SX Add QSPI support' patch.
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +
include/configs/mx6sxsabresd.h | 14 ++
2 files changed, 54 insertions(+)
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 5eaec1b..f9cad5a 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, usdhc_cfg[0]); }
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+ MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA07__QSPI2_A_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA05__QSPI2_B_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+ /* Set the iomux */
+ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ARRAY_SIZE(quadspi_pads));
+
+ /* Set the clock */
+ enable_qspi_clk(1);
+
+ return 0;
+}
+#endif
+
int board_init(void)
{
/* Address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_FSL_QSPI
+ board_qspi_init();
+#endif
+
return 0;
}
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 1eda65e..00031ec 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -201,6 +201,20 @@
/* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH
+#define CONFIG_FSL_QSPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_FSL_QSPI_LE
+#define CONFIG_QSPI_BASE QSPI2_BASE_ADDR
+#define CONFIG_QSPI_MEMMAP_BASEQSPI2_ARB_BASE_ADDR
+#define FSL_QSPI_FLASH_SIZESZ_16M
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+
#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_SIZESZ_8K
#define CONFIG_ENV_IS_IN_MMC
--
1.8.4
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Re: [U-Boot] [PATCH v2 4/4] imx: mx6: Set Pfuze mode to decrease power number for DSM
On 9/11/2014 10:28 AM, Fabio Estevam wrote: On Wed, Sep 10, 2014 at 11:25 PM, Ye.Li b37...@freescale.com wrote: Set all switches APS mode in normal and PFM mode in standby. So when mx6 entering DSM mode, the power number can be decreased. There is no impact for mx6 in run mode. Changes for boards: -mx6 sabreauto -mx6 sabresd -mx6slevk -mx6sxsabresd Signed-off-by: Ye.Li b37...@freescale.com --- Changes since v1: - Correct the return code per Fabio's comments. Are you sure about that? I still see a lot of return -1 in this patch ;-) Sorry, my fault. Send out v3 soon. Best regards, Ye Li ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] u-boot-socfpga repository
On Thu, 11 Sep 2014 01:33:20 +0200 Marek Vasut ma...@denx.de wrote: Hello, I'd be interested in maintaining u-boot-socfpga repository. So far, we don't have a repo for this platform and there is a large flurry of patches flying around without any kind of central point for them. I'd like to get your formal consent for starting this and if you agree, I'd start sending PR to Albert once the repo is in place. Me too. I'd like to own u-boot-uniphier to collect Panasonic-SoC-specific changes. That would be faster and would not disturb Albert. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/4] imx: mx6slevk: Add I2C1 support
Add I2C1 pin and pad settings, and enable the MXC I2C driver.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
Changes since v2:
- None
arch/arm/include/asm/arch-mx6/mx6sl_pins.h |5 +
board/freescale/mx6slevk/mx6slevk.c| 26 ++
include/configs/mx6slevk.h |6 ++
3 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 045ccc4..ac84270 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -34,5 +34,10 @@ enum {
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT=
IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
MX6_PAD_FEC_RX_ER__GPIO_4_19=
IOMUX_PAD(0x0428, 0x0138, 5, 0x, 0, 0),
MX6_PAD_FEC_TX_CLK__GPIO_4_21 =
IOMUX_PAD(0x0434, 0x0144, 5, 0x, 0, 0),
+
+ MX6_PAD_I2C1_SDA__I2C1_SDA =
IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
+ MX6_PAD_I2C1_SDA__GPIO_3_13 =
IOMUX_PAD(0x0450, 0x0160, 5, 0x, 0, 0),
+ MX6_PAD_I2C1_SCL__I2C1_SCL =
IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
+ MX6_PAD_I2C1_SCL__GPIO_3_12 =
IOMUX_PAD(0x044C, 0x015C, 5, 0x, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index a990b4c..fedd5c3 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -13,12 +13,14 @@
#include asm/arch/sys_proto.h
#include asm/gpio.h
#include asm/imx-common/iomux-v3.h
+#include asm/imx-common/mxc_i2c.h
#include asm/io.h
#include linux/sizes.h
#include common.h
#include fsl_esdhc.h
#include mmc.h
#include netdev.h
+#include i2c.h
DECLARE_GLOBAL_DATA_PTR;
@@ -37,8 +39,29 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE |\
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info0 = {
+ .sda = {
+ .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+ .gp = IMX_GPIO_NR(3, 13),
+ },
+ .scl = {
+ .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+ .gp = IMX_GPIO_NR(3, 12),
+ },
+};
+
int dram_init(void)
{
gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -162,6 +185,9 @@ int board_init(void)
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info0);
+
return 0;
}
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 3d05a64..bf5066f 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -60,6 +60,12 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 10
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
--
1.7.4.1
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[U-Boot] [PATCH v3 3/4] imx: mx6sabresd: Add clear print for pfuze200
Add clear print log to show pfuze200 or pfuze100 found on mx6sabresd. Signed-off-by: Ye.Li b37...@freescale.com --- Changes since v1: - None Changes since v2: - None board/freescale/mx6sabresd/mx6sabresd.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 5f65f1b..72d6562 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -472,7 +472,8 @@ static int pfuze_init(void) return ret; pmic_reg_read(p, PFUZE100_DEVICEID, reg); - printf(PMIC: PFUZE100 ID=0x%02x\n, reg); + printf(PMIC: PFUZE%s ID=0x%02x\n, + ((reg 0xf) == 0) ? 100 : 200, reg); /* Increase VGEN3 from 2.5 to 2.8V */ pmic_reg_read(p, PFUZE100_VGEN3VOL, reg); -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 2/4] imx: mx6slevk: Add PMIC Pfuze support
Initialize the Pfuze on I2C1 at board late init. The mx6slevk board
has Pfuze100 or Pfuze200, print the chip type by parsing the ID.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- None
Changes since v2:
- None
board/freescale/mx6slevk/mx6slevk.c | 57 +++
include/configs/mx6slevk.h |7
2 files changed, 64 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index fedd5c3..8b6a79c 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -21,6 +21,8 @@
#include mmc.h
#include netdev.h
#include i2c.h
+#include power/pmic.h
+#include power/pfuze100_pmic.h
DECLARE_GLOBAL_DATA_PTR;
@@ -48,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define I2C_PMIC 0
+
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info0 = {
.sda = {
@@ -191,6 +195,59 @@ int board_init(void)
return 0;
}
+static int pfuze_init(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg;
+
+ ret = power_pfuze100_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get(PFUZE100);
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, reg);
+ printf(PMIC: PFUZE%s ID=0x%02x\n,
+ ((reg 0xf) == 0) ? 100 : 200, reg);
+
+ /* Set SW1AB stanby volage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1ABSTBY, reg);
+ reg = ~0x3f;
+ reg |= 0x1b;
+ pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PUZE_100_SW1ABCONF, reg);
+ reg = ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+ /* Set SW1C standby voltage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1CSTBY, reg);
+ reg = ~0x3f;
+ reg |= 0x1b;
+ pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE100_SW1CCONF, reg);
+ reg = ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ pfuze_init();
+
+ return 0;
+}
+
u32 get_board_rev(void)
{
return get_cpu_rev();
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index bf5066f..09d0896 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -30,6 +30,7 @@
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
@@ -66,6 +67,12 @@
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 10
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
--
1.7.4.1
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[U-Boot] [PATCH v3 4/4] imx: mx6: Set Pfuze mode to decrease power number for DSM
Set all switches APS mode in normal and PFM mode in standby. So when
mx6 entering DSM mode, the power number can be decreased. There is
no impact for mx6 in run mode.
Changes for boards:
-mx6 sabreauto
-mx6 sabresd
-mx6slevk
-mx6sxsabresd
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- Try to correct the return code per Fabio's comments, but send out a false
patch
Changes since v2:
- Correct the return code
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 41 +
board/freescale/mx6sabresd/mx6sabresd.c | 41 +
board/freescale/mx6slevk/mx6slevk.c | 41 +
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40
4 files changed, 163 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 76b024b..df7f845 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -263,6 +263,41 @@ int board_init(void)
return 0;
}
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+ unsigned char offset, i, switch_num, value;
+ int ret;
+
+ if (!chip) {
+ /* pfuze100 */
+ switch_num = 6;
+ offset = 0x31;
+ } else {
+ /* pfuze200 */
+ switch_num = 4;
+ offset = 0x38;
+ }
+
+ value = 0xc;
+ ret = pmic_reg_write(p, 0x23, value);
+ if (ret) {
+ printf(Set SW1AB mode error: %d!\n, ret);
+ return ret;
+ }
+
+ for (i = 0; i switch_num - 1; i++) {
+ ret = pmic_reg_write(p, offset + i * 7, value);
+ if (ret) {
+ printf(Set switch%x mode error: %d!\n, offset, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+
static int pfuze_init(void)
{
struct pmic *p;
@@ -281,6 +316,12 @@ static int pfuze_init(void)
pmic_reg_read(p, PFUZE100_DEVICEID, reg);
printf(PMIC: PFUZE100 ID=0x%02x\n, reg);
+ ret = pfuze_setup_mode(p, (reg 0xf));
+ if (ret) {
+ printf(setup pfuze mode error: %d!\n, ret);
+ return ret;
+ }
+
/* Set SW1AB stanby volage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, reg);
reg = ~0x3f;
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
b/board/freescale/mx6sabresd/mx6sabresd.c
index 72d6562..e0f0d2c 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -456,6 +456,41 @@ int board_init(void)
return 0;
}
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+ unsigned char offset, i, switch_num, value;
+ int ret;
+
+ if (!chip) {
+ /* pfuze100 */
+ switch_num = 6;
+ offset = 0x31;
+ } else {
+ /* pfuze200 */
+ switch_num = 4;
+ offset = 0x38;
+ }
+
+ value = 0xc;
+ ret = pmic_reg_write(p, 0x23, value);
+ if (ret) {
+ printf(Set SW1AB mode error: %d!\n, ret);
+ return ret;
+ }
+
+ for (i = 0; i switch_num - 1; i++) {
+ ret = pmic_reg_write(p, offset + i * 7, value);
+ if (ret) {
+ printf(Set switch%x mode error: %d!\n, offset, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+
static int pfuze_init(void)
{
struct pmic *p;
@@ -475,6 +510,12 @@ static int pfuze_init(void)
printf(PMIC: PFUZE%s ID=0x%02x\n,
((reg 0xf) == 0) ? 100 : 200, reg);
+ ret = pfuze_setup_mode(p, (reg 0xf));
+ if (ret) {
+ printf(setup pfuze mode error: %d!\n, ret);
+ return ret;
+ }
+
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, reg);
reg = ~0xf;
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index 8b6a79c..8fa58c4 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -195,6 +195,41 @@ int board_init(void)
return 0;
}
+/* set all switches APS in normal and PFM mode in standby */
+static int pfuze_setup_mode(struct pmic *p, int chip)
+{
+ unsigned char offset, i, switch_num, value;
+ int ret;
+
+ if (!chip) {
+ /* pfuze100 */
+ switch_num = 6;
+ offset = 0x31;
+ } else {
+ /* pfuze200 */
+ switch_num = 4;
+ offset = 0x38;
+ }
+
+ value = 0xc;
+ ret = pmic_reg_write(p, 0x23, value);
+ if (ret) {
+
[U-Boot] [PATCH 2/2] mpc85xx: configs - Add hash command in freescale platforms
Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com CC: York Sun york...@freescale.com --- The patch series is dependent on https://patchwork.ozlabs.org/patch/387174/ https://patchwork.ozlabs.org/patch/387175/ include/configs/B4860QDS.h | 4 include/configs/BSC9131RDB.h | 4 include/configs/BSC9132QDS.h | 4 include/configs/C29XPCIE.h | 4 include/configs/P1010RDB.h | 4 include/configs/P2041RDB.h | 4 include/configs/T1040QDS.h | 4 include/configs/T104xRDB.h | 4 include/configs/T208xQDS.h | 4 include/configs/T208xRDB.h | 4 include/configs/T4240QDS.h | 4 include/configs/T4240RDB.h | 4 include/configs/corenet_ds.h | 4 13 files changed, 52 insertions(+) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 953d06b..58932ad 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -758,6 +758,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * USB */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 56a3e94..fb50db0 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -382,6 +382,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index aeded6d..922ac00 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -598,6 +598,10 @@ combinations. this should be removed later #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 715616d..ca1b2f5 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -506,6 +506,10 @@ #define CONFIG_CMD_SETEXPR #define CONFIG_CMD_REGINFO +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index a373990..45ef53d 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -832,6 +832,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 16f7525..7ff2dd5 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -647,6 +647,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index a781ba3..5870a49 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -716,6 +716,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 0ee0ff2..8e43931 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -727,6 +727,10 @@ #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 395472b..9a8a3b6 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -777,6 +777,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + /* * Miscellaneous configurable options */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index e5936c7..4ff31e6 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -736,6
[U-Boot] [PATCH 1/2] fsl_sec : Add hardware accelerated SHA256 and SHA1
SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's
The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
CC: York Sun york...@freescale.com
---
The patch series is dependent on
https://patchwork.ozlabs.org/patch/387174/
https://patchwork.ozlabs.org/patch/387175/
arch/powerpc/cpu/mpc85xx/cpu_init.c | 5 +
arch/powerpc/include/asm/config.h | 4 +
arch/powerpc/include/asm/immap_85xx.h | 5 +
arch/powerpc/include/asm/types.h | 4 +
drivers/crypto/Makefile | 1 +
drivers/crypto/fsl/Makefile | 9 +
drivers/crypto/fsl/desc.h | 651 ++
drivers/crypto/fsl/desc_constr.h | 280 +++
drivers/crypto/fsl/error.c| 258 ++
drivers/crypto/fsl/fsl_hash.c | 119 +++
drivers/crypto/fsl/jobdesc.c | 45 +++
drivers/crypto/fsl/jobdesc.h | 18 +
drivers/crypto/fsl/jr.c | 288 +++
drivers/crypto/fsl/jr.h | 100 ++
include/fsl_sec.h | 45 +++
15 files changed, 1832 insertions(+)
create mode 100644 drivers/crypto/fsl/Makefile
create mode 100644 drivers/crypto/fsl/desc.h
create mode 100644 drivers/crypto/fsl/desc_constr.h
create mode 100644 drivers/crypto/fsl/error.c
create mode 100644 drivers/crypto/fsl/fsl_hash.c
create mode 100644 drivers/crypto/fsl/jobdesc.c
create mode 100644 drivers/crypto/fsl/jobdesc.h
create mode 100644 drivers/crypto/fsl/jr.c
create mode 100644 drivers/crypto/fsl/jr.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index bf9fbbf..21c3194 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -27,6 +27,7 @@
#include hwconfig.h
#include linux/compiler.h
#include mp.h
+#include fsl_sec.h
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include nand.h
#include errno.h
@@ -938,6 +939,10 @@ int cpu_init_r(void)
fman_enet_init();
#endif
+#if CONFIG_SYS_FSL_SEC_COMPAT = 4
+ sec_init();
+#endif
+
#if defined(CONFIG_FSL_SATA_V2) defined(CONFIG_FSL_SATA_ERRATUM_A001)
/*
* For P1022/1013 Rev1.0 silicon, after power on SATA host
diff --git a/arch/powerpc/include/asm/config.h
b/arch/powerpc/include/asm/config.h
index 423a6fb..e1b2c20 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -103,4 +103,8 @@
/* All PPC boards must swap IDE bytes */
#define CONFIG_IDE_SWAP_IO
+#if CONFIG_SYS_FSL_SEC_COMPAT = 4
+#define CONFIG_FSL_CAAM
+#endif
+
#endif /* _ASM_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index e426314..88c1e08 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2875,6 +2875,7 @@ struct ccsr_sfp_regs {
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET0x22
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET0x221000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x30
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
@@ -2935,8 +2936,10 @@ struct ccsr_sfp_regs {
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET0x2e000
#if defined(CONFIG_PPC_C29X)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x8
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
#else
#define CONFIG_SYS_FSL_SEC_OFFSET 0x3
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
#endif
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
@@ -3041,6 +3044,8 @@ struct ccsr_sfp_regs {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_FM1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
index b27a6b7..b29ce79 100644
--- a/arch/powerpc/include/asm/types.h
+++ b/arch/powerpc/include/asm/types.h
@@ -41,8 +41,12 @@ typedef unsigned long long u64;
#define BITS_PER_LONG 32
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long dma_addr_t;
+#else
/* DMA addresses are 32-bits wide */
typedef u32 dma_addr_t;
+#endif
#ifdef CONFIG_PHYS_64BIT
typedef unsigned long long phys_addr_t;
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index b807795..7b79237 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -6,3 +6,4 @@
#
obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o
+obj-y += fsl/
diff --git
Re: [U-Boot] u-boot-socfpga repository
Hi, On 09/11/2014 05:09 AM, Masahiro Yamada wrote: On Thu, 11 Sep 2014 01:33:20 +0200 Marek Vasut ma...@denx.de wrote: Hello, I'd be interested in maintaining u-boot-socfpga repository. So far, we don't have a repo for this platform and there is a large flurry of patches flying around without any kind of central point for them. I'd like to get your formal consent for starting this and if you agree, I'd start sending PR to Albert once the repo is in place. Me too. I'd like to own u-boot-uniphier to collect Panasonic-SoC-specific changes. That would be faster and would not disturb Albert. I am not sure if you need to have separate repo to work like this. I am keeping zynq patches in my microblaze repo and sending pull request to Albert (or Tom now) and there is no problem with that. Alberts know that and it is working quite well. It is enough to talk to him and that's it. In socfpga case I think there are guys from Altera who maintain it. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] odroid: set MPLL clock to 880MHz
On 05/09/14 19:50, Przemyslaw Marczak wrote: Hello Minkyu, On 09/05/2014 08:55 AM, Minkyu Kang wrote: On 24/07/14 19:42, Przemyslaw Marczak wrote: This patch changes MPLL from 800MHz to 880MHz on Odroid. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com --- board/samsung/odroid/odroid.c | 60 +-- 1 file changed, 30 insertions(+), 30 deletions(-) applied to u-boot-samsung. Thanks, Minkyu Kang. Thank you for applying the Odroid patch set. I would like to note, that this one patch was intended for MR. Daniel just for his tests. This patch breaks dw mmc performance: e.g. eMMC uImage(fat) read performance: - before this commit: 47.6 MiB/s - after this commit: 13.0 MiB/s So this requires some more changes in clocks and also in dw mmc driver. And it can break some kernel clocks divider dependencies. It is not tested. So please revert this patch. Best Regards, reverted.. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 7/8] Makefile: default to cc for host compiler
Hi Jeroen, On Tue, 09 Sep 2014 19:34:44 +0200 Jeroen Hofstee jer...@myspectrum.nl wrote: Hello Albert, On 09-09-14 16:31, Albert ARIBAUD wrote: On Thu, 31 Jul 2014 19:01:22 +0900, Masahiro Yamada yamad...@jp.panasonic.com wrote: HOSTCXX = g++ HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer For consistency, HOSTCXX = c++ ? So, Jeroen, what is your pick ? Will you send a v3 7/8, or are you sticking with g++? (or if everyone agrees, I could to the change to v2 7/8 when applying it, and add a comment about it in the commit message.) I did check Masahiro's statement that cpp is actually used in u-boot and it is; make xconfig uses it, if I recall correctly. And as Masahiro suggested I sent it to linux-kbuild mailinglist, but I am in the impression it never arrived, perhaps I need to be subscribed or something... I received it because you cced me. But I am afraid it did not reach the kbuild ML because I could not find it in the kbuild ML archive. I recommend to subscribe to the ML and then resend your patch. To subscribe to it, visit the following and click 'subscribe' http://vger.kernel.org/vger-lists.html#linux-kbuild The kbuild ML does not have much volume. I guess you won't be annoyed. To attract the attention of key persons, I'd like to suggest: - add 'kbuild: ' prefix to the subject like: kbuild: default to cc/c++ for host compiler - you can cc linux-ker...@vger.kernel.org too. (scripts/get_maintainer.pl will do it automatically. But I am not sure if it can be reached from unsubscribers. this ML has a huge volume..) Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] odroid: set MPLL clock to 880MHz
Hi, On 09/11/2014 02:03 PM, Minkyu Kang wrote: On 05/09/14 19:50, Przemyslaw Marczak wrote: Hello Minkyu, On 09/05/2014 08:55 AM, Minkyu Kang wrote: On 24/07/14 19:42, Przemyslaw Marczak wrote: This patch changes MPLL from 800MHz to 880MHz on Odroid. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com --- board/samsung/odroid/odroid.c | 60 +-- 1 file changed, 30 insertions(+), 30 deletions(-) applied to u-boot-samsung. Thanks, Minkyu Kang. Thank you for applying the Odroid patch set. I would like to note, that this one patch was intended for MR. Daniel just for his tests. This patch breaks dw mmc performance: e.g. eMMC uImage(fat) read performance: - before this commit: 47.6 MiB/s - after this commit: 13.0 MiB/s So this requires some more changes in clocks and also in dw mmc driver. MPLL is used to the eMMC's source clock. If MPLL is changed to 880MHz, then eMMC's clock should not be set to correct value. It has to test before changed MPLL clock. otherwise, we need to use other source clock. Best Regards, Jaehoon Chung And it can break some kernel clocks divider dependencies. It is not tested. So please revert this patch. Best Regards, reverted.. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] u-boot-socfpga repository
Hi Michal, On Thu, 11 Sep 2014 06:56:04 +0200 Michal Simek mon...@monstr.eu wrote: Hi, On 09/11/2014 05:09 AM, Masahiro Yamada wrote: On Thu, 11 Sep 2014 01:33:20 +0200 Marek Vasut ma...@denx.de wrote: Hello, I'd be interested in maintaining u-boot-socfpga repository. So far, we don't have a repo for this platform and there is a large flurry of patches flying around without any kind of central point for them. I'd like to get your formal consent for starting this and if you agree, I'd start sending PR to Albert once the repo is in place. Me too. I'd like to own u-boot-uniphier to collect Panasonic-SoC-specific changes. That would be faster and would not disturb Albert. I am not sure if you need to have separate repo to work like this. I am keeping zynq patches in my microblaze repo and sending pull request to Albert (or Tom now) and there is no problem with that. The point is that you collect Zynq-specific patches in your own place by yourself and then send a pull-req to Albert or Tom, right? It does not matter whether it is a separate u-boot-zynq repo or u-boot-microbraze/zynq branch. I have sent the first series to add the core support of Panasonic SoCs and boards (but it is taking much longer than I have expected) and then I am planning to send more features and boards in the next phase. What's the difference between what I want to do for Panasonic SoCs and what you usually do for Zynq SoCs? Alberts know that and it is working quite well. It is enough to talk to him and that's it. In socfpga case I think there are guys from Altera who maintain it. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
