date:20141231

Hi Masahiro,

On 11 December 2014 at 10:37, Masahiro YAMADA  wrote:
> Hi Simon,
>
>
>
>>
>> diff --git a/Kconfig b/Kconfig
>> index 153ee2b..d4ca152 100644
>> --- a/Kconfig
>> +++ b/Kconfig
>> @@ -158,3 +158,5 @@ source "drivers/Kconfig"
>>  source "fs/Kconfig"
>>
>>  source "lib/Kconfig"
>> +
>> +source "test/dm/Kconfig"
>
> Perhaps we might want "test/Kconfig" in the future.
>
>
>
>
>
>> --- a/arch/arm/cpu/armv7/tegra-common/Kconfig
>> +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig
>> @@ -20,6 +20,27 @@ endchoice
>>  config USE_PRIVATE_LIBGCC
>> default y if SPL_BUILD
>>
>> +config DM
>> +   default y
>> +
>> +config SPL_DM
>> +   default y
>> +
>> +config DM_SERIAL
>> +   default y
>> +
>> +config DM_SPI
>> +   default y
>> +
>> +config DM_SPI_FLASH
>> +   default y
>> +
>> +config DM_I2C
>> +   default y
>> +
>> +config DM_GPIO
>> +   default y
>> +
>
>
> Are all of these user-configurable?
>
> I mean, do Tegra boards work fine without CONFIG_DM_* ?
> I doubt it because you have already converted Tegra drivers.
>
>
> - Use "select" if the option is mandatory for that board
>
> - Use "default y" if the option is still optional, but recommended.
>
>

OK will change this for tegra.

>
>
>
>
>
>>  source "arch/arm/cpu/armv7/tegra20/Kconfig"
>>  source "arch/arm/cpu/armv7/tegra30/Kconfig"
>>  source "arch/arm/cpu/armv7/tegra114/Kconfig"
>> diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
>> index 3057325..1b4cbce 100644
>> --- a/arch/sandbox/Kconfig
>> +++ b/arch/sandbox/Kconfig
>> @@ -10,4 +10,43 @@ config SYS_BOARD
>>  config SYS_CONFIG_NAME
>> default "sandbox"
>>
>> +config DM
>> +   default y
>> +
>> +config DM_GPIO
>> +   default y
>> +
>> +config DM_SERIAL
>> +   default y
>> +
>> +config CMD_DEMO
>> +   default y
>> +
>> +config CMD_DM
>> +   default y
>> +
>> +config DM_DEMO
>> +   default y
>> +
>> +config DM_DEMO_SIMPLE
>> +   default y
>> +
>> +config DM_DEMO_SHAPE
>> +   default y
>> +
>> +config DM_TEST
>> +   default y
>> +
>> +config DM_CROS_EC
>> +   default y
>> +
>> +config DM_SPI
>> +   default y
>> +
>> +config DM_SPI_FLASH
>> +   default y
>> +
>> +config DM_I2C
>> +   default y
>> +
>
>
> Why do you like this syntax?
>
>  - If the option is not user-configurable, use "select"
>  - If the option is user-configurable and you want change the default value,
>add it to configs/sandbox_defconfig
>
>

OK I'll split these into two types.

>
>
>
>
>
>> diff --git a/board/samsung/goni/Kconfig b/board/samsung/goni/Kconfig
>> index cbbf5a9..006e864 100644
>> --- a/board/samsung/goni/Kconfig
>> +++ b/board/samsung/goni/Kconfig
>> @@ -12,4 +12,13 @@ config SYS_SOC
>>  config SYS_CONFIG_NAME
>> default "s5p_goni"
>>
>> +config DM
>> +   default y
>> +
>> +config DM_GPIO
>> +   default y
>> +
>> +config DM_SERIAL
>> +   default y
>> +
>
>
> "select" or "_defconfig"
>

Will go with select here.

>
>
>> diff --git a/common/Kconfig b/common/Kconfig
>> index fd84fa0..174bf4f 100644
>> --- a/common/Kconfig
>> +++ b/common/Kconfig
>> @@ -153,6 +153,29 @@ endmenu
>>
>>  menu "Device access commands"
>>
>> +config CMD_DM
>> +   bool "dm - Access to driver model information"
>> +   depends on DM
>> +   default y
>> +   help
>> + Provides access to driver model data structures and information,
>> + such as a list of devices, list of uclasses and the state of each
>> + device (e.g. activated). This is not required for operation, but
>> + can be useful to see the state of driver model for debugging or
>> + interest.
>> +
>> +config CMD_DEMO
>> +   bool "demo - Demonstration commands for driver model"
>> +   depends on DM
>> +   help
>> + Procides a 'demo' command which can be used to play around with
>> + driver model. To use this properly you will need to enable one or
>> + both of the demo devices (DM_DEMO_SHAPE and DM_DEMO_SIMPLE).
>> + Otherwise you will always get an empty list of devices. The demo
>> + devices are defined in the sandbox device tree, so the easiest
>> + option is to use sandbox and pass the -d point to sandbox's
>> + u-boot.dtb file.
>> +
>
>
> These seems rather "Misc commands".
>

They are driver-model-related though.

>
>
>>  config CMD_LOADB
>> bool "loadb"
>> help
>> diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig 
>> b/configs/Linksprite_pcDuino3_fdt_defconfig
>> index a33f3a7..931b5dd 100644
>> --- a/configs/Linksprite_pcDuino3_fdt_defconfig
>> +++ b/configs/Linksprite_pcDuino3_fdt_defconfig
>> @@ -2,6 +2,8 @@ CONFIG_SPL=y
>>  
>> CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
>>  CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
>>  CONFIG_DM=y
>> +CONFIG_DM_GPIO=y
>> +CONFIG_DM_SERIAL=y
>>  CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
>>  CONFIG_OF_CONTROL=y
>>  CONFIG_OF_SEPARATE=

Re: [U-Boot] [PATCH] x86: Simplify the fsp hob access functions

On 31 December 2014 at 01:22, Bin Meng  wrote:
> Hi Simon,
>
> On Wed, Dec 31, 2014 at 7:02 AM, Simon Glass  wrote:
>> Hi Bin,
>>
>> On 30 December 2014 at 01:02, Bin Meng  wrote:
>>> Remove the troublesome union hob_pointers so that some annoying casts
>>> are no longer needed in those hob access routines. This also improves
>>> the readability.
>>>
>>> Signed-off-by: Bin Meng 
>>> ---
>>>
>>>  arch/x86/cpu/queensbay/fsp_support.c   | 95 
>>> --
>>>  arch/x86/cpu/queensbay/tnc_dram.c  | 39 +
>>>  arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h  | 46 ---
>>>  .../include/asm/arch-queensbay/fsp/fsp_support.h   |  5 +-
>>>  arch/x86/lib/cmd_hob.c | 16 ++--
>>>  5 files changed, 101 insertions(+), 100 deletions(-)
>>>
>>
>> Yes a big improvement - see a few additional ideas for a follow-on patch 
>> below.
>>
>> Acked-by: Simon Glass 

Applied to u-boot-x86/next, thanks!
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[U-Boot] [PATCH 10/12] dt: socfpga: Import and enable Arria V DK DTS

Import DTS for Arria V development kit and enable support
for DT. The DT is imported from Linux 3.19-rc1 as of commit
97bf6af1f928216fd6c5a66e8a57bfa95a659672 .

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/socfpga_arria5.dtsi  | 34 
 arch/arm/dts/socfpga_arria5_socdk.dts | 74 +++
 configs/socfpga_arria5_defconfig  |  2 +
 4 files changed, 111 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria5.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c851d65..2a84323 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -49,6 +49,7 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
 dtb-$(CONFIG_SOCFPGA) +=   \
+   socfpga_arria5_socdk.dtb\
socfpga_cyclone5_socdk.dtb  \
socfpga_cyclone5_socrates.dtb
 
diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi
new file mode 100644
index 000..5175f03
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria5.dtsi
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x 0x0001000;
+#include "socfpga.dtsi"
+
+/ {
+   soc {
+   clkmgr@ffd04000 {
+   clocks {
+   osc1 {
+   clock-frequency = <2500>;
+   };
+   };
+   };
+
+   mmc0: dwmmc0@ff704000 {
+   num-slots = <1>;
+   broken-cd;
+   bus-width = <4>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   };
+
+   sysmgr@ffd08000 {
+   cpu1-start-addr = <0xffd080c4>;
+   };
+   };
+};
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts 
b/arch/arm/dts/socfpga_arria5_socdk.dts
new file mode 100644
index 000..4e529a1
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -0,0 +1,74 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "socfpga_arria5.dtsi"
+
+/ {
+   model = "Altera SOCFPGA Arria V SoC Development Kit";
+   compatible = "altr,socfpga-arria5", "altr,socfpga";
+
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   aliases {
+   /* this allow the ethaddr uboot environmnet variable contents
+   * to be added to the gmac1 device tree blob.
+   */
+   ethernet0 = &gmac1;
+   };
+
+   regulator_3_3v: 3-3-v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+};
+
+&gmac1 {
+   status = "okay";
+   phy-mode = "rgmii";
+
+   rxd0-skew-ps = <0>;
+   rxd1-skew-ps = <0>;
+   rxd2-skew-ps = <0>;
+   rxd3-skew-ps = <0>;
+   txen-skew-ps = <0>;
+   txc-skew-ps = <2600>;
+   rxdv-skew-ps = <0>;
+   rxc-skew-ps = <2000>;
+};
+
+&i2c0 {
+   status = "okay";
+
+   eeprom@51 {
+   compatible = "atmel,24c32";
+   reg = <0x51>;
+   pagesize = <32>;
+   };
+
+   rtc@68 {
+   compatible = "dallas,ds1339";
+   reg = <0x68>;
+   };
+};
+
+&mmc0 {
+   vmmc-supply = <®ulator_3_3v>;
+   vqmmc-supply = <®ulator_3_3v>;
+};
+
+&usb1 {
+   status = "okay";
+};
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index f290042..f152e9d 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SOCFPGA_ARRIA5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
-- 
2.1.3

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[U-Boot] [PATCH 09/12] dt: socfpga: Import and enable Cyclone V DK DTS

Import DTS for Cyclone V development kit and enable support
for DT. The DT is imported from Linux 3.19-rc1 as of commit
97bf6af1f928216fd6c5a66e8a57bfa95a659672 .

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 arch/arm/dts/Makefile   |  4 +-
 arch/arm/dts/socfpga_cyclone5_socdk.dts | 79 +
 configs/socfpga_cyclone5_defconfig  |  2 +
 3 files changed, 84 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e6a495c..c851d65 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -48,7 +48,9 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc770-xm013.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
-dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb
+dtb-$(CONFIG_SOCFPGA) +=   \
+   socfpga_cyclone5_socdk.dtb  \
+   socfpga_cyclone5_socrates.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts 
b/arch/arm/dts/socfpga_cyclone5_socdk.dts
new file mode 100644
index 000..8e1f88c
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -0,0 +1,79 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+   model = "Altera SOCFPGA Cyclone V SoC Development Kit";
+   compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   aliases {
+   /* this allow the ethaddr uboot environmnet variable contents
+* to be added to the gmac1 device tree blob.
+*/
+   ethernet0 = &gmac1;
+   };
+
+   regulator_3_3v: 3-3-v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+};
+
+&gmac1 {
+   status = "okay";
+   phy-mode = "rgmii";
+
+   rxd0-skew-ps = <0>;
+   rxd1-skew-ps = <0>;
+   rxd2-skew-ps = <0>;
+   rxd3-skew-ps = <0>;
+   txen-skew-ps = <0>;
+   txc-skew-ps = <2600>;
+   rxdv-skew-ps = <0>;
+   rxc-skew-ps = <2000>;
+};
+
+&gpio1 {
+   status = "okay";
+};
+
+&i2c0 {
+   status = "okay";
+
+   eeprom@51 {
+   compatible = "atmel,24c32";
+   reg = <0x51>;
+   pagesize = <32>;
+   };
+
+   rtc@68 {
+   compatible = "dallas,ds1339";
+   reg = <0x68>;
+   };
+};
+
+&mmc0 {
+   cd-gpios = <&portb 18 0>;
+   vmmc-supply = <®ulator_3_3v>;
+   vqmmc-supply = <®ulator_3_3v>;
+};
+
+&usb1 {
+   status = "okay";
+};
diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index 4b2ede4..2d3dd47 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
-- 
2.1.3

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[U-Boot] [PATCH 12/12] arm: socfpga: Zap board_early_init_f()

Zap this unused empty function, no point in having it.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 board/altera/socfpga/socfpga.c   | 8 
 include/configs/socfpga_common.h | 1 -
 2 files changed, 9 deletions(-)

diff --git a/board/altera/socfpga/socfpga.c b/board/altera/socfpga/socfpga.c
index 2b2b63d..20d2216 100644
--- a/board/altera/socfpga/socfpga.c
+++ b/board/altera/socfpga/socfpga.c
@@ -19,14 +19,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
- * Initialization function which happen at early stage of c code
- */
-int board_early_init_f(void)
-{
-   return 0;
-}
-
-/*
  * Miscellaneous platform dependent initialisations
  */
 int board_init(void)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c2a4c72..5254e9b 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -20,7 +20,6 @@
  */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_CLOCKS
-- 
2.1.3

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[U-Boot] [PATCH 08/12] dt: socfpga: Replace num-chipselect with num-cs

This optional DT property is called 'num-cs', so repair the misnomers.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 arch/arm/dts/socfpga.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 93d3776..bf791c5 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -637,7 +637,7 @@
interrupts = <0 151 4>;
clocks = <&qspi_clk>;
ext-decoder = <0>;  /* external decoder */
-   num-chipselect = <4>;
+   num-cs = <4>;
fifo-depth = <128>;
bus-num = <2>;
status = "disabled";
@@ -649,7 +649,7 @@
#size-cells = <0>;
reg = <0xfff0 0x1000>;
interrupts = <0 154 4>;
-   num-chipselect = <4>;
+   num-cs = <4>;
bus-num = <0>;
tx-dma-channel = <&pdma 16>;
rx-dma-channel = <&pdma 17>;
@@ -663,7 +663,7 @@
#size-cells = <0>;
reg = <0xfff01000 0x1000>;
interrupts = <0 156 4>;
-   num-chipselect = <4>;
+   num-cs = <4>;
bus-num = <1>;
tx-dma-channel = <&pdma 20>;
rx-dma-channel = <&pdma 21>;
-- 
2.1.3

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[U-Boot] [PATCH 07/12] dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi

Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.
Fix the naming before we have to support both names.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 arch/arm/dts/socfpga.dtsi| 4 ++--
 drivers/spi/designware_spi.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 969e5ad..93d3776 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -644,7 +644,7 @@
};
 
spi0: spi@fff0 {
-   compatible = "snps,dw-spi-mmio";
+   compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff0 0x1000>;
@@ -658,7 +658,7 @@
};
 
spi1: spi@fff01000 {
-   compatible = "snps,dw-spi-mmio";
+   compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff01000 0x1000>;
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 98c9f03..a42c0af 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -409,7 +409,7 @@ static const struct dm_spi_ops dw_spi_ops = {
 };
 
 static const struct udevice_id dw_spi_ids[] = {
-   { .compatible = "snps,dw-spi-mmio" },
+   { .compatible = "snps,dw-apb-ssi" },
{ }
 };
 
-- 
2.1.3

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[U-Boot] [PATCH 11/12] arm: socfpga: Zap checkboard()

Since all boards now have a DT, instead of hard-coding the board
name into the U-Boot binary, read the board name from DT "model"
property.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 board/altera/socfpga/socfpga.c   | 16 
 include/configs/socfpga_common.h |  2 +-
 2 files changed, 1 insertion(+), 17 deletions(-)

diff --git a/board/altera/socfpga/socfpga.c b/board/altera/socfpga/socfpga.c
index a9c330d..2b2b63d 100644
--- a/board/altera/socfpga/socfpga.c
+++ b/board/altera/socfpga/socfpga.c
@@ -19,22 +19,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
- * Print Board information
- */
-int checkboard(void)
-{
-#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
-   puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
-#endif
-
-#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
-   puts("BOARD: Altera SoCFPGA Arria5 Board\n");
-#endif
-
-   return 0;
-}
-
-/*
  * Initialization function which happen at early stage of c code
  */
 int board_early_init_f(void)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 6b1f967..c2a4c72 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -19,7 +19,7 @@
  * High level configuration
  */
 #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_SYS_NO_FLASH
-- 
2.1.3

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[U-Boot] [PATCH 05/12] arm: socfpga: Drop cyclone5 suffix from board file name

Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file
will contain Arria 5 support as well.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 board/altera/socfpga/Makefile  | 2 +-
 board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (100%)

diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile
index 44baa00..c867f73 100644
--- a/board/altera/socfpga/Makefile
+++ b/board/altera/socfpga/Makefile
@@ -6,5 +6,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  := socfpga_cyclone5.o
+obj-y  := socfpga.o
 obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o
diff --git a/board/altera/socfpga/socfpga_cyclone5.c 
b/board/altera/socfpga/socfpga.c
similarity index 100%
rename from board/altera/socfpga/socfpga_cyclone5.c
rename to board/altera/socfpga/socfpga.c
-- 
2.1.3

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[U-Boot] [PATCH 01/12] arm: socfpga: Minor coding style fix

Replace multiple spaces with a single tab.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 board/altera/socfpga/iocsr_config.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/altera/socfpga/iocsr_config.h 
b/board/altera/socfpga/iocsr_config.h
index 490f109..4a7ed46 100644
--- a/board/altera/socfpga/iocsr_config.h
+++ b/board/altera/socfpga/iocsr_config.h
@@ -9,9 +9,9 @@
 #ifndef _PRELOADER_IOCSR_CONFIG_H_
 #define _PRELOADER_IOCSR_CONFIG_H_
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH(764)
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH(1719)
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH(955)
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH(16766)
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
 
 #endif /*_PRELOADER_IOCSR_CONFIG_H_*/
-- 
2.1.3

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[U-Boot] [PATCH 06/12] arm: socfpga: Add Altera Arria V DK support

Add support for the Altera Arria V development kit.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 arch/arm/Kconfig |   5 +
 board/altera/socfpga/Kconfig |  16 +
 board/altera/socfpga/iocsr_config.c  | 688 +++
 board/altera/socfpga/iocsr_config.h  |   9 +
 board/altera/socfpga/pinmux_config.c | 215 +++
 board/altera/socfpga/socfpga.c   |   7 +
 configs/socfpga_arria5_defconfig |   3 +
 include/configs/socfpga_arria5.h | 107 ++
 8 files changed, 1050 insertions(+)
 create mode 100644 configs/socfpga_arria5_defconfig
 create mode 100644 include/configs/socfpga_arria5.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5eb1d03..0a04cca 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -687,6 +687,11 @@ config TARGET_CM_FX6
select CPU_V7
select SUPPORT_SPL
 
+config TARGET_SOCFPGA_ARRIA5
+   bool "Support socfpga_arria5"
+   select CPU_V7
+   select SUPPORT_SPL
+
 config TARGET_SOCFPGA_CYCLONE5
bool "Support socfpga_cyclone5"
select CPU_V7
diff --git a/board/altera/socfpga/Kconfig b/board/altera/socfpga/Kconfig
index fc42185..cbed8d6 100644
--- a/board/altera/socfpga/Kconfig
+++ b/board/altera/socfpga/Kconfig
@@ -13,3 +13,19 @@ config SYS_CONFIG_NAME
default "socfpga_cyclone5"
 
 endif
+
+if TARGET_SOCFPGA_ARRIA5
+
+config SYS_BOARD
+   default "socfpga"
+
+config SYS_VENDOR
+   default "altera"
+
+config SYS_SOC
+   default "socfpga"
+
+config SYS_CONFIG_NAME
+   default "socfpga_arria5"
+
+endif
diff --git a/board/altera/socfpga/iocsr_config.c 
b/board/altera/socfpga/iocsr_config.c
index b4b5ff8..c79aa6d 100644
--- a/board/altera/socfpga/iocsr_config.c
+++ b/board/altera/socfpga/iocsr_config.c
@@ -8,6 +8,7 @@
 
 #include 
 
+#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
 const unsigned long iocsr_scan_chain0_table[((
CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x,
@@ -655,3 +656,690 @@ const unsigned long iocsr_scan_chain3_table[((
0x001F,
0x4100,
 };
+#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
+const unsigned long iocsr_scan_chain0_table[((
+   CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+   0x,
+   0x,
+   0x,
+   0x,
+   0x,
+   0x8000,
+   0x00060180,
+   0x1806,
+   0x1860,
+   0x00018060,
+   0x06018060,
+   0x4000,
+   0x0C0300C0,
+   0x0C03,
+   0x0030,
+   0x,
+   0x,
+   0x2000,
+   0x,
+   0x,
+   0x0600,
+   0x6018,
+   0x01806018,
+   0x1000,
+   0xC030,
+   0x0400,
+   0x0300,
+   0x300C,
+   0x,
+   0x0800,
+   0x6018,
+   0x01806000,
+   0x0180,
+   0x0006,
+   0x1806,
+   0x0400,
+   0x300C,
+   0x00C03000,
+   0x00C0,
+   0x0003,
+   0x0C03,
+   0x0200,
+};
+
+const unsigned long iocsr_scan_chain1_table[((
+   CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+   0x0010,
+   0x300C,
+   0x30C0,
+   0x00C0,
+   0x000300C0,
+   0x8000,
+   0x00060180,
+   0x1806,
+   0x1800,
+   0x0060,
+   0x00018060,
+   0x4000,
+   0x000300C0,
+   0x1000,
+   0x0C00,
+   0x0030,
+   0xC030,
+   0x2000,
+   0x06018060,
+   0x06018000,
+   0x01FE,
+   0xF800,
+   0x0007,
+   0x1000,
+   0xC030,
+   0x0300C000,
+   0x0300,
+   0x300C,
+   0x300C,
+   0x0800,
+   0x6018,
+   0x01806000,
+   0x0180,
+   0x0006,
+   0x2000,
+   0x0400,
+   0x300C,
+   0x0100,
+   0x,
+   0x0004,
+   0x0C03,
+   0x0200,
+   0x1806,
+   0x0080,
+   0x,
+   0x0002,
+   0x0800,
+   0x0100,
+   0x1000,
+   0x0040,
+   0xC030,
+   0x,
+   0x0400,
+   0x0080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((
+   CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+   0x0010,
+   0x4000,
+   0x,
+   0x0100,
+   0x0004,
+   0x8000,
+   0x18060180,
+   0x2000,
+   0x,
+   0x0080,
+   0x0002,
+   0x4000,
+   0x0004,
+   0x1000,
+   0x,
+   0x,
+   0x0001,
+   0x2000,
+   0x10038060,
+   0x,
+   0x,
+   0x0020,
+   0x01806018,
+   0x1000,
+   0

[U-Boot] [PATCH 03/12] arm: socfpga: Sync Cyclone V DK PLL configuration

Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at
  which point this will likely need further rework.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 board/altera/socfpga/pll_config.h | 34 +++---
 1 file changed, 11 insertions(+), 23 deletions(-)

diff --git a/board/altera/socfpga/pll_config.h 
b/board/altera/socfpga/pll_config.h
index f0f59a9..8130fa4 100644
--- a/board/altera/socfpga/pll_config.h
+++ b/board/altera/socfpga/pll_config.h
@@ -16,9 +16,9 @@
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT   (0)
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT  (0)
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT  (3)
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3)
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT   (12)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT  (511)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT   (15)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK  (1)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK  (1)
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK  (1)
@@ -36,7 +36,7 @@
 
 /* Peripheral PLL */
 #define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)
 /*
  * To tell where is the VCOs source:
  * 0 = EOSC1
@@ -45,13 +45,13 @@
  */
 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC  (0)
 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT  (3)
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT  (3)
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT(1)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT  (511)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT(511)
 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT   (4)
 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT(4)
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT   (9)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT   (511)
 #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK(0)
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK   (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK   (4)
 #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK   (1)
 #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK   (1)
 #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
@@ -66,15 +66,8 @@
 #define CONFIG_HPS_PERPLLGRP_SRC_QSPI  (1)
 
 /* SDRAM PLL */
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
- * This if..else... is not required if generated by tools */
 #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127)
-#else
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79)
 
 /*
  * To tell where is the VCOs source:
@@ -94,17 +87,12 @@
 
 /* Info for driver */
 #define CONFIG_HPS_CLK_OSC1_HZ (2500)
-#define CONFIG_HPS_CLK_OSC2_HZ 0
+#define CONFIG_HPS_CLK_OSC2_HZ (2500)
 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ  0
 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ  0
 #define CONFIG_HPS_CLK_MAINVCO_HZ  (16)
 #define CONFIG_HPS_CLK_PERVCO_HZ   (10)
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define CONFIG_HPS_CLK_SDRVCO_HZ   (106600)
-#else
-#define CONFIG_HPS_CLK_SDRVCO_HZ   (8)
-#endif
+#define CONFIG_HPS_CLK_SDRVCO_HZ   (6)
 #define CONFIG_HPS_CLK_EMAC0_HZ(25000)
 #define CONFIG_HPS_CLK_EMAC1_HZ(25000)
 #define CONFIG_HPS_CLK_USBCLK_HZ   (2)
-- 
2.1.3

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[U-Boot] [PATCH 00/12] arm: socfpga: Arria V support and fixes

This series brings in a couple of minor fixes (mostly coding
style and sync with rocketboards u-boot) and improvements
(USB UMS and DFU support for Cyclone V SoC DK). There are
also fixes for DT properties in this series to make those
compatible with Linux.

This series also adds Arria V SoC DK support. By adding the
Arria V support, the pieces of code which are specific to a
particular CPU model are now clearly isolated by an #ifdef.
These #ifdef mark code which should be easy to dissolve and
migrate into DT in the next step.

While at this, the SoCFPGA platform is made dependent on having
a proper Device Tree available (attached at the end of U-Boot
binary). The board name is no longer hard-coded into the U-Boot
binary, but is instead extracted from the DT ; this is the first
step toward moving to DT altogether. At this point, no new SoCFPGA
platform without DT is accepted anymore.

Note: The DT files imported in this series come from Linux 3.18
  mainline.

Marek Vasut (12):
  arm: socfpga: Minor coding style fix
  arm: socfpga: Sync Cyclone V DK pinmux configuration
  arm: socfpga: Sync Cyclone V DK PLL configuration
  arm: socfpga: Add USB and UDC support for Cyclone V DK
  arm: socfpga: Drop cyclone5 suffix from board file name
  arm: socfpga: Add Altera Arria V DK support
  dt: socfpga: Rename snps,dw-spi-mmio to snps,dw-apb-ssi
  dt: socfpga: Replace num-chipselect with num-cs
  dt: socfpga: Import and enable Cyclone V DK DTS
  dt: socfpga: Import and enable Arria V DK DTS
  arm: socfpga: Zap checkboard()
  arm: socfpga: Zap board_early_init_f()

 arch/arm/Kconfig   |   5 +
 arch/arm/dts/Makefile  |   5 +-
 arch/arm/dts/socfpga.dtsi  |  10 +-
 arch/arm/dts/socfpga_arria5.dtsi   |  34 +
 arch/arm/dts/socfpga_arria5_socdk.dts  |  74 +++
 arch/arm/dts/socfpga_cyclone5_socdk.dts|  79 +++
 board/altera/socfpga/Kconfig   |  16 +
 board/altera/socfpga/Makefile  |   2 +-
 board/altera/socfpga/iocsr_config.c| 688 +
 board/altera/socfpga/iocsr_config.h|  17 +-
 board/altera/socfpga/pinmux_config.c   | 403 +---
 board/altera/socfpga/pinmux_config.h   |  14 +-
 board/altera/socfpga/pll_config.h  |  34 +-
 .../socfpga/{socfpga_cyclone5.c => socfpga.c}  |  17 -
 configs/socfpga_arria5_defconfig   |   5 +
 configs/socfpga_cyclone5_defconfig |   2 +
 drivers/spi/designware_spi.c   |   2 +-
 include/configs/socfpga_arria5.h   | 107 
 include/configs/socfpga_common.h   |   3 +-
 include/configs/socfpga_cyclone5.h |   9 +
 20 files changed, 1371 insertions(+), 155 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria5.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts
 create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts
 rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (86%)
 create mode 100644 configs/socfpga_arria5_defconfig
 create mode 100644 include/configs/socfpga_arria5.h

Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 

-- 
2.1.3

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[U-Boot] [PATCH 02/12] arm: socfpga: Sync Cyclone V DK pinmux configuration

Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 board/altera/socfpga/pinmux_config.c | 188 +--
 board/altera/socfpga/pinmux_config.h |  14 +--
 2 files changed, 101 insertions(+), 101 deletions(-)

diff --git a/board/altera/socfpga/pinmux_config.c 
b/board/altera/socfpga/pinmux_config.c
index 8b09005..b124768 100644
--- a/board/altera/socfpga/pinmux_config.c
+++ b/board/altera/socfpga/pinmux_config.c
@@ -4,100 +4,100 @@
 
 /* pin mux configuration data */
 unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
-   0, /* EMACIO0 - Unused */
-   2, /* EMACIO1 - USB */
-   2, /* EMACIO2 - USB */
-   2, /* EMACIO3 - USB */
-   2, /* EMACIO4 - USB */
-   2, /* EMACIO5 - USB */
-   2, /* EMACIO6 - USB */
-   2, /* EMACIO7 - USB */
-   2, /* EMACIO8 - USB */
-   0, /* EMACIO9 - Unused */
-   2, /* EMACIO10 - USB */
-   2, /* EMACIO11 - USB */
-   2, /* EMACIO12 - USB */
-   2, /* EMACIO13 - USB */
-   0, /* EMACIO14 - N/A */
-   0, /* EMACIO15 - N/A */
-   0, /* EMACIO16 - N/A */
-   0, /* EMACIO17 - N/A */
-   0, /* EMACIO18 - N/A */
-   0, /* EMACIO19 - N/A */
-   3, /* FLASHIO0 - SDMMC */
-   3, /* FLASHIO1 - SDMMC */
-   3, /* FLASHIO2 - SDMMC */
-   3, /* FLASHIO3 - SDMMC */
-   0, /* FLASHIO4 - SDMMC */
-   0, /* FLASHIO5 - SDMMC */
-   0, /* FLASHIO6 - SDMMC */
-   0, /* FLASHIO7 - SDMMC */
-   0, /* FLASHIO8 - SDMMC */
-   3, /* FLASHIO9 - SDMMC */
-   3, /* FLASHIO10 - SDMMC */
-   3, /* FLASHIO11 - SDMMC */
-   3, /* GENERALIO0 - TRACE */
-   3, /* GENERALIO1 - TRACE */
-   3, /* GENERALIO2 - TRACE */
-   3, /* GENERALIO3 - TRACE  */
-   3, /* GENERALIO4 - TRACE  */
-   3, /* GENERALIO5 - TRACE  */
-   3, /* GENERALIO6 - TRACE  */
-   3, /* GENERALIO7 - TRACE  */
-   3, /* GENERALIO8 - TRACE  */
-   3, /* GENERALIO9 - SPIM0 */
-   3, /* GENERALIO10 - SPIM0 */
-   3, /* GENERALIO11 - SPIM0 */
-   3, /* GENERALIO12 - SPIM0 */
-   2, /* GENERALIO13 - CAN0 */
-   2, /* GENERALIO14 - CAN0 */
-   3, /* GENERALIO15 - I2C0 */
-   3, /* GENERALIO16 - I2C0 */
-   2, /* GENERALIO17 - UART0 */
-   2, /* GENERALIO18 - UART0 */
-   0, /* GENERALIO19 - N/A */
-   0, /* GENERALIO20 - N/A */
-   0, /* GENERALIO21 - N/A */
-   0, /* GENERALIO22 - N/A */
-   0, /* GENERALIO23 - N/A */
-   0, /* GENERALIO24 - N/A */
-   0, /* GENERALIO25 - N/A */
-   0, /* GENERALIO26 - N/A */
-   0, /* GENERALIO27 - N/A */
-   0, /* GENERALIO28 - N/A */
-   0, /* GENERALIO29 - N/A */
-   0, /* GENERALIO30 - N/A */
-   0, /* GENERALIO31 - N/A */
-   2, /* MIXED1IO0 - EMAC */
-   2, /* MIXED1IO1 - EMAC */
-   2, /* MIXED1IO2 - EMAC */
-   2, /* MIXED1IO3 - EMAC */
-   2, /* MIXED1IO4 - EMAC */
-   2, /* MIXED1IO5 - EMAC */
-   2, /* MIXED1IO6 - EMAC */
-   2, /* MIXED1IO7 - EMAC */
-   2, /* MIXED1IO8 - EMAC */
-   2, /* MIXED1IO9 - EMAC */
-   2, /* MIXED1IO10 - EMAC */
-   2, /* MIXED1IO11 - EMAC */
-   2, /* MIXED1IO12 - EMAC */
-   2, /* MIXED1IO13 - EMAC */
-   0, /* MIXED1IO14 - Unused */
-   3, /* MIXED1IO15 - QSPI */
-   3, /* MIXED1IO16 - QSPI */
-   3, /* MIXED1IO17 - QSPI */
-   3, /* MIXED1IO18 - QSPI */
-   3, /* MIXED1IO19 - QSPI */
-   3, /* MIXED1IO20 - QSPI */
-   0, /* MIXED1IO21 - GPIO */
-   0, /* MIXED2IO0 - N/A */
-   0, /* MIXED2IO1 - N/A */
-   0, /* MIXED2IO2 - N/A */
-   0, /* MIXED2IO3 - N/A */
-   0, /* MIXED2IO4 - N/A */
-   0, /* MIXED2IO5 - N/A */
-   0, /* MIXED2IO6 - N/A */
-   0, /* MIXED2IO7 - N/A */
+   3, /* EMACIO0 */
+   3, /* EMACIO1 */
+   3, /* EMACIO2 */
+   3, /* EMACIO3 */
+   3, /* EMACIO4 */
+   3, /* EMACIO5 */
+   3, /* EMACIO6 */
+   3, /* EMACIO7 */
+   3, /* EMACIO8 */
+   3, /* EMACIO9 */
+   3, /* EMACIO10 */
+   3, /* EMACIO11 */
+   3, /* EMACIO12 */
+   3, /* EMACIO13 */
+   0, /* EMACIO14 */
+   0, /* EMACIO15 */
+   0, /* EMACIO16 */
+   0, /* EMACIO17 */
+   0, /* EMACIO18 */
+   0, /* EMACIO19 */
+   3, /* FLASHIO0 */
+   0, /* FLASHIO1 */
+   3, /* FLASHIO2 */
+   3, /* FLASHIO3 */
+   3, /* FLASHIO4 */
+   3, /* FLASHIO5 */
+   3, /* FLASHIO6 */
+   3, /* FLASHIO7 */
+   0, /* FLASHIO8 */
+   3, /* FLASHIO9 */
+   3, /* FLASHIO10 */
+   3, /* FLASHIO11 */
+   0, /* GENERALIO0 */
+   1, /* GENERALIO1 */
+   1, /* GENERALIO2 */
+   0, /* GENERALIO3 */
+   0, /* GENERALIO4 */
+   1, /* GENERALIO5 */
+   1, /* GENERA

[U-Boot] [PATCH 04/12] arm: socfpga: Add USB and UDC support for Cyclone V DK

Add support for USB host mode and USB device mode for the
Cyclone V development kit and enable support for UMS (to
export SD card as USB mass storage). The UMS is activated
via 'ums 0 mmc 0' command, the system must be connected to
a host PC via HPS USB port and SD card must be installed
for this to work.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
---
 include/configs/socfpga_cyclone5.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/include/configs/socfpga_cyclone5.h 
b/include/configs/socfpga_cyclone5.h
index c3d958c..676144a 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -21,6 +21,7 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
@@ -33,6 +34,8 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
 
 #define CONFIG_REGEX   /* Enable regular expression support */
 
@@ -66,6 +69,12 @@
 
 #endif
 
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR   SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER  "Altera"
+
 /* Extra Environment */
 #define CONFIG_HOSTNAMEsocfpga_cyclone5
 
-- 
2.1.3

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Re: [U-Boot] Make "usb start" only start / scan usb once ?

On Wednesday, November 26, 2014 at 01:44:23 PM, Hans de Goede wrote:
> Hi,

Hello Hans,

> Currently we've this magic in include/config_distro_bootcmd.h to avoid
> scanning the usb bus multiple times.
> 
> And it does not work when also using an usb keyboard because then the
> preboot command has already scanned the bus, so we're still scanning it
> twice.
> 
> While discussing my latest attempt at fixing this:
> 
> http://patchwork.ozlabs.org/patch/413394/
> http://patchwork.ozlabs.org/patch/413395/
> 
> With Ian, Ian said why not simply make "usb start" keep track of if it
> already has started things, and then we can remove all the magic for it
> from include/config_distro_bootcmd.h and just call it unconditionally.
> 
> This would also cause "usb start" and "usb reset" to actually do something
> different, where as currently they are 100% the same.
> 
> I must say I like this idea, the only downside is, that it could be seen
> as a break of the u-boot cmdline API, one could easily argue it is not,
> because usb will be started by "usb start" if necessary, and people can
> still force a rescan with "usb reset".
> 
> So any input on this, specifically would a patch-set to make "usb start"
> start usb only once (per boot) be acceptable ?

It just makes a lot of sense, so yes. You're right it'd break the command
like API and it might be a surprise to some, but you're also right that the
current "way of things" is confusing and possibly even wrong.

Apologies I got back to you so late.

Best regards,
Marek Vasut
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[U-Boot] [PULL] u-boot-usb/master

Looks like there're still two dangling patches, so let's make Rene happy
and apply them please.

Thanks!

The following changes since commit 125738e819a3b9d15210794b3dcef9f4d9bcf866:

  Prepare v2015.01-rc4 (2014-12-29 21:22:38 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-usb.git master

for you to fetch changes up to edd88905ae292355991f13fd0d3c7b3368103050:

  usb: eth: enable AX88179 DRIVER for ARNDALE 5250 (2014-12-31 19:10:13 +0100)


Rene Griessl (2):
  usb: eth: add ASIX AX88179 DRIVER
  usb: eth: enable AX88179 DRIVER for ARNDALE 5250

 drivers/usb/eth/Makefile|   1 +
 drivers/usb/eth/asix88179.c | 700 
++
 drivers/usb/eth/usb_ether.c |   7 ++
 include/configs/arndale.h   |   1 +
 include/usb_ether.h |   6 +
 5 files changed, 715 insertions(+)
 create mode 100644 drivers/usb/eth/asix88179.c
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Re: [U-Boot] coreboot uboot qemu x86

Hi Ajoy,

On 30 December 2014 at 22:28, Ajoy Das  wrote:
[snip]

>>> On Tue, Dec 30, 2014 at 4:17 AM, Simon Glass  wrote:

 Hi Ajoy,

 > On Mon, Dec 29, 2014 at 9:28 PM, Simon Glass  wrote:
 >
 >> Hi Ajoy,
 >>
 >>
 >> > On Mon, Dec 29, 2014 at 7:36 PM, Simon Glass 
 >> > wrote:
 >> >>
 >> >> Hi,
 >> >>
 >> >> On 28 December 2014 at 21:38, Ajoy Das 
 >> >> wrote:
 >> >> > Hi
 >> >> >
 >> >> > Need Help
 >> >> >
 >> >> > I want to run U-BOOT as coreboot payload on QEMU platform
 >> >> >
 >> >> > I am on uboot-x86 git
 >> >> >
 >> >> > Compiled U-BOOT with make coreboot-x86_defconfig and make all
 >> >> >
 >> >> > Running qemu with
 >> >> > qemu-system-i386 -bios ../coreboot/build/coreboot.rom -hda
 >> >> > disk.img
 >> >> > -nographic -m 1g
 >> >> >
 >> >> > But The system crashes with the following message
 >> >> >
 >> >> > qemu: fatal: Trying to execute code outside RAM or ROM at
 >> >> > 0x5e2a36c2
 >> >> >
 >> >> > Loading Segment: addr: 0x0111 memsz:
 >> >> > 0x000588e8
 >> >> > filesz:
 >> >> > 0x000252eb
 >> >> > lb: [0x0010, 0x0012b030)
 >> >> > Post relocation: addr: 0x0111 memsz:
 >> >> > 0x000588e8
 >> >> > filesz:
 >> >> > 0x000252eb
 >> >> > using LZMA
 >> >> > [ 0x0111, 011688e8, 0x011688e8) <- fffd2770
 >> >> > dest 0111, end 011688e8, bouncebuffer 3ff77000
 >> >> > Loaded segments
 >> >> > Jumping to boot code at 01110015
 >> >> > CPU0: stack: 00126000 - 00127000, lowest used address 00126b8c,
 >> >> > stack
 >> >> > used:
 >> >> > 1140 bytes
 >> >> > entry= 0x01110015
 >> >> > lb_start = 0x0010
 >> >> > lb_size  = 0x0002b030
 >> >> > buffer   = 0x3ff77000
 >> >> > qemu: fatal: Trying to execute code outside RAM or ROM at
 >> >> > 0x5e2a36c2
 >> >> >
 >> >> > EAX=000a EBX=000186a0 ECX=01145d15 EDX=19203eb0
 >> >> > ESI= EDI= EBP=01145f6c ESP=01145f54
 >> >> > EIP=5e2a36c2 EFL=0002 [---] CPL=0 II=0 A20=1 SMM=0 HLT=0
 >> >> > ES =0018   00cf9300 DPL=0 DS   [-WA]
 >> >> > CS =0010   00cf9b00 DPL=0 CS32 [-RA]
 >> >> > SS =0018   00cf9300 DPL=0 DS   [-WA]
 >> >> > DS =0018   00cf9300 DPL=0 DS   [-WA]
 >> >> > FS =0020 19203f5c  00cf9300 DPL=0 DS   [-WA]
 >> >> > GS =0018   00cf9300 DPL=0 DS   [-WA]
 >> >> > LDT=   8200 DPL=0 LDT
 >> >> > TR =   8b00 DPL=0 TSS32-busy
 >> >> > GDT= 19203e60 0047
 >> >> > IDT=  
 >> >> > CR0=6033 CR2= CR3= CR4=
 >> >> > DR0= DR1= DR2= DR3=
 >> >> > DR6=0ff0 DR7=0400
 >> >> > CCS=0218 CCD=01145f50 CCO=ADDL
 >> >> > EFER=
 >> >> > FCW=037f FSW= [ST=0] FTW=00 MXCSR=1f80
 >> >> > FPR0=  FPR1= 
 >> >> > FPR2=  FPR3= 
 >> >> > FPR4=  FPR5= 
 >> >> > FPR6=  FPR7= 
 >> >> > XMM00=
 >> >> > XMM01=
 >> >> > XMM02=
 >> >> > XMM03=
 >> >> > XMM04=
 >> >> > XMM05=
 >> >> > XMM06=
 >> >> > XMM07=
 >> >> > Aborted (core dumped)
 >> >> >
 >> >> > qemu-system-i386 --version
 >> >> > QEMU emulator version 1.0 (qemu-kvm-1.0), Copyright (c)
 >> >> > 2003-2008
 >> >> > Fabrice
 >> >> > Bellard
 >> >> >
 >> >> > Is QEMU not supported for coreboot and u-boot
 >> >>
 >> >> I'm not sure it's been tried but there's no reason why it should
 >> >> work.
 >> >> It seems to be crashing in U-Boot before there is any serial
 >> >> output.
 >> >> Did you put u-boot-dtb.bin as the payload?

 >> On 29 December 2014 at 07:34, Ajoy Das  wrote:
 >> > Hi Simon
 >> >
 >> > Thanks for your reply
 >> >
 >> > I have added u-boot ELF as the coreboot payload
 >> >
 >> > u-boot: ELF 32-bit LSB shared object, Intel 80386, version 1
 >> > (SYSV),
 >> > statically linked, not stripped.
 >> >
 >> > Got this link but its a year old.
 >> > http://lists.denx.de/pipermail/u-boot/2013-July/159140.html
 >> >
 >> > Thanks
 >> > Ajoy
 >> >
 >>
 [snip]
 >>
 >> I suggest using cbfstool add-flat-binary -f u-boot-dtb.bin -n
 >> fallback/payl

Re: [U-Boot] [PATCH v4 4/4] x86: crownbay: Add pci devices in the dts file

On 31 December 2014 at 11:20, Simon Glass  wrote:
> On 31 December 2014 at 01:05, Bin Meng  wrote:
>> The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
>> 1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
>> Open Firmware PCI bus bindings.
>>
>> Also a comment block is added for the 'stdout-path' property in the
>> chosen node, mentioning that by default the legacy superio serial
>> port (io addr 0x3f8) is still used on Crown Bay as the console port.
>>
>> Signed-off-by: Bin Meng 
>
> Acked-by: Simon Glass 
>
Applied to u-boot-x86/next, thanks!

>>
>> ---
>>
>> Changes in v4:
>> - Add , after pciclass in the pci compatible string per spec
>> - Drop the first 3 patches which are already applied
>>
>> Changes in v3: None
>> Changes in v2:
>> - New patch to add pci devices in crownbay.dts
>> - Drop v1 patch: Add an API for finding pci devices in the early phase
>> - Drop v1 patch: Support PCI UART in the x86_serial driver
>> - Drop v1 patch: Add PCI UART related defines in crownbay.h
>>
>>  arch/x86/dts/crownbay.dts | 81 
>> +++
>>  1 file changed, 81 insertions(+)
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Re: [U-Boot] [PATCH v4 3/4] x86: Use ePAPR defined properties for x86-uart

On 31 December 2014 at 01:05, Bin Meng  wrote:
> Use ePAPR defined properties for x86-uart: clock-frequency and
> current-speed. Assign the value of clock-frequency in device tree
> to plat->clock of x86-uart instead of using hardcoded number.
>
> Signed-off-by: Bin Meng 
> Acked-by: Simon Glass 
>
Applied to u-boot-x86/next, thanks!

> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - New patch to use ePAPR defined properties for x86-uart
>
>  arch/x86/dts/serial.dtsi| 5 ++---
>  drivers/serial/serial_x86.c | 8 +++-
>  2 files changed, 9 insertions(+), 4 deletions(-)
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Re: [U-Boot] [PATCH v4 2/4] serial: ns16550: Support ns16550 compatible pci uart devices

On 31 December 2014 at 01:05, Bin Meng  wrote:
> There are many pci uart devices which are ns16550 compatible. We can
> describe them in the board dts file and use it as the U-Boot serial
> console as specified in the chosen node 'stdout-path' property.
>
> Those pci uart devices can have their register be memory-mapped, or
> i/o-mapped. The driver will try to use the memory-mapped register if
> the reg property in the node has an entry to describe the memory-mapped
> register, otherwise i/o-mapped register will be used.
>
> Signed-off-by: Bin Meng 
> Acked-by: Simon Glass 

Applied to u-boot-x86/next, thanks!

>
> ---
>
> Changes in v4: None
> Changes in v3:
> - Update to use 'memory-mapped' and 'i/o-mapped' in several places
> - Use 'Processor Local Bus' instead of 'plb'
> - Change the logic in ns16550_serial_ofdata_to_platdata() to avoid goto
>
> Changes in v2:
> - New patch to support ns16550 compatible pci uart devices
>
>  drivers/serial/ns16550.c | 31 +++
>  1 file changed, 31 insertions(+)
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Re: [U-Boot] [PATCH v4 1/4] fdt: Add several apis to decode pci device node

On 31 December 2014 at 11:17, Simon Glass  wrote:
> On 31 December 2014 at 01:05, Bin Meng  wrote:
>> This commit adds several APIs to decode PCI device node according to
>> the Open Firmware PCI bus bindings, including:
>> - fdtdec_get_pci_addr() for encoded pci address
>> - fdtdec_get_pci_vendev() for vendor id and device id
>> - fdtdec_get_pci_bdf() for pci device bdf triplet
>> - fdtdec_get_pci_bar32() for pci device register bar
>>
>> Signed-off-by: Bin Meng 
>>
>> ---
>>
>> Changes in v4:
>> - Check compatible string 12th byte against '\0'
>
> Acked-by: Simon Glass 

Applied to u-boot-x86/next, thanks!
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Re: [U-Boot] [PATCH v4 4/4] x86: crownbay: Add pci devices in the dts file

On 31 December 2014 at 01:05, Bin Meng  wrote:
> The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
> 1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
> Open Firmware PCI bus bindings.
>
> Also a comment block is added for the 'stdout-path' property in the
> chosen node, mentioning that by default the legacy superio serial
> port (io addr 0x3f8) is still used on Crown Bay as the console port.
>
> Signed-off-by: Bin Meng 

Acked-by: Simon Glass 

>
> ---
>
> Changes in v4:
> - Add , after pciclass in the pci compatible string per spec
> - Drop the first 3 patches which are already applied
>
> Changes in v3: None
> Changes in v2:
> - New patch to add pci devices in crownbay.dts
> - Drop v1 patch: Add an API for finding pci devices in the early phase
> - Drop v1 patch: Support PCI UART in the x86_serial driver
> - Drop v1 patch: Add PCI UART related defines in crownbay.h
>
>  arch/x86/dts/crownbay.dts | 81 
> +++
>  1 file changed, 81 insertions(+)
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Re: [U-Boot] [PATCH v4 1/4] fdt: Add several apis to decode pci device node

On 31 December 2014 at 01:05, Bin Meng  wrote:
> This commit adds several APIs to decode PCI device node according to
> the Open Firmware PCI bus bindings, including:
> - fdtdec_get_pci_addr() for encoded pci address
> - fdtdec_get_pci_vendev() for vendor id and device id
> - fdtdec_get_pci_bdf() for pci device bdf triplet
> - fdtdec_get_pci_bar32() for pci device register bar
>
> Signed-off-by: Bin Meng 
>
> ---
>
> Changes in v4:
> - Check compatible string 12th byte against '\0'

Acked-by: Simon Glass 

>
> Changes in v3:
> - Fixed a typo: parant -> parent
> - Return better error code in fdtdec_get_pci_addr()
> - Add some debug output in fdtdec_get_pci_addr()
> - Reuse variable 'len' instead of creating a new one 'l'
> - Check compatible string length and existence of '.'
> - Using simple_strtol() directly on the compatible sub-string
> - Change variable 'bn' to 'barnum' which is self-documenting
>
> Changes in v2:
> - New patch to add several apis to decode pci device node
>
>  include/fdtdec.h | 108 +++
>  lib/fdtdec.c | 171 
> ++-
>  2 files changed, 254 insertions(+), 25 deletions(-)
>
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Re: [U-Boot] [PATCH] arm: omap3: cm-t35: convert to generic board

2014-12-31 Thread Igor Grinberg

On 12/31/14 15:00, Nikita Kiryanov wrote:
> Convert cm-t35 to generic board.
> 
> Cc: Igor Grinberg 
> Cc: Tom Rini 
> Signed-off-by: Nikita Kiryanov 

Acked-by: Igor Grinberg 

> ---
>  include/configs/cm_t35.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
> index ccd9b88..9767512 100644
> --- a/include/configs/cm_t35.h
> +++ b/include/configs/cm_t35.h
> @@ -25,6 +25,7 @@
>  #define CONFIG_CMD_GPIO
>  #define CONFIG_CM_T3X/* working with CM-T35 and CM-T3730 */
>  #define CONFIG_OMAP_COMMON
> +#define CONFIG_SYS_GENERIC_BOARD
>  
>  #define CONFIG_SDRC  /* The chip has SDRC controller */
>  
> 

-- 
Regards,
Igor.
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[U-Boot] [PATCH] arm: omap3: cm-t35: convert to generic board

2014-12-31 Thread Nikita Kiryanov

Convert cm-t35 to generic board.

Cc: Igor Grinberg 
Cc: Tom Rini 
Signed-off-by: Nikita Kiryanov 
---
 include/configs/cm_t35.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index ccd9b88..9767512 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -25,6 +25,7 @@
 #define CONFIG_CMD_GPIO
 #define CONFIG_CM_T3X  /* working with CM-T35 and CM-T3730 */
 #define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
 
 #define CONFIG_SDRC/* The chip has SDRC controller */
 
-- 
1.9.1

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[U-Boot] [PATCH v3 2/4] sun7i: Add PSCI v0.2 support

From: Jan Kiszka 

This extends the PSCI support for the A20 to a dual v0.2 and v0.1
interface. Recent OSes will prefer v0.2, olders will still find the
original interface, just at v0.2 service IDs.

In addition to the existing services, v0.2 requires us to implement both
system off and reset. At least Linux will make use of them in favor of
its own implementations and, thus, fail if they do not work.

Signed-off-by: Jan Kiszka 
---
 arch/arm/cpu/armv7/psci.S |  35 +-
 arch/arm/cpu/armv7/sunxi/psci.S   | 117 ++
 arch/arm/cpu/armv7/virt-dt.c  |   5 +-
 arch/arm/include/asm/arch-sunxi/cpu.h |   2 +
 arch/arm/include/asm/psci.h   |  24 +--
 5 files changed, 173 insertions(+), 10 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index bf11a34..e2a38ca 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -49,8 +49,18 @@ ENTRY(psci_cpu_suspend)
 ENTRY(psci_cpu_off)
 ENTRY(psci_cpu_on)
 ENTRY(psci_migrate)
+ENTRY(psci_affinity_info)
+ENTRY(psci_migrate_info_type)
+ENTRY(psci_migrate_info_up_cpu)
+ENTRY(psci_system_off)
+ENTRY(psci_system_reset)
mov r0, #ARM_PSCI_RET_NI@ Return -1 (Not Implemented)
mov pc, lr
+ENDPROC(psci_system_reset)
+ENDPROC(psci_system_off)
+ENDPROC(psci_migrate_info_up_cpu)
+ENDPROC(psci_migrate_info_type)
+ENDPROC(psci_affinity_info)
 ENDPROC(psci_migrate)
 ENDPROC(psci_cpu_on)
 ENDPROC(psci_cpu_off)
@@ -59,16 +69,33 @@ ENDPROC(psci_cpu_suspend)
 .weak psci_cpu_off
 .weak psci_cpu_on
 .weak psci_migrate
+.weak psci_affinity_info
+.weak psci_migrate_info_type
+.weak psci_migrate_info_up_cpu
+.weak psci_system_off
+.weak psci_system_reset
 
 _psci_table:
+   .word   ARM_PSCI_FN_PSCI_VERSION
+   .word   psci_version
.word   ARM_PSCI_FN_CPU_SUSPEND
.word   psci_cpu_suspend
.word   ARM_PSCI_FN_CPU_OFF
.word   psci_cpu_off
.word   ARM_PSCI_FN_CPU_ON
.word   psci_cpu_on
+   .word   ARM_PSCI_FN_AFFINITY_INFO
+   .word   psci_affinity_info
.word   ARM_PSCI_FN_MIGRATE
.word   psci_migrate
+   .word   ARM_PSCI_FN_MIGRATE_INFO_TYPE
+   .word   psci_migrate_info_type
+   .word   ARM_PSCI_FN_MIGRATE_INFO_UP_CPU
+   .word   psci_migrate_info_up_cpu
+   .word   ARM_PSCI_FN_SYSTEM_OFF
+   .word   psci_system_off
+   .word   ARM_PSCI_FN_SYSTEM_RESET
+   .word   psci_system_reset
.word   0
.word   0
 
@@ -86,7 +113,7 @@ _smc_psci:
ldr r6, [r4, #4]@ Load target PC
cmp r5, #0  @ If reach the end, bail out
moveq   r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid)
-   beq 2f
+   beq return
cmp r0, r5  @ If not matching, try next entry
addne   r4, r4, #8
bne 1b
@@ -94,9 +121,13 @@ _smc_psci:
blx r6  @ Execute PSCI function
 
@ Switch back to non-secure
-2: mcr p15, 0, r7, c1, c1, 0
+return:mcr p15, 0, r7, c1, c1, 0
 
pop {r4-r7, lr}
movspc, lr  @ Return to the kernel
 
+psci_version:
+   mov r0, #0x0002 @ Version 0.2
+   b   return
+
.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 739ce77..d1fa33d 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -2,6 +2,9 @@
  * Copyright (C) 2013 - ARM Ltd
  * Author: Marc Zyngier 
  *
+ * Copyright (C) Siemens AG, 2014
+ * Author: Jan Kiszka 
+ *
  * Based on code by Carl van Schaik .
  *
  * This program is free software; you can redistribute it and/or modify
@@ -42,6 +45,35 @@
 #defineGICD_BASE   0x1c81000
 #defineGICC_BASE   0x1c82000
 
+#defineTWI_DATA0x0008
+#defineTWI_CNTR0x000c
+#defineTWI_STAT0x0010
+#defineTWI_CCR 0x0014
+#defineTWI_SRST0x0018
+
+#defineTWI_CNTR_STOP   (1 << 4)
+#defineTWI_CNTR_START  (1 << 5)
+#defineTWI_CNTR_BUSEN  (1 << 6)
+
+#defineTWI_STAT_START_SENT 0x08
+#defineTWI_STAT_ADDR_ACK   0x18
+#defineTWI_STAT_DATA_ACK   0x28
+
+#defineTWI_CCR_100KHZ  ((11 << 3) | 2)
+
+#defineAXP209_ADDR 0x34
+#defineAXP209_REG_SHUTDOWN 0x32
+#defineAXP209_SHUTDOWN_CTRL0x80
+
+#defineWDOG_CTL0x00
+#defineWDOG_MODE   0x04
+
+#defineWDOG_CTL_RSTART (1 << 0)
+
+#defineWDOG_MODE_EN(1 << 0)
+#defineWDOG_MODE_RSTEN (1 << 1)
+#defineWDOG_MODE_0_5_S (0x0 << 3)
+
 .macro timer_wait  reg, ticks
@ Program CNTP_TVAL
movw\reg, #(\ticks &

[U-Boot] [PATCH v3 3/4] sun7i: Move psci_arch_init close to text_end

From: Jan Kiszka 

"adr rX, text_end" only works if the label is close. Adding further code
to the other functions will prevent this. So move the containing
function close to label. No functional change.

Signed-off-by: Jan Kiszka 
---
 arch/arm/cpu/armv7/sunxi/psci.S | 80 -
 1 file changed, 40 insertions(+), 40 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index d1fa33d..02c1769 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -94,46 +94,6 @@
isb
 .endm
 
-.globl psci_arch_init
-psci_arch_init:
-   movwr4, #(GICD_BASE & 0x)
-   movtr4, #(GICD_BASE >> 16)
-
-   ldr r5, [r4, #GICD_IGROUPRn]
-   bic r5, r5, #(1 << 15)  @ SGI15 as Group-0
-   str r5, [r4, #GICD_IGROUPRn]
-
-   mov r5, #0  @ Set SGI15 priority to 0
-   strbr5, [r4, #(GICD_IPRIORITYRn + 15)]
-
-   add r4, r4, #0x1000 @ GICC address
-
-   mov r5, #0xff
-   str r5, [r4, #GICC_PMR] @ Be cool with non-secure
-
-   ldr r5, [r4, #GICC_CTLR]
-   orr r5, r5, #(1 << 3)   @ Switch FIQEn on
-   str r5, [r4, #GICC_CTLR]
-
-   mrc p15, 0, r5, c1, c1, 0   @ Read SCR
-   orr r5, r5, #4  @ Enable FIQ in monitor mode
-   bic r5, r5, #1  @ Secure mode
-   mcr p15, 0, r5, c1, c1, 0   @ Write SCR
-   isb
-
-   mrc p15, 0, r4, c0, c0, 5   @ MPIDR
-   and r4, r4, #3  @ cpu number in cluster
-   mov r5, #0x400  @ 1kB of stack per CPU
-   mul r4, r4, r5
-
-   adr r5, text_end@ end of text
-   add r5, r5, #0x2000 @ Skip two pages
-   lsr r5, r5, #12 @ Align to start of page
-   lsl r5, r5, #12
-   sub sp, r5, r4  @ here's our stack!
-
-   bx  lr
-
 .globl psci_fiq_enter
 psci_fiq_enter:
push{r0-r12}
@@ -446,5 +406,45 @@ psci_system_reset:
str r1, [r0, #WDOG_CTL]
 1: b   1b
 
+.globl psci_arch_init
+psci_arch_init:
+   movwr4, #(GICD_BASE & 0x)
+   movtr4, #(GICD_BASE >> 16)
+
+   ldr r5, [r4, #GICD_IGROUPRn]
+   bic r5, r5, #(1 << 15)  @ SGI15 as Group-0
+   str r5, [r4, #GICD_IGROUPRn]
+
+   mov r5, #0  @ Set SGI15 priority to 0
+   strbr5, [r4, #(GICD_IPRIORITYRn + 15)]
+
+   add r4, r4, #0x1000 @ GICC address
+
+   mov r5, #0xff
+   str r5, [r4, #GICC_PMR] @ Be cool with non-secure
+
+   ldr r5, [r4, #GICC_CTLR]
+   orr r5, r5, #(1 << 3)   @ Switch FIQEn on
+   str r5, [r4, #GICC_CTLR]
+
+   mrc p15, 0, r5, c1, c1, 0   @ Read SCR
+   orr r5, r5, #4  @ Enable FIQ in monitor mode
+   bic r5, r5, #1  @ Secure mode
+   mcr p15, 0, r5, c1, c1, 0   @ Write SCR
+   isb
+
+   mrc p15, 0, r4, c0, c0, 5   @ MPIDR
+   and r4, r4, #3  @ cpu number in cluster
+   mov r5, #0x400  @ 1kB of stack per CPU
+   mul r4, r4, r5
+
+   adr r5, text_end@ end of text
+   add r5, r5, #0x2000 @ Skip two pages
+   lsr r5, r5, #12 @ Align to start of page
+   lsl r5, r5, #12
+   sub sp, r5, r4  @ here's our stack!
+
+   bx  lr
+
 text_end:
.popsection
-- 
1.8.4.5

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[U-Boot] [PATCH v3 0/4] sun7i: PSCI enhancements

This adds CPU offlining and PSCI v0.2 support. Changes since v2:
 - add more comments to psci_fiq_enter (patch 1)
 - rebase over u-boot-sunxi/next

See patches for further details.

Jan

Jan Kiszka (4):
  sun7i: Add support for taking CPUs offline via PSCI
  sun7i: Add PSCI v0.2 support
  sun7i: Move psci_arch_init close to text_end
  sun7i: Implement PSCI v0.2 AFFINITY_INFO

 arch/arm/cpu/armv7/psci.S |  35 +++-
 arch/arm/cpu/armv7/sunxi/psci.S   | 351 --
 arch/arm/cpu/armv7/virt-dt.c  |   5 +-
 arch/arm/include/asm/arch-sunxi/cpu.h |   2 +
 arch/arm/include/asm/psci.h   |  24 ++-
 5 files changed, 392 insertions(+), 25 deletions(-)

-- 
1.8.4.5

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[U-Boot] [PATCH v3 4/4] sun7i: Implement PSCI v0.2 AFFINITY_INFO

From: Jan Kiszka 

It's mandatory according to the spec, and Linux uses it for checking if
an offlined CPU is already dead. Without this implemented, we get some
warnings on the kernel console at least.

Signed-off-by: Jan Kiszka 
---
 arch/arm/cpu/armv7/sunxi/psci.S | 33 +
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 02c1769..1705ad7 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -160,6 +160,12 @@ psci_fiq_enter:
tst r10, #0x100
beq 1b
 
+   @ Mark CPU disabled
+   adr r2, _cpu_off
+   ldr r0, [r2]
+   orr r0, r0, r9
+   str r0, [r2]
+
@ Restore security level
 out:   mcr p15, 0, r7, c1, c1, 0
 
@@ -228,6 +234,12 @@ psci_cpu_on:
orr r6, r6, r4
str r6, [r0, #0x1e4]
 
+   @ Mark CPU enabled
+   adr r2, _cpu_off
+   ldr r0, [r2]
+   bic r0, r0, r4
+   str r0, [r2]
+
mov r0, #ARM_PSCI_RET_SUCCESS   @ Return PSCI_RET_SUCCESS
mov pc, lr
 
@@ -235,6 +247,8 @@ _target_pc:
.word   0
 _context:
.word   0
+_cpu_off:
+   .word   0x2
 
 /* Imported from Linux kernel */
 v7_flush_dcache_all:
@@ -328,6 +342,25 @@ psci_cpu_off:
 1: wfi
b   1b
 
+   @ r1 = target CPU
+   @ r2 = lowest affinity level
+.globl psci_affinity_info
+psci_affinity_info:
+   @ only support full match
+   cmp r2, #0
+   mov r0, #ARM_PSCI_RET_INVAL
+   bne 1
+
+   @ prepare CPU ID in r1, only caring about the first cluster
+   and r1, r1, #3
+
+   adr r2, _cpu_off
+   ldr r0, [r2]@ load bitmap of offlined CPUs
+   lsr r0, r0, r1  @ shift right by CPU ID
+   and r0, r0, #1  @ filter out relevant bit
+
+1: mov pc, lr
+
 /*
  * r0: TWI base address
  * r1: state to wait for
-- 
1.8.4.5

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[U-Boot] [PATCH v3 1/4] sun7i: Add support for taking CPUs offline via PSCI

From: Jan Kiszka 

Based on the original version by Marc Zyngier. It adds a psci_cpu_off
implementation for the A20 SoC. The mechanism works by first preparing
the calling CPU to go offline (disable and flush cache, disable SMP),
then requesting CPU 0 to pull the plug. The request is sent as FIQ on
SGI15.

Signed-off-by: Jan Kiszka 
---
 arch/arm/cpu/armv7/sunxi/psci.S | 171 
 1 file changed, 171 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index a84807d..739ce77 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -18,6 +18,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 
@@ -38,6 +39,8 @@
 
 #defineONE_MS  (CONFIG_SYS_CLK_FREQ / 1000)
 #defineTEN_MS  (10 * ONE_MS)
+#defineGICD_BASE   0x1c81000
+#defineGICC_BASE   0x1c82000
 
 .macro timer_wait  reg, ticks
@ Program CNTP_TVAL
@@ -61,7 +64,27 @@
 
 .globl psci_arch_init
 psci_arch_init:
+   movwr4, #(GICD_BASE & 0x)
+   movtr4, #(GICD_BASE >> 16)
+
+   ldr r5, [r4, #GICD_IGROUPRn]
+   bic r5, r5, #(1 << 15)  @ SGI15 as Group-0
+   str r5, [r4, #GICD_IGROUPRn]
+
+   mov r5, #0  @ Set SGI15 priority to 0
+   strbr5, [r4, #(GICD_IPRIORITYRn + 15)]
+
+   add r4, r4, #0x1000 @ GICC address
+
+   mov r5, #0xff
+   str r5, [r4, #GICC_PMR] @ Be cool with non-secure
+
+   ldr r5, [r4, #GICC_CTLR]
+   orr r5, r5, #(1 << 3)   @ Switch FIQEn on
+   str r5, [r4, #GICC_CTLR]
+
mrc p15, 0, r5, c1, c1, 0   @ Read SCR
+   orr r5, r5, #4  @ Enable FIQ in monitor mode
bic r5, r5, #1  @ Secure mode
mcr p15, 0, r5, c1, c1, 0   @ Write SCR
isb
@@ -79,6 +102,78 @@ psci_arch_init:
 
bx  lr
 
+.globl psci_fiq_enter
+psci_fiq_enter:
+   push{r0-r12}
+
+   @ Switch to secure
+   mrc p15, 0, r7, c1, c1, 0
+   bic r8, r7, #1
+   mcr p15, 0, r8, c1, c1, 0
+   isb
+
+   @ Validate reason based on IAR and acknowledge
+   movwr8, #(GICC_BASE & 0x)
+   movtr8, #(GICC_BASE >> 16)
+   ldr r9, [r8, #GICC_IAR]
+   movwr10, #0x3ff
+   movtr10, #0
+   cmp r9, r10 @ skip spurious interrupt 1023
+   beq out
+   movwr10, #0x3fe @ ...and 1022
+   cmp r9, r10
+   beq out
+   str r9, [r8, #GICC_EOIR]@ acknowledge the interrupt
+   dsb
+
+   @ Compute CPU number
+   lsr r9, r9, #10
+   and r9, r9, #0xf
+
+   movwr8, #(SUN7I_CPUCFG_BASE & 0x)
+   movtr8, #(SUN7I_CPUCFG_BASE >> 16)
+
+   @ Wait for the core to enter WFI
+   lsl r11, r9, #6 @ x64
+   add r11, r11, r8
+
+1: ldr r10, [r11, #0x48]
+   tst r10, #(1 << 2)
+   bne 2f
+   timer_wait r10, ONE_MS
+   b   1b
+
+   @ Reset CPU
+2: mov r10, #0
+   str r10, [r11, #0x40]
+
+   @ Lock CPU
+   mov r10, #1
+   lsl r9, r10, r9 @ r9 is now CPU mask
+   ldr r10, [r8, #0x1e4]
+   bic r10, r10, r9
+   str r10, [r8, #0x1e4]
+
+   @ Set power gating
+   ldr r10, [r8, #0x1b4]
+   orr r10, r10, #1
+   str r10, [r8, #0x1b4]
+   timer_wait r10, ONE_MS
+
+   @ Activate power clamp
+   mov r10, #1
+1: str r10, [r8, #0x1b0]
+   lsl r10, r10, #1
+   orr r10, r10, #1
+   tst r10, #0x100
+   beq 1b
+
+   @ Restore security level
+out:   mcr p15, 0, r7, c1, c1, 0
+
+   pop {r0-r12}
+   subspc, lr, #4
+
@ r1 = target CPU
@ r2 = target PC
 .globl psci_cpu_on
@@ -144,6 +239,53 @@ psci_cpu_on:
 _target_pc:
.word   0
 
+/* Imported from Linux kernel */
+v7_flush_dcache_all:
+   dmb @ ensure ordering with previous 
memory accesses
+   mrc p15, 1, r0, c0, c0, 1   @ read clidr
+   andsr3, r0, #0x700  @ extract loc from clidr
+   mov r3, r3, lsr #23 @ left align loc bit field
+   beq finished@ if loc is 0, then no need to 
clean
+   mov r10, #0 @ start clean at cache level 0
+flush_levels:
+   add r2, r10, r10, lsr #1@ work out 3x current cache 
level
+   mov r1, r0, lsr r2  @ extract cache type bits from 
clidr
+   and r1, r1, #7  @ mask of the bits for current 
cache only
+   cmp r1, #2  @ see what cache we have at 
this level
+   blt skip@ skip

[U-Boot] Bug in buildman?

2014-12-31 Thread Andreas Bießmann

Hi Simon,

while test-building 2015.01-rc4 I encountered following strange
behaviour of buildman:

---8<---
andreas@andreas-pc % ./tools/buildman/buildman -b buildtest -o /tmp/bar
-v avr32
boards.cfg is up to date. Nothing to do.
Building 1 commit for 10 boards (6 threads, 1 job per thread)
Cloning repo for thread 0
Cloning repo for thread 1
Cloning repo for thread 2
Cloning repo for thread 3
Cloning repo for thread 4
Cloning repo for thread 5
01: Prepare v2015.01-rc4
 avr32: +   atstk1006
01: Prepare v2015.01-rc4
 avr32: +   atngw100
01: Prepare v2015.01-rc4
 avr32: +   favr-32-ezkit
01: Prepare v2015.01-rc4
 avr32: +   atstk1004
01: Prepare v2015.01-rc4
 avr32: +   hammerhead
01: Prepare v2015.01-rc4
 avr32: +   grasshopper
01: Prepare v2015.01-rc4
 avr32: +   atstk1003
01: Prepare v2015.01-rc4
 avr32: +   atstk1002
01: Prepare v2015.01-rc4
 avr32: +   mimc200
01: Prepare v2015.01-rc4
 avr32: +   atngw100mkii
046 /10 0:00:02  : atngw100mkii
./tools/buildman/buildman -b buildtest -o /tmp/bar -v avr32  82.57s user
16.90s system 249% cpu 39.899 total
andreas@andreas-pc % ./tools/buildman/buildman -b buildtest -o /tmp/bar
-v -lsed
boards.cfg is up to date. Nothing to do.
Summary of 1 commit for 1204 boards (6 threads, 1 job per thread)
01: Prepare v2015.01-rc4
 avr32: +   atngw100mkii atstk1003 grasshopper favr-32-ezkit
atstk1006 atstk1004 atstk1002 atngw100 hammerhead mimc200
+(grasshopper,atngw100,favr-32-ezkit,atstk1006,atstk1004,hammerhead)
Could not find linker script.
+(grasshopper,atngw100,favr-32-ezkit,atstk1006,atstk1004,hammerhead)
make[1]: *** [prepare1] Error 1
+(grasshopper,atngw100,favr-32-ezkit,atstk1006,atstk1004,hammerhead)
make: *** [sub-make] Error 2
w+(atngw100mkii,atstk1002,atstk1003,mimc200) ../tools/kwbimage.c: In
function ‘kwbimage_set_header’:
w+(atngw100mkii,atstk1002,atstk1003,mimc200) ../tools/kwbimage.c:803:8:
warning: ‘headersz’ may be used uninitialized in this function
[-Wmaybe-uninitialized]
andreas@andreas-pc % ./tools/buildman/buildman -b buildtest -o /tmp/bar
-v -lsed grasshopper
boards.cfg is up to date. Nothing to do.
Summary of 1 commit for 1 boards (1 thread, 6 jobs per thread)
01: Prepare v2015.01-rc4
 avr32: +   grasshopper
+(grasshopper)   Could not find linker script.
+(grasshopper) make[1]: *** [prepare1] Error 1
+(grasshopper) make: *** [sub-make] Error 2
andreas@andreas-pc % ./tools/buildman/buildman -b buildtest -o
/tmp/grasshopper -v grasshopper
boards.cfg is up to date. Nothing to do.
Building 1 commit for 1 boards (1 thread, 6 jobs per thread)
Cloning repo for thread 0
01: Prepare v2015.01-rc4
 avr32: +   grasshopper
010 /1  grasshopper
./tools/buildman/buildman -b buildtest -o /tmp/grasshopper -v
grasshopper  14.11s user 2.69s system 183% cpu 9.171 total
andreas@andreas-pc % ./tools/buildman/buildman -b buildtest -o
/tmp/grasshopper -v -lsed grasshopper
boards.cfg is up to date. Nothing to do.
Summary of 1 commit for 1 boards (1 thread, 6 jobs per thread)
01: Prepare v2015.01-rc4
 avr32: +   grasshopper
w+(grasshopper) ../tools/kwbimage.c: In function ‘kwbimage_set_header’:
w+(grasshopper) ../tools/kwbimage.c:803:8: warning: ‘headersz’ may be
used uninitialized in this function [-Wmaybe-uninitialized]
--->8---

buildman complains about missing linker script for most boards which is
an error when building all avr32 boards. While it detects the correct
warning for still not fixed kwbimage.c maybe-uninitialized when building
just the single board which had an error before. Both builds are based
on v2015.01-rc4 and built in different locations.

Best regards

Andreas Bießmann
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Re: [U-Boot] [PATCH 6/9] imx: cm_fx6: Remove reference to gdata

2014-12-31 Thread Nikita Kiryanov


Hi Simon,

On 12/23/2014 09:04 PM, Simon Glass wrote:

The global_data pointer (gd) has already been set before board_init_f()
is called. We should not assign it again. We should also not use gdata since
it is going away.

Signed-off-by: Simon Glass 
---


Tested-by: Nikita Kiryanov 
Acked-by: Nikita Kiryanov 

--
Regards,
Nikita Kiryanov
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[U-Boot] [PATCH v2 2/2] sunxi: video: Enable video on sun8i, which supports LCD but not HDMI

The A23 (sun8i) only has lcd output support, so allow building the video code
without HDMI support for use with the A23.

Also the A23 has the same reset bits (and necessity to enable the DRC block)
as the sun6i, so enable those bits for sun8i too.

Note building without HDMI support is useful for the A13 (sun5i variant) too,
as that one does not have HDMI either.

Signed-off-by: Hans de Goede 
---
Changes in v2:
-Improve commit message to better reflect what the patch does
---
 board/sunxi/Kconfig   |  7 +++
 drivers/video/sunxi_display.c | 30 ++
 2 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 6f2377d..ff4fbb4 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -288,6 +288,13 @@ config VIDEO
or VGA output found on most sunxi devices. See doc/README.video for
info on how to select the video output and mode.
 
+config VIDEO_HDMI
+   boolean "HDMI output support"
+   depends on VIDEO && !MACH_SUN8I
+   default y
+   ---help---
+   Say Y here to add support for outputting video over HDMI.
+
 config VIDEO_LCD_MODE
string "LCD panel timing details"
depends on VIDEO
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index fee1474..9481b95 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -39,6 +39,8 @@ struct sunxi_display {
unsigned int depth;
 } sunxi_display;
 
+#ifdef CONFIG_VIDEO_HDMI
+
 /*
  * Wait up to 200ms for value to be set in given part of reg.
  */
@@ -267,6 +269,8 @@ static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes 
*mode)
return 0;
 }
 
+#endif /* CONFIG_VIDEO_HDMI */
+
 /*
  * This is the entity that mixes and matches the different layers and inputs.
  * Allwinner calls it the back-end, but i like composer better.
@@ -279,7 +283,7 @@ static void sunxi_composer_init(void)
(struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
int i;
 
-#ifdef CONFIG_MACH_SUN6I
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
/* Reset off */
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 #endif
@@ -409,7 +413,7 @@ static void sunxi_lcdc_init(void)
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 
/* Reset off */
-#ifdef CONFIG_MACH_SUN6I
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 #else
setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
@@ -565,6 +569,8 @@ static void sunxi_lcdc_tcon0_mode_set(const struct 
ctfb_res_modes *mode)
writel(0, &lcdc->tcon0_io_tristate);
 }
 
+#ifdef CONFIG_VIDEO_HDMI
+
 static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
  int *clk_div, int *clk_double)
 {
@@ -711,9 +717,11 @@ static void sunxi_hdmi_enable(void)
setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 }
 
+#endif /* CONFIG_VIDEO_HDMI */
+
 static void sunxi_drc_init(void)
 {
-#ifdef CONFIG_MACH_SUN6I
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
@@ -738,6 +746,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes 
*mode,
break;
case sunxi_monitor_dvi:
case sunxi_monitor_hdmi: {
+#ifdef CONFIG_VIDEO_HDMI
int clk_div, clk_double;
sunxi_composer_mode_set(mode, address);
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double);
@@ -745,6 +754,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes 
*mode,
sunxi_composer_enable();
sunxi_lcdc_enable();
sunxi_hdmi_enable();
+#endif
}
break;
case sunxi_monitor_lcd:
@@ -778,9 +788,12 @@ void *video_hw_init(void)
const struct ctfb_res_modes *mode;
struct ctfb_res_modes custom;
const char *options;
-   int i, ret, hpd, edid;
+#ifdef CONFIG_VIDEO_HDMI
+   int ret, hpd, edid;
+#endif
char mon[16];
char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
+   int i;
 
memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 
@@ -790,9 +803,13 @@ void *video_hw_init(void)
 
video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
 &sunxi_display.depth, &options);
+#ifdef CONFIG_VIDEO_HDMI
hpd = video_get_option_int(options, "hpd", 1);
edid = video_get_option_int(options, "edid", 1);
sunxi_display.monitor = sunxi_monitor_dvi;
+#else
+   sunxi_display.monitor = sunxi_monitor_lcd;
+#endif
video_get_option_string(options, "monitor", mon, sizeof(mon),
sunxi_get_mon_desc(sunxi_display.monitor));
for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
@@ -810,

Re: [U-Boot] [PATCH 10/17] sunxi: video: Add suppport SoCs without HDMI, e.g. the A13 and A23


Hi,

On 29-12-14 14:50, Ian Campbell wrote:

On Wed, 2014-12-24 at 20:06 +0100, Hans de Goede wrote:

You've got three p's in suppport in the subject.


Some SoCs, specifically the A13 (sun5i variant) and the A23 (sun8i) only have
lcd output support.

Signed-off-by: Hans de Goede 
---
  board/sunxi/Kconfig   |  7 +++
  drivers/video/sunxi_display.c | 30 ++
  2 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 35c59e9..7a8503b 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -246,6 +246,13 @@ config VIDEO
or VGA output found on most sunxi devices. See doc/README.video for
info on how to select the video output and mode.

+config VIDEO_HDMI
+   boolean "HDMI output support"
+   depends on VIDEO && !MACH_SUN8I


There is no "&& !MACH_SUN5I" here because there are sun5i variants other
than the A13 which do have HDMI, correct?


Correct, the A10s has HDMI out support.


@@ -278,7 +282,7 @@ static void sunxi_composer_init(void)
(struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
int i;

-#ifdef CONFIG_MACH_SUN6I
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I


These seem a bit odd. If the sun8i has no HDMI why are we messing with
the reset bits? (Or at least, why is such messing new in this particular
patch).

I think perhaps rather than "disabling the non-existent HDMI on sun8i"
which is how I read the patch description I should have read "enable
video on sun8i, which supports LCD but not HDMI"?


Yeah that is better, I'll do a v2 with the commit message fixed.

Regards,

Hans
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[U-Boot] [PATCH v2 1/2] sunxi: video: Add lcd output support

Add lcd output support, see the new Kconfig entries and doc/README.video for
how to enable / configure this.

Signed-off-by: Hans de Goede 
---
Changes in v2:
-Do not request backlight gpio twices
-Fix some spelling errors in comments
-Fix some no longer accurate comments
---
 arch/arm/include/asm/arch-sunxi/display.h |  25 -
 arch/arm/include/asm/arch-sunxi/gpio.h|   2 +
 board/sunxi/Kconfig   |  43 ++-
 doc/README.video  |  50 +++--
 drivers/video/sunxi_display.c | 179 --
 5 files changed, 272 insertions(+), 27 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/display.h 
b/arch/arm/include/asm/arch-sunxi/display.h
index 00e3466..dcb2fe4 100644
--- a/arch/arm/include/asm/arch-sunxi/display.h
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -57,14 +57,13 @@ struct sunxi_lcdc_reg {
u32 int0;   /* 0x04 */
u32 int1;   /* 0x08 */
u8 res0[0x04];  /* 0x0c */
-   u32 frame_ctrl; /* 0x10 */
-   u8 res1[0x2c];  /* 0x14 */
+   u32 frame_ctrl[12]; /* 0x10 */
u32 tcon0_ctrl; /* 0x40 */
u32 tcon0_dclk; /* 0x44 */
-   u32 tcon0_basic_timing0;/* 0x48 */
-   u32 tcon0_basic_timing1;/* 0x4c */
-   u32 tcon0_basic_timing2;/* 0x50 */
-   u32 tcon0_basic_timing3;/* 0x54 */
+   u32 tcon0_timing_active;/* 0x48 */
+   u32 tcon0_timing_h; /* 0x4c */
+   u32 tcon0_timing_v; /* 0x50 */
+   u32 tcon0_timing_sync;  /* 0x54 */
u32 tcon0_hv_intf;  /* 0x58 */
u8 res2[0x04];  /* 0x5c */
u32 tcon0_cpu_intf; /* 0x60 */
@@ -179,7 +178,21 @@ struct sunxi_hdmi_reg {
 #define SUNXI_LCDC_CTRL_IO_MAP_TCON0   (0 << 0)
 #define SUNXI_LCDC_CTRL_IO_MAP_TCON1   (1 << 0)
 #define SUNXI_LCDC_CTRL_TCON_ENABLE(1 << 31)
+#define SUNXI_LCDC_FRAME_CTRL0_RGB666  ((1 << 31) | (0 << 4))
+#define SUNXI_LCDC_FRAME_CTRL0_RGB656  ((1 << 31) | (5 << 4))
+#define SUNXI_LCDC_FRAME_CTRL_DITHER0  0x
+#define SUNXI_LCDC_FRAME_CTRL_DITHER1  0x0101
+#define SUNXI_LCDC_FRAME_CTRL_DITHER2  0x1515
+#define SUNXI_LCDC_FRAME_CTRL_DITHER3  0x5757
+#define SUNXI_LCDC_FRAME_CTRL_DITHER4  0x7f7f
+#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
+#define SUNXI_LCDC_TCON0_CTRL_ENABLE   (1 << 31)
+#define SUNXI_LCDC_TCON0_DCLK_DIV(n)   ((n) << 0)
 #define SUNXI_LCDC_TCON0_DCLK_ENABLE   (0xf << 28)
+#define SUNXI_LCDC_TCON0_TIMING_H_BP(n)(((n) - 1) << 0)
+#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16)
+#define SUNXI_LCDC_TCON0_TIMING_V_BP(n)(((n) - 1) << 0)
+#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16)
 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
 #define SUNXI_LCDC_TCON1_CTRL_ENABLE   (1 << 31)
 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n)(((n) - 1) << 0)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 32941cb..9438f5a 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -150,6 +150,8 @@ enum sunxi_gpio_number {
 
 #define SUNXI_GPC6_SDC23
 
+#define SUNXI_GPD0_LCD02
+
 #define SUNXI_GPF0_SDC02
 
 #define SUNXI_GPF2_SDC02
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 72c0165..6f2377d 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -281,17 +281,52 @@ config USB2_VBUS_PIN
See USB1_VBUS_PIN help text.
 
 config VIDEO
-   boolean "Enable graphical uboot console on HDMI"
+   boolean "Enable graphical uboot console on HDMI, LCD or VGA"
default y
---help---
-   Say Y here to add support for using a cfb console on the HDMI output
-   found on most sunxi devices.
+   Say Y here to add support for using a cfb console on the HDMI, LCD
+   or VGA output found on most sunxi devices. See doc/README.video for
+   info on how to select the video output and mode.
+
+config VIDEO_LCD_MODE
+   string "LCD panel timing details"
+   depends on VIDEO
+   default ""
+   ---help---
+   LCD panel timing details string, leave empty if there is no LCD panel.
+   This is in drivers/video/videomodes.c: video_get_params() format, e.g.
+   
x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
+
+config VIDEO_LCD_POWER
+   string "LCD panel power enable pin"
+   depends on VIDEO
+   default ""
+   ---help---
+   Set the power enable pin for the LCD panel. This takes a string in the
+

Re: [U-Boot] [PATCH] devkit8000: convert to use generic board code

2014-12-31 Thread Anthoine Bourgeois

Hi,

 Anthoine Bourgeois wrote:

> Signed-off-by: Anthoine Bourgeois 
> ---
>
>  include/configs/devkit8000.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
> index 930b08e..77e2f58 100644
> --- a/include/configs/devkit8000.h
> +++ b/include/configs/devkit8000.h
> @@ -21,6 +21,7 @@
>  #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
>  #define CONFIG_OMAP_GPIO
>  #define CONFIG_OMAP_COMMON
> +#define CONFIG_SYS_GENERIC_BOARD

I try this patch with my devkit8000 board and it works well but I wonder
if the devkit8000.h configuration should inherit the ti_omap3_common.h
configuration. I can do those modifications but is it a good idea ? Is
it worth to try ?

Thanks, Anthoine
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Re: [U-Boot] [PATCH 09/17] sunxi: video: Add lcd output support


Hi,

On 29-12-14 14:43, Ian Campbell wrote:

On Wed, 2014-12-24 at 20:06 +0100, Hans de Goede wrote:


+static void sunxi_lcdc_panel_enable(void)
+{
+   int pin;
+
+   /*
+* Start with backlight disabled to avoid the screen flashing to
+* white while the lcd inits.
+*/
+   pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
+   if (pin != -1) {
+   gpio_request(pin, "lcd_backlight_enable");


You request this and the backlight pwm again in backlight_enable. Are
such multiple requests OK?


No, not when using the device_model, I've removed the 2nd gpio_request
call done for both from backlight_enable. I'll send a v2 with this fixed.


+   gpio_direction_output(pin, 0);
+   }
+
+   pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
+   if (pin != -1) {
+   gpio_request(pin, "lcd_backlight_pwm");
+   /* backlight pwm is inverted, set to 1 to disable backlight */
+   gpio_direction_output(pin, 1);
+   }
+
+   /* Give the backlight some time to turn off and power up the panel. */
+   mdelay(40);
+   pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
+   if (pin != -1) {
+   gpio_request(pin, "lcd_power");
+   gpio_direction_output(pin, 1);
+   }
+}
+
+static void sunxi_lcdc_backlight_enable(void)
+{
+   int pin;
+
+   /*
+* We want to have scanned out atleast one frame before enabling the


"at least".


Fixed for v2.


+* backlight to avoid the screen flashing to white when we enable it.
+*/
+   mdelay(40);


I take it there isn't a vsync status bit or something we can watch for?


There is a line interrupt, which we could theoretically use, but the docs are
rather lacking, so I believe this is the best solution for now.




[...]
+   switch (sunxi_display.monitor) {
+   case sunxi_monitor_none:
+   return 0;
+   case sunxi_monitor_dvi:
+   case sunxi_monitor_hdmi:
+   pipeline = "de_be0-lcd0-hdmi";
+   break;
+   case sunxi_monitor_lcd:
+   pipeline = "de_be0-lcd0";
+   break;
+   case sunxi_monitor_vga:
+   break;
+   }
+
/* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */


This comment is no longer accurate.


Fixed for v2.


offset = fdt_node_offset_by_compatible(blob, -1,
   "allwinner,simple-framebuffer");
while (offset >= 0) {
ret = fdt_find_string(blob, offset, "allwinner,pipeline",
- "de_be0-lcd0-hdmi");
+ pipeline);
if (ret == 0)
break;
offset = fdt_node_offset_by_compatible(blob, offset,


Ian.


Regards,

Hans
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Re: [U-Boot] [PATCH v2 0/5] sun7i: PSCI enhancements

On 2014-12-31 12:30, Ian Campbell wrote:
> On Tue, 2014-12-30 at 18:14 +0100, Jan Kiszka wrote:
> 
> I had a couple of comments on v1 a few days ago (a bit late, sorry)
> which I think you may have missed? AFIACT they still stand on this
> version.
> 
>> This adds CPU offlining and PSCI v0.2 support. Changes since v1:
>>  - add AFFINITY_INFO support (mandatory for v0.2)
>>  - rebase over master
>>  - include "sunxi: Align PSCI stack calculation to comment" to provide
>>the complete queue
> 
> Would be better to base on #next at this point I think, which would
> include the first patch already.

Will rebase over your tree and address the comment.

Jan




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Re: [U-Boot] [PATCH 1/2] sun7i: Add support for taking CPUs offline via PSCI

On 2014-12-29 15:08, Ian Campbell wrote:
> On Mon, 2014-12-15 at 12:37 +0100, Jan Kiszka wrote:
>> +movwr8, #(GICC_BASE & 0x)
>> +movtr8, #(GICC_BASE >> 16)
>> +ldr r9, [r8, #GICC_IAR]
>> +movwr10, #0x3ff
>> +movtr10, #0
>> +cmp r9, r10
>> +beq out
>> +movwr10, #0x3fe
>> +cmp r9, r10
>> +beq out
>> +str r9, [r8, #GICC_EOIR]
>> +dsb
> 
> This block could do with a leading comment like the others. It is
> reading IAR and discarding any spurious interrupts (1022+1023), but not
> explicitly checking for SGI15, presumably because it can be asserted
> that there is no other possible interrupt which can end up here, is that
> right?

That would be my interpretations as well: no other interrupt was routed
to the monitor. Will add a comment.

> 
>> +
>> +.globl  psci_cpu_off
>> +psci_cpu_off:
>> +mrc p15, 0, r0, c1, c0, 0   @ SCTLR
>> +bic r0, r0, #(1 << 2)   @ Clear C bit
>> +mcr p15, 0, r0, c1, c0, 0   @ SCTLR
>> +isb
>> +dsb
>> +
>> +bl  v7_flush_dcache_all
>> +
>> +clrex   @ Why???
> 
> Anyone got any clues? (Just curiosity, not a blocker)
> 
> Apart from the comment:
> Acked-by: Ian Campbell 
> 

Thanks,
Jan




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Re: [U-Boot] [PATCH 2/2] sun7i: Add PSCI v0.2 support

On 2014-12-29 15:12, Ian Campbell wrote:
> On Mon, 2014-12-15 at 12:37 +0100, Jan Kiszka wrote:
>> This extends the PSCI support for the A20 to a dual v0.2 and v0.1
>> interface. Recent OSes will prefer v0.2, olders will still find the
>> original interface, just at v0.2 service IDs.
>>
>> In addition to the existing services, v0.2 requires us to implement both
>> system off and reset. At least Linux will make use of them in favor of
>> its own implementations and, thus, fail if they do not work.
> 
> What functionality does v0.2 give us over v0.1 that you are aiming to
> expose here?

For us, the added value is currently in next layer: we can simplify the
Jailhouse hypervisor a bit when leaving out v0.1 support right from the
beginning. But that means U-Boot has to support v0.2 on the platforms we
target at.

v0.2 is the current standard, so I would expect new boards to use that
one in the future by default. Thus, this lays the ground, though there
will surely be more work required to make some code better reusable.

Jan

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Re: [U-Boot] [PATCH] sun7i: Add new Bananapro board / defconfig


Hi,

On 31-12-14 11:42, Ian Campbell wrote:

On Wed, 2014-12-31 at 11:38 +0100, Hans de Goede wrote:

Add support for the new Bananapro A20 development board from lemaker.org.
This board features 1G RAM, 2 USB A receptacles, 1 micro USB receptacle for
OTG, 1 micro USB receptacle for power, HDMI, sata, Gbit ethernet, ir receiver,
3.5 mm jack for a/v out, on board microphone, 40 gpio pins and sdio wifi.

Signed-off-by: Hans de Goede 


Acked-by: Ian Campbell 


Thanks, I've rebased u-boot-sunxi/next to the latest master, squashed the
sun6i m / k pll5 fix into the original commit as you suggested, added this
patch and done a forced push with the result.

If you plan to add Jan Kiszka's patches to next (which I think is a good
idea), please base them on top of what I've just pushed.

Thanks & Regards,

Hans
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Re: [U-Boot] [PATCH v2 0/5] sun7i: PSCI enhancements

2014-12-31 Thread Ian Campbell

On Tue, 2014-12-30 at 18:14 +0100, Jan Kiszka wrote:

I had a couple of comments on v1 a few days ago (a bit late, sorry)
which I think you may have missed? AFIACT they still stand on this
version.

> This adds CPU offlining and PSCI v0.2 support. Changes since v1:
>  - add AFFINITY_INFO support (mandatory for v0.2)
>  - rebase over master
>  - include "sunxi: Align PSCI stack calculation to comment" to provide
>the complete queue

Would be better to base on #next at this point I think, which would
include the first patch already.

Ian.

> 
> See patches for further details.
> 
> Jan
> 
> Jan Kiszka (5):
>   sunxi: Align PSCI stack calculation to comment
>   sun7i: Add support for taking CPUs offline via PSCI
>   sun7i: Add PSCI v0.2 support
>   sun7i: Move psci_arch_init close to text_end
>   sun7i: Implement PSCI v0.2 AFFINITY_INFO
> 
>  arch/arm/cpu/armv7/psci.S |  35 +++-
>  arch/arm/cpu/armv7/sunxi/psci.S   | 350 
> --
>  arch/arm/cpu/armv7/virt-dt.c  |   5 +-
>  arch/arm/include/asm/arch-sunxi/cpu.h |   2 +
>  arch/arm/include/asm/psci.h   |  24 ++-
>  5 files changed, 391 insertions(+), 25 deletions(-)
> 


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Re: [U-Boot] [PATCH] sun7i: Add new Bananapro board / defconfig


Hi,

On 31-12-14 11:42, Ian Campbell wrote:

On Wed, 2014-12-31 at 11:38 +0100, Hans de Goede wrote:

Add support for the new Bananapro A20 development board from lemaker.org.
This board features 1G RAM, 2 USB A receptacles, 1 micro USB receptacle for
OTG, 1 micro USB receptacle for power, HDMI, sata, Gbit ethernet, ir receiver,
3.5 mm jack for a/v out, on board microphone, 40 gpio pins and sdio wifi.

Signed-off-by: Hans de Goede 


Acked-by: Ian Campbell 


-#ifdef CONFIG_TARGET_BANANAPI
+#if defined CONFIG_TARGET_BANANAPI || defined CONFIG_TARGET_BANANAPRO
setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);


Did we ever get to the bottom of what this was?


Yes it sets the TX clock delay chain, which is something which one
typically need to do for RGMII phy-s, why this is not needed on the
cubietruck is not known / clear.


I take it that you've confirmed it is needed for the pro, rather than
just carrying it over?


I've not tested the gmac myself yet, but this is being done by their own
u-boot port for the pro in their lemaker github account.

Regards,

Hans
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Re: [U-Boot] [PATCH 15/17] sunxi: Ippo_q8h defconfigs: Enable the LCD panel found on these tablets.

Hi,

On 30-12-14 13:17, Siarhei Siamashka wrote:

On Tue, 30 Dec 2014 11:26:51 +0100
Hans de Goede wrote:

Hi,

On 30-12-14 11:18, Siarhei Siamashka wrote:

On Thu, 25 Dec 2014 11:59:55 +0100
Hans de Goede wrote:

Ah yes, I used the slightly different timings from the olimex 7" lcd
panel for olinuxino boards, and since those worked fine on my a23
tablet I never adjusted things. Here is a translation table:

CONFIG_VIDEO_LCD_MODE fex value(s)

x lcd_x
y lcd_y
depth:18lcd_frm = 1
pclk_khzlcd_dclk_freq * 1000
hs lcd_hv_hspw (with a minimum of 1)
vs lcd_hv_vspw (with a minimum of 1)
le lcd_hbp - hs
ri lcd_ht - lcd_x - lcd_hbp
up lcd_vbp - vs

On sun4i/sun5i/sun7i:
lo (lcd_vt / 2) - lcd_y - lcd_vbp
On sun8i:
lo lcd_vt - lcd_y - lcd_vbp

sync0
mode0

I notice that the Ippo_q8h_v5 fex uses 0 for lcd_hv_hspw and lcd_hv_vspw, which
is not a valid value as the register value contains hspw - 1, so the minimum is
1,
and looking at a register dump under android with my A23 tablet the value indeed
should be 1.

That's interesting. What would be the correct general formula for the
hs/vs values then? "max(lcd_hv_hspw, 1)" or maybe "lcd_hv_hspw + 1"?

Looking at the register values set by android vs the fex file, the correct
formula is "max(lcd_hv_hspw, 1)".

How can this be verified? Which hardware register needs to be read?

Register 0x01C0C054 "TCON0_BASIC3_REG", low 16 bits contain VSPW with 0-x
meaning a vspw value of 1 - (x + 1), high 16 bits contain HSPW in the same
format.

I can use Android to test this on Primo73 tablet, where the
hs/vs values are originally non-zero in fex.

BTW, I have done a preliminary automatic conversion for all FEX
files from sunxi-boards, which enable lcd0 in fex. The results are
now available at the all the same http://linux-sunxi.org/LCD wiki page.

Cool, thanks for doing this!

If "hs = lcd_hv_hspw + 1" is a better choice, then the whole table
probably needs to be re-generated.

Also additional explanations about GPIO related options (what would be
the exact rules to interpret FEX?) and more details about "lcd_frm" and
"lcd_if" would help a lot to get a better understanding about what
still needs to be done to get LCD displays supported on all devices.

Currently basically only lcd_if = 0 and lcd_frm = 1 are supported, it
should be possible to add support for other lcd_frm = x values easily,
so if you encounter those let me know, lcd_if != 0 is going to be much
harder to support and currently is not on my schedule.

It's all in the orange part of the table at the bottom. The lcd_frm = 0
seems to be relatively common. The links to FEX files for each device
are also there in the table and can be used to confirm the details.

The http://linux-sunxi.org/Wexler_TAB_7200 tablet with its fex file
https://github.com/linux-sunxi/sunxi-boards/blob/master/sys_config/a20/wexler_tab_7200.fex
is one of the examples.

Ok, so I've looked this up in the linux-sunxi code again to freshen my
memory, and grepping that code gives this:

drivers/video/sunxi/disp/ebios_lcdc_tve.h
51: LCDC_FRM_RGB888 = 0,
52: LCDC_FRM_RGB666 = 1,
53: LCDC_FRM_RGB656 = 2,

All 3 of which are already supported (but other then LCDC_FRM_RGB666
untested) in the u-boot lcd code :

LCDC_FRM_RGB888 -> depth:24
LCDC_FRM_RGB666 -> depth:18
LCDC_FRM_RGB656 -> depth:17

So this results in the following translation:

lcd_frm = 0 -> depth:24
lcd_frm = 1 -> depth:18
lcd_frm = 2 -> depth:17

If I understand it correctly, the kernel sources from the Allwinner SDK
contain the relevant code for handling the information from FEX, and
this code is the best reference. And it's more reliable to refer to
A23 SDK for interpreting the FEX files originally snatched from A23
devices, and likewise A31 SDK for A31 devices. For example, it is not
uncommon to see both 'lcd_pwm_used' and 'lcd_pwm_not_used' variables
defined in FEX. And sometimes the values of these variables even
contradict each other. So the fine details about the relative
priorities of these variables and other similar things might need
to be discovered for perfectly correct conversion.

All I can say here is that I agree with the above, I'm afraid I'm not
familiar enough with the (quite large) sunxi display code in the SDK
kernels to provide answers here.

I'm not familiar with that code either. I have just started looking at
these sources, searching for some answers. For example, that's where
I found the information about the 'pwm0_para' section and some other
things. SDK is not useful for anything other than the FEX interpretation
details. For implemen

Re: [U-Boot] [PATCH 15/17] sunxi: Ippo_q8h defconfigs: Enable the LCD panel found on these tablets.


Hi,

On 30-12-14 12:25, Siarhei Siamashka wrote:

On Tue, 30 Dec 2014 11:36:23 +0100
Hans de Goede  wrote:


Hi,

On 30-12-14 11:26, Hans de Goede wrote:

Hi,

On 30-12-14 11:18, Siarhei Siamashka wrote:





BTW, I have done a preliminary automatic conversion for all FEX
files from sunxi-boards, which enable lcd0 in fex. The results are
now available at the all the same http://linux-sunxi.org/LCD wiki page.


Cool, thanks for doing this!


I've just taken a look, looks good, as for the yellow entries with:

# warning: could not decode 'lcd_power' (port:power0<1><0><1>)

Those should be translated to:

CONFIG_VIDEO_LCD_FOO="AXP0-0" for power0
CONFIG_VIDEO_LCD_FOO="AXP0-1" for power1


Is this supported only for AXP209 so far?


Yes.


What about the devices with a different PMIC?


Adding support for those should be easy to do on an as needed basis,
and will use the same string notation. The string parsing code is
generic and not isolated to axp209.c .




And I think you can also drop the:

"# warning: 'lcd_pwm' gpio extracted from 'pwm0_para' section"

That seems to be the right thing todo for A23 at least.


OK. Right now it looks up the "pwmX_para" section, where X is the
number from "lcd_pwm_ch" found in the "lcd0_para" section.

Thanks for your comments and clarifications.


You're welcome, thanks for your work on this.

Regards,

Hans

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Re: [U-Boot] [PATCH] sun7i: Add new Bananapro board / defconfig

2014-12-31 Thread Ian Campbell

On Wed, 2014-12-31 at 11:38 +0100, Hans de Goede wrote:
> Add support for the new Bananapro A20 development board from lemaker.org.
> This board features 1G RAM, 2 USB A receptacles, 1 micro USB receptacle for
> OTG, 1 micro USB receptacle for power, HDMI, sata, Gbit ethernet, ir receiver,
> 3.5 mm jack for a/v out, on board microphone, 40 gpio pins and sdio wifi.
> 
> Signed-off-by: Hans de Goede 

Acked-by: Ian Campbell 

> -#ifdef CONFIG_TARGET_BANANAPI
> +#if defined CONFIG_TARGET_BANANAPI || defined CONFIG_TARGET_BANANAPRO
>   setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);

Did we ever get to the bottom of what this was?

I take it that you've confirmed it is needed for the pro, rather than
just carrying it over?

Ian.


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[U-Boot] [PATCH] sun7i: Add new Bananapro board / defconfig

Add support for the new Bananapro A20 development board from lemaker.org.
This board features 1G RAM, 2 USB A receptacles, 1 micro USB receptacle for
OTG, 1 micro USB receptacle for power, HDMI, sata, Gbit ethernet, ir receiver,
3.5 mm jack for a/v out, on board microphone, 40 gpio pins and sdio wifi.

Signed-off-by: Hans de Goede 
---
 board/sunxi/Kconfig | 4 
 board/sunxi/Makefile| 1 +
 board/sunxi/gmac.c  | 2 +-
 configs/Bananapro_defconfig | 9 +
 4 files changed, 15 insertions(+), 1 deletion(-)
 create mode 100644 configs/Bananapro_defconfig

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 0cbfb26..8782394 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -97,6 +97,10 @@ config TARGET_BANANAPI
bool "BANANAPI"
depends on MACH_SUN7I
 
+config TARGET_BANANAPRO
+   bool "BANANAPRO"
+   depends on MACH_SUN7I
+
 config TARGET_COLOMBUS
bool "COLOMBUS"
depends on MACH_SUN6I
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 97aff10..8ca01f6 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_TARGET_A20_OLINUXINO_M)  += 
dram_sun7i_384_1024_iow16.o
 obj-$(CONFIG_TARGET_AUXTEK_T004)   += dram_a10s_olinuxino_m.o
 obj-$(CONFIG_TARGET_BA10_TV_BOX)   += dram_sun4i_384_1024_iow8.o
 obj-$(CONFIG_TARGET_BANANAPI)  += dram_bananapi.o
+obj-$(CONFIG_TARGET_BANANAPRO) += dram_bananapi.o
 obj-$(CONFIG_TARGET_CUBIEBOARD)+= dram_cubieboard.o
 obj-$(CONFIG_TARGET_CUBIEBOARD2)   += dram_cubieboard2.o
 obj-$(CONFIG_TARGET_CUBIETRUCK)+= dram_cubietruck.o
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 571bc9e..4e4615e 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -34,7 +34,7 @@ int sunxi_gmac_initialize(bd_t *bis)
 * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain"
 * of the GMAC clk register to 3.
 */
-#ifdef CONFIG_TARGET_BANANAPI
+#if defined CONFIG_TARGET_BANANAPI || defined CONFIG_TARGET_BANANAPRO
setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
 #endif
 
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
new file mode 100644
index 000..7f9ce13
--- /dev/null
+++ b/configs/Bananapro_defconfig
@@ -0,0 +1,9 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-bananapro.dtb"
+CONFIG_USB1_VBUS_PIN="PH0"
+CONFIG_USB2_VBUS_PIN="PH1"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_BANANAPRO=y
-- 
2.1.0

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Re: [U-Boot] [PATCH v4 0/5] qspi: qspi support for mx6sxsabresd

2014-12-31 Thread Peng Fan




On 12/31/2014 5:35 PM, Jagan Teki wrote:

On 31 December 2014 at 08:31, Peng Fan  wrote:

This patch set is to support qspi for mx6sxsabresd board.

To mx6sxsabresd Revb board, 32M flash is used, but in header file,
CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M. The LUT
initialization qspi_set_lut function uses 32BIT addr, however
CONFIG_SPI_FLASH_BAR  and 24BIT addr should be used to access
bigger than 16MB size flash, and BRRD/BRWR should also be supported.
Future patches will fix this.


Please do remember your self, for next patches. of-course I have added this
note on "[U-Boot,v4,5/5] imx:mx6sxsabresd add qspi support" commit body.



Thanks. Actually I am doing the work.



Since flash opcodes are not recommended to use in driver level, use
QSPI_CMD_xx to replace OPCODE_xx. It is qspi controller's feature
to program LUT with QSPI_CMD_xx which same value with OPCODE_xx.

Since Revb board's qspi flash support 4K erase, 4K erase is added in driver.

Peng Fan (5):
   QuadSPI: use QSPI_CMD_xx instead of flash opcodes
   QuadSPI: use correct amba_base
   arm:mx6sx add QSPI support
   imx:qspi add 4K erase support
   imx:mx6sxsabresd add qspi support

  arch/arm/cpu/armv7/mx6/clock.c  |  50 ++
  arch/arm/include/asm/arch-mx6/clock.h   |   1 +
  arch/arm/include/asm/arch-mx6/imx-regs.h|  12 +--
  board/freescale/mx6sxsabresd/mx6sxsabresd.c |  40 
  drivers/spi/fsl_qspi.c  | 137 +++-
  include/configs/mx6sxsabresd.h  |  12 +++
  6 files changed, 205 insertions(+), 47 deletions(-)

--
1.8.4




Applied to u-boot-spi/master

thanks!


Regards,
Peng.
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Re: [U-Boot] [PATCH v4 0/5] qspi: qspi support for mx6sxsabresd

2014-12-31 Thread Jagan Teki

On 31 December 2014 at 08:31, Peng Fan  wrote:
> This patch set is to support qspi for mx6sxsabresd board.
>
> To mx6sxsabresd Revb board, 32M flash is used, but in header file,
> CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M. The LUT
> initialization qspi_set_lut function uses 32BIT addr, however
> CONFIG_SPI_FLASH_BAR  and 24BIT addr should be used to access
> bigger than 16MB size flash, and BRRD/BRWR should also be supported.
> Future patches will fix this.

Please do remember your self, for next patches. of-course I have added this
note on "[U-Boot,v4,5/5] imx:mx6sxsabresd add qspi support" commit body.

>
> Since flash opcodes are not recommended to use in driver level, use
> QSPI_CMD_xx to replace OPCODE_xx. It is qspi controller's feature
> to program LUT with QSPI_CMD_xx which same value with OPCODE_xx.
>
> Since Revb board's qspi flash support 4K erase, 4K erase is added in driver.
>
> Peng Fan (5):
>   QuadSPI: use QSPI_CMD_xx instead of flash opcodes
>   QuadSPI: use correct amba_base
>   arm:mx6sx add QSPI support
>   imx:qspi add 4K erase support
>   imx:mx6sxsabresd add qspi support
>
>  arch/arm/cpu/armv7/mx6/clock.c  |  50 ++
>  arch/arm/include/asm/arch-mx6/clock.h   |   1 +
>  arch/arm/include/asm/arch-mx6/imx-regs.h|  12 +--
>  board/freescale/mx6sxsabresd/mx6sxsabresd.c |  40 
>  drivers/spi/fsl_qspi.c  | 137 
> +++-
>  include/configs/mx6sxsabresd.h  |  12 +++
>  6 files changed, 205 insertions(+), 47 deletions(-)
>
> --
> 1.8.4
>
>

Applied to u-boot-spi/master

thanks!
-- 
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Re: [U-Boot] [PATCH] imx:mx6slevk add spi nor boot support

2014-12-31 Thread Jagan Teki

On 31 December 2014 at 08:56, Peng Fan  wrote:
> Hi Jagan,
>
>
> On 12/30/2014 8:38 PM, Jagan Teki wrote:
>>
>> On 30 December 2014 at 08:44, Peng Fan  wrote:
>>>
>>> Add spi nor boot support for mx6slevk board.
>>>
>>> Signed-off-by: Peng Fan 
>>> ---
>>>   board/freescale/mx6slevk/MAINTAINERS |  1 +
>>>   configs/mx6slevk_spinor_defconfig|  3 +++
>>>   include/configs/mx6slevk.h   | 13 -
>>>   3 files changed, 16 insertions(+), 1 deletion(-)
>>>   create mode 100644 configs/mx6slevk_spinor_defconfig
>>>
>>> diff --git a/board/freescale/mx6slevk/MAINTAINERS
>>> b/board/freescale/mx6slevk/MAINTAINERS
>>> index 660af91..18d31a8 100644
>>> --- a/board/freescale/mx6slevk/MAINTAINERS
>>> +++ b/board/freescale/mx6slevk/MAINTAINERS
>>> @@ -4,3 +4,4 @@ S:  Maintained
>>>   F: board/freescale/mx6slevk/
>>>   F: include/configs/mx6slevk.h
>>>   F: configs/mx6slevk_defconfig
>>> +F: configs/mx6slevk_spinor_defconfig
>>> diff --git a/configs/mx6slevk_spinor_defconfig
>>> b/configs/mx6slevk_spinor_defconfig
>>> new file mode 100644
>>> index 000..93efe73
>>> --- /dev/null
>>> +++ b/configs/mx6slevk_spinor_defconfig
>>> @@ -0,0 +1,3 @@
>>>
>>> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR"
>>> +CONFIG_ARM=y
>>> +CONFIG_TARGET_MX6SLEVK=y
>>> diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
>>> index e3e7f76..e6c4130 100644
>>> --- a/include/configs/mx6slevk.h
>>> +++ b/include/configs/mx6slevk.h
>>> @@ -187,9 +187,20 @@
>>>   /* FLASH and environment organization */
>>>   #define CONFIG_SYS_NO_FLASH
>>>
>>> -#define CONFIG_ENV_OFFSET  (6 * SZ_64K)
>>>   #define CONFIG_ENV_SIZESZ_8K
>>> +
>>> +#if defined CONFIG_SYS_BOOT_SPINOR
>>> +#define CONFIG_ENV_IS_IN_SPI_FLASH
>>> +#define CONFIG_ENV_OFFSET   (768 * 1024)
>>> +#define CONFIG_ENV_SECT_SIZE(64 * 1024)
>>> +#define CONFIG_ENV_SPI_BUS  CONFIG_SF_DEFAULT_BUS
>>> +#define CONFIG_ENV_SPI_CS   CONFIG_SF_DEFAULT_CS
>>> +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
>>> +#define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
>>
>>
>> If you need default values may be you couldn't define these so-that
>> common/env_sf.c
>> will take the defaults for undefs - please check.
>>
>
> Default values are defined in mx6slevk.h
>
> #define CONFIG_SF_DEFAULT_BUS  0
> #define CONFIG_SF_DEFAULT_CS   0
> #define CONFIG_SF_DEFAULT_SPEED 2000
> #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
>
> In env_sf.c
> I did not see any undefs, there is only a piece of code like:
> #ifndef CONFIG_ENV_SPI_BUS
> #define CONFIG_ENV_SPI_BUS 0
> #endif
>
>>> +#else
>>> +#define CONFIG_ENV_OFFSET  (6 * SZ_64K)
>>>   #define CONFIG_ENV_IS_IN_MMC
>>> +#endif
>>>
>>>   #define CONFIG_OF_LIBFDT
>>>   #define CONFIG_CMD_BOOTZ
>>> --
>>> 1.8.4

Applied to u-boot-spi/master

thanks!
-- 
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[U-Boot] [PATCH v2] x86: ahci: Make sure interface is not busy after enabling the port

Each time U-Boot boots on Intel Crown Bay board, the displayed hard
drive information is wrong. It could be either wrong capacity or just
a 'Capacity: not available' message. After enabling the debug switch,
we can see the scsi inquiry command did not execute successfully.
However, doing a 'scsi scan' in the U-Boot shell does not expose
this issue.

SCSI:  Target spinup took 0 ms.
SATA link 1 timeout.
AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
ahci_device_data_io: 0 byte transferred.   <--- scsi inquiry fails
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
  Device 0: (0:0) Vendor: ATA Prod.:  Rev: ?8
  Type: Hard Disk
  Capacity: 912968.3 MB = 891.5 GB (1869759264 x 512)
  Found 1 device(s).

So uninitialized contents on the stack were passed to dev_print() to
display those wrong information.

The symptom were observed on two hard drives (one is Seagate, the
other one is Western Digital). The fix is to make sure the AHCI
interface is not busy by checking the error and status information
from task file register after enabling the port in ahci_port_start()
before proceeding other operations like scsi_scan().

Signed-off-by: Bin Meng 

---

Changes in v2:
- Return error codes in ahci_port_start() when timeout
- Use get_timer() instead of plain loop when checking tfdata status

 drivers/block/ahci.c | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index c9a3beb..bbc7e7d 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -500,6 +500,20 @@ static void ahci_set_feature(u8 port)
 }
 #endif
 
+static int wait_spinup(volatile u8 *port_mmio)
+{
+   ulong start;
+   u32 tf_data;
+
+   start = get_timer(0);
+   do {
+   tf_data = readl(port_mmio + PORT_TFDATA);
+   if (!(tf_data & ATA_BUSY))
+   return 0;
+   } while (get_timer(start) < WAIT_MS_SPINUP);
+
+   return -ETIMEDOUT;
+}
 
 static int ahci_port_start(u8 port)
 {
@@ -566,7 +580,11 @@ static int ahci_port_start(u8 port)
 
debug("Exit start port %d\n", port);
 
-   return 0;
+   /*
+* Make sure interface is not busy based on error and status
+* information from task file data register before proceeding
+*/
+   return wait_spinup(port_mmio);
 }
 
 
-- 
1.8.2.1

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Re: [U-Boot] [PATCH] x86: Simplify the fsp hob access functions

Hi Simon,

On Wed, Dec 31, 2014 at 7:02 AM, Simon Glass  wrote:
> Hi Bin,
>
> On 30 December 2014 at 01:02, Bin Meng  wrote:
>> Remove the troublesome union hob_pointers so that some annoying casts
>> are no longer needed in those hob access routines. This also improves
>> the readability.
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>  arch/x86/cpu/queensbay/fsp_support.c   | 95 
>> --
>>  arch/x86/cpu/queensbay/tnc_dram.c  | 39 +
>>  arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h  | 46 ---
>>  .../include/asm/arch-queensbay/fsp/fsp_support.h   |  5 +-
>>  arch/x86/lib/cmd_hob.c | 16 ++--
>>  5 files changed, 101 insertions(+), 100 deletions(-)
>>
>
> Yes a big improvement - see a few additional ideas for a follow-on patch 
> below.
>
> Acked-by: Simon Glass 
>
>> diff --git a/arch/x86/cpu/queensbay/fsp_support.c 
>> b/arch/x86/cpu/queensbay/fsp_support.c
>> index ef1916b..4764e3c 100644
>> --- a/arch/x86/cpu/queensbay/fsp_support.c
>> +++ b/arch/x86/cpu/queensbay/fsp_support.c
>> @@ -231,26 +231,28 @@ u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase)
>>
>>  u32 fsp_get_usable_lowmem_top(const void *hob_list)
>>  {
>> -   union hob_pointers hob;
>> +   const struct hob_header *hdr;
>> +   struct hob_res_desc *res_desc;
>> phys_addr_t phys_start;
>> u32 top;
>>
>> /* Get the HOB list for processing */
>> -   hob.raw = (void *)hob_list;
>> +   hdr = hob_list;
>>
>> /* * Collect memory ranges */
>> top = FSP_LOWMEM_BASE;
>> -   while (!end_of_hob(hob)) {
>> -   if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
>> -   if (hob.res_desc->type == RES_SYS_MEM) {
>> -   phys_start = hob.res_desc->phys_start;
>> +   while (!end_of_hob(hdr)) {
>> +   if (get_hob_type(hdr) == HOB_TYPE_RES_DESC) {
>> +   res_desc = (struct hob_res_desc *)hdr;
>> +   if (res_desc->type == RES_SYS_MEM) {
>> +   phys_start = res_desc->phys_start;
>> /* Need memory above 1MB to be collected 
>> here */
>> if (phys_start >= FSP_LOWMEM_BASE &&
>> phys_start < 
>> (phys_addr_t)FSP_HIGHMEM_BASE)
>> -   top += (u32)(hob.res_desc->len);
>> +   top += (u32)(res_desc->len);
>> }
>> }
>> -   hob.raw = get_next_hob(hob);
>> +   hdr = get_next_hob(hdr);
>> }
>>
>> return top;
>> @@ -258,25 +260,27 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
>>
>>  u64 fsp_get_usable_highmem_top(const void *hob_list)
>>  {
>> -   union hob_pointers hob;
>> +   const struct hob_header *hdr;
>> +   struct hob_res_desc *res_desc;
>> phys_addr_t phys_start;
>> u64 top;
>>
>> /* Get the HOB list for processing */
>> -   hob.raw = (void *)hob_list;
>> +   hdr = hob_list;
>>
>> /* Collect memory ranges */
>> top = FSP_HIGHMEM_BASE;
>> -   while (!end_of_hob(hob)) {
>> -   if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
>> -   if (hob.res_desc->type == RES_SYS_MEM) {
>> -   phys_start = hob.res_desc->phys_start;
>> +   while (!end_of_hob(hdr)) {
>> +   if (get_hob_type(hdr) == HOB_TYPE_RES_DESC) {
>> +   res_desc = (struct hob_res_desc *)hdr;
>> +   if (res_desc->type == RES_SYS_MEM) {
>> +   phys_start = res_desc->phys_start;
>> /* Need memory above 1MB to be collected 
>> here */
>> if (phys_start >= 
>> (phys_addr_t)FSP_HIGHMEM_BASE)
>> -   top += (u32)(hob.res_desc->len);
>> +   top += (u32)(res_desc->len);
>> }
>> }
>> -   hob.raw = get_next_hob(hob);
>> +   hdr = get_next_hob(hdr);
>> }
>>
>> return top;
>> @@ -285,24 +289,26 @@ u64 fsp_get_usable_highmem_top(const void *hob_list)
>>  u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
>>struct efi_guid *guid)
>>  {
>> -   union hob_pointers hob;
>> +   const struct hob_header *hdr;
>> +   struct hob_res_desc *res_desc;
>>
>> /* Get the HOB list for processing */
>> -   hob.raw = (void *)hob_list;
>> +   hdr = hob_list;
>>
>> /* Collect memory ranges */
>> -   while (!end_of_hob(hob)) {
>> -   if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
>> -   if (hob.res_desc->type == RES_MEM_RESERVED) {
>> -   if (com

[U-Boot] [PATCH v4 4/4] x86: crownbay: Add pci devices in the dts file

The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.

Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.

Signed-off-by: Bin Meng 

---

Changes in v4:
- Add , after pciclass in the pci compatible string per spec
- Drop the first 3 patches which are already applied

Changes in v3: None
Changes in v2:
- New patch to add pci devices in crownbay.dts
- Drop v1 patch: Add an API for finding pci devices in the early phase
- Drop v1 patch: Support PCI UART in the x86_serial driver
- Drop v1 patch: Add PCI UART related defines in crownbay.h

 arch/x86/dts/crownbay.dts | 81 +++
 1 file changed, 81 insertions(+)

diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 97f7a52..e81054e 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -32,6 +32,14 @@
};
 
chosen {
+   /*
+* By default the legacy superio serial port is used as the
+* U-Boot serial console. If we want to use UART from Topcliff
+* PCH as the console, change this property to &pciuart#.
+*
+* For example, stdout-path = &pciuart0 will use the first
+* UART on Topcliff PCH.
+*/
stdout-path = "/serial";
};
 
@@ -52,4 +60,77 @@
};
};
 
+   pci {
+   #address-cells = <3>;
+   #size-cells = <2>;
+   compatible = "intel,pci";
+   device_type = "pci";
+
+   pcie@17,0 {
+   #address-cells = <3>;
+   #size-cells = <2>;
+   compatible = "intel,pci";
+   device_type = "pci";
+
+   topcliff@0,0 {
+   #address-cells = <3>;
+   #size-cells = <2>;
+   compatible = "intel,pci";
+   device_type = "pci";
+
+   pciuart0: uart@a,1 {
+   compatible = "pci8086,8811.00",
+   "pci8086,8811",
+   "pciclass,070002",
+   "pciclass,0700",
+   "x86-uart";
+   reg = <0x00025100 0x0 0x0 0x0 0x0
+  0x01025110 0x0 0x0 0x0 0x0>;
+   reg-shift = <0>;
+   clock-frequency = <1843200>;
+   current-speed = <115200>;
+   };
+
+   pciuart1: uart@a,2 {
+   compatible = "pci8086,8812.00",
+   "pci8086,8812",
+   "pciclass,070002",
+   "pciclass,0700",
+   "x86-uart";
+   reg = <0x00025200 0x0 0x0 0x0 0x0
+  0x01025210 0x0 0x0 0x0 0x0>;
+   reg-shift = <0>;
+   clock-frequency = <1843200>;
+   current-speed = <115200>;
+   };
+
+   pciuart2: uart@a,3 {
+   compatible = "pci8086,8813.00",
+   "pci8086,8813",
+   "pciclass,070002",
+   "pciclass,0700",
+   "x86-uart";
+   reg = <0x00025300 0x0 0x0 0x0 0x0
+  0x01025310 0x0 0x0 0x0 0x0>;
+   reg-shift = <0>;
+   clock-frequency = <1843200>;
+   current-speed = <115200>;
+   };
+
+   pciuart3: uart@a,4 {
+   compatible = "pci8086,8814.00",
+   "pci8086,8814",
+   "pciclass,070002",
+   "pciclass,0700"

[U-Boot] [PATCH v4 3/4] x86: Use ePAPR defined properties for x86-uart

Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.

Signed-off-by: Bin Meng 
Acked-by: Simon Glass 

---

Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to use ePAPR defined properties for x86-uart

 arch/x86/dts/serial.dtsi| 5 ++---
 drivers/serial/serial_x86.c | 8 +++-
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
index ebdda76..9b097f4 100644
--- a/arch/x86/dts/serial.dtsi
+++ b/arch/x86/dts/serial.dtsi
@@ -3,8 +3,7 @@
compatible = "x86-uart";
reg = <0x3f8 8>;
reg-shift = <0>;
-   io-mapped = <1>;
-   multiplier = <1>;
-   baudrate = <115200>;
+   clock-frequency = <1843200>;
+   current-speed = <115200>;
};
 };
diff --git a/drivers/serial/serial_x86.c b/drivers/serial/serial_x86.c
index e81e035..4bf6062 100644
--- a/drivers/serial/serial_x86.c
+++ b/drivers/serial/serial_x86.c
@@ -6,9 +6,12 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static const struct udevice_id x86_serial_ids[] = {
{ .compatible = "x86-uart" },
{ }
@@ -22,10 +25,13 @@ static int x86_serial_ofdata_to_platdata(struct udevice 
*dev)
ret = ns16550_serial_ofdata_to_platdata(dev);
if (ret)
return ret;
-   plat->clock = 1843200;
+
+   plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+"clock-frequency", 1843200);
 
return 0;
 }
+
 U_BOOT_DRIVER(serial_ns16550) = {
.name   = "serial_x86",
.id = UCLASS_SERIAL,
-- 
1.8.2.1

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[U-Boot] [PATCH v4 2/4] serial: ns16550: Support ns16550 compatible pci uart devices

There are many pci uart devices which are ns16550 compatible. We can
describe them in the board dts file and use it as the U-Boot serial
console as specified in the chosen node 'stdout-path' property.

Those pci uart devices can have their register be memory-mapped, or
i/o-mapped. The driver will try to use the memory-mapped register if
the reg property in the node has an entry to describe the memory-mapped
register, otherwise i/o-mapped register will be used.

Signed-off-by: Bin Meng 
Acked-by: Simon Glass 

---

Changes in v4: None
Changes in v3:
- Update to use 'memory-mapped' and 'i/o-mapped' in several places
- Use 'Processor Local Bus' instead of 'plb'
- Change the logic in ns16550_serial_ofdata_to_platdata() to avoid goto

Changes in v2:
- New patch to support ns16550 compatible pci uart devices

 drivers/serial/ns16550.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index af5beba..70c9462 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -289,7 +289,38 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
struct ns16550_platdata *plat = dev->platdata;
fdt_addr_t addr;
 
+   /* try Processor Local Bus device first */
addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+#ifdef CONFIG_PCI
+   if (addr == FDT_ADDR_T_NONE) {
+   /* then try pci device */
+   struct fdt_pci_addr pci_addr;
+   u32 bar;
+   int ret;
+
+   /* we prefer to use a memory-mapped register */
+   ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
+ FDT_PCI_SPACE_MEM32, "reg",
+ &pci_addr);
+   if (ret) {
+   /* try if there is any i/o-mapped register */
+   ret = fdtdec_get_pci_addr(gd->fdt_blob,
+ dev->of_offset,
+ FDT_PCI_SPACE_IO,
+ "reg", &pci_addr);
+   if (ret)
+   return ret;
+   }
+
+   ret = fdtdec_get_pci_bar32(gd->fdt_blob, dev->of_offset,
+  &pci_addr, &bar);
+   if (ret)
+   return ret;
+
+   addr = bar;
+   }
+#endif
+
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
 
-- 
1.8.2.1

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[U-Boot] [PATCH v4 0/4] x86: Support pci based uart as the U-Boot serial console

This series add support to the ns16550 compatible pci devices.

Newer x86 Platform Controller Hub chipset (like Topcliff, BayTrail)
starts to integrate ns16550 compatible pci uart devices. In order to
use them, we have to scan the pci bus and allocate memory/io address
in the early phase. A gd->hose is added to save the pci bus controller
hose in the early phase so that pci apis can be used.

On Intel Crown Bay board, there are 4 DB9 connectors, one of which
is from the superio legacy serial port and the other 3 are connected
to the Topcliff PCH UART devices. In order to use them as the U-Boot
serial console, we need describe those devices in the board's dts
file per Open Firmware PCI bus bindings and specify it as the console
via the 'stdout-path' in the chosen node. Several APIs are added in
fdtdec.c to provide help for decoding the pci device nodes.

Changes in v4:
- Check compatible string 12th byte against '\0'
- Add , after pciclass in the pci compatible string per spec
- Drop the first 3 patches which are already applied

Changes in v3:
- Fixed a typo: parant -> parent
- Return better error code in fdtdec_get_pci_addr()
- Add some debug output in fdtdec_get_pci_addr()
- Reuse variable 'len' instead of creating a new one 'l'
- Check compatible string length and existence of '.'
- Using simple_strtol() directly on the compatible sub-string
- Change variable 'bn' to 'barnum' which is self-documenting
- Update to use 'memory-mapped' and 'i/o-mapped' in several places
- Use 'Processor Local Bus' instead of 'plb'
- Change the logic in ns16550_serial_ofdata_to_platdata() to avoid goto

Changes in v2:
- New patch to add several apis to decode pci device node
- New patch to support ns16550 compatible pci uart devices
- New patch to use ePAPR defined properties for x86-uart
- New patch to add pci devices in crownbay.dts
- Drop v1 patch: Add an API for finding pci devices in the early phase
- Drop v1 patch: Support PCI UART in the x86_serial driver
- Drop v1 patch: Add PCI UART related defines in crownbay.h

Bin Meng (4):
  fdt: Add several apis to decode pci device node
  serial: ns16550: Support ns16550 compatible pci uart devices
  x86: Use ePAPR defined properties for x86-uart
  x86: crownbay: Add pci devices in the dts file

 arch/x86/dts/crownbay.dts   |  81 +
 arch/x86/dts/serial.dtsi|   5 +-
 drivers/serial/ns16550.c|  31 
 drivers/serial/serial_x86.c |   8 ++-
 include/fdtdec.h| 108 +---
 lib/fdtdec.c| 171 
 6 files changed, 375 insertions(+), 29 deletions(-)

-- 
1.8.2.1

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[U-Boot] [PATCH v4 1/4] fdt: Add several apis to decode pci device node