On Wed, 2016-07-27 at 00:28 +0200, Hans de Goede wrote:
> Disable the sun8i emac driver for now, there are 2 issues with it:
>
> 1) It is causing issues with network connectivity under the kernel
> driver,
> when booting the kernel with v2 of Corentin's sun8i-h3 emac driver, I
> get
> the
On Wed, 2016-07-27 at 00:28 +0200, Hans de Goede wrote:
> There is a new Orange Pi PC *Plus* version available now,
> this is an extended version of the regular Orange Pi PC
> with sdio wifi and an eMMC.
>
> The upstream kernel devs have decided that they want a separate
> dts for the PC Plus
Hi Tom,
>
> I'm confused because I both can't replicate my problem but know I
> checked in drivers/misc for output (I use O= always).
I have no idea.
I tried with O=
and drivers/misc/i2c_eeprom.o was built as well.
>> > And
>> > moveconfig.py also didn't see it needed.
>>
>> This is
On 27 July 2016 at 12:54, Siva Durga Prasad Paladugu
wrote:
> Hi Jagan,
>
>> -Original Message-
>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
>> Sent: Tuesday, July 26, 2016 11:16 AM
>> To: Siva Durga Prasad Paladugu
>> Cc:
On 19 July 2016 at 14:40, Siva Durga Prasad Paladugu
wrote:
> Dont set quad enable for micron devices in all cases
> Setting the quad enable bit in micron expects all other
> commands like register reads on quad lines which may
> not be supported by some
On 25 July 2016 at 19:08, Tom Rini wrote:
> On Mon, Jul 25, 2016 at 03:45:46PM +0530, Vignesh R wrote:
>
>> Now that QSPI driver can support 76.8MHz, update the
>> CONFIG_SF_DEFAULT_SPEED to the same value.
>>
>> Signed-off-by: Vignesh R
>
> Reviewed-by: Tom
On 25 July 2016 at 15:45, Vignesh R wrote:
> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
> the driver to use the same.
>
> Signed-off-by: Vignesh R
> ---
> drivers/spi/ti_qspi.c | 17 -
> 1 file changed, 12
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Wednesday, July 27, 2016 1:24 PM
> To: Siva Durga Prasad Paladugu
> Cc: u-boot@lists.denx.de; Michal Simek ; Siva Durga
> Prasad Paladugu
Please resend the patch, patchwork mbox download shows different.
On 24 July 2016 at 00:49, Lad, Prabhakar wrote:
> On Sat, Jul 23, 2016 at 5:19 PM, Jagan Teki wrote:
>>
>> On 23 June 2016 at 19:28, Lad, Prabhakar
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, July 26, 2016 11:16 AM
> To: Siva Durga Prasad Paladugu
> Cc: u-boot@lists.denx.de; Michal Simek ; Siva Durga
> Prasad Paladugu
On 19 July 2016 at 14:40, Siva Durga Prasad Paladugu
wrote:
> This adds QSPI driver support for ZynqMP platform
> This driver supports all spi flash commands in
> qspi single mode.
>
> Signed-off-by: Siva Durga Prasad Paladugu
> ---
> Changes
On 19 July 2016 at 21:18, Siva Durga Prasad Paladugu
wrote:
> This series enables the Quad and dual modes support
> for zynq. It also contains fixes for issues found
> during testing of dual parallel and stacked modes.
>
> Siva Durga Prasad Paladugu (9):
> spi:
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Wednesday, July 27, 2016 1:47 PM
> To: Siva Durga Prasad Paladugu
> Cc: u-boot@lists.denx.de; Michal Simek ; Siva Durga
> Prasad Paladugu
On 27 July 2016 at 14:31, Siva Durga Prasad Paladugu
wrote:
> Hi Jagan,
>
>> -Original Message-
>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
>> Sent: Wednesday, July 27, 2016 1:24 PM
>> To: Siva Durga Prasad Paladugu
>> Cc:
Hi York,
> -Original Message-
> From: york sun
> Sent: Tuesday, July 26, 2016 12:26 PM
> To: Qianyu Gong ; u-boot@lists.denx.de; Prabhakar
> Kushwaha ; Mingkai Hu
> Cc: Shaohui Xie ; Zhiqiang Hou
> -Original Message-
> From: york sun
> Sent: Tuesday, July 26, 2016 1:38 AM
> To: Yangbo Lu; u-boot@lists.denx.de
> Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620
>
> On 05/20/2016 03:20 AM, Yangbo Lu wrote:
> > Erratum Title:
> > Data timeout error not getting
On 27 July 2016 at 14:28, Siva Durga Prasad Paladugu
wrote:
> Hi Jagan,
>
>> -Original Message-
>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
>> Sent: Wednesday, July 27, 2016 1:47 PM
>> To: Siva Durga Prasad Paladugu
>> Cc:
On 2 of my H3 boards bytes 13-15 of the SID are all 0 leading to
the NIC specific bytes of the mac all being 0, which leads to the
boards not getting an ipv6 address from the dhcp server.
This commits adds a check to ensure this does not happen.
Cc: Chen-Yu Tsai
Cc: Corentin
On 02/23/2016 01:32 AM, Aneesh Bansal wrote:
> sec_init() which was earlier called in misc_init_r()
> is now done in board_init() before PPA init as SEC
> block will be used during PPA image validation.
>
> Signed-off-by: Aneesh Bansal
> ---
> The patchset is dependent on
>
Hi Tom
Missed this thread to reply.
>> index ef12f9f..ed3e295 100644
>> --- a/Kconfig
>> +++ b/Kconfig
>> @@ -336,6 +336,33 @@ config SPL_FIT_IMAGE_POST_PROCESS
>>injected into the FIT creation (i.e. the blobs would have been pre-
>>processed before being added to the FIT image).
On 27/07/16 00:43, Simon Glass wrote:
Hi Paul,
On 26 July 2016 at 16:24, Paul Burton wrote:
This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe
On 07/27/2016 12:10 AM, Yangbo Lu wrote:
>> -Original Message-
>> From: york sun
>> Sent: Tuesday, July 26, 2016 1:38 AM
>> To: Yangbo Lu; u-boot@lists.denx.de
>> Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620
>>
>> On 05/20/2016 03:20 AM, Yangbo Lu wrote:
>>>
On 27 July 2016 at 19:28, Tom Rini wrote:
> On Wed, Jul 27, 2016 at 06:58:24PM +0530, Jagan Teki wrote:
>> On 27 July 2016 at 04:06, Tom Rini wrote:
>> > On Mon, Jul 25, 2016 at 09:42:27AM +0200, Maxime Ripard wrote:
>> >> On Fri, Jul 15, 2016 at
It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID
are always 0 on H3 making it a poor candidate to use as source for the
serialnr / mac-address, switch to word1 which seems to be more random.
Cc: Chen-Yu Tsai
Cc: Corentin LABBE
Cc:
This fixes the following CACHE warnings when using sun8i_emac:
=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [7bf594a8, 7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [7bf59c90, 7bf59e10]
CACHE: Misaligned operation at range [7bf5a478,
With the recent bug fixes for the sun8i_emac driver all known issues
are resolved, so we can re-enable the driver.
While at it, also enable the emac on the Orange Pi One.
Cc: Chen-Yu Tsai
Cc: Corentin LABBE
Cc: Amit Singh Tomar
On Wed, Jul 27, 2016 at 06:58:24PM +0530, Jagan Teki wrote:
> On 27 July 2016 at 04:06, Tom Rini wrote:
> > On Mon, Jul 25, 2016 at 09:42:27AM +0200, Maxime Ripard wrote:
> >> On Fri, Jul 15, 2016 at 10:45:34AM +0200, Hans de Goede wrote:
> >> > Hi,
> >> >
> >> > On 04-07-16
HDMI output must be enabled very early to also enable the pre-console buffer
Signed-off-by: Soeren Moch
---
Cc: Stefano Babic
Cc: u-boot@lists.denx.de
---
include/configs/tbs2910.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA & an
Intel EG20T Platform Controller Hub, used largely as part of the
development of new CPUs and their software support. It is essentially
the successor to the older
The regmap_read & regmap_write functions were previously declared in
regmap.h but not implemented anywhere. The regmap implementation &
commit message of 6f98b7504f70 ("dm: Add support for register maps
(regmap)") indicate that only memory mapped accesses are supported for
now, so providing simple
Provide a trivial syscon driver matching the generic "syscon" compatible
string, allowing for simple system controllers to be used without a
custom driver just as in Linux.
Signed-off-by: Paul Burton
---
Changes in v2:
- New patch
drivers/core/syscon-uclass.c | 11
Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.
Signed-off-by: Paul Burton
The pch_gbe driver previously casted pointers to & from unsigned 32 bit
integers in many locations. This breaks the driver on 64 bit systems,
producing streams of compiler warnings about mismatched pointer &
integer sizes and then failing to keep track of addresses correctly at
runtime.
Fix the
Reading the PCI BAR & converting the result to a physical address is not
safe across all architectures. For example on MIPS the virtual:physical
mapping is not 1:1, so we cannot directly make use of the physical
address.
Use the more generic BAR-mapping function dm_pci_map_bar to discover the
In pci_uclass_pre_probe an attempt is made to detect whether the parent
of a device is a PCI device and that the device is thus a bridge. This
was being done by checking whether the parent of the device is of the
UCLASS_ROOT class. This causes problems if the PCI controller is a child
of some
This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe ECAM specification, but with some
quirks about what devices are valid to access.
Signed-off-by: Paul Burton
Import a copy of the dt-bindings/interrupt-controller/mips-gic.h header
from Linux, such that we can use device trees which include it without
modification.
Signed-off-by: Paul Burton
---
Changes in v2: None
include/dt-bindings/interrupt-controller/mips-gic.h | 9
On Wed, Jul 27, 2016 at 02:04:24PM +, B, Ravi wrote:
> Hi Tom
>
> Missed this thread to reply.
>
> >> index ef12f9f..ed3e295 100644
> >> --- a/Kconfig
> >> +++ b/Kconfig
> >> @@ -336,6 +336,33 @@ config SPL_FIT_IMAGE_POST_PROCESS
> >> injected into the FIT creation (i.e. the blobs would
'usb start' is much faster now, so always enable usb keyboard
Signed-off-by: Soeren Moch
---
Cc: Stefano Babic
Cc: u-boot@lists.denx.de
---
include/configs/tbs2910.h | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git
Previously ns16550 compatible UARTs probed via device tree have needed
their device tree nodes to contain a clock-frequency property. An
alternative to this commonly used with Linux is to reference a clock via
a phandle. This patch allows U-Boot to support that, retrieving the
clock frequency by
This series introduces initial support for the MIPS Boston, and FPGA
based development board & successor to the older Malta board. Further
peripheral work is needed but this introduces the basics.
This can be tested in a currently out-of-tree QEMU port if desired,
which can be found in the boston
On 07/19/2016 01:36 AM, Prabhakar Kushwaha wrote:
> LS1012AFRDM has 512MB of DDR.
> So update Kernel load address as 0x9600 instead of default
> 0xa000.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
> include/configs/ls1012afrdm.h | 16
> 1 file
On Tuesday 26 July 2016 11:53 AM, Heiko Schocher wrote:
> Hello Vignesh,
>
> Am 25.07.2016 um 12:56 schrieb Vignesh R:
>> As I2C can be used before DRAM initialization for reading EEPROM,
>> avoid using static variables stored in BSS, since BSS is in DRAM, which
>> may not have been initialised
Hi Jaehoon,
On 2016年07月28日 13:26, Jaehoon Chung wrote:
According to DesignWare TRM, FIFO_COUNT is bit[29:17].
If get the correct fifo_count value, it has to use the FIFO_MASK
as 0x1FFF, not 0x1FF.
Ah, I have no doubt the fifo_count defined. The fifo depth of Rockchip
SoCs is 256, the former
On Wed, 2016-07-27 at 18:10 +0200, Hans de Goede wrote:
> With the recent bug fixes for the sun8i_emac driver all known issues
> are resolved, so we can re-enable the driver.
>
> While at it, also enable the emac on the Orange Pi One.
>
> Cc: Chen-Yu Tsai
> Cc: Corentin LABBE
On Wed, 2016-07-27 at 18:10 +0200, Hans de Goede wrote:
> It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the
> SID
> are always 0 on H3 making it a poor candidate to use as source for
> the
> serialnr / mac-address, switch to word1 which seems to be more
> random.
>
> Cc: Chen-Yu
This commit allows injecting a board/platform/device-specific post-
processing function into the FIT image data loading process, which can
include modifying the size and altering the starting source address of
an image data artifact. This might be desired to do things like strip
headers or footers
On Tue, 26 Jul 2016 08:52:52 +0200
Anatolij Gustschin ag...@denx.de wrote:
> From: Alexey Brodkin
>
> This change introduces default_splash_locations which
> simplifies splash recovery from the first partition of
> USB/MMC/SATA drive.
>
> Given usual mapping of the
On Wed, 2016-07-27 at 18:10 +0200, Hans de Goede wrote:
> On 2 of my H3 boards bytes 13-15 of the SID are all 0 leading to
> the NIC specific bytes of the mac all being 0, which leads to the
> boards not getting an ipv6 address from the dhcp server.
>
> This commits adds a check to ensure this
On 07/27/2016 03:00 AM, Qianyu Gong wrote:
>
> Hi York,
>
>> -Original Message-
>> From: york sun
>> Sent: Tuesday, July 26, 2016 12:26 PM
>> To: Qianyu Gong ; u-boot@lists.denx.de; Prabhakar
>> Kushwaha ; Mingkai Hu
>>
On Wed, Jul 27, 2016 at 09:31:25PM +0530, Jagan Teki wrote:
> >> >> FWIW, if anyone is interested in taking over, I'm can help with the
> >> >> load if needed.
> >> >
> >> > I would also be quite happy to see a joint custodian setup similar to
> >> > how some of the Linux Kernel trees are handled,
Hello,
> index 7c088c3..877859c 100644
> --- a/drivers/net/sun8i_emac.c
> +++ b/drivers/net/sun8i_emac.c
> @@ -32,7 +32,8 @@
>
> #define CONFIG_TX_DESCR_NUM32
> #define CONFIG_RX_DESCR_NUM32
> -#define CONFIG_ETH_BUFSIZE 2024
> +#define CONFIG_ETH_BUFSIZE 2048
> +#define
On Wed, 2016-07-27 at 18:10 +0200, Hans de Goede wrote:
> This fixes the following CACHE warnings when using sun8i_emac:
>
> => dhcp
> BOOTP broadcast 1
> BOOTP broadcast 2
> CACHE: Misaligned operation at range [7bf594a8, 7bf59628]
> BOOTP broadcast 3
> CACHE: Misaligned operation at range
Hello,
I'm about to use U-Boot for an embedded project. I need a fallback
strategy if the network boot (no matter what exactly) fails e.g. no server
reached after a timeout period. In this case it should boot an linux image
from flash memory.
The U-Boot docs say nothing about that...
Hello Robert,
Am 27.07.2016 um 14:03 schrieb Robert P. J. Day:
On Tue, 26 Jul 2016, Heiko Schocher wrote:
... snip ...
it appears that, no matter what, the environment *is* updated
every single time because of this line in the bootdelay_process()
routine:
setenv_ulong("bootcount",
Hello,
I'm about to use U-Boot for an embedded project. I need a fallback
strategy if the network boot (no matter what exactly) fails e.g. no server
reached after a timeout period. In this case it should boot an linux image
from flash memory.
The U-Boot docs say nothing about that...
Hello,
I'm about to use U-Boot for an embedded project. I need a fallback
strategy if the network boot (no matter what exactly) fails e.g. no server
reached after a timeout period. In this case it should boot an linux image
from flash memory.
The U-Boot docs say nothing about that...
On 07/03/2016 09:37 PM, Rajesh Bhagat wrote:
>
>
> Will take care in v3.
>
Did you send v3 patch set?
York
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On Wed, Jul 27, 2016 at 08:10:08PM +0200, Maxime Ripard wrote:
> On Wed, Jul 27, 2016 at 09:31:25PM +0530, Jagan Teki wrote:
> > >> >> FWIW, if anyone is interested in taking over, I'm can help with the
> > >> >> load if needed.
> > >> >
> > >> > I would also be quite happy to see a joint
On 07/21/2016 04:45 AM, Marek Vasut wrote:
> On 07/21/2016 10:02 AM, Rajesh Bhagat wrote:
>> Hi All,
>>
>> Any Comments?
>
> York, please check this.
Passed compiling tests on powerpc and arm platforms.
York
>
>>> -Original Message-
>>> From: Rajesh Bhagat [mailto:rajesh.bha...@nxp.com]
On 07/20/2016 03:51 AM, Gong Qianyu wrote:
> The current code would always use the speed and mode set by
> CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
> SPI driver model it should get the values from DT.
>
> Signed-off-by: Gong Qianyu
> ---
>
Hello Hans,
On Wed, 27 Jul 2016 18:10:34 +0200
Hans de Goede wrote:
> It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID
> are always 0 on H3 making it a poor candidate to use as source for the
> serialnr / mac-address, switch to word1 which seems to be
Hi Tom,
On Mon, 25 Jul 2016 17:46:31 -0400
Tom Rini tr...@konsulko.com wrote:
...
> Hey, good catch. Anatolij, please fix and re-submit, thanks!
sandbox build fixed now, here is updated pull request:
The following changes since commit 19ce924ff914f315dc2fdf79f357825c513aed6e:
Prepare
Am 27.07.2016 um 16:26 schrieb Paul Burton:
> This patch introduces support for building U-Boot to run on the MIPS
> Boston development board. This is a board built around an FPGA & an
> Intel EG20T Platform Controller Hub, used largely as part of the
> development of new CPUs and their software
From: Bryan Wu
Tegra186 has 8 I2C controllers including BPMP I2C. This patch adds the
other 7 generic controllers to Tegra186's DT.
Signed-off-by: Bryan Wu
(swarren, fixed DT node sort order, tweak patch description)
Signed-off-by: Stephen Warren
From: Bryan Wu
Enable I2C devices in DT and enable building tegra_i2c.c driver.
Signed-off-by: Bryan Wu
(swarren, commit msg rework, fixed DT node sort order)
Signed-off-by: Stephen Warren
---
arch/arm/dts/tegra186-p2771-.dtsi | 35
From: Bryan Wu
clk/reset API was tested on T186 platform and previous chip like
T210/T124 will still use the old APIs.
Signed-off-by: Bryan Wu
(swarren, simplified some ifdefs, removed indent level inside an ifdef)
Signed-off-by: Stephen Warren
From: Stephen Warren
Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.
On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY)
From: Stephen Warren
The Tegra186 PCIe DT content is almost identical to previous chips, except
that the:
- There are 3 ports instead of 2.
- Some physical addresses have moved.
- PHY programming is handled by firmware, so CCPLEX DTs don't need to
reference any PHY.
- The
From: Stephen Warren
Introduce tegra_board_init() and call it from board_init(). Tegra wil use
tegra_board_init() for board-specific initialization, and board_init() for
SoC-specific initialization.
Signed-off-by: Stephen Warren
---
Pad configuration for SERIRQ is not set to enable the SERIRQ function
on soft reset though strangely, it is on initial boot.
Signed-off-by: George McCollister
---
arch/x86/dts/baytrail_som-db5800-som-6867.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git
On Wed, Jul 27, 2016 at 09:17:28PM +0200, Anatolij Gustschin wrote:
> Hi Tom,
>
> On Mon, 25 Jul 2016 17:46:31 -0400
> Tom Rini tr...@konsulko.com wrote:
> ...
> > Hey, good catch. Anatolij, please fix and re-submit, thanks!
>
> sandbox build fixed now, here is updated pull request:
>
> The
print_bi_boot_params outputs boot parameters structure location.
Signed-off-by: Max Filippov
---
cmd/bdinfo.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index f2435ab..60aaafb 100644
---
print_bi_flash outputs flashstart, flashsize and flashoffset lines.
Signed-off-by: Max Filippov
---
cmd/bdinfo.c | 54 +++---
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index
print_std_bdinfo outputs typical set of board information entries:
boot params location, memory and flash addresses and sizes, network
interfaces information and configured serial baud rate.
Signed-off-by: Max Filippov
---
cmd/bdinfo.c | 32
print_eth_ip_addr outputs eth configurations for up to 6 interfaces and
configured IP address.
Signed-off-by: Max Filippov
---
cmd/bdinfo.c | 113 +++
1 file changed, 36 insertions(+), 77 deletions(-)
diff --git
print_bi_mem outputs memstart and memsize lines.
Signed-off-by: Max Filippov
---
cmd/bdinfo.c | 42 ++
1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 60aaafb..df68b58 100644
---
Hi,
this series extracts common parts of cmd/bdinfo.c used by various
architectures into reusable functions.
Changes v1->v2:
- fix build for architectures w/o CONFIG_NR_DRAM_BANKS and bi_dram in
bd_t.
Please review.
Max Filippov (7):
cmd/bdinfo: extract print_bi_boot_params
cmd/bdinfo:
print_baudrate outputs serial baud rate.
Signed-off-by: Max Filippov
---
cmd/bdinfo.c | 39 +--
1 file changed, 25 insertions(+), 14 deletions(-)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 4ffb757..403ed3e 100644
--- a/cmd/bdinfo.c
print_bi_dram outputs start address and size for each DRAM bank.
Signed-off-by: Max Filippov
---
Changes v1->v2:
- fix build for architectures w/o CONFIG_NR_DRAM_BANKS and bi_dram in
bd_t.
cmd/bdinfo.c | 60 +++-
1
From: Stephen Warren
In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
(Boot and Power Management Processor). This change implements a driver
that does that. A tegra/ sub-directory is created to follow the existing
pattern. It is unconditionally
From: Stephen Warren
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. These bindings dictate how to
From: Stephen Warren
This adds the DT content that's needed to allow board DTs to enable use
of BPMP, clocks, resets, GPIOs, eMMC, and SD cards.
Signed-off-by: Stephen Warren
---
arch/arm/dts/tegra186.dtsi | 55
From: Stephen Warren
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. This driver provides the core
From: Stephen Warren
The DT binding for the Tegra186 HSP module apparently wasn't quite final
when I posted initial U-Boot support for it. Add the final DT binding doc
and adapt all code and DT files to match it.
Signed-off-by: Stephen Warren
---
From: Stephen Warren
In Tegra186, on-SoC reset signals are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that. It is unconditionally selected by CONFIG_TEGRA186
since virtually any Tegra186 build of
From: Stephen Warren
In Tegra186, SoC power domains are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that.
Signed-off-by: Stephen Warren
---
drivers/power/domain/Kconfig
From: Stephen Warren
Tegra186 supports the new standard clock and reset APIs. Older Tegra SoCs
still use custom APIs. Enhance the Tegra MMC driver so that it can operate
with either set of APIs.
Signed-off-by: Stephen Warren
Cc: Pantelis Antoniou
Hi,
On 07/27/2016 10:10 AM, Minkyu Kang wrote:
> Hi,
>
> On 26/07/16 19:06, Jaehoon Chung wrote:
>> buswidth isn't used anywhere in sdhci_setup_cfg.
>>
>> Signed-off-by: Jaehoon Chung
>> ---
>> drivers/mmc/msm_sdhci.c | 4 ++--
>> drivers/mmc/sdhci.c | 4 ++--
>>
out_be32 and in_be32 are actually #defined to little endian
writel/readl in arch/microblaze.
Just use __raw_writel/readl instead. That is also what is used
in the Linux kernel driver for this IP block
Tested on MIPSfpga. Can tftp a kernel.
Signed-off-by: Zubair Lutfullah Kakakhel
On Tue, 26 Jul 2016, Heiko Schocher wrote:
... snip ...
> > it appears that, no matter what, the environment *is* updated
> > every single time because of this line in the bootdelay_process()
> > routine:
> >
> >setenv_ulong("bootcount", bootcount);
> >
> > why? it seems, from the above,
Am 27.07.2016 um 12:51 schrieb Zubair Lutfullah Kakakhel:
> MIPSfpga is an FPGA based dev platform.
>
> In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks
>
> The FPGA dev board used is the Nexys4DDR board by Digilent.
>
> For more information, check the Readme file in
Hi Tom,
Could you help to assign this mmc patch reviewing to right person?
It seems no one had reviewed it for almost half year.
And another my mmc patch also needs to be reviewed.
I submitted in May. Please help.
http://patchwork.ozlabs.org/patch/624448/
Thank you very much.
Best regards,
On 07/27/2016 04:28 PM, Yangbo Lu wrote:
> Hi Tom,
>
> Could you help to assign this mmc patch reviewing to right person?
> It seems no one had reviewed it for almost half year.
>
> And another my mmc patch also needs to be reviewed.
> I submitted in May. Please help.
>
Using PSCI to reset the system.
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/zynqmp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index f15dc5d71522..0c5d9979316f 100644
---
On Wed, Jul 27, 2016 at 03:42:40PM +0900, Masahiro Yamada wrote:
[snip]
> The tool will show as follows:
>
> uniphier_ld4_sld8_defconfig
> CONFIG_I2C_EEPROM is not defined in Kconfig. Do nothing.
>
>
> This is the message.
>
>
>
> - CONFIG_... is not defined in Kconfig. Do nothing.
>
On 27/07/16 12:37, Daniel Schwierzeck wrote:
+#define EXT(field) ((mmcmdiv & field) >> (ffs(field) - 1))
+
+ in_rate = EXT(BOSTON_PLAT_MMCMDIV_INPUT);
+ mul = EXT(BOSTON_PLAT_MMCMDIV_MUL);
+ clk0_div = EXT(BOSTON_PLAT_MMCMDIV_CLK0DIV);
+
+#undef EXT
+
+ clk0_rate =
On 07/27/2016 04:10 PM, Yangbo Lu wrote:
>> -Original Message-
>> From: york sun
>> Sent: Tuesday, July 26, 2016 1:38 AM
>> To: Yangbo Lu; u-boot@lists.denx.de
>> Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620
>>
>> On 05/20/2016 03:20 AM, Yangbo Lu wrote:
>>>
Hi,
This patch series changes the emaclite driver to be slightly more generic
and then enables it for the MIPS arch.
Regards,
ZubairLK
Zubair Lutfullah Kakakhel (3):
net: emaclite: Use ioremap_nocache
net: emaclite: use __raw_readl/writel instead of weird define
net: emaclite: Enable
MIPSfpga is an FPGA based dev platform by Imagination Technologies Ltd.
DDR is already initialized before u-boot.
And the peripherals supported in the u-boot port are an n16550 uart and
a xilinx ethernet IP (axi_emaclite) which already have drivers in u-boot.
Hence the port is mostly DT +
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