Hi Andrew,
On 11 November 2016 at 14:22, Andrew Duda wrote:
> Simon,
>
> So I looked into this more after you asked this, and it looks very
> platform dependent. I tested on two builds: sandbox and a version of
> x86-common. The before/after for sandbox image was
>
On 11 November 2016 at 14:16, Andrew Duda wrote:
>
> Simon,
>
> padded_len could work. I decided to go with key_len to be more
> RSA-independent since I have been dealing with ECDSA primarily. More
> specifically, ECDSA has no notion of padding or padded_len, but it
> does
On Mon, Nov 14, 2016 at 07:58:03PM +0100, Maxime Ripard wrote:
> Hi,
>
> On Mon, Nov 14, 2016 at 10:25:27AM -0500, Tom Rini wrote:
> > On Mon, Nov 14, 2016 at 04:20:49PM +0100, Maxime Ripard wrote:
> > > On Fri, Nov 11, 2016 at 11:20:47AM -0500, Tom Rini wrote:
> > > > On Tue, Nov 08, 2016 at
Hi,
On Mon, Nov 14, 2016 at 10:25:27AM -0500, Tom Rini wrote:
> On Mon, Nov 14, 2016 at 04:20:49PM +0100, Maxime Ripard wrote:
> > On Fri, Nov 11, 2016 at 11:20:47AM -0500, Tom Rini wrote:
> > > On Tue, Nov 08, 2016 at 05:21:14PM +0100, Maxime Ripard wrote:
> > >
> > > > This program generates
On Thu, 3 Nov 2016 00:58:12 +
Andre Przywara wrote:
> Somehow an int returning function without a return statement sneaked
> in. Fix it.
>
> Signed-off-by: Andre Przywara
> ---
> drivers/mtd/spi/sunxi_spi_spl.c | 3 ++-
> 1 file changed, 2
On 11/06/2016 08:14 PM, macro.wav...@gmail.com wrote:
> From: Hongbo Zhang
>
> A most basic PSCI implementation with only one psci_version is added for
> LS1043A, this can verify the generic PSCI framework, and more platform
> specific
> implementation will be added later.
On Mon, 14 Nov 2016 11:56:50 -0500
Tom Rini wrote:
> On Mon, Nov 14, 2016 at 04:47:26PM +, Andre Przywara wrote:
> > Hi,
> >
> > On 14/11/16 16:30, Jagan Teki wrote:
> > > On Thu, Nov 3, 2016 at 6:28 AM, Andre Przywara
> > > wrote:
> > >>
On 10/26/2016 03:47 AM, Sumit Garg wrote:
> Add NOR secure boot target. Also enable sec init.
>
> Signed-off-by: Vinitha Pillai
> Signed-off-by: Sumit Garg
> ---
>
> Changes in v2:
> Split patches logically from 2 to 3.
>
>
On 11/07/2016 10:36 AM, york@nxp.com wrote:
> On 10/27/2016 02:47 AM, Calvin Johnson wrote:
>> Hi York,
>>
>>> -Original Message-
>>> From: york sun
>>> Sent: Wednesday, October 26, 2016 10:09 PM
>>> To: Calvin Johnson ; Prabhakar Kushwaha
>>>
On Mon, Nov 14, 2016 at 10:16 PM, Tom Rini wrote:
> Hey all,
>
> I've released v2016.11 and it's now live on git and FTP and ACD (along
> with PGP sig file).
>
> In many ways it feels good to say that the highlights of the last
> release once again apply. We've had more DM
> On 10 November 2016 at 02:49, Alison Wang wrote:
> > This series is to support loading a 32-bit OS, the execution state
> will change from AArch64 to AArch32 when jumping to kernel. The
> architecture information will be got through checking FIT image, then
> U-Boot will
On 11/07/2016 10:03 PM, Yao Yuan wrote:
> On 11/08/2016 02:27 AM, York Sun wrote:
>> On 10/25/2016 07:10 PM, Yuan Yao wrote:
>>> From: Yuan Yao
>>>
>>> The default configuration for QSPI AHB bus can't support 16MB+.
>>> But some flash on NXP layerscape board are more than 16MB.
Duncan Hare
714 931 7952
- Forwarded Message -
From: "d...@synoia.com"
To: "u-boot@lists.denx.de"
Cc: Cédric Schieli
Sent: Sunday, November 13, 2016 4:08 PM
Subject: FDT retrived varaibles appear to have different
On 09/23/2016 12:38 AM, Y.B. Lu wrote:
>> ditto.
>
> [Lu Yangbo-B47093] Ok, I will check the return. Thanks :)
>>
Yangbo,
Do you have an update?
York
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On 11/03/2016 04:12 AM, Priyanka Jain wrote:
> Signed-off-by: Priyanka Jain
> ---
> arch/arm/cpu/armv8/fsl-layerscape/cpu.c|7 ---
> arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S |9 +
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h
On Mon, Nov 14, 2016 at 03:21:41PM +0100, Hans de Goede wrote:
> Hi,
>
> On 14-11-16 15:12, Maxime Ripard wrote:
> >On Mon, Nov 14, 2016 at 12:18:06PM +0100, Hans de Goede wrote:
> >>> #ifdef CONFIG_SPL_SPI_SUNXI
> >>>@@ -143,7 +157,14 @@
> >>> #define CONFIG_GENERIC_MMC
> >>> #define
Hans, Ian, All,
On 2016-11-14 12:53 +0100, Hans de Goede spake thusly:
> A while back I wrote:
>
> "Between my $dayjob, linux-sunxi, other foss projects and last but
> not least spending time with my wife and children I'm way too
> busy lately.
>
> So I've decided to seriously scale back my
On Mon, Nov 14, 2016 at 04:47:26PM +, Andre Przywara wrote:
> Hi,
>
> On 14/11/16 16:30, Jagan Teki wrote:
> > On Thu, Nov 3, 2016 at 6:28 AM, Andre Przywara
> > wrote:
> >> Somehow an int returning function without a return statement sneaked
> >> in. Fix it.
> >>
>
Hi,
On 14/11/16 16:30, Jagan Teki wrote:
> On Thu, Nov 3, 2016 at 6:28 AM, Andre Przywara wrote:
>> Somehow an int returning function without a return statement sneaked
>> in. Fix it.
>>
>> Signed-off-by: Andre Przywara
>> ---
>>
Hey all,
I've released v2016.11 and it's now live on git and FTP and ACD (along
with PGP sig file).
In many ways it feels good to say that the highlights of the last
release once again apply. We've had more DM conversion work, Kconfig
conversion work and arch / SoC / platform updates. We've
On Thu, Nov 3, 2016 at 6:28 AM, Andre Przywara wrote:
> Somehow an int returning function without a return statement sneaked
> in. Fix it.
>
> Signed-off-by: Andre Przywara
> ---
> drivers/mtd/spi/sunxi_spi_spl.c | 3 ++-
> 1 file changed, 2
On Mon, Nov 14, 2016 at 12:53:25PM +0100, Hans de Goede wrote:
> Ian has not had any time for sunxi for some time now and I'm
> in the same situation now, so I'm stepping down as sunxi
> custodian and marking the sunxi support as Orphan.
>
> Cc: Maxime Ripard
>
Hi Phil,
> The offset was applied to write, but not read, now its applied to
> both.
>
> Signed-off-by: Phil Edworthy
> ---
> drivers/dfu/dfu_sf.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c
On Mon, Nov 14, 2016 at 04:20:49PM +0100, Maxime Ripard wrote:
> On Fri, Nov 11, 2016 at 11:20:47AM -0500, Tom Rini wrote:
> > On Tue, Nov 08, 2016 at 05:21:14PM +0100, Maxime Ripard wrote:
> >
> > > This program generates raw SPL images that can be flashed on the NAND with
> > > the ECC and
On Mon, Nov 14, 2016 at 1:19 PM, Phil Edworthy
wrote:
> The offset was applied to write, but not read, now its applied to
> both.
>
> Signed-off-by: Phil Edworthy
Reviewed-by: Fabio Estevam
On Fri, Nov 11, 2016 at 11:20:47AM -0500, Tom Rini wrote:
> On Tue, Nov 08, 2016 at 05:21:14PM +0100, Maxime Ripard wrote:
>
> > This program generates raw SPL images that can be flashed on the NAND with
> > the ECC and randomizer properly set up.
> >
> > Signed-off-by: Maxime Ripard
The offset was applied to write, but not read, now its applied to
both.
Signed-off-by: Phil Edworthy
---
drivers/dfu/dfu_sf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c
index 9702eee..b6d5fe2
On Mon, Nov 14, 2016 at 02:42:59PM +0100, Maxime Ripard wrote:
> Hi,
>
> On Fri, Nov 11, 2016 at 11:16:39AM -0800, Moritz Fischer wrote:
> > > +U_BOOT_DRIVER(ds2431) = {
> > > + .name = "ds2431",
> > > + .id = UCLASS_EEPROM,
> > > + .ops= _ops,
On 11/14/2016 04:07 PM, Anatolij Gustschin wrote:
> Add CycloneV based Terasic DE1-SoC board. The board boots
> from SD/MMC. Ethernet and USB host is supported.
>
> Signed-off-by: Anatolij Gustschin
> Cc: Marek Vasut
> ---
>
Applied, thanks.
--
Best regards,
Add CycloneV based Terasic DE1-SoC board. The board boots
from SD/MMC. Ethernet and USB host is supported.
Signed-off-by: Anatolij Gustschin
Cc: Marek Vasut
---
v2:
- drop custom raw partition configuration, use default instead
arch/arm/dts/Makefile
On 11/14/2016 03:17 PM, Anatolij Gustschin wrote:
> Hi,
>
> On Mon, 14 Nov 2016 15:07:31 +0100
> Marek Vasut ma...@denx.de wrote:
> ...
>>> +#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
>>> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2
>>
>> Why is this needed ? Just start U-Boot
Hi,
On 14-11-16 15:12, Maxime Ripard wrote:
On Mon, Nov 14, 2016 at 12:18:06PM +0100, Hans de Goede wrote:
#ifdef CONFIG_SPL_SPI_SUNXI
@@ -143,7 +157,14 @@
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SUNXI
#define CONFIG_MMC_SUNXI_SLOT 0
-#define CONFIG_ENV_IS_IN_MMC
+#endif
+
Hi,
On Mon, 14 Nov 2016 15:07:31 +0100
Marek Vasut ma...@denx.de wrote:
...
> > +#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
> > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2
>
> Why is this needed ? Just start U-Boot from partition 1 as all the other
> SoCFPGAs do , esp. since
Hans,
On 14-11-16 15:13, Hans de Goede wrote:
Hi,
On 14-11-16 15:11, Olliver Schinagl wrote:
Hey Hans,
On 14-11-16 12:26, Hans de Goede wrote:
Hi,
On 08-11-16 17:38, Olliver Schinagl wrote:
The current implementation to force the PHY into master mode is to
have a
define which affects
Hi,
On 14-11-16 15:11, Olliver Schinagl wrote:
Hey Hans,
On 14-11-16 12:26, Hans de Goede wrote:
Hi,
On 08-11-16 17:38, Olliver Schinagl wrote:
The current implementation to force the PHY into master mode is to have a
define which affects all realtek PHY's. This is not needed as the
On Mon, Nov 14, 2016 at 12:18:06PM +0100, Hans de Goede wrote:
> > #ifdef CONFIG_SPL_SPI_SUNXI
> > @@ -143,7 +157,14 @@
> > #define CONFIG_GENERIC_MMC
> > #define CONFIG_MMC_SUNXI
> > #define CONFIG_MMC_SUNXI_SLOT 0
> > -#define CONFIG_ENV_IS_IN_MMC
> > +#endif
> > +
> > +#if
Hi,
On 14-11-16 15:09, Maxime Ripard wrote:
Hi,
On Mon, Nov 14, 2016 at 12:18:06PM +0100, Hans de Goede wrote:
#ifdef CONFIG_SPL_SPI_SUNXI
@@ -143,7 +157,14 @@
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SUNXI
#define CONFIG_MMC_SUNXI_SLOT 0
-#define CONFIG_ENV_IS_IN_MMC
Hey Hans,
On 14-11-16 12:26, Hans de Goede wrote:
Hi,
On 08-11-16 17:38, Olliver Schinagl wrote:
The current implementation to force the PHY into master mode is to
have a
define which affects all realtek PHY's. This is not needed as the
problem
only exists in the RTL8211C chips. Let us thus
Hi,
On 14-11-16 14:53, Maxime Ripard wrote:
On Mon, Nov 14, 2016 at 12:29:25PM +0100, Hans de Goede wrote:
Hi,
On 14-11-16 12:18, Hans de Goede wrote:
Hi,
On 08-11-16 17:21, Maxime Ripard wrote:
This program generates raw SPL images that can be flashed on the NAND with
the ECC and
From: Shaohui Xie
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.
Signed-off-by: Shaohui Xie
---
not sure what was
From: Shaohui Xie
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.
Signed-off-by: Shaohui Xie
---
Hi,
On Mon, Nov 14, 2016 at 12:18:06PM +0100, Hans de Goede wrote:
> > #ifdef CONFIG_SPL_SPI_SUNXI
> > @@ -143,7 +157,14 @@
> > #define CONFIG_GENERIC_MMC
> > #define CONFIG_MMC_SUNXI
> > #define CONFIG_MMC_SUNXI_SLOT 0
> > -#define CONFIG_ENV_IS_IN_MMC
> > +#endif
> > +
> > +#if
Fix the following error, the $ret variable handling must
be part of the loop, while due to the missing parenthesis
it was not.
drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’:
drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard...
[-Wmisleading-indentation]
for
On 11/14/2016 02:53 PM, Anatolij Gustschin wrote:
> Add CycloneV based Terasic DE1-SoC board. The board boots
> from SD/MMC. Ethernet and USB host is supported.
>
> Signed-off-by: Anatolij Gustschin
> Cc: Marek Vasut
[...]
> diff --git
Add CycloneV based Terasic DE1-SoC board. The board boots
from SD/MMC. Ethernet and USB host is supported.
Signed-off-by: Anatolij Gustschin
Cc: Marek Vasut
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 66 +++
On Mon, Nov 14, 2016 at 12:29:25PM +0100, Hans de Goede wrote:
> Hi,
>
> On 14-11-16 12:18, Hans de Goede wrote:
> > Hi,
> >
> > On 08-11-16 17:21, Maxime Ripard wrote:
> > > This program generates raw SPL images that can be flashed on the NAND with
> > > the ECC and randomizer properly set up.
On Mon, 2016-11-14 at 12:53 +0100, Hans de Goede wrote:
> Ian has not had any time for sunxi for some time now and I'm
> in the same situation now, so I'm stepping down as sunxi
> custodian and marking the sunxi support as Orphan.
>
> Cc: Maxime Ripard
> Cc:
Hi,
On Fri, Nov 11, 2016 at 11:16:39AM -0800, Moritz Fischer wrote:
> > +U_BOOT_DRIVER(ds2431) = {
> > + .name = "ds2431",
> > + .id = UCLASS_EEPROM,
> > + .ops= _ops,
>
> Do you want to add a .flags = DM_UC_FLAG_SEQ_ALIAS here?
I don't know.
Hi Moritz,
On Fri, Nov 11, 2016 at 11:13:39AM -0800, Moritz Fischer wrote:
> Hi Maxime,
>
> On Fri, Nov 11, 2016 at 8:17 AM, Simon Glass wrote:
> > Hi Maxime,
> >
> > On 8 November 2016 at 03:19, Maxime Ripard
> > wrote:
> >> We might want
Hi Simon,
On Fri, Nov 11, 2016 at 09:17:20AM -0700, Simon Glass wrote:
> Hi Maxime,
>
> On 8 November 2016 at 03:06, Maxime Ripard
> wrote:
> > Add a bus driver for bitbanging a 1-Wire bus over a GPIO.
> >
> > Signed-off-by: Maxime Ripard
On Mon, Nov 14, 2016 at 12:53:13PM +0100, Hans de Goede wrote:
> Hi All,
>
> A while back I wrote:
>
> "Between my $dayjob, linux-sunxi, other foss projects and last but
> not least spending time with my wife and children I'm way too
> busy lately.
>
> So I've decided to seriously scale back my
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.
Signed-off-by: Shaohui Xie
---
not sure what was wrong, the patch did not show in
Hi Hans,
On 14.11.2016 12:53, Hans de Goede wrote:
A while back I wrote:
"Between my $dayjob, linux-sunxi, other foss projects and last but
not least spending time with my wife and children I'm way too
busy lately.
So I've decided to seriously scale back my involvement in
linux-sunxi, as such
On 11/14/2016 03:51 AM, Hans de Goede wrote:
> Hi,
>
> On 04-11-16 16:18, Maxime Ripard wrote:
>> The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the
>> support for those too.
>>
>> Signed-off-by: Maxime Ripard
>
> LGTM:
>
> Reviewed-by: Hans
On 11/14/2016 03:51 AM, Hans de Goede wrote:
> Hi,
>
> On 04-11-16 16:18, Maxime Ripard wrote:
>> The SinA33 comes with an optional 7" display. Enable it in the
>> configuration.
>>
>> Signed-off-by: Maxime Ripard
>
> LGTM:
>
> Reviewed-by: Hans de Goede
On 11/14/2016 03:51 AM, Hans de Goede wrote:
> Hi,
>
> On 04-11-16 16:18, Maxime Ripard wrote:
>> The SinA33 has an 4GB Toshiba eMMC connected to the MMC2 controller.
>> Enable it.
>>
>> Signed-off-by: Maxime Ripard
>
> LGTM:
>
> Reviewed-by: Hans de Goede
On 11/14/2016 03:50 AM, Hans de Goede wrote:
> Hi,
>
> On 04-11-16 16:18, Maxime Ripard wrote:
>> Some eMMC will fail at the first switch, but would succeed in a subsequent
>> one.
>>
>> Make sure we try several times to cover those cases. The number of retries
>> (and the behaviour) is currently
Ian has not had any time for sunxi for some time now and I'm
in the same situation now, so I'm stepping down as sunxi
custodian and marking the sunxi support as Orphan.
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Cc: Ian Campbell
Hi All,
A while back I wrote:
"Between my $dayjob, linux-sunxi, other foss projects and last but
not least spending time with my wife and children I'm way too
busy lately.
So I've decided to seriously scale back my involvement in
linux-sunxi, as such I'm going to step down as u-boot sunxi
Hi,
On 14-11-16 12:19, Hans de Goede wrote:
Hi,
On 08-11-16 17:21, Maxime Ripard wrote:
Introduce a new sunxi-spl-with-ecc.bin image with already the right header,
ECC, randomizer and padding for the BROM to be able to read it.
It needs to be flashed using a raw access to the NAND so that
Hi,
On 14-11-16 12:18, Hans de Goede wrote:
Hi,
On 08-11-16 17:21, Maxime Ripard wrote:
This program generates raw SPL images that can be flashed on the NAND with
the ECC and randomizer properly set up.
Signed-off-by: Maxime Ripard
Looks good to me:
Hi,
On 08-11-16 17:38, Olliver Schinagl wrote:
The current implementation to force the PHY into master mode is to have a
define which affects all realtek PHY's. This is not needed as the problem
only exists in the RTL8211C chips. Let us thus turn this into a quirk flag
instead.
Series looks
Hi,
On Wed, Nov 9, 2016 at 6:38 PM, Hans de Goede wrote:
> Hi,
>
> On 09-11-16 11:21, Chen-Yu Tsai wrote:
>>
>> Hi everyone,
>>
>> This series adds basic PSCI support for the A80 to enable SMP on the
>> first cluster. This at least allows people to use more than one core.
>>
Hi,
On 08-11-16 17:21, Maxime Ripard wrote:
The CHIP Pro is a SoM that features the GR8 SIP, an AXP209, a BT/WiFi chip
and a 512MiB SLC NAND.
This it's an SLC NAND, it doesn't suffer the same drawbacks than found on
the MLC NANDs, and we can enable it right away.
Signed-off-by: Maxime Ripard
Hi,
On 08-11-16 17:21, Maxime Ripard wrote:
The SPL image needs to be built with a different ECC configuration than the
U-Boot binary.
Add Kconfig options with defaults to provide a value that should work for
anyone, but is still configurable if needs be.
Signed-off-by: Maxime Ripard
Hi,
On 08-11-16 17:21, Maxime Ripard wrote:
Introduce a new sunxi-spl-with-ecc.bin image with already the right header,
ECC, randomizer and padding for the BROM to be able to read it.
It needs to be flashed using a raw access to the NAND so that the
controller doesn't change a thing to it,
Hi,
On 08-11-16 17:21, Maxime Ripard wrote:
This program generates raw SPL images that can be flashed on the NAND with
the ECC and randomizer properly set up.
Signed-off-by: Maxime Ripard
Looks good to me:
Reviewed-by: Hans de Goede
Hi,
On 08-11-16 17:21, Maxime Ripard wrote:
From: Hans de Goede
Enable the NAND and UBI support in the configuration header so that we can
(finally) use it.
Signed-off-by: Hans de Goede
Signed-off-by: Maxime Ripard
Hi,
On 08-11-16 17:21, Maxime Ripard wrote:
From: Boris Brezillon
Add the description of the Toshiba TC58NVG2S0H SLC nand to the nand_ids
table so we can use the NAND ECC infos and the ONFI timings.
Signed-off-by: Boris Brezillon
Hi,
On 08-11-16 17:21, Maxime Ripard wrote:
Those DT will be part of 4.10, sync them so we can have our own config.
Signed-off-by: Maxime Ripard
Looks good to me:
Reviewed-by: Hans de Goede
Regards,
Hans
---
Hi,
On 08-11-16 11:19, Maxime Ripard wrote:
The NextThing's C.H.I.P. can have expansion boards called DIPs. Those DIPs
are connected through the external headers, and comes with an
identification mechanism based on 1-Wire EEPROMs.
That auto-detection works great, because 1-Wire allows the
Hi Hans,
On 11/14/2016 03:51 AM, Hans de Goede wrote:
> Hi,
>
> On 04-11-16 16:18, Maxime Ripard wrote:
>> The SinA33 comes with an optional 7" display. Enable it in the
>> configuration.
>>
>> Signed-off-by: Maxime Ripard
>
> LGTM:
>
> Reviewed-by: Hans de
On 11/14/2016 06:56 PM, Hans de Goede wrote:
> Hi,
>
> On 14-11-16 01:34, Jaehoon Chung wrote:
>> On 11/14/2016 07:50 AM, Tom Rini wrote:
>>> On Sun, Nov 13, 2016 at 07:50:53PM +0100, Hans de Goede wrote:
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
> Some eMMC will fail at the
Hi Simon,
On 11/12/2016 12:17 AM, Simon Glass wrote:
Hi Kever,
On 8 November 2016 at 03:13, Kever Yang wrote:
enable the vbus for usb host in board_init().
Note 'borad_init' typo in subject.
Will fix in next version.
Signed-off-by: Kever Yang
Hi,
On 14-11-16 01:34, Jaehoon Chung wrote:
On 11/14/2016 07:50 AM, Tom Rini wrote:
On Sun, Nov 13, 2016 at 07:50:53PM +0100, Hans de Goede wrote:
Hi,
On 04-11-16 16:18, Maxime Ripard wrote:
Some eMMC will fail at the first switch, but would succeed in a subsequent
one.
Make sure we try
On 14/11/2016 10:23, Alexander Graf wrote:
To enable working efifb support, let's map the frame buffer as 32bpp
instead of 16bpp.
Signed-off-by: Alexander Graf
Thanks, applied to efi-next
Alex
Sorry, that was script magic going wild. Bcm2835 patches obviously have
to go
> To enable working efifb support, let's map the frame buffer as 32bpp
> instead of 16bpp.
>
> Signed-off-by: Alexander Graf
Thanks, applied to efi-next
Alex
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> Firmware provides a spin table on the raspberry pi. This table shouldn't
> get overwritten by payloads, so we need to mark it as reserved.
>
> Signed-off-by: Alexander Graf
Thanks, applied to efi-next
Alex
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> The rpi has a pretty simple way of resetting the whole system. All it takes
> is to poke a few registers at a well defined location in MMIO space.
>
> This patch adds support for the EFI loader implementation to allow an OS to
> reset and power off the system when we're outside of boot time.
>
Add support to detect RGMII link interface from link-interface
device tree entry. Also rename the existing link type enums so
that it provides meaning full interface like SGMII.
Signed-off-by: Mugunthan V N
---
Without this support there is a crash in K2G EVM tftp boot [1].
Hi Simon,
> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: 2016年11月12日 0:18
> To: Z.Q. Hou
> Cc: U-Boot Mailing List ; Albert ARIBAUD
> ; Prabhakar Kushwaha
>
Hi Jagan,
On 19/10/2016 13:23, Jagan Teki wrote:
> From: Jagan Teki
>
> This series convert fec_mxc to DM and tested both dm and
> non-dm code and it is on top of [1] with u-boot-imx/master
> branch.
>
> Changes for v7:
> - Remove fec_set_dev_name in dm probe
>
>
On 17/10/2016 15:51, Heiko Schocher wrote:
> post some small updates for the imx35 based flea3 board
> - add DT support
> - factorize SDRAM setup
> - add GPIO setup
> - adjust default environment
>
>
> Heiko Schocher (2):
> mx35: add DT support to flea3 board
> mx35: adjust default
On 08/10/2016 11:03, Peng Fan wrote:
> According to design team, we need to set REFTOP_VBGADJ
> in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the
> actually table is as below:
>
> '000" - set REFTOP_VBGADJ[2:0] to 3'b000
> '001" - set REFTOP_VBGADJ[2:0] to 3'b001
> '010" - set
Hi Peng,
On 08/10/2016 10:58, Peng Fan wrote:
> From: "Ye.Li"
>
> Need to gate ENET clock when switching to a new clock parent, because
> the mux is not glitchless.
>
> Signed-off-by: Peng Fan
> Signed-off-by: Ye.Li
> Cc: Stefano Babic
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