[U-Boot] [PATCH 1/1] arm: socfpga: cyclone5-socdk: Enable ports A & C

[Georges Savoundararadj]

With the port C enabled, we can read the GPI input state of:
* the DIP switches (USER_DIPSW_HPS[3:0]/HPS_GPI[7:4])
* the push buttons (USER_PB_HPS[3:0]/HPS_GPI[11:8])

Signed-off-by: Georges Savoundararadj 
Signed-off by: Sid-Ali Teir 
Cc: Dinh Nguyen 
Cc: Marek Vasut 
---
 arch/arm/dts/socfpga_cyclone5_socdk.dts | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts 
b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index d4df1a14da..f175ef2ead 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -54,10 +54,18 @@
rxc-skew-ps = <2000>;
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 
-- 
2.12.1

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[U-Boot] 答复: [PATCH] armv8/fsl-layerscape: fdt: On ls1012 don't check sysclk for USB

[Yingxi Yu]

Hi York:

Currenly LS1012A is the only case. If there is other platform apply it in 
the future, we can add other platform later.


Best Regards

Yingxi Yu


发件人: york sun
发送时间: 2017年3月27日 8:29:02
收件人: Yingxi Yu; u-boot@lists.denx.de
主题: Re: [PATCH] armv8/fsl-layerscape: fdt: On ls1012 don't check sysclk for USB

On 03/16/2017 12:32 AM, Yingxi Yu wrote:
> USB requires 100MHz clock. On ls1012, sysclk(125MHz) is not for USB.
> Another 100MHz clock is for USB. So For USB, check if sysclk is 100MHz
> is failed on ls1012, sysclk is not for USB. Don't check sysclk for
> USB on ls1012.

Does this only apply to LS1012A? Or does this apply a group of SoCs?

York

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Re: [U-Boot] [PATCH v2 00/13] sunxi: Add support for R40 SoC

[Chen-Yu Tsai]

Hi,

On Mon, Mar 6, 2017 at 4:05 PM, Chen-Yu Tsai  wrote:
> Hi everyone,
>
> This is v2 of my Allwinner R40 SoC support series.
>
> Changes since v1:
>
>   - Add Maxime's ack for all but the first patch.
>
>   - Add a patch to split up very long Kconfig lines.
>
> This series adds support for the new R40 SoC. The R40 is marketed as the
> successor to the A20. It is mostly pin compatible (in software) with the
> A20. It has a somewhat similar memory layout, a hybrid of A20 and newer
> sun6i gen.. Like the A20, it does not have a PRCM block.

What's the status on this? The series has been sitting for some time,
with all patches acked. AFAIK there are 3 patch series in flight that
will conflict with each other on the DRAM stuff. Can we at least start
by merging one so we can do conflict resolution?

Thanks
ChenYu
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[U-Boot] [PATCH v2 07/18] armv8: SPL: only compile GIC code if needed

[Andre Przywara]

Not every SoC needs to set up the GIC interrupt controller, so link
think code only when the respective config option is set.
This shaves off some bytes from the SPL code size.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 arch/arm/lib/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index b95e105..5733430 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -44,7 +44,9 @@ ifdef CONFIG_CPU_V7M
 obj-y  += interrupts_m.o
 else ifdef CONFIG_ARM64
 obj-y  += ccn504.o
+ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),)
 obj-y  += gic_64.o
+endif
 obj-y  += interrupts_64.o
 else
 obj-y  += interrupts.o
-- 
2.8.2

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[U-Boot] [PATCH v2 11/18] sunxi: SPL: add FIT config selector for Pine64 boards

[Andre Przywara]

For a board or platform to support FIT loading in the SPL, it has to
provide a board_fit_config_name_match() routine, which helps to select
one of possibly multiple DTBs contained in a FIT image.
Provide a simple function which chooses the DT name U-Boot was
configured with.
If the DT name is one of the two Pine64 versions, determine the exact
model by checking the DRAM size.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 board/sunxi/board.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index a510422..2ddff28 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -725,3 +725,26 @@ int ft_board_setup(void *blob, bd_t *bd)
 #endif
return 0;
 }
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+   const char *cmp_str;
+
+#ifdef CONFIG_DEFAULT_DEVICE_TREE
+   cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
+#else
+   return 0;
+#endif
+
+/* Differentiate the two Pine64 board DTs by their DRAM size. */
+   if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
+   if ((gd->ram_size > 512 * 1024 * 1024))
+   return !strstr(name, "plus");
+   else
+   return !!strstr(name, "plus");
+   } else {
+   return strcmp(name, cmp_str);
+   }
+}
+#endif
-- 
2.8.2

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[U-Boot] [PATCH v2 10/18] sunxi: SPL: store RAM size in gd

[Andre Przywara]

The sunxi SPL was holding the detected RAM size in some local variable
only, so it wasn't accessible for other functions.
Store the value in gd->ram_size instead, so it can be used later on.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 board/sunxi/board.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index b966012..a510422 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -480,7 +480,6 @@ void i2c_init_board(void)
 void sunxi_board_init(void)
 {
int power_failed = 0;
-   unsigned long ramsize;
 
 #ifdef CONFIG_SY8106A_POWER
power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
@@ -541,9 +540,9 @@ void sunxi_board_init(void)
 #endif
 #endif
printf("DRAM:");
-   ramsize = sunxi_dram_init();
-   printf(" %d MiB\n", (int)(ramsize >> 20));
-   if (!ramsize)
+   gd->ram_size = sunxi_dram_init();
+   printf(" %d MiB\n", (int)(gd->ram_size >> 20));
+   if (!gd->ram_size)
hang();
 
/*
-- 
2.8.2

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[U-Boot] [PATCH v2 12/18] Makefile: add rules to generate SPL FIT images

[Andre Przywara]

Some platforms require more complex U-Boot images than we can easily
generate via the mkimage command line, for instance to load additional
image files.
Introduce a CONFIG_SPL_FIT_SOURCE and CONFIG_SPL_FIT_GENERATOR symbol,
which can either hold an .its source file describing the image layout,
or, in the second case, a generator tool (script) to create such
a source file. This script gets passed the list of device tree files
from the CONFIG_OF_LIST variable.
A platform or board can define either of those in their defconfig file
to allow an easy building of such an image.

Signed-off-by: Andre Przywara 
---
 Kconfig  | 17 +
 Makefile | 20 
 2 files changed, 37 insertions(+)

diff --git a/Kconfig b/Kconfig
index e0744d1..69382ea 100644
--- a/Kconfig
+++ b/Kconfig
@@ -239,6 +239,23 @@ config SPL_FIT_IMAGE_POST_PROCESS
  injected into the FIT creation (i.e. the blobs would have been pre-
  processed before being added to the FIT image).
 
+config SPL_FIT_SOURCE
+   string ".its source file for U-Boot FIT image"
+   depends on SPL_FIT
+   help
+ Specifies a (platform specific) FIT source file to generate the
+ U-Boot FIT image. This could specify further image to load and/or
+ execute.
+
+config SPL_FIT_GENERATOR
+   string ".its file generator script for U-Boot FIT image"
+   depends on SPL_FIT
+   help
+ Specifies a (platform specific) script file to generate the FIT
+ source file used to build the U-Boot FIT image file. This gets
+ passed a list of supported device tree file stub names to
+ include in the generated image.
+
 endif # FIT
 
 config OF_BOARD_SETUP
diff --git a/Makefile b/Makefile
index 539fb20..5ecf40f 100644
--- a/Makefile
+++ b/Makefile
@@ -827,6 +827,10 @@ quiet_cmd_mkimage = MKIMAGE $@
 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
$(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
 
+quiet_cmd_mkfitimage = MKIMAGE $@
+cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f 
$(U_BOOT_ITS) -E $@ \
+   $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
+
 quiet_cmd_cat = CAT $@
 cmd_cat = cat $(filter-out $(PHONY), $^) > $@
 
@@ -946,6 +950,19 @@ quiet_cmd_cpp_cfg = CFG $@
 cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
-DDO_DEPS_ONLY -D__ASSEMBLY__ -x assembler-with-cpp -P -dM -E -o $@ $<
 
+# Boards with more complex image requirments can provide an .its source file
+# or a generator script
+ifneq ($(CONFIG_SPL_FIT_SOURCE),"")
+U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
+else
+ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
+U_BOOT_ITS := u-boot.its
+$(U_BOOT_ITS): FORCE
+   $(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
+   $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
+endif
+endif
+
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
@@ -978,6 +995,9 @@ u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl 
u-boot-ivt.img: \
$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin 
dts/dt.dtb,u-boot.bin) FORCE
$(call if_changed,mkimage)
 
+u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
+   $(call if_changed,mkfitimage)
+
 u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
 
-- 
2.8.2

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[U-Boot] [PATCH v2 13/18] sunxi: A64: Pine64: introduce FIT generator script

[Andre Przywara]

Now that the Makefile can call a generator script to build a more
advanced FIT image, let's use this feature to address the needs of
Allwinner A64 boards.
The (DTB stripped) U-Boot binary and the ATF are static, but we allow
an arbitrary number of supported device trees to be passed.
The script enters both a DT entry in the /images node and the respective
subnode in /configurations to support all listed DTBs.

This requires to copy the ARM Trusted Firmware build (bl31.bin) into
the U-Boot source directory (or to create a symlink to it).

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 board/sunxi/mksunxi_fit_atf.sh | 73 ++
 1 file changed, 73 insertions(+)
 create mode 100755 board/sunxi/mksunxi_fit_atf.sh

diff --git a/board/sunxi/mksunxi_fit_atf.sh b/board/sunxi/mksunxi_fit_atf.sh
new file mode 100755
index 000..afa22e8
--- /dev/null
+++ b/board/sunxi/mksunxi_fit_atf.sh
@@ -0,0 +1,73 @@
+#!/bin/sh
+#
+# script to generate FIT image source for 64-bit sunxi boards with
+# ARM Trusted Firmware and multiple device trees (given on the command line)
+#
+# usage: $0  [ [;
+
+   images {
+   uboot@1 {
+   description = "U-Boot (64-bit)";
+   data = /incbin/("u-boot-nodtb.bin");
+   type = "standalone";
+   arch = "arm64";
+   compression = "none";
+   load = <0x4a00>;
+   };
+   atf@1 {
+   description = "ARM Trusted Firmware";
+   data = /incbin/("bl31.bin");
+   type = "firmware";
+   arch = "arm64";
+   compression = "none";
+   load = <0x44000>;
+   entry = <0x44000>;
+   };
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+   cat << __FDT_IMAGE_EOF
+   fdt@$cnt {
+   description = "$(basename $dtname .dtb)";
+   data = /incbin/("$dtname");
+   type = "flat_dt";
+   compression = "none";
+   };
+__FDT_IMAGE_EOF
+   cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+   };
+   configurations {
+   default = "config@1";
+
+__CONF_HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+   cat << __CONF_SECTION_EOF
+   config@$cnt {
+   description = "$(basename $dtname .dtb)";
+   firmware = "uboot@1";
+   loadables = "atf@1";
+   fdt = "fdt@$cnt";
+   };
+__CONF_SECTION_EOF
+   cnt=$((cnt+1))
+done
+
+cat << __ITS_EOF
+   };
+};
+__ITS_EOF
-- 
2.8.2

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[U-Boot] [PATCH v2 09/18] sunxi: A64: move SPL stack to end of SRAM A2

[Andre Przywara]

The SPL stack is usually located at the end of SRAM A1, where it grows
towards the end of the SPL.
For the really big AArch64 binaries the stack overwrites code pretty
soon, so move the SPL stack to the end of SRAM A2, which is unused at this
time.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 include/configs/sunxi-common.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 171cea2..b7eb95e 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -182,7 +182,12 @@
 #ifdef CONFIG_SUNXI_HIGH_SRAM
 #define CONFIG_SPL_TEXT_BASE   0x10040 /* sram start+header */
 #define CONFIG_SPL_MAX_SIZE0x7fc0  /* 32 KiB */
+#ifdef CONFIG_ARM64
+/* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */
+#define LOW_LEVEL_SRAM_STACK   0x00054000
+#else
 #define LOW_LEVEL_SRAM_STACK   0x00018000
+#endif /* !CONFIG_ARM64 */
 #else
 #define CONFIG_SPL_TEXT_BASE   0x40/* sram start+header */
 #define CONFIG_SPL_MAX_SIZE0x5fc0  /* 24KB on sun4i/sun7i 
*/
-- 
2.8.2

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[U-Boot] [PATCH v2 17/18] sunxi: use SPL header DT name for FIT board matching

[Andre Przywara]

Now that we can store a DT name in the SPL header, use this string (if
available) when finding the right DT blob to load for U-Boot proper.
This allows a generic U-Boot (proper) image to be combined with a bunch
of supported DTs, with just the SPL (possibly only that string) to be
different.
Eventually this string can be written after the build process by some
firmware update tool.

Signed-off-by: Andre Przywara 
---
 board/sunxi/board.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 2ddff28..714f8fd 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -729,13 +729,19 @@ int ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-   const char *cmp_str;
+   struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
+   const char *cmp_str = (void *)(ulong)SPL_ADDR;
 
+   /* Check if there is a DT name stored in the SPL header and use that. */
+   if (spl->dt_name_offset) {
+   cmp_str += spl->dt_name_offset;
+   } else {
 #ifdef CONFIG_DEFAULT_DEVICE_TREE
-   cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
+   cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
 #else
-   return 0;
+   return 0;
 #endif
+   };
 
 /* Differentiate the two Pine64 board DTs by their DRAM size. */
if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
-- 
2.8.2

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[U-Boot] [PATCH v2 15/18] sunxi: OrangePi-PC2: defconfig: enable SPL FIT support

[Andre Przywara]

Enable the SPL FIT support and the FIT generator script for the
OrangePi PC2 board, as it also need to load an ATF binary.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 configs/orangepi_pc2_defconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index 19a5c2b..8a2d289 100644
--- a/configs/orangepi_pc2_defconfig
+++ b/configs/orangepi_pc2_defconfig
@@ -5,6 +5,12 @@ CONFIG_SPL=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881977
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2"
+CONFIG_OF_LIST="sun50i-h5-orangepi-pc2"
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_FIT_GENERATOR="board/sunxi/mksunxi_fit_atf.sh"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
 # CONFIG_CMD_IMLS is not set
-- 
2.8.2

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[U-Boot] [PATCH v2 06/18] tools: mksunxiboot: allow larger SPL binaries

[Andre Przywara]

mksunxiboot limits the size of the resulting SPL binaries to pretty
conservative values to cover all SoCs and all boot media (NAND).
It turns out that we have limit checks in place in the build process,
so mksunxiboot can be relaxed and allow packaging binaries up to the
actual 32KB the mask boot ROM actually imposes.
This allows to have a bigger SPL, which is crucial for AArch64 builds.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 tools/mksunxiboot.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index 0f0b003..6bb649c 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -48,7 +48,7 @@ int gen_check_sum(struct boot_file_head *head_p)
 #define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1)
 #define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))
 
-#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */
+#define SUN4I_SRAM_SIZE 0x8000 /* SoC with smaller size are limited before */
 #define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head))
 
 /*
-- 
2.8.2

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[U-Boot] [PATCH v2 16/18] sunxi: Store the device tree name in the SPL header

[Andre Przywara]

From: Siarhei Siamashka 

This patch updates the mksunxiboot tool to optionally add
the default device tree name string to the SPL header. This
information can be used by the firmware upgrade tools to
protect users from harming themselves by trying to upgrade
to an incompatible bootloader.

The primary use case here is a non-removable bootable media
(such as NAND, eMMC or SPI flash), which already may have
a properly working, but a little bit outdated bootloader
installed. For example, the user may download or build a
new U-Boot image for "Cubieboard", and then attemept to
install it on a "Cubieboard2" hardware by mistake as a
replacement for the already existing bootloader. If this
happens, the flash programming tool can identify this
problem and warn the user.

The size of the SPL header is also increased from 64 bytes
to 96 bytes to provide enough space for the device tree name
string.
[Andre: split patch to remove OF_LIST hash feature]

Signed-off-by: Siarhei Siamashka 
Signed-off-by: Andre Przywara 
---
 arch/arm/include/asm/arch-sunxi/spl.h | 19 +++---
 include/configs/sunxi-common.h|  8 +++---
 scripts/Makefile.spl  |  3 ++-
 tools/mksunxiboot.c   | 49 ---
 4 files changed, 67 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/spl.h 
b/arch/arm/include/asm/arch-sunxi/spl.h
index 831d0c0..9358397 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -10,7 +10,7 @@
 
 #define BOOT0_MAGIC"eGON.BT0"
 #define SPL_SIGNATURE  "SPL" /* marks "sunxi" SPL header */
-#define SPL_HEADER_VERSION 1
+#define SPL_HEADER_VERSION 2
 
 #ifdef CONFIG_SUNXI_HIGH_SRAM
 #define SPL_ADDR   0x1
@@ -58,11 +58,24 @@ struct boot_file_head {
 * compatible format, ready to be imported via "env import -t".
 */
uint32_t fel_uEnv_length;
-   uint32_t reserved1[2];
+   /*
+* Offset of an ASCIIZ string (relative to the SPL header), which
+* contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE).
+* This is optional and may be set to NULL. Is intended to be used
+* by flash programming tools for providing nice informative messages
+* to the users.
+*/
+   uint32_t dt_name_offset;
+   uint32_t reserved1;
uint32_t boot_media;/* written here by the boot ROM */
-   uint32_t reserved2[5];  /* padding, align to 64 bytes */
+   /* A padding area (may be used for storing text strings) */
+   uint32_t string_pool[13];
+   /* The header must be a multiple of 32 bytes (for VBAR alignment) */
 };
 
+/* Compile time check to assure proper alignment of structure */
+typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct 
boot_file_head) % 32)];
+
 #define is_boot0_magic(addr)   (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
 
 #endif
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 1982063..65f0f69 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -184,8 +184,8 @@
 #endif
 
 #ifdef CONFIG_SUNXI_HIGH_SRAM
-#define CONFIG_SPL_TEXT_BASE   0x10040 /* sram start+header */
-#define CONFIG_SPL_MAX_SIZE0x7fc0  /* 32 KiB */
+#define CONFIG_SPL_TEXT_BASE   0x10060 /* sram start+header */
+#define CONFIG_SPL_MAX_SIZE0x7fa0  /* 32 KiB */
 #ifdef CONFIG_ARM64
 /* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */
 #define LOW_LEVEL_SRAM_STACK   0x00054000
@@ -193,8 +193,8 @@
 #define LOW_LEVEL_SRAM_STACK   0x00018000
 #endif /* !CONFIG_ARM64 */
 #else
-#define CONFIG_SPL_TEXT_BASE   0x40/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE0x5fc0  /* 24KB on sun4i/sun7i 
*/
+#define CONFIG_SPL_TEXT_BASE   0x60/* sram start+header */
+#define CONFIG_SPL_MAX_SIZE0x5fa0  /* 24KB on sun4i/sun7i 
*/
 #define LOW_LEVEL_SRAM_STACK   0x8000  /* End of sram */
 #endif
 
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index d01af3b..d134b74 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -294,7 +294,8 @@ $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
$(call if_changed,mkimage)
 
 quiet_cmd_mksunxiboot = MKSUNXI $@
-cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@
+cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \
+   --default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@
 $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE
$(call if_changed,mksunxiboot)
 
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
index 6bb649c..4ac2791 100644
--- a/tools/mksunxiboot.c
+++ b/tools/mksunxiboot.c
@@ -70,11 +70,40 @@ int main(int 

[U-Boot] [PATCH v2 18/18] sunxi: update Pine64 README

[Andre Przywara]

With the DRAM init code and the SPL's ability to load the ATF binary as
well, we can now officially get rid of the boot0 boot method, which
involed a closed-source proprietary blob to be used.
Rework the Pine64 README file to document how to build the firmware.

Signed-off-by: Andre Przywara 
---
 board/sunxi/README.pine64 | 177 ++
 1 file changed, 115 insertions(+), 62 deletions(-)

diff --git a/board/sunxi/README.pine64 b/board/sunxi/README.pine64
index 5553415..41fb58e 100644
--- a/board/sunxi/README.pine64
+++ b/board/sunxi/README.pine64
@@ -8,75 +8,130 @@ This chip has ARM Cortex A-53 cores and thus can run both in 
AArch32
 in AArch32 mode and executes 32-bit code from the Boot ROM (BROM).
 This has some implications on U-Boot.
 
-Quick start
-
-- Get hold of a boot0.img file (see below for more details).
-- Get the boot0img tool source from the tools directory in [1] and compile
-  that on your host.
-- Build U-Boot:
+Quick Start / Overview
+==
+- Build the ARM Trusted Firmware binary (see "ARM Trusted firmware (ATF)" 
below)
+- Build U-Boot (see "SPL/U-Boot" below)
+- Transfer to an uSD card (see "microSD card" below)
+- Boot and enjoy!
+
+Building the firmware
+=
+
+The Allwinner A64 firmware consists of three parts: U-Boot's SPL, an
+ARM Trusted Firmware (ATF) build and the U-Boot proper.
+The SPL will load both ATF and U-Boot proper along with the right device
+tree blob (.dtb) and will pass execution to ATF (in EL3), which in turn will
+drop into the U-Boot proper (in EL2).
+As the ATF binary will become part of the U-Boot image file, you will need
+to build it first.
+
+ ARM Trusted firmware (ATF)
+
+Checkout the "allwinner" branch from the github repository [1] and build it:
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make PLAT=sun50iw1p1 DEBUG=1 bl31
+  The resulting binary is build/sun50iw1p1/debug/bl31.bin. Copy this to the
+  root of the U-Boot source tree (or create a symbolic link).
+
+ SPL/U-Boot
+
+Both U-Boot proper and the SPL are using the 64-bit mode. As the boot ROM
+enters the SPL still in AArch32 secure SVC mode, there is some shim code to
+enter AArch64 very early. The rest of the SPL runs in AArch64 EL3.
+U-boot proper runs in EL2 and can load any AArch64 code, EFI applications or
+arm64 Linux kernel images (often named "Image") using the booti command.
+
+$ make clean
 $ export CROSS_COMPILE=aarch64-linux-gnu-
 $ make pine64_plus_defconfig
 $ make
-- You also need a compiled ARM Trusted Firmware (ATF) binary. Checkout the
-  "allwinner" branch from the github repository [2] and build it:
-$ export CROSS_COMPILE=aarch64-linux-gnu-
-$ make PLAT=sun50iw1p1 DEBUG=1 bl31
-  The resulting binary is build/sun50iw1p1/debug/bl31.bin.
 
-Now put an empty (or disposable) micro SD card in your card reader and learn
-its device file name, replacing /dev/sd below with the result (that could
-be /dev/mmcblk as well):
+This will build the SPL in spl/sunxi-spl.bin and a FIT image called u-boot.itb,
+which contains the rest of the firmware.
+
 
-$ ./boot0img --device /dev/sd -e -u u-boot.bin -B boot0.img \
-   -d trampoline64:0x44000 -s bl31.bin -a 0x44008 -p 100
-(either copying the respective files to the working directory or specifying
-the paths directly)
+Boot process
+
+The on-die BROM code will try several methods to load and execute the firmware.
+On the Pine64 this will result in the following boot order:
+1) Reading 32KB from sector 16 (@8K) of the microSD card to SRAM A1. If the
+BROM finds the magic "eGON" header in the first bytes, it will execute that
+code. If not, it will:
+2) Initialize the SPI0 controller and try to access a NOR flash connected to
+it (using the CS0 pin). If a flash chip is found, the BROM will load the
+first 32KB (from offset 0) into SRAM A1. Now it checks for the magic eGON
+header and will execute the code upon finding it. If not, it will:
+3) Initialize the USB OTG controller and will wait for a host to connect to
+it, speaking the Allwinner proprietary (but deciphered) "FEL" USB protocol.
+
+To boot the Pine64 board, you can use U-Boot and any of the described methods.
 
-This will create a new partition table (with a 100 MB FAT boot partition),
-copies boot0.img, ATF and U-Boot to the proper locations on the SD card and
-will fill in the magic Allwinner header to be recognized by boot0.
-Prefix the above call with "sudo" if you don't have write access to the
-uSD card. You can also use "-o output.img" instead of "--device /dev/sd"
-to create an image file and "dd" that to the uSD card.
-Omitting the "-p" option will skip the partition table.
+FEL boot (USB OTG)
+--
+FEL is the name of the Allwinner defined USB boot protocol built in the
+mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely
+by using the USB-OTG interface and a host port on 

[U-Boot] [PATCH v2 05/18] SPL: FIT: allow loading multiple images

[Andre Przywara]

So far we were not using the FIT image format to its full potential:
The SPL FIT loader was just loading the first image from the /images
node plus one of the listed DTBs.
Now with the refactored loader code it's easy to load an arbitrary
number of images in addition to the two mentioned above.
As described in the FIT image source file format description, iterate
over all images listed at the "loadables" property in the configuration
node and load every image at its desired location.
This allows to load any kind of images:
- firmware images to execute before U-Boot proper (for instance
  ARM Trusted Firmware (ATF))
- firmware images for management processors (SCP, arisc, ...)
- firmware images for devices like WiFi controllers
- bit files for FPGAs
- additional configuration data
- kernels and/or ramdisks
The actual usage of this feature would be platform and/or board specific.

Also update the FIT documentation to mention the new SPL feature.

Signed-off-by: Andre Przywara 
Reviewed-by: Lokesh Vutla 
---
 common/spl/spl_fit.c | 42 --
 doc/uImage.FIT/howto.txt | 21 +
 2 files changed, 61 insertions(+), 2 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index cfcb1fe..edf4a43 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -231,6 +231,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
struct spl_image_info image_info;
int node, images, ret;
int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
+   int index = 0;
 
/*
 * Figure out where the external images start. This is the base for the
@@ -275,6 +276,11 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
if (node < 0) {
debug("could not find firmware image, trying loadables...\n");
node = spl_fit_get_image_node(fit, images, "loadables", 0);
+   /*
+* If we pick the U-Boot image from "loadables", start at
+* the second image when later loading additional images.
+*/
+   index = 1;
}
if (node < 0) {
debug("%s: Cannot find u-boot image node: %d\n",
@@ -302,6 +308,38 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 * Align the destination address to ARCH_DMA_MINALIGN.
 */
image_info.load_addr = spl_image->load_addr + spl_image->size;
-   return spl_load_fit_image(info, sector, fit, base_offset, node,
- _info);
+   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+_info);
+   if (ret < 0)
+   return ret;
+
+   /* Now check if there are more images for us to load */
+   for (; ; index++) {
+   node = spl_fit_get_image_node(fit, images, "loadables", index);
+   if (node < 0)
+   break;
+
+   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+_info);
+   if (ret < 0)
+   continue;
+
+   /*
+* If the "firmware" image did not provide an entry point,
+* use the first valid entry point from the loadables.
+*/
+   if (spl_image->entry_point == FDT_ERROR &&
+   image_info.entry_point != FDT_ERROR)
+   spl_image->entry_point = image_info.entry_point;
+   }
+
+   /*
+* If a platform does not provide CONFIG_SYS_UBOOT_START, U-Boot's
+* Makefile will set it to 0 and it will end up as the entry point
+* here. What it actually means is: use the load address.
+*/
+   if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0)
+   spl_image->entry_point = spl_image->load_addr;
+
+   return 0;
 }
diff --git a/doc/uImage.FIT/howto.txt b/doc/uImage.FIT/howto.txt
index 14e316f..2988a52 100644
--- a/doc/uImage.FIT/howto.txt
+++ b/doc/uImage.FIT/howto.txt
@@ -44,6 +44,27 @@ image source file mkimage + dtctransfer to 
target
+---> image file > bootm
 image data file(s)
 
+SPL usage
+-
+
+The SPL can make use of the new image format as well, this traditionally
+is used to ship multiple device tree files within one image. Code in the SPL
+will choose the one matching the current board and append this to the
+U-Boot proper binary to be automatically used up by it.
+Aside from U-Boot proper and one device tree blob the SPL can load multiple,
+arbitrary image files as well. These binaries should be specified in their
+own subnode under the /images node, which should then be referenced from one or
+multiple /configurations subnodes. The required images must be enumerated in
+the "loadables" property as a list 

[U-Boot] [PATCH v2 08/18] armv8: fsl: move ccn504 code into FSL Makefile

[Andre Przywara]

The generic ARMv8 assembly code contains routines for setting up
a CCN interconnect, though the Freescale SoCs are the only user.
Link this code only for Freescale targets, this saves some precious
bytes in the chronically tight SPL.

Signed-off-by: Andre Przywara 
---
 arch/arm/lib/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 5733430..82154f6 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -43,7 +43,7 @@ obj-y += stack.o
 ifdef CONFIG_CPU_V7M
 obj-y  += interrupts_m.o
 else ifdef CONFIG_ARM64
-obj-y  += ccn504.o
+obj-$(CONFIG_FSL_LAYERSCAPE) += ccn504.o
 ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),)
 obj-y  += gic_64.o
 endif
-- 
2.8.2

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[U-Boot] [PATCH v2 14/18] sunxi: Pine64: defconfig: enable SPL FIT support

[Andre Przywara]

The Pine64 (and all other 64-bit Allwinner boards) need to load an
ARM Trusted Firmware image beside the actual U-Boot proper.
This can now be easily achieved by using the just extended SPL FIT
loading support, so enable it in the Pine64 defconfig.
Also add the FIT image as a build target to 64-bit sunxi board to
trigger the respective Makefile rules.

Signed-off-by: Andre Przywara 
---
 configs/pine64_plus_defconfig  | 6 ++
 include/configs/sunxi-common.h | 4 
 2 files changed, 10 insertions(+)

diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 92bda60..8a90579 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -3,9 +3,14 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN50I=y
 CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
+CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
@@ -14,3 +19,4 @@ CONFIG_SPL=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SPL_FIT_GENERATOR="board/sunxi/mksunxi_fit_atf.sh"
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b7eb95e..1982063 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -32,6 +32,10 @@
 # define CONFIG_MACH_TYPE_COMPAT_REV   1
 #endif
 
+#ifdef CONFIG_ARM64
+#define CONFIG_BUILD_TARGET "u-boot.itb"
+#endif
+
 /* Serial & console */
 #define CONFIG_SYS_NS16550_SERIAL
 /* ns16550 reg in the low bits of cpu reg */
-- 
2.8.2

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[U-Boot] [PATCH v2 04/18] SPL: FIT: factor out spl_load_fit_image()

[Andre Przywara]

At the moment we load two images from a FIT image: the actual U-Boot
image and the .dtb file. Both times we have very similar code, that deals
with alignment requirements the media we load from imposes upon us.
Factor out this code into a new function, which we just call twice.

Signed-off-by: Andre Przywara 
---
 common/spl/spl_fit.c | 160 +--
 1 file changed, 78 insertions(+), 82 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 55da37a..cfcb1fe 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -158,19 +158,79 @@ static int get_aligned_image_size(struct spl_load_info 
*info, int data_size,
return (data_size + info->bl_len - 1) / info->bl_len;
 }
 
+/*
+ * spl_load_fit_image loads the image described in a certain FIT node.
+ * @info: points to information about the device to load data from
+ * @sector: the start sector of the FIT image on the device
+ * @fit: points to the flattened device tree blob describing the FIT image
+ * @base_offset: the beginning of the data area containing the actual
+ *  image data, relative to the beginning of the FIT
+ * @node: offset of the DT node describing the image to load (relative to @fit)
+ * @image_info: will be filled with information about the loaded image
+ * If the FIT node does not contain a "load" (address) property,
+ * the image gets loaded to the address pointed to by the
+ * load_addr member in this struct.
+ *
+ * Returns an error value or 0 on success.
+ */
+static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
+ void *fit, ulong base_offset, int node,
+ struct spl_image_info *image_info)
+{
+   ulong offset;
+   size_t length;
+   ulong load_addr, load_ptr;
+   void *src;
+   ulong overhead;
+   int nr_sectors;
+   int align_len = ARCH_DMA_MINALIGN - 1;
+
+   offset = fdt_getprop_u32(fit, node, "data-offset");
+   if (offset == FDT_ERROR)
+   return -ENOENT;
+   offset += base_offset;
+   length = fdt_getprop_u32(fit, node, "data-size");
+   if (length == FDT_ERROR)
+   return -ENOENT;
+   load_addr = fdt_getprop_u32(fit, node, "load");
+   if (load_addr == FDT_ERROR && image_info)
+   load_addr = image_info->load_addr;
+   load_ptr = (load_addr + align_len) & ~align_len;
+
+   overhead = get_aligned_image_overhead(info, offset);
+   nr_sectors = get_aligned_image_size(info, length, offset);
+
+   if (info->read(info, sector + get_aligned_image_offset(info, offset),
+  nr_sectors, (void*)load_ptr) != nr_sectors)
+   return -EIO;
+   debug("image: dst=%lx, offset=%lx, size=%lx\n", load_ptr, offset,
+ (unsigned long)length);
+
+   src = (void *)load_ptr + overhead;
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+   board_fit_image_post_process(, );
+#endif
+
+   memcpy((void*)load_addr, src, length);
+
+   if (image_info) {
+   image_info->load_addr = load_addr;
+   image_info->size = length;
+   image_info->entry_point = fdt_getprop_u32(fit, node, "entry");
+   }
+
+   return 0;
+}
+
 int spl_load_simple_fit(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong sector, void *fit)
 {
int sectors;
-   ulong size, load;
+   ulong size;
unsigned long count;
-   int node, images;
-   void *load_ptr;
-   int fdt_offset, fdt_len;
-   int data_offset, data_size;
+   struct spl_image_info image_info;
+   int node, images, ret;
int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
-   int src_sector;
-   void *dst, *src;
 
/*
 * Figure out where the external images start. This is the base for the
@@ -222,46 +282,13 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
return -1;
}
 
-   /* Get its information and set up the spl_image structure */
-   data_offset = fdt_getprop_u32(fit, node, "data-offset");
-   if (data_offset == FDT_ERROR)
-   return -1;
-   data_size = fdt_getprop_u32(fit, node, "data-size");
-   if (data_size == FDT_ERROR)
-   return -1;
-   load = fdt_getprop_u32(fit, node, "load");
-   debug("data_offset=%x, data_size=%x\n", data_offset, data_size);
-   spl_image->load_addr = load;
-   spl_image->entry_point = load;
-   spl_image->os = IH_OS_U_BOOT;
-
-   /*
-* Work out where to place the image. We read it so that the first
-* byte will be at 'load'. This may mean we need to load it starting
-* before then, since we can only read whole blocks.
-*/
-   data_offset += base_offset;
-   sectors = get_aligned_image_size(info, data_size, data_offset);
-  

[U-Boot] [PATCH v2 03/18] SPL: FIT: improve error handling

[Andre Przywara]

At the moment we ignore any errors due to missing FIT properties,
instead go ahead and calculate our addresses with the -1 return value.
Fix this and bail out if any of the mandatory properties are missing.

Signed-off-by: Andre Przywara 
---
 common/spl/spl_fit.c | 15 +--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index a4ac27b..55da37a 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -11,14 +11,17 @@
 #include 
 #include 
 
+#define FDT_ERROR ((ulong)(-1))
+
 static ulong fdt_getprop_u32(const void *fdt, int node, const char *prop)
 {
const u32 *cell;
int len;
 
cell = fdt_getprop(fdt, node, prop, );
-   if (len != sizeof(*cell))
-   return -1U;
+   if (!cell || len != sizeof(*cell))
+   return FDT_ERROR;
+
return fdt32_to_cpu(*cell);
 }
 
@@ -221,7 +224,11 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 
/* Get its information and set up the spl_image structure */
data_offset = fdt_getprop_u32(fit, node, "data-offset");
+   if (data_offset == FDT_ERROR)
+   return -1;
data_size = fdt_getprop_u32(fit, node, "data-size");
+   if (data_size == FDT_ERROR)
+   return -1;
load = fdt_getprop_u32(fit, node, "load");
debug("data_offset=%x, data_size=%x\n", data_offset, data_size);
spl_image->load_addr = load;
@@ -264,6 +271,10 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
}
fdt_offset = fdt_getprop_u32(fit, node, "data-offset");
fdt_len = fdt_getprop_u32(fit, node, "data-size");
+   if (fdt_offset == FDT_ERROR || fdt_len == FDT_ERROR) {
+   debug("%s: cannot load FDT data\n" __func__);
+   return -1;
+   }
 
/*
 * Read the device tree and place it after the image. There may be
-- 
2.8.2

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[U-Boot] [PATCH v2 01/18] SPL: FIT: refactor FDT loading

[Andre Przywara]

Currently the SPL FIT loader uses the spl_fit_select_fdt() function to
find the offset to the right DTB within the FIT image.
For this it iterates over all subnodes of the /configuration node in
the FIT tree and compares all "description" strings therein using a
board specific matching function.
If that finds a match, it uses the string in the "fdt" property of that
subnode to locate the matching subnode in the /images node, which points
to the DTB data.
Now this works very well, but is quite specific to cover this particular
use case. To open up the door for a more generic usage, let's split this
function into:
1) a function that just returns the node offset for the matching
   configuration node (spl_fit_find_config_node())
2) a function that returns the image data any given property in a given
   configuration node points to, additionally using a given index into
   a possbile list of strings (spl_fit_select_index())
This allows us to replace the specific function above by asking for the
image the _first string of the "fdt" property_ in the matching
configuration subnode points to.

This patch introduces no functional changes, it just refactors the code
to allow reusing it later.

(diff is overly clever here and produces a hard-to-read patch, so I
recommend to throw a look at the result instead).

Signed-off-by: Andre Przywara 
Reviewed-by: Lokesh Vutla 
---
 common/spl/spl_fit.c | 88 ++--
 1 file changed, 57 insertions(+), 31 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index aae556f..bf9fbb6 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -22,13 +22,16 @@ static ulong fdt_getprop_u32(const void *fdt, int node, 
const char *prop)
return fdt32_to_cpu(*cell);
 }
 
-static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
+/*
+ * Iterate over all /configurations subnodes and call a platform specific
+ * function to find the matching configuration.
+ * Returns the node offset.
+ */
+static int spl_fit_find_config_node(const void *fdt)
 {
-   const char *name, *fdt_name;
-   int conf, node, fdt_node;
-   int len;
+   const char *name;
+   int conf, node, len;
 
-   *fdt_offsetp = 0;
conf = fdt_path_offset(fdt, FIT_CONFS_PATH);
if (conf < 0) {
debug("%s: Cannot find /configurations node: %d\n", __func__,
@@ -50,39 +53,61 @@ static int spl_fit_select_fdt(const void *fdt, int images, 
int *fdt_offsetp)
continue;
 
debug("Selecting config '%s'", name);
-   fdt_name = fdt_getprop(fdt, node, FIT_FDT_PROP, );
-   if (!fdt_name) {
-   debug("%s: Cannot find fdt name property: %d\n",
- __func__, len);
-   return -EINVAL;
-   }
 
-   debug(", fdt '%s'\n", fdt_name);
-   fdt_node = fdt_subnode_offset(fdt, images, fdt_name);
-   if (fdt_node < 0) {
-   debug("%s: Cannot find fdt node '%s': %d\n",
- __func__, fdt_name, fdt_node);
-   return -EINVAL;
+   return node;
+   }
+
+   return -1;
+}
+
+static int spl_fit_select_index(const void *fit, int images, int *offsetp,
+   const char *type, int index)
+{
+   const char *name, *str;
+   int node, conf_node;
+   int len, i;
+
+   *offsetp = 0;
+   conf_node = spl_fit_find_config_node(fit);
+   if (conf_node < 0) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+   printf("No matching DT out of these options:\n");
+   for (node = fdt_first_subnode(fit, conf_node);
+node >= 0;
+node = fdt_next_subnode(fit, node)) {
+   name = fdt_getprop(fit, node, "description", );
+   printf("   %s\n", name);
}
+#endif
+   return -ENOENT;
+   }
 
-   *fdt_offsetp = fdt_getprop_u32(fdt, fdt_node, "data-offset");
-   len = fdt_getprop_u32(fdt, fdt_node, "data-size");
-   debug("FIT: Selected '%s'\n", name);
+   name = fdt_getprop(fit, conf_node, type, );
+   if (!name) {
+   debug("cannot find property '%s': %d\n", type, len);
+   return -EINVAL;
+   }
 
-   return len;
+   str = name;
+   for (i = 0; i < index; i++) {
+   str = strchr(str, '\0') + 1;
+   if (!str || (str - name >= len)) {
+   debug("no string for index %d\n", index);
+   return -E2BIG;
+   }
}
 
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-   printf("No matching DT out of these options:\n");
-   for (node = fdt_first_subnode(fdt, conf);
-node >= 0;
-node = 

[U-Boot] [PATCH v2 02/18] SPL: FIT: rework U-Boot image loading

[Andre Przywara]

Currently the SPL FIT loader always looks only for the first image in
the /images node a FIT tree, which it loads and later executes.

Generalize this by looking for a "firmware" property in the matched
configuration subnode, or, if that does not exist, for the first string
in the "loadables" property. Then using the string in that property,
load the image of that name from the /images node.
This still loads only one image at the moment, but refactors the code to
allow extending this in a following patch.
To simplify later re-usage, we also generalize the spl_fit_select_index()
function to not return the image location, but just the node offset.

Signed-off-by: Andre Przywara 
Reviewed-by: Lokesh Vutla 
---
 common/spl/spl_fit.c | 45 +++--
 1 file changed, 31 insertions(+), 14 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index bf9fbb6..a4ac27b 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -60,14 +60,24 @@ static int spl_fit_find_config_node(const void *fdt)
return -1;
 }
 
-static int spl_fit_select_index(const void *fit, int images, int *offsetp,
-   const char *type, int index)
+/*
+ * By using the matching configuration subnode, retrieve the name of an image,
+ * specified by a property name and an index into that.
+ * @fit: Pointer to the FDT blob.
+ * @images: Offset of the /images subnode.
+ * @type: Name of the property within the configuration subnode.
+ * @index: Index into the list of strings in this property.
+ *
+ * Returns the node offset of the respective image node or a negative error
+ * number.
+ */
+static int spl_fit_get_image_node(const void *fit, int images,
+ const char *type, int index)
 {
const char *name, *str;
int node, conf_node;
int len, i;
 
-   *offsetp = 0;
conf_node = spl_fit_find_config_node(fit);
if (conf_node < 0) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -104,10 +114,7 @@ static int spl_fit_select_index(const void *fit, int 
images, int *offsetp,
return -EINVAL;
}
 
-   *offsetp = fdt_getprop_u32(fit, node, "data-offset");
-   len = fdt_getprop_u32(fit, node, "data-size");
-
-   return len;
+   return node;
 }
 
 static int get_aligned_image_offset(struct spl_load_info *info, int offset)
@@ -193,15 +200,22 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
if (count == 0)
return -EIO;
 
-   /* find the firmware image to load */
+   /* find the node holding the images information */
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
if (images < 0) {
debug("%s: Cannot find /images node: %d\n", __func__, images);
return -1;
}
-   node = fdt_first_subnode(fit, images);
+
+   /* find the U-Boot image */
+   node = spl_fit_get_image_node(fit, images, "firmware", 0);
+   if (node < 0) {
+   debug("could not find firmware image, trying loadables...\n");
+   node = spl_fit_get_image_node(fit, images, "loadables", 0);
+   }
if (node < 0) {
-   debug("%s: Cannot find first image node: %d\n", __func__, node);
+   debug("%s: Cannot find u-boot image node: %d\n",
+ __func__, node);
return -1;
}
 
@@ -243,10 +257,13 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
memcpy(dst, src, data_size);
 
/* Figure out which device tree the board wants to use */
-   fdt_len = spl_fit_select_index(fit, images, _offset,
-  FIT_FDT_PROP, 0);
-   if (fdt_len < 0)
-   return fdt_len;
+   node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
+   if (node < 0) {
+   debug("%s: cannot find FDT node\n", __func__);
+   return node;
+   }
+   fdt_offset = fdt_getprop_u32(fit, node, "data-offset");
+   fdt_len = fdt_getprop_u32(fit, node, "data-size");
 
/*
 * Read the device tree and place it after the image. There may be
-- 
2.8.2

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[U-Boot] [PATCH v2 00/18] SPL: extend FIT loading support

[Andre Przywara]

A fixed version of the SPL FIT loading series.
The error handling has been improved, also quite some comments and
documentation has been added.
The README.pine64 file has been totally reworked to reflect the new
way of building the firmware for the Pine64 (and other 64-bit Allwinner
SoCs, really).
Some minor bugs have been fixed and Reviewed-by: tags have been added.

The first five patches introduce the core of the extened SPL FIT loading
support, see below for a description.
Patches 6-9 make some room in the sunxi 64-bit SPL to allow
compiling in the FIT loading bits. Patch 10 and 11 let the SPL choose
the proper DT from the FIT image.
The next two patches add the infrastructure and an actual generator script,
so the FIT image is automatically created at build time.
Patches 14 and 15 enable the SPL FIT support in the Pine64 and the
OrangePi PC 2 defconfigs.
The following two patches store a DT file name in the SPL header, so
U-Boot can easily pick the proper DT when scanning the FIT image.
The idea is that this DT name should stay with the board, ideally on
eMMC or SPI flash. So both U-Boot and a firmware update tool could
identify a board, updating with compatible firmware while keeping the
DT name in place. Ideally a board vendor would once seed this name
onto on-board storage like SPI flash.
I kept those two patches in, as the work on replacing mksunxiboot with
an mkimage extension is not ready yet. Feel free to drop those from
the series if this is a problem.
The final patch updates the Pine64 README file to document the current
way of building U-Boot, which now includes the ARM Trusted Firmware build
in its image.

I would be delighted if that series can make it into the next release,
as this finally enables the fully open source firmware for the 64-bit
Allwinner SoCs (including the ATF binary).

This series is based on sunxi/master, rebased upon origin/master.

Cheers,
Andre.

---
Currently the FIT format is not used to its full potential in the SPL:
It only loads the first image from the /images node and appends the
proper FDT.
Some boards and platforms would benefit from loading more images before
starting U-Boot proper, notably Allwinner A64 and ARMv8 Rockchip boards,
which use an ARM Trusted Firmware (ATF) image to be executed before U-Boot.

This series tries to solve this in a board agnostic and generic way:
We extend the SPL FIT loading scheme to allow loading multiple images.
So apart from loading the image which is referenced by the "firmware"
property in the respective configuration node and placing the DTB right
behind it, we iterate over all strings in the "loadable" property.
Each image referenced there will be loaded to its specified load address.
The entry point U-Boot eventually branches to will be taken from the
first image to explicitly provide the "entry" property, or, if none
of them does so, from the load address of the "firmware" image.
This keeps the scheme compatible with the FIT images our Makefile creates
automatically at the moment.
Apart from the already mentioned ATF scenario this opens up more usage
scenarios, of which the commit message of patch 04/11 lists some.
The remaining patches prepare ane finally enable this scheme for the 64-bit
Allwinner boards.

Andre Przywara (17):
  SPL: FIT: refactor FDT loading
  SPL: FIT: rework U-Boot image loading
  SPL: FIT: improve error handling
  SPL: FIT: factor out spl_load_fit_image()
  SPL: FIT: allow loading multiple images
  tools: mksunxiboot: allow larger SPL binaries
  armv8: SPL: only compile GIC code if needed
  armv8: fsl: move ccn504 code into FSL Makefile
  sunxi: A64: move SPL stack to end of SRAM A2
  sunxi: SPL: store RAM size in gd
  sunxi: SPL: add FIT config selector for Pine64 boards
  Makefile: add rules to generate SPL FIT images
  sunxi: A64: Pine64: introduce FIT generator script
  sunxi: Pine64: defconfig: enable SPL FIT support
  sunxi: OrangePi-PC2: defconfig: enable SPL FIT support
  sunxi: use SPL header DT name for FIT board matching
  sunxi: update Pine64 README

Siarhei Siamashka (1):
  sunxi: Store the device tree name in the SPL header

 Kconfig   |  17 ++
 Makefile  |  20 +++
 arch/arm/include/asm/arch-sunxi/spl.h |  19 ++-
 arch/arm/lib/Makefile |   4 +-
 board/sunxi/README.pine64 | 177 +---
 board/sunxi/board.c   |  36 +++-
 board/sunxi/mksunxi_fit_atf.sh|  73 +
 common/spl/spl_fit.c  | 298 ++
 configs/orangepi_pc2_defconfig|   6 +
 configs/pine64_plus_defconfig |   6 +
 doc/uImage.FIT/howto.txt  |  21 +++
 include/configs/sunxi-common.h|  17 +-
 scripts/Makefile.spl  |   3 +-
 tools/mksunxiboot.c   |  51 +-
 14 files changed, 563 insertions(+), 185 deletions(-)
 create mode 100755 board/sunxi/mksunxi_fit_atf.sh

-- 
2.8.2

Re: [U-Boot] [PATCH v4 1/2] armv7m: add instruction & data cache support

[Vikas Manocha]

Hi Marek,

On 03/27/2017 02:27 PM, Marek Vasut wrote:
> On 03/27/2017 10:41 PM, Vikas Manocha wrote:
>> Hi Marek,
>>
>> On 03/27/2017 01:34 PM, Marek Vasut wrote:
>>> On 03/27/2017 10:02 PM, Vikas Manocha wrote:
 This patch adds armv7m instruction & data cache support.

 Signed-off-by: Vikas Manocha 
 cc: Christophe KERELLO 
 ---

 Changed in v4:
 - invalidate_dcache_range() & flush_dcache_range() function added.
 - blank lines added.
 - comments added for registers, functions & barriers.
 - register names changed for better clarity.
 - typecasting moved to macro definitions.

 Changed in v3:
 - uint32 replcaed with u32.
 - multiple read of hardware register replaced with single.
 - pointers replaced with macros for base address.
 - register names added as comment for system control block registers.

 Changed in v2:
 - changed strucures for memory mapped cache registers to macros
 - added lines better readability.
 - replaced magic numbers with macros.

  arch/arm/cpu/armv7m/Makefile  |   3 +-
  arch/arm/cpu/armv7m/cache.c   | 336 
 ++
  arch/arm/include/asm/armv7m.h |  26 +++-
  arch/arm/lib/Makefile |   2 +
  4 files changed, 363 insertions(+), 4 deletions(-)
  create mode 100644 arch/arm/cpu/armv7m/cache.c

 diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
 index e1a6c40..93c9085 100644
 --- a/arch/arm/cpu/armv7m/Makefile
 +++ b/arch/arm/cpu/armv7m/Makefile
 @@ -6,6 +6,5 @@
  #
  
  extra-y := start.o
 -obj-y += cpu.o
 -
 +obj-y += cpu.o cache.o
  obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
 diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
 new file mode 100644
 index 000..162cfe3
 --- /dev/null
 +++ b/arch/arm/cpu/armv7m/cache.c
 @@ -0,0 +1,336 @@
 +/*
 + * (C) Copyright 2017
 + * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com.
 + *
 + * SPDX-License-Identifier:   GPL-2.0+
 + */
 +
 +#include 
 +#include 
 +#include 
 +#include 
 +
 +/* Cache maintenance operation registers */
 +
 +#define V7M_CACHE_REG_ICIALLU ((u32 *)(V7M_CACHE_MAINT_BASE + 
 0x00))
>>>  ^
>>> Drop this whole part,
>>> it's a register offset, not address. Just calculate the address
>>> in-place. The cast is also not needed.
>>
>> These are fixed addresses in armv7m architecture.
> 
> So what ?

So, no need to calculate in-plcae. It was your suggestion also.

> 
>> In place calculations were replaced by
>> this fixed address macro as per your comment.
> 
> And then one of the two things will happen:
> a) these addresses will be moved
> b) someone will look at the surrounding code, where _REG_ means register
> offset all over the place and will screw things up ...

moving these addresses...its fixed by architecture.

> 
>> casting was moved here from code as per Simon's suggestion on on v3.
>>
>>>
 +#define INVAL_ICACHE_POU  0
 +#define V7M_CACHE_REG_ICIMVALU((u32 *)(V7M_CACHE_MAINT_BASE + 
 0x08))
 +#define V7M_CACHE_REG_DCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 
 0x0C))
 +#define V7M_CACHE_REG_DCISW   ((u32 *)(V7M_CACHE_MAINT_BASE + 
 0x10))
 +#define V7M_CACHE_REG_DCCMVAU ((u32 *)(V7M_CACHE_MAINT_BASE + 
 0x14))
 +#define V7M_CACHE_REG_DCCMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 
 0x18))
 +#define V7M_CACHE_REG_DCCSW   ((u32 *)(V7M_CACHE_MAINT_BASE + 
 0x1C))
 +#define V7M_CACHE_REG_DCCIMVAC((u32 *)(V7M_CACHE_MAINT_BASE + 
 0x20))
 +#define V7M_CACHE_REG_DCCISW  ((u32 *)(V7M_CACHE_MAINT_BASE + 
 0x24))
 +#define WAYS_SHIFT30
 +#define SETS_SHIFT5
 +
 +/* armv7m processor feature registers */
 +
 +#define V7M_PROC_REG_CLIDR((u32 *)(V7M_PROC_FTR_BASE + 
 0x00))
 +#define V7M_PROC_REG_CTR  ((u32 *)(V7M_PROC_FTR_BASE + 0x04))
 +#define V7M_PROC_REG_CCSIDR   ((u32 *)(V7M_PROC_FTR_BASE + 
 0x08))
 +#define MASK_NUM_WAYS GENMASK(12, 3)
 +#define MASK_NUM_SETS GENMASK(27, 13)
 +#define CLINE_SIZE_MASK   GENMASK(2, 0)
 +#define NUM_WAYS_SHIFT3
 +#define NUM_SETS_SHIFT13
>>>
>>> Well use those macros in MASK_* above ...
>>
>> macros are being used, shifts are required after masking.
> 
> Then look at the GENMASK() above and the hardcoded values ...

hardcoded in GENMASK...really ?

> 
 +#define 

[U-Boot] __FILE__ usage and and SPL limits for SRAM

[Nishanth Menon]

Hi,

we've kind of run into an interesting situation recently, but might be 
of interest for various folks trying to reduce the image sizes.


our AM335x device has a limited amount of sram.. and the SPL tries to 
fit into it (a bit tricky given the restricted space we have on it on 
certain class of devices).


arch/arm/mach-omap2/am33xx/u-boot-spl.lds is a bit custom tailored 
around this.


Key in this is:
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram

. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram


Now, our jenkins build system happens to use a varied build path and 
uses O= path. to simplify the details:
mkdir 
/tmp//b/cc
mkdir 
/tmp//b/cc/b


git clone u-boot
cd u-boot

git clean -fdx
make CROSS_COMPILE=arm-linux-gnueabihf- O=../b am335x_evm_defconfig
make CROSS_COMPILE=arm-linux-gnueabihf- O=../b all

depending on depth of the path, this would fail.. a little bit of 
headscratching later..
when using O= build system uses absolute paths, which translates to 
__FILE__ being absolute paths as well..


in u-boot, any printf("%s", __FILE__) makes u-boot allocate this file 
path in rodata.


So, depending on how deep the path is rodata size varies and ends up 
pushing .data out of sram max range.


we dont really care to put a print of complete absolute path anyways, 
and I am not really sure of a clean way to resolve this:

a) override __FILE__ with something.. -Wbuiltin-macro-redefined kicks in
b) replace usage of __FILE__ with something like __FILENAME__ as 
recommended by [1]



What is the suggestion we do?

[1] http://stackoverflow.com/questions/8487986/file-macro-shows-full-path
--
Regards,
Nishanth Menon
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Re: [U-Boot] [PATCH v4 1/2] armv7m: add instruction & data cache support

[Marek Vasut]

On 03/27/2017 10:41 PM, Vikas Manocha wrote:
> Hi Marek,
> 
> On 03/27/2017 01:34 PM, Marek Vasut wrote:
>> On 03/27/2017 10:02 PM, Vikas Manocha wrote:
>>> This patch adds armv7m instruction & data cache support.
>>>
>>> Signed-off-by: Vikas Manocha 
>>> cc: Christophe KERELLO 
>>> ---
>>>
>>> Changed in v4:
>>> - invalidate_dcache_range() & flush_dcache_range() function added.
>>> - blank lines added.
>>> - comments added for registers, functions & barriers.
>>> - register names changed for better clarity.
>>> - typecasting moved to macro definitions.
>>>
>>> Changed in v3:
>>> - uint32 replcaed with u32.
>>> - multiple read of hardware register replaced with single.
>>> - pointers replaced with macros for base address.
>>> - register names added as comment for system control block registers.
>>>
>>> Changed in v2:
>>> - changed strucures for memory mapped cache registers to macros
>>> - added lines better readability.
>>> - replaced magic numbers with macros.
>>>
>>>  arch/arm/cpu/armv7m/Makefile  |   3 +-
>>>  arch/arm/cpu/armv7m/cache.c   | 336 
>>> ++
>>>  arch/arm/include/asm/armv7m.h |  26 +++-
>>>  arch/arm/lib/Makefile |   2 +
>>>  4 files changed, 363 insertions(+), 4 deletions(-)
>>>  create mode 100644 arch/arm/cpu/armv7m/cache.c
>>>
>>> diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
>>> index e1a6c40..93c9085 100644
>>> --- a/arch/arm/cpu/armv7m/Makefile
>>> +++ b/arch/arm/cpu/armv7m/Makefile
>>> @@ -6,6 +6,5 @@
>>>  #
>>>  
>>>  extra-y := start.o
>>> -obj-y += cpu.o
>>> -
>>> +obj-y += cpu.o cache.o
>>>  obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
>>> diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
>>> new file mode 100644
>>> index 000..162cfe3
>>> --- /dev/null
>>> +++ b/arch/arm/cpu/armv7m/cache.c
>>> @@ -0,0 +1,336 @@
>>> +/*
>>> + * (C) Copyright 2017
>>> + * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com.
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + */
>>> +
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +
>>> +/* Cache maintenance operation registers */
>>> +
>>> +#define V7M_CACHE_REG_ICIALLU  ((u32 *)(V7M_CACHE_MAINT_BASE + 
>>> 0x00))
>>  ^
>> Drop this whole part,
>> it's a register offset, not address. Just calculate the address
>> in-place. The cast is also not needed.
> 
> These are fixed addresses in armv7m architecture.

So what ?

> In place calculations were replaced by
> this fixed address macro as per your comment.

And then one of the two things will happen:
a) these addresses will be moved
b) someone will look at the surrounding code, where _REG_ means register
offset all over the place and will screw things up ...

> casting was moved here from code as per Simon's suggestion on on v3.
> 
>>
>>> +#define INVAL_ICACHE_POU   0
>>> +#define V7M_CACHE_REG_ICIMVALU ((u32 *)(V7M_CACHE_MAINT_BASE + 
>>> 0x08))
>>> +#define V7M_CACHE_REG_DCIMVAC  ((u32 *)(V7M_CACHE_MAINT_BASE + 
>>> 0x0C))
>>> +#define V7M_CACHE_REG_DCISW((u32 *)(V7M_CACHE_MAINT_BASE + 
>>> 0x10))
>>> +#define V7M_CACHE_REG_DCCMVAU  ((u32 *)(V7M_CACHE_MAINT_BASE + 
>>> 0x14))
>>> +#define V7M_CACHE_REG_DCCMVAC  ((u32 *)(V7M_CACHE_MAINT_BASE + 
>>> 0x18))
>>> +#define V7M_CACHE_REG_DCCSW((u32 *)(V7M_CACHE_MAINT_BASE + 
>>> 0x1C))
>>> +#define V7M_CACHE_REG_DCCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 
>>> 0x20))
>>> +#define V7M_CACHE_REG_DCCISW   ((u32 *)(V7M_CACHE_MAINT_BASE + 
>>> 0x24))
>>> +#define WAYS_SHIFT 30
>>> +#define SETS_SHIFT 5
>>> +
>>> +/* armv7m processor feature registers */
>>> +
>>> +#define V7M_PROC_REG_CLIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x00))
>>> +#define V7M_PROC_REG_CTR   ((u32 *)(V7M_PROC_FTR_BASE + 0x04))
>>> +#define V7M_PROC_REG_CCSIDR((u32 *)(V7M_PROC_FTR_BASE + 
>>> 0x08))
>>> +#define MASK_NUM_WAYS  GENMASK(12, 3)
>>> +#define MASK_NUM_SETS  GENMASK(27, 13)
>>> +#define CLINE_SIZE_MASKGENMASK(2, 0)
>>> +#define NUM_WAYS_SHIFT 3
>>> +#define NUM_SETS_SHIFT 13
>>
>> Well use those macros in MASK_* above ...
> 
> macros are being used, shifts are required after masking.

Then look at the GENMASK() above and the hardcoded values ...

>>> +#define V7M_PROC_REG_CSSELR((u32 *)(V7M_PROC_FTR_BASE + 
>>> 0x0C))
>>> +#define SEL_I_OR_D BIT(0)
>>> +
>>> +enum cache_type {
>>> +   DCACHE,
>>> +   ICACHE,
>>> +};
>>> +
>>> +/* PoU : Point of Unification, Poc: Point of Coherency */
>>> +enum cache_action {
>>> +   INVALIDATE_POU, /* i-cache invalidate by address */

Re: [U-Boot] [PATCH 2/3] string: Provide a slimmed-down memset()

[Alexander Graf]

On 27/03/2017 17:17, Heiko Stuebner wrote:

Am Montag, 27. März 2017, 09:14:47 CEST schrieb Alexander Graf:


On 27/03/2017 01:38, Simon Glass wrote:

Most of the time the optimised memset() is what we want. For extreme
situations such as TPL it may be too large. For example on the 'rock'
board, using a simple loop saves a useful 48 bytes. With gcc 4.9 and
the rodata bug, this patch is enough to reduce the TPL image below the
limit.

Signed-off-by: Simon Glass 
---

 lib/Kconfig  | 9 +
 lib/string.c | 6 --
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/lib/Kconfig b/lib/Kconfig
index 65c01573e1..5bf512d8c0 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -52,6 +52,15 @@ config LIB_RAND
help
  This library provides pseudo-random number generator functions.

+config FAST_MEMSET
+   bool "Use an optimised memset()"
+   default y
+   help
+ The faster memset() is the arch-specific one (if available) enabled
+ by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get
+ better performance by write a word at a time. Disable this option
+ to reduce code size slightly at the cost of some speed.


The comment sounds slightly confused - it took me a few times of reading
it until I grasped what it was trying to tell me :).


+
 source lib/dhry/Kconfig

 source lib/rsa/Kconfig
diff --git a/lib/string.c b/lib/string.c
index 67d5f6a421..159493ed17 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -437,8 +437,10 @@ char *strswab(const char *s)
 void * memset(void * s,int c,size_t count)
 {
unsigned long *sl = (unsigned long *) s;
-   unsigned long cl = 0;
char *s8;
+
+#ifdef CONFIG_FAST_MEMSET
+   unsigned long cl = 0;
int i;

/* do it one word at a time (32 bits or 64 bits) while possible */
@@ -452,7 +454,7 @@ void * memset(void * s,int c,size_t count)
count -= sizeof(*sl);
}
}
-   /* fill 8 bits at a time */
+#endif /* fill 8 bits at a time */


So while this is all neat, a few ideas:

1) Would having memset in a header improve things even more? After all,
each external function call clobbers registers that you need to
save/restore...


I'd guess it really depends on the size constraints. The regular
libgeneric memset compiles on my rk3188 tpl to a total of
64bytes on both gcc-4.9 and gcc-6.3 while Simon's fast-memset
comes down to 14bytes on my rk3188.

On the rk3188 the only memset user is board_init_f, so here memset
is called only once without needing to save registers and I'd guess if an
implementation really is that size-constrained to worry about 50bytes
this one caller will probably always be the only one?


I'm not sure I follow. If you put it into a header, the compiler has a 
better chance of evicting untaken code paths and optimize register usage 
over object linked variants (unless you use GOLD). I was mostly 
wondering whether that would already give you the savings without 
introducing a complicated #ifdef that is going to bitrot over time :).


I'm just slightly worried about the massive number of preprocessor 
excludes that happen in U-Boot in general. It seems like something 
that's really hard to ever have full testing coverage on.



2) How much would GOLD save you? Have you tried? U-Boot is small enough
of a code base that global optimizations should be able to give
significant size savings.


I think the issue that this is trying to solve is to allow more
toolchains to be used and thus make rebuilds on changes work on a lot
of boards at the same time with random toolchains.

gcc-6.3 already produces way smaller results (well within the size
constraints the rk3188 has) than for example the gcc-4.9 used by
buildman as baseline toolchain.


Ah, I see. So 4.9 does not have -lto? There's a good chance my gut 
feeling that GOLD actually saves anything is wrong - I don't know. Has 
anyone done the numbers? Then we would have something to actually base 
gut feeling on.


Size is always a serious constraint in U-Boot, especially in SPL 
environments. If we can include one more tool in our portfolio to 
optimize size across the board, I'm all for it. This patch just feels 
slightly short-term - but I'm definitely not nack'ing it :).



Alex
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Re: [U-Boot] [PATCH v4 1/2] armv7m: add instruction & data cache support

[Vikas Manocha]

Hi Marek,

On 03/27/2017 01:34 PM, Marek Vasut wrote:
> On 03/27/2017 10:02 PM, Vikas Manocha wrote:
>> This patch adds armv7m instruction & data cache support.
>>
>> Signed-off-by: Vikas Manocha 
>> cc: Christophe KERELLO 
>> ---
>>
>> Changed in v4:
>> - invalidate_dcache_range() & flush_dcache_range() function added.
>> - blank lines added.
>> - comments added for registers, functions & barriers.
>> - register names changed for better clarity.
>> - typecasting moved to macro definitions.
>>
>> Changed in v3:
>> - uint32 replcaed with u32.
>> - multiple read of hardware register replaced with single.
>> - pointers replaced with macros for base address.
>> - register names added as comment for system control block registers.
>>
>> Changed in v2:
>> - changed strucures for memory mapped cache registers to macros
>> - added lines better readability.
>> - replaced magic numbers with macros.
>>
>>  arch/arm/cpu/armv7m/Makefile  |   3 +-
>>  arch/arm/cpu/armv7m/cache.c   | 336 
>> ++
>>  arch/arm/include/asm/armv7m.h |  26 +++-
>>  arch/arm/lib/Makefile |   2 +
>>  4 files changed, 363 insertions(+), 4 deletions(-)
>>  create mode 100644 arch/arm/cpu/armv7m/cache.c
>>
>> diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
>> index e1a6c40..93c9085 100644
>> --- a/arch/arm/cpu/armv7m/Makefile
>> +++ b/arch/arm/cpu/armv7m/Makefile
>> @@ -6,6 +6,5 @@
>>  #
>>  
>>  extra-y := start.o
>> -obj-y += cpu.o
>> -
>> +obj-y += cpu.o cache.o
>>  obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
>> diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
>> new file mode 100644
>> index 000..162cfe3
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7m/cache.c
>> @@ -0,0 +1,336 @@
>> +/*
>> + * (C) Copyright 2017
>> + * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/* Cache maintenance operation registers */
>> +
>> +#define V7M_CACHE_REG_ICIALLU   ((u32 *)(V7M_CACHE_MAINT_BASE + 
>> 0x00))
>  ^
> Drop this whole part,
> it's a register offset, not address. Just calculate the address
> in-place. The cast is also not needed.

These are fixed addresses in armv7m architecture. In place calculations were 
replaced by
this fixed address macro as per your comment.
casting was moved here from code as per Simon's suggestion on on v3.

> 
>> +#define INVAL_ICACHE_POU0
>> +#define V7M_CACHE_REG_ICIMVALU  ((u32 *)(V7M_CACHE_MAINT_BASE + 
>> 0x08))
>> +#define V7M_CACHE_REG_DCIMVAC   ((u32 *)(V7M_CACHE_MAINT_BASE + 
>> 0x0C))
>> +#define V7M_CACHE_REG_DCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x10))
>> +#define V7M_CACHE_REG_DCCMVAU   ((u32 *)(V7M_CACHE_MAINT_BASE + 
>> 0x14))
>> +#define V7M_CACHE_REG_DCCMVAC   ((u32 *)(V7M_CACHE_MAINT_BASE + 
>> 0x18))
>> +#define V7M_CACHE_REG_DCCSW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x1C))
>> +#define V7M_CACHE_REG_DCCIMVAC  ((u32 *)(V7M_CACHE_MAINT_BASE + 
>> 0x20))
>> +#define V7M_CACHE_REG_DCCISW((u32 *)(V7M_CACHE_MAINT_BASE + 
>> 0x24))
>> +#define WAYS_SHIFT  30
>> +#define SETS_SHIFT  5
>> +
>> +/* armv7m processor feature registers */
>> +
>> +#define V7M_PROC_REG_CLIDR  ((u32 *)(V7M_PROC_FTR_BASE + 0x00))
>> +#define V7M_PROC_REG_CTR((u32 *)(V7M_PROC_FTR_BASE + 0x04))
>> +#define V7M_PROC_REG_CCSIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x08))
>> +#define MASK_NUM_WAYS   GENMASK(12, 3)
>> +#define MASK_NUM_SETS   GENMASK(27, 13)
>> +#define CLINE_SIZE_MASK GENMASK(2, 0)
>> +#define NUM_WAYS_SHIFT  3
>> +#define NUM_SETS_SHIFT  13
> 
> Well use those macros in MASK_* above ...

macros are being used, shifts are required after masking.

> 
>> +#define V7M_PROC_REG_CSSELR ((u32 *)(V7M_PROC_FTR_BASE + 0x0C))
>> +#define SEL_I_OR_D  BIT(0)
>> +
>> +enum cache_type {
>> +DCACHE,
>> +ICACHE,
>> +};
>> +
>> +/* PoU : Point of Unification, Poc: Point of Coherency */
>> +enum cache_action {
>> +INVALIDATE_POU, /* i-cache invalidate by address */
>> +INVALIDATE_POC, /* d-cache invalidate by address */
>> +INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
>> +FLUSH_POU,  /* d-cache clean by address to the PoU */
>> +FLUSH_POC,  /* d-cache clean by address to the PoC */
>> +FLUSH_SET_WAY,  /* d-cache clean by sets/ways */
>> +FLUSH_INVAL_POC,/* d-cache clean & invalidate by addr to PoC */
>> +FLUSH_INVAL_SET_WAY,/* d-cache clean & 

Re: [U-Boot] [PATCH v4 1/2] armv7m: add instruction & data cache support

[Marek Vasut]

On 03/27/2017 10:02 PM, Vikas Manocha wrote:
> This patch adds armv7m instruction & data cache support.
> 
> Signed-off-by: Vikas Manocha 
> cc: Christophe KERELLO 
> ---
> 
> Changed in v4:
> - invalidate_dcache_range() & flush_dcache_range() function added.
> - blank lines added.
> - comments added for registers, functions & barriers.
> - register names changed for better clarity.
> - typecasting moved to macro definitions.
> 
> Changed in v3:
> - uint32 replcaed with u32.
> - multiple read of hardware register replaced with single.
> - pointers replaced with macros for base address.
> - register names added as comment for system control block registers.
> 
> Changed in v2:
> - changed strucures for memory mapped cache registers to macros
> - added lines better readability.
> - replaced magic numbers with macros.
> 
>  arch/arm/cpu/armv7m/Makefile  |   3 +-
>  arch/arm/cpu/armv7m/cache.c   | 336 
> ++
>  arch/arm/include/asm/armv7m.h |  26 +++-
>  arch/arm/lib/Makefile |   2 +
>  4 files changed, 363 insertions(+), 4 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7m/cache.c
> 
> diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
> index e1a6c40..93c9085 100644
> --- a/arch/arm/cpu/armv7m/Makefile
> +++ b/arch/arm/cpu/armv7m/Makefile
> @@ -6,6 +6,5 @@
>  #
>  
>  extra-y := start.o
> -obj-y += cpu.o
> -
> +obj-y += cpu.o cache.o
>  obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
> diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
> new file mode 100644
> index 000..162cfe3
> --- /dev/null
> +++ b/arch/arm/cpu/armv7m/cache.c
> @@ -0,0 +1,336 @@
> +/*
> + * (C) Copyright 2017
> + * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com.
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* Cache maintenance operation registers */
> +
> +#define V7M_CACHE_REG_ICIALLU((u32 *)(V7M_CACHE_MAINT_BASE + 
> 0x00))
 ^
Drop this whole part,
it's a register offset, not address. Just calculate the address
in-place. The cast is also not needed.

> +#define INVAL_ICACHE_POU 0
> +#define V7M_CACHE_REG_ICIMVALU   ((u32 *)(V7M_CACHE_MAINT_BASE + 
> 0x08))
> +#define V7M_CACHE_REG_DCIMVAC((u32 *)(V7M_CACHE_MAINT_BASE + 
> 0x0C))
> +#define V7M_CACHE_REG_DCISW  ((u32 *)(V7M_CACHE_MAINT_BASE + 0x10))
> +#define V7M_CACHE_REG_DCCMVAU((u32 *)(V7M_CACHE_MAINT_BASE + 
> 0x14))
> +#define V7M_CACHE_REG_DCCMVAC((u32 *)(V7M_CACHE_MAINT_BASE + 
> 0x18))
> +#define V7M_CACHE_REG_DCCSW  ((u32 *)(V7M_CACHE_MAINT_BASE + 0x1C))
> +#define V7M_CACHE_REG_DCCIMVAC   ((u32 *)(V7M_CACHE_MAINT_BASE + 
> 0x20))
> +#define V7M_CACHE_REG_DCCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x24))
> +#define WAYS_SHIFT   30
> +#define SETS_SHIFT   5
> +
> +/* armv7m processor feature registers */
> +
> +#define V7M_PROC_REG_CLIDR   ((u32 *)(V7M_PROC_FTR_BASE + 0x00))
> +#define V7M_PROC_REG_CTR ((u32 *)(V7M_PROC_FTR_BASE + 0x04))
> +#define V7M_PROC_REG_CCSIDR  ((u32 *)(V7M_PROC_FTR_BASE + 0x08))
> +#define MASK_NUM_WAYSGENMASK(12, 3)
> +#define MASK_NUM_SETSGENMASK(27, 13)
> +#define CLINE_SIZE_MASK  GENMASK(2, 0)
> +#define NUM_WAYS_SHIFT   3
> +#define NUM_SETS_SHIFT   13

Well use those macros in MASK_* above ...

> +#define V7M_PROC_REG_CSSELR  ((u32 *)(V7M_PROC_FTR_BASE + 0x0C))
> +#define SEL_I_OR_D   BIT(0)
> +
> +enum cache_type {
> + DCACHE,
> + ICACHE,
> +};
> +
> +/* PoU : Point of Unification, Poc: Point of Coherency */
> +enum cache_action {
> + INVALIDATE_POU, /* i-cache invalidate by address */
> + INVALIDATE_POC, /* d-cache invalidate by address */
> + INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
> + FLUSH_POU,  /* d-cache clean by address to the PoU */
> + FLUSH_POC,  /* d-cache clean by address to the PoC */
> + FLUSH_SET_WAY,  /* d-cache clean by sets/ways */
> + FLUSH_INVAL_POC,/* d-cache clean & invalidate by addr to PoC */
> + FLUSH_INVAL_SET_WAY,/* d-cache clean & invalidate by set/ways */
> +};
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +struct dcache_config {
> + u32 ways;
> + u32 sets;
> +};
> +
> +static void get_cache_ways_sets(struct dcache_config *cache)
> +{
> + u32 cache_size_id = readl(V7M_PROC_REG_CCSIDR);
> +
> + cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
> + cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT;
> +}
> +
> +/*
> 

[U-Boot] [PATCH v4 2/2] stm32f7: enable instruction & data cache

[Vikas Manocha]

It also enables commands for cache enable/disable/status.

Signed-off-by: Vikas Manocha 
cc: Christophe KERELLO 
---

Changed in v4: None
Changed in v3: None
Changed in v2: None

 arch/arm/mach-stm32/stm32f7/soc.c | 2 ++
 include/configs/stm32f746-disco.h | 4 +---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-stm32/stm32f7/soc.c 
b/arch/arm/mach-stm32/stm32f7/soc.c
index 06af631..6f9704a 100644
--- a/arch/arm/mach-stm32/stm32f7/soc.c
+++ b/arch/arm/mach-stm32/stm32f7/soc.c
@@ -58,6 +58,8 @@ int arch_cpu_init(void)
 (V7M_MPU_RASR_XN_ENABLE
 | V7M_MPU_RASR_AP_RW_RW
 | 0x01 << V7M_MPU_RASR_TEX_SHIFT
+| 0x01 << V7M_MPU_RASR_B_SHIFT
+| 0x01 << V7M_MPU_RASR_C_SHIFT
 | V7M_MPU_RASR_SIZE_8MB
 | V7M_MPU_RASR_EN)
 , _MPU->rasr
diff --git a/include/configs/stm32f746-disco.h 
b/include/configs/stm32f746-disco.h
index ae3211a..9e9406a 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -14,9 +14,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR0x2005
 #define CONFIG_SYS_TEXT_BASE   0x0800
 
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-
 /*
  * Configuration of the external SDRAM memory
  */
@@ -82,4 +79,5 @@
 #define CONFIG_CMDLINE_EDITING
 
 #define CONFIG_CMD_MEM
+#define CONFIG_CMD_CACHE
 #endif /* __CONFIG_H */
-- 
1.9.1

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[U-Boot] [PATCH v4 1/2] armv7m: add instruction & data cache support

[Vikas Manocha]

This patch adds armv7m instruction & data cache support.

Signed-off-by: Vikas Manocha 
cc: Christophe KERELLO 
---

Changed in v4:
- invalidate_dcache_range() & flush_dcache_range() function added.
- blank lines added.
- comments added for registers, functions & barriers.
- register names changed for better clarity.
- typecasting moved to macro definitions.

Changed in v3:
- uint32 replcaed with u32.
- multiple read of hardware register replaced with single.
- pointers replaced with macros for base address.
- register names added as comment for system control block registers.

Changed in v2:
- changed strucures for memory mapped cache registers to macros
- added lines better readability.
- replaced magic numbers with macros.

 arch/arm/cpu/armv7m/Makefile  |   3 +-
 arch/arm/cpu/armv7m/cache.c   | 336 ++
 arch/arm/include/asm/armv7m.h |  26 +++-
 arch/arm/lib/Makefile |   2 +
 4 files changed, 363 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/cpu/armv7m/cache.c

diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
index e1a6c40..93c9085 100644
--- a/arch/arm/cpu/armv7m/Makefile
+++ b/arch/arm/cpu/armv7m/Makefile
@@ -6,6 +6,5 @@
 #
 
 extra-y := start.o
-obj-y += cpu.o
-
+obj-y += cpu.o cache.o
 obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
new file mode 100644
index 000..162cfe3
--- /dev/null
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -0,0 +1,336 @@
+/*
+ * (C) Copyright 2017
+ * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/* Cache maintenance operation registers */
+
+#define V7M_CACHE_REG_ICIALLU  ((u32 *)(V7M_CACHE_MAINT_BASE + 0x00))
+#define INVAL_ICACHE_POU   0
+#define V7M_CACHE_REG_ICIMVALU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x08))
+#define V7M_CACHE_REG_DCIMVAC  ((u32 *)(V7M_CACHE_MAINT_BASE + 0x0C))
+#define V7M_CACHE_REG_DCISW((u32 *)(V7M_CACHE_MAINT_BASE + 0x10))
+#define V7M_CACHE_REG_DCCMVAU  ((u32 *)(V7M_CACHE_MAINT_BASE + 0x14))
+#define V7M_CACHE_REG_DCCMVAC  ((u32 *)(V7M_CACHE_MAINT_BASE + 0x18))
+#define V7M_CACHE_REG_DCCSW((u32 *)(V7M_CACHE_MAINT_BASE + 0x1C))
+#define V7M_CACHE_REG_DCCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x20))
+#define V7M_CACHE_REG_DCCISW   ((u32 *)(V7M_CACHE_MAINT_BASE + 0x24))
+#define WAYS_SHIFT 30
+#define SETS_SHIFT 5
+
+/* armv7m processor feature registers */
+
+#define V7M_PROC_REG_CLIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x00))
+#define V7M_PROC_REG_CTR   ((u32 *)(V7M_PROC_FTR_BASE + 0x04))
+#define V7M_PROC_REG_CCSIDR((u32 *)(V7M_PROC_FTR_BASE + 0x08))
+#define MASK_NUM_WAYS  GENMASK(12, 3)
+#define MASK_NUM_SETS  GENMASK(27, 13)
+#define CLINE_SIZE_MASKGENMASK(2, 0)
+#define NUM_WAYS_SHIFT 3
+#define NUM_SETS_SHIFT 13
+#define V7M_PROC_REG_CSSELR((u32 *)(V7M_PROC_FTR_BASE + 0x0C))
+#define SEL_I_OR_D BIT(0)
+
+enum cache_type {
+   DCACHE,
+   ICACHE,
+};
+
+/* PoU : Point of Unification, Poc: Point of Coherency */
+enum cache_action {
+   INVALIDATE_POU, /* i-cache invalidate by address */
+   INVALIDATE_POC, /* d-cache invalidate by address */
+   INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
+   FLUSH_POU,  /* d-cache clean by address to the PoU */
+   FLUSH_POC,  /* d-cache clean by address to the PoC */
+   FLUSH_SET_WAY,  /* d-cache clean by sets/ways */
+   FLUSH_INVAL_POC,/* d-cache clean & invalidate by addr to PoC */
+   FLUSH_INVAL_SET_WAY,/* d-cache clean & invalidate by set/ways */
+};
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+struct dcache_config {
+   u32 ways;
+   u32 sets;
+};
+
+static void get_cache_ways_sets(struct dcache_config *cache)
+{
+   u32 cache_size_id = readl(V7M_PROC_REG_CCSIDR);
+
+   cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+   cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT;
+}
+
+/*
+ * Return the io register to perform required cache action like clean or clean
+ * & invalidate by sets/ways.
+ */
+static u32 *get_action_reg_set_ways(enum cache_action action)
+{
+   switch (action) {
+   case INVALIDATE_SET_WAY:
+   return V7M_CACHE_REG_DCISW;
+   case FLUSH_SET_WAY:
+   return V7M_CACHE_REG_DCCSW;
+   case FLUSH_INVAL_SET_WAY:
+   return V7M_CACHE_REG_DCCISW;
+   default:
+   break;
+   };
+
+   return NULL;
+}
+
+/*
+ * Return the io register to perform required cache action like clean or clean
+ * 

[U-Boot] [PATCH v4 0/2] add armv7m cache support

[Vikas Manocha]

This patchset adds armv7m instruction/data caches support &
enable it for stm32f7.

Changed in v4:
- invalidate_dcache_range() & flush_dcache_range() function added.
- blank lines added.
- comments added for registers, functions & barriers.
- register names changed for better clarity.
- typecasting moved to macro definitions.

Changed in v3:
- uint32 replcaed with u32.
- multiple read of hardware register replaced with single.
- pointers replaced with macros for base address.
- register names added as comment for system control block registers.

Changed in v2:
- changed strucures for memory mapped cache registers to macros
- added lines better readability.
- replaced magic numbers with macros.

Vikas Manocha (2):
  armv7m: add instruction & data cache support
  stm32f7: enable instruction & data cache

 arch/arm/cpu/armv7m/Makefile  |   3 +-
 arch/arm/cpu/armv7m/cache.c   | 336 ++
 arch/arm/include/asm/armv7m.h |  26 ++-
 arch/arm/lib/Makefile |   2 +
 arch/arm/mach-stm32/stm32f7/soc.c |   2 +
 include/configs/stm32f746-disco.h |   4 +-
 6 files changed, 366 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/cpu/armv7m/cache.c

-- 
1.9.1

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Re: [U-Boot] [PATCH 0/8] rockchip: rk3188: fixups and armclk speedup

[Heiko Stuebner]

Am Montag, 27. März 2017, 12:36:00 CEST schrieb Simon Glass:
> Hi Heiko,
> 
> On 24 March 2017 at 10:04, Heiko Stuebner  wrote:
> > Am Donnerstag, 23. März 2017, 21:28:01 CET schrieb Simon Glass:
> >> Hi Heiko,
> >>
> >> On 20 March 2017 at 05:40, Heiko Stuebner  wrote:
> >> > The ARMCLK starts at 24MHz on the rk3188 which makes u-boot startup
> >> > unnecessary slow. We can easily switch to 600MHz without involving
> >> > the pmic and thus do this in the SPL to also make the rc4-decoding
> >> > of the U-Boot image faster.
> >> >
> >> > Some smaller fixes also turned up while adding the ARMCLK-support.
> >> >
> >> > It's currently based on Simon's spl-working branch and Kever's
> >> > spl_early_init patch, as that includes the last missing rk3188
> >> > patches and also keeps uboot starting on rk3188.
> >>
> >> This should be in mainline now so can you also please test against that?
> >
> > yep, all good.
> >
> > As stated in my fixup series yesterday, this should of course go on
> > top of the final radxarock addition.
> 
> I sent a few patches which get it building for me. Please take a look
> and see what you think.

Patches 1+2 look very nice, see replies.

I'm not sure about the third patch though, as I don't see it affecting the
rock-tpl to much. When looking at the diassembly of the tpl-binary, the
only driver-related functions still present there, are serial_post_probe
and serial_pre_remove.

Yesterday I was playing around with serial options a bit but trying to
disable the default DM_SERIAL seemed to create just more mayhem and
would probably need even more header config settings when saving 26 bytes.

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Re: [U-Boot] [PATCH 2/3] string: Provide a slimmed-down memset()

[Heiko Stuebner]

Am Sonntag, 26. März 2017, 17:38:16 CEST schrieb Simon Glass:
> Most of the time the optimised memset() is what we want. For extreme
> situations such as TPL it may be too large. For example on the 'rock'
> board, using a simple loop saves a useful 48 bytes. With gcc 4.9 and
> the rodata bug, this patch is enough to reduce the TPL image below the
> limit.
> 
> Signed-off-by: Simon Glass 

This brings down the rk3188-rock tpl from 1020 to 972 bytes (with a
1020 byte size limit for the tpl) even with gcc-4.9 and down to 748 bytes
on gcc-6.3.

I was using the original memset in all tests before, so am quite sure
it should work without issues, but cannot test it on actual hardware
this week.


Heiko


> ---
> 
>  lib/Kconfig  | 9 +
>  lib/string.c | 6 --
>  2 files changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/Kconfig b/lib/Kconfig
> index 65c01573e1..5bf512d8c0 100644
> --- a/lib/Kconfig
> +++ b/lib/Kconfig
> @@ -52,6 +52,15 @@ config LIB_RAND
>   help
> This library provides pseudo-random number generator functions.
>  
> +config FAST_MEMSET
> + bool "Use an optimised memset()"
> + default y
> + help
> +   The faster memset() is the arch-specific one (if available) enabled
> +   by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get
> +   better performance by write a word at a time. Disable this option
> +   to reduce code size slightly at the cost of some speed.
> +
>  source lib/dhry/Kconfig
>  
>  source lib/rsa/Kconfig
> diff --git a/lib/string.c b/lib/string.c
> index 67d5f6a421..159493ed17 100644
> --- a/lib/string.c
> +++ b/lib/string.c
> @@ -437,8 +437,10 @@ char *strswab(const char *s)
>  void * memset(void * s,int c,size_t count)
>  {
>   unsigned long *sl = (unsigned long *) s;
> - unsigned long cl = 0;
>   char *s8;
> +
> +#ifdef CONFIG_FAST_MEMSET
> + unsigned long cl = 0;
>   int i;
>  
>   /* do it one word at a time (32 bits or 64 bits) while possible */
> @@ -452,7 +454,7 @@ void * memset(void * s,int c,size_t count)
>   count -= sizeof(*sl);
>   }
>   }
> - /* fill 8 bits at a time */
> +#endif   /* fill 8 bits at a time */
>   s8 = (char *)sl;
>   while (count--)
>   *s8++ = c;
> 


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[U-Boot] [PATCH] serial: ns16550: Link in the DM driver when when using platdata

[Alexandru Gagniuc]

Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA.
This is inconsistent with the majority of other drivers. This also
blocks OF_PLATDATA boards with an 16550-compatible serial from using
serial in SPL.

Signed-off-by: Alexandru Gagniuc 
---
 drivers/serial/ns16550.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 1f819d4..9738a47 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -452,8 +452,7 @@ const struct dm_serial_ops ns16550_serial_ops = {
.setbrg = ns16550_serial_setbrg,
 };
 
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 /*
  * Please consider existing compatible strings before adding a new
  * one to keep this table compact. Or you may add a generic "ns16550"
@@ -473,13 +472,13 @@ static const struct udevice_id ns16550_serial_ids[] = {
{ .compatible = "ti,dra742-uart",   .data = PORT_NS16550 },
{}
 };
-#endif
+#endif /* OF_CONTROL && !OF_PLATDATA */
 
 #if CONFIG_IS_ENABLED(SERIAL_PRESENT)
 U_BOOT_DRIVER(ns16550_serial) = {
.name   = "ns16550_serial",
.id = UCLASS_SERIAL,
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = ns16550_serial_ids,
.ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
@@ -489,6 +488,6 @@ U_BOOT_DRIVER(ns16550_serial) = {
.ops= _serial_ops,
.flags  = DM_FLAG_PRE_RELOC,
 };
-#endif
-#endif /* !OF_PLATDATA */
+#endif /* SERIAL_PRESENT */
+
 #endif /* CONFIG_DM_SERIAL */
-- 
2.9.3

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Re: [U-Boot] [PATCH 1/3] Makefile: Correct dependency race condition with TPL

[Heiko Stuebner]

Am Sonntag, 26. März 2017, 17:38:15 CEST schrieb Simon Glass:
> At present we sometimes see the following build error when building on a
> machine with multiple cores.
> 
> +make[2]: *** No rule to make target 'dts/dt.dtb', needed by 
> 'tpl/u-boot-tpl.dtb'.  Stop.
> 
> Add a dependency to correct this.
> 
> Signed-off-by: Simon Glass 

Fixes the build of rk3188-rock board using buildman for me with more than
one job, which failed very reliable before, so

Tested-by: Heiko Stuebner 

> ---
> 
>  Makefile | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Makefile b/Makefile
> index 1001bc5a7b..5e82b78ade 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1351,7 +1351,8 @@ spl/u-boot-spl.sfp: spl/u-boot-spl
>  spl/boot.bin: spl/u-boot-spl
>   @:
>  
> -tpl/u-boot-tpl.bin: tools prepare
> +tpl/u-boot-tpl.bin: tools prepare \
> + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
>   $(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
>  
>  TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
> 


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Re: [U-Boot] spl: Kconfig: SPL_MMC_SUPPORT depends on GENERIC_MMC

[Alexandru Gagniuc]

On 03/20/2017 05:04 PM, Tom Rini wrote:

On Fri, Mar 17, 2017 at 10:05:40PM -0700, Alexandru Gagniuc wrote:


spl_mmc.c calls mmc_initialize(). This symbol is provided in
drivers/mmc/mmc.c when CONFIG_GENERIC_MMC is enabled.

Signed-off-by: Alexandru Gagniuc 
---
 common/spl/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 60ae60c..0b2b7ff 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -354,6 +354,7 @@ config SPL_LIBGENERIC_SUPPORT
 config SPL_MMC_SUPPORT
bool "Support MMC"
depends on SPL
+   depends on GENERIC_MMC
help
  Enable support for MMC (Multimedia Card) within SPL. This enables
  the MMC protocol implementation and allows any enabled drivers to


This isn't 100% right as it breaks some sunxi boards as-is, CHIP (which
indeed doesn't do MMC) and Nintendo_NES_Classic_Edition.


How exactly does it break things? Do you have a link to build test 
results. If I don't know what's broken, I can't fix it.


Alex
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Re: [U-Boot] [PATCH 0/8] rockchip: rk3188: fixups and armclk speedup

[Simon Glass]

Hi Heiko,

On 24 March 2017 at 10:04, Heiko Stuebner  wrote:
> Am Donnerstag, 23. März 2017, 21:28:01 CET schrieb Simon Glass:
>> Hi Heiko,
>>
>> On 20 March 2017 at 05:40, Heiko Stuebner  wrote:
>> > The ARMCLK starts at 24MHz on the rk3188 which makes u-boot startup
>> > unnecessary slow. We can easily switch to 600MHz without involving
>> > the pmic and thus do this in the SPL to also make the rc4-decoding
>> > of the U-Boot image faster.
>> >
>> > Some smaller fixes also turned up while adding the ARMCLK-support.
>> >
>> > It's currently based on Simon's spl-working branch and Kever's
>> > spl_early_init patch, as that includes the last missing rk3188
>> > patches and also keeps uboot starting on rk3188.
>>
>> This should be in mainline now so can you also please test against that?
>
> yep, all good.
>
> As stated in my fixup series yesterday, this should of course go on
> top of the final radxarock addition.

I sent a few patches which get it building for me. Please take a look
and see what you think.

Regards,
Simon
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[U-Boot] [PATCH 4/5] i.MX6UL: geam6ul: Add mmc_late_init

[Jagan Teki]

From: Jagan Teki 

Let the runtime code can set the mmcdev and mmcroot based
on the devno using mmc_get_env_dev instead of defining
separately in build-time configs using mmc_late_init func.

Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Cc: Stefano Babic 
Signed-off-by: Jagan Teki 
---
 board/engicam/geam6ul/geam6ul.c | 22 ++
 include/configs/imx6ul_geam.h   |  2 --
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c
index 29a4830..3593719 100644
--- a/board/engicam/geam6ul/geam6ul.c
+++ b/board/engicam/geam6ul/geam6ul.c
@@ -7,6 +7,7 @@
  */
 
 #include 
+#include 
 
 #include 
 #include 
@@ -103,12 +104,33 @@ static void setup_gpmi_nand(void)
 }
 #endif /* CONFIG_NAND_MXS */
 
+#ifdef CONFIG_ENV_IS_IN_MMC
+static void mmc_late_init(void)
+{
+   char cmd[32];
+   char mmcblk[32];
+   u32 dev_no = mmc_get_env_dev();
+
+   setenv_ulong("mmcdev", dev_no);
+
+   /* Set mmcblk env */
+   sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
+   setenv("mmcroot", mmcblk);
+
+   sprintf(cmd, "mmc dev %d", dev_no);
+   run_command(cmd, 0);
+}
+#endif
+
 int board_late_init(void)
 {
switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
+#ifdef CONFIG_ENV_IS_IN_MMC
+   mmc_late_init();
+#endif
setenv("modeboot", "mmcboot");
break;
case IMX6_BMODE_NAND:
diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h
index e9a1a06..d331744 100644
--- a/include/configs/imx6ul_geam.h
+++ b/include/configs/imx6ul_geam.h
@@ -44,9 +44,7 @@
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x8780\0" \
"boot_fdt=try\0" \
-   "mmcdev=0\0" \
"mmcpart=1\0" \
-   "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
-- 
1.9.1

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[U-Boot] [PATCH 2/5] i.MX6Q: icorem6: Add mmc_late_init

[Jagan Teki]

From: Jagan Teki 

Let the runtime code can set the mmcdev and mmcroot based
on the devno using mmc_get_env_dev instead of defining
separately in build-time configs using mmc_late_init func.

Cc: Stefano Babic 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 board/engicam/icorem6/icorem6.c | 22 ++
 include/configs/imx6qdl_icore.h |  2 --
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index f78f8c9..55fc77f 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -7,6 +7,7 @@
  */
 
 #include 
+#include 
 
 #include 
 #include 
@@ -205,12 +206,33 @@ int board_early_init_f(void)
return 0;
 }
 
+#ifdef CONFIG_ENV_IS_IN_MMC
+static void mmc_late_init(void)
+{
+   char cmd[32];
+   char mmcblk[32];
+   u32 dev_no = mmc_get_env_dev();
+
+   setenv_ulong("mmcdev", dev_no);
+
+   /* Set mmcblk env */
+   sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
+   setenv("mmcroot", mmcblk);
+
+   sprintf(cmd, "mmc dev %d", dev_no);
+   run_command(cmd, 0);
+}
+#endif
+
 int board_late_init(void)
 {
switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
+#ifdef CONFIG_ENV_IS_IN_MMC
+   mmc_late_init();
+#endif
setenv("modeboot", "mmcboot");
break;
case IMX6_BMODE_NAND:
diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h
index b517e87..4bdba57 100644
--- a/include/configs/imx6qdl_icore.h
+++ b/include/configs/imx6qdl_icore.h
@@ -45,9 +45,7 @@
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x1800\0" \
"boot_fdt=try\0" \
-   "mmcdev=0\0" \
"mmcpart=1\0" \
-   "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
-- 
1.9.1

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[U-Boot] [PATCH 5/5] MAINTAINERS: Fix ARM FREESCALE IMX files

[Jagan Teki]

From: Jagan Teki 

- Remove arch/arm/cpu/arm926ejs/imx/ which is not available
- arch/arm/cpu/imx-common/ => arch/arm/imx-common/

Cc: Stefano Babic 
Signed-off-by: Jagan Teki 
---
 MAINTAINERS | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 19c0eed..c60cd2a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -93,10 +93,9 @@ S:   Maintained
 T: git git://git.denx.de/u-boot-imx.git
 F: arch/arm/cpu/arm1136/mx*/
 F: arch/arm/cpu/arm926ejs/mx*/
-F: arch/arm/cpu/arm926ejs/imx/
 F: arch/arm/cpu/armv7/mx*/
 F: arch/arm/cpu/armv7/vf610/
-F: arch/arm/cpu/imx-common/
+F: arch/arm/imx-common/
 F: arch/arm/include/asm/arch-imx/
 F: arch/arm/include/asm/arch-mx*/
 F: arch/arm/include/asm/arch-vf610/
-- 
1.9.1

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[U-Boot] [PATCH 3/5] i.MX6UL: geam6ul: Add modeboot env via board_late_init

[Jagan Teki]

From: Jagan Teki 

Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.

Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Cc: Stefano Babic 
Signed-off-by: Jagan Teki 
---
 arch/arm/cpu/armv7/mx6/Kconfig  |  1 +
 board/engicam/geam6ul/geam6ul.c | 19 +++
 include/configs/imx6ul_geam.h   | 35 ---
 3 files changed, 36 insertions(+), 19 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 37f271b..3170442 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -244,6 +244,7 @@ config TARGET_MX6UL_14X14_EVK
 
 config TARGET_MX6UL_GEAM
bool "Support Engicam GEAM6UL"
+   select BOARD_LATE_INIT
select MX6UL
select OF_CONTROL
select DM
diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c
index 40f20a9..29a4830 100644
--- a/board/engicam/geam6ul/geam6ul.c
+++ b/board/engicam/geam6ul/geam6ul.c
@@ -103,6 +103,25 @@ static void setup_gpmi_nand(void)
 }
 #endif /* CONFIG_NAND_MXS */
 
+int board_late_init(void)
+{
+   switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
+   IMX6_BMODE_SHIFT) {
+   case IMX6_BMODE_SD:
+   case IMX6_BMODE_ESD:
+   setenv("modeboot", "mmcboot");
+   break;
+   case IMX6_BMODE_NAND:
+   setenv("modeboot", "nandboot");
+   break;
+   default:
+   setenv("modeboot", "");
+   break;
+   }
+
+   return 0;
+}
+
 int board_init(void)
 {
/* Address of boot parameters */
diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h
index 8bffacd..e9a1a06 100644
--- a/include/configs/imx6ul_geam.h
+++ b/include/configs/imx6ul_geam.h
@@ -63,7 +63,7 @@
"fitboot=echo Booting FIT image from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
-   "mmcboot=echo Booting from mmc ...; " \
+   "_mmcboot=run mmcargs; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
@@ -78,6 +78,20 @@
"else " \
"bootm; " \
"fi\0" \
+   "mmcboot=echo Booting from mmc ...; " \
+   "if mmc rescan; then " \
+   "if run loadbootscript; then " \
+   "run bootscript; " \
+   "else " \
+   "if run loadfit; then " \
+   "run fitboot; " \
+   "else " \
+   "if run loadimage; then " \
+   "run _mmcboot; " \
+   "fi; " \
+   "fi; " \
+   "fi; " \
+   "fi\0" \
"nandboot=echo Booting from nand ...; " \
"if mtdparts; then " \
"echo Starting nand boot ...; " \
@@ -89,24 +103,7 @@
"nand read ${fdt_addr} dtb 0x10; " \
"bootm ${loadaddr} - ${fdt_addr}\0"
 
-#ifdef CONFIG_NAND_MXS
-# define CONFIG_BOOTCOMMAND"run nandboot"
-#else
-# define CONFIG_BOOTCOMMAND \
-   "if mmc rescan; then " \
-   "if run loadbootscript; then " \
-   "run bootscript; " \
-   "else " \
-   "if run loadfit; then " \
-   "run fitboot; " \
-   "else " \
-   "if run loadimage; then " \
-   "run mmcboot; " \
-   "fi; " \
-   "fi; " \
-   "fi; " \
-   "fi"
-#endif
+#define CONFIG_BOOTCOMMAND "run $modeboot"
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_MEMTEST_START   0x8000
-- 
1.9.1

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[U-Boot] [PATCH 1/5] i.MX6Q: icorem6: Add modeboot env via board_late_init

[Jagan Teki]

From: Jagan Teki 

Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.

Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Cc: Stefano Babic 
Signed-off-by: Jagan Teki 
---
 arch/arm/cpu/armv7/mx6/Kconfig  |  1 +
 board/engicam/icorem6/icorem6.c | 19 +++
 include/configs/imx6qdl_icore.h | 36 
 3 files changed, 36 insertions(+), 20 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 9174136..37f271b 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -160,6 +160,7 @@ config TARGET_MX6QARM2
 
 config TARGET_MX6Q_ICORE
bool "Support Engicam i.Core"
+   select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
select DM
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index 171ec45..f78f8c9 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -205,6 +205,25 @@ int board_early_init_f(void)
return 0;
 }
 
+int board_late_init(void)
+{
+   switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
+   IMX6_BMODE_SHIFT) {
+   case IMX6_BMODE_SD:
+   case IMX6_BMODE_ESD:
+   setenv("modeboot", "mmcboot");
+   break;
+   case IMX6_BMODE_NAND:
+   setenv("modeboot", "nandboot");
+   break;
+   default:
+   setenv("modeboot", "");
+   break;
+   }
+
+   return 0;
+}
+
 int board_init(void)
 {
/* Address of boot parameters */
diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h
index 5a28b15..b517e87 100644
--- a/include/configs/imx6qdl_icore.h
+++ b/include/configs/imx6qdl_icore.h
@@ -64,7 +64,7 @@
"fitboot=echo Booting FIT image from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
-   "mmcboot=echo Booting from mmc ...; " \
+   "_mmcboot=run mmcargs; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
@@ -79,6 +79,20 @@
"else " \
"bootm; " \
"fi\0" \
+   "mmcboot=echo Booting from mmc ...; " \
+   "if mmc rescan; then " \
+   "if run loadbootscript; then " \
+   "run bootscript; " \
+   "else " \
+   "if run loadfit; then " \
+   "run fitboot; " \
+   "else " \
+   "if run loadimage; then " \
+   "run _mmcboot; " \
+   "fi; " \
+   "fi; " \
+   "fi; " \
+   "fi\0" \
"nandboot=echo Booting from nand ...; " \
"if mtdparts; then " \
"echo Starting nand boot ...; " \
@@ -90,25 +104,7 @@
"nand read ${fdt_addr} dtb 0x10; " \
"bootm ${loadaddr} - ${fdt_addr}\0"
 
-#ifdef CONFIG_NAND_MXS
-# define CONFIG_BOOTCOMMAND"run nandboot"
-#else
-# define CONFIG_BOOTCOMMAND \
-   "mmc dev ${mmcdev};" \
-   "if mmc rescan; then " \
-   "if run loadbootscript; then " \
-   "run bootscript; " \
-   "else " \
-   "if run loadfit; then " \
-   "run fitboot; " \
-   "else " \
-   "if run loadimage; then " \
-   "run mmcboot; " \
-   "fi; " \
-   "fi; " \
-   "fi; " \
-   "fi"
-#endif
+#define CONFIG_BOOTCOMMAND "run $modeboot"
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_MEMTEST_START   0x8000
-- 
1.9.1

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Re: [U-Boot] [PATCH v2] net: designware: Add phy supply support

[Joe Hershberger]

On Mon, Mar 27, 2017 at 3:54 AM, Jacob Chen  wrote:
> Some board need a regulator for gmac phy, so add this code to handle it.
> Signed-off-by: Jacob Chen 

Acked-by: Joe Hershberger 
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Re: [U-Boot] sf: Remove spansion_s25fss_disable_4KB_erase

[Jagan Teki]

On Mon, Mar 27, 2017 at 11:05 PM, york sun  wrote:
> On 03/15/2017 06:44 PM, york@nxp.com wrote:
>> On 01/27/2017 10:04 AM, Jagan Teki wrote:
>>> On Mon, Jan 23, 2017 at 8:05 PM, york sun  wrote:
 On 12/12/2016 09:32 PM, Yao Yuan wrote:
> Hi Jagan,
>
>
>
> Do you have any comments?
>
>
>
> Thanks for your work and you know it’s important for QSPI with
> S25FS512S.
>
>
>
> It seems S25FS512S can’t support the SECT_4K, right?
>
> And it better to retain the disable_4kb, but we can add a flag in
> dts to
> select whether enable it.
>
>

 Jagan,

 This is blocking me from using the board with this specific flash chip.
 Can you take a look? By reverting this single commit 116e005c, my board
 works again.
>>>
>>> I will try to work on this.
>>>
>>
>> Guys,
>>
>> Where are we on this issue?
>>
>> York
>>
>
> Can we revert this patch or have a fix?

Just wanted to understand more about this, I've attached programming
model in previous mail about this and based on that I've fixed with
all 4K. Waiting for 'Yao Yuan' inputs on this.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] sf: Remove spansion_s25fss_disable_4KB_erase

[york sun]

On 03/15/2017 06:44 PM, york@nxp.com wrote:
> On 01/27/2017 10:04 AM, Jagan Teki wrote:
>> On Mon, Jan 23, 2017 at 8:05 PM, york sun  wrote:
>>> On 12/12/2016 09:32 PM, Yao Yuan wrote:
 Hi Jagan,



 Do you have any comments?



 Thanks for your work and you know it’s important for QSPI with
 S25FS512S.



 It seems S25FS512S can’t support the SECT_4K, right?

 And it better to retain the disable_4kb, but we can add a flag in
 dts to
 select whether enable it.


>>>
>>> Jagan,
>>>
>>> This is blocking me from using the board with this specific flash chip.
>>> Can you take a look? By reverting this single commit 116e005c, my board
>>> works again.
>>
>> I will try to work on this.
>>
>
> Guys,
>
> Where are we on this issue?
>
> York
>

Can we revert this patch or have a fix?

York

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Re: [U-Boot] [PATCH v3 39/45] net: mvpp2: Add GoP and NetC support for port 0 (SFI)

[Joe Hershberger]

On Mon, Mar 27, 2017 at 7:00 AM, Stefan Roese  wrote:
> This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
> the Marvell mvpp2 ethernet driver for the missing port 0. This code is
> mostly copied from the Marvell U-Boot version and was written by Stefan
> Chulski. Please note that only SFI support have been added, as this
> is the only interface that this code has been tested with. XAUI and
> RXAUI support might follow at a later stage.
>
> Signed-off-by: Stefan Roese 
> Cc: Stefan Chulski 
> Cc: Kostya Porotchkin 
> Cc: Nadav Haklai 
> Cc: Joe Hershberger 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH v3 38/45] net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)

[Joe Hershberger]

Hi Stefan,

On Mon, Mar 27, 2017 at 7:00 AM, Stefan Roese  wrote:
> This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
> the Marvell mvpp2 ethernet driver. This code is mostly copied from the
> Marvell U-Boot version and was written by Stefan Chulski. Please
> note that only RGMII and SGMII support have been added, as these are
> the only interfaces that this code has been tested with.
>
> Signed-off-by: Stefan Roese 
> Cc: Stefan Chulski 
> Cc: Kostya Porotchkin 
> Cc: Nadav Haklai 
> Cc: Joe Hershberger 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH v3] net: Kconfig:make PHY_GIGE and individual Micrel PHYs selectable

[Joe Hershberger]

On Sun, Mar 26, 2017 at 11:50 AM, Philipp Tomsich
 wrote:
> This change migrate the following configuration options for Kconfig:
>  * PHY_GIGE, indicates that a controller (with an appropriate PHY) is
>Gigabit capable and enables extra support in the miiutil for
>parsing the status of Gigabit PHYs
>  * adds configuration options for Micrel KSZ9021 and KSZ9031 GbE PHYs,
>which previously had to enabled through a board-specific config file
>
> Signed-off-by: Philipp Tomsich 

Acked-by: Joe Hershberger 

> ---
>
> Changes in v3:
> - add a label to the PHY_GIGE option to make it selectable via menuconf
> - automatically select PHY_GIGE when a KSZ9021 or KSZ9031 is selected
> - fix indentations (convert spaces to tabs)
> - adds help text for PHY_MICREL
>
> Changes in v2:
> - migrate PHY_GIGE to Kconfig
>
>  drivers/net/Kconfig |  8 
>  drivers/net/phy/Kconfig | 34 ++
>  2 files changed, 42 insertions(+)
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 70e3661..653ee5a 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -22,6 +22,13 @@ menuconfig NETDEVICES
>
>  if NETDEVICES
>
> +config PHY_GIGE
> +   bool "Enable GbE PHY status parsing and configuration"
> +   help
> + Enables support for parsing the status output and for
> + configuring GbE PHYs (affects the inner workings of some
> + commands and miiphyutil.c).
> +
>  config AG7XXX
> bool "Atheros AG7xxx Ethernet MAC support"
> depends on DM_ETH && ARCH_ATH79
> @@ -165,6 +172,7 @@ config SUN8I_EMAC
>  bool "Allwinner Sun8i Ethernet MAC support"
>  depends on DM_ETH
>  select PHYLIB
> +   select PHY_GIGE
>  help
>This driver supports the  Allwinner based SUN8I/SUN50I Ethernet 
> MAC.
>   It can be found in H3/A64/A83T based SoCs and compatible with both
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index 1d514e9..e2dfd88 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -44,6 +44,40 @@ config PHY_MARVELL
>
>  config PHY_MICREL
> bool "Micrel Ethernet PHYs support"
> +   help
> + Enable support for the GbE PHYs manufactured by Micrel (now
> + a part of Microchip). This includes drivers for the KSZ804,
> + KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, KSZ8721
> + either/or KSZ9021 (see the "Micrel KSZ9021 family support"
> + config option for details), and KSZ9031 (if configured).
> +
> +if PHY_MICREL
> +
> +config PHY_MICREL_KSZ9021
> +   bool "Micrel KSZ9021 family support"
> +   select PHY_GIGE
> +   help
> + Enable support for the Micrel KSZ9021 GbE PHY family.  If
> + enabled, the extended register read/write for KSZ9021 PHYs
> + is supported through the 'mdio' command and any RGMII signal
> + delays configured in the device tree will be applied to the
> + PHY during initialisation.

Typo here, but I'll fix it up.

> +
> + Note that the KSZ9021 uses the same part number os the
> + KSZ8921BL, so enabling this option disables support for the
> + KSZ8721BL.
> +
> +config PHY_MICREL_KSZ9031
> +   bool "Micrel KSZ9031 family support"
> +   select PHY_GIGE
> +   help
> + Enable support for the Micrel KSZ9031 GbE PHY family.  If
> + enabled, the extended register read/write for KSZ9021 PHYs
> + is supported through the 'mdio' command and any RGMII signal
> + delays configured in the device tree will be applied to the
> + PHY during initialisatioin.

Typo here, but I'll fix it up.

> +
> +endif # PHY_MICREL
>
>  config PHY_MSCC
> bool "Microsemi Corp Ethernet PHYs support"
> --
> 1.9.1
>
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[U-Boot] [PATCH v3 6/6] [DO NOT MERGE] sunxi: add AXP803 support

[Jernej Skrabec]

From: Icenowy Zheng 

The A64 uses the AXP803 as its PMIC.

Signed-off-by: Icenowy Zheng 
Signed-off-by: Jernej Skrabec 
---

 arch/arm/mach-sunxi/Makefile   |   3 +
 arch/arm/mach-sunxi/pmic_bus.c |   6 +-
 arch/arm/mach-sunxi/rsb.c  |   2 +-
 board/sunxi/board.c|  31 ++---
 drivers/power/Kconfig  |  87 --
 drivers/power/Makefile |   1 +
 drivers/power/axp803.c | 256 +
 drivers/power/axp818.c |   2 +-
 include/axp803.h   |  73 
 include/axp_pmic.h |   3 +
 10 files changed, 414 insertions(+), 50 deletions(-)
 create mode 100644 drivers/power/axp803.c
 create mode 100644 include/axp803.h

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index efab4811ee..861a52c6d0 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -19,9 +19,11 @@ endif
 obj-$(CONFIG_MACH_SUN6I)   += prcm.o
 obj-$(CONFIG_MACH_SUN8I)   += prcm.o
 obj-$(CONFIG_MACH_SUN9I)   += prcm.o
+obj-$(CONFIG_MACH_SUN50I)  += prcm.o
 obj-$(CONFIG_MACH_SUN6I)   += p2wi.o
 obj-$(CONFIG_MACH_SUN8I)   += rsb.o
 obj-$(CONFIG_MACH_SUN9I)   += rsb.o
+obj-$(CONFIG_MACH_SUN50I)  += rsb.o
 obj-$(CONFIG_MACH_SUN4I)   += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)   += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)   += clock_sun6i.o
@@ -37,6 +39,7 @@ obj-$(CONFIG_MACH_SUN9I)  += clock_sun9i.o gtbus_sun9i.o
 obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
+obj-$(CONFIG_AXP803_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP809_POWER) += pmic_bus.o
 obj-$(CONFIG_AXP818_POWER) += pmic_bus.o
 
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 7c57f02792..0ac64a97cf 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -36,7 +36,7 @@ int pmic_bus_init(void)
if (!needs_init)
return 0;
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined 
CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
p2wi_init();
ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
@@ -62,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data)
return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
 #elif defined CONFIG_AXP209_POWER
return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined 
CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
return p2wi_read(reg, data);
 # else
@@ -77,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data)
return i2c_write(AXP152_I2C_ADDR, reg, 1, , 1);
 #elif defined CONFIG_AXP209_POWER
return i2c_write(AXP209_I2C_ADDR, reg, 1, , 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined 
CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined 
CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
return p2wi_write(reg, data);
 # else
diff --git a/arch/arm/mach-sunxi/rsb.c b/arch/arm/mach-sunxi/rsb.c
index 6fd11f1529..28d05e962a 100644
--- a/arch/arm/mach-sunxi/rsb.c
+++ b/arch/arm/mach-sunxi/rsb.c
@@ -20,7 +20,7 @@ static int rsb_set_device_mode(void);
 
 static void rsb_cfg_io(void)
 {
-#ifdef CONFIG_MACH_SUN8I
+#if defined CONFIG_MACH_SUN8I || defined CONFIG_MACH_SUN50I
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index b9660128e5..75e53bebbd 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -487,26 +487,27 @@ void sunxi_board_init(void)
 #endif
 
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
-   defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-   defined CONFIG_AXP818_POWER
+   defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+   defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
power_failed = axp_init();
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-   defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+   defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
 #endif
power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
-#if 

[U-Boot] [PATCH v3 0/6] sunxi: video: Add support for HDMI output on A64/H3/H5

[Jernej Skrabec]

This series implements support for HDMI output. This is done using
DM video framework and sharing the HDMI controller code with RK3288.

Patch 1 splits out TCON code which is completely reusable on
all Allwinner SoCs.

Patch 2 converts common TCON code to use DM video compatible timing
structure.

Patch 3 adds all necessary clocks which are needed for Display
Engine 2, TCON and HDMI.

Patch 4 implement actual DE2 and HDMI driver and patch 5 disables HDMI
on all boards which don't have it (default is on).

Patch 6 is included here only for testing HDMI output on A64 due
to missing power regulator support (AXP803). Another option is to
use ATF which powers on HDMI. Such ATF can be found on Andre
Przywara's github.

Code was tested on OrangePi 2 & OrangePi Plus 2E (both H3),
OrangePi PC 2 (H5) and Pine64 (A64). It was tested on A10, A13 and A20
boards by others.

This series was developed on u-boot-sunxi repository with additional,
not yet merged, patch: https://patchwork.ozlabs.org/patch/735617/

All Rockchip patches were already merged to u-boot-rockchip repository
and are not yet present in u-boot-sunxi. They have to be cherry picked:
a0a2774aebdaa039ce787090c903cf47263f04c9
520c174b3564ae183f0e7c118dc8ce3770ae20b0
3bffe88d68e43b7bead12ef8020267fabc6c7ebf

Best regards,
Jernej Skrabec

Changes in v3:
- drop patch 1 because it was merged
- changed video output to 32 bpp
- collect acked by tags
- convert preprocessor symbol to Kconfig option (patch 3)
- Kconfig option in patch 4 depends on new option

Changes in v2:
- patch 1 & 2 were removed because they were merged
- collect reviewed by and tested by tags
- TCON split out patch is splitted in two patches
- fixed lcdc_enable() calls in video driver for old SoCs
- defconfigs should disable video driver, not enable it
- minor constant style fix


Icenowy Zheng (1):
  [DO NOT MERGE] sunxi: add AXP803 support

Jernej Skrabec (5):
  sunxi: video: Split out TCON code
  sunxi: video: Convert lcdc to use struct display_timing
  sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs
  sunxi: video: Add A64/H3/H5 HDMI driver
  sunxi: Disable DE2 video driver where not needed

 arch/arm/include/asm/arch-sunxi/clock_sun6i.h |  54 
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h   |   8 +
 arch/arm/include/asm/arch-sunxi/display.h | 103 ---
 arch/arm/include/asm/arch-sunxi/display2.h| 124 
 arch/arm/include/asm/arch-sunxi/lcdc.h| 128 +
 arch/arm/mach-sunxi/Makefile  |   3 +
 arch/arm/mach-sunxi/clock_sun6i.c |  40 ++-
 arch/arm/mach-sunxi/pmic_bus.c|   6 +-
 arch/arm/mach-sunxi/rsb.c |   2 +-
 board/sunxi/Kconfig   |  16 ++
 board/sunxi/board.c   |  31 +-
 configs/nanopi_neo_air_defconfig  |   1 +
 configs/nanopi_neo_defconfig  |   1 +
 configs/orangepi_zero_defconfig   |   1 +
 drivers/power/Kconfig |  87 +++---
 drivers/power/Makefile|   1 +
 drivers/power/axp803.c| 256 +
 drivers/power/axp818.c|   2 +-
 drivers/video/Makefile|   2 +-
 drivers/video/sunxi/Makefile  |   9 +
 drivers/video/sunxi/lcdc.c| 209 ++
 drivers/video/sunxi/sunxi_de2.c   | 258 +
 drivers/video/{ => sunxi}/sunxi_display.c | 220 +++
 drivers/video/sunxi/sunxi_dw_hdmi.c   | 389 ++
 include/axp803.h  |  73 +
 include/axp_pmic.h|   3 +
 include/configs/sunxi-common.h|   5 +
 27 files changed, 1701 insertions(+), 331 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/display2.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/lcdc.h
 create mode 100644 drivers/power/axp803.c
 create mode 100644 drivers/video/sunxi/Makefile
 create mode 100644 drivers/video/sunxi/lcdc.c
 create mode 100644 drivers/video/sunxi/sunxi_de2.c
 rename drivers/video/{ => sunxi}/sunxi_display.c (87%)
 create mode 100644 drivers/video/sunxi/sunxi_dw_hdmi.c
 create mode 100644 include/axp803.h

-- 
2.12.1

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[U-Boot] [PATCH v3 5/6] sunxi: Disable DE2 video driver where not needed

[Jernej Skrabec]

Because DE2 driver is enabled by default, it is nice to disable it on
all boards which don't have any video output. List of such boards is
also much shorter.

Signed-off-by: Jernej Skrabec 
Acked-by: Maxime Ripard 
---
Changes in v3:
- add acked by tag

Changes in v2:
- invert logic (disable instead of enable)

 configs/nanopi_neo_air_defconfig | 1 +
 configs/nanopi_neo_defconfig | 1 +
 configs/orangepi_zero_defconfig  | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig
index 9598bd5cd5..5400d37bd1 100644
--- a/configs/nanopi_neo_air_defconfig
+++ b/configs/nanopi_neo_air_defconfig
@@ -15,3 +15,4 @@ CONFIG_SPL=y
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_EHCI_HCD=y
+# CONFIG_VIDEO_DE2 is not set
diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig
index 89f5687884..5afd5d565a 100644
--- a/configs/nanopi_neo_defconfig
+++ b/configs/nanopi_neo_defconfig
@@ -16,3 +16,4 @@ CONFIG_SPL=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
+# CONFIG_VIDEO_DE2 is not set
diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
index abb3fcf307..f5947d121b 100644
--- a/configs/orangepi_zero_defconfig
+++ b/configs/orangepi_zero_defconfig
@@ -15,3 +15,4 @@ CONFIG_SUN8I_EMAC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SPL_SPI_SUNXI=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
+# CONFIG_VIDEO_DE2 is not set
-- 
2.12.1

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[U-Boot] [PATCH v3 4/6] sunxi: video: Add A64/H3/H5 HDMI driver

[Jernej Skrabec]

This commit adds support for HDMI output.

Signed-off-by: Jernej Skrabec 
Reviewed-by: Simon Glass 
Acked-by: Maxime Ripard 
---
Changes in v3:
- changed to 32 bpp
- add acked by tag
- VIDEO_DE2 option now depends on SUNXI_DE2

Changes in v2:
- add reviewed by tag

 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |   8 +
 arch/arm/include/asm/arch-sunxi/display2.h  | 124 +
 board/sunxi/Kconfig |  10 +
 drivers/video/sunxi/Makefile|   1 +
 drivers/video/sunxi/sunxi_de2.c | 258 ++
 drivers/video/sunxi/sunxi_dw_hdmi.c | 389 
 include/configs/sunxi-common.h  |   5 +
 7 files changed, 795 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/display2.h
 create mode 100644 drivers/video/sunxi/sunxi_de2.c
 create mode 100644 drivers/video/sunxi/sunxi_dw_hdmi.c

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index ea672fe844..3ce46d024e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -18,6 +18,8 @@
 #define SUNXI_SRAM_D_BASE  0x0001  /* 4 kiB */
 #define SUNXI_SRAM_B_BASE  0x0002  /* 64 kiB (secure) */
 
+#define SUNXI_DE2_BASE 0x0100
+
 #ifdef CONFIG_MACH_SUN8I_A83T
 #define SUNXI_CPUCFG_BASE  0x0170
 #endif
@@ -46,7 +48,9 @@
 #define SUNXI_USB1_BASE0x01c14000
 #endif
 #define SUNXI_SS_BASE  0x01c15000
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
 #define SUNXI_HDMI_BASE0x01c16000
+#endif
 #define SUNXI_SPI2_BASE0x01c17000
 #define SUNXI_SATA_BASE0x01c18000
 #ifdef CONFIG_SUNXI_GEN_SUN4I
@@ -164,6 +168,10 @@ defined(CONFIG_MACH_SUN50I)
 #define SUNXI_MP_BASE  0x01e8
 #define SUNXI_AVG_BASE 0x01ea
 
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+#define SUNXI_HDMI_BASE0x01ee
+#endif
+
 #define SUNXI_RTC_BASE 0x01f0
 #define SUNXI_PRCM_BASE0x01f01400
 
diff --git a/arch/arm/include/asm/arch-sunxi/display2.h 
b/arch/arm/include/asm/arch-sunxi/display2.h
new file mode 100644
index 00..b5875f9605
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/display2.h
@@ -0,0 +1,124 @@
+/*
+ * Sunxi platform display controller register and constant defines
+ *
+ * (C) Copyright 2017 Jernej Skrabec 
+ *
+ * Based on out of tree Linux DRM driver defines:
+ * Copyright (C) 2016 Jean-Francois Moine 
+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
+*
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_DISPLAY2_H
+#define _SUNXI_DISPLAY2_H
+
+/* internal clock settings */
+struct de_clk {
+   u32 gate_cfg;
+   u32 bus_cfg;
+   u32 rst_cfg;
+   u32 div_cfg;
+   u32 sel_cfg;
+};
+
+/* global control */
+struct de_glb {
+   u32 ctl;
+   u32 status;
+   u32 dbuff;
+   u32 size;
+};
+
+/* alpha blending */
+struct de_bld {
+   u32 fcolor_ctl;
+   struct {
+   u32 fcolor;
+   u32 insize;
+   u32 offset;
+   u32 dum;
+   } attr[4];
+   u32 dum0[15];
+   u32 route;
+   u32 premultiply;
+   u32 bkcolor;
+   u32 output_size;
+   u32 bld_mode[4];
+   u32 dum1[4];
+   u32 ck_ctl;
+   u32 ck_cfg;
+   u32 dum2[2];
+   u32 ck_max[4];
+   u32 dum3[4];
+   u32 ck_min[4];
+   u32 dum4[3];
+   u32 out_ctl;
+};
+
+/* VI channel */
+struct de_vi {
+   struct {
+   u32 attr;
+   u32 size;
+   u32 coord;
+   u32 pitch[3];
+   u32 top_laddr[3];
+   u32 bot_laddr[3];
+   } cfg[4];
+   u32 fcolor[4];
+   u32 top_haddr[3];
+   u32 bot_haddr[3];
+   u32 ovl_size[2];
+   u32 hori[2];
+   u32 vert[2];
+};
+
+struct de_ui {
+   struct {
+   u32 attr;
+   u32 size;
+   u32 coord;
+   u32 pitch;
+   u32 top_laddr;
+   u32 bot_laddr;
+   u32 fcolor;
+   u32 dum;
+   } cfg[4];
+   u32 top_haddr;
+   u32 bot_haddr;
+   u32 ovl_size;
+};
+
+/*
+ * DE register constants.
+ */
+#define SUNXI_DE2_MUX0_BASE(SUNXI_DE2_BASE + 0x10)
+#define SUNXI_DE2_MUX1_BASE(SUNXI_DE2_BASE + 0x20)
+
+#define SUNXI_DE2_MUX_GLB_REGS 0x0
+#define SUNXI_DE2_MUX_BLD_REGS 0x01000
+#define SUNXI_DE2_MUX_CHAN_REGS0x02000
+#define SUNXI_DE2_MUX_CHAN_SZ  0x1000
+#define 

[U-Boot] [PATCH v3 3/6] sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

[Jernej Skrabec]

This is needed for HDMI, which will be added later.

Signed-off-by: Jernej Skrabec 
Reviewed-by: Simon Glass 
---
Changes in v3:
- convert define to Kconfig option

Changes in v2:
- add reviewed by tag
- constant style fix

 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 54 +++
 arch/arm/mach-sunxi/clock_sun6i.c | 40 +++-
 board/sunxi/Kconfig   |  6 +++
 drivers/video/sunxi/lcdc.c|  4 ++
 4 files changed, 103 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 1aefd5a64c..a44ea77576 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -67,13 +67,22 @@ struct sunxi_ccm_reg {
u32 dram_pll_cfg;   /* 0xf8 PLL_DDR cfg register, A33 only */
u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */
u32 dram_clk_gate;  /* 0x100 DRAM module gating */
+#ifdef CONFIG_SUNXI_DE2
+   u32 de_clk_cfg; /* 0x104 DE module clock */
+#else
u32 be0_clk_cfg;/* 0x104 BE0 module clock */
+#endif
u32 be1_clk_cfg;/* 0x108 BE1 module clock */
u32 fe0_clk_cfg;/* 0x10c FE0 module clock */
u32 fe1_clk_cfg;/* 0x110 FE1 module clock */
u32 mp_clk_cfg; /* 0x114 MP module clock */
+#ifdef CONFIG_SUNXI_DE2
+   u32 lcd0_clk_cfg;   /* 0x118 LCD0 module clock */
+   u32 lcd1_clk_cfg;   /* 0x11c LCD1 module clock */
+#else
u32 lcd0_ch0_clk_cfg;   /* 0x118 LCD0 CH0 module clock */
u32 lcd1_ch0_clk_cfg;   /* 0x11c LCD1 CH0 module clock */
+#endif
u32 reserved14[3];
u32 lcd0_ch1_clk_cfg;   /* 0x12c LCD0 CH1 module clock */
u32 lcd1_ch1_clk_cfg;   /* 0x130 LCD1 CH1 module clock */
@@ -85,7 +94,11 @@ struct sunxi_ccm_reg {
u32 dmic_clk_cfg;   /* 0x148 Digital Mic module clock*/
u32 reserved15;
u32 hdmi_clk_cfg;   /* 0x150 HDMI module clock */
+#ifdef CONFIG_SUNXI_DE2
+   u32 hdmi_slow_clk_cfg;  /* 0x154 HDMI slow module clock */
+#else
u32 ps_clk_cfg; /* 0x154 PS module clock */
+#endif
u32 mtc_clk_cfg;/* 0x158 MTC module clock */
u32 mbus0_clk_cfg;  /* 0x15c MBUS0 module clock */
u32 mbus1_clk_cfg;  /* 0x160 MBUS1 module clock */
@@ -193,6 +206,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL3_CTRL_N_MASK   (0x7f << CCM_PLL3_CTRL_N_SHIFT)
 #define CCM_PLL3_CTRL_N(n) n) - 1) & 0x7f) << 8)
 #define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24)
+#define CCM_PLL3_CTRL_LOCK (0x1 << 28)
 #define CCM_PLL3_CTRL_EN   (0x1 << 31)
 
 #define CCM_PLL5_CTRL_M(n) n) - 1) & 0x3) << 0)
@@ -222,6 +236,16 @@ struct sunxi_ccm_reg {
 #define CCM_MIPI_PLL_CTRL_LDO_EN   (0x3 << 22)
 #define CCM_MIPI_PLL_CTRL_EN   (0x1 << 31)
 
+#define CCM_PLL10_CTRL_M_SHIFT 0
+#define CCM_PLL10_CTRL_M_MASK  (0xf << CCM_PLL10_CTRL_M_SHIFT)
+#define CCM_PLL10_CTRL_M(n)n) - 1) & 0xf) << 0)
+#define CCM_PLL10_CTRL_N_SHIFT 8
+#define CCM_PLL10_CTRL_N_MASK  (0x7f << CCM_PLL10_CTRL_N_SHIFT)
+#define CCM_PLL10_CTRL_N(n)n) - 1) & 0x7f) << 8)
+#define CCM_PLL10_CTRL_INTEGER_MODE(0x1 << 24)
+#define CCM_PLL10_CTRL_LOCK(0x1 << 28)
+#define CCM_PLL10_CTRL_EN  (0x1 << 31)
+
 #define CCM_PLL11_CTRL_N(n)n) - 1) & 0x3f) << 8)
 #define CCM_PLL11_CTRL_SIGMA_DELTA_EN  (0x1 << 24)
 #define CCM_PLL11_CTRL_UPD (0x1 << 30)
@@ -273,9 +297,15 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_DRC0   25
 #define AHB_GATE_OFFSET_DE_FE0 14
 #define AHB_GATE_OFFSET_DE_BE0 12
+#define AHB_GATE_OFFSET_DE 12
 #define AHB_GATE_OFFSET_HDMI   11
+#ifndef CONFIG_SUNXI_DE2
 #define AHB_GATE_OFFSET_LCD1   5
 #define AHB_GATE_OFFSET_LCD0   4
+#else
+#define AHB_GATE_OFFSET_LCD1   4
+#define AHB_GATE_OFFSET_LCD0   3
+#endif
 
 #define CCM_MMC_CTRL_M(x)  ((x) - 1)
 #define CCM_MMC_CTRL_OCLK_DLY(x)   ((x) << 8)
@@ -357,6 +387,12 @@ struct sunxi_ccm_reg {
 #define CCM_LCD_CH1_CTRL_PLL7_2X   (3 << 24)
 #define CCM_LCD_CH1_CTRL_GATE  (0x1 << 31)
 
+#define CCM_LCD0_CTRL_GATE (0x1 << 31)
+#define CCM_LCD0_CTRL_M(n) n) - 1) & 0xf) << 0)
+
+#define CCM_LCD1_CTRL_GATE (0x1 << 31)
+#define CCM_LCD1_CTRL_M(n) n) - 1) & 0xf) << 0)
+
 #define CCM_HDMI_CTRL_M(n) n) - 1) & 0xf) << 0)
 #define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
 #define CCM_HDMI_CTRL_PLL3 (0 << 24)
@@ -366,6 +402,8 @@ struct sunxi_ccm_reg {
 #define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
 #define CCM_HDMI_CTRL_GATE (0x1 

[U-Boot] [PATCH v3 2/6] sunxi: video: Convert lcdc to use struct display_timing

[Jernej Skrabec]

Video driver for older Allwinner SoCs uses cfb console framework which
in turn uses struct ctfb_res_modes to hold timing informations. However,
DM video framework uses different structure - struct display_timing.

It makes more sense to convert lcdc to use new timing structure because
all new drivers should use DM video framework and older drivers might be
rewritten to use new framework too.

Signed-off-by: Jernej Skrabec 
Acked-by: Maxime Ripard 
---
Changes in v3:
- add acked by tag

Changes in v2:
- new patch

 arch/arm/include/asm/arch-sunxi/lcdc.h |  6 ++--
 drivers/video/sunxi/lcdc.c | 64 --
 drivers/video/sunxi/sunxi_display.c| 35 +--
 3 files changed, 67 insertions(+), 38 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/lcdc.h 
b/arch/arm/include/asm/arch-sunxi/lcdc.h
index e4c8c160ed..a751698b4f 100644
--- a/arch/arm/include/asm/arch-sunxi/lcdc.h
+++ b/arch/arm/include/asm/arch-sunxi/lcdc.h
@@ -10,7 +10,7 @@
 #ifndef _LCDC_H
 #define _LCDC_H
 
-struct ctfb_res_modes;
+#include 
 
 struct sunxi_lcdc_reg {
u32 ctrl;   /* 0x00 */
@@ -118,11 +118,11 @@ struct sunxi_lcdc_reg {
 void lcdc_init(struct sunxi_lcdc_reg * const lcdc);
 void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth);
 void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
-const struct ctfb_res_modes *mode,
+const struct display_timing *mode,
 int clk_div, bool for_ext_vga_dac,
 int depth, int dclk_phase);
 void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
-const struct ctfb_res_modes *mode,
+const struct display_timing *mode,
 bool ext_hvsync, bool is_composite);
 
 #endif /* _LCDC_H */
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
index caf1859b0d..8c8fb2e4ee 100644
--- a/drivers/video/sunxi/lcdc.c
+++ b/drivers/video/sunxi/lcdc.c
@@ -13,15 +13,13 @@
 #include 
 #include 
 
-#include "../videomodes.h"
-
-static int lcdc_get_clk_delay(const struct ctfb_res_modes *mode, int tcon)
+static int lcdc_get_clk_delay(const struct display_timing *mode, int tcon)
 {
int delay;
 
-   delay = mode->lower_margin + mode->vsync_len +
-   mode->upper_margin;
-   if (mode->vmode == FB_VMODE_INTERLACED)
+   delay = mode->vfront_porch.typ + mode->vsync_len.typ +
+   mode->vback_porch.typ;
+   if (mode->flags & DISPLAY_FLAGS_INTERLACED)
delay /= 2;
if (tcon == 1)
delay -= 2;
@@ -70,7 +68,7 @@ void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int 
depth)
 }
 
 void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
-const struct ctfb_res_modes *mode,
+const struct display_timing *mode,
 int clk_div, bool for_ext_vga_dac,
 int depth, int dclk_phase)
 {
@@ -87,22 +85,22 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
   SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), >tcon0_dclk);
 
-   writel(SUNXI_LCDC_X(mode->xres) |
-  SUNXI_LCDC_Y(mode->yres), >tcon0_timing_active);
+   writel(SUNXI_LCDC_X(mode->hactive.typ) |
+  SUNXI_LCDC_Y(mode->vactive.typ), >tcon0_timing_active);
 
-   bp = mode->hsync_len + mode->left_margin;
-   total = mode->xres + mode->right_margin + bp;
+   bp = mode->hsync_len.typ + mode->hback_porch.typ;
+   total = mode->hactive.typ + mode->hfront_porch.typ + bp;
writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
   SUNXI_LCDC_TCON0_TIMING_H_BP(bp), >tcon0_timing_h);
 
-   bp = mode->vsync_len + mode->upper_margin;
-   total = mode->yres + mode->lower_margin + bp;
+   bp = mode->vsync_len.typ + mode->vback_porch.typ;
+   total = mode->vactive.typ + mode->vfront_porch.typ + bp;
writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
   SUNXI_LCDC_TCON0_TIMING_V_BP(bp), >tcon0_timing_v);
 
 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
-   writel(SUNXI_LCDC_X(mode->hsync_len) |
-  SUNXI_LCDC_Y(mode->vsync_len), >tcon0_timing_sync);
+   writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
+  SUNXI_LCDC_Y(mode->vsync_len.typ), >tcon0_timing_sync);
 
writel(0, >tcon0_hv_intf);
writel(0, >tcon0_cpu_intf);
@@ -131,9 +129,9 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
}
 
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase);
-   if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
+   if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW)
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
-   if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
+   if (mode->flags & 

[U-Boot] [PATCH v3 1/6] sunxi: video: Split out TCON code

[Jernej Skrabec]

TCON unit has similar layout and functionality also on newer SoCs. This
commit splits out TCON code for easier reuse later.

Signed-off-by: Jernej Skrabec 
Acked-by: Maxime Ripard 
---
Changes in v3:
- add acked by tag

Changes in v2:
- lcdc conversion to use struct display_timing is done in a new patch
- fix issue with lcdc_enable() calls

 arch/arm/include/asm/arch-sunxi/display.h | 103 ---
 arch/arm/include/asm/arch-sunxi/lcdc.h| 128 ++
 drivers/video/Makefile|   2 +-
 drivers/video/sunxi/Makefile  |   8 ++
 drivers/video/sunxi/lcdc.c| 207 ++
 drivers/video/{ => sunxi}/sunxi_display.c | 199 +++-
 6 files changed, 362 insertions(+), 285 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/lcdc.h
 create mode 100644 drivers/video/sunxi/Makefile
 create mode 100644 drivers/video/sunxi/lcdc.c
 rename drivers/video/{ => sunxi}/sunxi_display.c (86%)

diff --git a/arch/arm/include/asm/arch-sunxi/display.h 
b/arch/arm/include/asm/arch-sunxi/display.h
index b64f310b8b..93803addfb 100644
--- a/arch/arm/include/asm/arch-sunxi/display.h
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -157,52 +157,6 @@ struct sunxi_de_be_reg {
u32 output_color_coef[12];  /* 0x9d0 */
 };
 
-struct sunxi_lcdc_reg {
-   u32 ctrl;   /* 0x00 */
-   u32 int0;   /* 0x04 */
-   u32 int1;   /* 0x08 */
-   u8 res0[0x04];  /* 0x0c */
-   u32 tcon0_frm_ctrl; /* 0x10 */
-   u32 tcon0_frm_seed[6];  /* 0x14 */
-   u32 tcon0_frm_table[4]; /* 0x2c */
-   u8 res1[4]; /* 0x3c */
-   u32 tcon0_ctrl; /* 0x40 */
-   u32 tcon0_dclk; /* 0x44 */
-   u32 tcon0_timing_active;/* 0x48 */
-   u32 tcon0_timing_h; /* 0x4c */
-   u32 tcon0_timing_v; /* 0x50 */
-   u32 tcon0_timing_sync;  /* 0x54 */
-   u32 tcon0_hv_intf;  /* 0x58 */
-   u8 res2[0x04];  /* 0x5c */
-   u32 tcon0_cpu_intf; /* 0x60 */
-   u32 tcon0_cpu_wr_dat;   /* 0x64 */
-   u32 tcon0_cpu_rd_dat0;  /* 0x68 */
-   u32 tcon0_cpu_rd_dat1;  /* 0x6c */
-   u32 tcon0_ttl_timing0;  /* 0x70 */
-   u32 tcon0_ttl_timing1;  /* 0x74 */
-   u32 tcon0_ttl_timing2;  /* 0x78 */
-   u32 tcon0_ttl_timing3;  /* 0x7c */
-   u32 tcon0_ttl_timing4;  /* 0x80 */
-   u32 tcon0_lvds_intf;/* 0x84 */
-   u32 tcon0_io_polarity;  /* 0x88 */
-   u32 tcon0_io_tristate;  /* 0x8c */
-   u32 tcon1_ctrl; /* 0x90 */
-   u32 tcon1_timing_source;/* 0x94 */
-   u32 tcon1_timing_scale; /* 0x98 */
-   u32 tcon1_timing_out;   /* 0x9c */
-   u32 tcon1_timing_h; /* 0xa0 */
-   u32 tcon1_timing_v; /* 0xa4 */
-   u32 tcon1_timing_sync;  /* 0xa8 */
-   u8 res3[0x44];  /* 0xac */
-   u32 tcon1_io_polarity;  /* 0xf0 */
-   u32 tcon1_io_tristate;  /* 0xf4 */
-   u8 res4[0x108]; /* 0xf8 */
-   u32 mux_ctrl;   /* 0x200 */
-   u8 res5[0x1c];  /* 0x204 */
-   u32 lvds_ana0;  /* 0x220 */
-   u32 lvds_ana1;  /* 0x224 */
-};
-
 struct sunxi_hdmi_reg {
u32 version_id; /* 0x000 */
u32 ctrl;   /* 0x004 */
@@ -347,63 +301,6 @@ struct sunxi_tve_reg {
 #define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE   1
 
 /*
- * LCDC register constants.
- */
-#define SUNXI_LCDC_X(x)(((x) - 1) << 16)
-#define SUNXI_LCDC_Y(y)(((y) - 1) << 0)
-#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
-#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
-#define SUNXI_LCDC_CTRL_IO_MAP_MASK(1 << 0)
-#define SUNXI_LCDC_CTRL_IO_MAP_TCON0   (0 << 0)
-#define SUNXI_LCDC_CTRL_IO_MAP_TCON1   (1 << 0)
-#define SUNXI_LCDC_CTRL_TCON_ENABLE(1 << 31)
-#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666   ((1 << 31) | (0 << 4))
-#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565   ((1 << 31) | (5 << 4))
-#define SUNXI_LCDC_TCON0_FRM_SEED  0x
-#define SUNXI_LCDC_TCON0_FRM_TAB0  0x0101
-#define SUNXI_LCDC_TCON0_FRM_TAB1  0x1515
-#define SUNXI_LCDC_TCON0_FRM_TAB2  0x5757
-#define SUNXI_LCDC_TCON0_FRM_TAB3  0x7f7f
-#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
-#define SUNXI_LCDC_TCON0_CTRL_ENABLE   (1 << 31)
-#define SUNXI_LCDC_TCON0_DCLK_DIV(n)   ((n) 

Re: [U-Boot] [PATCH v2] spi: atmel: check GPIO validity before using cs_gpios

[Jagan Teki]

On Thu, Mar 23, 2017 at 10:19 AM, Wenyou Yang  wrote:
> Before using the cs_gpio, check if the GPIO is valid or not.
>
> Signed-off-by: Wenyou Yang 
> ---
>
> Changes in v2:
>  - Rebase on v2017.03.
>
>  drivers/spi/atmel_spi.c | 13 +
>  1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
> index 7649114231..8d29f7c4eb 100644
> --- a/drivers/spi/atmel_spi.c
> +++ b/drivers/spi/atmel_spi.c
> @@ -296,7 +296,8 @@ static void atmel_spi_cs_activate(struct udevice *dev)
> struct dm_spi_slave_platdata *slave_plat = 
> dev_get_parent_platdata(dev);
> u32 cs = slave_plat->cs;
>
> -   dm_gpio_set_value(>cs_gpios[cs], 0);
> +   if (dm_gpio_is_valid(>cs_gpios[cs]))
> +   dm_gpio_set_value(>cs_gpios[cs], 0);
>  }

Can rearrange like below, this look more reasonable.

if (!dm_gpio_is_valid(>cs_gpios[cs]))
 return;

dm_gpio_set_value(>cs_gpios[cs], 0);

thanks!
-- 
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U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH v2 1/2] spi: fsl_qspi: Add support for one chip select

[Jagan Teki]

On Tue, Feb 21, 2017 at 2:26 PM, Suresh Gupta  wrote:
> SOC’s like LS1012A has only one chip select signal
> out to connect with flash. So at one time only one
> flash is active and it is not possible to scan other
> flash at run time.
>
> Signed-off-by: Suresh Gupta 

Reviewed-by: Jagan Teki 

York, pick this from your tree.

thanks!
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Re: [U-Boot] board: ge: bx50v3: fix AR8033 reset timing issue

[Joe Hershberger]

Hi Yung-Ching,

https://patchwork.ozlabs.org/patch/730331/ was applied to u-boot-net.git.

Thanks!
-Joe
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Re: [U-Boot] drivers/net/phy: add fixed-phy / fixed-link support

[Joe Hershberger]

Hi Hannes,

https://patchwork.ozlabs.org/patch/742677/ was applied to u-boot-net.git.

Thanks!
-Joe
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Re: [U-Boot] net: link_local: Fix netmask endianness bug

[Joe Hershberger]

Hi slemieux.t...@gmail.com,

https://patchwork.ozlabs.org/patch/738893/ was applied to u-boot-net.git.

Thanks!
-Joe
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Re: [U-Boot] net: fix cache misaligned issue in Broadcom SF2 driver

[Joe Hershberger]

Hi Steve,

https://patchwork.ozlabs.org/patch/735256/ was applied to u-boot-net.git.

Thanks!
-Joe
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Re: [U-Boot] fdt_support: Fixup 'ethernet' aliases not ending in digits

[Joe Hershberger]

Hi Tuomas,

https://patchwork.ozlabs.org/patch/740833/ was applied to u-boot-net.git.

Thanks!
-Joe
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Re: [U-Boot] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

[Joe Hershberger]

Hi Yung-Ching,

https://patchwork.ozlabs.org/patch/730332/ was applied to u-boot-net.git.

Thanks!
-Joe
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Re: [U-Boot] net: sunxi: Enable eeprom on OLinuXino Lime boards

[Joe Hershberger]

Hi oli...@schinagl.nl,

https://patchwork.ozlabs.org/patch/699297/ was applied to u-boot-net.git.

Thanks!
-Joe
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Re: [U-Boot] net: sunxi-emac: Write HW address via function

[Joe Hershberger]

Hi oli...@schinagl.nl,

https://patchwork.ozlabs.org/patch/699295/ was applied to u-boot-net.git.

Thanks!
-Joe
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[U-Boot] Pull request: u-boot-net.git master

[Joe Hershberger]

Hi Tom,

The following changes since commit 5cf618ee60a752d058a767372ca1ecb8d9c09b16:

  Merge git://git.denx.de/u-boot-arc (2017-03-24 08:19:30 -0400)

are available in the git repository at:


  git://git.denx.de/u-boot-net.git master

for you to fetch changes up to db40c1aa1c100d8a9e33206575efd8b3678f31db:

  drivers/net/phy: add fixed-phy / fixed-link support (2017-03-26 09:58:26 
-0500)


Alexandre Messier (1):
  net: link_local: Fix netmask endianness bug

Hannes Schmelzer (1):
  drivers/net/phy: add fixed-phy / fixed-link support

Suji Velupillai (1):
  net: fix cache misaligned issue in Broadcom SF2 driver

Tuomas Tynkkynen (1):
  fdt_support: Fixup 'ethernet' aliases not ending in digits

Yung-Ching LIN (2):
  board: ge: bx50v3: fix AR8033 reset timing issue
  board: ge: bx50v3: apply the proper register setting to fix the voltage 
peak issue

oli...@schinagl.nl (2):
  net: sunxi-emac: Write HW address via function
  net: sunxi: Enable eeprom on OLinuXino Lime boards

 board/ge/bx50v3/bx50v3.c|   6 +-
 common/fdt_support.c|  10 ++-
 configs/A10-OLinuXino-Lime_defconfig|   4 +
 configs/A20-OLinuXino-Lime2_defconfig   |   4 +
 configs/A20-OLinuXino-Lime_defconfig|   4 +
 configs/A20-OLinuXino_MICRO_defconfig   |   4 +
 doc/device-tree-bindings/net/fixed-link.txt |  30 
 drivers/net/bcm-sf2-eth-gmac.c  | 113 +++-
 drivers/net/bcm-sf2-eth.h   |   4 +-
 drivers/net/phy/Kconfig |  10 +++
 drivers/net/phy/Makefile|   1 +
 drivers/net/phy/fixed.c |  82 
 drivers/net/phy/phy.c   |  23 +-
 drivers/net/sunxi_emac.c|  19 -
 include/phy.h   |   3 +
 net/link_local.c|   2 +-
 16 files changed, 249 insertions(+), 70 deletions(-)
 create mode 100644 doc/device-tree-bindings/net/fixed-link.txt
 create mode 100644 drivers/net/phy/fixed.c

Thanks!
-Joe
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Re: [U-Boot] [PATCH v2] ls1043ardb: SPL size reduction in case of non-xip boot

[york sun]

On 03/27/2017 09:39 AM, Sumit Garg wrote:
>> -Original Message-
>> From: york sun
>> Sent: Monday, March 27, 2017 9:41 PM
>> To: Sumit Garg ; u-boot@lists.denx.de
>> Cc: Ruchika Gupta ; Prabhakar Kushwaha
>> ; Mingkai Hu ; Vini
>> Pillai 
>> Subject: Re: [PATCH v2] ls1043ardb: SPL size reduction in case of non-xip 
>> boot
>>
>> On 03/27/2017 08:59 AM, Sumit Garg wrote:
>>> Using changes in this patch we were able to reduce approx 10k size of
>>> u-boot-spl.bin image. Following is breif description of changes to
>>> reduce SPL size:
>>> 1. Changes in board/freescale/ls1043ardb/Makefile to remove
>>>compilation of eth.c and cpld.c in case of SPL build.
>>> 2. Changes in board/freescale/ls1043ardb/ls1043ardb.c to keep
>>>only ddr_init and board_early_init_f funcations in case of SPL
>>>build.
>>> 3. Changes in ls1043a_common.h & ls1043ardb.h to remove driver
>>>specific macros due to which static data was being compiled in
>>>case of SPL build.
>>> 4. Disable MMC driver from bieng compiled in case of SPL NAND
>>>build and NAND driver from bieng compiled in case of SPL MMC build.
>>> 5. Remove I2C driver support from SPL in case of LS1043ARDB.
>>>
>>> Signed-off-by: Vinitha Pillai 
>>> Signed-off-by: Sumit Garg 
>>> ---
>>>
>>> Changes in v2:
>>> Rebased and fixed compilation warning on ls1043aqds.
>>>
>>>  board/freescale/ls1043aqds/Makefile |  2 ++
>>>  board/freescale/ls1043ardb/Makefile |  4 +++-
>>>  board/freescale/ls1043ardb/ls1043ardb.c | 18 +++---
>>>  configs/ls1043ardb_sdcard_defconfig |  1 -
>>>  include/configs/ls1043a_common.h| 10 ++
>>>  include/configs/ls1043ardb.h|  6 ++
>>>  6 files changed, 32 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/board/freescale/ls1043aqds/Makefile
>>> b/board/freescale/ls1043aqds/Makefile
>>> index f727bfd..49d8d7d 100644
>>> --- a/board/freescale/ls1043aqds/Makefile
>>> +++ b/board/freescale/ls1043aqds/Makefile
>>> @@ -5,5 +5,7 @@
>>>  #
>>>
>>>  obj-y += ddr.o
>>> +ifndef CONFIG_SPL_BUILD
>>>  obj-y += eth.o
>>> +endif
>>>  obj-y += ls1043aqds.o
>>> diff --git a/board/freescale/ls1043ardb/Makefile
>>> b/board/freescale/ls1043ardb/Makefile
>>> index 5fe1cc9..2a4452e 100644
>>> --- a/board/freescale/ls1043ardb/Makefile
>>> +++ b/board/freescale/ls1043ardb/Makefile
>>> @@ -4,7 +4,9 @@
>>>  # SPDX-License-Identifier: GPL-2.0+
>>>  #
>>>
>>> -obj-y += cpld.o
>>>  obj-y += ddr.o
>>>  obj-y += ls1043ardb.o
>>> +ifndef CONFIG_SPL_BUILD
>>>  obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
>>> +obj-y += cpld.o
>>> +endif
>>> diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
>>> b/board/freescale/ls1043ardb/ls1043ardb.c
>>> index 2333843..6de7f9a 100644
>>> --- a/board/freescale/ls1043ardb/ls1043ardb.c
>>> +++ b/board/freescale/ls1043ardb/ls1043ardb.c
>>> @@ -29,6 +29,15 @@
>>>
>>>  DECLARE_GLOBAL_DATA_PTR;
>>>
>>> +int board_early_init_f(void)
>>> +{
>>> +   fsl_lsch2_early_init_f();
>>> +
>>> +   return 0;
>>> +}
>>> +
>>> +#ifndef CONFIG_SPL_BUILD
>>> +
>>>  int checkboard(void)
>>>  {
>>> static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; @@ -67,13
>>> +76,6 @@ int checkboard(void)
>>> return 0;
>>>  }
>>>
>>> -int board_early_init_f(void)
>>> -{
>>> -   fsl_lsch2_early_init_f();
>>> -
>>> -   return 0;
>>> -}
>>> -
>>>  int board_init(void)
>>>  {
>>> struct ccsr_scfg *scfg = (struct ccsr_scfg
>>> *)CONFIG_SYS_FSL_SCFG_ADDR; @@ -215,3 +217,5 @@ u16
>> flash_read16(void
>>> *addr)
>>>
>>> return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);  }
>>> +
>>> +#endif
>>> diff --git a/configs/ls1043ardb_sdcard_defconfig
>>> b/configs/ls1043ardb_sdcard_defconfig
>>> index e57c42b..6bebbd9 100644
>>> --- a/configs/ls1043ardb_sdcard_defconfig
>>> +++ b/configs/ls1043ardb_sdcard_defconfig
>>> @@ -17,7 +17,6 @@ CONFIG_SPL=y
>>>  CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
>>>  CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
>>>  CONFIG_SPL_ENV_SUPPORT=y
>>> -CONFIG_SPL_I2C_SUPPORT=y
>>>  CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
>>>  CONFIG_HUSH_PARSER=y
>>>  CONFIG_CMD_GPT=y
>>> diff --git a/include/configs/ls1043a_common.h
>>> b/include/configs/ls1043a_common.h
>>> index 5a5f951..3dd4dd6 100644
>>> --- a/include/configs/ls1043a_common.h
>>> +++ b/include/configs/ls1043a_common.h
>>> @@ -81,6 +81,7 @@
>>>  #define CONFIG_SYS_MONITOR_LEN 0xa
>>>  #endif
>>>
>>> +#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
>>
>> Is this right? You would skip IFC if SD_BOOT is not enabled. Did you try NOR
>> boot with this change?
>>
>
> Here this check is with "!" operation, means to skip IFC if SD_BOOT & 
> SPL_BUILD are enabled.

OK. I guess missed one pair of brackets.
It is not easy to maintain if you add many #if in this header file. 
Maybe you can put #ifndef CONFIG_SPL_BUILD on the top, and select 

Re: [U-Boot] sf: Remove spansion_s25fss_disable_4KB_erase

[Jagan Teki]

Ping?

On Mon, Mar 20, 2017 at 9:42 PM, Jagan Teki  wrote:
> Hi,
>
> Let's start the discussion, if possible we may add linux-mtd ML.
>
> Here is the details: from attached pdf Page no:2
>
> In spansion S25FS-S family the physical sectors are grouped as
> normal and parameter sectors. Parameter sectors are 4kB in size
> with 8 set located at the bottom or top address of a device.
> Normal sectors are similar to other flash family with sizes of
> 64kB or 32 kB.
>
> Do we agree till this point?
>
> To erase whole flash using sector erase(D8h or DCh) won't effect
> the parameter sectors, so in order to erase these we must use 4K
> sector erase commands (20h or 21h) separately.
>
> So better to erase the whole flash using 4K sector erase instead
> of detecting these family parts again and do two different erase
> operations.
>
> On Tue, Dec 13, 2016 at 10:57 AM, Yao Yuan  wrote:
>> Hi Jagan,
>>
>> Do you have any comments?
>>
>> Thanks for your work and you know it's important for QSPI with S25FS512S.
>>
>> It seems S25FS512S can't support the SECT_4K, right?
>> And it better to retain the disable_4kb, but we can add a flag in dts to 
>> select whether enable it.
>>
>> Best Regards,
>> Yao
>>
>> From: Yao Yuan
>> Sent: Wednesday, November 30, 2016 3:23 PM
>> To: 'Jagan Teki' 
>> Subject: sf: Remove spansion_s25fss_disable_4KB_erase
>>
>> Hi Jagan,
>>
>> I have noticed that you have a patch to:
>>
>> commit 116e005cfd00021424f5f81eeedd355e4ca72f07
>> Author: Jagan Teki 
>> >
>> Date:   Tue Nov 15 22:57:42 2016 +0530
>>
>> - Removed spansion_s25fss_disable_4KB_erase code
>> - Add SECT_4K for S25FS512S chip
>>
>> Do you have any test for this patch?
>> Because with this patch, my QSPI driver can't working with S25FS512S.
>>
>> As you said,
>> In spansion S25FS-S family the physical sectors are grouped as normal and 
>> parameter sectors.
>> Parameter sectors are 4kB in size with 8 set located at the bottom or top 
>> address of a device.
>> Normal sectors are similar to other flash family with sizes of 64kB or 32 kB.
>>
>> Base on the RM and in my understand, not all the erase sectors are 4-kb.
>>
>> In my case regions are:
>>
>> 1. 0-32KiB (8*4KiB) - 4K_ERASE (0x20/0x21)
>>
>> 2. 32 - 256 - SE_CMD (0xd8/0xdc)
>>
>> 3. Rest of the flash SE_CMD (0xd8/0xdc)
>>
>> 4. To erase whole flash you can also use CHIP_ERASE_CMD
>>
>> (0x60/0xC7) command, you just need to add one more mtd
>>
>> partition that will cover whole flash.
>>
>> So we can't add SECT_4K for S25FS512S chip.
>> If we add SECT_4K for S25FS512S chip, that means all the erase sectors are 
>> 4-kb.
>> But I think it's not right.
>>
>> And disable 4kb is necessary for me, I also suggestion to add a flag to 
>> select whether enable 4-kb.
>>
>> if (of_property_read_bool(np, "spi-nor, disable-4kb")) {
>>
>> spansion_s25fs_disable_4kb_erase();
>>
>> }
>>
>> else
>>
>> ...
>>
>>
>>
>> In dts:
>>
>>  {
>>
>> qflash0: s25fs512s@0 {
>>
>> compatible = "spansion, s25fs512s";
>>
>> spi-nor, disable-4kb
>>
>> #address-cells = <1>;
>>
>> #size-cells = <1>;
>>
>> spi-max-frequency = <2000>;
>>
>> reg = <0>;
>>
>> };
>>
>>
>> Attachment is the RM for S25FS-S.
>
> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com
> U-Boot, Linux | Upstream Maintainer
> Hyderabad, India.



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Re: [U-Boot] [PATCH v2] ls1043ardb: SPL size reduction in case of non-xip boot

[Sumit Garg]

> -Original Message-
> From: york sun
> Sent: Monday, March 27, 2017 9:41 PM
> To: Sumit Garg ; u-boot@lists.denx.de
> Cc: Ruchika Gupta ; Prabhakar Kushwaha
> ; Mingkai Hu ; Vini
> Pillai 
> Subject: Re: [PATCH v2] ls1043ardb: SPL size reduction in case of non-xip boot
> 
> On 03/27/2017 08:59 AM, Sumit Garg wrote:
> > Using changes in this patch we were able to reduce approx 10k size of
> > u-boot-spl.bin image. Following is breif description of changes to
> > reduce SPL size:
> > 1. Changes in board/freescale/ls1043ardb/Makefile to remove
> >compilation of eth.c and cpld.c in case of SPL build.
> > 2. Changes in board/freescale/ls1043ardb/ls1043ardb.c to keep
> >only ddr_init and board_early_init_f funcations in case of SPL
> >build.
> > 3. Changes in ls1043a_common.h & ls1043ardb.h to remove driver
> >specific macros due to which static data was being compiled in
> >case of SPL build.
> > 4. Disable MMC driver from bieng compiled in case of SPL NAND
> >build and NAND driver from bieng compiled in case of SPL MMC build.
> > 5. Remove I2C driver support from SPL in case of LS1043ARDB.
> >
> > Signed-off-by: Vinitha Pillai 
> > Signed-off-by: Sumit Garg 
> > ---
> >
> > Changes in v2:
> > Rebased and fixed compilation warning on ls1043aqds.
> >
> >  board/freescale/ls1043aqds/Makefile |  2 ++
> >  board/freescale/ls1043ardb/Makefile |  4 +++-
> >  board/freescale/ls1043ardb/ls1043ardb.c | 18 +++---
> >  configs/ls1043ardb_sdcard_defconfig |  1 -
> >  include/configs/ls1043a_common.h| 10 ++
> >  include/configs/ls1043ardb.h|  6 ++
> >  6 files changed, 32 insertions(+), 9 deletions(-)
> >
> > diff --git a/board/freescale/ls1043aqds/Makefile
> > b/board/freescale/ls1043aqds/Makefile
> > index f727bfd..49d8d7d 100644
> > --- a/board/freescale/ls1043aqds/Makefile
> > +++ b/board/freescale/ls1043aqds/Makefile
> > @@ -5,5 +5,7 @@
> >  #
> >
> >  obj-y += ddr.o
> > +ifndef CONFIG_SPL_BUILD
> >  obj-y += eth.o
> > +endif
> >  obj-y += ls1043aqds.o
> > diff --git a/board/freescale/ls1043ardb/Makefile
> > b/board/freescale/ls1043ardb/Makefile
> > index 5fe1cc9..2a4452e 100644
> > --- a/board/freescale/ls1043ardb/Makefile
> > +++ b/board/freescale/ls1043ardb/Makefile
> > @@ -4,7 +4,9 @@
> >  # SPDX-License-Identifier: GPL-2.0+
> >  #
> >
> > -obj-y += cpld.o
> >  obj-y += ddr.o
> >  obj-y += ls1043ardb.o
> > +ifndef CONFIG_SPL_BUILD
> >  obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
> > +obj-y += cpld.o
> > +endif
> > diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
> > b/board/freescale/ls1043ardb/ls1043ardb.c
> > index 2333843..6de7f9a 100644
> > --- a/board/freescale/ls1043ardb/ls1043ardb.c
> > +++ b/board/freescale/ls1043ardb/ls1043ardb.c
> > @@ -29,6 +29,15 @@
> >
> >  DECLARE_GLOBAL_DATA_PTR;
> >
> > +int board_early_init_f(void)
> > +{
> > +   fsl_lsch2_early_init_f();
> > +
> > +   return 0;
> > +}
> > +
> > +#ifndef CONFIG_SPL_BUILD
> > +
> >  int checkboard(void)
> >  {
> > static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; @@ -67,13
> > +76,6 @@ int checkboard(void)
> > return 0;
> >  }
> >
> > -int board_early_init_f(void)
> > -{
> > -   fsl_lsch2_early_init_f();
> > -
> > -   return 0;
> > -}
> > -
> >  int board_init(void)
> >  {
> > struct ccsr_scfg *scfg = (struct ccsr_scfg
> > *)CONFIG_SYS_FSL_SCFG_ADDR; @@ -215,3 +217,5 @@ u16
> flash_read16(void
> > *addr)
> >
> > return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);  }
> > +
> > +#endif
> > diff --git a/configs/ls1043ardb_sdcard_defconfig
> > b/configs/ls1043ardb_sdcard_defconfig
> > index e57c42b..6bebbd9 100644
> > --- a/configs/ls1043ardb_sdcard_defconfig
> > +++ b/configs/ls1043ardb_sdcard_defconfig
> > @@ -17,7 +17,6 @@ CONFIG_SPL=y
> >  CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> >  CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
> >  CONFIG_SPL_ENV_SUPPORT=y
> > -CONFIG_SPL_I2C_SUPPORT=y
> >  CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
> >  CONFIG_HUSH_PARSER=y
> >  CONFIG_CMD_GPT=y
> > diff --git a/include/configs/ls1043a_common.h
> > b/include/configs/ls1043a_common.h
> > index 5a5f951..3dd4dd6 100644
> > --- a/include/configs/ls1043a_common.h
> > +++ b/include/configs/ls1043a_common.h
> > @@ -81,6 +81,7 @@
> >  #define CONFIG_SYS_MONITOR_LEN 0xa
> >  #endif
> >
> > +#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
> 
> Is this right? You would skip IFC if SD_BOOT is not enabled. Did you try NOR
> boot with this change?
>
 
Here this check is with "!" operation, means to skip IFC if SD_BOOT & SPL_BUILD 
are enabled.
 
> >  /* IFC */
> >  #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
> > #define CONFIG_FSL_IFC @@ -102,6 +103,7 @@
> >  #define CONFIG_FLASH_SHOW_PROGRESS 45  /* count down from
> 45/5: 9..1 */
> >  #endif
> >  #endif

Re: [U-Boot] [PATCH v2] ls1043ardb: SPL size reduction in case of non-xip boot

[york sun]

On 03/27/2017 08:59 AM, Sumit Garg wrote:
> Using changes in this patch we were able to reduce approx 10k
> size of u-boot-spl.bin image. Following is breif description of
> changes to reduce SPL size:
> 1. Changes in board/freescale/ls1043ardb/Makefile to remove
>compilation of eth.c and cpld.c in case of SPL build.
> 2. Changes in board/freescale/ls1043ardb/ls1043ardb.c to keep
>only ddr_init and board_early_init_f funcations in case of SPL
>build.
> 3. Changes in ls1043a_common.h & ls1043ardb.h to remove driver
>specific macros due to which static data was being compiled in
>case of SPL build.
> 4. Disable MMC driver from bieng compiled in case of SPL NAND
>build and NAND driver from bieng compiled in case of SPL MMC build.
> 5. Remove I2C driver support from SPL in case of LS1043ARDB.
>
> Signed-off-by: Vinitha Pillai 
> Signed-off-by: Sumit Garg 
> ---
>
> Changes in v2:
> Rebased and fixed compilation warning on ls1043aqds.
>
>  board/freescale/ls1043aqds/Makefile |  2 ++
>  board/freescale/ls1043ardb/Makefile |  4 +++-
>  board/freescale/ls1043ardb/ls1043ardb.c | 18 +++---
>  configs/ls1043ardb_sdcard_defconfig |  1 -
>  include/configs/ls1043a_common.h| 10 ++
>  include/configs/ls1043ardb.h|  6 ++
>  6 files changed, 32 insertions(+), 9 deletions(-)
>
> diff --git a/board/freescale/ls1043aqds/Makefile 
> b/board/freescale/ls1043aqds/Makefile
> index f727bfd..49d8d7d 100644
> --- a/board/freescale/ls1043aqds/Makefile
> +++ b/board/freescale/ls1043aqds/Makefile
> @@ -5,5 +5,7 @@
>  #
>
>  obj-y += ddr.o
> +ifndef CONFIG_SPL_BUILD
>  obj-y += eth.o
> +endif
>  obj-y += ls1043aqds.o
> diff --git a/board/freescale/ls1043ardb/Makefile 
> b/board/freescale/ls1043ardb/Makefile
> index 5fe1cc9..2a4452e 100644
> --- a/board/freescale/ls1043ardb/Makefile
> +++ b/board/freescale/ls1043ardb/Makefile
> @@ -4,7 +4,9 @@
>  # SPDX-License-Identifier:   GPL-2.0+
>  #
>
> -obj-y += cpld.o
>  obj-y += ddr.o
>  obj-y += ls1043ardb.o
> +ifndef CONFIG_SPL_BUILD
>  obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
> +obj-y += cpld.o
> +endif
> diff --git a/board/freescale/ls1043ardb/ls1043ardb.c 
> b/board/freescale/ls1043ardb/ls1043ardb.c
> index 2333843..6de7f9a 100644
> --- a/board/freescale/ls1043ardb/ls1043ardb.c
> +++ b/board/freescale/ls1043ardb/ls1043ardb.c
> @@ -29,6 +29,15 @@
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> +int board_early_init_f(void)
> +{
> + fsl_lsch2_early_init_f();
> +
> + return 0;
> +}
> +
> +#ifndef CONFIG_SPL_BUILD
> +
>  int checkboard(void)
>  {
>   static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
> @@ -67,13 +76,6 @@ int checkboard(void)
>   return 0;
>  }
>
> -int board_early_init_f(void)
> -{
> - fsl_lsch2_early_init_f();
> -
> - return 0;
> -}
> -
>  int board_init(void)
>  {
>   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
> @@ -215,3 +217,5 @@ u16 flash_read16(void *addr)
>
>   return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
>  }
> +
> +#endif
> diff --git a/configs/ls1043ardb_sdcard_defconfig 
> b/configs/ls1043ardb_sdcard_defconfig
> index e57c42b..6bebbd9 100644
> --- a/configs/ls1043ardb_sdcard_defconfig
> +++ b/configs/ls1043ardb_sdcard_defconfig
> @@ -17,7 +17,6 @@ CONFIG_SPL=y
>  CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
>  CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
>  CONFIG_SPL_ENV_SUPPORT=y
> -CONFIG_SPL_I2C_SUPPORT=y
>  CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
>  CONFIG_HUSH_PARSER=y
>  CONFIG_CMD_GPT=y
> diff --git a/include/configs/ls1043a_common.h 
> b/include/configs/ls1043a_common.h
> index 5a5f951..3dd4dd6 100644
> --- a/include/configs/ls1043a_common.h
> +++ b/include/configs/ls1043a_common.h
> @@ -81,6 +81,7 @@
>  #define CONFIG_SYS_MONITOR_LEN   0xa
>  #endif
>
> +#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))

Is this right? You would skip IFC if SD_BOOT is not enabled. Did you try 
NOR boot with this change?

>  /* IFC */
>  #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
>  #define CONFIG_FSL_IFC
> @@ -102,6 +103,7 @@
>  #define CONFIG_FLASH_SHOW_PROGRESS   45  /* count down from 45/5: 9..1 */
>  #endif
>  #endif
> +#endif
>
>  /* I2C */
>  #define CONFIG_SYS_I2C
> @@ -111,6 +113,7 @@
>  #define CONFIG_SYS_I2C_MXC_I2C3
>  #define CONFIG_SYS_I2C_MXC_I2C4
>
> +#ifndef CONFIG_SPL_BUILD
>  /* PCIe */
>  #define CONFIG_PCIE1 /* PCIE controller 1 */
>  #define CONFIG_PCIE2 /* PCIE controller 2 */
> @@ -124,13 +127,17 @@
>
>  /* Command line configuration */
>  #define CONFIG_CMD_ENV
> +#endif
>
> +#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))

So MMC is only available for NAND_BOOT?

>  /*  MMC  */
>  #ifdef CONFIG_MMC
>  #define CONFIG_FSL_ESDHC
>  #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
>  #endif
> +#endif
>

York
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[U-Boot] [PATCH v2] ls1046ardb: SPL size reduction in case of non-xip boot

[Sumit Garg]

Using changes in this patch we were able to reduce approx 4k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1046ardb/Makefile to remove
   compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1046ardb/ls1046ardb.c to keep
   only ddr_init and board_early_init_f funcations in case of SPL
   build.
3. Changes in ls1046a_common.h & ls1046ardb.h to remove driver
   specific macros due to which static data was being compiled in
   case of SPL build.
4. Disable MMC driver from bieng compiled in case of SPL NAND
   build and NAND driver from bieng compiled in case of SPL MMC build.

Signed-off-by: Vinitha Pillai 
Signed-off-by: Sumit Garg 
---

Changes in v2:
Rebased and fixed compilation warning on ls1046aqds.

 board/freescale/ls1046aqds/Makefile |  2 ++
 board/freescale/ls1046ardb/Makefile |  4 +++-
 board/freescale/ls1046ardb/ls1046ardb.c | 16 +---
 include/configs/ls1046a_common.h| 10 ++
 include/configs/ls1046ardb.h|  7 ++-
 5 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/board/freescale/ls1046aqds/Makefile 
b/board/freescale/ls1046aqds/Makefile
index df6e546..6267522 100644
--- a/board/freescale/ls1046aqds/Makefile
+++ b/board/freescale/ls1046aqds/Makefile
@@ -5,5 +5,7 @@
 #
 
 obj-y += ddr.o
+ifndef CONFIG_SPL_BUILD
 obj-y += eth.o
+endif
 obj-y += ls1046aqds.o
diff --git a/board/freescale/ls1046ardb/Makefile 
b/board/freescale/ls1046ardb/Makefile
index 348eb76..b92ed0b 100644
--- a/board/freescale/ls1046ardb/Makefile
+++ b/board/freescale/ls1046ardb/Makefile
@@ -4,7 +4,9 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y += cpld.o
 obj-y += ddr.o
 obj-y += ls1046ardb.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+obj-y += cpld.o
+endif
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c 
b/board/freescale/ls1046ardb/ls1046ardb.c
index 02b6c4c..0cc508b 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -24,6 +24,14 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int board_early_init_f(void)
+{
+   fsl_lsch2_early_init_f();
+
+   return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
 int checkboard(void)
 {
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
@@ -56,13 +64,6 @@ int checkboard(void)
return 0;
 }
 
-int board_early_init_f(void)
-{
-   fsl_lsch2_early_init_f();
-
-   return 0;
-}
-
 int board_init(void)
 {
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
@@ -161,3 +162,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
return 0;
 }
+#endif
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 1ed7517..614ab6f 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -108,21 +108,27 @@
 #define CONFIG_SYS_I2C_MXC_I2C3
 #define CONFIG_SYS_I2C_MXC_I2C4
 
+#ifndef CONFIG_SPL_BUILD
 /* Command line configuration */
 #define CONFIG_CMD_ENV
+#endif
 
+#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
 /* MMC */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
+#endif
 
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_SYS_DPAA_QBMAN  /* Support Q/Bman */
 
 /* FMan ucode */
 #define CONFIG_SYS_DPAA_FMAN
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_FM_MURAM_SIZE   0x6
+#endif
 
 #ifdef CONFIG_SD_BOOT
 /*
@@ -156,6 +162,7 @@
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE   128
 
+#ifndef CONFIG_SPL_BUILD
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
"hwconfig=fsl_ddr:bank_intlv=auto\0"\
@@ -173,13 +180,16 @@
 #define CONFIG_BOOTARGS"console=ttyS0,115200 
root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500 " \
MTDPARTS_DEFAULT
+#endif
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE  512 /* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE /* Boot args buffer */
 #define CONFIG_SYS_LONGHELP
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_CMDLINE_EDITING 1
+#endif
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS 64  /* max command args */
 
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 2141b82..67f7273 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -51,13 +51,14 @@
 #endif
 #endif
 
+#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
 /* IFC */
 #define CONFIG_FSL_IFC
-
 /*
  * NAND Flash Definitions
  */
 #define CONFIG_NAND_FSL_IFC
+#endif
 
 #define CONFIG_SYS_NAND_BASE  

[U-Boot] [PATCH v2] ls1043ardb: SPL size reduction in case of non-xip boot

[Sumit Garg]

Using changes in this patch we were able to reduce approx 10k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1043ardb/Makefile to remove
   compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1043ardb/ls1043ardb.c to keep
   only ddr_init and board_early_init_f funcations in case of SPL
   build.
3. Changes in ls1043a_common.h & ls1043ardb.h to remove driver
   specific macros due to which static data was being compiled in
   case of SPL build.
4. Disable MMC driver from bieng compiled in case of SPL NAND
   build and NAND driver from bieng compiled in case of SPL MMC build.
5. Remove I2C driver support from SPL in case of LS1043ARDB.

Signed-off-by: Vinitha Pillai 
Signed-off-by: Sumit Garg 
---

Changes in v2:
Rebased and fixed compilation warning on ls1043aqds.

 board/freescale/ls1043aqds/Makefile |  2 ++
 board/freescale/ls1043ardb/Makefile |  4 +++-
 board/freescale/ls1043ardb/ls1043ardb.c | 18 +++---
 configs/ls1043ardb_sdcard_defconfig |  1 -
 include/configs/ls1043a_common.h| 10 ++
 include/configs/ls1043ardb.h|  6 ++
 6 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/board/freescale/ls1043aqds/Makefile 
b/board/freescale/ls1043aqds/Makefile
index f727bfd..49d8d7d 100644
--- a/board/freescale/ls1043aqds/Makefile
+++ b/board/freescale/ls1043aqds/Makefile
@@ -5,5 +5,7 @@
 #
 
 obj-y += ddr.o
+ifndef CONFIG_SPL_BUILD
 obj-y += eth.o
+endif
 obj-y += ls1043aqds.o
diff --git a/board/freescale/ls1043ardb/Makefile 
b/board/freescale/ls1043ardb/Makefile
index 5fe1cc9..2a4452e 100644
--- a/board/freescale/ls1043ardb/Makefile
+++ b/board/freescale/ls1043ardb/Makefile
@@ -4,7 +4,9 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y += cpld.o
 obj-y += ddr.o
 obj-y += ls1043ardb.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+obj-y += cpld.o
+endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c 
b/board/freescale/ls1043ardb/ls1043ardb.c
index 2333843..6de7f9a 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -29,6 +29,15 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int board_early_init_f(void)
+{
+   fsl_lsch2_early_init_f();
+
+   return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+
 int checkboard(void)
 {
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
@@ -67,13 +76,6 @@ int checkboard(void)
return 0;
 }
 
-int board_early_init_f(void)
-{
-   fsl_lsch2_early_init_f();
-
-   return 0;
-}
-
 int board_init(void)
 {
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
@@ -215,3 +217,5 @@ u16 flash_read16(void *addr)
 
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 }
+
+#endif
diff --git a/configs/ls1043ardb_sdcard_defconfig 
b/configs/ls1043ardb_sdcard_defconfig
index e57c42b..6bebbd9 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
 CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPT=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 5a5f951..3dd4dd6 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -81,6 +81,7 @@
 #define CONFIG_SYS_MONITOR_LEN 0xa
 #endif
 
+#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
 /* IFC */
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_FSL_IFC
@@ -102,6 +103,7 @@
 #define CONFIG_FLASH_SHOW_PROGRESS 45  /* count down from 45/5: 9..1 */
 #endif
 #endif
+#endif
 
 /* I2C */
 #define CONFIG_SYS_I2C
@@ -111,6 +113,7 @@
 #define CONFIG_SYS_I2C_MXC_I2C3
 #define CONFIG_SYS_I2C_MXC_I2C4
 
+#ifndef CONFIG_SPL_BUILD
 /* PCIe */
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 #define CONFIG_PCIE2   /* PCIE controller 2 */
@@ -124,13 +127,17 @@
 
 /* Command line configuration */
 #define CONFIG_CMD_ENV
+#endif
 
+#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
 /*  MMC  */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
+#endif
 
+#ifndef CONFIG_SPL_BUILD
 /*  DSPI  */
 #define CONFIG_FSL_DSPI
 #ifdef CONFIG_FSL_DSPI
@@ -176,6 +183,7 @@
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH   0x1
 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif
+#endif
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_DDR_SDRAM_BASE + 0x1000)
@@ -183,6 +191,7 @@
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE   128
 
+#ifndef CONFIG_SPL_BUILD
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 

Re: [U-Boot] [PATCH] armv8/fsl-layerscape: fdt: On ls1012 don't check sysclk for USB

[york sun]

On 03/16/2017 12:32 AM, Yingxi Yu wrote:
> USB requires 100MHz clock. On ls1012, sysclk(125MHz) is not for USB.
> Another 100MHz clock is for USB. So For USB, check if sysclk is 100MHz
> is failed on ls1012, sysclk is not for USB. Don't check sysclk for
> USB on ls1012.

Does this only apply to LS1012A? Or does this apply a group of SoCs?

York

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Re: [U-Boot] [PATCHv3 1/5] mtd: nand: add initialization flag

[york sun]

On 03/17/2017 01:27 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang 
>
> Add initialization flag to avoid initializing NAND Flash multiple
> times, otherwise it will calculate a wrong total size.
>
> Signed-off-by: Hou Zhiqiang 
> ---
> V3:
>  - no change
>
>  drivers/mtd/nand/nand.c | 10 ++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
> index 0551241..3ea2dcf 100644
> --- a/drivers/mtd/nand/nand.c
> +++ b/drivers/mtd/nand/nand.c
> @@ -133,6 +133,16 @@ static void create_mtd_concat(void)
>
>  void nand_init(void)
>  {
> + static int initialized;
> +
> + /*
> +  * Avoid initializing NAND Flash multiple times,
> +  * otherwise it will calculate a wrong total size.
> +  */
> + if (initialized)
> + return;
> + initialized = 1;
> +
>  #ifdef CONFIG_SYS_NAND_SELF_INIT
>   board_nand_init();
>  #else
>

Scott,

Are you OK with this one and #2 in this set? If so, I am going to bring 
them in.

York
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Re: [U-Boot] [PATCH 2/3] string: Provide a slimmed-down memset()

[Heiko Stuebner]

Am Montag, 27. März 2017, 09:14:47 CEST schrieb Alexander Graf:
> 
> On 27/03/2017 01:38, Simon Glass wrote:
> > Most of the time the optimised memset() is what we want. For extreme
> > situations such as TPL it may be too large. For example on the 'rock'
> > board, using a simple loop saves a useful 48 bytes. With gcc 4.9 and
> > the rodata bug, this patch is enough to reduce the TPL image below the
> > limit.
> >
> > Signed-off-by: Simon Glass 
> > ---
> >
> >  lib/Kconfig  | 9 +
> >  lib/string.c | 6 --
> >  2 files changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/lib/Kconfig b/lib/Kconfig
> > index 65c01573e1..5bf512d8c0 100644
> > --- a/lib/Kconfig
> > +++ b/lib/Kconfig
> > @@ -52,6 +52,15 @@ config LIB_RAND
> > help
> >   This library provides pseudo-random number generator functions.
> >
> > +config FAST_MEMSET
> > +   bool "Use an optimised memset()"
> > +   default y
> > +   help
> > + The faster memset() is the arch-specific one (if available) enabled
> > + by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get
> > + better performance by write a word at a time. Disable this option
> > + to reduce code size slightly at the cost of some speed.
> 
> The comment sounds slightly confused - it took me a few times of reading 
> it until I grasped what it was trying to tell me :).
> 
> > +
> >  source lib/dhry/Kconfig
> >
> >  source lib/rsa/Kconfig
> > diff --git a/lib/string.c b/lib/string.c
> > index 67d5f6a421..159493ed17 100644
> > --- a/lib/string.c
> > +++ b/lib/string.c
> > @@ -437,8 +437,10 @@ char *strswab(const char *s)
> >  void * memset(void * s,int c,size_t count)
> >  {
> > unsigned long *sl = (unsigned long *) s;
> > -   unsigned long cl = 0;
> > char *s8;
> > +
> > +#ifdef CONFIG_FAST_MEMSET
> > +   unsigned long cl = 0;
> > int i;
> >
> > /* do it one word at a time (32 bits or 64 bits) while possible */
> > @@ -452,7 +454,7 @@ void * memset(void * s,int c,size_t count)
> > count -= sizeof(*sl);
> > }
> > }
> > -   /* fill 8 bits at a time */
> > +#endif /* fill 8 bits at a time */
> 
> So while this is all neat, a few ideas:
> 
> 1) Would having memset in a header improve things even more? After all, 
> each external function call clobbers registers that you need to 
> save/restore...

I'd guess it really depends on the size constraints. The regular
libgeneric memset compiles on my rk3188 tpl to a total of
64bytes on both gcc-4.9 and gcc-6.3 while Simon's fast-memset
comes down to 14bytes on my rk3188.

On the rk3188 the only memset user is board_init_f, so here memset
is called only once without needing to save registers and I'd guess if an
implementation really is that size-constrained to worry about 50bytes
this one caller will probably always be the only one?


> 2) How much would GOLD save you? Have you tried? U-Boot is small enough 
> of a code base that global optimizations should be able to give 
> significant size savings.

I think the issue that this is trying to solve is to allow more
toolchains to be used and thus make rebuilds on changes work on a lot
of boards at the same time with random toolchains.

gcc-6.3 already produces way smaller results (well within the size
constraints the rk3188 has) than for example the gcc-4.9 used by
buildman as baseline toolchain.


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[U-Boot] [PATCH v2 4/7] i2c: lpc32xx: Add DM for lpc32xx I2C

[Sylvain Lemieux]

From: Liam Beguin 

Adding DM specific wrapper functions and definitions.

Signed-off-by: Liam Beguin 
Signed-off-by: Sylvain Lemieux 
---
Changes from v1 to v2:
* Fixed checkpatch issue.

 drivers/i2c/lpc32xx_i2c.c | 91 +++
 1 file changed, 91 insertions(+)

diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index 62d2d7eee5..17e8b744e5 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -15,6 +15,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /*
  * Provide default speed and slave if target did not
@@ -47,6 +49,14 @@ struct lpc32xx_i2c_base {
u32 stxfl;
 };
 
+#ifdef CONFIG_DM_I2C
+struct lpc32xx_i2c_dev {
+   struct lpc32xx_i2c_base *base;
+   int index;
+   uint speed;
+};
+#endif /* CONFIG_DM_I2C */
+
 /* TX register fields */
 #define LPC32XX_I2C_TX_START   0x0100
 #define LPC32XX_I2C_TX_STOP0x0200
@@ -61,11 +71,13 @@ struct lpc32xx_i2c_base {
 #define LPC32XX_I2C_STAT_NAI   0x0004
 #define LPC32XX_I2C_STAT_TDI   0x0001
 
+#ifndef CONFIG_DM_I2C
 static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
(struct lpc32xx_i2c_base *)I2C1_BASE,
(struct lpc32xx_i2c_base *)I2C2_BASE,
(struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
 };
+#endif
 
 /* Set I2C bus speed */
 static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
@@ -241,6 +253,7 @@ static int __i2c_write(struct lpc32xx_i2c_base *base, u8 
dev, uint addr,
return 0;
 }
 
+#ifndef CONFIG_DM_I2C
 static void lpc32xx_i2c_init(struct i2c_adapter *adap,
 int requested_speed, int slaveadd)
 {
@@ -294,3 +307,80 @@ U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
 10,
 0,
 2)
+#else /* CONFIG_DM_I2C */
+static int lpc32xx_i2c_probe(struct udevice *bus)
+{
+   struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+
+   __i2c_init(dev->base, dev->speed, 0, dev->index);
+   return 0;
+}
+
+static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+ u32 chip_flags)
+{
+   struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+   return __i2c_probe_chip(dev->base, chip_addr);
+}
+
+static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+   int nmsgs)
+{
+   struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+   struct i2c_msg *dmsg, *omsg, dummy;
+   uint i = 0, address = 0;
+
+   memset(, 0, sizeof(struct i2c_msg));
+
+   /* We expect either two messages (one with an offset and one with the
+* actual data) or one message (just data)
+*/
+   if (nmsgs > 2 || nmsgs == 0) {
+   debug("%s: Only one or two messages are supported.", __func__);
+   return -1;
+   }
+
+   omsg = nmsgs == 1 ?  : msg;
+   dmsg = nmsgs == 1 ? msg : msg + 1;
+
+   /* the address is expected to be a uint, not a array. */
+   address = omsg->buf[0];
+   for (i = 1; i < omsg->len; i++)
+   address = (address << 8) + omsg->buf[i];
+
+   if (dmsg->flags & I2C_M_RD)
+   return __i2c_read(dev->base, dmsg->addr, address,
+ omsg->len, dmsg->buf, dmsg->len);
+   else
+   return __i2c_write(dev->base, dmsg->addr, address,
+  omsg->len, dmsg->buf, dmsg->len);
+}
+
+static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+   struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+   return __i2c_set_bus_speed(dev->base, speed, dev->index);
+}
+
+static int lpc32xx_i2c_reset(struct udevice *bus)
+{
+   struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
+
+   __i2c_init(dev->base, dev->speed, 0, dev->index);
+   return 0;
+}
+
+static const struct dm_i2c_ops lpc32xx_i2c_ops = {
+   .xfer  = lpc32xx_i2c_xfer,
+   .probe_chip= lpc32xx_i2c_probe_chip,
+   .deblock   = lpc32xx_i2c_reset,
+   .set_bus_speed = lpc32xx_i2c_set_bus_speed,
+};
+
+U_BOOT_DRIVER(i2c_lpc32xx) = {
+   .id   = UCLASS_I2C,
+   .name = "i2c_lpc32xx",
+   .probe= lpc32xx_i2c_probe,
+   .ops  = _i2c_ops,
+};
+#endif /* CONFIG_DM_I2C */
-- 
2.11.0

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[U-Boot] [PATCH v2 3/7] i2c: lpc32xx: Factor out i2c_adapter parameter

[Sylvain Lemieux]

From: Liam Beguin 

This is part of the prep work for the migration to the driver model.
It will enable the driver to support DM and non-DM configurations
using the same functions.

Signed-off-by: Liam Beguin 
Signed-off-by: Sylvain Lemieux 
---
Changes from v1 to v2:
* Fixed checkpatch issue.

 drivers/i2c/lpc32xx_i2c.c | 107 +++---
 1 file changed, 53 insertions(+), 54 deletions(-)

diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index e5dfdfe1df..62d2d7eee5 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -29,7 +29,7 @@
 #endif
 
 /* i2c register set */
-struct lpc32xx_i2c_registers {
+struct lpc32xx_i2c_base {
union {
u32 rx;
u32 tx;
@@ -61,15 +61,15 @@ struct lpc32xx_i2c_registers {
 #define LPC32XX_I2C_STAT_NAI   0x0004
 #define LPC32XX_I2C_STAT_TDI   0x0001
 
-static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {
-   (struct lpc32xx_i2c_registers *)I2C1_BASE,
-   (struct lpc32xx_i2c_registers *)I2C2_BASE,
-   (struct lpc32xx_i2c_registers *)(USB_BASE + 0x300)
+static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
+   (struct lpc32xx_i2c_base *)I2C1_BASE,
+   (struct lpc32xx_i2c_base *)I2C2_BASE,
+   (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
 };
 
 /* Set I2C bus speed */
-static unsigned int __i2c_set_bus_speed(struct i2c_adapter *adap,
-   unsigned int speed)
+static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
+   unsigned int speed, unsigned int chip)
 {
int half_period;
 
@@ -77,7 +77,7 @@ static unsigned int __i2c_set_bus_speed(struct i2c_adapter 
*adap,
return -EINVAL;
 
/* OTG I2C clock source and CLK registers are different */
-   if (adap->hwadapnr == 2) {
+   if (chip == 2) {
half_period = (get_periph_clk_rate() / speed) / 2;
if (half_period > 0xFF)
return -EINVAL;
@@ -87,38 +87,35 @@ static unsigned int __i2c_set_bus_speed(struct i2c_adapter 
*adap,
return -EINVAL;
}
 
-   writel(half_period, _i2c[adap->hwadapnr]->clk_hi);
-   writel(half_period, _i2c[adap->hwadapnr]->clk_lo);
+   writel(half_period, >clk_hi);
+   writel(half_period, >clk_lo);
return 0;
 }
 
 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
-static void __i2c_init(struct i2c_adapter *adap,
-   int requested_speed, int slaveadd)
+static void __i2c_init(struct lpc32xx_i2c_base *base,
+  int requested_speed, int slaveadd, unsigned int chip)
 {
-   struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
-
/* soft reset (auto-clears) */
-   writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
+   writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
/* set HI and LO periods for half of the default speed */
-   __i2c_set_bus_speed(adap, requested_speed);
+   __i2c_set_bus_speed(base, requested_speed, chip);
 }
 
 /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
-static int __i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
+static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
 {
-   struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
int stat;
 
/* Soft-reset the controller */
-   writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
-   while (readl(>ctrl) & LPC32XX_I2C_SOFT_RESET)
+   writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
+   while (readl(>ctrl) & LPC32XX_I2C_SOFT_RESET)
;
/* Addre slave for write with start before and stop after */
writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
-  >tx);
+  >tx);
/* wait for end of transation */
-   while (!((stat = readl(>stat)) & LPC32XX_I2C_STAT_TDI))
+   while (!((stat = readl(>stat)) & LPC32XX_I2C_STAT_TDI))
;
/* was there no acknowledge? */
return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
@@ -128,20 +125,19 @@ static int __i2c_probe_chip(struct i2c_adapter *adap, u8 
dev)
  * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
  * Begin write, send address byte(s), begin read, receive data bytes, end.
  */
-static int __i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
-int alen, u8 *data, int length)
+static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
+ int alen, u8 *data, int length)
 {
-   struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
int stat, wlen;
 
/* Soft-reset the controller */
-   writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
-   while (readl(>ctrl) & LPC32XX_I2C_SOFT_RESET)
+   writel(LPC32XX_I2C_SOFT_RESET, >ctrl);
+   while (readl(>ctrl) & LPC32XX_I2C_SOFT_RESET)
 

[U-Boot] [PATCH] MCCMON6: defconfig: Add tftp_nor_dtb command for NOR DTB update

[Lukasz Majewski]

Signed-off-by: Lukasz Majewski 
---
 include/configs/mccmon6.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 8c72455..46ca32e 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -270,6 +270,14 @@
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
"run nor_update;" \
"fi\0" \
+   "tftp_nor_dtb="\
+   "echo 'Update mccmon6 NOR DTB via TFTP'; " \
+   "setenv nor_img_file imx6q-mccmon6.dtb; " \
+   "setenv nor_img_size 0x2; " \
+   "setenv nor_bank_start 0x0998; " \
+   "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+   "run nor_update;" \
+   "fi\0" \
"tftp_nor_img="\
"echo 'Update mccmon6 NOR image via TFTP'; " \
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
-- 
2.1.4

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Re: [U-Boot] [PATCH v2] Add support for Microchip LAN78xx

[Marek Vasut]

On 03/27/2017 01:59 PM, yuiko.osh...@microchip.com wrote:
> From: Yuiko Oshino 
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: Friday, March 24, 2017 2:29 PM
>> To: Yuiko Oshino - C18177; u-boot@lists.denx.de
>> Subject: Re: [PATCH v2] Add support for Microchip LAN78xx
>>
>> On 03/24/2017 07:25 PM, yuiko.osh...@microchip.com wrote:
>>> From: Yuiko Oshino 
 -Original Message-
 From: Marek Vasut [mailto:ma...@denx.de]
 Sent: Friday, March 10, 2017 2:19 PM
 To: Yuiko Oshino - C18177; u-boot@lists.denx.de
 Subject: Re: [PATCH v2] Add support for Microchip LAN78xx

 On 03/10/2017 07:38 PM, yuiko.osh...@microchip.com wrote:
> From: Yuiko Oshino 
>
> Add support for Microchip LAN7800 and 7850, USB to 10/100/1000
> Ethernet Controllers
>
> Signed-off-by: Yuiko Oshino 
> Cc: Marek Vasut 
> ---
> Changes for v2:
>- lan78xx.c header comment cleanup
>
>>>
>>> [...]
>>>

 Why does a lot of this stuff look like the SMSC95xx driver ?
 Do we even need a separate driver or can the SMSC95xx driver be
 updated to support the LAN78xx ?

>>>
>>> Marek,
>>> Thank you so much for your review.
>>> The LAN78xx's register addresses and bit definitions are not compatible to
>> our old part LAN95xx (==SMSC95xx).
>>> The new devices LAN78xx and LAN75xx device have similarities. I plan to
>> support these two devices in this driver.
>>> I will take care of all your comments and will submit a new PATCH with a 
>>> file
>> name change to lan7x.c.
>>>
>>
>> Is the rename really mandatory ?
>>
> Yes, if we are going to make one file that supports both LAN78xx and LAN75xx, 
> it's very important for us to make the driver file name to support both 
> devices.

The filename has nothing to do with which chips are supported though ?

>> Then again, I looked into Linux and that one has two separate drivers .
>> So I wonder if it's really a good idea. Maybe we can share some common code
>> and have the rest separate ?
> 
> Marek,
> 1. we can submit LAN78xx and LA75xx drivers separately like in Linux. We do 
> prefer this option.
> 2. we can submit one LAN7x.c that supports both LAN78xx and LAN75xx in one 
> file.
> Could you pick one?

Can we have option 3 -- pull common code into some file and make both
drivers use the common code ?

> Thank you.
> Yuiko
> 
>>
>> --
>> Best regards,
>> Marek Vasut


-- 
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Re: [U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram

[Ruchika Gupta]

> -Original Message-
> From: york sun
> Sent: Saturday, March 25, 2017 10:16 PM
> To: Ruchika Gupta ; u-boot@lists.denx.de;
> prabhakar.khushw...@nxp.com
> Subject: Re: [U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead
> of L1 as init_ram
> 
> On 03/01/2017 07:37 PM, Ruchika Gupta wrote:
> > Fir E6500 cores, L2 cache has been used as init_ram. L1 cache is a
> > write through cache on E6500.If lines are not locked in both L1 and L2
> > caches, crashes are observed during secure boot. This patch
> > locks/unlocks both L1 as well as L2 cache to prevent the crash.
> 
> I didn't even know you could/should lock L1. Any reason why it would crash?
> 
> York
In secure boot scenarios, L2 cache is also locked by Rom for usage and then 
cleared before exiting ROM. Some castouts were being observed when only L2 
cache lines were being locked in uboot hinting that lines were probably not 
getting locked. The e6500 core expert suggested to try locking in both the 
caches. This seems to resolve the crashed which we were observing. 

Ruchika

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Re: [U-Boot] [GIT] Pull request: u-boot-dfu

[Marek Vasut]

On 03/27/2017 01:23 PM, Lukasz Majewski wrote:
> Dear Marek,
> 
> Please find pull request for dfu repository:
> 
> The following changes since commit
> 8fb397da91eefe472f25c0a3c7d910fb8f9be129:
> 
>   drivers/usb/ehci: Use platform-specific accessors (2017-03-24
>   13:55:45 +0100)
> 
> are available in the git repository at:
> 
>   ssh://gu-...@git.denx.de/u-boot-dfu/master 

Applied, thanks


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Re: [U-Boot] [PATCH v2 00/45] Add PPv2.2 support to the mvpp2 ethernet driver and enable it for A7k/8k

[Stefan Roese]

Hi Joe,

On 25.03.2017 22:42, Joe Hershberger wrote:

On Thu, Mar 23, 2017 at 12:01 PM, Stefan Roese  wrote:


This patchset does the following things:

- It brings the latest Linux changes from the mvpp2 ethernet driver done
  by Thomas Petazzoni to the U-Boot version of this driver. This enables
  the usage of this driver on the new Marvell Armada 7k / 8k ARMv8 SoCs.

- This driver is enabled for the currently available Armada 7k / 8k
  boards and the necessary configuration is done to the config header.

v2 status:
The GoP / NetC patch has been split into multiple smaller patches for
easier review. The code for untested / unsupported interfaces (like
QSGMII, XAUI and RXAUI) has been removed for now.

Thanks,
Stefan


I think you should be good to go to pull this into your board tree.


Thanks Joe. I've just sent a v3 for the 2 GoP / NetC patches, with
the mv_reset enum removed. If this is okay, I'll pull the
complete patchset later this week via the mvebu tree.

Thanks,
Stefan
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[U-Boot] [PATCH v3 39/45] net: mvpp2: Add GoP and NetC support for port 0 (SFI)

[Stefan Roese]

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver for the missing port 0. This code is
mostly copied from the Marvell U-Boot version and was written by Stefan
Chulski. Please note that only SFI support have been added, as this
is the only interface that this code has been tested with. XAUI and
RXAUI support might follow at a later stage.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Cc: Joe Hershberger 
---
Changes in v3:
- Removed usage of mv_reset enum and used "int" type instead
- Changed "bool" enable / reset parameters to "int" type

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 161 
 1 file changed, 161 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index e9637ca13d..10904b9dc5 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -3232,6 +3232,130 @@ static int gop_gpcs_reset(struct mvpp2_port *port, int 
reset)
return 0;
 }
 
+/* Set the internal mux's to the required PCS in the PI */
+static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
+{
+   u32 val;
+   int lane;
+
+   switch (num_of_lanes) {
+   case 1:
+   lane = 0;
+   break;
+   case 2:
+   lane = 1;
+   break;
+   case 4:
+   lane = 2;
+   break;
+   default:
+   return -1;
+   }
+
+   /* configure XG MAC mode */
+   val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+   val &= ~MVPP22_XPCS_PCSMODE_OFFS;
+   val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
+   val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
+   writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+   return 0;
+}
+
+static int gop_mpcs_mode(struct mvpp2_port *port)
+{
+   u32 val;
+
+   /* configure PCS40G COMMON CONTROL */
+   val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+   val &= ~FORWARD_ERROR_CORRECTION_MASK;
+   writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+
+   /* configure PCS CLOCK RESET */
+   val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
+   val &= ~CLK_DIVISION_RATIO_MASK;
+   val |= 1 << CLK_DIVISION_RATIO_OFFS;
+   writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+   val &= ~CLK_DIV_PHASE_SET_MASK;
+   val |= MAC_CLK_RESET_MASK;
+   val |= RX_SD_CLK_RESET_MASK;
+   val |= TX_SD_CLK_RESET_MASK;
+   writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+
+   return 0;
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
+{
+   u32 val;
+
+   /* configure 10G MAC mode */
+   val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+   val |= MVPP22_XLG_RX_FC_EN;
+   writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+   val = readl(port->base + MVPP22_XLG_CTRL3_REG);
+   val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
+   val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
+   writel(val, port->base + MVPP22_XLG_CTRL3_REG);
+
+   /* read - modify - write */
+   val = readl(port->base + MVPP22_XLG_CTRL4_REG);
+   val &= ~MVPP22_XLG_MODE_DMA_1G;
+   val |= MVPP22_XLG_FORWARD_PFC_EN;
+   val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
+   val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
+   writel(val, port->base + MVPP22_XLG_CTRL4_REG);
+
+   /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
+   val = readl(port->base + MVPP22_XLG_CTRL1_REG);
+   val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
+   val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
+   writel(val, port->base + MVPP22_XLG_CTRL1_REG);
+
+   /* unmask link change interrupt */
+   val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+   val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
+   val |= 1; /* unmask summary bit */
+   writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
+
+   return 0;
+}
+
+/* Set PCS to reset or exit from reset */
+static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
+{
+   u32 val;
+
+   /* read - modify - write */
+   val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+   if (reset)
+   val &= ~MVPP22_XPCS_PCSRESET;
+   else
+   val |= MVPP22_XPCS_PCSRESET;
+   writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+   return 0;
+}
+
+/* Set the MAC to reset or exit from reset */
+static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
+{
+   u32 val;
+
+   /* read - modify - write */
+   val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+   if (reset)
+   val &= ~MVPP22_XLG_MAC_RESETN;
+   else
+   val 

[U-Boot] [PATCH v3 38/45] net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)

[Stefan Roese]

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver. This code is mostly copied from the
Marvell U-Boot version and was written by Stefan Chulski. Please
note that only RGMII and SGMII support have been added, as these are
the only interfaces that this code has been tested with.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Cc: Joe Hershberger 
---
Changes in v3:
- Removed usage of mv_reset enum and used "int" type instead
- Changed "bool" enable / reset parameters to "int" type

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 764 +++-
 1 file changed, 756 insertions(+), 8 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 6f9a4137f8..e9637ca13d 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -355,6 +355,7 @@ do {
\
 /* Per-port registers */
 #define MVPP2_GMAC_CTRL_0_REG  0x0
 #define  MVPP2_GMAC_PORT_EN_MASK   BIT(0)
+#define  MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
 #define  MVPP2_GMAC_MAX_RX_SIZE_OFFS   2
 #define  MVPP2_GMAC_MAX_RX_SIZE_MASK   0x7ffc
 #define  MVPP2_GMAC_MIB_CNTR_EN_MASK   BIT(15)
@@ -366,29 +367,131 @@ do { 
\
 #define  MVPP2_GMAC_SA_LOW_OFFS7
 #define MVPP2_GMAC_CTRL_2_REG  0x8
 #define  MVPP2_GMAC_INBAND_AN_MASK BIT(0)
+#define  MVPP2_GMAC_SGMII_MODE_MASKBIT(0)
 #define  MVPP2_GMAC_PCS_ENABLE_MASKBIT(3)
 #define  MVPP2_GMAC_PORT_RGMII_MASKBIT(4)
+#define  MVPP2_GMAC_PORT_DIS_PADING_MASK   BIT(5)
 #define  MVPP2_GMAC_PORT_RESET_MASKBIT(6)
+#define  MVPP2_GMAC_CLK_125_BYPS_EN_MASK   BIT(9)
 #define MVPP2_GMAC_AUTONEG_CONFIG  0xc
 #define  MVPP2_GMAC_FORCE_LINK_DOWNBIT(0)
 #define  MVPP2_GMAC_FORCE_LINK_PASSBIT(1)
+#define  MVPP2_GMAC_EN_PCS_AN  BIT(2)
+#define  MVPP2_GMAC_AN_BYPASS_EN   BIT(3)
 #define  MVPP2_GMAC_CONFIG_MII_SPEED   BIT(5)
 #define  MVPP2_GMAC_CONFIG_GMII_SPEED  BIT(6)
 #define  MVPP2_GMAC_AN_SPEED_ENBIT(7)
 #define  MVPP2_GMAC_FC_ADV_EN  BIT(9)
+#define  MVPP2_GMAC_EN_FC_AN   BIT(11)
 #define  MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
 #define  MVPP2_GMAC_AN_DUPLEX_EN   BIT(13)
+#define  MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIGBIT(15)
 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS6
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK0x1fc0
 #define  MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
+#define MVPP2_GMAC_CTRL_4_REG  0x90
+#define  MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASKBIT(0)
+#define  MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK  BIT(5)
+#define  MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
+#define  MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASKBIT(7)
 
-#define MVPP22_SMI_MISC_CFG_REG0x1204
+/*
+ * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
+ * relative to port->base.
+ */
+
+/* Port Mac Control0 */
+#define MVPP22_XLG_CTRL0_REG   0x100
+#define  MVPP22_XLG_PORT_ENBIT(0)
+#define  MVPP22_XLG_MAC_RESETN BIT(1)
+#define  MVPP22_XLG_RX_FC_EN   BIT(7)
+#define  MVPP22_XLG_MIBCNT_DIS BIT(13)
+/* Port Mac Control1 */
+#define MVPP22_XLG_CTRL1_REG   0x104
+#define  MVPP22_XLG_MAX_RX_SIZE_OFFS   0
+#define  MVPP22_XLG_MAX_RX_SIZE_MASK   0x1fff
+/* Port Interrupt Mask */
+#define MVPP22_XLG_INTERRUPT_MASK_REG  0x118
+#define  MVPP22_XLG_INTERRUPT_LINK_CHANGE  BIT(1)
+/* Port Mac Control3 */
+#define MVPP22_XLG_CTRL3_REG   0x11c
+#define  MVPP22_XLG_CTRL3_MACMODESELECT_MASK   (7 << 13)
+#define  MVPP22_XLG_CTRL3_MACMODESELECT_GMAC   (0 << 13)
+#define  MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
+/* Port Mac Control4 */
+#define MVPP22_XLG_CTRL4_REG   0x184
+#define  MVPP22_XLG_FORWARD_802_3X_FC_EN   BIT(5)
+#define  MVPP22_XLG_FORWARD_PFC_EN BIT(6)
+#define  MVPP22_XLG_MODE_DMA_1GBIT(12)
+#define  MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
+
+/* XPCS registers */
+
+/* Global Configuration 0 */
+#define MVPP22_XPCS_GLOBAL_CFG_0_REG   0x0
+#define  MVPP22_XPCS_PCSRESET  BIT(0)
+#define  MVPP22_XPCS_PCSMODE_OFFS  3
+#define  

Re: [U-Boot] [PATCH v2] Add support for Microchip LAN78xx

[Yuiko.Oshino]

From: Yuiko Oshino 
>-Original Message-
>From: Marek Vasut [mailto:ma...@denx.de]
>Sent: Friday, March 24, 2017 2:29 PM
>To: Yuiko Oshino - C18177; u-boot@lists.denx.de
>Subject: Re: [PATCH v2] Add support for Microchip LAN78xx
>
>On 03/24/2017 07:25 PM, yuiko.osh...@microchip.com wrote:
>> From: Yuiko Oshino 
>>> -Original Message-
>>> From: Marek Vasut [mailto:ma...@denx.de]
>>> Sent: Friday, March 10, 2017 2:19 PM
>>> To: Yuiko Oshino - C18177; u-boot@lists.denx.de
>>> Subject: Re: [PATCH v2] Add support for Microchip LAN78xx
>>>
>>> On 03/10/2017 07:38 PM, yuiko.osh...@microchip.com wrote:
 From: Yuiko Oshino 

 Add support for Microchip LAN7800 and 7850, USB to 10/100/1000
 Ethernet Controllers

 Signed-off-by: Yuiko Oshino 
 Cc: Marek Vasut 
 ---
 Changes for v2:
- lan78xx.c header comment cleanup

>>
>> [...]
>>
>>>
>>> Why does a lot of this stuff look like the SMSC95xx driver ?
>>> Do we even need a separate driver or can the SMSC95xx driver be
>>> updated to support the LAN78xx ?
>>>
>>
>> Marek,
>> Thank you so much for your review.
>> The LAN78xx's register addresses and bit definitions are not compatible to
>our old part LAN95xx (==SMSC95xx).
>> The new devices LAN78xx and LAN75xx device have similarities. I plan to
>support these two devices in this driver.
>> I will take care of all your comments and will submit a new PATCH with a file
>name change to lan7x.c.
>>
>
>Is the rename really mandatory ?
>
Yes, if we are going to make one file that supports both LAN78xx and LAN75xx, 
it's very important for us to make the driver file name to support both devices.

>Then again, I looked into Linux and that one has two separate drivers .
>So I wonder if it's really a good idea. Maybe we can share some common code
>and have the rest separate ?

Marek,
1. we can submit LAN78xx and LA75xx drivers separately like in Linux. We do 
prefer this option.
2. we can submit one LAN7x.c that supports both LAN78xx and LAN75xx in one file.
Could you pick one?
Thank you.
Yuiko

>
>--
>Best regards,
>Marek Vasut
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[U-Boot] [GIT] Pull request: u-boot-dfu

[Lukasz Majewski]

Dear Marek,

Please find pull request for dfu repository:

The following changes since commit
8fb397da91eefe472f25c0a3c7d910fb8f9be129:

  drivers/usb/ehci: Use platform-specific accessors (2017-03-24
  13:55:45 +0100)

are available in the git repository at:

  ssh://gu-...@git.denx.de/u-boot-dfu/master 

for you to fetch changes up to f51a176d749ca38c3e8ca5fc8dada26bb2dd8877:

  usb: gadget: g_dnl: don't set iProduct nor iSerialNumber (2017-03-27
  13:09:51 +0200)


Felipe Balbi (3):
  usb: gadget: g_dnl: hold maximum string descriptor
  usb: gadget: g_dnl: only set iSerialNumber if we have a serial#
  usb: gadget: g_dnl: don't set iProduct nor iSerialNumber

 drivers/usb/gadget/g_dnl.c | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH v2 38/45] net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII)

[Stefan Roese]

Hi Joe,

On 25.03.2017 21:05, Joe Hershberger wrote:

On Thu, Mar 23, 2017 at 12:02 PM, Stefan Roese  wrote:

This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver. This code is mostly copied from the
Marvell U-Boot version and was written by Stefan Chulski. Please
note that only RGMII and SGMII support have been added, as these are
the only interfaces that this code has been tested with.

Signed-off-by: Stefan Roese 
Cc: Stefan Chulski 
Cc: Kostya Porotchkin 
Cc: Nadav Haklai 
Cc: Joe Hershberger 

---

Changes in v2:
- New patch

 drivers/net/mvpp2.c | 766 +++-
 1 file changed, 758 insertions(+), 8 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 6f9a4137f8..76370faff0 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c





@@ -2833,6 +2986,570 @@ static inline void mvpp2_gmac_max_rx_size_set(struct 
mvpp2_port *port)
writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
 }

+/* PPv2.2 GoP/GMAC config */
+
+/* Set the MAC to reset or exit from reset */
+static int gop_gmac_reset(struct mvpp2_port *port, enum mv_reset reset)


Is this copied from somewhere? The enum parameter seems unnecessary.
Why not just int for type?


Yes, its copied from the original Marvell sources. And yes, I also
am not fond of this additional enum (just forgot to get rid of it
actually). I'll change it int instead.


+{
+   u32 val;
+
+   /* read - modify - write */
+   val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+   if (reset == RESET)
+   val |= MVPP2_GMAC_PORT_RESET_MASK;
+   else
+   val &= ~MVPP2_GMAC_PORT_RESET_MASK;
+   writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+   return 0;
+}
+
+/*
+ * gop_gpcs_mode_cfg
+ *
+ * Configure port to working with Gig PCS or don't.
+ */
+static int gop_gpcs_mode_cfg(struct mvpp2_port *port, bool en)


Similar here. Copied? Do we really use "bool" in U-Boot much? I care
less about this one that the enum above, though.


Also copied, yes. "bool" is probably not used that much in U-Boot,
even though somewhat in this Linux driver. I'll move to int though
with these parameters.

Thanks,
Stefan
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Re: [U-Boot] unused-const-variable warnings in FSL DDR driver

[Thomas Schaefer]

> From: york sun [mailto:york@nxp.com] 
> Sent: Samstag, 25. März 2017 16:35
> To: Thomas Schaefer; Tom Rini
> Cc: u-boot@lists.denx.de
> Re: Re: AW: [U-Boot] unused-const-variable warnings in FSL DDR driver
>
> Thomas,
>
> Can you put your patch together with proper commit message and signature? I 
> prefer your solution than this one http://patchwork.ozlabs.org/patch/726353/
>
> York
>

Hi York,

please find the patch in the attachment.

Best regards,
Thomas


commit 66dcf316bf2649e576f1b79aad3a5bb950d178d6
Author: Thomas Schaefer 
Date:   Mon Mar 27 10:17:09 2017 +0200

drivers: ddr: fix unused-const-variable warnings

Depending on DDR configuration, gcc-6.x will show up unused-const-
variable messages. Use __maybe_unused specifier for all dynamic_odt
variable definitions to remove these warnings.

Memory footprint will not increase as gcc will optimize out unused
constants.

Signed-off-by: Thomas Schaefer 

diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index d6a8fcb216..64aaa77047 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -33,7 +33,7 @@ struct dynamic_odt {
 /* Quad rank is not verified yet due availability.
  * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
  */
-static const struct dynamic_odt single_Q[4] = {
+__maybe_unused static const struct dynamic_odt single_Q[4] = {
{   /* cs0 */
FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_CS_AND_OTHER_DIMM,
@@ -60,7 +60,7 @@ static const struct dynamic_odt single_Q[4] = {
}
 };

-static const struct dynamic_odt single_D[4] = {
+__maybe_unused static const struct dynamic_odt single_D[4] = {
{   /* cs0 */
FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_ALL,
@@ -77,7 +77,7 @@ static const struct dynamic_odt single_D[4] = {
{0, 0, 0, 0}
 };

-static const struct dynamic_odt single_S[4] = {
+__maybe_unused static const struct dynamic_odt single_S[4] = {
{   /* cs0 */
FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_ALL,
@@ -89,7 +89,7 @@ static const struct dynamic_odt single_S[4] = {
{0, 0, 0, 0},
 };

-static const struct dynamic_odt dual_DD[4] = {
+__maybe_unused static const struct dynamic_odt dual_DD[4] = {
{   /* cs0 */
FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_SAME_DIMM,
@@ -116,7 +116,7 @@ static const struct dynamic_odt dual_DD[4] = {
}
 };

-static const struct dynamic_odt dual_DS[4] = {
+__maybe_unused static const struct dynamic_odt dual_DS[4] = {
{   /* cs0 */
FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_SAME_DIMM,
@@ -137,7 +137,7 @@ static const struct dynamic_odt dual_DS[4] = {
},
{0, 0, 0, 0}
 };
-static const struct dynamic_odt dual_SD[4] = {
+__maybe_unused static const struct dynamic_odt dual_SD[4] = {
{   /* cs0 */
FSL_DDR_ODT_OTHER_DIMM,
FSL_DDR_ODT_ALL,
@@ -159,7 +159,7 @@ static const struct dynamic_odt dual_SD[4] = {
}
 };

-static const struct dynamic_odt dual_SS[4] = {
+__maybe_unused static const struct dynamic_odt dual_SS[4] = {
{   /* cs0 */
FSL_DDR_ODT_OTHER_DIMM,
FSL_DDR_ODT_ALL,
@@ -176,7 +176,7 @@ static const struct dynamic_odt dual_SS[4] = {
{0, 0, 0, 0}
 };

-static const struct dynamic_odt dual_D0[4] = {
+__maybe_unused static const struct dynamic_odt dual_D0[4] = {
{   /* cs0 */
FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_SAME_DIMM,
@@ -193,7 +193,7 @@ static const struct dynamic_odt dual_D0[4] = {
{0, 0, 0, 0}
 };

-static const struct dynamic_odt dual_0D[4] = {
+__maybe_unused static const struct dynamic_odt dual_0D[4] = {
{0, 0, 0, 0},
{0, 0, 0, 0},
{   /* cs2 */
@@ -210,7 +210,7 @@ static const struct dynamic_odt dual_0D[4] = {
}
 };

-static const struct dynamic_odt dual_S0[4] = {
+__maybe_unused static const struct dynamic_odt dual_S0[4] = {
{   /* cs0 */
FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_CS,
@@ -223,7 +223,7 @@ static const struct dynamic_odt dual_S0[4] = {

 };

-static const struct dynamic_odt dual_0S[4] = {
+__maybe_unused static const struct dynamic_odt dual_0S[4] = {
{0, 0, 0, 0},
{0, 0, 0, 0},
{   /* cs2 */
@@ -236,7 +236,7 @@ static const struct dynamic_odt dual_0S[4] = {

 };

-static const struct dynamic_odt odt_unknown[4] = {
+__maybe_unused static const struct dynamic_odt odt_unknown[4] = {
{   /* cs0 */
FSL_DDR_ODT_NEVER,
FSL_DDR_ODT_CS,
@@ -263,7 +263,7 @@ static const struct dynamic_odt odt_unknown[4] = {
}
 };
 #elif defined(CONFIG_SYS_FSL_DDR3)
-static const struct dynamic_odt single_Q[4] = {
+__maybe_unused static const struct dynamic_odt single_Q[4] = {
   

[U-Boot] [PATCH 4/4 v4] dm: test: Add test for device removal

[Stefan Roese]

Add a test for the correct device removal. Currently two different ways
for device removal are supported:

- Normal device removal via the device_remove() API
- Removal via selective device driver flags (DM_FLAG_ACTIVE_DMA)

This new test "remove_active_dma" adds tests cases for those both ways
of removal. This is done by adding a new test driver, which has this
flag set.

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
---
v4:
- Added explicit test that a device without the active DMA flags is not
  removed upon the active DMA remove call. For this, a new test driver
  is added (test_act_dma_drv).

v2:
- New patch in patchset

 test/dm/core.c| 66 +++
 test/dm/test-driver.c | 11 +
 2 files changed, 77 insertions(+)

diff --git a/test/dm/core.c b/test/dm/core.c
index 07b2419ea4..50ee41b9e2 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -67,6 +67,10 @@ static struct driver_info driver_info_pre_reloc = {
.platdata = _pdata_pre_reloc,
 };
 
+static struct driver_info driver_info_act_dma = {
+   .name = "test_act_dma_drv",
+};
+
 void dm_leak_check_start(struct unit_test_state *uts)
 {
uts->start = mallinfo();
@@ -656,6 +660,68 @@ static int dm_test_pre_reloc(struct unit_test_state *uts)
 }
 DM_TEST(dm_test_pre_reloc, 0);
 
+/*
+ * Test that removal of devices, either via the "normal" device_remove()
+ * API or via the device driver selective flag works as expected
+ */
+static int dm_test_remove_active_dma(struct unit_test_state *uts)
+{
+   struct dm_test_state *dms = uts->priv;
+   struct udevice *dev;
+
+   ut_assertok(device_bind_by_name(dms->root, false, _info_act_dma,
+   ));
+   ut_assert(dev);
+
+   /* Probe the device */
+   ut_assertok(device_probe(dev));
+
+   /* Test if device is active right now */
+   ut_asserteq(true, device_active(dev));
+
+   /* Remove the device via selective remove flag */
+   dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+
+   /* Test if device is inactive right now */
+   ut_asserteq(false, device_active(dev));
+
+   /* Probe the device again */
+   ut_assertok(device_probe(dev));
+
+   /* Test if device is active right now */
+   ut_asserteq(true, device_active(dev));
+
+   /* Remove the device via "normal" remove API */
+   ut_assertok(device_remove(dev, DM_REMOVE_NORMAL));
+
+   /* Test if device is inactive right now */
+   ut_asserteq(false, device_active(dev));
+
+   /*
+* Test if a device without the active DMA flags is not removed upon
+* the active DMA remove call
+*/
+   ut_assertok(device_unbind(dev));
+   ut_assertok(device_bind_by_name(dms->root, false, _info_manual,
+   ));
+   ut_assert(dev);
+
+   /* Probe the device */
+   ut_assertok(device_probe(dev));
+
+   /* Test if device is active right now */
+   ut_asserteq(true, device_active(dev));
+
+   /* Remove the device via selective remove flag */
+   dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+
+   /* Test if device is still active right now */
+   ut_asserteq(true, device_active(dev));
+
+   return 0;
+}
+DM_TEST(dm_test_remove_active_dma, 0);
+
 static int dm_test_uclass_before_ready(struct unit_test_state *uts)
 {
struct uclass *uc;
diff --git a/test/dm/test-driver.c b/test/dm/test-driver.c
index d10af51147..2b432a71fd 100644
--- a/test/dm/test-driver.c
+++ b/test/dm/test-driver.c
@@ -157,3 +157,14 @@ U_BOOT_DRIVER(test_pre_reloc_drv) = {
.unbind = test_manual_unbind,
.flags  = DM_FLAG_PRE_RELOC,
 };
+
+U_BOOT_DRIVER(test_act_dma_drv) = {
+   .name   = "test_act_dma_drv",
+   .id = UCLASS_TEST,
+   .ops= _manual_ops,
+   .bind   = test_manual_bind,
+   .probe  = test_manual_probe,
+   .remove = test_manual_remove,
+   .unbind = test_manual_unbind,
+   .flags  = DM_FLAG_ACTIVE_DMA,
+};
-- 
2.12.2

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[U-Boot] [PATCH 2/4 v4] dm: core: Add dm_remove_devices_flags() and hook it into device_remove()

[Stefan Roese]

The new function dm_remove_devices_flags() is intented for driver specific
last-stage cleanup operations before the OS is started. This patch adds
this functionality and hooks it into the common device_remove()
function.

Drivers wanting to use this feature for some last-stage removal calls,
need to add one of the DM_REMOVE_xx flags to their driver .flags.

Signed-off-by: Stefan Roese 
Reviewed-by: Simon Glass 
---
v4:
- Make comparison of flags more explicit by masking the driver flags
  with the drivers "remove flags" before masking them with the
  device_remove() removal flags parameter

v3:
- Add conditional compilation to fix compilation breakage on platforms
  without DM and DM_DEVICE_REMOVE support. With this change, Travis
  compiles all targets without any error

v2:
- Added Simons Reviewed-by

drivers/core/device-remove.c | 17 +
 drivers/core/root.c  |  9 +
 include/dm/root.h| 16 
 3 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index b80bf52320..cc0043b990 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -174,7 +174,13 @@ int device_remove(struct udevice *dev, uint flags)
if (ret)
goto err;
 
-   if (drv->remove) {
+   /*
+* Remove the device if called with the "normal" remove flag set,
+* or if the remove flag matches any of the drivers remove flags
+*/
+   if (drv->remove &&
+   ((flags & DM_REMOVE_NORMAL) ||
+(flags & (drv->flags & DM_FLAG_ACTIVE_DMA {
ret = drv->remove(dev);
if (ret)
goto err_remove;
@@ -188,10 +194,13 @@ int device_remove(struct udevice *dev, uint flags)
}
}
 
-   device_free(dev);
+   if ((flags & DM_REMOVE_NORMAL) ||
+   (flags & (drv->flags & DM_FLAG_ACTIVE_DMA))) {
+   device_free(dev);
 
-   dev->seq = -1;
-   dev->flags &= ~DM_FLAG_ACTIVATED;
+   dev->seq = -1;
+   dev->flags &= ~DM_FLAG_ACTIVATED;
+   }
 
return ret;
 
diff --git a/drivers/core/root.c b/drivers/core/root.c
index d8c51fb496..42679d047c 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -184,6 +184,15 @@ int dm_uninit(void)
return 0;
 }
 
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+int dm_remove_devices_flags(uint flags)
+{
+   device_remove(dm_root(), flags);
+
+   return 0;
+}
+#endif
+
 int dm_scan_platdata(bool pre_reloc_only)
 {
int ret;
diff --git a/include/dm/root.h b/include/dm/root.h
index 3cf730dcee..058eb98923 100644
--- a/include/dm/root.h
+++ b/include/dm/root.h
@@ -115,4 +115,20 @@ int dm_init(void);
  */
 int dm_uninit(void);
 
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+/**
+ * dm_remove_devices_flags - Call remove function of all drivers with
+ *   specific removal flags set to selectively
+ *   remove drivers
+ *
+ * All devices with the matching flags set will be removed
+ *
+ * @flags: Flags for selective device removal
+ * @return 0 if OK, -ve on error
+ */
+int dm_remove_devices_flags(uint flags);
+#else
+static inline int dm_remove_devices_flags(uint flags) { return 0; }
+#endif
+
 #endif
-- 
2.12.2

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[U-Boot] [PATCH v2] net: designware: Add phy supply support

[Jacob Chen]

Some board need a regulator for gmac phy, so add this code to handle it.
Signed-off-by: Jacob Chen 
---

 drivers/net/designware.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index f9fb8e0..0fcd125 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "designware.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -661,6 +662,22 @@ int designware_eth_probe(struct udevice *dev)
ulong ioaddr;
int ret;
 
+#if defined(CONFIG_DM_REGULATOR)
+   struct udevice *phy_supply;
+
+   ret = device_get_supply_regulator(dev, "phy-supply",
+ _supply);
+   if (ret) {
+   debug("%s: No phy supply\n", dev->name);
+   } else {
+   ret = regulator_set_enable(phy_supply, true);
+   if (ret) {
+   puts("Error enabling phy supply\n");
+   return ret;
+   }
+   }
+#endif
+
 #ifdef CONFIG_DM_PCI
/*
 * If we are on PCI bus, either directly attached to a PCI root port,
-- 
1.9.1

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Re: [U-Boot] fatls returncode

[Wolfgang Denk]

Dear Mirza,

In message 

Re: [U-Boot] [PATCH v2 4/7] sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

[Maxime Ripard]

On Fri, Mar 24, 2017 at 05:02:16PM +0100, Jernej Škrabec wrote:
> Dne petek, 24. marec 2017 ob 16:53:07 CET je Maxime Ripard napisal(a):
> > On Wed, Mar 22, 2017 at 06:19:12PM +0100, Jernej Škrabec wrote:
> > > Hi,
> > > 
> > > Dne sreda, 22. marec 2017 ob 08:45:48 CET je Maxime Ripard napisal(a):
> > > > On Tue, Mar 21, 2017 at 11:26:46PM +0100, Jernej Škrabec wrote:
> > > > > Hi,
> > > > > 
> > > > > Dne torek, 21. marec 2017 ob 20:34:33 CET je Maxime Ripard napisal(a):
> > > > > > Hi,
> > > > > > 
> > > > > > On Mon, Mar 20, 2017 at 11:01:25PM +0100, Jernej Skrabec wrote:
> > > > > > > diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h
> > > > > > > index 1b7bfb6c22..146f7f4e1b 100644
> > > > > > > --- a/include/configs/sun50i.h
> > > > > > > +++ b/include/configs/sun50i.h
> > > > > > > @@ -21,6 +21,8 @@
> > > > > > > 
> > > > > > >  #define GICD_BASE0x1c81000
> > > > > > >  #define GICC_BASE0x1c82000
> > > > > > > 
> > > > > > > +#define CONFIG_SUNXI_DE2
> > > > > > > +
> > > > > > > 
> > > > > > >  /*
> > > > > > >  
> > > > > > >   * Include common sunxi configuration where most the settings are
> > > > > > >   */
> > > > > > > 
> > > > > > > diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
> > > > > > > index a4c3fb69e4..c42b901107 100644
> > > > > > > --- a/include/configs/sun8i.h
> > > > > > > +++ b/include/configs/sun8i.h
> > > > > > > @@ -25,6 +25,10 @@
> > > > > > > 
> > > > > > >   #define CONFIG_SUNXI_USB_PHYS   2
> > > > > > >  
> > > > > > >  #endif
> > > > > > > 
> > > > > > > +#ifdef CONFIG_MACH_SUNXI_H3_H5
> > > > > > > +#define CONFIG_SUNXI_DE2
> > > > > > > +#endif
> > > > > > > +
> > > > > > > 
> > > > > > >  /*
> > > > > > >  
> > > > > > >   * Include common sunxi configuration where most the settings are
> > > > > > >   */
> > > > > > > 
> > > > > > > diff --git a/scripts/config_whitelist.txt
> > > > > > > b/scripts/config_whitelist.txt
> > > > > > > index 8e5dc36fa7..ba0eb12665 100644
> > > > > > > --- a/scripts/config_whitelist.txt
> > > > > > > +++ b/scripts/config_whitelist.txt
> > > > > > > @@ -3102,6 +3102,7 @@ CONFIG_STV0991_HZ_CLOCK
> > > > > > > 
> > > > > > >  CONFIG_ST_SMI
> > > > > > >  CONFIG_SUN4
> > > > > > >  CONFIG_SUNXI_AHCI
> > > > > > > 
> > > > > > > +CONFIG_SUNXI_DE2
> > > > > > > 
> > > > > > >  CONFIG_SUNXI_EMAC
> > > > > > >  CONFIG_SUNXI_GMAC
> > > > > > >  CONFIG_SUNXI_GPIO
> > > > > > 
> > > > > > This should be a Kconfig option.
> > > > > 
> > > > > So hidden option in board/sunxi/Kconfig will probably be the best
> > > > > then?
> > > > 
> > > > Yes, I guess, but I'm not entirely sure why you need two different
> > > > options there?
> > > 
> > > I used define for CONFIG_SUNXI_DE2 here because SoC has or has not DE2 IP
> > > block and that is not a choice. Option in patch 5 is configurable and
> > > gives opportunity to build video driver or skip it, whithout influencing
> > > clock structure.
> > > 
> > > I could make only one option, but then it would have to be configurable,
> > > which doesn't really make sense from patch 4 perspective, because, as I
> > > already stated before, this is property of the SoC.
> > > 
> > > Which solution do you prefer? One option, define and option (as it is now)
> > > or two options?
> > > 
> > > Frankly, none of them is ideal. Best solution would be to convert clocks
> > > to
> > > use driver model framework.
> > 
> > I guess you could make a hidden Kconfig option selected by the
> > relevant MACH_ options.
> > 
> > As a general basis, we move away from the old-style config options, so
> > adding any new !Kconfig options isn't really an option.
> 
> Ok.
> 
> Do you mind if I switch from 16 BPP to 32 BPP in patch 5? efifb linux driver 
> doesn't work well with 16 BPP.

Not at all, I think it's also what we use in the previous SoCs.

Maxime

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Re: [U-Boot] [PATCH 2/2] i2c: ti: Update method to calculate psc, sscl and ssch I2C parameters

[Heiko Schocher]

Hello Lukasz,

Am 27.03.2017 um 10:04 schrieb Lukasz Majewski:

Dear All,


This patch updates the way in which psc, sscl and ssch I2C parameters
are calculated to be in sync with v4.9 Linux kernel
SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826
in the ./drivers/i2c/busses/i2c-omap.c


Any comments on this?


I am fine with it, it is in my queue for sending a pull
request to Tom.

bye,
Heiko





The previous method was causing several issues:
- The internal I2C frequency (after prescaler) was far above
recommended one (7 - 12 MHz [*]) - the current approach brings better
noise suppression (as stated in Linux commit: SHA1:
84bf2c868f3ca996e5bb)

- The values calculated (psc, sscl and ssch) were far from optimal,
which caused on the test platform (AM57xx) the I2C0 SCL signal low
time (Fast Mode) of ~1.0us (the standard requires > 1.3 us).

[*] for AM57xx TRM SPRUHZ6G, Table 24,7
"HS I2C Register Values for Maximum I2C Bit Rates in I2C F/S, I2C HS
Modes"

Signed-off-by: Lukasz Majewski 
---
  drivers/i2c/omap24xx_i2c.c | 66
-- 1 file changed, 41
insertions(+), 25 deletions(-)

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 0006343..26996e9 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -64,36 +64,52 @@ struct omap_i2c {

  static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
  {
-   unsigned int sampleclk, prescaler;
-   int fsscll, fssclh;
+   unsigned long internal_clk = 0, fclk;
+   unsigned int prescaler;

-   speed <<= 1;
-   prescaler = 0;
/*
-* some divisors may cause a precission loss, but shouldn't
-* be a big thing, because i2c_clk is then allready very
slow.
+* This method is only called for Standard and Fast Mode
speeds
+*
+* For some TI SoCs it is explicitly written in TRM (e,g,
SPRUHZ6G,
+* page 5685, Table 24-7)
+* that the internal I2C clock (after prescaler) should be
between
+* 7-12 MHz (at least for Fast Mode (FS)).
+*
+* Such approach is used in v4.9 Linux kernel in:
+* ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
 */
-   while (prescaler <= 0xFF) {
-   sampleclk = I2C_IP_CLK / (prescaler+1);

-   fsscll = sampleclk / speed;
-   fssclh = fsscll;
-   fsscll -= I2C_FASTSPEED_SCLL_TRIM;
-   fssclh -= I2C_FASTSPEED_SCLH_TRIM;
-
-   if (((fsscll > 0) && (fssclh > 0)) &&
-   ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) &&
-   (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM {
-   if (pscl)
-   *pscl = fsscll;
-   if (psch)
-   *psch = fssclh;
-
-   return prescaler;
-   }
-   prescaler++;
+   speed /= 1000; /* convert speed to kHz */
+
+   if (speed > 100)
+   internal_clk = 9600;
+   else
+   internal_clk = 4000;
+
+   fclk = I2C_IP_CLK / 1000;
+   prescaler = fclk / internal_clk;
+   prescaler = prescaler - 1;
+
+   if (speed > 100) {
+   unsigned long scl;
+
+   /* Fast mode */
+   scl = internal_clk / speed;
+   *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
+   *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
+   } else {
+   /* Standard mode */
+   *pscl = internal_clk / (speed * 2) -
I2C_FASTSPEED_SCLL_TRIM;
+   *psch = internal_clk / (speed * 2) -
I2C_FASTSPEED_SCLH_TRIM; }
-   return -1;
+
+   debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch:
0x%x\n",
+ __func__, speed, prescaler, *pscl, *psch);
+
+   if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
+   return -EINVAL;
+
+   return prescaler;
  }

  /*





Best regards,

Lukasz Majewski

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DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de



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Re: [U-Boot] [PATCH v3] net: Kconfig:make PHY_GIGE and individual Micrel PHYs selectable

[Maxime Ripard]

On Sun, Mar 26, 2017 at 06:50:23PM +0200, Philipp Tomsich wrote:
> This change migrate the following configuration options for Kconfig:
>  * PHY_GIGE, indicates that a controller (with an appropriate PHY) is
>Gigabit capable and enables extra support in the miiutil for
>parsing the status of Gigabit PHYs
>  * adds configuration options for Micrel KSZ9021 and KSZ9031 GbE PHYs,
>which previously had to enabled through a board-specific config file
> 
> Signed-off-by: Philipp Tomsich 

Acked-by: Maxime Ripard 

Maxime

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Re: [U-Boot] [PATCH 1/2] i2c: ti: Update SCLH and SCLL to be in sync with v4.9 Linux kernel

[Heiko Schocher]

Hello Lukasz,

Am 27.03.2017 um 10:04 schrieb Lukasz Majewski:

Dear All,


v4.9 Linux release:
SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826
in the ./drivers/i2c/busses/i2c-omap.c

recommends to use SCLH=5 and SCLL=7 values.
This patch sets them to default.


Any comments on this?


I am fine with it, it is in my queue for sending a pull
request to Tom.

bye,
Heiko




Signed-off-by: Lukasz Majewski 
---
  drivers/i2c/omap24xx_i2c.h | 10 +-
  1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h
index 3dae295..8a4ae98 100644
--- a/drivers/i2c/omap24xx_i2c.h
+++ b/drivers/i2c/omap24xx_i2c.h
@@ -121,17 +121,17 @@
   * scll_trim = 7
   * sclh_trim = 5
   *
- * The linux 2.6.30 kernel uses
- * scll_trim = 6
- * sclh_trim = 6
+ * The linux 4.9 kernel uses
+ * scll_trim = 7
+ * sclh_trim = 5
   *
   * These are the trim values for standard and fast speed
   */
  #ifndef I2C_FASTSPEED_SCLL_TRIM
-#define I2C_FASTSPEED_SCLL_TRIM6
+#define I2C_FASTSPEED_SCLL_TRIM7
  #endif
  #ifndef I2C_FASTSPEED_SCLH_TRIM
-#define I2C_FASTSPEED_SCLH_TRIM6
+#define I2C_FASTSPEED_SCLH_TRIM5
  #endif

  /* These are the trim values for high speed */





Best regards,

Lukasz Majewski

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Re: [U-Boot] [EXT] Re: [PATCH 7/7] scsi: dts: a3700: add scsi node

[Ken Ma]

Hi Stefan

I think it's a good way, but I wonder why the codes calls ffs() but not fls()?
If the linkmap is 0x, it seems that ffs() returns 1 while fls() returns 16, 
I think max_id should be 16 then.

Yours,
Ken

-Original Message-
From: Stefan Roese [mailto:s...@denx.de] 
Sent: 2017年3月24日 21:24
To: Ken Ma; u-boot@lists.denx.de
Cc: Simon Glass; Michal Simek; Kostya Porotchkin; Hua Jing; Wilson Ding
Subject: Re: [EXT] Re: [PATCH 7/7] scsi: dts: a3700: add scsi node

Hi Ken,

btw, regarding the max-lun and max-id you could perhaps take a look at this 
recent patch, also dealing with these parameters:

https://patchwork.ozlabs.org/patch/743160/

I've not looked too close into this, just wanted to point it out to you.

Thanks,
Stefan
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Re: [U-Boot] [PATCH 2/4 v3] dm: core: Add dm_remove_devices_flags() and hook it into device_remove()

[Stefan Roese]

Hi Simon,

On 26.03.2017 05:52, Simon Glass wrote:

On 25 March 2017 at 19:17, Simon Glass  wrote:

Hi Stefan,

On 22 March 2017 at 00:28, Stefan Roese  wrote:

The new function dm_remove_devices_flags() is intented for driver specific
last-stage cleanup operations before the OS is started. This patch adds
this functionality and hooks it into the common device_remove()
function.

Drivers wanting to use this feature for some last-stage removal calls,
need to add one of the DM_REMOVE_xx flags to their driver .flags.

Signed-off-by: Stefan Roese 
Reviewed-by: Simon Glass 
---
v3:
- Add conditional compilation to fix compilation breakage on platforms
  without DM and DM_DEVICE_REMOVE support. With this change, Travis
  compiles all targets without any error

v2:
- Added Simons Reviewed-by

 drivers/core/device-remove.c | 15 +++
 drivers/core/root.c  |  9 +
 include/dm/root.h| 16 
 3 files changed, 36 insertions(+), 4 deletions(-)

diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index b80bf52320..ca4680f7c2 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -174,7 +174,12 @@ int device_remove(struct udevice *dev, uint flags)
if (ret)
goto err;

-   if (drv->remove) {
+   /*
+* Remove the device if called with the "normal" remove flag set,
+* or if the remove flag matches the driver flags
+*/
+   if (drv->remove &&
+   ((flags & DM_REMOVE_NORMAL) || (flags & drv->flags))) {


This seems to be comparing different things. The DM_REMOVE_NORMAL flag
is not from the same enum as drv->flags, is it?


I have to admit that this comparison above is a bit "vague". I'll
make it more explicit in the next patch version.

Thanks,
Stefan
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Re: [U-Boot] [EXT] Re: [PATCH 7/7] scsi: dts: a3700: add scsi node

[Ken Ma]

Hi Stefan



Thanks a lot for your kind reply.



But I still do not think it's very good to change sata's uclass id from 
"UCLASS_AHCI" to "UCLASS_SCSI".

If we do such change, UCLASS_AHCI is lost since from the sata.c codes, it does 
the AHCI initialization work but not SCSI initialization work.

If u-boot supports ISIS scanner which supports SCSI, I think its uclass id 
should be like UCLASS_ISIS but not UCLASS_SCSI.

And if we set sata's uclass id as "UCLASS_SCSI", it should provide basic SCSI 
function, then why can’t we connect a parallel SCSI device like SCSI scanner or 
cd-rom to the SATA interface?

From https://en.wikipedia.org/wiki/Serial_ATA#SATA_and_SCSI

In general, SATA devices link compatibly to SAS enclosures and adapters, 
whereas SCSI devices cannot be directly connected to a SATA bus





Actually Marvell’s sata controller is SAS(Serial Attached SCSI system), it 
integrates SCSI and SATA(AHCI); SAS provides a SCSI bus which works only in SAS 
range(for example, 2 sata ports in SAS), so actually the SCSI bus controller is 
not "virtual" controllers but has the same device base register as SATA.



From https://en.wikipedia.org/wiki/Serial_Attached_SCSI

A typical Serial Attached SCSI system consists of the following basic 
components:
1.An initiator: a device that originates device-service and 
task-management 
requests for processing by a target device and receives responses for the same 
requests from other target devices. Initiators may be provided as an on-board 
component on the motherboard (as is the case with many server-oriented 
motherboards) or as an add-on host bus 
adapter.
2.A target: …
So in my opinion, there are two ways to implement SAS as below

A.  If our codes provide SAS controller as an on-board component – then a 
uclass id of UCLASS_SAS should be defined and then in scsi_scan() of 
scsi_scan.c, both devices of UCLASS_SCSI and UCLASS_SAS should be scanned. In 
such implementation, UCLASS_SCSI is for parallel SCSI while UCLASS_SAS is for 
serial attached SCSI;

B.  SAS works as an add-on host bus 
adapter as above said, SAS’s 
SCSI controller and AHCI controller are both itself as below - SCSI controller 
is not a virtual device, it exists and only works in SAS internal range(since 
there is no UCLASS_SAS, I take this way);

Although the SAS’s SCSI controller does not need to any special hardware 
configuration; but actually I think there is something to do, we should bind 
special scsi_exec() to SCSI devices in SCSI driver or SAS driver (For different 
SCSI controls, SAS must have different implementation of scsi_exec() comparing 
to SCSI scanner, or other SCSI devices)

By the way, I think we should move the work of creating block devices to 
scsi-uclass.c

scsi: scsi@e {

compatible = "marvell,mvebu-scsi";

reg = <0xe 0x2000>;

sata: sata@e {

  compatible = "marvell,armada-3700-ahci";

  reg = <0xe 0x2000>;

  interrupts = ;

};

  };





Yours,

Ken





-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: 2017年3月24日 21:22
To: Ken Ma; u-boot@lists.denx.de
Cc: Simon Glass; Michal Simek; Kostya Porotchkin; Hua Jing; Wilson Ding
Subject: Re: [EXT] Re: [PATCH 7/7] scsi: dts: a3700: add scsi node



Hi Ken,



On 24.03.2017 05:11, Ken Ma wrote:







>> b/arch/arm/dts/armada-3720-db.dts index 85761af..9fc60f6 100644

>

>> --- a/arch/arm/dts/armada-3720-db.dts

>

>> +++ b/arch/arm/dts/armada-3720-db.dts

>

>> @@ -89,6 +89,10 @@

>

>> status = "okay";

>

>>  };

>

>>

>

>> + {

>

>> +   status = "okay";

>

>> +};

>

>> +

>

>>  /* CON3 */

>

>>   {

>

>> status = "okay";

>

>> diff --git a/arch/arm/dts/armada-37xx.dtsi

>

>> b/arch/arm/dts/armada-37xx.dtsi index 062f2a6..de5d3a1 100644

>

>> --- a/arch/arm/dts/armada-37xx.dtsi

>

>> +++ b/arch/arm/dts/armada-37xx.dtsi

>

>> @@ -149,11 +149,19 @@

>

>>   status = "disabled";

>

>> };

>

>>

>

>> -   sata: sata@e {

>

>> - compatible = "marvell,armada-3700-ahci";

>

>> - reg = <0xe 0x2000>;

>

>> - interrupts = ;

>

>> +   scsi: scsi {

>

>> + compatible = "marvell,mvebu-scsi";

>

>> + #address-cells = <1>;

>

>> + #size-cells = <1>;

>

>> + max-id = <1>;

>

>> + max-lun = <1>;

>

>>   status = "disabled";

>

>> + sata: sata@e {

>

>> +   compatible = "marvell,armada-3700-ahci";

>

>> +   reg = 

Re: [U-Boot] [U-Boot 0/3] introduce Rockchip rockusb

[Lukasz Majewski]

HI Eddie,

> rockusb is a protocol run between host pc and device. it help people
> get device info, flash image to device. this patch implement rockusb
> on device side. 

I'm a bit confused, since I don't know if you work on v2 of those
patches (as Kever Yang pointed out that UMS approach could be
re-used here)?

(And just gentle reminder of the README.xxx file to describe
this protocol). 

> 
> Eddie Cai (3):
>   drivers: usb: gadget: add the rockusb gadget
>   cmd: add rockusb command
>   rockchip: rk3288: enable rockusb support on rk3288 based device
> 
>  cmd/Kconfig |  12 +
>  cmd/Makefile|   1 +
>  cmd/rockusb.c   |  79 
>  drivers/usb/gadget/Makefile |   1 +
>  drivers/usb/gadget/f_rockusb.c  | 801
> 
> include/configs/rk3288_common.h |   4 +
> include/rockusb.h   |  13 + 7 files changed, 911
> insertions(+) create mode 100644 cmd/rockusb.c
>  create mode 100644 drivers/usb/gadget/f_rockusb.c
>  create mode 100644 include/rockusb.h
> 


Best regards,

Lukasz Majewski

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