On Tue, May 07, 2019 at 07:53:41AM +0200, Heinrich Schuchardt wrote:
> On 5/7/19 7:44 AM, Takahiro Akashi wrote:
> >On Tue, May 07, 2019 at 07:26:46AM +0200, Heinrich Schuchardt wrote:
> >>On 5/7/19 5:02 AM, Takahiro Akashi wrote:
> >>>On Sat, May 04, 2019 at 10:36:33AM +0200, Heinrich Schuchardt
On 5/7/19 7:44 AM, Takahiro Akashi wrote:
On Tue, May 07, 2019 at 07:26:46AM +0200, Heinrich Schuchardt wrote:
On 5/7/19 5:02 AM, Takahiro Akashi wrote:
On Sat, May 04, 2019 at 10:36:33AM +0200, Heinrich Schuchardt wrote:
In UnloadImage() we need to know if an image is already started.
Add a
On 5/7/19 6:39 AM, Takahiro Akashi wrote:
On Sat, May 04, 2019 at 10:36:36AM +0200, Heinrich Schuchardt wrote:
Implement unloading of images in the Exit() boot services:
* unload images that are not yet started,
* unload started applications,
* unload drivers returning an error.
On Tue, May 07, 2019 at 07:26:46AM +0200, Heinrich Schuchardt wrote:
> On 5/7/19 5:02 AM, Takahiro Akashi wrote:
> >On Sat, May 04, 2019 at 10:36:33AM +0200, Heinrich Schuchardt wrote:
> >>In UnloadImage() we need to know if an image is already started.
> >>
> >>Add a field to the handle structure
On 06.05.19 18:35, Luka Kovacic wrote:
CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and
like some of the other similar boards requires bin_hdr.
bin_hdr (DDR3 init stage) is currently retrieved from the stock
bootloader and compiled into the kwb image.
Adds support for
On 5/7/19 5:02 AM, Takahiro Akashi wrote:
On Sat, May 04, 2019 at 10:36:33AM +0200, Heinrich Schuchardt wrote:
In UnloadImage() we need to know if an image is already started.
Add a field to the handle structure identifying loaded and started images.
Signed-off-by: Heinrich Schuchardt
---
From: "Ang, Chee Hong"
The address of PSCI text, data and stack sections start at
0x1000 (SDRAM).
Signed-off-by: Ang, Chee Hong
---
arch/arm/mach-socfpga/Kconfig | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/Kconfig
From: "Ang, Chee Hong"
Enable psci_cpu_on support for Stratix10. This PSCI function
will pass the cpu release address for CPU1-CPU3. Then send event
signal shall be triggered to get these CPUs running Linux code.
Signed-off-by: Ang, Chee Hong
---
arch/arm/mach-socfpga/psci.c | 35
From: "Ang, Chee Hong"
Enable psci_system_reset support for Stratix10. This PSCI function
will eventually trigger the mailbox HPS_REBOOT to SDM.
Signed-off-by: Ang, Chee Hong
---
arch/arm/mach-socfpga/Makefile | 3 +++
arch/arm/mach-socfpga/psci.c | 21 +
2 files
From: "Ang, Chee Hong"
Add "SYTEM_RESET" (cold reset) and "CPU_ON" (SMP) PSCI support
for booting Linux on Stratix 10 platform.
Ang, Chee Hong (3):
ARM: socfpga: stratix10: Enable PSCI system reset
ARM: socfpga: stratix10: Enable PSCI CPU_ON
ARM: socfpga: stratix10: Enable PSCI support
On 5/7/19 3:53 AM, Takahiro Akashi wrote:
On Tue, Apr 30, 2019 at 08:11:15AM +0200, Heinrich Schuchardt wrote:
The field boot OptionalData in structure _EFI_LOAD_OPTIONS is for binary
data.
When we use `efidebug boot add` we should convert the 5th argument from
UTF-8 to UTF-16 before putting
From: "Ang, Chee Hong"
Prior U-Boot pass control to Linux, U-Boot will send a mailbox command
"HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW
transition.
Signed-off-by: Chin Liang See
Signed-off-by: Ang, Chee Hong
---
arch/arm/mach-socfpga/misc_s10.c | 5 +
1 file
From: "Ang, Chee Hong"
Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device
Manager (SDM) on the stage of HPS code execution. In general, there
are three main code execution stages: First Stage Boot Loader (FSBL)
which is U-Boot SPL, Second Stage Boot Loader (SSBL) which is
From: "Ang, Chee Hong"
Notify Secure Device Manager (SDM) on the stage of HPS code execution.
In general, there are three main code execution stages:
(1) First Stage Boot Loader (FSBL) which is U-Boot SPL.
(2) Second Stage Boot Loader (SSBL) which is U-Boot.
(3) Operating System which is Linux.
From: "Ang, Chee Hong"
Prior SPL pass control to U-Boot, SPL will send a mailbox command
"HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW
transition.
This is for debug purpose as user can query SDM on HPS error
details when HPS enters a warm reset due to error such as
Hi Philipp and Klaus,
Does this patch OK for your boards?
Thanks,
-Kever
On 04/28/2019 05:09 PM, Jagan Teki wrote:
> Right now puma rk3399 board need to copy bl31-rk3399.bin and
> rk3399m0.bin into u-boot source directory to make use of building
> u-boot.itb.
>
> So, add environment variable
Hi Simon,
On Mon, May 06, 2019 at 09:51:56PM -0600, Simon Glass wrote:
> Hi Andreas,
>
> On Fri, 3 May 2019 at 14:25, Andreas Dannenberg wrote:
> >
> > Simon,
> >
> > On Sat, Mar 30, 2019 at 09:18:08PM +0100, Simon Goldschmidt wrote:
> > > Simon Glass schrieb am Sa., 30. März 2019, 21:06:
> >
On Sat, May 04, 2019 at 10:36:36AM +0200, Heinrich Schuchardt wrote:
> Implement unloading of images in the Exit() boot services:
>
> * unload images that are not yet started,
> * unload started applications,
> * unload drivers returning an error.
>
> Signed-off-by: Heinrich Schuchardt
> ---
>
On Mon, 2019-05-06 at 21:51 -0600, Simon Glass wrote:
> Hi Matti,
>
> On Thu, 25 Apr 2019 at 03:51, Matti Vaittinen
> wrote:
> >
> > BD71837 and BD71847 is PMIC intended for powering single-core,
> > dual-core, and quad-core SoC’s such as NXP-i.MX 8M. BD71847
> > is used for example on NXP
Hi Jagan,
On 04/27/2019 07:48 PM, Jagan Teki wrote:
> Add default SPL_FIT_GENERATOR py script for rockchip platforms if
> specific target enabled SPL_LOAD_FIT.
>
> So, this would help get rid of explicitly mentioning the default
> SPL FIT generator in defconfigs. however some targets, like
On Thu, 25 Apr 2019 at 03:48, Matti Vaittinen
wrote:
>
> https://source.codeaurora.org/external/imx/uboot-imx
>
> cherry picked, styled and merged commits:
> - MLK-18387 pmic: Add pmic driver for BD71837: e9a3bec2e95a
> - MLK-18590 pmic: bd71837: Change to use new fdt API: acdc5c297a96
>
>
Hi Thierry,
On Thu, 25 Apr 2019 at 07:25, Thierry Reding wrote:
>
> On Mon, Apr 15, 2019 at 10:08:20AM +0200, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > The fdt_setprop_u32() function does everything that we need, so we
> > really only use the function as a convenience wrapper, in
Hi Thierry,
On Fri, 26 Apr 2019 at 06:01, Thierry Reding wrote:
>
> On Mon, Apr 15, 2019 at 10:08:21AM +0200, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > U-Boot already defines the {upper,lower}_32_bits() macros that have the
> > same purpose. Use the existing macros instead of
Hi Jean-Jacques,
On Fri, 5 Apr 2019 at 06:56, Jean-Jacques Hiblot wrote:
>
> This uclass is intended for devices that do not need any features from the
> uclass, including binding children.
> This will typically be used by devices that are used to bind child devices
> but do not use
Hi Matti,
On Thu, 25 Apr 2019 at 03:51, Matti Vaittinen
wrote:
>
> BD71837 and BD71847 is PMIC intended for powering single-core,
> dual-core, and quad-core SoC’s such as NXP-i.MX 8M. BD71847
> is used for example on NXP imx8mm EVK.
>
> Add regulator driver for ROHM BD71837 and BD71847 PMICs.
>
Hi Andreas,
On Fri, 3 May 2019 at 14:25, Andreas Dannenberg wrote:
>
> Simon,
>
> On Sat, Mar 30, 2019 at 09:18:08PM +0100, Simon Goldschmidt wrote:
> > Simon Glass schrieb am Sa., 30. März 2019, 21:06:
> >
> > > Hi Simon,
> > >
> > > On Wed, 27 Mar 2019 at 13:40, Simon Goldschmidt
> > >
On Fri, 3 May 2019 at 20:03, Z.q. Hou wrote:
>
> From: Hou Zhiqiang
Needs a commit message.
>
> Signed-off-by: Hou Zhiqiang
> ---
> configs/T2080QDS_defconfig | 5 +
> 1 file changed, 5 insertions(+)
Reviewed-by: Simon Glass
___
U-Boot
On Fri, 3 May 2019 at 20:03, Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> T2080 integrated 4 PCIe controllers, which is compatible with
> the PCI Express™ Base Specification, Revision 3.0, and this
> patch is to add DT node for each PCIe controller.
>
> Signed-off-by: Hou Zhiqiang
> ---
>
On Fri, 3 May 2019 at 20:03, Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Disable legacy PCIe driver and remove unused PCIe macros.
>
> Signed-off-by: Hou Zhiqiang
> ---
> include/configs/T208xQDS.h | 18 --
> 1 file changed, 18 deletions(-)
>
Reviewed-by: Simon Glass
On Sun, 28 Apr 2019 at 03:43, Peng Fan wrote:
>
> `if (!strncmp(dev->name, name, strlen(name)))` might find out
> the wrong device, it might find out `dram_pll_ref_sel`, when name is
> `dram_pll`. So use strcmp to avoid such issue.
>
> Signed-off-by: Peng Fan
> ---
> drivers/core/uclass.c | 2
On Fri, 3 May 2019 at 20:03, Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Compile the legacy PCIe initialization reoutines only when DM_PCI
> is not enabled.
>
> Signed-off-by: Hou Zhiqiang
> ---
> board/freescale/t208xqds/pci.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Simon Glass
On Fri, 3 May 2019 at 20:03, Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Compile the routines of mpc85xx/pci.c when both FSL_PCI_INIT
> and DM_PCI are not enabled.
>
> Signed-off-by: Hou Zhiqiang
> ---
> arch/powerpc/cpu/mpc85xx/pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On 04/16/2019 09:57 PM, David Wu wrote:
> As the common set_mux func(), implement the feature at the own file
> for each Soc.
>
> Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
>
> Change in v3:
> - None
>
> drivers/pinctrl/rockchip/pinctrl-rk3036.c | 23 -
>
On 04/16/2019 09:57 PM, David Wu wrote:
> As the mux/pull/drive feature implement at own file,
> the type and label are not necessary.
>
> Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
>
> Change in v3:
> - None
>
> drivers/pinctrl/rockchip/pinctrl-rk3036.c | 2 --
On 04/16/2019 09:58 PM, David Wu wrote:
> Only some Soc need Schmitter feature, so move the
> implementation into their own files.
>
> Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
>
> Change in v3:
> - None
>
> drivers/pinctrl/rockchip/pinctrl-rk3328.c | 17
On 04/16/2019 09:50 PM, David Wu wrote:
> RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
> bits, need to read before write the register.
>
> Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
>
> Change in v3:
> - Add some comment
>
>
On 04/16/2019 09:57 PM, David Wu wrote:
> RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
> bits, need to read before write the register.
>
> Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
>
> Change in v3:
> - None
>
>
On 04/16/2019 09:56 PM, David Wu wrote:
> RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
> corresponding bits, need to read before write the register.
>
> Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
>
> Change in v3:
> - Add some comment
>
>
On 04/16/2019 09:55 PM, David Wu wrote:
> As the common set_mux func(), implement the feature at the own file
> for each Soc.
>
> Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
>
> Change in v3:
> - None
>
> drivers/pinctrl/rockchip/pinctrl-rk322x.c | 25 -
>
The following changes since commit 86f578ee85a697afb980233312f9aac1d98816df:
Merge tag 'mips-pull-2019-05-03' of git://git.denx.de/u-boot-mips
(2019-05-04 20:02:42 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to
On 04/16/2019 09:50 PM, David Wu wrote:
> Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
> higher 16 writing corresponding bits, use common set_mux() func would
> introduce more code, so implement their set_mux() in each Soc's own
> file to reduce the size of code.
>
>
On 04/16/2019 09:50 PM, David Wu wrote:
> Some files have the redundant spaces, remove them.
>
> Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
>
> Change in v3:
> - None
>
> drivers/pinctrl/rockchip/pinctrl-rk3036.c | 12 ++--
>
On 04/16/2019 09:50 PM, David Wu wrote:
> Some Socs use the pull-pin-default config param, need to add it.
> And input-enable/disable config params are not necessary, remove it.
>
> Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
>
> Change in v3:
> - Add some commit
On 5/7/19 5:28 AM, Ang, Chee Hong wrote:
> On Fri, 2019-05-03 at 21:31 +0200, Marek Vasut wrote:
>> On 5/3/19 7:56 PM, Ang, Chee Hong wrote:
>>>
>>> On Fri, 2019-05-03 at 19:04 +0200, Marek Vasut wrote:
On 5/3/19 5:53 PM, Ang, Chee Hong wrote:
>
>
> On Fri, 2019-05-03 at
On Fri, 2019-05-03 at 21:31 +0200, Marek Vasut wrote:
> On 5/3/19 7:56 PM, Ang, Chee Hong wrote:
> >
> > On Fri, 2019-05-03 at 19:04 +0200, Marek Vasut wrote:
> > >
> > > On 5/3/19 5:53 PM, Ang, Chee Hong wrote:
> > > >
> > > >
> > > > On Fri, 2019-05-03 at 11:55 +0200, Marek Vasut wrote:
> >
Enable watchdog which is sp805, can be found on some NXP
Layerscape SoC.
Signed-off-by: Zhao Qiang
---
configs/ls1028ardb_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/ls1028ardb_defconfig b/configs/ls1028ardb_defconfig
index e3ff21f10c..5edcaae24b 100644
---
sp805 is watchdog on some NXP layerscape SoCs, Now add its driver in uboot.
To add
CONFIG_WDT_SP805=y
CONFIG_WDT=y
CONFIG_CMD_WDT=y
in defconfig to use it.
Signed-off-by: Zhao Qiang
---
MAINTAINERS | 1 +
drivers/watchdog/Kconfig | 7 ++
add sp805 nodes in fsl-ls1028a.dtsi
Signed-off-by: Zhao Qiang
---
arch/arm/dts/fsl-ls1028a.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 35382eb3b4..30fb20cd3e 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++
changes for v2:
- modify the driver to DM
changes for v3:
- drop member "timeout" of struct "sp805_wat_priv", it is not
needed
Zhao Qiang (3):
watchdog: add sp805 watchdog support
dts: fsl-ls1028a: add sp805 node which is a watchdog
defconfig: ls1028ardb: enable
On Sat, May 04, 2019 at 10:36:33AM +0200, Heinrich Schuchardt wrote:
> In UnloadImage() we need to know if an image is already started.
>
> Add a field to the handle structure identifying loaded and started images.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> include/efi_loader.h |
Hi Tom,
In order to determine whether linux entry point has been called or not, I put a
loop in kernel:
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 261f3f88364c..dea6cb8baa6a 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -80,6 +80,7 @@ _head:
On Sun, May 05, 2019 at 10:12:24PM +0530, Jagan Teki wrote:
> Hi Tom,
>
> Please pull this spi-mem fix.
>
> thanks,
> Jagan.
>
> The following changes since commit b4ee6daad7a2604ca9466b2ba48de86cc27d381f:
>
> Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx (2019-05-01
>
On Sun, May 05, 2019 at 09:18:04PM +0200, Marek Vasut wrote:
> The following changes since commit 4862830b696a6d0750e19d32a82553cdb41a85f8:
>
> Merge git://git.denx.de/u-boot-socfpga (2019-05-03 14:23:01 -0400)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-sh.git
Heiko,
On 04/05/2019 04:30 PM, Heiko Stuebner wrote:
> We want to use ATF loaded by the SPL, so need support for the itb FIT
> in SPL which therefore needs real mmc reading capabilities making it
> too big for the sram. So convert to use TPL for memory init beforehand
> similar to rk3288-vyasa.
Heiko,
On 04/05/2019 04:30 PM, Heiko Stuebner wrote:
> ATF resides in the first 2MB of ram and will also protect this
> area from non-secure access.
>
> So similar to other Rockchip socs keep this area from the usable ram.
>
> Signed-off-by: Heiko Stuebner
> ---
>
Hi Heiko,
On 04/05/2019 04:30 PM, Heiko Stuebner wrote:
> Enable both rk3288-evb variants to load an ATF binary between
> spl and u-boot proper.
Does this the same as aarch64 boot/load flow?
tpl->spl->atf->u-boot
>
> Doing the regular spl->u-boot load of course still stays possible
> with this
On Tue, Apr 30, 2019 at 08:11:15AM +0200, Heinrich Schuchardt wrote:
> The field boot OptionalData in structure _EFI_LOAD_OPTIONS is for binary
> data.
>
> When we use `efidebug boot add` we should convert the 5th argument from
> UTF-8 to UTF-16 before putting it into the Boot variable.
On 5/7/19 2:49 AM, Atish Patra wrote:
> This patch adds booti support for RISC-V Linux kernel. The existing
> bootm method will also continue to work as it is.
>
> It depends on the following kernel patch which adds the header to the
> flat Image. Gzip compressed Image (Image.gz) support is not
This patch adds booti support for RISC-V Linux kernel. The existing
bootm method will also continue to work as it is.
It depends on the following kernel patch which adds the header to the
flat Image. Gzip compressed Image (Image.gz) support is not enabled with
this patch.
On 5/6/19 2:27 PM, Tom Rini wrote:
On Mon, May 06, 2019 at 11:10:57PM +0200, Heinrich Schuchardt wrote:
On 5/6/19 10:39 PM, Karsten Merker wrote:
On Mon, May 06, 2019 at 10:06:39PM +0200, Heinrich Schuchardt wrote:
On 5/6/19 8:11 PM, Atish Patra wrote:
This patch adds booti support for
On Tue, 30 Apr 2019 10:18:12 +
Peng Fan wrote:
> Add pre reloc flag to use this driver before relocation
>
> Signed-off-by: Peng Fan
> ---
> drivers/clk/clk_fixed_rate.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/clk_fixed_rate.c
> b/drivers/clk/clk_fixed_rate.c
On Tue, 30 Apr 2019 10:18:15 +
Peng Fan wrote:
> Import some clk helpers from Linux Kernel for i.MX8MM usage
>
Please globally provide SHA1 and tag of ported code from Linux kernel.
> Signed-off-by: Peng Fan
> ---
> drivers/clk/imx/clk.h | 81
>
Hi Peng,
> Export the structure for others to use.
>
> Signed-off-by: Peng Fan
> ---
> drivers/clk/clk_fixed_rate.c | 8 +---
> include/linux/clk-provider.h | 7 +++
> 2 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/clk_fixed_rate.c
>
On Tue, 30 Apr 2019 10:17:54 +
Peng Fan wrote:
> Add set parent support for clk mux
>
I suppose that it was ported from Linux kernel directly?
If yes, please state the SHA1 of Linux master (or exact tag).
> Signed-off-by: Peng Fan
> ---
> drivers/clk/clk-mux.c| 70
>
On Tue, 30 Apr 2019 10:17:58 +
Peng Fan wrote:
> Export mux/divider ops for composite usage
>
> Signed-off-by: Peng Fan
> ---
> include/linux/clk-provider.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/linux/clk-provider.h
> b/include/linux/clk-provider.h index
On Tue, 30 Apr 2019 10:18:05 +
Peng Fan wrote:
Please state the exact SHA1 or tag when porting the code from Linux
kernel.
> Signed-off-by: Peng Fan
> ---
> drivers/clk/clk-divider.c | 88
> +++ 1 file changed, 88
> insertions(+)
>
> diff --git
On Tue, 30 Apr 2019 10:17:50 +
Peng Fan wrote:
> Print err value when clk_get_rate failed
>
> Signed-off-by: Peng Fan
> ---
> cmd/clk.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/cmd/clk.c b/cmd/clk.c
> index 2ea82176aa..73d963184d 100644
> --- a/cmd/clk.c
> +++
On Tue, 30 Apr 2019 10:17:47 +
Peng Fan wrote:
> Sync more clk flags that might be used in U-Boot CCF.
>
> Signed-off-by: Peng Fan
> ---
> include/linux/clk-provider.h | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/include/linux/clk-provider.h
>
On Tue, 30 Apr 2019 10:17:43 +
Peng Fan wrote:
> Preparing to support composite clk.
>
> Signed-off-by: Peng Fan
> ---
> drivers/clk/clk-divider.c | 4 ++--
> drivers/clk/clk-mux.c | 6 --
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git
On Tue, 30 Apr 2019 10:17:40 +
Peng Fan wrote:
> When support Clock Common Framework, U-Boot use dev for
> clk tree information, there is no clk->parent.
There is a function in clk uclass named:
clk_get_parent() to provide parent of the clock.
> When
> support composite clk, it contains
On Tue, 30 Apr 2019 10:17:36 +
Peng Fan wrote:
> driver data is not clk, not clk_fixed_factor, fix it.
This description is a bit misleading, IMHO.
The dev->driver_data holds pointer to corresponding struct clk clk
element (as described [1]).
This patch resembles changes from PATCH
Hi Peng,
> Directly use driver data is wrong, need to the helper to get
> the correct clk_divider and etc
I just followed the kernel approach.
This works as the address of first element of struct clk_XXX is always
struct clk clk address;
But yes, this may be the preferred (more readable)
Hi Peng,
> This patch set is based Lukasz V3 CCF patchset,
> [PATCH v3 00/11] clk: Port Linux common clock framework [CCF] to
> U-boot (tag: 5.0-rc3)
> https://github.com/lmajewski/u-boot-dfu/commits/CCF-v3
>
> Added a few fixes to Lukasz's v3 patchset.
> Introduced clk-gate/composite
> Added
If the size of the source buffer is 0, return EFI_LOAD_ERROR.
(UEFI SCT II 2017: 3.4.1 LoadImage() - 5.1.4.1.6)
Signed-off-by: Heinrich Schuchardt
---
v3
put change into separate patch
---
lib/efi_loader/efi_boottime.c | 4
1 file changed, 4 insertions(+)
diff --git
On Mon, May 06, 2019 at 11:10:57PM +0200, Heinrich Schuchardt wrote:
> On 5/6/19 10:39 PM, Karsten Merker wrote:
> >On Mon, May 06, 2019 at 10:06:39PM +0200, Heinrich Schuchardt wrote:
> >>On 5/6/19 8:11 PM, Atish Patra wrote:
> >>>This patch adds booti support for RISC-V Linux kernel. The
If the parent image handle does not refer to a loaded image return
EFI_INVALID_PARAMETER.
(UEFI SCT II 2017: 3.4.1 LoadImage() - 5.1.4.1.1)
Mark our root node as a loaded image to avoid an error when using it as
parent image.
Signed-off-by: Heinrich Schuchardt
---
v3
put change into
If the parent image handle does not refer to a loaded image return
EFI_INVALID_PARAMETER.
(UEFI SCT II 2017: 3.4.1 LoadImage() - 5.1.4.1.1)
If the size of the source buffer is 0, return EFI_LOAD_ERROR.
(UEFI SCT II 2017: 3.4.1 LoadImage() - 5.1.4.1.6)
v3
Put each change into a separate
On 5/6/19 10:13 PM, Simon Goldschmidt wrote:
[...]
> +static int socfpga_reset_bind(struct udevice *dev)
> +{
> + int ret;
> + struct udevice *sys_child;
> +
> + /*
> + * The sysreset driver does not have a device node, so bind it here.
> + * Bind it to the node, too, so
On 5/6/19 10:39 PM, Karsten Merker wrote:
On Mon, May 06, 2019 at 10:06:39PM +0200, Heinrich Schuchardt wrote:
On 5/6/19 8:11 PM, Atish Patra wrote:
This patch adds booti support for RISC-V Linux kernel. The existing
bootm method will also continue to work as it is.
[...]
+ "boot
Hi Neil,
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA512
>
> Hi Lukasw,
>
> Le 19/04/2019 08:17, Lukasz Majewski a écrit :
> > Hi Neil,
> >
> >> Adds support for Amlogic G12A USB Device mode.
> >>
> >> The DWC2 Controller behind the Glue can be connected to an OTG
> >> capable PHY. The
On 5/6/19 9:50 PM, Simon Goldschmidt wrote:
> Am 06.05.2019 um 00:51 schrieb Marek Vasut:
>> On 5/5/19 10:21 PM, Simon Goldschmidt wrote:
>>> Am 05.05.2019 um 22:17 schrieb Marek Vasut:
On 5/5/19 8:05 AM, Simon Goldschmidt wrote:
>
>
> On 05.05.19 03:42, Marek Vasut wrote:
>>
On Mon, May 06, 2019 at 10:06:39PM +0200, Heinrich Schuchardt wrote:
> On 5/6/19 8:11 PM, Atish Patra wrote:
> > This patch adds booti support for RISC-V Linux kernel. The existing
> > bootm method will also continue to work as it is.
[...]
> > + "boot arm64/riscv Linux Image image from memory",
Am 06.05.2019 um 17:45 schrieb Wolfgang Grandegger:
Re-add support for Aries Embedded MCV SoM, which is CycloneV based
and the associated MCVEVK baseboard. The board can boot from eMMC.
Ethernet and USB is supported.
The Aries Embedded boards have been removed with commit 03b54997d568
This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga
to a UCLASS_SYSRESET based dm driver.
A side effect is that gen5 and a10 can now select between cold and warm
reset.
Signed-off-by: Simon Goldschmidt
---
Changes in v2:
- adapt to patch that separates drivers/sysreset
This adds a define for the bit in rstmgr's ctrl regiser that issues
a cold reset (we had a define for the warm reset bit only) in preparation
for a proper sysrese driver.
Signed-off-by: Simon Goldschmidt
Series changes: 2
- separate this patch to the register descriptions from the actual
On 5/6/19 8:11 PM, Atish Patra wrote:
This patch adds booti support for RISC-V Linux kernel. The existing
bootm method will also continue to work as it is.
It depends on the following kernel patch which adds the header to the
flat Image. Gzip compressed Image (Image.gz) support is not enabled
Hi Matti,
On Wed, 24 Apr 2019 at 23:58, Vaittinen, Matti
wrote:
>
> Hello Simon and thanks again for taking the time to check this =)
>
> On Wed, 2019-04-24 at 17:58 -0600, Simon Glass wrote:
> > HI Matti,
> >
> > On Wed, 24 Apr 2019 at 06:37, Matti Vaittinen
> > wrote:
> > >
> > > BD71837 and
Am 06.05.2019 um 00:51 schrieb Marek Vasut:
On 5/5/19 10:21 PM, Simon Goldschmidt wrote:
Am 05.05.2019 um 22:17 schrieb Marek Vasut:
On 5/5/19 8:05 AM, Simon Goldschmidt wrote:
On 05.05.19 03:42, Marek Vasut wrote:
On 5/4/19 9:10 PM, Simon Goldschmidt wrote:
Am 04.05.2019 um 20:43 schrieb
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA512
Hi Lukasw,
Le 19/04/2019 08:17, Lukasz Majewski a écrit :
> Hi Neil,
>
>> Adds support for Amlogic G12A USB Device mode.
>>
>> The DWC2 Controller behind the Glue can be connected to an OTG
>> capable PHY. The Glue setups the PHY mode.
>>
>> This
On 5/5/19 4:07 AM, Karsten Merker wrote:
On Wed, May 01, 2019 at 01:07:31PM -0700, Atish Patra wrote:
This patch adds booti support for RISC-V Linux kernel. The existing
bootm method will also continue to work as it is.
It depends on the following kernel patch which adds the header to the
flat
This patch adds booti support for RISC-V Linux kernel. The existing
bootm method will also continue to work as it is.
It depends on the following kernel patch which adds the header to the
flat Image. Gzip compressed Image (Image.gz) support is not enabled with
this patch.
On 2019-05-06, Marek Vasut wrote:
> On 5/6/19 5:26 AM, Vagrant Cascadian wrote:
>> On 2019-05-06, Marek Vasut wrote:
>>> Enable DM USB support on iMX6Q Novena.
...
>> => load usb 0:1 $kernel_addr_r misc/Binaries/linux/Image
>> data abort
>> pc : [] lr : []
>> reloc pc : [<17832f0e>]lr
On 5/6/19 5:45 PM, Wolfgang Grandegger wrote:
> Re-add support for Aries Embedded MCV SoM, which is CycloneV based
> and the associated MCVEVK baseboard. The board can boot from eMMC.
> Ethernet and USB is supported.
I thought the board is now called MCVEVP , not MCVEVK ?
> The Aries Embedded
On Mon, May 06, 2019 at 06:44:48PM +0200, Niel Fourie wrote:
> Hi Tom,
>
> On 5/6/19 4:18 PM, Tom Rini wrote:
> >On Mon, May 06, 2019 at 04:02:53PM +0200, Niel Fourie wrote:
> >
> >>Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
> >>phyBOARD-Wega AM335x.
> >>
> >>CPU :
On Mon, 6 May 2019 at 07:18, Christian Gmeiner
wrote:
>
> malloc(..) and memalign(..) are both allocating memory and as a result
> we leak the memory allocated with malloc(..).
>
> Signed-off-by: Christian Gmeiner
> ---
> drivers/ata/ahci.c | 5 +
> 1 file changed, 1 insertion(+), 4
Hi,
On Fri, 3 May 2019 at 20:03, Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Add PCIe DM driver for Freescale PowerPC PCIe controllers.
>
> Signed-off-by: Hou Zhiqiang
> ---
> drivers/pci/Kconfig | 7 +
> drivers/pci/Makefile | 1 +
> drivers/pci/pcie_fsl.c | 612
On 2019-05-06, Marek Vasut wrote:
> On 5/6/19 5:31 AM, Vagrant Cascadian wrote:
>> On 2019-05-06, Marek Vasut wrote:
>>> Enable DM Video support on iMX6Q Novena and fix minor details
>>> to restore previous behavior of the system.
>>
>> Also required:
>>
>> "[U-Boot] video: ipuv3: Set max
Hi Tom,
On 5/6/19 4:18 PM, Tom Rini wrote:
On Mon, May 06, 2019 at 04:02:53PM +0200, Niel Fourie wrote:
Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
phyBOARD-Wega AM335x.
CPU : AM335X-GP rev 2.1
Model: Phytec AM335x phyBOARD-WEGA
DRAM: 256 MiB
NAND: 256 MiB
MMC: OMAP
CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and
like some of the other similar boards requires bin_hdr.
bin_hdr (DDR3 init stage) is currently retrieved from the stock
bootloader and compiled into the kwb image.
Adds support for U-Boot, enable UART, SPI, Winbond SPI flash
Re-add support for Aries Embedded MCV SoM, which is CycloneV based
and the associated MCVEVK baseboard. The board can boot from eMMC.
Ethernet and USB is supported.
The Aries Embedded boards have been removed with commit 03b54997d568
("board/aries: Remove"). I will now take care of them.
1 - 100 of 200 matches
Mail list logo
