Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> Add support for multiple DRAM configuration subnodes, while retaining the
> support for a single flat DRAM configuration node. This is useful on systems
> which can be manufactured in multiple configurations and where the DRAM
>
Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> The AV96 board does exist in multiple variants. To cater for all of them,
> implement
> board code handling. There are two GPIOs which code the type of the board,
> read
> them out and use the value to pick the correct device
Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> Add weak implementation of board_early_init_f() hook into the
> STM32MP1 SPL. This can be used to read out e.g. configuration straps before
> initializing the DRAM.
>
> Reviewed-by: Patrick Delaunay
> Signed-off-by: Marek Vasut
Disable PCS autonegotiation if fixed-link node is present in device tree.
This way systems with multiple GEM instances with a combination of
SGMII-fixed and SGMII-PHY will work.
Reported-by: Goran Marinkovic
Signed-off-by: Michal Simek
Signed-off-by: Ashok Reddy Soma
---
Hi Marek,
> From: U-Boot On Behalf Of Patrick DELAUNAY
> Sent: mercredi 22 avril 2020 10:25
>
> Dear Marek,
>
> > From: Marek Vasut
> > Sent: vendredi 10 avril 2020 20:56
> >
> > Add default U-Boot configuration for the DHCOR SoM on AV96 board.
> >
> > Signed-off-by: Marek Vasut
> > Cc:
Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> The DHCOR board does exist in multiple variants with different DDR3 DRAM
> sizes.
> To cater for all of them, implement DDR3 code handling.
> There are two GPIOs which code the DRAM size populated on the SoM, read them
> out and
Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> Adjust the DDR configuration dtsi such that they only generate the DRAM
> configuration node, the DDR controller node is moved into the stm32mp157-u-
> boot.dtsi itself. This permits including multiple DDR configuration dtsi
>
Hi Daniel,
On 13.05.20 14:49, Daniel Schwierzeck wrote:
sorry for the delay ;)
NP. I know that its sometimes not easy to find the time for this
maintainer / review job. ;)
Am 02.05.20 um 10:59 schrieb Stefan Roese:
From: Aaron Williams
This patch adds very basic support for the Octeon
On 13.05.20 14:59, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.
Signed-off-by: Stefan Roese
---
arch/mips/lib/cache.c | 13
On 13.05.20 15:05, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
The Octeon platform is cache coherent and cache flushes and invalidates
are not needed. This patch makes use of the newly introduced Kconfig
option CONFIG_MIPS_CACHE_COHERENT to effectively disable all the
From: Suneel Garapati
Add support for I2C controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
Signed-off-by: Stefan Roese
Cc: Heiko Schocher
Cc: Simon Glass
Cc: Daniel Schwierzeck
Cc: Aaron Williams
Cc:
Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> Add default U-Boot configuration for the DHCOR SoM on AV96 board.
>
> Reviewed-by: Patrick Delaunay
> Signed-off-by: Marek Vasut
> Cc: Manivannan Sadhasivam
> Cc: Patrick Delaunay
> Cc: Patrice Chotard
> ---
> V2: No change
On Thu, Apr 30, 2020 at 6:13 AM Michal Simek wrote:
>
> On 29. 04. 20 16:55, Rob Herring wrote:
> > On Tue, Apr 28, 2020 at 8:51 AM Michal Simek
> > wrote:
> >>
> >> On 28. 04. 20 15:23, Rob Herring wrote:
> >>> On Wed, Apr 1, 2020 at 4:23 AM Michal Simek
> >>> wrote:
>
> Hi Rob and
From: Pengpeng Chen
Add SPI Flash controller driver for Cortina Access
CA SoCs
Signed-off-by: Pengpeng Chen
Signed-off-by: Alex Nemirovsky
CC: Jagan Teki
CC: Vignesh R
ca slfash fixup
---
Changes in v7:
- Replace substring "OPCODE" with "OP" in MACROs to help
reduce code line lengths
Change DT compatibility name to match change in driver's name.
Remove unused io_ds and fifo_mode fields from DT.
Signed-off-by: Alex Nemirovsky
CC: Peng Fan
---
Changes in v7:
- Cleanup typos in commit subject line and description
Changes in v6: None
Changes in v5:
- Rebase on codebase basis
Add I2C board support for Cortina Access Presidio Engineering Board
Signed-off-by: Alex Nemirovsky
CC: Heiko Schocher
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
configs/cortina_presidio-asic-emmc_defconfig | 3
From: Jway Lin
Add Cortina Access LED controller support for CA SOCs
Signed-off-by: Jway Lin
Signed-off-by: Alex Nemirovsky
CC: Simon Glass
---
Changes in v7:
- rename OFFSET to SHIFT from macros
- add additinal struct comments
- Reading the DT should really happen in the
This release adds the following drivers and
integrates support into the Cortina Access
Presidio Engineering Board:
CA SoC eMMC/SD controller
CA SoC I2C controller
CA Soc LED controller
CA SPI NAND and NOR controller
Changes in v7:
- Cleanup typos in commit subject line and
From: Jway Lin
Add LED support for Cortina Access Presidio Engineering Board
Signed-off-by: Jway Lin
Signed-off-by: Alex Nemirovsky
Reviewed-by: Simon Glass
CC: Simon Glass
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- rename DT blink rate symbol
From: Arthur Li
Add I2C controller support for Cortina Access CA SoCs
Signed-off-by: Arthur Li
Signed-off-by: Alex Nemirovsky
CC: Heiko Schocher
CA_I2C: DT binding for I2C controller
DT binding document for Cortina I2C driver
---
Changes in v7:
- Added additional description info in
Add SPI NOR support for Cortina Access
Presidio Engineering Board
Signed-off-by: Alex Nemirovsky
CC: Jagan Teki
CC: Vignesh R
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- NAND support removed from presidio-asic board DT.
Changes in v4: None
Changes in v3: None
Changes in v2:
From: Arthur Li
- Rename DT compatible name
- Remove uneccessary if-statement to support 8-bit buswidth
- Remove redundant error msg
- Use symbolic constants in switch statement
Signed-off-by: Arthur Li
Signed-off-by: Alex Nemirovsky
CC: Peng Fan
---
Changes in v7: None
Changes in v6: None
On 2020/5/12 下午6:34, Heiko Stuebner wrote:
From: Heiko Stuebner
In a loading chain SPL -> ATF (->OP-TEE) -> U-Boot, ATF and a subsequent
OP-TEE will re-use the same fdt as the U-Boot target and may need the
information about usable memory ranges.
Especially OP-TEE needs this to initialize
On 2020/5/13 下午3:15, Frank Wang wrote:
From: Jagan Teki
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.
When use
On 2020/5/10 上午12:56, Jagan Teki wrote:
Enable PCIe/M.2 support on
- NanoPC-T4
- ROC-RK3399-PC Mezzanine boards.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v3:
- none
arch/arm/dts/rk3399-u-boot.dtsi | 1 +
On 2020/5/12 下午6:34, Heiko Stuebner wrote:
From: Heiko Stuebner
Parts of later SPL may need RAM information as well, so do full
dram_init() call, which includes the existing dram probing but also
initializes the ram information in gd.
NAK.
I would prefer to use DM interface and leave the
On 2020/5/13 下午3:15, Frank Wang wrote:
From: Jagan Teki
Add USB TYPEC PHY driver for rockchip platform.
Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
Reviewed-by: Kever
Hi Jagan, Frank,
On 2020/5/13 下午3:15, Frank Wang wrote:
From: Jagan Teki
Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.
I don't understand for this,
On 2020/5/13 下午3:17, Frank Wang wrote:
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
for Rockchip RK3399 Evaluation Board.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3399-evb-u-boot.dtsi | 13
On 2020/5/13 下午3:17, Frank Wang wrote:
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
configs/evb-rk3399_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git
On 2020/5/13 下午3:17, Frank Wang wrote:
We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/usb/host/Kconfig
On 2020/5/13 下午3:17, Frank Wang wrote:
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang
On 2020/5/13 下午3:17, Frank Wang wrote:
From: Jagan Teki
By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).
Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such
On 2020/5/13 下午3:18, Frank Wang wrote:
From: Jagan Teki
Enable USB3.0 Host support for ROC-RK3399-PC boards.
Tested USB3.0 SSD on Type C1 port on board.
=> usb start
starting USB...
Bus usb@fe38: USB EHCI 1.00
Bus usb@fe3c: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Hi Heinrich,
On 2020/5/10 上午3:31, Heinrich Schuchardt wrote:
Building with -Wtype-limits yields
tools/rkcommon.c: In function ‘rkcommon_check_params’:
tools/rkcommon.c:158:27: warning: comparison of
unsigned expression < 0 is always false [-Wtype-limits]
158 | if (spl_params.init_size < 0)
On 2020/5/14 上午3:15, Urja Rannikko wrote:
Apparently speedy was forgotten from this list of veyron devices.
Fixes: 49105fb7ed ("rockchip: add common spl board file")
Signed-off-by: Urja Rannikko
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/spl.c | 3 ++-
1
On 2020/5/14 上午3:15, Urja Rannikko wrote:
Previously veyron_init() was called in board_init() context, which is
called after relocation. Moving it to veyron.c used board_early_init_f
which is called way earlier, and causes veyron_init to hang.
Using board_early_init_r instead fixes this.
On 2020/5/14 上午3:15, Urja Rannikko wrote:
gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang
after f0921f5098 ("fdt: Sync up to the latest libfdt").
We use the same test that is used in spl_common_init on whether to call
fdtdec_setup to unconditionally avoid linking in the
On 2020/5/14 上午3:15, Urja Rannikko wrote:
Veyrons do not need full pinctrl support for SPL.
The full pinctrl support does nothing when enabled with OF_PLATDATA,
thus was already unused.
This frees about 4kB of SPL size.
Signed-off-by: Urja Rannikko
Reviewed-by: Kever Yang
Thanks,
- Kever
On 2020/5/13 下午3:13, Frank Wang wrote:
From: Jagan Teki
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.
assigned-clocks = <
On 2020/5/13 下午3:13, Frank Wang wrote:
From: Jagan Teki
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/clk/rockchip/clk_rk3399.c | 12
1
On 2020/5/13 下午3:13, Frank Wang wrote:
From: Jagan Teki
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
On 2020/5/13 下午3:13, Frank Wang wrote:
From: Jagan Teki
Enable/Disable TCPHY clock for rk3399 platform.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/clk/rockchip/clk_rk3399.c | 24
1 file changed, 24 insertions(+)
diff --git
On 2020/5/10 上午12:56, Jagan Teki wrote:
Yes, it is possible to have a dedicated UCLASS PHY driver
for this Rockchip PCIe PHY but there are some issues on
Generic PHY framework to support the same.
The Generic PHY framework is unable to get the PHY if
the PHY parent is of a different uclass.
On 2020/5/10 上午12:56, Jagan Teki wrote:
Enable/Disable the PCIEPHY clk for rk3399.
CLK is clear in both enable and disable functionality.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes for v3:
- none
drivers/clk/rockchip/clk_rk3399.c | 6 ++
1
On 2020/5/10 上午12:56, Jagan Teki wrote:
Yes, most of the high speed peripheral clocks
in rk3399 enabled by default.
But it would be better to handle them via clk
enable/disable API for handling proper reset
conditions like 'usb reset' over command line.
So, enable USB, GMAC clock via
On 2020/5/10 上午12:56, Jagan Teki wrote:
Due to board limitation some SSD's would work
on rock960 PCIe M.2 only with 1.8V IO domain.
So, this patch enables grf io_sel explicitly to
make PCIe/M.2 to work.
Cc: Tom Cubie
Signed-off-by: Jagan Teki
Acked-by: Manivannan Sadhasivam
Reviewed-by:
Am 2020-05-14 20:35, schrieb Heinrich Schuchardt:
On 5/14/20 2:38 PM, Michael Walle wrote:
The first argument has to be aligned with EFI_PAGE_SIZE. This
alignment
is already checked for external callers but it is not checked for
internal callers. Unfortunately, most of the time the return
Am 2020-05-14 20:27, schrieb Heinrich Schuchardt:
On 5/14/20 2:38 PM, Michael Walle wrote:
Commit 7a82c3051c8f ("efi_loader: Align runtime section to 64kb")
already aligned the memory region to 64kb, but it does not align the
actual efi runtime code. Thus it is likely, that efi_add_memory_map()
On 5/14/20 2:38 PM, Michael Walle wrote:
> The start parameter must be aligned to EFI_PAGE_SIZE.
>
> Fixes: 5a37a2f0140c ("armv8: ls2080a: Declare spin tables as reserved for efi
> loader")
> Signed-off-by: Michael Walle
> ---
> arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +-
> 1 file changed,
On 5/14/20 9:04 PM, Michael Walle wrote:
> Am 2020-05-14 20:27, schrieb Heinrich Schuchardt:
>> On 5/14/20 2:38 PM, Michael Walle wrote:
>>> Commit 7a82c3051c8f ("efi_loader: Align runtime section to 64kb")
>>> already aligned the memory region to 64kb, but it does not align the
>>> actual efi
Use CONFIG_IS_ENABLED to prevent ifdef in sf_probe.c
Cc: Simon Glass
Cc: Vignesh R
Cc: Daniel Schwierzeck
Signed-off-by: Jagan Teki
---
Changes for v2:
- CONFIG_IS_ENABLED() instead of IS_ENABLED()
drivers/mtd/spi/sf_internal.h | 10 ++
drivers/mtd/spi/sf_probe.c| 17
On 5/14/20 2:38 PM, Michael Walle wrote:
> Commit 7a82c3051c8f ("efi_loader: Align runtime section to 64kb")
> already aligned the memory region to 64kb, but it does not align the
> actual efi runtime code. Thus it is likely, that efi_add_memory_map()
> actually adds a larger memory region than
On 5/14/20 2:38 PM, Michael Walle wrote:
> On some architectures, specifically the layerscape, the secondary cores
> wait for an interrupt before entering the spin-tables. This applies only
> to boards which doesn't have PSCI provided by TF-a and u-boot does the
%s/TF-a/TF-A/, %s/u-boot/U-Boot/
čt 14. 5. 2020 v 20:07 odesílatel Rob Herring napsal:
>
> On Thu, Apr 30, 2020 at 6:13 AM Michal Simek wrote:
> >
> > On 29. 04. 20 16:55, Rob Herring wrote:
> > > On Tue, Apr 28, 2020 at 8:51 AM Michal Simek
> > > wrote:
> > >>
> > >> On 28. 04. 20 15:23, Rob Herring wrote:
> > >>> On Wed,
On 5/14/20 2:38 PM, Michael Walle wrote:
> The first argument has to be aligned with EFI_PAGE_SIZE. This alignment
> is already checked for external callers but it is not checked for
> internal callers. Unfortunately, most of the time the return value is
> not checked, so scream loud and clear.
On 14.05.20 20:46, Heinrich Schuchardt wrote:
On 5/14/20 2:38 PM, Michael Walle wrote:
On some architectures, specifically the layerscape, the secondary cores
wait for an interrupt before entering the spin-tables. This applies only
to boards which doesn't have PSCI provided by TF-a and u-boot
Am 2020-05-14 22:17, schrieb Alexander Graf:
On 14.05.20 20:46, Heinrich Schuchardt wrote:
On 5/14/20 2:38 PM, Michael Walle wrote:
On some architectures, specifically the layerscape, the secondary
cores
wait for an interrupt before entering the spin-tables. This applies
only
to boards which
Handling probing code for a particular uclass between
dm vs nodm always confusing and requires additional
ifdefs to handle them properly.
But, having separate low-level code bases for dm and
nodm can make it easy for the command level to use same
function name to probe the devices. This would
Right now, the sf have common driver to handle
both dm and nodm code, where nondm has spi_flash
probe and dm has U_BOOT_DRIVER for dm spi flash.
Having a common code base for dm and nodm with
ifdef make it difficult to extend functionalities
and also difficult to read.
So, keep them separate and
Hi Simon,
-"Simon Glass" schrieb: -
> Betreff: [PATCH v2 05/35] acpi: Support generation of ACPI code
>
> Add a new file to handle generating ACPI code programatically. This is
> used when information must be dynamically added to the tables, e.g. the
> SSDT.
>
> Initial support is just
On 13.05.20 17:03, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.
Signed-off-by: Stefan Roese
---
drivers/sysreset/Kconfig | 7
drivers/sysreset/Makefile | 1 +
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 18 mars 2020 09:25
>
>
> Add a specific command stm32prog for STM32MP soc family witch allows to
> update the devices on the board with the STMicroelectronics tool
> STM32CubeProgrammer (http://www.st.com/STM32CubeProg).
>
> This command use the
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 24 avril 2020 15:48
> To: u-boot@lists.denx.de
> Cc: Lionel DEBIEVE ; Patrick DELAUNAY
> ; Lukasz Majewski ; Patrice
> CHOTARD ; U-Boot STM32 mailman.stormreply.com>
> Subject: [PATCH] clk: stm32mp1: fix CK_MPU calculation
> Importance: High
>
>
Using .set mips3/32/64 without .set push/pop is fragile. This patch
solves this issue by sync'ing the inline-asm functions with the
latest Linux ones.
Signed-off-by: Stefan Roese
---
Changes in v2: None
arch/mips/include/asm/mipsregs.h | 44 +++-
1 file changed, 26
Hi Heiko
> From: Heiko Schocher
> Sent: mardi 12 mai 2020 09:32
>
> Hello tom, Patrick,
>
> Am 12.05.2020 um 08:26 schrieb Heiko Schocher:
> > Hello Tom, Patrick,
> >
> > Am 27.04.2020 um 08:47 schrieb Heiko Schocher:
> >> Hello Tom, Patrick,
> >>
> >> Am 27.04.2020 um 07:16 schrieb Heiko
Hi Matthias,
On Thu, 14 May 2020 at 02:56, Matthias Brugger wrote:
>
>
>
> On 15/04/2020 21:59, Tom Rini wrote:
> > On Tue, Apr 14, 2020 at 08:23:10PM -0600, Simon Glass wrote:
> >> Hi,
> >>
> >> On Sun, 22 Mar 2020 at 21:16, Simon Glass wrote:
> >>>
> >>> At present the pinctrl nodes are not
On 13.05.20 15:16, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
With the introduction of the MIPS Octeon support, lets use the newly
added Kconfig symbol CONFIG_CPU_MIPS64_OCTEON instead of the old Linux
CONFIG_CPU_CAVIUM_OCTEON one (which was never set). Remove these
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 22 avril 2020 14:29
>
>
> It is a V2 for the serie
> http://patchwork.ozlabs.org/project/uboot/list/?series=167872
>
> Rebased on master branch and after the first reviews:
>
> [01/16] arm: stm32mp: update dependency for STM32_ETZPC
> is
Hi,
> From: Patrick DELAUNAY
> Sent: jeudi 30 avril 2020 09:52
>
> Change the mmc displayed name in U-Boot for stm32_sdmmc2 driver to
> “STM32 SD/MMC”.
>
> This stm32_sdmmc2 driver is for version 2 of the ST HW IP SDMMC but the
> displayed name "STM32 SDMMC2" is confusing for user, between the
> -Original Message-
> From: Priyanka Jain (OSS)
> Sent: Tuesday, May 12, 2020 2:57 PM
> To: Chaitanya Sakinam ; u-
> b...@lists.denx.de; joe.hershber...@ni.com
> Cc: bmeng...@gmail.com; Alexandru Marginean
> ; s...@chromium.org; Z.q. Hou
> ; Andy Tang ;
> tommyh...@gmail.com; Anji
Hi Tom,
Please pull the STM32 related fixes for v2020.07-rc3 = u-boot-stm32-20200514
With the following changes:
- stm32mp1: migrate MTD and DFU configuration in Kconfig
- stm32mp1: add command stm32prog
- stm32mp1: several board and arch updates
- stm32mp1: activate data cache in SPL
Signed-off-by: Christian Gmeiner
---
arch/x86/cpu/coreboot/tables.c | 14 ++
arch/x86/include/asm/arch-coreboot/sysinfo.h | 2 ++
arch/x86/include/asm/coreboot_tables.h | 11 +++
3 files changed, 27 insertions(+)
diff --git
UCLASS_SPI_FLASH driver at driver/mtd/spi is a generic
spi flash driver to probe jedec,spi-nor flash chips.
Technically a probe call in U_BOOT_DRIVER is local to that
driver and not applicable to use it another driver or in
another code.
The apollolake SPL code using the generic probe by adding
On 5/14/20 2:30 PM, Tom Rini wrote:
> Unless we mark the function as 'static inline' it may end up being
> non-inlined by the compiled and result in duplicate functions.
>
> Cc: Marek Vasut
> Cc: Simon Goldschmidt
> Cc: Ley Foon Tan
> Signed-off-by: Tom Rini
Acked-by: Marek Vasut
On 5/14/20 2:30 PM, Tom Rini wrote:
> Enable the new CONFIG_OPTIMIZE_INLINING and CONFIG_SPL_OPTIMIZE_INLINING
> options for this platform. With gcc-9.2 from kernel.org this saves us
> 1784 bytes in U-Boot and 80 bytes in SPL.
>
> Cc: Marek Vasut
> Cc: Chin-Liang See
> Cc: Dinh Nguyen
>
Hi Patrick
On 5/14/20 3:00 PM, Patrick Delaunay wrote:
> Update the compatible associated with the STM32 MPU glue
> in the DWC ethernet driver.
>
> The supported compatible is the specific "st,stm32mp1-dwmac"
> as indicated in Linux binding
> Documentation/devicetree/bindings/net/stm32-dwmac.txt
Add linefeeds before and after the announce string. This makes the
output easier to read, especially if some text follows the announce
message without a specific additional CR.
Signed-off-by: Stefan Roese
---
include/debug_uart.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi Daniel,
On 14.05.20 18:31, Daniel Schwierzeck wrote:
Am 14.05.20 um 14:11 schrieb Jagan Teki:
Use IS_ENABLED to prevent ifdef in sf_probe.c
Cc: Simon Glass
Cc: Vignesh R
Cc: Daniel Schwierzeck
Signed-off-by: Jagan Teki
---
drivers/mtd/spi/sf_internal.h | 10 ++
Hi Heinrich,
On Fri, May 15, 2020 at 5:27 AM Heinrich Schuchardt wrote:
>
> On 5/13/20 5:27 PM, Rayagonda Kokatanur wrote:
> > From: Corneliu Doban
> >
> > Add eMMC and GPT support.
> > - GPT partition list and command to create the GPT added to u-boot
> > environment
> > - eMMC boot commands
On 15/04/2020 21:59, Tom Rini wrote:
> On Tue, Apr 14, 2020 at 08:23:10PM -0600, Simon Glass wrote:
>> Hi,
>>
>> On Sun, 22 Mar 2020 at 21:16, Simon Glass wrote:
>>>
>>> At present the pinctrl nodes are not enabled in pre-relocation U-Boot so
>>> the UARTs do not correctly select the pinconfig
Hi,
> From: Marek Vasut
> Sent: lundi 27 avril 2020 13:16
>
> The commit 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and
> AV96 board") was not applied correctly and in full, and omitted an important
> split
> of the SoM into 3V3 and 1V8 options. The Avenger96 board is based on
Hi,
> From: Patrick DELAUNAY
> Sent: jeudi 30 avril 2020 15:53
> To: u-boot@lists.denx.de
> Cc: Patrick DELAUNAY ; Marek Vasut
> ; Tom Rini ; U-Boot STM32 st...@st-md-mailman.stormreply.com>
> Subject: [PATCH] ARM: dts: stm32mp1: DT alignment with Linux 5.7-rc2
> Importance: High
>
> DT
From: Aaron Williams
This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.
Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches
later. To still use
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with this
port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot
to the prompt on
This patch adds the base dtsi file for the Octeon 3 cn73xx SoC.
Signed-off-by: Stefan Roese
---
Changes in v2: None
MAINTAINERS| 1 +
arch/mips/dts/mrvl,cn73xx.dtsi | 64 ++
2 files changed, 65 insertions(+)
create mode 100644
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.
Signed-off-by: Stefan Roese
---
Changes in v2: None
drivers/sysreset/Kconfig | 7
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_octeon.c | 52 ++
3
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
the exception base register.
Signed-off-by: Stefan Roese
---
Changes in v2:
- Move bit macro definition to mipsregs.h
arch/mips/include/asm/mipsregs.h | 1 +
arch/mips/lib/traps.c| 4
2 files changed, 5
Since Octeon now runs from L2 cache, we can't reset the cache at this
time. So let's opt-out this function on Octeon, as the cache is
coherent on Octeon anyways.
Signed-off-by: Stefan Roese
---
Changes in v2:
- New patch
arch/mips/cpu/start.S | 2 ++
1 file changed, 2 insertions(+)
diff
Hi Tom,
Please have a look at the updates for RPi below.
I know I'm a bit late in the cycle. I'll try to send my pull requests earlier
next time, sorry for that.
I just pushed the tag, so the CI is not green yet:
https://travis-ci.org/github/mbgg/u-boot/builds/686914330
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 18 mars 2020 09:23
>
>
> This serie migrate the dynamically build MTD
> (CONFIG_SYS_MTDPARTS_RUNTIME) and the DFU configuration
> (CONFIG_SET_DFU_ALT_INFO) previously based on ENV variables to
> CONFIG_.
>
> These patches reduce the size of the
Hi Simon,
On 29.04.20 20:04, Simon Glass wrote:
On Wed, 29 Apr 2020 at 01:08, Stefan Roese wrote:
Including the assembler headers before including common.h etc leads to
compilation errors upon MIPS64 based platforms using OF_LIVE. This
patch reorders the include files to the "correct" oder.
Hi Marek,
> From: Marek Vasut
> Sent: mercredi 29 avril 2020 15:09
>
> Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put
> them into use by the board file instead of the default ones. These new DRAM
> settings are a better fit for the SoMs.
>
> Signed-off-by: Marek Vasut
> Cc:
This Kconfig symbol will be introduced with the base Octeon MIPS support.
Using it, its possible to use a TEXT_BASE address which differs from
the reset PC. And with the earliest function call to mips_sram_init()
the CPU will transfer execution to the actual TEXT_BASE region. So after
returning
Simon,
On 05/05/20 12:20 pm, Faiz Abbas wrote:
> Hi,
>
> On 04/05/20 6:44 pm, Simon Glass wrote:
>> Hi Bart,
>>
>> On Mon, 4 May 2020 at 01:10, Bartosz Golaszewski wrote:
>>>
>>> pt., 1 maj 2020 o 20:32 Tom Rini napisał(a):
On Thu, Apr 30, 2020 at 01:43:30PM +0200, Bartosz
On 13.05.20 16:47, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with
On 14.05.20 01:43, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
From: Aaron Williams
This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.
Please note that the basic Octeon port does not include the
Hi Patrice
> From: Patrice CHOTARD
> Sent: jeudi 30 avril 2020 18:41
>
> On DK1/2 board, when a 1.5A power supply is detected, a warning message is
> displayed. In this message, "1.5mA" is displayed instead of "1.5A".
>
> Signed-off-by: Patrice Chotard
> ---
>
> board/st/stm32mp1/stm32mp1.c
Hi,
> From: Marek Vasut
> Sent: lundi 27 avril 2020 12:27
>
> Define I2C EEPROM bus and address, so that the 'eeprom' command uses the
> correct ones and does not generate the following error:
> eeprom_rw_block: Cannot find udev for a bus 0
>
> Signed-off-by: Marek Vasut
> Cc: Patrick
This patch adds very basic support for the Octeon III SoCs. Only CFI
parallel UART, reset and NOR flash are supported for now.
Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches later.
To still use U-Boot on with
1 - 100 of 181 matches
Mail list logo
