Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
On 4/13/21 12:12 AM, Rick Chen wrote: Hi Sean On 4/12/21 10:39 PM, Rick Chen wrote: Hi Green, From: Green Wan [mailto:green@sifive.com] Sent: Monday, April 12, 2021 10:33 AM To: Sean Anderson Cc: Rick Chen; Rick Jian-Zhi Chen(陳建志); Bin Meng; U-Boot Mailing List; Paul Walmsley; Pragnesh Patel; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad Kim Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core Hi Bin and Sean, While we keep the consistency of cache control discussion going, later today I'd like to send the v5 patch which is not directly relevant to cache control. I will prefer not to mix cache control issue into this patch. Like I said, this callback is a init for all harts before lottery. Yes, but enabling caches is a very similar thing (this proposal even uses it to turn on caches, among other things). At the moment we have two calls to enable caches at almost the same time as what Green proposes. These calls only translate into work done on one platform. I think having one call (or perhaps two) for this purpose would help reduce codepaths across different platforms going forward. Maybe we can add two callbacks (early_lottery_init and late_lottery_init) before and after lottery individually for all scenarios. Yes, that is a possibility. But do we actually need that flexibility? This comes back around to my original question: why does ax25 disable cache on all harts before jumping to Linux? And of course, does this actually need to be done before the lottery? --Sean
Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
Hi Sean
> On 4/12/21 10:39 PM, Rick Chen wrote:
> > Hi Green,
> >
> >> From: Green Wan [mailto:green@sifive.com]
> >> Sent: Monday, April 12, 2021 10:33 AM
> >> To: Sean Anderson
> >> Cc: Rick Chen; Rick Jian-Zhi Chen(陳建志); Bin Meng; U-Boot Mailing List;
> >> Paul Walmsley; Pragnesh Patel; Simon Glass; Atish Patra; Leo Yu-Chi
> >> Liang(梁育齊); Brad Kim
> >> Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init
> >> each core
> >>
> >> Hi Bin and Sean,
> >>
> >> While we keep the consistency of cache control discussion going, later
> >> today I'd like to send the v5 patch which is not directly relevant to
> >> cache control.
> >
> > I will prefer not to mix cache control issue into this patch.
> > Like I said, this callback is a init for all harts before lottery.
>
> Yes, but enabling caches is a very similar thing (this proposal even
> uses it to turn on caches, among other things). At the moment we have
> two calls to enable caches at almost the same time as what Green
> proposes. These calls only translate into work done on one platform. I
> think having one call (or perhaps two) for this purpose would help
> reduce codepaths across different platforms going forward.
>
Maybe we can add two callbacks (early_lottery_init and
late_lottery_init) before and after lottery individually for all
scenarios.
Thanks,
Rick
> --Sean
>
> >
> > Thanks,
> > Rick
> >
> >>
> >> Regards,
> >> Green
> >>
> >> On Sun, Apr 11, 2021 at 11:43 PM Sean Anderson wrote:
> >>>
> >>> On 4/9/21 12:05 PM, Green Wan wrote:
> Hi folks,
>
> Correct me if I'm wrong, like Rick mentioned, i/dcache
> enable/disable() is only called on the main hart. Right now the dummy
> i/dcache enable/disable are empty and shared among all riscv CPU. The
> ax25 is the only one that has its own implementation for now.
> >>>
> >>> Right, so why are caches are disabled on all harts before booting Linux
> >>> on ax25? Is there a requirement for this on ax25 which that other
> >>> platforms (which have always-on caches like k210, or which have
> >>> non-disableable caches like fuX40) do not have?
> >>>
> >>> --Sean
> >>>
>
> FU540/FU740 also leverages the dummy i/dcache enable/disable()
> functions (only main hart calls them). L2 cache on FU540/FU740 is
> enabled as SRAM purpose. And according to the HW design behavior, once
> L2 is enabled, it can't be disabled unless doing a reset.[1] The Linux
> L2$ driver will handle that according to the configuration of L2
> registers.
>
> [1] https://static.dev.sifive.com/FU540-C000-v1.0.pdf
>
> Thanks,
>
> On Fri, Apr 9, 2021 at 9:18 PM Sean Anderson wrote:
> >
> > On 4/9/21 4:16 AM, Rick Chen wrote:
> >> Hi Sean ,Bin
> >>
> >>> From: Bin Meng [mailto:bmeng...@gmail.com]
> >>> Sent: Tuesday, April 06, 2021 5:16 PM
> >>> To: Sean Anderson
> >>> Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh
> >>> Patel; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊);
> >>> Brad Kim; U-Boot Mailing List
> >>> Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to
> >>> init each core
> >>>
> >>> On Sat, Apr 3, 2021 at 6:53 AM Sean Anderson
> >>> wrote:
>
> On 3/30/21 1:26 AM, Green Wan wrote:
> > Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S
> > to
> > allow different riscv hart perform setup code for each hart as early
> > as possible. Since all the harts enter the callback, they must be
> > able
> > to run the same setup.
> >
> > Signed-off-by: Green Wan
> > ---
> > arch/riscv/cpu/cpu.c | 15 +++
> > arch/riscv/cpu/start.S | 14 ++
> > 2 files changed, 29 insertions(+)
> >
> > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > index 85592f5bee..1652e51137 100644
> > --- a/arch/riscv/cpu/cpu.c
> > +++ b/arch/riscv/cpu/cpu.c
> > @@ -140,3 +140,18 @@ int arch_early_init_r(void)
> > {
> > return riscv_cpu_probe();
> > }
> > +
> > +/**
> > + * riscv_hart_early_init() - A dummy function called by
> > + * ./arch/riscv/cpu/start.S to allow to disable/enable features of
> > each core.
> > + * For example, turn on or off the functional block of CPU harts.
> > + *
> > + * In a multi-core system, this function must not access shared
> > resources.
> > + *
> > + * Any access to such resources would probably be better done with
> > + * available_harts_lock held. However, I doubt that any such
> > access will be
> > + * necessary.
> > + */
> > +__weak void riscv_hart_early_init(void)
> > +{
> > +}
> >
Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
Hi Green,
> From: Green Wan [mailto:green@sifive.com]
> Sent: Tuesday, March 30, 2021 1:27 PM
> Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel; Sean
> Anderson; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad
> Kim; u-boot@lists.denx.de
> Subject: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
>
> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
> allow different riscv hart perform setup code for each hart as early
> as possible. Since all the harts enter the callback, they must be able
> to run the same setup.
>
> Signed-off-by: Green Wan
> ---
> arch/riscv/cpu/cpu.c | 15 +++
> arch/riscv/cpu/start.S | 14 ++
> 2 files changed, 29 insertions(+)
>
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index 85592f5bee..1652e51137 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -140,3 +140,18 @@ int arch_early_init_r(void)
> {
> return riscv_cpu_probe();
> }
> +
> +/**
> + * riscv_hart_early_init() - A dummy function called by
Maybe you can rename as harts_early_init(), riscv seems to be extra prefix here.
And dummy sounds like a negative word, it will be better to describe
it as a callback for customize CSR features ...etc.
> + * ./arch/riscv/cpu/start.S to allow to disable/enable features of each core.
> + * For example, turn on or off the functional block of CPU harts.
> + *
> + * In a multi-core system, this function must not access shared resources.
> + *
> + * Any access to such resources would probably be better done with
> + * available_harts_lock held. However, I doubt that any such access will be
> + * necessary.
> + */
> +__weak void riscv_hart_early_init(void)
> +{
> +}
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index 8589509e01..ab73008f23 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -117,6 +117,20 @@ call_board_init_f_0:
> mv sp, a0
> #endif
>
> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
> + /*
> +* Jump to riscv_hart_early_init() to perform init for each core. Not
> +* expect to access gd since gd is not initialized. All operations in
> the
> +* function should affect core itself only. In multi-core system, any
> access
> +* to common resource or registers outside core should be avoided or
> need a
> +* protection for multicore.
You can emphasize this init is a callback for customize CSR settings
for all harts simply.
Any memory access is prohibited here.
> +*
> +* A dummy implementation is provided in ./arch/riscv/cpu/cpu.c.
This description for path is not necessary here.
Thanks,
Rick
> +*/
> +call_riscv_hart_early_init:
> + jal riscv_hart_early_init
> +#endif
> +
> #ifndef CONFIG_XIP
> /*
> * Pick hart to initialize global data and run U-Boot. The other harts
> --
> 2.31.0
Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
On 4/12/21 10:39 PM, Rick Chen wrote:
Hi Green,
From: Green Wan [mailto:green@sifive.com]
Sent: Monday, April 12, 2021 10:33 AM
To: Sean Anderson
Cc: Rick Chen; Rick Jian-Zhi Chen(陳建志); Bin Meng; U-Boot Mailing List; Paul
Walmsley; Pragnesh Patel; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad
Kim
Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
Hi Bin and Sean,
While we keep the consistency of cache control discussion going, later
today I'd like to send the v5 patch which is not directly relevant to
cache control.
I will prefer not to mix cache control issue into this patch.
Like I said, this callback is a init for all harts before lottery.
Yes, but enabling caches is a very similar thing (this proposal even
uses it to turn on caches, among other things). At the moment we have
two calls to enable caches at almost the same time as what Green
proposes. These calls only translate into work done on one platform. I
think having one call (or perhaps two) for this purpose would help
reduce codepaths across different platforms going forward.
--Sean
Thanks,
Rick
Regards,
Green
On Sun, Apr 11, 2021 at 11:43 PM Sean Anderson wrote:
On 4/9/21 12:05 PM, Green Wan wrote:
Hi folks,
Correct me if I'm wrong, like Rick mentioned, i/dcache
enable/disable() is only called on the main hart. Right now the dummy
i/dcache enable/disable are empty and shared among all riscv CPU. The
ax25 is the only one that has its own implementation for now.
Right, so why are caches are disabled on all harts before booting Linux
on ax25? Is there a requirement for this on ax25 which that other
platforms (which have always-on caches like k210, or which have
non-disableable caches like fuX40) do not have?
--Sean
FU540/FU740 also leverages the dummy i/dcache enable/disable()
functions (only main hart calls them). L2 cache on FU540/FU740 is
enabled as SRAM purpose. And according to the HW design behavior, once
L2 is enabled, it can't be disabled unless doing a reset.[1] The Linux
L2$ driver will handle that according to the configuration of L2
registers.
[1] https://static.dev.sifive.com/FU540-C000-v1.0.pdf
Thanks,
On Fri, Apr 9, 2021 at 9:18 PM Sean Anderson wrote:
On 4/9/21 4:16 AM, Rick Chen wrote:
Hi Sean ,Bin
From: Bin Meng [mailto:bmeng...@gmail.com]
Sent: Tuesday, April 06, 2021 5:16 PM
To: Sean Anderson
Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel; Bin
Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad Kim; U-Boot Mailing
List
Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
On Sat, Apr 3, 2021 at 6:53 AM Sean Anderson wrote:
On 3/30/21 1:26 AM, Green Wan wrote:
Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
allow different riscv hart perform setup code for each hart as early
as possible. Since all the harts enter the callback, they must be able
to run the same setup.
Signed-off-by: Green Wan
---
arch/riscv/cpu/cpu.c | 15 +++
arch/riscv/cpu/start.S | 14 ++
2 files changed, 29 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 85592f5bee..1652e51137 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -140,3 +140,18 @@ int arch_early_init_r(void)
{
return riscv_cpu_probe();
}
+
+/**
+ * riscv_hart_early_init() - A dummy function called by
+ * ./arch/riscv/cpu/start.S to allow to disable/enable features of each core.
+ * For example, turn on or off the functional block of CPU harts.
+ *
+ * In a multi-core system, this function must not access shared resources.
+ *
+ * Any access to such resources would probably be better done with
+ * available_harts_lock held. However, I doubt that any such access will be
+ * necessary.
+ */
+__weak void riscv_hart_early_init(void)
+{
+}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8589509e01..ab73008f23 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -117,6 +117,20 @@ call_board_init_f_0:
mv sp, a0
#endif
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ /*
+ * Jump to riscv_hart_early_init() to perform init for each core. Not
+ * expect to access gd since gd is not initialized. All operations in the
+ * function should affect core itself only. In multi-core system, any
access
+ * to common resource or registers outside core should be avoided or need
a
+ * protection for multicore.
+ *
+ * A dummy implementation is provided in ./arch/riscv/cpu/cpu.c.
+ */
+call_riscv_hart_early_init:
+ jal riscv_hart_early_init
+#endif
+
I wonder if we could move the calls to icache_enable and dcache_enable
into this function. Though this would have the consequence of enabling
caches on all harts for CPUs which previously only enabled them for the
boot hart. I think ax25 is the only CPU which currently does this. Bin,
would this be an issue?
Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
On Tue, Apr 13, 2021 at 10:39 AM Rick Chen wrote:
>
> Hi Green,
>
> > From: Green Wan [mailto:green@sifive.com]
> > Sent: Monday, April 12, 2021 10:33 AM
> > To: Sean Anderson
> > Cc: Rick Chen; Rick Jian-Zhi Chen(陳建志); Bin Meng; U-Boot Mailing List; Paul
> > Walmsley; Pragnesh Patel; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊);
> > Brad Kim
> > Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each
> > core
> >
> > Hi Bin and Sean,
> >
> > While we keep the consistency of cache control discussion going, later
> > today I'd like to send the v5 patch which is not directly relevant to
> > cache control.
>
> I will prefer not to mix cache control issue into this patch.
> Like I said, this callback is a init for all harts before lottery.
>
> Thanks,
> Rick
Agree with you.
- Green
>
> >
> > Regards,
> > Green
> >
> > On Sun, Apr 11, 2021 at 11:43 PM Sean Anderson wrote:
> > >
> > > On 4/9/21 12:05 PM, Green Wan wrote:
> > > > Hi folks,
> > > >
> > > > Correct me if I'm wrong, like Rick mentioned, i/dcache
> > > > enable/disable() is only called on the main hart. Right now the dummy
> > > > i/dcache enable/disable are empty and shared among all riscv CPU. The
> > > > ax25 is the only one that has its own implementation for now.
> > >
> > > Right, so why are caches are disabled on all harts before booting Linux
> > > on ax25? Is there a requirement for this on ax25 which that other
> > > platforms (which have always-on caches like k210, or which have
> > > non-disableable caches like fuX40) do not have?
> > >
> > > --Sean
> > >
> > > >
> > > > FU540/FU740 also leverages the dummy i/dcache enable/disable()
> > > > functions (only main hart calls them). L2 cache on FU540/FU740 is
> > > > enabled as SRAM purpose. And according to the HW design behavior, once
> > > > L2 is enabled, it can't be disabled unless doing a reset.[1] The Linux
> > > > L2$ driver will handle that according to the configuration of L2
> > > > registers.
> > > >
> > > > [1] https://static.dev.sifive.com/FU540-C000-v1.0.pdf
> > > >
> > > > Thanks,
> > > >
> > > > On Fri, Apr 9, 2021 at 9:18 PM Sean Anderson wrote:
> > > >>
> > > >> On 4/9/21 4:16 AM, Rick Chen wrote:
> > > >>> Hi Sean ,Bin
> > > >>>
> > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > Sent: Tuesday, April 06, 2021 5:16 PM
> > > To: Sean Anderson
> > > Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh
> > > Patel; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊);
> > > Brad Kim; U-Boot Mailing List
> > > Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to
> > > init each core
> > >
> > > On Sat, Apr 3, 2021 at 6:53 AM Sean Anderson
> > > wrote:
> > > >
> > > > On 3/30/21 1:26 AM, Green Wan wrote:
> > > >> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S
> > > >> to
> > > >> allow different riscv hart perform setup code for each hart as
> > > >> early
> > > >> as possible. Since all the harts enter the callback, they must be
> > > >> able
> > > >> to run the same setup.
> > > >>
> > > >> Signed-off-by: Green Wan
> > > >> ---
> > > >> arch/riscv/cpu/cpu.c | 15 +++
> > > >> arch/riscv/cpu/start.S | 14 ++
> > > >> 2 files changed, 29 insertions(+)
> > > >>
> > > >> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > > >> index 85592f5bee..1652e51137 100644
> > > >> --- a/arch/riscv/cpu/cpu.c
> > > >> +++ b/arch/riscv/cpu/cpu.c
> > > >> @@ -140,3 +140,18 @@ int arch_early_init_r(void)
> > > >> {
> > > >> return riscv_cpu_probe();
> > > >> }
> > > >> +
> > > >> +/**
> > > >> + * riscv_hart_early_init() - A dummy function called by
> > > >> + * ./arch/riscv/cpu/start.S to allow to disable/enable features
> > > >> of each core.
> > > >> + * For example, turn on or off the functional block of CPU harts.
> > > >> + *
> > > >> + * In a multi-core system, this function must not access shared
> > > >> resources.
> > > >> + *
> > > >> + * Any access to such resources would probably be better done with
> > > >> + * available_harts_lock held. However, I doubt that any such
> > > >> access will be
> > > >> + * necessary.
> > > >> + */
> > > >> +__weak void riscv_hart_early_init(void)
> > > >> +{
> > > >> +}
> > > >> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> > > >> index 8589509e01..ab73008f23 100644
> > > >> --- a/arch/riscv/cpu/start.S
> > > >> +++ b/arch/riscv/cpu/start.S
> > > >> @@ -117,6 +117,20 @@ call_board_init_f_0:
> > > >> mv sp, a0
> > > >> #endif
> > > >>
> > > >> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
> > > >> + /*
> > > >> + * Jump to riscv_hart_early_init() to perform init for each
> > > >> core. Not
> >
Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
Hi Green,
> From: Green Wan [mailto:green@sifive.com]
> Sent: Monday, April 12, 2021 10:33 AM
> To: Sean Anderson
> Cc: Rick Chen; Rick Jian-Zhi Chen(陳建志); Bin Meng; U-Boot Mailing List; Paul
> Walmsley; Pragnesh Patel; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊);
> Brad Kim
> Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each
> core
>
> Hi Bin and Sean,
>
> While we keep the consistency of cache control discussion going, later
> today I'd like to send the v5 patch which is not directly relevant to
> cache control.
I will prefer not to mix cache control issue into this patch.
Like I said, this callback is a init for all harts before lottery.
Thanks,
Rick
>
> Regards,
> Green
>
> On Sun, Apr 11, 2021 at 11:43 PM Sean Anderson wrote:
> >
> > On 4/9/21 12:05 PM, Green Wan wrote:
> > > Hi folks,
> > >
> > > Correct me if I'm wrong, like Rick mentioned, i/dcache
> > > enable/disable() is only called on the main hart. Right now the dummy
> > > i/dcache enable/disable are empty and shared among all riscv CPU. The
> > > ax25 is the only one that has its own implementation for now.
> >
> > Right, so why are caches are disabled on all harts before booting Linux
> > on ax25? Is there a requirement for this on ax25 which that other
> > platforms (which have always-on caches like k210, or which have
> > non-disableable caches like fuX40) do not have?
> >
> > --Sean
> >
> > >
> > > FU540/FU740 also leverages the dummy i/dcache enable/disable()
> > > functions (only main hart calls them). L2 cache on FU540/FU740 is
> > > enabled as SRAM purpose. And according to the HW design behavior, once
> > > L2 is enabled, it can't be disabled unless doing a reset.[1] The Linux
> > > L2$ driver will handle that according to the configuration of L2
> > > registers.
> > >
> > > [1] https://static.dev.sifive.com/FU540-C000-v1.0.pdf
> > >
> > > Thanks,
> > >
> > > On Fri, Apr 9, 2021 at 9:18 PM Sean Anderson wrote:
> > >>
> > >> On 4/9/21 4:16 AM, Rick Chen wrote:
> > >>> Hi Sean ,Bin
> > >>>
> > From: Bin Meng [mailto:bmeng...@gmail.com]
> > Sent: Tuesday, April 06, 2021 5:16 PM
> > To: Sean Anderson
> > Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel;
> > Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad Kim;
> > U-Boot Mailing List
> > Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init
> > each core
> >
> > On Sat, Apr 3, 2021 at 6:53 AM Sean Anderson wrote:
> > >
> > > On 3/30/21 1:26 AM, Green Wan wrote:
> > >> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
> > >> allow different riscv hart perform setup code for each hart as early
> > >> as possible. Since all the harts enter the callback, they must be
> > >> able
> > >> to run the same setup.
> > >>
> > >> Signed-off-by: Green Wan
> > >> ---
> > >> arch/riscv/cpu/cpu.c | 15 +++
> > >> arch/riscv/cpu/start.S | 14 ++
> > >> 2 files changed, 29 insertions(+)
> > >>
> > >> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > >> index 85592f5bee..1652e51137 100644
> > >> --- a/arch/riscv/cpu/cpu.c
> > >> +++ b/arch/riscv/cpu/cpu.c
> > >> @@ -140,3 +140,18 @@ int arch_early_init_r(void)
> > >> {
> > >> return riscv_cpu_probe();
> > >> }
> > >> +
> > >> +/**
> > >> + * riscv_hart_early_init() - A dummy function called by
> > >> + * ./arch/riscv/cpu/start.S to allow to disable/enable features of
> > >> each core.
> > >> + * For example, turn on or off the functional block of CPU harts.
> > >> + *
> > >> + * In a multi-core system, this function must not access shared
> > >> resources.
> > >> + *
> > >> + * Any access to such resources would probably be better done with
> > >> + * available_harts_lock held. However, I doubt that any such access
> > >> will be
> > >> + * necessary.
> > >> + */
> > >> +__weak void riscv_hart_early_init(void)
> > >> +{
> > >> +}
> > >> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> > >> index 8589509e01..ab73008f23 100644
> > >> --- a/arch/riscv/cpu/start.S
> > >> +++ b/arch/riscv/cpu/start.S
> > >> @@ -117,6 +117,20 @@ call_board_init_f_0:
> > >> mv sp, a0
> > >> #endif
> > >>
> > >> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
> > >> + /*
> > >> + * Jump to riscv_hart_early_init() to perform init for each
> > >> core. Not
> > >> + * expect to access gd since gd is not initialized. All
> > >> operations in the
> > >> + * function should affect core itself only. In multi-core
> > >> system, any access
> > >> + * to common resource or registers outside core should be
> > >> avoided or need a
> > >> + * protection for multicore.
> >
Re: [PATCH 2/3] fit: Use hash.c to call SHA code
On Wed, Feb 17, 2021 at 01:50:41PM +1030, Joel Stanley wrote: > Currently the FIT hashing will call directly into the SHA algorithms to > get a hash. > > This moves the fit code to use hash_lookup_algo, giving a common > entrypoint into the hashing code and removing the duplicated algorithm > look up. It also allows the use of hardware acceleration if configured. > > Signed-off-by: Joel Stanley This breaks a few boards: ls1046ardb_qspi_spl imx8mm_beacon imx8mn_beacon imx8mn_beacon_2g imx8mm_evk imx8mn_ddr4_evk imx8mn_evk imx8mp_evk imx8mq_evk imx8mm_venice imx8mq_phanbell phycore-imx8mm phycore-imx8mp pico-imx8mq verdin-imx8mm mt8183_pumpkin mt8516_pumpkin that use FIT images, in SPL, but don't actually check hashes apparently. Just including hash.o for the hash-lookup function fails because we don't have crc16, etc, enabled and also I think need: https://patchwork.ozlabs.org/project/uboot/patch/2021032211.1646575-1-mr.nuke...@gmail.com/ for consistent symbol naming. So, I like this patch in concept, but I think it'll need to be reworked a bit, after I pull in some other changes soon. Thanks! -- Tom signature.asc Description: PGP signature
[PATCH 1/5] lib: add crypt subsystem
Add the basic functionality required to support the standard crypt format. The files crypt-sha256.c and crypt-sha512.c originate from libxcrypt and their formatting is therefor retained. The integration is done via a crypt_compare() function in crypt.c. ``` libxcrypt $ git describe --long --always --all tags/v4.4.17-0-g6b110bc ``` Signed-off-by: Steffen Jaeckel --- include/crypt.h | 13 ++ lib/Kconfig | 1 + lib/Makefile | 1 + lib/crypt/Kconfig| 29 lib/crypt/Makefile | 10 ++ lib/crypt/alg-sha256.h | 17 ++ lib/crypt/alg-sha512.h | 17 ++ lib/crypt/crypt-port.h | 28 lib/crypt/crypt-sha256.c | 313 + lib/crypt/crypt-sha512.c | 328 +++ lib/crypt/crypt.c| 73 + 11 files changed, 830 insertions(+) create mode 100644 include/crypt.h create mode 100644 lib/crypt/Kconfig create mode 100644 lib/crypt/Makefile create mode 100644 lib/crypt/alg-sha256.h create mode 100644 lib/crypt/alg-sha512.h create mode 100644 lib/crypt/crypt-port.h create mode 100644 lib/crypt/crypt-sha256.c create mode 100644 lib/crypt/crypt-sha512.c create mode 100644 lib/crypt/crypt.c diff --git a/include/crypt.h b/include/crypt.h new file mode 100644 index 00..e0be2832ff --- /dev/null +++ b/include/crypt.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (C) 2020 Steffen Jaeckel */ + +/** + * Compare should with the processed passphrase. + * + * @should The crypt-style string to compare against + * @passphrase The plaintext passphrase + * @equal Pointer to an int where the result is stored + * '0' = unequal + * '1' = equal + */ +void crypt_compare(const char *should, const char *passphrase, int *equal); diff --git a/lib/Kconfig b/lib/Kconfig index 80ff2443cb..99a4e1a5a7 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -297,6 +297,7 @@ config AES source lib/rsa/Kconfig source lib/crypto/Kconfig +source lib/crypt/Kconfig config TPM bool "Trusted Platform Module (TPM) Support" diff --git a/lib/Makefile b/lib/Makefile index c42d4e1233..ab78f32eb1 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_$(SPL_)RSA) += rsa/ obj-$(CONFIG_SHA1) += sha1.o obj-$(CONFIG_SHA256) += sha256.o obj-$(CONFIG_SHA512_ALGO) += sha512.o +obj-$(CONFIG_CRYPT_PW) += crypt/ obj-$(CONFIG_$(SPL_)ZLIB) += zlib/ obj-$(CONFIG_$(SPL_)ZSTD) += zstd/ diff --git a/lib/crypt/Kconfig b/lib/crypt/Kconfig new file mode 100644 index 00..6f828cefd6 --- /dev/null +++ b/lib/crypt/Kconfig @@ -0,0 +1,29 @@ +config CRYPT_PW + bool "Add crypt support for password-based unlock" + help + Enable support for crypt-style hashed passphrases. + This will then be used as the mechanism of choice to + verify whether the entered password to unlock the + console is correct or not. + To make it fully functional, one has also to enable + CONFIG_AUTOBOOT_KEYED and CONFIG_AUTOBOOT_ENCRYPTION + +if CRYPT_PW + +config CRYPT_PW_SHA256 + bool "Provide sha256crypt" + select SHA256 + select SHA256_ALGO + help + Enables support for the sha256crypt password-hashing algorithm. + The prefix is "$5$". + +config CRYPT_PW_SHA512 + bool "Provide sha512crypt" + select SHA512 + select SHA512_ALGO + help + Enables support for the sha512crypt password-hashing algorithm. + The prefix is "$6$". + +endif diff --git a/lib/crypt/Makefile b/lib/crypt/Makefile new file mode 100644 index 00..290231064c --- /dev/null +++ b/lib/crypt/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2013, Google Inc. +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. + +obj-$(CONFIG_CRYPT_PW) += crypt.o +obj-$(CONFIG_CRYPT_PW_SHA256) += crypt-sha256.o +obj-$(CONFIG_CRYPT_PW_SHA512) += crypt-sha512.o diff --git a/lib/crypt/alg-sha256.h b/lib/crypt/alg-sha256.h new file mode 100644 index 00..e4b29c9f31 --- /dev/null +++ b/lib/crypt/alg-sha256.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (C) 2020 Steffen Jaeckel */ + +#ifndef USE_HOSTCC +#include "common.h" +#else +#include +#endif + +#include "u-boot/sha256.h" + +#define INCLUDE_sha256crypt 1 + +#define SHA256_CTX sha256_context +#define SHA256_Init sha256_starts +#define SHA256_Update(c, i, l) sha256_update(c, (const void *)i, l) +#define SHA256_Final(b, c) sha256_finish(c, b) diff --git a/lib/crypt/alg-sha512.h b/lib/crypt/alg-sha512.h new file mode 100644 index 00..93b6109fae --- /dev/null +++ b/lib/crypt/alg-sha512.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (C) 2020 Steffen Jaeckel */ + +#ifndef USE_HOSTCC +#include "common.h" +#else +#include +#endif + +#include "u-boot/sha512.h" + +#define
[PATCH 0/5] common: Introduce crypt-style password support
This patchset introduces support for crypt-style passwords to unlock the console in autoboot mode. The implementation of crypt-sha256 and crypt-sha512 originate from libxcrypt at https://github.com/besser82/libxcrypt.git Version v4.4.17 Git commit hash 6b110bc I didn't re-format those two files to make diffing to the original versions from libxcrypt easier, which leads to a huge load of checkpatch.pl warnings Please advise on whether they should be re-formatted or can be kept as is. The remaining warnings from checkpatch.pl are intentional resp. open for discussion. Cheers, Steffen Steffen Jaeckel (5): lib: add crypt subsystem common: integrate crypt-based passwords common: Rename macro appropriately cmd: allow disabling of timeout for password entry configs: add new values to bcm963158 defconfig cmd/Kconfig | 8 + common/Kconfig.boot | 23 ++- common/autoboot.c | 87 +++-- configs/bcm963158_ram_defconfig | 8 + include/crypt.h | 13 ++ lib/Kconfig | 1 + lib/Makefile| 1 + lib/crypt/Kconfig | 29 +++ lib/crypt/Makefile | 10 + lib/crypt/alg-sha256.h | 17 ++ lib/crypt/alg-sha512.h | 17 ++ lib/crypt/crypt-port.h | 28 +++ lib/crypt/crypt-sha256.c| 313 ++ lib/crypt/crypt-sha512.c| 328 lib/crypt/crypt.c | 73 +++ 15 files changed, 936 insertions(+), 20 deletions(-) create mode 100644 include/crypt.h create mode 100644 lib/crypt/Kconfig create mode 100644 lib/crypt/Makefile create mode 100644 lib/crypt/alg-sha256.h create mode 100644 lib/crypt/alg-sha512.h create mode 100644 lib/crypt/crypt-port.h create mode 100644 lib/crypt/crypt-sha256.c create mode 100644 lib/crypt/crypt-sha512.c create mode 100644 lib/crypt/crypt.c -- 2.30.1
[PATCH 5/5] configs: add new values to bcm963158 defconfig
In order to have at least one defconfig that enables all those newly added values. Signed-off-by: Steffen Jaeckel --- configs/bcm963158_ram_defconfig | 8 1 file changed, 8 insertions(+) diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig index 0be1e0981a..7e1e9b639d 100644 --- a/configs/bcm963158_ram_defconfig +++ b/configs/bcm963158_ram_defconfig @@ -54,4 +54,12 @@ CONFIG_BCM63XX_HSSPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_WDT_BCM6345=y +CONFIG_CRYPT_PW=y +CONFIG_CRYPT_PW_SHA256=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n" +CONFIG_AUTOBOOT_ENCRYPTION=y +# default password "password" +CONFIG_AUTOBOOT_STOP_STR_CRYPT="$5$rounds=64$TM4lL4zXDG7F4aRX$JM7a9wmvodnA0WasjTztj6mxg.KVuk6doQ/eBhdcapB" +CONFIG_AUTOBOOT_NEVER_TIMEOUT=y # CONFIG_GENERATE_SMBIOS_TABLE is not set -- 2.30.1
[PATCH 4/5] cmd: allow disabling of timeout for password entry
In case a user has to enter a complicated password it is sometimes
desireable to give the user more time than the default timeout.
Enabling this feature will disable the timeout entirely in case the user
presses the key before entering any other character.
Signed-off-by: Steffen Jaeckel
---
cmd/Kconfig | 8
common/autoboot.c | 8 +++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index c735e81b37..03c07d0f32 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -177,6 +177,14 @@ config CMD_SBI
help
Display information about the SBI implementation.
+config AUTOBOOT_NEVER_TIMEOUT
+ bool "Make the password entry never time-out"
+ depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
+ help
+ This option removes the timeout from the password entry
+ when the user first presses the key before entering
+ any other character.
+
endmenu
menu "Boot commands"
diff --git a/common/autoboot.c b/common/autoboot.c
index 5bda3da7b1..467333db9d 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -62,6 +62,7 @@ static int passwd_abort_crypt(uint64_t etime)
char presskey[DELAY_STOP_STR_MAX_LENGTH];
u_int presskey_len = 0;
int abort = 0;
+ int never_timeout = 0;
if (IS_ENABLED(HAS_STOP_STR_CRYPT) && !crypt_env_str)
crypt_env_str = AUTOBOOT_STOP_STR_ENC;
@@ -82,6 +83,11 @@ static int passwd_abort_crypt(uint64_t etime)
if ((presskey[presskey_len] == '\r') ||
(presskey[presskey_len] == '\n')) {
+ if (IS_ENABLED(CONFIG_AUTOBOOT_NEVER_TIMEOUT) &&
+ !presskey_len) {
+ never_timeout = 1;
+ continue;
+ }
presskey[presskey_len] = '\0';
crypt_compare(crypt_env_str, presskey, );
/* you had one chance */
@@ -90,7 +96,7 @@ static int passwd_abort_crypt(uint64_t etime)
presskey_len++;
}
}
- } while (get_ticks() <= etime);
+ } while (never_timeout || get_ticks() <= etime);
return abort;
}
--
2.30.1
[PATCH 3/5] common: Rename macro appropriately
While doing code-review internally this got nitpicked by 2 reviewers, so
I decided to include this here.
Signed-off-by: Steffen Jaeckel
---
common/autoboot.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/common/autoboot.c b/common/autoboot.c
index 732a01d0e5..5bda3da7b1 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#define MAX_DELAY_STOP_STR 64
+#define DELAY_STOP_STR_MAX_LENGTH 64
#ifndef DEBUG_BOOTKEYS
#define DEBUG_BOOTKEYS 0
@@ -59,7 +59,7 @@ static int menukey;
static int passwd_abort_crypt(uint64_t etime)
{
const char *crypt_env_str = env_get("bootstopkeycrypt");
- char presskey[MAX_DELAY_STOP_STR];
+ char presskey[DELAY_STOP_STR_MAX_LENGTH];
u_int presskey_len = 0;
int abort = 0;
@@ -75,7 +75,7 @@ static int passwd_abort_crypt(uint64_t etime)
do {
if (tstc()) {
/* Check for input string overflow */
- if (presskey_len >= MAX_DELAY_STOP_STR)
+ if (presskey_len >= DELAY_STOP_STR_MAX_LENGTH)
return 0;
presskey[presskey_len] = getchar();
@@ -136,9 +136,9 @@ static int passwd_abort_sha256(uint64_t etime)
if (sha_env_str == NULL)
sha_env_str = AUTOBOOT_STOP_STR_ENC;
- presskey = malloc_cache_aligned(MAX_DELAY_STOP_STR);
+ presskey = malloc_cache_aligned(DELAY_STOP_STR_MAX_LENGTH);
c = strstr(sha_env_str, ":");
- if (c && (c - sha_env_str < MAX_DELAY_STOP_STR)) {
+ if (c && (c - sha_env_str < DELAY_STOP_STR_MAX_LENGTH)) {
/* preload presskey with salt */
memcpy(presskey, sha_env_str, c - sha_env_str);
presskey_len = c - sha_env_str;
@@ -165,7 +165,7 @@ static int passwd_abort_sha256(uint64_t etime)
do {
if (tstc()) {
/* Check for input string overflow */
- if (presskey_len >= MAX_DELAY_STOP_STR) {
+ if (presskey_len >= DELAY_STOP_STR_MAX_LENGTH) {
free(presskey);
free(sha);
return 0;
@@ -209,7 +209,7 @@ static int passwd_abort_key(uint64_t etime)
{ .str = env_get("bootstopkey"), .retry = 0 },
};
- char presskey[MAX_DELAY_STOP_STR];
+ char presskey[DELAY_STOP_STR_MAX_LENGTH];
int presskey_len = 0;
int presskey_max = 0;
int i;
@@ -226,8 +226,8 @@ static int passwd_abort_key(uint64_t etime)
for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i++) {
delaykey[i].len = delaykey[i].str == NULL ?
0 : strlen(delaykey[i].str);
- delaykey[i].len = delaykey[i].len > MAX_DELAY_STOP_STR ?
- MAX_DELAY_STOP_STR : delaykey[i].len;
+ delaykey[i].len = delaykey[i].len > DELAY_STOP_STR_MAX_LENGTH ?
+ DELAY_STOP_STR_MAX_LENGTH : delaykey[i].len;
presskey_max = presskey_max > delaykey[i].len ?
presskey_max : delaykey[i].len;
--
2.30.1
[PATCH 2/5] common: integrate crypt-based passwords
Hook into the autoboot flow as an alternative to the existing
mechanisms.
Signed-off-by: Steffen Jaeckel
---
common/Kconfig.boot | 23 +---
common/autoboot.c | 67 +++--
2 files changed, 77 insertions(+), 13 deletions(-)
diff --git a/common/Kconfig.boot b/common/Kconfig.boot
index 9c335f4f8c..59fec48c5d 100644
--- a/common/Kconfig.boot
+++ b/common/Kconfig.boot
@@ -802,10 +802,16 @@ config AUTOBOOT_ENCRYPTION
depends on AUTOBOOT_KEYED
help
This option allows a string to be entered into U-Boot to stop the
- autoboot. The string itself is hashed and compared against the hash
- in the environment variable 'bootstopkeysha256'. If it matches then
- boot stops and a command-line prompt is presented.
-
+ autoboot.
+ The behavior depends whether CONFIG_CRYPT_PW is enabled or not.
+ In case CONFIG_CRYPT_PW is enabled, the string will be forwarded
+ to the crypt-based functionality and be compared against the
+ string in the environment variable 'bootstopkeycrypt'.
+ In case CONFIG_CRYPT_PW is disabled the string itself is hashed
+ and compared against the hash in the environment variable
+ 'bootstopkeysha256'.
+ If it matches in either case then boot stops and
+ a command-line prompt is presented.
This provides a way to ship a secure production device which can also
be accessed at the U-Boot command line.
@@ -843,6 +849,15 @@ config AUTOBOOT_KEYED_CTRLC
Setting this variable provides an escape sequence from the
limited "password" strings.
+config AUTOBOOT_STOP_STR_CRYPT
+ string "Stop autobooting via crypt-hashed password"
+ depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
+ help
+ This option adds the feature to only stop the autobooting,
+ and therefore boot into the U-Boot prompt, when the input
+ string / password matches a values that is hashed via
+ one of support crypt options and saved in the environment.
+
config AUTOBOOT_STOP_STR_SHA256
string "Stop autobooting via SHA256 encrypted password"
depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
diff --git a/common/autoboot.c b/common/autoboot.c
index 0bb08e7a4c..732a01d0e5 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -38,18 +39,62 @@ DECLARE_GLOBAL_DATA_PTR;
static int stored_bootdelay;
static int menukey;
-#ifdef CONFIG_AUTOBOOT_ENCRYPTION
-#define AUTOBOOT_STOP_STR_SHA256 CONFIG_AUTOBOOT_STOP_STR_SHA256
-#else
-#define AUTOBOOT_STOP_STR_SHA256 ""
+#if defined(CONFIG_AUTOBOOT_ENCRYPTION)
+#if defined(CONFIG_CRYPT_PW) && defined(CONFIG_AUTOBOOT_STOP_STR_CRYPT)
+#define AUTOBOOT_STOP_STR_ENC CONFIG_AUTOBOOT_STOP_STR_CRYPT
+#define HAS_STOP_STR_CRYPT 1
+#elif defined(CONFIG_AUTOBOOT_STOP_STR_SHA256)
+#define AUTOBOOT_STOP_STR_ENC CONFIG_AUTOBOOT_STOP_STR_SHA256
+#endif
+#endif
+#if !defined(AUTOBOOT_STOP_STR_ENC)
+#define AUTOBOOT_STOP_STR_ENC ""
#endif
-
#ifdef CONFIG_USE_AUTOBOOT_MENUKEY
#define AUTOBOOT_MENUKEY CONFIG_USE_AUTOBOOT_MENUKEY
#else
#define AUTOBOOT_MENUKEY 0
#endif
+static int passwd_abort_crypt(uint64_t etime)
+{
+ const char *crypt_env_str = env_get("bootstopkeycrypt");
+ char presskey[MAX_DELAY_STOP_STR];
+ u_int presskey_len = 0;
+ int abort = 0;
+
+ if (IS_ENABLED(HAS_STOP_STR_CRYPT) && !crypt_env_str)
+ crypt_env_str = AUTOBOOT_STOP_STR_ENC;
+
+ if (!crypt_env_str)
+ return 0;
+
+ /*
+* We expect the stop-string to be newline terminated.
+*/
+ do {
+ if (tstc()) {
+ /* Check for input string overflow */
+ if (presskey_len >= MAX_DELAY_STOP_STR)
+ return 0;
+
+ presskey[presskey_len] = getchar();
+
+ if ((presskey[presskey_len] == '\r') ||
+ (presskey[presskey_len] == '\n')) {
+ presskey[presskey_len] = '\0';
+ crypt_compare(crypt_env_str, presskey, );
+ /* you had one chance */
+ break;
+ } else {
+ presskey_len++;
+ }
+ }
+ } while (get_ticks() <= etime);
+
+ return abort;
+}
+
/*
* Use a "constant-length" time compare function for this
* hash compare:
@@ -89,7 +134,7 @@ static int passwd_abort_sha256(uint64_t etime)
int ret;
if (sha_env_str == NULL)
- sha_env_str = AUTOBOOT_STOP_STR_SHA256;
+ sha_env_str = AUTOBOOT_STOP_STR_ENC;
presskey = malloc_cache_aligned(MAX_DELAY_STOP_STR);
c =
Re: [PATCH 1/1] cmd/exception: support ebreak exception on RISC-V
> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de] > Sent: Friday, April 09, 2021 6:48 PM > To: Rick Jian-Zhi Chen(陳建志) > Cc: u-boot@lists.denx.de; Heinrich Schuchardt > Subject: [PATCH 1/1] cmd/exception: support ebreak exception on RISC-V > > The ebreak instruction should generate a breakpoint exception. > > Signed-off-by: Heinrich Schuchardt > --- > cmd/riscv/exception.c | 10 ++ > doc/usage/exception.rst | 3 +++ > 2 files changed, 13 insertions(+) Reviewed-by: Rick Chen
Re: [PATCH 2/3] fit: Use hash.c to call SHA code
On Wed, 17 Feb 2021 at 05:04, AKASHI Takahiro
wrote:
>
> Simon,
>
> # This is not a direct comment on this patch.
>
> On Wed, Feb 17, 2021 at 01:50:41PM +1030, Joel Stanley wrote:
> > Currently the FIT hashing will call directly into the SHA algorithms to
> > get a hash.
> >
> > This moves the fit code to use hash_lookup_algo, giving a common
> > entrypoint into the hashing code and removing the duplicated algorithm
> > look up. It also allows the use of hardware acceleration if configured.
> >
> > Signed-off-by: Joel Stanley
> > ---
> > common/image-fit.c | 34 --
> > 1 file changed, 8 insertions(+), 26 deletions(-)
> >
> > diff --git a/common/image-fit.c b/common/image-fit.c
> > index 28b3d2b19111..3451cdecc95b 100644
> > --- a/common/image-fit.c
> > +++ b/common/image-fit.c
> > @@ -1210,37 +1210,19 @@ int fit_set_timestamp(void *fit, int noffset,
> > time_t timestamp)
> > * 0, on success
> > *-1, when algo is unsupported
> > */
> > -int calculate_hash(const void *data, int data_len, const char *algo,
> > +int calculate_hash(const void *data, int data_len, const char *algo_name,
> > uint8_t *value, int *value_len)
> > {
> > - if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) {
> > - *((uint32_t *)value) = crc32_wd(0, data, data_len,
> > - CHUNKSZ_CRC32);
> > - *((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
> > - *value_len = 4;
> > - } else if (IMAGE_ENABLE_SHA1 && strcmp(algo, "sha1") == 0) {
> > - sha1_csum_wd((unsigned char *)data, data_len,
> > - (unsigned char *)value, CHUNKSZ_SHA1);
> > - *value_len = 20;
> > - } else if (IMAGE_ENABLE_SHA256 && strcmp(algo, "sha256") == 0) {
> > - sha256_csum_wd((unsigned char *)data, data_len,
> > -(unsigned char *)value, CHUNKSZ_SHA256);
> > - *value_len = SHA256_SUM_LEN;
> > - } else if (IMAGE_ENABLE_SHA384 && strcmp(algo, "sha384") == 0) {
> > - sha384_csum_wd((unsigned char *)data, data_len,
> > -(unsigned char *)value, CHUNKSZ_SHA384);
> > - *value_len = SHA384_SUM_LEN;
> > - } else if (IMAGE_ENABLE_SHA512 && strcmp(algo, "sha512") == 0) {
> > - sha512_csum_wd((unsigned char *)data, data_len,
> > -(unsigned char *)value, CHUNKSZ_SHA512);
> > - *value_len = SHA512_SUM_LEN;
> > - } else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) {
> > - md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
> > - *value_len = 16;
> > - } else {
> > + struct hash_algo *algo;
> > +
> > + if (hash_lookup_algo(algo_name, )) {
> > debug("Unsupported hash alogrithm\n");
> > return -1;
> > }
> > +
> > + algo->hash_func_ws(data, data_len, value, algo->chunk_size);
> > + *value_len = algo->digest_size;
>
> With this patch applied, there co-exists a very similar, hence
> confusing function, hash_calculate(), in rsa-checksum.c (now checksum.c?).
> If there is no particular reason for those two functions,
> we'd better unify them?
hash_calculate is doing a progressive hash over a count of regions.
This code is hashing a single chunk of data.
I agree the naming could be improved to make this clearer.
Cheers,
Joel
>
> -Takahiro Akashi
>
>
> > return 0;
> > }
> >
> > --
> > 2.30.0
> >
Re: [PATCH 0/3] Improvements to FIT hashing
Helli Simon, On Wed, 17 Feb 2021 at 03:20, Joel Stanley wrote: > > Here are some small changes to the FIT hashing code in order to use > more code from common/, which in turns allows hw implementations of SHA. > > This was motivated by a need to reduce the SPL size for the Aspeed > platforms by using the hardware engine. I have a driver for the Aspeed > SoC that I will submit. Do you have any thoughts on this series? Cheers, Joel > > Joel Stanley (3): > hw_sha: Fix coding style errors > fit: Use hash.c to call SHA code > hash: Allow for SHA512 hardware implementations > > common/hash.c | 24 ++-- > common/image-fit.c | 34 -- > include/hw_sha.h | 38 -- > lib/Kconfig| 15 +++ > 4 files changed, 69 insertions(+), 42 deletions(-) > > -- > 2.30.0 >
Re: [PATCH] checkpatch: Ignore ENOSYS warnings
On 4/12/21 2:04 PM, Simon Glass wrote:
Hi Sean,
On Mon, 12 Apr 2021 at 16:22, Sean Anderson wrote:
There are no system calls in U-Boot, but ENOSYS is still allowed (and
preferred since 42a2668743 ("dm: core: Document the common error codes")).
Silence this warning.
Signed-off-by: Sean Anderson
Seriies-to: sjg
This looks OK, except for that tag.
Should I resend the patch?
--Sean
Regards,
Simon
---
.checkpatch.conf | 3 +++
1 file changed, 3 insertions(+)
diff --git a/.checkpatch.conf b/.checkpatch.conf
index ed0c2150ba..9e40ea060b 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -26,6 +26,9 @@
# addresses are __aligned(2)".
--ignore PREFER_ETHER_ADDR_COPY
+# ENOSYS is a conventionally used error, even though U-Boot lacks system calls.
+--ignore ENOSYS
+
# A bit shorter of a description is OK with us.
--min-conf-desc-length=2
--
2.31.0
Re: [PATCH 0/5] Fix i.MXRT1050 hang on lcdif init and improve DT for mxsfb
On 4/13/21 1:03 AM, Giulio Benetti wrote: This patchset fixes u-boot hang on i.MXRT1050 while setting lcdif in mxsfb driver. There are 2 gates to be enabled to initialize mxsfb so let's introduce the missing gate as a clock and rename "per" clock to "pix" clock since in the other .dts files using *-lcdif "pix" is used. This patchset add also "disp_axi" clock enabling in mxsfb that should make able to every i.MX SoC with lcdif using DT. I didn't test it other than i.MXRT1050 since I don't have the boards. If someone can test it it would be great. Note that i.MX23/28 should fail using DT instead because they don't specify any clock-names in their dts. I've forgotten to specify that this patchset depends on this patchset: https://patchwork.ozlabs.org/project/uboot/list/?series=237909 Best regards -- Giulio Benetti Benetti Engineering sas Giulio Benetti (5): video: mxsfb: add enabling of "axi" clock other than "per" clock video: mxsfb: add enabling of "disp_axi" clock clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APB ARM: dts: imxrt1050: move lcdif assigned clock to dtsi ARM: dts: imxrt1050: set lcdif clocks according to mxsfb driver arch/arm/dts/imxrt1050-evk.dts | 3 -- arch/arm/dts/imxrt1050.dtsi | 7 ++-- drivers/clk/imx/clk-imxrt1050.c | 6 ++-- drivers/video/mxsfb.c | 36 + include/dt-bindings/clock/imxrt1050-clock.h | 5 +-- 5 files changed, 41 insertions(+), 16 deletions(-)
[PATCH 4/5] ARM: dts: imxrt1050: move lcdif assigned clock to dtsi
Since we assume pll5 is the default lcdif clock source let's move
assigned-clocks(-parents) properties to .dtsi file.
Signed-off-by: Giulio Benetti
---
arch/arm/dts/imxrt1050-evk.dts | 3 ---
arch/arm/dts/imxrt1050.dtsi| 2 ++
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index 2052d4eb4e..dc66fc9c37 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -238,9 +238,6 @@
display = <>;
status = "okay";
- assigned-clocks = < IMXRT1050_CLK_LCDIF_SEL>;
- assigned-clock-parents = < IMXRT1050_CLK_PLL5_VIDEO>;
-
display0: display0 {
bits-per-pixel = <16>;
bus-width = <16>;
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 6f9da3fe8a..eb5e09e971 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -152,6 +152,8 @@
interrupts = ;
clocks = < IMXRT1050_CLK_LCDIF>;
clock-names = "per";
+ assigned-clocks = < IMXRT1050_CLK_LCDIF_SEL>;
+ assigned-clock-parents = <
IMXRT1050_CLK_PLL5_VIDEO>;
status = "disabled";
};
--
2.25.1
[PATCH 3/5] clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APB
Lcd peripheral needs 2 different gates to be enable to work, so let's
introduce the missing one(LCDIF_PIX) and rename the existing one
(LCDIF_APB).
Signed-off-by: Giulio Benetti
---
drivers/clk/imx/clk-imxrt1050.c | 6 --
include/dt-bindings/clock/imxrt1050-clock.h | 5 +++--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 594093ee5f..eb6847f865 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -255,8 +255,10 @@ static int imxrt1050_clk_probe(struct udevice *dev)
imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
clk_dm(IMXRT1050_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
- clk_dm(IMXRT1050_CLK_LCDIF,
- imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10));
+ clk_dm(IMXRT1050_CLK_LCDIF_APB,
+ imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+ clk_dm(IMXRT1050_CLK_LCDIF_PIX,
+ imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10));
struct clk *clk, *clk1;
diff --git a/include/dt-bindings/clock/imxrt1050-clock.h
b/include/dt-bindings/clock/imxrt1050-clock.h
index c174f90c1a..09b65e5df2 100644
--- a/include/dt-bindings/clock/imxrt1050-clock.h
+++ b/include/dt-bindings/clock/imxrt1050-clock.h
@@ -52,7 +52,7 @@
#define IMXRT1050_CLK_USDHC2 43
#define IMXRT1050_CLK_LPUART1 44
#define IMXRT1050_CLK_SEMC 45
-#define IMXRT1050_CLK_LCDIF46
+#define IMXRT1050_CLK_LCDIF_APB46
#define IMXRT1050_CLK_PLL1_ARM 47
#define IMXRT1050_CLK_PLL2_SYS 48
#define IMXRT1050_CLK_PLL3_USB_OTG 49
@@ -60,6 +60,7 @@
#define IMXRT1050_CLK_PLL5_VIDEO 51
#define IMXRT1050_CLK_PLL6_ENET52
#define IMXRT1050_CLK_PLL7_USB_HOST53
-#define IMXRT1050_CLK_END 54
+#define IMXRT1050_CLK_LCDIF_PIX54
+#define IMXRT1050_CLK_END 55
#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
--
2.25.1
[PATCH 5/5] ARM: dts: imxrt1050: set lcdif clocks according to mxsfb driver
Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index eb5e09e971..ec1eb88e45 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -150,8 +150,9 @@ compatible = "fsl,imxrt-lcdif"; reg = <0x402b8000 0x4000>; interrupts = ; - clocks = < IMXRT1050_CLK_LCDIF>; - clock-names = "per"; + clocks = < IMXRT1050_CLK_LCDIF_PIX>, +< IMXRT1050_CLK_LCDIF_APB>; + clock-names = "pix", "axi"; assigned-clocks = < IMXRT1050_CLK_LCDIF_SEL>; assigned-clock-parents = < IMXRT1050_CLK_PLL5_VIDEO>; status = "disabled"; -- 2.25.1
[PATCH 2/5] video: mxsfb: add enabling of "disp_axi" clock
Some SoC needs "disp_axi" clock to be enabled, so let's try to retrieve it
and enabling. If it fails it gives only a debug(), but this clock as well
as "axi" clock is not mandatory.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 147bd668fe..523d8a8d98 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -98,6 +98,17 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
return;
}
}
+
+ ret = clk_get_by_name(dev, "disp_axi", );
+ if (!ret) {
+ debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__,
ret);
+ } else {
+ ret = clk_enable();
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs disp_axi clk: %d\n",
ret);
+ return;
+ }
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
--
2.25.1
[PATCH 1/5] video: mxsfb: add enabling of "axi" clock other than "per" clock
On some SoC mxsfb needs more than one clock gate(actual "per" clock). So
let's introduce "axi" clock that can be provided but it's not mandatory.
This is inspired from linux mxsfb driver. Also let's rename "per" clock to
"pix" clock for compatibility with already existing .dts lcdif nodes
implementation.
Signed-off-by: Giulio Benetti
---
drivers/video/mxsfb.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index e1fd36a62d..147bd668fe 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -67,26 +67,37 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
uint32_t vdctrl0;
#if CONFIG_IS_ENABLED(CLK)
- struct clk per_clk;
+ struct clk clk;
int ret;
- ret = clk_get_by_name(dev, "per", _clk);
+ ret = clk_get_by_name(dev, "pix", );
if (ret) {
- dev_err(dev, "Failed to get mxs clk: %d\n", ret);
+ dev_err(dev, "Failed to get mxs pix clk: %d\n", ret);
return;
}
- ret = clk_set_rate(_clk, timings->pixelclock.typ);
+ ret = clk_set_rate(, timings->pixelclock.typ);
if (ret < 0) {
- dev_err(dev, "Failed to set mxs clk: %d\n", ret);
+ dev_err(dev, "Failed to set mxs pix clk: %d\n", ret);
return;
}
- ret = clk_enable(_clk);
+ ret = clk_enable();
if (ret < 0) {
- dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
+ dev_err(dev, "Failed to enable mxs pix clk: %d\n", ret);
return;
}
+
+ ret = clk_get_by_name(dev, "axi", );
+ if (!ret) {
+ debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret);
+ } else {
+ ret = clk_enable();
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable mxs axi clk: %d\n", ret);
+ return;
+ }
+ }
#else
/* Kick in the LCDIF clock */
mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
--
2.25.1
[PATCH 0/5] Fix i.MXRT1050 hang on lcdif init and improve DT for mxsfb
This patchset fixes u-boot hang on i.MXRT1050 while setting lcdif in mxsfb driver. There are 2 gates to be enabled to initialize mxsfb so let's introduce the missing gate as a clock and rename "per" clock to "pix" clock since in the other .dts files using *-lcdif "pix" is used. This patchset add also "disp_axi" clock enabling in mxsfb that should make able to every i.MX SoC with lcdif using DT. I didn't test it other than i.MXRT1050 since I don't have the boards. If someone can test it it would be great. Note that i.MX23/28 should fail using DT instead because they don't specify any clock-names in their dts. Giulio Benetti (5): video: mxsfb: add enabling of "axi" clock other than "per" clock video: mxsfb: add enabling of "disp_axi" clock clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APB ARM: dts: imxrt1050: move lcdif assigned clock to dtsi ARM: dts: imxrt1050: set lcdif clocks according to mxsfb driver arch/arm/dts/imxrt1050-evk.dts | 3 -- arch/arm/dts/imxrt1050.dtsi | 7 ++-- drivers/clk/imx/clk-imxrt1050.c | 6 ++-- drivers/video/mxsfb.c | 36 + include/dt-bindings/clock/imxrt1050-clock.h | 5 +-- 5 files changed, 41 insertions(+), 16 deletions(-) -- 2.25.1
[PATCH v2 3/3] test: Add test for partitions
This is technically a library function, but we use MMCs for testing, so
it is easier to do it with DM. At the moment, the only block devices in
sandbox are MMCs (AFAIK) so we just test with those.
Signed-off-by: Sean Anderson
---
Changes in v2:
- New
test/dm/Makefile | 1 +
test/dm/part.c | 76
2 files changed, 77 insertions(+)
create mode 100644 test/dm/part.c
diff --git a/test/dm/Makefile b/test/dm/Makefile
index f5cc5540e8..7d017f8750 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -98,5 +98,6 @@ endif
ifneq ($(CONFIG_EFI_PARTITION),)
obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o
endif
+obj-$(CONFIG_EFI_PARTITION) += part.o
endif
endif # !SPL
diff --git a/test/dm/part.c b/test/dm/part.c
new file mode 100644
index 00..051e9010b6
--- /dev/null
+++ b/test/dm/part.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int dm_test_part(struct unit_test_state *uts)
+{
+ char str_disk_guid[UUID_STR_LEN + 1];
+ struct blk_desc *mmc_dev_desc;
+ struct disk_partition part_info;
+ struct disk_partition parts[2] = {
+ {
+ .start = 48, /* GPT data takes up the first 34 blocks
or so */
+ .size = 1,
+ .name = "test1",
+ },
+ {
+ .start = 49,
+ .size = 1,
+ .name = "test2",
+ },
+ };
+
+ ut_asserteq(1, blk_get_device_by_str("mmc", "1", _dev_desc));
+ if (CONFIG_IS_ENABLED(RANDOM_UUID)) {
+ gen_rand_uuid_str(parts[0].uuid, UUID_STR_FORMAT_STD);
+ gen_rand_uuid_str(parts[1].uuid, UUID_STR_FORMAT_STD);
+ gen_rand_uuid_str(str_disk_guid, UUID_STR_FORMAT_STD);
+ }
+ ut_assertok(gpt_restore(mmc_dev_desc, str_disk_guid, parts,
+ ARRAY_SIZE(parts)));
+
+#define test(expected, part_str, whole) \
+ ut_asserteq(expected, \
+ part_get_info_by_dev_and_name_or_num("mmc", part_str, \
+_dev_desc, \
+_info, whole))
+
+ test(-ENODEV, "", true);
+ env_set("bootdevice", "0");
+ test(0, "", true);
+ env_set("bootdevice", "1");
+ test(1, "", false);
+ test(1, "-", false);
+ env_set("bootdevice", "");
+ test(-EPROTONOSUPPORT, "0", false);
+ test(0, "0", true);
+ test(0, ":0", true);
+ test(0, ".0", true);
+ test(0, ".0:0", true);
+ test(-EINVAL, "#test1", true);
+ test(1, "1", false);
+ test(1, "1", true);
+ test(-ENOENT, "1:0", false);
+ test(0, "1:0", true);
+ test(1, "1:1", false);
+ test(2, "1:2", false);
+ test(1, "1.0", false);
+ test(0, "1.0:0", true);
+ test(1, "1.0:1", false);
+ test(2, "1.0:2", false);
+ test(-EINVAL, "1#bogus", false);
+ test(1, "1#test1", false);
+ test(2, "1#test2", false);
+
+ return 0;
+}
+DM_TEST(dm_test_part, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
--
2.25.1
[PATCH v2 2/3] part: Fix bogus return from part_get_info_by_dev_and_name
blk_get_device_by_str returns the device number on success. So we must check if the return was negative to determine an error. Signed-off-by: Sean Anderson --- Changes in v2: - New disk/part.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disk/part.c b/disk/part.c index 80ced2ba88..5e7e59cf25 100644 --- a/disk/part.c +++ b/disk/part.c @@ -725,7 +725,7 @@ static int part_get_info_by_dev_and_name(const char *dev_iface, } ret = blk_get_device_by_str(dev_iface, dev_str, dev_desc); - if (ret) + if (ret < 0) goto cleanup; ret = part_get_info_by_name(*dev_desc, part_str, part_info); -- 2.25.1
[PATCH v2 1/3] cmd: fs: Use part_get_info_by_dev_and_name_or_num to parse partitions
This allows using dev#partlabel syntax.
Signed-off-by: Sean Anderson
---
Changes in v2:
- Add stub for when CONFIG_PARTITIONS=n
fs/fs.c| 4 ++--
include/part.h | 12 +++-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/fs/fs.c b/fs/fs.c
index 900928c394..b7936fd4cf 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -385,8 +385,8 @@ int fs_set_blk_dev(const char *ifname, const char
*dev_part_str, int fstype)
}
#endif
- part = blk_get_device_part_str(ifname, dev_part_str, _dev_desc,
- _partition, 1);
+ part = part_get_info_by_dev_and_name_or_num(ifname, dev_part_str,
_dev_desc,
+ _partition, 1);
if (part < 0)
return -1;
diff --git a/include/part.h b/include/part.h
index 7f78271a98..419c859708 100644
--- a/include/part.h
+++ b/include/part.h
@@ -230,7 +230,7 @@ int part_get_info_by_name(struct blk_desc *dev_desc,
* @param[in] allow_whole_dev true to allow the user to select partition 0
* (which means the whole device), false to require a valid
* partition number >= 1
- * @return 0 on success, or a negative on error
+ * @return the partition number on success, or negative errno on error
*/
int part_get_info_by_dev_and_name_or_num(const char *dev_iface,
const char *dev_part_str,
@@ -275,6 +275,16 @@ static inline int blk_get_device_part_str(const char
*ifname,
struct disk_partition *info,
int allow_whole_dev)
{ *dev_desc = NULL; return -1; }
+static inline int
+part_get_info_by_dev_and_name_or_num(const char *dev_iface,
+const char *dev_part_str,
+struct blk_desc **dev_desc,
+struct disk_partition *part_info,
+int allow_whole_dev)
+{
+ *dev_desc = NULL;
+ return -ENOSYS;
+}
#endif
/*
--
2.25.1
Re: Getting rid of falcon mode
On Mon, Apr 12, 2021 at 04:32:49PM -0500, Alex G. wrote: > ## Introduction > > Today we use "falcon mode" to mean "boot linux straight from SPL". This > designation makes sense, since falcons "fly at high speed and change > direction rapidly" according to Wikipedia. > > The way we implement falcon mode is to reserve two areas of storage: > * kernel area/partition > * dtb area/partition > By using some "special cases", and "spl export", SPL can more or less figure > out how to skip u-boot. > > > ## The plot twist > > People familiar with FIT, will have recognized that the above is achievable > with a very basic FIT image. With some advantages: > > - No "special cases" in SPL code > - Signed kernel images > - Signed kernel devicetree > - Devicetree overlays > - Automatic selection of correct devicetree > > > ## The problems > > The advantages of FIT are not obvious by looking at SPL code. A noticeable > amount of SPL code is hidden under #ifdef CONFIG_SPL_OS_BOOT, leading one to > believe that SPL_OS_BOOT is very important. It must be since it takes up so > much code. > > Enabling falcon mode is not well documented, and requires a lot of trial and > error. I've had to define 7 macros, and one new function to get it working > on my board -- and vividly remember the grief. This is an antiquated way of > doing things, and completely ignores the u-boot devicetree -- we could just > as well have defined those seven values in the dtb. > > SPL assumes that it must load u-boot, unless in instances under > CONFIG_SPL_OS_BOOT. This has cause me a huge amount of grief and confusion > over the past several months. I have no less than three patch series trying > to address shortfalls there. It's awful. > > > ## The proposal > > I propose we drop falcon mode support for legacy images. > > - Drop CONFIG_SPL_OS_BOOT. Support for this is implied by SPL_FIT > - Drop the "dtb area/partition". The dtb is derived from the FIT > - Drop "spl export" > > > How do we deal with devicetrees in the FIT then? The options are to use a > modified devicetree which has the desired "/chosen" node, or use DTB > overlays. > > What are the reasons why we shouldn't go this route? Please send an RFC that shows what doc/usage/falcon.rst would look like (base it as much or as little on doc/README.falon as you like). Conceptually, yes, this sounds like the right way to go moving forward. It should just be removing code, except for around the "boot to U-Boot not OS" stuff. Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] cmd: fs: Use part_get_info_by_dev_and_name_or_num to parse partitions
On 4/12/21 5:44 PM, Tom Rini wrote: > On Tue, Mar 09, 2021 at 03:56:24PM -0500, Sean Anderson wrote: > >> This allows using dev#partlabel syntax. >> >> Signed-off-by: Sean Anderson >> --- >> >> fs/fs.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/fs/fs.c b/fs/fs.c >> index 900928c394..b7936fd4cf 100644 >> --- a/fs/fs.c >> +++ b/fs/fs.c >> @@ -385,8 +385,8 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype) >>} >> #endif >> >> - part = blk_get_device_part_str(ifname, dev_part_str, _dev_desc, >> - _partition, 1); >> + part = part_get_info_by_dev_and_name_or_num(ifname, dev_part_str, _dev_desc, >> + _partition, 1); >>if (part < 0) >>return -1; > > This breaks a small number of platforms that have FS_LOADER support > without PARTITION support: > xilinx_versal_mini xilinx_zynqmp_mini xilinx_zynqmp_mini_nand > xilinx_zynqmp_mini_nand_single mt7620_mt7530_rfb mt7628_rfb and I > suspect in all cases it's an intentional and valid config. > Ok, I will add a stub like what is done for blk_get_device_part_str in v2. --Sean
Re: [PATCH] cmd: fs: Use part_get_info_by_dev_and_name_or_num to parse partitions
On Tue, Mar 09, 2021 at 03:56:24PM -0500, Sean Anderson wrote: > This allows using dev#partlabel syntax. > > Signed-off-by: Sean Anderson > --- > > fs/fs.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/fs/fs.c b/fs/fs.c > index 900928c394..b7936fd4cf 100644 > --- a/fs/fs.c > +++ b/fs/fs.c > @@ -385,8 +385,8 @@ int fs_set_blk_dev(const char *ifname, const char > *dev_part_str, int fstype) > } > #endif > > - part = blk_get_device_part_str(ifname, dev_part_str, _dev_desc, > - _partition, 1); > + part = part_get_info_by_dev_and_name_or_num(ifname, dev_part_str, > _dev_desc, > + _partition, 1); > if (part < 0) > return -1; This breaks a small number of platforms that have FS_LOADER support without PARTITION support: xilinx_versal_mini xilinx_zynqmp_mini xilinx_zynqmp_mini_nand xilinx_zynqmp_mini_nand_single mt7620_mt7530_rfb mt7628_rfb and I suspect in all cases it's an intentional and valid config. -- Tom signature.asc Description: PGP signature
Getting rid of falcon mode
## Introduction Today we use "falcon mode" to mean "boot linux straight from SPL". This designation makes sense, since falcons "fly at high speed and change direction rapidly" according to Wikipedia. The way we implement falcon mode is to reserve two areas of storage: * kernel area/partition * dtb area/partition By using some "special cases", and "spl export", SPL can more or less figure out how to skip u-boot. ## The plot twist People familiar with FIT, will have recognized that the above is achievable with a very basic FIT image. With some advantages: - No "special cases" in SPL code - Signed kernel images - Signed kernel devicetree - Devicetree overlays - Automatic selection of correct devicetree ## The problems The advantages of FIT are not obvious by looking at SPL code. A noticeable amount of SPL code is hidden under #ifdef CONFIG_SPL_OS_BOOT, leading one to believe that SPL_OS_BOOT is very important. It must be since it takes up so much code. Enabling falcon mode is not well documented, and requires a lot of trial and error. I've had to define 7 macros, and one new function to get it working on my board -- and vividly remember the grief. This is an antiquated way of doing things, and completely ignores the u-boot devicetree -- we could just as well have defined those seven values in the dtb. SPL assumes that it must load u-boot, unless in instances under CONFIG_SPL_OS_BOOT. This has cause me a huge amount of grief and confusion over the past several months. I have no less than three patch series trying to address shortfalls there. It's awful. ## The proposal I propose we drop falcon mode support for legacy images. - Drop CONFIG_SPL_OS_BOOT. Support for this is implied by SPL_FIT - Drop the "dtb area/partition". The dtb is derived from the FIT - Drop "spl export" How do we deal with devicetrees in the FIT then? The options are to use a modified devicetree which has the desired "/chosen" node, or use DTB overlays. What are the reasons why we shouldn't go this route? Alex
Re: [PATCH] Revert "spl: Drop bd_info in the data section"
Hi Tom, On Tue, 13 Apr 2021 at 06:38, Tom Rini wrote: > > On Tue, Apr 13, 2021 at 06:26:08AM +1200, Simon Glass wrote: > > Hi Tom, > > > > On Tue, 13 Apr 2021 at 06:18, Tom Rini wrote: > > > > > > On Tue, Apr 13, 2021 at 05:49:19AM +1200, Simon Glass wrote: > [snip] > > > > As to a weak function, what would the default behaviour be? If we can > > > > define that, then it would be better IMO. > > > > > > > > When we try to refactor things, weak functions and undefined (or > > > > arch-specific behaviour) can really make things tough. > > > > > > Well, what was the problem you were trying to solve here? I assumed > > > there was a case where things actively broke, with the previous design, > > > and it's not just the 64byte savings in some cases. But is it? > > > > Yes the region of memory is not writable, so must be allocated at runtime. > > Where, on x86? Some ARM cases? That's one of the other things to sort > out here. Yes, on coral and likely newer things to come...For ARM I don't know of any such problems. Regards, Simon
Re: [PATCH] Revert "spl: Drop bd_info in the data section"
On Tue, Apr 13, 2021 at 06:26:08AM +1200, Simon Glass wrote: > Hi Tom, > > On Tue, 13 Apr 2021 at 06:18, Tom Rini wrote: > > > > On Tue, Apr 13, 2021 at 05:49:19AM +1200, Simon Glass wrote: [snip] > > > As to a weak function, what would the default behaviour be? If we can > > > define that, then it would be better IMO. > > > > > > When we try to refactor things, weak functions and undefined (or > > > arch-specific behaviour) can really make things tough. > > > > Well, what was the problem you were trying to solve here? I assumed > > there was a case where things actively broke, with the previous design, > > and it's not just the 64byte savings in some cases. But is it? > > Yes the region of memory is not writable, so must be allocated at runtime. Where, on x86? Some ARM cases? That's one of the other things to sort out here. -- Tom signature.asc Description: PGP signature
Re: [PATCH] Revert "spl: Drop bd_info in the data section"
Hi Tom, On Tue, 13 Apr 2021 at 06:18, Tom Rini wrote: > > On Tue, Apr 13, 2021 at 05:49:19AM +1200, Simon Glass wrote: > > Hi Tom, Alex, > > > > On Tue, 13 Apr 2021 at 04:26, Tom Rini wrote: > > > > > > On Mon, Apr 12, 2021 at 10:21:18AM -0500, Alex G. wrote: > > > > > > > > > > > > On 4/12/21 9:40 AM, Tom Rini wrote: > > > > > On Mon, Apr 12, 2021 at 08:51:11AM -0500, Alex G. wrote: > > > > > > > > > > > > > > > > > > On 4/12/21 8:25 AM, Tom Rini wrote: > > > > > > > On Fri, Apr 09, 2021 at 05:29:36PM -0700, Tim Harvey wrote: > > > > > > > > On Fri, Apr 9, 2021 at 1:53 PM Tom Rini > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > On Fri, Apr 09, 2021 at 03:24:41PM -0500, Adam Ford wrote: > > > > > > > > > > On Fri, Apr 9, 2021 at 2:20 PM Alex G. > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Simon > > > > > > > > > > > > > > > > > > > > > > On 4/8/21 6:55 PM, Simon Glass wrote: > > > > > > > > > > > > Hi Alexandru, > > > > > > > > > > > > > > > > > > > > > > > > On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > This reverts commit > > > > > > > > > > > > > 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75. > > > > > > > > > > > > > > > > > > > > > > > > > > struct global_data contains a pointer to the bd_info > > > > > > > > > > > > > structure. This > > > > > > > > > > > > > pointer was populated spl_set_bd() to a pre-allocated > > > > > > > > > > > > > bd_info in the > > > > > > > > > > > > > ".data" section. The referenced commit replaced this > > > > > > > > > > > > > mechanism to one > > > > > > > > > > > > > that uses malloc(). That new mechanism is only used > > > > > > > > > > > > > if SPL_ALLOC_BD=y. > > > > > > > > > > > > > which very few boards do. > > > > > > > > > > > > > > > > > > > > > > > > > > The result is that (struct global_data)->bd is NULL > > > > > > > > > > > > > in SPL on most > > > > > > > > > > > > > platforms. This breaks falcon mode, since > > > > > > > > > > > > > arch_fixup_fdt() tries to > > > > > > > > > > > > > access (struct global_data)->bd and set the "/memory" > > > > > > > > > > > > > node in the > > > > > > > > > > > > > devicetree. The result is that the "/memory" node > > > > > > > > > > > > > contains garbage > > > > > > > > > > > > > values, causing linux to panic() as it sets up the > > > > > > > > > > > > > page table. > > > > > > > > > > > > > > > > > > > > > > > > > > Instead of trying to fix the mess, potentially > > > > > > > > > > > > > causing other issues, > > > > > > > > > > > > > revert to the code that worked, while this change is > > > > > > > > > > > > > reworked. > > > > > > > > > > > > > > > > > > > > > > > > The goal here is to drop a feature that few boards use > > > > > > > > > > > > and reduce > > > > > > > > > > > > memory usage in SPL. It has been in place for two > > > > > > > > > > > > releases now. > > > > > > > > > > > > > > > > > > > > > > > > If Falcon mode needs it, perhaps you could add an > > > > > > > > > > > > 'imply' in the > > > > > > > > > > > > Kconfig for that feature? Is there one? Or perhaps > > > > > > > > > > > > CONFIG_ARCH_FIXUP_FDT_MEMORY ? > > > > > > > > > > > > > > > > > > > > > > > > One option would be to return an error in > > > > > > > > > > > > arch_fixup_fdt(). In > > > > > > > > > > > > general, fixups make things tricky because there is no > > > > > > > > > > > > way to > > > > > > > > > > > > determine when they are used but at least this one has > > > > > > > > > > > > a CONFIG. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > The argument that this has been in place for two releases > > > > > > > > > > > is incorrect. > > > > > > > > > > > Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only > > > > > > > > > > > introduced with > > > > > > > > > > > the v2021.04 release. It definitely was not in 2021.01. > > > > > > > > > > > It's only in the > > > > > > > > > > > last release, which is four days old t the time of this > > > > > > > > > > > writing. > > > > > > > > > > > > > > > > > > Yes. But another way of saying that is that we're 4 days in > > > > > > > > > to the > > > > > > > > > merge window. That's a bit early to say we must revert the > > > > > > > > > change. If > > > > > > > > > this was just before the release, yes, revert would be the > > > > > > > > > right answer. > > > > > > > > > It's also the case the original commit fixes some cases while > > > > > > > > > also > > > > > > > > > saving size, if I read it right. So a strict revert isn't > > > > > > > > > right, we'd > > > > > > > > > need to also probably also default y SPL_ALLOC_BD in some > > > > > > > > > cases. > > > > > > > > > > > > > > > > > > > > Although I was able to find one example, the reality is > > > > > > > > > > > that we don't > > > > > > > > > > > know the full extent of the breakage. The prudent thing > > > > > > > > > > > at this point is > >
Re: [PATCH] Revert "spl: Drop bd_info in the data section"
On Tue, Apr 13, 2021 at 05:49:19AM +1200, Simon Glass wrote: > Hi Tom, Alex, > > On Tue, 13 Apr 2021 at 04:26, Tom Rini wrote: > > > > On Mon, Apr 12, 2021 at 10:21:18AM -0500, Alex G. wrote: > > > > > > > > > On 4/12/21 9:40 AM, Tom Rini wrote: > > > > On Mon, Apr 12, 2021 at 08:51:11AM -0500, Alex G. wrote: > > > > > > > > > > > > > > > On 4/12/21 8:25 AM, Tom Rini wrote: > > > > > > On Fri, Apr 09, 2021 at 05:29:36PM -0700, Tim Harvey wrote: > > > > > > > On Fri, Apr 9, 2021 at 1:53 PM Tom Rini > > > > > > > wrote: > > > > > > > > > > > > > > > > On Fri, Apr 09, 2021 at 03:24:41PM -0500, Adam Ford wrote: > > > > > > > > > On Fri, Apr 9, 2021 at 2:20 PM Alex G. > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Simon > > > > > > > > > > > > > > > > > > > > On 4/8/21 6:55 PM, Simon Glass wrote: > > > > > > > > > > > Hi Alexandru, > > > > > > > > > > > > > > > > > > > > > > On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > This reverts commit > > > > > > > > > > > > 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75. > > > > > > > > > > > > > > > > > > > > > > > > struct global_data contains a pointer to the bd_info > > > > > > > > > > > > structure. This > > > > > > > > > > > > pointer was populated spl_set_bd() to a pre-allocated > > > > > > > > > > > > bd_info in the > > > > > > > > > > > > ".data" section. The referenced commit replaced this > > > > > > > > > > > > mechanism to one > > > > > > > > > > > > that uses malloc(). That new mechanism is only used if > > > > > > > > > > > > SPL_ALLOC_BD=y. > > > > > > > > > > > > which very few boards do. > > > > > > > > > > > > > > > > > > > > > > > > The result is that (struct global_data)->bd is NULL in > > > > > > > > > > > > SPL on most > > > > > > > > > > > > platforms. This breaks falcon mode, since > > > > > > > > > > > > arch_fixup_fdt() tries to > > > > > > > > > > > > access (struct global_data)->bd and set the "/memory" > > > > > > > > > > > > node in the > > > > > > > > > > > > devicetree. The result is that the "/memory" node > > > > > > > > > > > > contains garbage > > > > > > > > > > > > values, causing linux to panic() as it sets up the page > > > > > > > > > > > > table. > > > > > > > > > > > > > > > > > > > > > > > > Instead of trying to fix the mess, potentially causing > > > > > > > > > > > > other issues, > > > > > > > > > > > > revert to the code that worked, while this change is > > > > > > > > > > > > reworked. > > > > > > > > > > > > > > > > > > > > > > The goal here is to drop a feature that few boards use > > > > > > > > > > > and reduce > > > > > > > > > > > memory usage in SPL. It has been in place for two > > > > > > > > > > > releases now. > > > > > > > > > > > > > > > > > > > > > > If Falcon mode needs it, perhaps you could add an 'imply' > > > > > > > > > > > in the > > > > > > > > > > > Kconfig for that feature? Is there one? Or perhaps > > > > > > > > > > > CONFIG_ARCH_FIXUP_FDT_MEMORY ? > > > > > > > > > > > > > > > > > > > > > > One option would be to return an error in > > > > > > > > > > > arch_fixup_fdt(). In > > > > > > > > > > > general, fixups make things tricky because there is no > > > > > > > > > > > way to > > > > > > > > > > > determine when they are used but at least this one has a > > > > > > > > > > > CONFIG. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > The argument that this has been in place for two releases > > > > > > > > > > is incorrect. > > > > > > > > > > Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only > > > > > > > > > > introduced with > > > > > > > > > > the v2021.04 release. It definitely was not in 2021.01. > > > > > > > > > > It's only in the > > > > > > > > > > last release, which is four days old t the time of this > > > > > > > > > > writing. > > > > > > > > > > > > > > > > Yes. But another way of saying that is that we're 4 days in to > > > > > > > > the > > > > > > > > merge window. That's a bit early to say we must revert the > > > > > > > > change. If > > > > > > > > this was just before the release, yes, revert would be the > > > > > > > > right answer. > > > > > > > > It's also the case the original commit fixes some cases while > > > > > > > > also > > > > > > > > saving size, if I read it right. So a strict revert isn't > > > > > > > > right, we'd > > > > > > > > need to also probably also default y SPL_ALLOC_BD in some cases. > > > > > > > > > > > > > > > > > > Although I was able to find one example, the reality is > > > > > > > > > > that we don't > > > > > > > > > > know the full extent of the breakage. The prudent thing at > > > > > > > > > > this point is > > > > > > > > > > to revert. > > > > > > > > > > > > > > > > > > > > The knowledge of how to init the platform is in the > > > > > > > > > > devicetree and code. > > > > > > > > > > Why should kconfig also be involved in storing this > > > > > > > > > > knowledge? By this > > >
Re: [PATCH v3 1/2] dm: core: Add size operations on device tree references
On Mon, 12 Apr 2021 at 18:51, chenguanqiao wrote: > > From: Chen Guanqiao > > Add functions to add size of addresses in the device tree using ofnode > references. > > If the size is not set, return FDT_SIZE_T_NONE. > > Signed-off-by: Chen Guanqiao > --- > drivers/core/ofnode.c | 11 +++ > include/dm/ofnode.h | 10 ++ > include/fdtdec.h | 5 +++-- > 3 files changed, 24 insertions(+), 2 deletions(-) Reviewed-by: Simon Glass
Re: [PATCH v3 2/2] test: dm: add test item for ofnode_get_addr() and ofnode_get_size()
On Mon, 12 Apr 2021 at 18:51, chenguanqiao wrote: > > From: Chen Guanqiao > > Add test item for getting address and size functions > > Test the following function: > - ofnode_get_addr() > - ofnode_get_size() > > Signed-off-by: Chen Guanqiao > --- > test/dm/ofnode.c | 31 +++ > 1 file changed, 31 insertions(+) Reviewed-by: Simon Glass
Re: [PATCH] checkpatch: Ignore ENOSYS warnings
Hi Sean,
On Mon, 12 Apr 2021 at 16:22, Sean Anderson wrote:
>
> There are no system calls in U-Boot, but ENOSYS is still allowed (and
> preferred since 42a2668743 ("dm: core: Document the common error codes")).
> Silence this warning.
>
> Signed-off-by: Sean Anderson
> Seriies-to: sjg
This looks OK, except for that tag.
Regards,
Simon
> ---
>
> .checkpatch.conf | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/.checkpatch.conf b/.checkpatch.conf
> index ed0c2150ba..9e40ea060b 100644
> --- a/.checkpatch.conf
> +++ b/.checkpatch.conf
> @@ -26,6 +26,9 @@
> # addresses are __aligned(2)".
> --ignore PREFER_ETHER_ADDR_COPY
>
> +# ENOSYS is a conventionally used error, even though U-Boot lacks system
> calls.
> +--ignore ENOSYS
> +
> # A bit shorter of a description is OK with us.
> --min-conf-desc-length=2
>
> --
> 2.31.0
>
Re: [PATCH] Revert "spl: Drop bd_info in the data section"
Hi Tom, Alex, On Tue, 13 Apr 2021 at 04:26, Tom Rini wrote: > > On Mon, Apr 12, 2021 at 10:21:18AM -0500, Alex G. wrote: > > > > > > On 4/12/21 9:40 AM, Tom Rini wrote: > > > On Mon, Apr 12, 2021 at 08:51:11AM -0500, Alex G. wrote: > > > > > > > > > > > > On 4/12/21 8:25 AM, Tom Rini wrote: > > > > > On Fri, Apr 09, 2021 at 05:29:36PM -0700, Tim Harvey wrote: > > > > > > On Fri, Apr 9, 2021 at 1:53 PM Tom Rini wrote: > > > > > > > > > > > > > > On Fri, Apr 09, 2021 at 03:24:41PM -0500, Adam Ford wrote: > > > > > > > > On Fri, Apr 9, 2021 at 2:20 PM Alex G. > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Simon > > > > > > > > > > > > > > > > > > On 4/8/21 6:55 PM, Simon Glass wrote: > > > > > > > > > > Hi Alexandru, > > > > > > > > > > > > > > > > > > > > On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > This reverts commit > > > > > > > > > > > 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75. > > > > > > > > > > > > > > > > > > > > > > struct global_data contains a pointer to the bd_info > > > > > > > > > > > structure. This > > > > > > > > > > > pointer was populated spl_set_bd() to a pre-allocated > > > > > > > > > > > bd_info in the > > > > > > > > > > > ".data" section. The referenced commit replaced this > > > > > > > > > > > mechanism to one > > > > > > > > > > > that uses malloc(). That new mechanism is only used if > > > > > > > > > > > SPL_ALLOC_BD=y. > > > > > > > > > > > which very few boards do. > > > > > > > > > > > > > > > > > > > > > > The result is that (struct global_data)->bd is NULL in > > > > > > > > > > > SPL on most > > > > > > > > > > > platforms. This breaks falcon mode, since > > > > > > > > > > > arch_fixup_fdt() tries to > > > > > > > > > > > access (struct global_data)->bd and set the "/memory" > > > > > > > > > > > node in the > > > > > > > > > > > devicetree. The result is that the "/memory" node > > > > > > > > > > > contains garbage > > > > > > > > > > > values, causing linux to panic() as it sets up the page > > > > > > > > > > > table. > > > > > > > > > > > > > > > > > > > > > > Instead of trying to fix the mess, potentially causing > > > > > > > > > > > other issues, > > > > > > > > > > > revert to the code that worked, while this change is > > > > > > > > > > > reworked. > > > > > > > > > > > > > > > > > > > > The goal here is to drop a feature that few boards use and > > > > > > > > > > reduce > > > > > > > > > > memory usage in SPL. It has been in place for two releases > > > > > > > > > > now. > > > > > > > > > > > > > > > > > > > > If Falcon mode needs it, perhaps you could add an 'imply' > > > > > > > > > > in the > > > > > > > > > > Kconfig for that feature? Is there one? Or perhaps > > > > > > > > > > CONFIG_ARCH_FIXUP_FDT_MEMORY ? > > > > > > > > > > > > > > > > > > > > One option would be to return an error in arch_fixup_fdt(). > > > > > > > > > > In > > > > > > > > > > general, fixups make things tricky because there is no way > > > > > > > > > > to > > > > > > > > > > determine when they are used but at least this one has a > > > > > > > > > > CONFIG. > > > > > > > > > > > > > > > > > > > > > > > > > > > > The argument that this has been in place for two releases is > > > > > > > > > incorrect. > > > > > > > > > Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only > > > > > > > > > introduced with > > > > > > > > > the v2021.04 release. It definitely was not in 2021.01. It's > > > > > > > > > only in the > > > > > > > > > last release, which is four days old t the time of this > > > > > > > > > writing. > > > > > > > > > > > > > > Yes. But another way of saying that is that we're 4 days in to > > > > > > > the > > > > > > > merge window. That's a bit early to say we must revert the > > > > > > > change. If > > > > > > > this was just before the release, yes, revert would be the right > > > > > > > answer. > > > > > > > It's also the case the original commit fixes some cases while also > > > > > > > saving size, if I read it right. So a strict revert isn't right, > > > > > > > we'd > > > > > > > need to also probably also default y SPL_ALLOC_BD in some cases. > > > > > > > > > > > > > > > > Although I was able to find one example, the reality is that > > > > > > > > > we don't > > > > > > > > > know the full extent of the breakage. The prudent thing at > > > > > > > > > this point is > > > > > > > > > to revert. > > > > > > > > > > > > > > > > > > The knowledge of how to init the platform is in the > > > > > > > > > devicetree and code. > > > > > > > > > Why should kconfig also be involved in storing this > > > > > > > > > knowledge? By this > > > > > > > > > model, as the number of boards increases without bounds, > > > > > > > > > every "if" > > > > > > > > > predicate tends to be Kconfig driven. That is not > > > > > > > > > maintainable, and why > > > > > > > > > I think the original change --and the proposed fixes-- are > > > > > > >
Re: [PATCH] Revert "spl: Drop bd_info in the data section"
On Mon, Apr 12, 2021 at 10:21:18AM -0500, Alex G. wrote: > > > On 4/12/21 9:40 AM, Tom Rini wrote: > > On Mon, Apr 12, 2021 at 08:51:11AM -0500, Alex G. wrote: > > > > > > > > > On 4/12/21 8:25 AM, Tom Rini wrote: > > > > On Fri, Apr 09, 2021 at 05:29:36PM -0700, Tim Harvey wrote: > > > > > On Fri, Apr 9, 2021 at 1:53 PM Tom Rini wrote: > > > > > > > > > > > > On Fri, Apr 09, 2021 at 03:24:41PM -0500, Adam Ford wrote: > > > > > > > On Fri, Apr 9, 2021 at 2:20 PM Alex G. > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Simon > > > > > > > > > > > > > > > > On 4/8/21 6:55 PM, Simon Glass wrote: > > > > > > > > > Hi Alexandru, > > > > > > > > > > > > > > > > > > On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > This reverts commit > > > > > > > > > > 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75. > > > > > > > > > > > > > > > > > > > > struct global_data contains a pointer to the bd_info > > > > > > > > > > structure. This > > > > > > > > > > pointer was populated spl_set_bd() to a pre-allocated > > > > > > > > > > bd_info in the > > > > > > > > > > ".data" section. The referenced commit replaced this > > > > > > > > > > mechanism to one > > > > > > > > > > that uses malloc(). That new mechanism is only used if > > > > > > > > > > SPL_ALLOC_BD=y. > > > > > > > > > > which very few boards do. > > > > > > > > > > > > > > > > > > > > The result is that (struct global_data)->bd is NULL in SPL > > > > > > > > > > on most > > > > > > > > > > platforms. This breaks falcon mode, since arch_fixup_fdt() > > > > > > > > > > tries to > > > > > > > > > > access (struct global_data)->bd and set the "/memory" node > > > > > > > > > > in the > > > > > > > > > > devicetree. The result is that the "/memory" node contains > > > > > > > > > > garbage > > > > > > > > > > values, causing linux to panic() as it sets up the page > > > > > > > > > > table. > > > > > > > > > > > > > > > > > > > > Instead of trying to fix the mess, potentially causing > > > > > > > > > > other issues, > > > > > > > > > > revert to the code that worked, while this change is > > > > > > > > > > reworked. > > > > > > > > > > > > > > > > > > The goal here is to drop a feature that few boards use and > > > > > > > > > reduce > > > > > > > > > memory usage in SPL. It has been in place for two releases > > > > > > > > > now. > > > > > > > > > > > > > > > > > > If Falcon mode needs it, perhaps you could add an 'imply' in > > > > > > > > > the > > > > > > > > > Kconfig for that feature? Is there one? Or perhaps > > > > > > > > > CONFIG_ARCH_FIXUP_FDT_MEMORY ? > > > > > > > > > > > > > > > > > > One option would be to return an error in arch_fixup_fdt(). In > > > > > > > > > general, fixups make things tricky because there is no way to > > > > > > > > > determine when they are used but at least this one has a > > > > > > > > > CONFIG. > > > > > > > > > > > > > > > > > > > > > > > > > The argument that this has been in place for two releases is > > > > > > > > incorrect. > > > > > > > > Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only > > > > > > > > introduced with > > > > > > > > the v2021.04 release. It definitely was not in 2021.01. It's > > > > > > > > only in the > > > > > > > > last release, which is four days old t the time of this writing. > > > > > > > > > > > > Yes. But another way of saying that is that we're 4 days in to the > > > > > > merge window. That's a bit early to say we must revert the change. > > > > > > If > > > > > > this was just before the release, yes, revert would be the right > > > > > > answer. > > > > > > It's also the case the original commit fixes some cases while also > > > > > > saving size, if I read it right. So a strict revert isn't right, > > > > > > we'd > > > > > > need to also probably also default y SPL_ALLOC_BD in some cases. > > > > > > > > > > > > > > Although I was able to find one example, the reality is that we > > > > > > > > don't > > > > > > > > know the full extent of the breakage. The prudent thing at this > > > > > > > > point is > > > > > > > > to revert. > > > > > > > > > > > > > > > > The knowledge of how to init the platform is in the devicetree > > > > > > > > and code. > > > > > > > > Why should kconfig also be involved in storing this knowledge? > > > > > > > > By this > > > > > > > > model, as the number of boards increases without bounds, every > > > > > > > > "if" > > > > > > > > predicate tends to be Kconfig driven. That is not maintainable, > > > > > > > > and why > > > > > > > > I think the original change --and the proposed fixes-- are > > > > > > > > broken by design. > > > > > > > > > > > > > > > > Furthermore, I'm happy to discuss what to do about Falcon mode, > > > > > > > > and if > > > > > > > > we should kill it entirely (I have an alternative proposal). > > > > > > > > But we > > > > > > > > shouldn't have that discussion in a manner holding my platform
[PATCH v2] arm: dts: k3-j721e-main: Update the speed modes supported and their itap delay values for MMCSD subsystems
According to latest errata of J721e [1], HS400 mode is not supported
in MMCSD0 subsystem (i2024) and SDR104 mode is not supported in MMCSD1/2
subsystems (i2090). Therefore, replace mmc-hs400-1_8v with mmc-hs200-1_8v
in MMCSD0 subsystem and add a sdhci mask to disable SDR104 speed mode.
Also, update the itap delay values for all the MMCSD subsystems according
the latest J721e data sheet[2]
[1] - https://www.ti.com/lit/er/sprz455/sprz455.pdf
[2] - https://www.ti.com/lit/ds/symlink/tda4vm.pdf
Fixes: 70e167495ab2 ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot")
Signed-off-by: Aswath Govindraju
---
Changes since v1:
- Corrected the fixes tag.
arch/arm/dts/k3-j721e-main.dtsi | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index e47b6c0eb706..07b489679ed9 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -1078,13 +1078,12 @@
assigned-clocks = <_clks 91 1>;
assigned-clock-parents = <_clks 91 2>;
bus-width = <8>;
- mmc-hs400-1_8v;
+ mmc-hs200-1_8v;
mmc-ddr-1_8v;
ti,otap-del-sel-legacy = <0xf>;
ti,otap-del-sel-mmc-hs = <0xf>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x6>;
- ti,otap-del-sel-hs400 = <0x0>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,itap-del-sel-ddr52 = <0x3>;
@@ -1102,14 +1101,20 @@
assigned-clocks = <_clks 92 0>;
assigned-clock-parents = <_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ ti,itap-del-sel-ddr50 = <0x2>;
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
+ sdhci-caps-mask = <0x2 0x0>;
};
main_sdhci2: sdhci@4f98000 {
@@ -1122,14 +1127,20 @@
assigned-clocks = <_clks 93 0>;
assigned-clock-parents = <_clks 93 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ ti,itap-del-sel-ddr50 = <0x2>;
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
+ sdhci-caps-mask = <0x2 0x0>;
};
usbss0: cdns-usb@4104000 {
--
2.17.1
Re: [PATCH] arm: dts: k3-j721e-main: Update the speed modes supported and their itap delay values for MMCSD subsystems
Hi all,
On 12/04/21 6:36 pm, Aswath Govindraju wrote:
> According to latest errata of J721e [1], HS400 mode is not supported
> in MMCSD0 subsystem (i2024) and SDR104 mode is not supported in MMCSD1/2
> subsystems (i2090). Therefore, replace mmc-hs400-1_8v with mmc-hs200-1_8v
> in MMCSD0 subsystem and add a sdhci mask to disable SDR104 speed mode.
>
> Also, update the itap delay values for all the MMCSD subsystems according
> the latest J721e data sheet[2]
>
> [1] - https://www.ti.com/lit/er/sprz455/sprz455.pdf
> [2] - https://www.ti.com/lit/ds/symlink/tda4vm.pdf
>
> Fixes: 52de3c324de4 ("arm: dts: k3-j721e-main: Update otap-delay values")
> Signed-off-by: Aswath Govindraju
> ---
Please ignore this patch, the fixes tag that I have used is not the
correct one. Will fix it and post a respin. Sorry about the noise.
Thanks,
Aswath
> arch/arm/dts/k3-j721e-main.dtsi | 19 +++
> 1 file changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
> index e47b6c0eb706..07b489679ed9 100644
> --- a/arch/arm/dts/k3-j721e-main.dtsi
> +++ b/arch/arm/dts/k3-j721e-main.dtsi
> @@ -1078,13 +1078,12 @@
> assigned-clocks = <_clks 91 1>;
> assigned-clock-parents = <_clks 91 2>;
> bus-width = <8>;
> - mmc-hs400-1_8v;
> + mmc-hs200-1_8v;
> mmc-ddr-1_8v;
> ti,otap-del-sel-legacy = <0xf>;
> ti,otap-del-sel-mmc-hs = <0xf>;
> ti,otap-del-sel-ddr52 = <0x5>;
> ti,otap-del-sel-hs200 = <0x6>;
> - ti,otap-del-sel-hs400 = <0x0>;
> ti,itap-del-sel-legacy = <0x10>;
> ti,itap-del-sel-mmc-hs = <0xa>;
> ti,itap-del-sel-ddr52 = <0x3>;
> @@ -1102,14 +1101,20 @@
> assigned-clocks = <_clks 92 0>;
> assigned-clock-parents = <_clks 92 1>;
> ti,otap-del-sel-legacy = <0x0>;
> - ti,otap-del-sel-sd-hs = <0xf>;
> + ti,otap-del-sel-sd-hs = <0x0>;
> ti,otap-del-sel-sdr12 = <0xf>;
> ti,otap-del-sel-sdr25 = <0xf>;
> ti,otap-del-sel-sdr50 = <0xc>;
> ti,otap-del-sel-ddr50 = <0xc>;
> + ti,itap-del-sel-legacy = <0x0>;
> + ti,itap-del-sel-sd-hs = <0x0>;
> + ti,itap-del-sel-sdr12 = <0x0>;
> + ti,itap-del-sel-sdr25 = <0x0>;
> + ti,itap-del-sel-ddr50 = <0x2>;
> ti,trm-icp = <0x8>;
> ti,clkbuf-sel = <0x7>;
> dma-coherent;
> + sdhci-caps-mask = <0x2 0x0>;
> };
>
> main_sdhci2: sdhci@4f98000 {
> @@ -1122,14 +1127,20 @@
> assigned-clocks = <_clks 93 0>;
> assigned-clock-parents = <_clks 93 1>;
> ti,otap-del-sel-legacy = <0x0>;
> - ti,otap-del-sel-sd-hs = <0xf>;
> + ti,otap-del-sel-sd-hs = <0x0>;
> ti,otap-del-sel-sdr12 = <0xf>;
> ti,otap-del-sel-sdr25 = <0xf>;
> ti,otap-del-sel-sdr50 = <0xc>;
> ti,otap-del-sel-ddr50 = <0xc>;
> + ti,itap-del-sel-legacy = <0x0>;
> + ti,itap-del-sel-sd-hs = <0x0>;
> + ti,itap-del-sel-sdr12 = <0x0>;
> + ti,itap-del-sel-sdr25 = <0x0>;
> + ti,itap-del-sel-ddr50 = <0x2>;
> ti,trm-icp = <0x8>;
> ti,clkbuf-sel = <0x7>;
> dma-coherent;
> + sdhci-caps-mask = <0x2 0x0>;
> };
>
> usbss0: cdns-usb@4104000 {
>
Re: [PATCH] Revert "spl: Drop bd_info in the data section"
On 4/12/21 9:40 AM, Tom Rini wrote:
On Mon, Apr 12, 2021 at 08:51:11AM -0500, Alex G. wrote:
On 4/12/21 8:25 AM, Tom Rini wrote:
On Fri, Apr 09, 2021 at 05:29:36PM -0700, Tim Harvey wrote:
On Fri, Apr 9, 2021 at 1:53 PM Tom Rini wrote:
On Fri, Apr 09, 2021 at 03:24:41PM -0500, Adam Ford wrote:
On Fri, Apr 9, 2021 at 2:20 PM Alex G. wrote:
Hi Simon
On 4/8/21 6:55 PM, Simon Glass wrote:
Hi Alexandru,
On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc wrote:
This reverts commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75.
struct global_data contains a pointer to the bd_info structure. This
pointer was populated spl_set_bd() to a pre-allocated bd_info in the
".data" section. The referenced commit replaced this mechanism to one
that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y.
which very few boards do.
The result is that (struct global_data)->bd is NULL in SPL on most
platforms. This breaks falcon mode, since arch_fixup_fdt() tries to
access (struct global_data)->bd and set the "/memory" node in the
devicetree. The result is that the "/memory" node contains garbage
values, causing linux to panic() as it sets up the page table.
Instead of trying to fix the mess, potentially causing other issues,
revert to the code that worked, while this change is reworked.
The goal here is to drop a feature that few boards use and reduce
memory usage in SPL. It has been in place for two releases now.
If Falcon mode needs it, perhaps you could add an 'imply' in the
Kconfig for that feature? Is there one? Or perhaps
CONFIG_ARCH_FIXUP_FDT_MEMORY ?
One option would be to return an error in arch_fixup_fdt(). In
general, fixups make things tricky because there is no way to
determine when they are used but at least this one has a CONFIG.
The argument that this has been in place for two releases is incorrect.
Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only introduced with
the v2021.04 release. It definitely was not in 2021.01. It's only in the
last release, which is four days old t the time of this writing.
Yes. But another way of saying that is that we're 4 days in to the
merge window. That's a bit early to say we must revert the change. If
this was just before the release, yes, revert would be the right answer.
It's also the case the original commit fixes some cases while also
saving size, if I read it right. So a strict revert isn't right, we'd
need to also probably also default y SPL_ALLOC_BD in some cases.
Although I was able to find one example, the reality is that we don't
know the full extent of the breakage. The prudent thing at this point is
to revert.
The knowledge of how to init the platform is in the devicetree and code.
Why should kconfig also be involved in storing this knowledge? By this
model, as the number of boards increases without bounds, every "if"
predicate tends to be Kconfig driven. That is not maintainable, and why
I think the original change --and the proposed fixes-- are broken by design.
Furthermore, I'm happy to discuss what to do about Falcon mode, and if
we should kill it entirely (I have an alternative proposal). But we
shouldn't have that discussion in a manner holding my platform hostage.
To be fair to you, I don't think reverting a 64-byte savings in .data
will hold your platform hostage either.
That original patch broke a bunch of OMAP boards, but enabling
SPL_ALLOC_BD was the solution to fix the issue.
Can you try enabling SPL_ALLOC_BD and see if that fixes it? Maybe we
can make falcon mode imply it.
It would be "select" since it needs it rather than imply.
I just ran into this as well finding that commit 38d6b7ebdaee ("spl:
Drop bd_info in the data section") breaks Gateworks Ventana and
defining SPL_ALLOC_BD does resolve it. In this case, Falcon mode is
not being used and the breakage is because arch/arm/mach-imx/spl.c
dram_init_banksize() accesses gd->bd which is NULL.
So I would guess that this probably broke a whole lot of IMX based
boards that use SPL.
I don't quite know what the best solution is... we now have a v2021.04
that is broken for several or many boards and I dont' know if its
clear what cases break.
Looking forward, I think we need to rework this. Simon, I gather you
have some platforms where we need to set gd->bd to something that we
malloc() ? So perhaps spl_set_bd() should have been __weak so that
architectures / platforms could override as needed, but also move it
just past mem_malloc_init().
Let's try and avoid making new weak functions. Why not introduce a
spl_platform_alloc_bd(), that each plat- *must* implement? No diversion to
Kconfig and no __weak__ required.
Well, who needs something different than what we had before exactly?
I'm not sure. From reading the commit message of the broken change, it
seems the main driver was to save 64 bytes on coral. I'm assuming coral
is the codename for a platform.
This shouldn't be kicked up to "every SoC must define...", but maybe
"every
Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages
Hi,
I promised to send my summary of Trusted Substrate architecture council
call on HOBs, here it is:
Topics where there seem to be consensus
- Scope include diverse firmware flows (U-Boot/SPL, TFA, CoreBoot…) on
difference architectures (Arm, RiscV)
- Definitions: The Hand Over Function is the firmware component that
hands off to the booted payload = {OS/Hypervisor/Grub/Shim}.
- Hand Over Function can be EDK2, U-Boot or LinuxBoot.
- The HOF, through ACPI or DT is responsible to describe what shall be
controlled and partly how (some parameters)
- *There is information that can only be discovered at runtime and needs
to be conveyed through the HOF to the booted payload.*
- The proposal is to convey that dynamic information in the form of
HandOverBlocks (HOBs) whose format is yet to be defined and built as a
linked list of objects. The other proposal to use call backs (mmc calls or
equivalent) from HOF to firmware is rejected. In Arm architecture, that
choice does not preclude some firmware components to use SCMI calls into
SCP to obtain authoritative information.
- The firmware components shall not care about what is the actual
HOF:the format is standard regardless if HOF is EDK2, U-Boot or LinuxBoot.
In TF-A words, the HOBs become part of the input ABI for BL33.
Characteristics to consider about HOBs:
- HOBs can be built by very early components and must fit into highly
constrained SRAM
- A HOB may be passed between different firmware components, secure and
non-secure.
- A HOB can be built by secure and non-secure firmware components
- An information can have a single format: no alternative representation
is allowed. In other words if the information is passed as a data structure
it cannot be represented by a DT fragment by another implementation and
conversely.
Topics that need more discussion
- HOBs need a way to be identified: UUID, ID, hybrid (like Platform
Initialization).
*My views: the hybrid allows constraints firmware components to be using
simple IDs and richer components may want leverage UUIDs (same as Platform
Initialization).*
- HOB format: binary information; just static structure or flatten
device tree fragments/overlays.
*My views: again hybrid approach seem very efficient. Static structures for
memory information, DT fragment for device assignment (for non-secure
partitions or for secure world / secure partitions). Typically I would
imagine a UUID HOB with a DT fragment seems just good. This is actually
implemented like that with Platform Initialization:*
*HOBs are identified by a simple ID, out of IDs are
EFI_HOB_RESOURCE_DESCRIPTOR for DRAM description and EFI_HOB_GUID_TYPE that
contains something identified by a GUID. There is a GUID used in the
context of EDK2 to actually contain a DT fragment today.*
Cheers
FF
On Mon, 12 Apr 2021 at 16:49, Mark Kettenis wrote:
> > From: Simon Glass
> > Date: Fri, 9 Apr 2021 06:19:08 +1200
> >
> > Here are a few thoughts on UUIDs.
> > Why a UUID/GUID is probably not the answer
> >
> > sjg, 30-Mar-21
> > Code is for humans
> >
> > Code should be readable, so far as possible.
> >
> > This is not readable:
> >
> > #define FSP_HOB_RESOURCE_OWNER_SMM_PEI_SMRAM_GUID \
> >
> > EFI_GUID(0x6dadf1d1, 0xd4cc, 0x4910, \
> >
> > 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d)
> >
> > This is readable:
> >
> > enum {
> >
> > BLOBLISTT_SPL_HANDOFF = 123,
> >
> > };
> > UUID is more like a hash than a sequence number
>
> No kidding. Try figuring out what an ACPI ASL methods like _DSM and
> _OSC are supposed to do when trying to figure out what the code is
> supposed to do.
>
> They're terrible to grep for in source code since there is no uniform
> way to format them in the code.
>
> And then there is the issue of byte order of course.
> ___
> boot-architecture mailing list
> boot-architect...@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/boot-architecture
>
--
François-Frédéric Ozog | *Director Linaro Edge & Fog Computing Group*
T: +33.67221.6485
francois.o...@linaro.org | Skype: ffozog
[PATCH v2 1/4] efi_loader: capsule: Remove the check for capsule_authentication_enabled environment variable
The current capsule authentication code checks if the environment
variable capsule_authentication_enabled is set, for authenticating the
capsule. This is in addition to the check for the config symbol
CONFIG_EFI_CAPSULE_AUTHENTICATE. Remove the check for the environment
variable. The capsule will now be authenticated if the config symbol
is set.
Signed-off-by: Sughosh Ganu
---
Changes since V1:
* As pointed out by Heinrich in the review, remove the extra check of
the env variable 'capsule_authentication_enabled'for authenticating
the capsule. The capsule authentication will now be done based on
whether the corresponding config symbol is enabled.
board/emulation/common/qemu_capsule.c | 6 --
lib/efi_loader/efi_firmware.c | 5 ++---
2 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/board/emulation/common/qemu_capsule.c
b/board/emulation/common/qemu_capsule.c
index 5cb461d52b..6b8a87022a 100644
--- a/board/emulation/common/qemu_capsule.c
+++ b/board/emulation/common/qemu_capsule.c
@@ -41,9 +41,3 @@ int efi_get_public_key_data(void **pkey, efi_uintn_t
*pkey_len)
return 0;
}
-
-bool efi_capsule_auth_enabled(void)
-{
- return env_get("capsule_authentication_enabled") != NULL ?
- true : false;
-}
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index 7a3cca2793..a1b88dbfc2 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -190,7 +190,7 @@ static efi_status_t efi_get_dfu_info(
IMAGE_ATTRIBUTE_IMAGE_UPDATABLE;
/* Check if the capsule authentication is enabled */
- if (env_get("capsule_authentication_enabled"))
+ if (IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE))
image_info[0].attributes_setting |=
IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED;
@@ -421,8 +421,7 @@ efi_status_t EFIAPI efi_firmware_raw_set_image(
return EFI_EXIT(EFI_INVALID_PARAMETER);
/* Authenticate the capsule if authentication enabled */
- if (IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE) &&
- env_get("capsule_authentication_enabled")) {
+ if (IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)) {
capsule_payload = NULL;
capsule_payload_size = 0;
status = efi_capsule_authenticate(image, image_size,
--
2.17.1
[PATCH v2 0/4] Add support for embedding public key in platform's dtb
These patches add support for embedding the public key efi signature list(esl) file into the platform's device tree. The current solution for the Qemu arm64 platform has the public key as part of an overlay, and stored on the Efi System Partition(ESP). Having the provision to embed the public key into the platform's dtb which is then concatenated with the u-boot binary is a better approach, recommended by Heinrich[1]. Patch 1 removes the existing additional check for authenticating the capsule using the env variable. Patch 2 add two config symbols, EFI_PKEY_DTB_EMBED and EFI_PKEY_FILE which are used for enabling embedding of the public key in the dtb, and specifying the esl file name. Patch 3 adds a function for retrieving the public key which has been embedded in the platform's dtb. Patch 4 adds the functionality to embed the esl file into the platform's dtb during the platform build. I have tested this functionality on the STM32MP157C DK2 board, and it works as expected. [1] - https://lists.denx.de/pipermail/u-boot/2021-March/442867.html Changes since V1: * As pointed out by Heinrich in the review, remove the extra check of the env variable 'capsule_authentication_enabled'for authenticating the capsule. The capsule authentication will now be done based on whether the corresponding config symbol is enabled. * Provide a default name for public key file, eficapsule.esl as suggested by Heinrich. * Remove the superfluous default n statement for EFI_PKEY_DTB_EMBED * Remove the weak function, and add the functionality to retrieve the public key under the config symbol CONFIG_EFI_PKEY_DTB_EMBED. Sughosh Ganu (4): efi_loader: capsule: Remove the check for capsule_authentication_enabled environment variable efi_loader: Kconfig: Add symbols for embedding the public key into the platform's dtb efi_capsule: Add a function to get the public key needed for capsule authentication Makefile: Add provision for embedding public key in platform's dtb Makefile | 10 +++ board/emulation/common/qemu_capsule.c | 6 lib/efi_loader/Kconfig| 15 ++ lib/efi_loader/efi_capsule.c | 43 +++ lib/efi_loader/efi_firmware.c | 5 ++-- 5 files changed, 65 insertions(+), 14 deletions(-) -- 2.17.1
[PATCH v2 4/4] Makefile: Add provision for embedding public key in platform's dtb
Add provision for embedding the public key used for capsule
authentication in the platform's dtb. This is done by invoking the
mkeficapsule utility which puts the public key in the efi signature
list(esl) format into the dtb.
Signed-off-by: Sughosh Ganu
---
Changes since V1: None
Makefile | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Makefile b/Makefile
index b72d8d20c0..ebd4a6477c 100644
--- a/Makefile
+++ b/Makefile
@@ -1011,6 +1011,10 @@ cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@;
false; }
quiet_cmd_lzma = LZMA$@
cmd_lzma = lzma -c -z -k -9 $< > $@
+quiet_cmd_mkeficapsule = MKEFICAPSULE $@
+cmd_mkeficapsule = $(objtree)/tools/mkeficapsule -K $(CONFIG_EFI_PKEY_FILE) \
+ -D $@
+
cfg: u-boot.cfg
quiet_cmd_cfgcheck = CFGCHK $2
@@ -1161,8 +1165,14 @@ endif
PHONY += dtbs
dtbs: dts/dt.dtb
@:
+ifeq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE)$(CONFIG_EFI_PKEY_DTB_EMBED),yy)
+dts/dt.dtb: u-boot tools
+ $(Q)$(MAKE) $(build)=dts dtbs
+ $(call cmd,mkeficapsule)
+else
dts/dt.dtb: u-boot
$(Q)$(MAKE) $(build)=dts dtbs
+endif
quiet_cmd_copy = COPY$@
cmd_copy = cp $< $@
--
2.17.1
[PATCH v2 3/4] efi_capsule: Add a function to get the public key needed for capsule authentication
Define a function which would be used in the scenario where the
public key is stored on the platform's dtb. This dtb is concatenated
with the u-boot binary during the build process. Platforms which have
a different mechanism for getting the public key would define their
own platform specific function under a different Kconfig symbol.
Signed-off-by: Sughosh Ganu
---
Changes since V1:
* Remove the weak function, and add the functionality to retrieve the
public key under the config symbol CONFIG_EFI_PKEY_DTB_EMBED.
lib/efi_loader/efi_capsule.c | 43 +++-
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 2cc8f2dee0..d95e9377fe 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -14,10 +14,13 @@
#include
#include
+#include
#include
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID;
static const efi_guid_t efi_guid_firmware_management_capsule_id =
EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
@@ -208,15 +211,45 @@ skip:
const efi_guid_t efi_guid_capsule_root_cert_guid =
EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
-__weak int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
+#if defined(CONFIG_EFI_PKEY_DTB_EMBED)
+int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
{
- /* The platform is supposed to provide
-* a method for getting the public key
-* stored in the form of efi signature
-* list
+ /*
+* This is a function for retrieving the public key from the
+* platform's device tree. The platform's device tree has been
+* concatenated with the u-boot binary.
+* If a platform has a different mechanism to get the public
+* key, it can define it's own kconfig symbol and define a
+* function to retrieve the public key
*/
+ const void *fdt_blob = gd->fdt_blob;
+ const void *blob;
+ const char *cnode_name = "capsule-key";
+ const char *snode_name = "signature";
+ int sig_node;
+ int len;
+
+ sig_node = fdt_subnode_offset(fdt_blob, 0, snode_name);
+ if (sig_node < 0) {
+ EFI_PRINT("Unable to get signature node offset\n");
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ blob = fdt_getprop(fdt_blob, sig_node, cnode_name, );
+
+ if (!blob || len < 0) {
+ EFI_PRINT("Unable to get capsule-key value\n");
+ *pkey = NULL;
+ *pkey_len = 0;
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ *pkey = (void *)blob;
+ *pkey_len = len;
+
return 0;
}
+#endif /* CONFIG_EFI_PKEY_DTB_EMBED */
efi_status_t efi_capsule_authenticate(const void *capsule, efi_uintn_t
capsule_size,
void **image, efi_uintn_t *image_size)
--
2.17.1
[PATCH v2 2/4] efi_loader: Kconfig: Add symbols for embedding the public key into the platform's dtb
Add config options EFI_PKEY_DTB_EMBED and EFI_PKEY_FILE which are to be used for embedding the public key to be used for capsule authentication into the platform's device tree. The embedding of the public key would take place during the platform build process. Signed-off-by: Sughosh Ganu --- Changes since V1: * Provide a default name for public key file, eficapsule.esl as suggested by Heinrich. * Remove the superfluous default n statement for EFI_PKEY_DTB_EMBED lib/efi_loader/Kconfig | 15 +++ 1 file changed, 15 insertions(+) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 79b488823a..089acc 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -179,6 +179,21 @@ config EFI_CAPSULE_AUTHENTICATE Select this option if you want to enable capsule authentication +config EFI_PKEY_DTB_EMBED + bool "Embed the public key in the Device Tree" + depends on EFI_CAPSULE_AUTHENTICATE + help + Select this option if the public key used for capsule + authentication is to be embedded into the platform's + device tree. + +config EFI_PKEY_FILE + string "Public Key esl file to be embedded into the Device Tree" + default "eficapsule.esl" + help + Specify the absolute path of the public key esl file that is + to be embedded in the platform's device tree. + config EFI_CAPSULE_FIRMWARE_FIT bool "FMP driver for FIT image" depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT -- 2.17.1
Re: [PATCH] Revert "spl: Drop bd_info in the data section"
On Mon, Apr 12, 2021 at 08:51:11AM -0500, Alex G. wrote:
>
>
> On 4/12/21 8:25 AM, Tom Rini wrote:
> > On Fri, Apr 09, 2021 at 05:29:36PM -0700, Tim Harvey wrote:
> > > On Fri, Apr 9, 2021 at 1:53 PM Tom Rini wrote:
> > > >
> > > > On Fri, Apr 09, 2021 at 03:24:41PM -0500, Adam Ford wrote:
> > > > > On Fri, Apr 9, 2021 at 2:20 PM Alex G. wrote:
> > > > > >
> > > > > > Hi Simon
> > > > > >
> > > > > > On 4/8/21 6:55 PM, Simon Glass wrote:
> > > > > > > Hi Alexandru,
> > > > > > >
> > > > > > > On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > This reverts commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75.
> > > > > > > >
> > > > > > > > struct global_data contains a pointer to the bd_info structure.
> > > > > > > > This
> > > > > > > > pointer was populated spl_set_bd() to a pre-allocated bd_info
> > > > > > > > in the
> > > > > > > > ".data" section. The referenced commit replaced this mechanism
> > > > > > > > to one
> > > > > > > > that uses malloc(). That new mechanism is only used if
> > > > > > > > SPL_ALLOC_BD=y.
> > > > > > > > which very few boards do.
> > > > > > > >
> > > > > > > > The result is that (struct global_data)->bd is NULL in SPL on
> > > > > > > > most
> > > > > > > > platforms. This breaks falcon mode, since arch_fixup_fdt()
> > > > > > > > tries to
> > > > > > > > access (struct global_data)->bd and set the "/memory" node in
> > > > > > > > the
> > > > > > > > devicetree. The result is that the "/memory" node contains
> > > > > > > > garbage
> > > > > > > > values, causing linux to panic() as it sets up the page table.
> > > > > > > >
> > > > > > > > Instead of trying to fix the mess, potentially causing other
> > > > > > > > issues,
> > > > > > > > revert to the code that worked, while this change is reworked.
> > > > > > >
> > > > > > > The goal here is to drop a feature that few boards use and reduce
> > > > > > > memory usage in SPL. It has been in place for two releases now.
> > > > > > >
> > > > > > > If Falcon mode needs it, perhaps you could add an 'imply' in the
> > > > > > > Kconfig for that feature? Is there one? Or perhaps
> > > > > > > CONFIG_ARCH_FIXUP_FDT_MEMORY ?
> > > > > > >
> > > > > > > One option would be to return an error in arch_fixup_fdt(). In
> > > > > > > general, fixups make things tricky because there is no way to
> > > > > > > determine when they are used but at least this one has a CONFIG.
> > > > > > >
> > > > > >
> > > > > > The argument that this has been in place for two releases is
> > > > > > incorrect.
> > > > > > Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only introduced
> > > > > > with
> > > > > > the v2021.04 release. It definitely was not in 2021.01. It's only
> > > > > > in the
> > > > > > last release, which is four days old t the time of this writing.
> > > >
> > > > Yes. But another way of saying that is that we're 4 days in to the
> > > > merge window. That's a bit early to say we must revert the change. If
> > > > this was just before the release, yes, revert would be the right answer.
> > > > It's also the case the original commit fixes some cases while also
> > > > saving size, if I read it right. So a strict revert isn't right, we'd
> > > > need to also probably also default y SPL_ALLOC_BD in some cases.
> > > >
> > > > > > Although I was able to find one example, the reality is that we
> > > > > > don't
> > > > > > know the full extent of the breakage. The prudent thing at this
> > > > > > point is
> > > > > > to revert.
> > > > > >
> > > > > > The knowledge of how to init the platform is in the devicetree and
> > > > > > code.
> > > > > > Why should kconfig also be involved in storing this knowledge? By
> > > > > > this
> > > > > > model, as the number of boards increases without bounds, every "if"
> > > > > > predicate tends to be Kconfig driven. That is not maintainable, and
> > > > > > why
> > > > > > I think the original change --and the proposed fixes-- are broken
> > > > > > by design.
> > > > > >
> > > > > > Furthermore, I'm happy to discuss what to do about Falcon mode, and
> > > > > > if
> > > > > > we should kill it entirely (I have an alternative proposal). But we
> > > > > > shouldn't have that discussion in a manner holding my platform
> > > > > > hostage.
> > > > > > To be fair to you, I don't think reverting a 64-byte savings in
> > > > > > .data
> > > > > > will hold your platform hostage either.
> > > > >
> > > > > That original patch broke a bunch of OMAP boards, but enabling
> > > > > SPL_ALLOC_BD was the solution to fix the issue.
> > > > > Can you try enabling SPL_ALLOC_BD and see if that fixes it? Maybe we
> > > > > can make falcon mode imply it.
> > > >
> > > > It would be "select" since it needs it rather than imply.
> > > >
> > >
> > > I just ran into this as well finding that commit 38d6b7ebdaee ("spl:
> > > Drop bd_info in the data section") breaks Gateworks Ventana and
> > > defining
Re: [PATCH] Revert "spl: Drop bd_info in the data section"
On 4/12/21 8:25 AM, Tom Rini wrote:
On Fri, Apr 09, 2021 at 05:29:36PM -0700, Tim Harvey wrote:
On Fri, Apr 9, 2021 at 1:53 PM Tom Rini wrote:
On Fri, Apr 09, 2021 at 03:24:41PM -0500, Adam Ford wrote:
On Fri, Apr 9, 2021 at 2:20 PM Alex G. wrote:
Hi Simon
On 4/8/21 6:55 PM, Simon Glass wrote:
Hi Alexandru,
On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc wrote:
This reverts commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75.
struct global_data contains a pointer to the bd_info structure. This
pointer was populated spl_set_bd() to a pre-allocated bd_info in the
".data" section. The referenced commit replaced this mechanism to one
that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y.
which very few boards do.
The result is that (struct global_data)->bd is NULL in SPL on most
platforms. This breaks falcon mode, since arch_fixup_fdt() tries to
access (struct global_data)->bd and set the "/memory" node in the
devicetree. The result is that the "/memory" node contains garbage
values, causing linux to panic() as it sets up the page table.
Instead of trying to fix the mess, potentially causing other issues,
revert to the code that worked, while this change is reworked.
The goal here is to drop a feature that few boards use and reduce
memory usage in SPL. It has been in place for two releases now.
If Falcon mode needs it, perhaps you could add an 'imply' in the
Kconfig for that feature? Is there one? Or perhaps
CONFIG_ARCH_FIXUP_FDT_MEMORY ?
One option would be to return an error in arch_fixup_fdt(). In
general, fixups make things tricky because there is no way to
determine when they are used but at least this one has a CONFIG.
The argument that this has been in place for two releases is incorrect.
Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only introduced with
the v2021.04 release. It definitely was not in 2021.01. It's only in the
last release, which is four days old t the time of this writing.
Yes. But another way of saying that is that we're 4 days in to the
merge window. That's a bit early to say we must revert the change. If
this was just before the release, yes, revert would be the right answer.
It's also the case the original commit fixes some cases while also
saving size, if I read it right. So a strict revert isn't right, we'd
need to also probably also default y SPL_ALLOC_BD in some cases.
Although I was able to find one example, the reality is that we don't
know the full extent of the breakage. The prudent thing at this point is
to revert.
The knowledge of how to init the platform is in the devicetree and code.
Why should kconfig also be involved in storing this knowledge? By this
model, as the number of boards increases without bounds, every "if"
predicate tends to be Kconfig driven. That is not maintainable, and why
I think the original change --and the proposed fixes-- are broken by design.
Furthermore, I'm happy to discuss what to do about Falcon mode, and if
we should kill it entirely (I have an alternative proposal). But we
shouldn't have that discussion in a manner holding my platform hostage.
To be fair to you, I don't think reverting a 64-byte savings in .data
will hold your platform hostage either.
That original patch broke a bunch of OMAP boards, but enabling
SPL_ALLOC_BD was the solution to fix the issue.
Can you try enabling SPL_ALLOC_BD and see if that fixes it? Maybe we
can make falcon mode imply it.
It would be "select" since it needs it rather than imply.
I just ran into this as well finding that commit 38d6b7ebdaee ("spl:
Drop bd_info in the data section") breaks Gateworks Ventana and
defining SPL_ALLOC_BD does resolve it. In this case, Falcon mode is
not being used and the breakage is because arch/arm/mach-imx/spl.c
dram_init_banksize() accesses gd->bd which is NULL.
So I would guess that this probably broke a whole lot of IMX based
boards that use SPL.
I don't quite know what the best solution is... we now have a v2021.04
that is broken for several or many boards and I dont' know if its
clear what cases break.
Looking forward, I think we need to rework this. Simon, I gather you
have some platforms where we need to set gd->bd to something that we
malloc() ? So perhaps spl_set_bd() should have been __weak so that
architectures / platforms could override as needed, but also move it
just past mem_malloc_init().
Let's try and avoid making new weak functions. Why not introduce a
spl_platform_alloc_bd(), that each plat- *must* implement? No diversion
to Kconfig and no __weak__ required.
Alex
[PATCH v2 2/2] configs: rpi: Enable SMBIOS sysinfo driver
From: Matthias Brugger Enable this driver to allow U-Boot to get SMBIOS table information from a device tree node. Signed-off-by: Matthias Brugger Acked-by: Fabian Vogt --- Changes in v2: - fix typo in commit message configs/rpi_0_w_defconfig | 2 ++ configs/rpi_2_defconfig| 2 ++ configs/rpi_3_32b_defconfig| 2 ++ configs/rpi_3_b_plus_defconfig | 2 ++ configs/rpi_3_defconfig| 2 ++ configs/rpi_4_32b_defconfig| 2 ++ configs/rpi_4_defconfig| 2 ++ configs/rpi_arm64_defconfig| 2 ++ configs/rpi_defconfig | 2 ++ 9 files changed, 18 insertions(+) diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index c0a9b6c788..206be1590c 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -28,6 +28,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 33e0ef6989..d3d62f3028 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -28,6 +28,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index 15c62adc69..b69bc05833 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -30,6 +30,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index ebab0b4f86..8316a43116 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -30,6 +30,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index daeb6d1b64..bdfac3f31a 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -30,6 +30,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 0cbdd5fee1..7a10d4b0d4 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -39,6 +39,8 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_IPROC200=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 3f21f99edb..5d889df794 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -39,6 +39,8 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_IPROC200=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index d282d509ce..af45178962 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -36,6 +36,8 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_IPROC200=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 06b390d907..af084c8505 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -28,6 +28,8 @@ CONFIG_DM_ETH=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -- 2.30.2
[PATCH v2 1/2] arm: dts: bcm283x: Add minimal smbios information
From: Matthias Brugger
At present SMBIOS tables are empty, which breaks some use-cases that
rely on that. Add some minimal information to fulfill this.
Signed-off-by: Matthias Brugger
---
Changes in v2:
- drop product from chassi
- fix typo in commit message
arch/arm/dts/bcm283x-u-boot.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/dts/bcm283x-u-boot.dtsi b/arch/arm/dts/bcm283x-u-boot.dtsi
index 68d03627f4..22c67c4218 100644
--- a/arch/arm/dts/bcm283x-u-boot.dtsi
+++ b/arch/arm/dts/bcm283x-u-boot.dtsi
@@ -6,6 +6,25 @@
* (C) Copyright 2016 Fabian Vogt
*/
+/ {
+ smbios {
+ compatible = "u-boot,sysinfo-smbios";
+ smbios {
+ system {
+ manufacturer = "raspberrypi";
+ product = "rpi";
+ };
+ baseboard {
+ manufacturer = "raspberrypi";
+ product = "rpi";
+ };
+ chassis {
+ manufacturer = "raspberrypi";
+ };
+ };
+ };
+};
+
{
skip-init;
u-boot,dm-pre-reloc;
--
2.30.2
Re: [PATCH 1/2] arm: dts: bcm283x: Add minimal smbios information
On Fri, Apr 09, 2021 at 03:13:25PM +0200, Fabian Vogt wrote:
> Am Freitag, 9. April 2021, 14:35:10 CEST schrieb matthias@kernel.org:
> > From: Matthias Brugger
> >
> > At present SMBIOS tables are emtpy,
> ^ typo
>
> > which breaks some use-cases that rely on that.
> Can you give an example?
Management software that want's to know what HW a node is based on.
>
> > Add some minimal information to
> Isn't it possible to get the complete information from the firmware here?
> That would allow to have the correct product and serial at least.
That's the plan for the long run.
> If that's not possible or too complex, then I suggest to use the proper
> strings, e.g. "Raspberry Pi", as those are user visible.
I'd like to stay backwards compatible to older U-Boot versions for now.
>
> > fullfill this.
> ^ typo
>
> > Signed-off-by: Matthias Brugger
> > ---
> >
> > arch/arm/dts/bcm283x-u-boot.dtsi | 20
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/arch/arm/dts/bcm283x-u-boot.dtsi
> > b/arch/arm/dts/bcm283x-u-boot.dtsi
> > index 68d03627f4..f5235cb083 100644
> > --- a/arch/arm/dts/bcm283x-u-boot.dtsi
> > +++ b/arch/arm/dts/bcm283x-u-boot.dtsi
> > @@ -6,6 +6,26 @@
> > * (C) Copyright 2016 Fabian Vogt
> > */
> >
> > +/ {
> > + smbios {
> > + compatible = "u-boot,sysinfo-smbios";
> > + smbios {
> > + system {
> > + manufacturer = "raspberrypi";
> > + product = "rpi";
> > + };
> > + baseboard {
> > + manufacturer = "raspberrypi";
> > + product = "rpi";
> > + };
> > + chassis {
> > + manufacturer = "raspberrypi";
> > + product = "rpi";
>
> According to doc/device-tree-bindings/sysinfo/smbios.txt, "chassis"
> doesn't have a "product".
>
You are correct. I'll fix the typos and this in the next version.
Regards,
Matthias
> Cheers,
> Fabian
>
> > + };
> > + };
> > + };
> > +};
> > +
> > {
> > skip-init;
> > u-boot,dm-pre-reloc;
> >
>
Re: [PATCH] Revert "spl: Drop bd_info in the data section"
On Fri, Apr 09, 2021 at 05:29:36PM -0700, Tim Harvey wrote:
> On Fri, Apr 9, 2021 at 1:53 PM Tom Rini wrote:
> >
> > On Fri, Apr 09, 2021 at 03:24:41PM -0500, Adam Ford wrote:
> > > On Fri, Apr 9, 2021 at 2:20 PM Alex G. wrote:
> > > >
> > > > Hi Simon
> > > >
> > > > On 4/8/21 6:55 PM, Simon Glass wrote:
> > > > > Hi Alexandru,
> > > > >
> > > > > On Fri, 9 Apr 2021 at 04:56, Alexandru Gagniuc
> > > > > wrote:
> > > > >>
> > > > >> This reverts commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75.
> > > > >>
> > > > >> struct global_data contains a pointer to the bd_info structure. This
> > > > >> pointer was populated spl_set_bd() to a pre-allocated bd_info in the
> > > > >> ".data" section. The referenced commit replaced this mechanism to one
> > > > >> that uses malloc(). That new mechanism is only used if
> > > > >> SPL_ALLOC_BD=y.
> > > > >> which very few boards do.
> > > > >>
> > > > >> The result is that (struct global_data)->bd is NULL in SPL on most
> > > > >> platforms. This breaks falcon mode, since arch_fixup_fdt() tries to
> > > > >> access (struct global_data)->bd and set the "/memory" node in the
> > > > >> devicetree. The result is that the "/memory" node contains garbage
> > > > >> values, causing linux to panic() as it sets up the page table.
> > > > >>
> > > > >> Instead of trying to fix the mess, potentially causing other issues,
> > > > >> revert to the code that worked, while this change is reworked.
> > > > >
> > > > > The goal here is to drop a feature that few boards use and reduce
> > > > > memory usage in SPL. It has been in place for two releases now.
> > > > >
> > > > > If Falcon mode needs it, perhaps you could add an 'imply' in the
> > > > > Kconfig for that feature? Is there one? Or perhaps
> > > > > CONFIG_ARCH_FIXUP_FDT_MEMORY ?
> > > > >
> > > > > One option would be to return an error in arch_fixup_fdt(). In
> > > > > general, fixups make things tricky because there is no way to
> > > > > determine when they are used but at least this one has a CONFIG.
> > > > >
> > > >
> > > > The argument that this has been in place for two releases is incorrect.
> > > > Commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75 was only introduced with
> > > > the v2021.04 release. It definitely was not in 2021.01. It's only in the
> > > > last release, which is four days old t the time of this writing.
> >
> > Yes. But another way of saying that is that we're 4 days in to the
> > merge window. That's a bit early to say we must revert the change. If
> > this was just before the release, yes, revert would be the right answer.
> > It's also the case the original commit fixes some cases while also
> > saving size, if I read it right. So a strict revert isn't right, we'd
> > need to also probably also default y SPL_ALLOC_BD in some cases.
> >
> > > > Although I was able to find one example, the reality is that we don't
> > > > know the full extent of the breakage. The prudent thing at this point is
> > > > to revert.
> > > >
> > > > The knowledge of how to init the platform is in the devicetree and code.
> > > > Why should kconfig also be involved in storing this knowledge? By this
> > > > model, as the number of boards increases without bounds, every "if"
> > > > predicate tends to be Kconfig driven. That is not maintainable, and why
> > > > I think the original change --and the proposed fixes-- are broken by
> > > > design.
> > > >
> > > > Furthermore, I'm happy to discuss what to do about Falcon mode, and if
> > > > we should kill it entirely (I have an alternative proposal). But we
> > > > shouldn't have that discussion in a manner holding my platform hostage.
> > > > To be fair to you, I don't think reverting a 64-byte savings in .data
> > > > will hold your platform hostage either.
> > >
> > > That original patch broke a bunch of OMAP boards, but enabling
> > > SPL_ALLOC_BD was the solution to fix the issue.
> > > Can you try enabling SPL_ALLOC_BD and see if that fixes it? Maybe we
> > > can make falcon mode imply it.
> >
> > It would be "select" since it needs it rather than imply.
> >
>
> I just ran into this as well finding that commit 38d6b7ebdaee ("spl:
> Drop bd_info in the data section") breaks Gateworks Ventana and
> defining SPL_ALLOC_BD does resolve it. In this case, Falcon mode is
> not being used and the breakage is because arch/arm/mach-imx/spl.c
> dram_init_banksize() accesses gd->bd which is NULL.
>
> So I would guess that this probably broke a whole lot of IMX based
> boards that use SPL.
>
> I don't quite know what the best solution is... we now have a v2021.04
> that is broken for several or many boards and I dont' know if its
> clear what cases break.
Looking forward, I think we need to rework this. Simon, I gather you
have some platforms where we need to set gd->bd to something that we
malloc() ? So perhaps spl_set_bd() should have been __weak so that
architectures / platforms could override as needed, but also move it
just past mem_malloc_init().
--
Tom
[PATCH] arm: dts: k3-j721e-main: Update the speed modes supported and their itap delay values for MMCSD subsystems
According to latest errata of J721e [1], HS400 mode is not supported
in MMCSD0 subsystem (i2024) and SDR104 mode is not supported in MMCSD1/2
subsystems (i2090). Therefore, replace mmc-hs400-1_8v with mmc-hs200-1_8v
in MMCSD0 subsystem and add a sdhci mask to disable SDR104 speed mode.
Also, update the itap delay values for all the MMCSD subsystems according
the latest J721e data sheet[2]
[1] - https://www.ti.com/lit/er/sprz455/sprz455.pdf
[2] - https://www.ti.com/lit/ds/symlink/tda4vm.pdf
Fixes: 52de3c324de4 ("arm: dts: k3-j721e-main: Update otap-delay values")
Signed-off-by: Aswath Govindraju
---
arch/arm/dts/k3-j721e-main.dtsi | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index e47b6c0eb706..07b489679ed9 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -1078,13 +1078,12 @@
assigned-clocks = <_clks 91 1>;
assigned-clock-parents = <_clks 91 2>;
bus-width = <8>;
- mmc-hs400-1_8v;
+ mmc-hs200-1_8v;
mmc-ddr-1_8v;
ti,otap-del-sel-legacy = <0xf>;
ti,otap-del-sel-mmc-hs = <0xf>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x6>;
- ti,otap-del-sel-hs400 = <0x0>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,itap-del-sel-ddr52 = <0x3>;
@@ -1102,14 +1101,20 @@
assigned-clocks = <_clks 92 0>;
assigned-clock-parents = <_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ ti,itap-del-sel-ddr50 = <0x2>;
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
+ sdhci-caps-mask = <0x2 0x0>;
};
main_sdhci2: sdhci@4f98000 {
@@ -1122,14 +1127,20 @@
assigned-clocks = <_clks 93 0>;
assigned-clock-parents = <_clks 93 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ ti,itap-del-sel-ddr50 = <0x2>;
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
+ sdhci-caps-mask = <0x2 0x0>;
};
usbss0: cdns-usb@4104000 {
--
2.17.1
Weird issue when trying to access to uboot environment from Linux
Hello,
I am facing a strange/weird issue when trying to access to filesystem
based (/boot/uboot.env) in STM32MP157c-dk2 evaluation board.
Uboot is 2020.07-rc5 from github, the board DEVICETREE is
stm32mp157c-dk2, the kernel is from Robert C.Nelson repository (from
DigiKey EEWiki) and it is 5.12.0-rc6 with some patches applied during
built time.
The FSBL1 and FSBL2 and SSBL are written in the specific partitions.
The linux filesystem has 3 partitions: /boot (for kernel, devicetrees
and uboot.env) as EXT4 filesystem, / (for Debian 11 Bullseye
rootfilesystem) and /recoveryfs has a Debian 10 minimal bootstrap
configuration.
Usually UBoot is looking for the bit 2 of each partition (bootable flag)
and look for extlinux.conf configuration.
This configuration file is with a couple of entries:
label Linux 5.12.0-rc6-armv7-lpae-x7
kernel /vmlinuz-5.12.0-rc6-armv7-lpae-x7
append console=ttySTM0,115200 root=/dev/mmcblk0p6 ro rootfstype=ext4
rootwait noswap mem=512M
fdtdir /dtbs/5.12.0-rc6-armv7-lpae-x7/
devicetree /dtbs/5.12.0-rc6-armv7-lpae-x7/stm32mp157c-dk2.dtb
label Recovery 5.12.0-rc6-armv7-lpae-x7
kernel /vmlinuz-5.12.0-rc6-armv7-lpae-x7
append console=ttySTM0,115200 root=/dev/mmcblk0p5 ro rootfstype=ext4
rootwait noswap mem=512M recovery
fdtdir /dtbs/5.12.0-rc6-armv7-lpae-x7/
devicetree /dtbs/5.12.0-rc6-armv7-lpae-x7/stm32mp157c-dk2.dtb
Linux & Recovery.
Linux is Debian 11 Bullseye and Recovery is Debian 10 Minimal Install.
My goal at the moment is to add the ethaddr environment variable to the
/boot/uboot.env (EXT4) configuration file.
Using the u-boot tools with fw_printenv it fails with:
# fw_printenv
Cannot read environment, using default
Cannot read default environment from file
The file /etc/fw_env.config has only one entry:
/boot/uboot.env 0x 0x4000
The file itself is 8192 bytes (0x4000 == 16384) but the fw_env.config is
(partially) wrong. I do not know if this extra information are used when
accessing a file-system-based u-boot environment anyway.
Following strace fw_printenv here is the culprit:
execve("/usr/bin/fw_printenv", ["fw_printenv"], 0xbeaf6770 /* 20 vars */) = 0
brk(NULL) = 0x92f000
mmap2(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) =
0xb6fb2000
access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory)
openat(AT_FDCWD, "/etc/ld.so.cache", O_RDONLY|O_LARGEFILE|O_CLOEXEC) = 3
fstat64(3, {st_mode=S_IFREG|0644, st_size=118003, ...}) = 0
mmap2(NULL, 118003, PROT_READ, MAP_PRIVATE, 3, 0) = 0xb6f6e000
close(3)= 0
openat(AT_FDCWD, "/usr/lib/arm-linux-gnueabihf/libubootenv.so.0.3",
O_RDONLY|O_LARGEFILE|O_CLOEXEC) = 3
read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0(\0\1\0\0\0\320\f\0\0004\0\0\0"...,
512) = 512
fstat64(3, {st_mode=S_IFREG|0644, st_size=13784, ...}) = 0
mmap2(NULL, 78040, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) =
0xb6f5a000
mprotect(0xb6f5d000, 61440, PROT_NONE) = 0
mmap2(0xb6f6c000, 8192, PROT_READ|PROT_WRITE,
MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0xb6f6c000
close(3)= 0
openat(AT_FDCWD, "/lib/arm-linux-gnueabihf/libz.so.1",
O_RDONLY|O_LARGEFILE|O_CLOEXEC) = 3
read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0(\0\1\0\0\0h\32\0\0004\0\0\0"...,
512) = 512
fstat64(3, {st_mode=S_IFREG|0644, st_size=75404, ...}) = 0
mmap2(NULL, 139500, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) =
0xb6f37000
mprotect(0xb6f49000, 61440, PROT_NONE) = 0
mmap2(0xb6f58000, 8192, PROT_READ|PROT_WRITE,
MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x11000) = 0xb6f58000
close(3)= 0
openat(AT_FDCWD, "/lib/arm-linux-gnueabihf/libc.so.6",
O_RDONLY|O_LARGEFILE|O_CLOEXEC) = 3
read(3, "\177ELF\1\1\1\3\0\0\0\0\0\0\0\0\3\0(\0\1\0\0\0Y\253\1\0004\0\0\0"...,
512) = 512
fstat64(3, {st_mode=S_IFREG|0755, st_size=973416, ...}) = 0
mmap2(NULL, 1042632, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) =
0xb6e38000
mprotect(0xb6f22000, 61440, PROT_NONE) = 0
mmap2(0xb6f31000, 16384, PROT_READ|PROT_WRITE,
MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xe9000) = 0xb6f31000
mmap2(0xb6f35000, 6344, PROT_READ|PROT_WRITE,
MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0xb6f35000
close(3)= 0
set_tls(0xb6fb3580) = 0
mprotect(0xb6f31000, 8192, PROT_READ) = 0
mprotect(0xb6f58000, 4096, PROT_READ) = 0
mprotect(0xb6f6c000, 4096, PROT_READ) = 0
mprotect(0x431000, 4096, PROT_READ) = 0
mprotect(0xb6fb4000, 4096, PROT_READ) = 0
munmap(0xb6f6e000, 118003) = 0
brk(NULL) = 0x92f000
brk(0x95) = 0x95
Now the interesting stuff:
openat(AT_FDCWD, "/etc/fw_env.config", O_RDONLY) = 3
fstat64(3, {st_mode=S_IFREG|0644, st_size=36, ...}) = 0
read(3, "/boot/uboot.env0x0x4"..., 4096) = 36
lstat64("/boot", {st_mode=S_IFDIR|0755,
Re: [PATCH 1/1] cmd/exception: support ebreak exception on RISC-V
On Fri, Apr 9, 2021 at 6:48 PM Heinrich Schuchardt wrote: > > The ebreak instruction should generate a breakpoint exception. > > Signed-off-by: Heinrich Schuchardt > --- > cmd/riscv/exception.c | 10 ++ > doc/usage/exception.rst | 3 +++ > 2 files changed, 13 insertions(+) > Reviewed-by: Bin Meng
[PATCH 22/37] drivers: misc: s400_api: Update S400_SUCCESS_IND to 0xd6
From: Ye Li According to latest S400 API doc, the the success indicate value is changed to 0xd6. So update the driver codes. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/misc/imx8ulp/imx8ulp_mu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/imx8ulp/imx8ulp_mu.c index 3f6dd558e6..f3ca5473e3 100644 --- a/drivers/misc/imx8ulp/imx8ulp_mu.c +++ b/drivers/misc/imx8ulp/imx8ulp_mu.c @@ -185,7 +185,7 @@ static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg, } result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0]; - if ((result & 0xff) == 0) + if ((result & 0xff) == 0xd6) return 0; return -EIO; -- 2.30.0
[PATCH 12/37] driver: misc: Add MU and S400 API to communicate with Sentinel
From: Ye Li
Add MU driver and S400 API. Need enable MISC driver to work
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx8ulp/s400_api.h | 30 +++
arch/arm/include/asm/global_data.h | 5 +
drivers/misc/Makefile| 1 +
drivers/misc/imx8ulp/Makefile| 3 +
drivers/misc/imx8ulp/imx8ulp_mu.c| 247 +++
drivers/misc/imx8ulp/s400_api.c | 41 +++
6 files changed, 327 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/s400_api.h
create mode 100644 drivers/misc/imx8ulp/Makefile
create mode 100644 drivers/misc/imx8ulp/imx8ulp_mu.c
create mode 100644 drivers/misc/imx8ulp/s400_api.c
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
new file mode 100644
index 00..3ba6b525c5
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __S400_API_H__
+#define __S400_API_H__
+
+#define AHAB_VERSION0x6
+#define AHAB_CMD_TAG0x17
+#define AHAB_RESP_TAG 0xe1
+
+#define AHAB_LOG_CID0x21
+#define AHAB_AUTH_OEM_CTNR_CID 0x87
+#define AHAB_VERIFY_IMG_CID 0x88
+#define AHAB_RELEASE_CTNR_CID 0x89
+#define AHAB_RELEASE_RDC_REQ_CID 0xC4
+
+#define S400_MAX_MSG 8U
+
+struct imx8ulp_s400_msg {
+ u8 version;
+ u8 size;
+ u8 command;
+ u8 tag;
+ u32 data[(S400_MAX_MSG - 1U)];
+};
+
+int ahab_release_rdc(u8 core_id);
+#endif
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index fba655f3b9..d0f0ffb9c7 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -87,6 +87,11 @@ struct arch_global_data {
#ifdef CONFIG_ARCH_IMX8
struct udevice *scu_dev;
#endif
+
+#ifdef CONFIG_ARCH_IMX8ULP
+ struct udevice *s400_dev;
+#endif
+
};
#include
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 1a49396007..19a499ee29 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SANDBOX) += irq_sandbox.o
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
obj-$(CONFIG_IMX8) += imx8/
+obj-$(CONFIG_IMX8ULP) += imx8ulp/
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/imx8ulp/Makefile
new file mode 100644
index 00..1d792415d2
--- /dev/null
+++ b/drivers/misc/imx8ulp/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += s400_api.o imx8ulp_mu.o
diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c
b/drivers/misc/imx8ulp/imx8ulp_mu.c
new file mode 100644
index 00..3f6dd558e6
--- /dev/null
+++ b/drivers/misc/imx8ulp/imx8ulp_mu.c
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mu_type {
+ u32 ver;
+ u32 par;
+ u32 cr;
+ u32 sr;
+ u32 reserved0[68];
+ u32 tcr;
+ u32 tsr;
+ u32 rcr;
+ u32 rsr;
+ u32 reserved1[52];
+ u32 tr[16];
+ u32 reserved2[16];
+ u32 rr[16];
+ u32 reserved4[14];
+ u32 mu_attr;
+};
+
+struct imx8ulp_mu {
+ struct mu_type *base;
+};
+
+#define MU_SR_TE0_MASK BIT(0)
+#define MU_SR_RF0_MASK BIT(0)
+#define MU_TR_COUNT4
+#define MU_RR_COUNT4
+
+static inline void mu_hal_init(struct mu_type *base)
+{
+ writel(0, >tcr);
+ writel(0, >rcr);
+}
+
+static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
+{
+ u32 mask = MU_SR_TE0_MASK << reg_index;
+ u32 val;
+ int ret;
+
+ assert(reg_index < MU_TR_COUNT);
+
+ debug("sendmsg sr 0x%x\n", readl(>sr));
+
+ /* Wait TX register to be empty. */
+ ret = readl_poll_timeout(>tsr, val, val & mask, 1);
+ if (ret < 0) {
+ debug("%s timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ debug("tr[%d] 0x%x\n", reg_index, msg);
+
+ writel(msg, >tr[reg_index]);
+
+ return 0;
+}
+
+static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg)
+{
+ u32 mask = MU_SR_RF0_MASK << reg_index;
+ u32 val;
+ int ret;
+
+ assert(reg_index < MU_TR_COUNT);
+
+ debug("receivemsg sr 0x%x\n", readl(>sr));
+
+ /* Wait RX register to be full. */
+ ret = readl_poll_timeout(>rsr, val, val & mask, 1);
+ if (ret < 0) {
+ debug("%s timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ *msg = readl(>rr[reg_index]);
+
+ debug("rr[%d] 0x%x\n", reg_index, *msg);
+
+ return 0;
+}
+
+static int
[PATCH 31/37] arm: iMX8ULP: Add boot device relevant functions
From: Ye Li
Read from ROM API to get current boot device.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 +
arch/arm/mach-imx/imx8ulp/soc.c | 83 +++
2 files changed, 84 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 47ee46bdf4..1a142dce72 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -15,4 +15,5 @@ ulong spl_romapi_get_uboot_base(u32 image_offset, u32
rom_bt_dev);
enum bt_mode get_boot_mode(void);
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
+enum boot_device get_boot_device(void);
#endif
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 527a4e17d8..3fd49b220b 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -26,6 +26,89 @@ DECLARE_GLOBAL_DATA_PTR;
struct rom_api *g_rom_api = (struct rom_api *)0x1980;
+enum boot_device get_boot_device(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+ enum boot_device boot_dev = SD1_BOOT;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, ,
+ ((uintptr_t)) ^ QUERY_BT_DEV);
+ gd = pgd;
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return -1;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ switch (boot_type) {
+ case BT_DEV_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BT_DEV_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BT_DEV_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BT_DEV_TYPE_FLEXSPINOR:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BT_DEV_TYPE_USB:
+ boot_dev = USB_BOOT;
+ break;
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
+
+bool is_usb_boot(void)
+{
+ return get_boot_device() == USB_BOOT;
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int mmc_get_env_dev(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, ,
+ ((uintptr_t)) ^ QUERY_BT_DEV);
+ gd = pgd;
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return CONFIG_SYS_MMC_ENV_DEV;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ /* If not boot from sd/mmc, use default value */
+ if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC)
+ return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
+
+ return board_mmc_get_env_dev(boot_instance);
+}
+#endif
+
u32 get_cpu_rev(void)
{
return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0;
--
2.30.0
[PATCH 36/37] arm: dts: add i.MX8ULP dtsi
From: Peng Fan Add i.MX8ULP dtsi Signed-off-by: Peng Fan --- arch/arm/dts/imx8ulp-pinfunc.h| 978 ++ arch/arm/dts/imx8ulp.dtsi | 706 include/dt-bindings/clock/imx8ulp-clock.h | 247 ++ 3 files changed, 1931 insertions(+) create mode 100644 arch/arm/dts/imx8ulp-pinfunc.h create mode 100644 arch/arm/dts/imx8ulp.dtsi create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h diff --git a/arch/arm/dts/imx8ulp-pinfunc.h b/arch/arm/dts/imx8ulp-pinfunc.h new file mode 100644 index 00..c21c3b644e --- /dev/null +++ b/arch/arm/dts/imx8ulp-pinfunc.h @@ -0,0 +1,978 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __DTS_IMX8ULP_PINFUNC_H +#define __DTS_IMX8ULP_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX8ULP_PAD_PTD0__PTD00x 0x 0x1 0x0 +#define MX8ULP_PAD_PTD0__I2S6_RX_BCLK0x 0x0B44 0x7 0x1 +#define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x 0x 0x8 0x0 +#define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x 0x0974 0x9 0x1 +#define MX8ULP_PAD_PTD0__CLKOUT2 0x 0x 0xa 0x0 +#define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x 0x 0xb 0x0 +#define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_00x 0x 0xc 0x0 +#define MX8ULP_PAD_PTD0__CLKOUT1 0x 0x 0xd 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX0_00x 0x 0xe 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX1_00x 0x 0xf 0x0 +#define MX8ULP_PAD_PTD1__PTD10x0004 0x 0x1 0x0 +#define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1 +#define MX8ULP_PAD_PTD1__SDHC0_CMD 0x0004 0x 0x8 0x0 +#define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA70x0004 0x0970 0x9 0x1 +#define MX8ULP_PAD_PTD1__EPDC0_SDCLK 0x0004 0x 0xb 0x0 +#define MX8ULP_PAD_PTD1__DPI0_PCLK 0x0004 0x 0xc 0x0 +#define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_10x0004 0x 0xd 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX0_10x0004 0x 0xe 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX1_10x0004 0x 0xf 0x0 +#define MX8ULP_PAD_PTD2__PTD20x0008 0x 0x1 0x0 +#define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1 +#define MX8ULP_PAD_PTD2__SDHC0_CLK 0x0008 0x 0x8 0x0 +#define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA60x0008 0x096C 0x9 0x1 +#define MX8ULP_PAD_PTD2__EPDC0_SDLE 0x0008 0x 0xb 0x0 +#define MX8ULP_PAD_PTD2__DPI0_HSYNC 0x0008 0x 0xc 0x0 +#define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_20x0008 0x 0xd 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX0_20x0008 0x 0xe 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX1_20x0008 0x 0xf 0x0 +#define MX8ULP_PAD_PTD3__PTD30x000C 0x 0x1 0x0 +#define MX8ULP_PAD_PTD3__I2S6_RXD1 0x000C 0x0B38 0x7 0x1 +#define MX8ULP_PAD_PTD3__SDHC0_D70x000C 0x 0x8 0x0 +#define MX8ULP_PAD_PTD3__FLEXSPI2_B_DATA50x000C 0x0968 0x9 0x1 +#define MX8ULP_PAD_PTD3__EPDC0_GDSP 0x000C 0x 0xb 0x0 +#define MX8ULP_PAD_PTD3__DPI0_VSYNC 0x000C 0x 0xc 0x0 +#define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_30x000C 0x 0xd 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX0_30x000C 0x 0xe 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX1_30x000C 0x 0xf 0x0 +#define MX8ULP_PAD_PTD4__PTD40x0010 0x 0x1 0x0 +#define MX8ULP_PAD_PTD4__EXT_AUD_MCLK3 0x0010 0x0B14 0x4 0x1 +#define MX8ULP_PAD_PTD4__SDHC0_VS0x0010 0x 0x5 0x0 +#define MX8ULP_PAD_PTD4__TPM8_CH50x0010 0x0B2C 0x6 0x1 +#define MX8ULP_PAD_PTD4__I2S6_MCLK 0x0010 0x 0x7 0x0 +#define MX8ULP_PAD_PTD4__SDHC0_D60x0010 0x 0x8 0x0 +#define MX8ULP_PAD_PTD4__FLEXSPI2_B_DATA40x0010 0x0964 0x9 0x1 +#define MX8ULP_PAD_PTD4__EPDC0_SDCE0
[PATCH 16/37] arm: imx8ulp: add clock support
From: Peng Fan
Add i.MX8ULP clock support
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/cgc.h | 130 ++
arch/arm/include/asm/arch-imx8ulp/clock.h| 9 +-
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 1 +
arch/arm/include/asm/arch-imx8ulp/pcc.h | 139 ++
arch/arm/mach-imx/imx8ulp/Makefile | 2 +-
arch/arm/mach-imx/imx8ulp/cgc.c | 459 +++
arch/arm/mach-imx/imx8ulp/clock.c| 367 ++-
arch/arm/mach-imx/imx8ulp/pcc.c | 449 ++
arch/arm/mach-imx/imx8ulp/soc.c | 3 +
9 files changed, 1555 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/cgc.h
create mode 100644 arch/arm/include/asm/arch-imx8ulp/pcc.h
create mode 100644 arch/arm/mach-imx/imx8ulp/cgc.c
create mode 100644 arch/arm/mach-imx/imx8ulp/pcc.c
diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h
b/arch/arm/include/asm/arch-imx8ulp/cgc.h
new file mode 100644
index 00..34a15fb59c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef _ASM_ARCH_CGC_H
+#define _ASM_ARCH_CGC_H
+
+enum cgc1_clk {
+ DUMMY0_CLK,
+ DUMMY1_CLK,
+ LPOSC,
+ XBAR_BUSCLK,
+ SOSC,
+ SOSC_DIV1,
+ SOSC_DIV2,
+ SOSC_DIV3,
+ FRO,
+ FRO_DIV1,
+ FRO_DIV2,
+ FRO_DIV3,
+ PLL2,
+ PLL3,
+ PLL3_VCODIV,
+ PLL3_PFD0,
+ PLL3_PFD1,
+ PLL3_PFD2,
+ PLL3_PFD3,
+ PLL3_PFD0_DIV1,
+ PLL3_PFD0_DIV2,
+ PLL3_PFD1_DIV1,
+ PLL3_PFD1_DIV2,
+ PLL3_PFD2_DIV1,
+ PLL3_PFD2_DIV2,
+ PLL3_PFD3_DIV1,
+ PLL3_PFD3_DIV2,
+};
+
+struct cgc1_regs {
+ u32 verid;
+ u32 rsvd1[4];
+ u32 ca35clk;
+ u32 rsvd2[2];
+ u32 clkoutcfg;
+ u32 rsvd3[4];
+ u32 nicclk;
+ u32 xbarclk;
+ u32 rsvd4[21];
+ u32 clkdivrst;
+ u32 rsvd5[29];
+ u32 soscdiv;
+ u32 rsvd6[63];
+ u32 frodiv;
+ u32 rsvd7[189];
+ u32 pll2csr;
+ u32 rsvd8[3];
+ u32 pll2cfg;
+ u32 rsvd9;
+ u32 pll2denom;
+ u32 pll2num;
+ u32 pll2ss;
+ u32 rsvd10[55];
+ u32 pll3csr;
+ u32 pll3div_vco;
+ u32 pll3div_pfd0;
+ u32 pll3div_pfd1;
+ u32 pll3cfg;
+ u32 pll3pfdcfg;
+ u32 pll3denom;
+ u32 pll3num;
+ u32 pll3ss;
+ u32 pll3lock;
+ u32 rsvd11[54];
+ u32 enetstamp;
+ u32 rsvd12[67];
+ u32 pllusbcfg;
+ u32 rsvd13[59];
+ u32 aud_clk1;
+ u32 sai5_4_clk;
+ u32 tpm6_7clk;
+ u32 mqs1clk;
+ u32 rsvd14[60];
+ u32 lvdscfg;
+};
+
+struct cgc2_regs {
+ u32 verid;
+ u32 rsvd1[4];
+ u32 hificlk;
+ u32 rsvd2[2];
+ u32 clkoutcfg;
+ u32 rsvd3[6];
+ u32 niclpavclk;
+ u32 ddrclk;
+ u32 rsvd4[19];
+ u32 clkdivrst;
+ u32 rsvd5[29];
+ u32 soscdiv;
+ u32 rsvd6[63];
+ u32 frodiv;
+ u32 rsvd7[253];
+ u32 pll4csr;
+ u32 pll4div_vco;
+ u32 pll4div_pfd0;
+ u32 pll4div_pfd1;
+ u32 pll4cfg;
+ u32 pll4pfdcfg;
+ u32 pll4denom;
+ u32 pll4num;
+ u32 pll4ss;
+ u32 pll4lock;
+ u32 rsvd8[128];
+ u32 aud_clk2;
+ u32 sai7_6_clk;
+ u32 tpm8clk;
+ u32 rsvd9[1];
+ u32 spdifclk;
+ u32 rsvd10[59];
+ u32 lvdscfg;
+};
+
+u32 cgc1_clk_get_rate(enum cgc1_clk clk);
+void cgc1_pll3_init(void);
+void cgc1_pll2_init(void);
+void cgc1_soscdiv_init(void);
+void cgc1_init_core_clk(void);
+void cgc2_pll4_init(void);
+void cgc2_ddrclk_config(u32 src, u32 div);
+u32 cgc1_sosc_div(enum cgc1_clk clk);
+#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h
b/arch/arm/include/asm/arch-imx8ulp/clock.h
index e145c33f01..58e3356e32 100644
--- a/arch/arm/include/asm/arch-imx8ulp/clock.h
+++ b/arch/arm/include/asm/arch-imx8ulp/clock.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2020 NXP
+ * Copyright 2021 NXP
*/
#ifndef _ASM_ARCH_IMX8ULP_CLOCK_H
@@ -17,6 +17,7 @@ enum mxc_clock {
MXC_DDR_CLK,
MXC_ESDHC_CLK,
MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
MXC_I2C_CLK,
};
@@ -26,9 +27,15 @@ u32 get_lpuart_clk(void);
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
u32 imx_get_i2cclk(unsigned int i2c_num);
#endif
+void enable_usboh3_clk(unsigned char enable);
+int enable_usb_pll(ulong usb_phy_base);
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable);
#endif
void init_clk_usdhc(u32 index);
+void init_clk_fspi(int index);
+void init_clk_ddr(void);
+int set_ddr_clk(u32 phy_freq_mhz);
void clock_init(void);
+void cgc1_enet_stamp_sel(u32 clk_src);
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
[PATCH 33/37] arm: imx8ulp: add dummy imx_get_mac_from_fuse
From: Peng Fan
Add imx_get_mac_from_fuse for enet build pass
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 733654f7ba..e999cbca73 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -678,3 +678,8 @@ __weak void __noreturn jump_to_image_no_args(struct
spl_image_info *spl_image)
;
}
#endif
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ memset(mac, 0, 6);
+}
--
2.30.0
[PATCH 34/37] arm: imx8ulp: add iomuxc support
From: Peng Fan
Add i.MX8ULP iomuxc support
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/iomux.h | 82 +++
arch/arm/mach-imx/imx8ulp/iomux.c | 63 -
2 files changed, 144 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/iomux.h
diff --git a/arch/arm/include/asm/arch-imx8ulp/iomux.h
b/arch/arm/include/asm/arch-imx8ulp/iomux.h
new file mode 100644
index 00..3c8f2e067e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/iomux.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __MACH_IMX8ULP_IOMUX_H__
+#define __MACH_IMX8ULP_IOMUX_H__
+
+typedef u64 iomux_cfg_t;
+
+#define MUX_CTRL_OFS_SHIFT 0
+#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0x << MUX_CTRL_OFS_SHIFT)
+#define MUX_SEL_INPUT_OFS_SHIFT16
+#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0x << MUX_SEL_INPUT_OFS_SHIFT)
+
+#define MUX_MODE_SHIFT 32
+#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT)
+#define MUX_SEL_INPUT_SHIFT38
+#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
+#define MUX_PAD_CTRL_SHIFT 42
+#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7 << MUX_PAD_CTRL_SHIFT)
+
+#define MUX_PAD_CTRL(x)((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+
+#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,
sel_input, pad_ctrl) \
+ (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
+ ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
+ ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
+ ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
+ ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
+
+#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) |
MUX_PAD_CTRL(pad))
+
+#define IOMUX_CONFIG_MPORTS 0x20
+#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \
MUX_MODE_SHIFT)
+
+/* Bit definition below needs to be fixed acccording to ulp rm */
+
+#define NO_PAD_CTRLBIT(18)
+#define PAD_CTL_OBE_ENABLE BIT(17)
+#define PAD_CTL_IBE_ENABLE BIT(16)
+#define PAD_CTL_DSEBIT(6)
+#define PAD_CTL_ODEBIT(5)
+#define PAD_CTL_SRE_FAST (0 << 2)
+#define PAD_CTL_SRE_SLOW BIT(2)
+#define PAD_CTL_PUEBIT(1)
+#define PAD_CTL_PUS_UP (BIT(0) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE)
+
+#define IOMUXC_PCR_MUX_ALT0(0 << 8)
+#define IOMUXC_PCR_MUX_ALT1(1 << 8)
+#define IOMUXC_PCR_MUX_ALT2(2 << 8)
+#define IOMUXC_PCR_MUX_ALT3(3 << 8)
+#define IOMUXC_PCR_MUX_ALT4(4 << 8)
+#define IOMUXC_PCR_MUX_ALT5(5 << 8)
+#define IOMUXC_PCR_MUX_ALT6(6 << 8)
+#define IOMUXC_PCR_MUX_ALT7(7 << 8)
+#define IOMUXC_PCR_MUX_ALT8(8 << 8)
+#define IOMUXC_PCR_MUX_ALT9(9 << 8)
+#define IOMUXC_PCR_MUX_ALT10 (10 << 8)
+#define IOMUXC_PCR_MUX_ALT11 (11 << 8)
+#define IOMUXC_PCR_MUX_ALT12 (12 << 8)
+#define IOMUXC_PCR_MUX_ALT13 (13 << 8)
+#define IOMUXC_PCR_MUX_ALT14 (14 << 8)
+#define IOMUXC_PCR_MUX_ALT15 (15 << 8)
+
+#define IOMUXC_PSMI_IMUX_ALT0 (0x0)
+#define IOMUXC_PSMI_IMUX_ALT1 (0x1)
+#define IOMUXC_PSMI_IMUX_ALT2 (0x2)
+#define IOMUXC_PSMI_IMUX_ALT3 (0x3)
+#define IOMUXC_PSMI_IMUX_ALT4 (0x4)
+#define IOMUXC_PSMI_IMUX_ALT5 (0x5)
+#define IOMUXC_PSMI_IMUX_ALT6 (0x6)
+#define IOMUXC_PSMI_IMUX_ALT7 (0x7)
+
+#define IOMUXC_PCR_MUX_ALT_SHIFT (8)
+#define IOMUXC_PCR_MUX_ALT_MASK(0xF00)
+#define IOMUXC_PSMI_IMUX_ALT_SHIFT (0)
+
+void imx8ulp_iomux_setup_pad(iomux_cfg_t pad);
+void imx8ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, unsigned
count);
+#endif
diff --git a/arch/arm/mach-imx/imx8ulp/iomux.c
b/arch/arm/mach-imx/imx8ulp/iomux.c
index c52ccdeaea..71a8c59d64 100644
--- a/arch/arm/mach-imx/imx8ulp/iomux.c
+++ b/arch/arm/mach-imx/imx8ulp/iomux.c
@@ -1,4 +1,65 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
+
+#include
+#include
+#include
+#include
+
+static void *base = (void *)IOMUXC_BASE_ADDR;
+
+/*
+ * iomuxc0 base address. In imx7ulp-pins.h,
+ * the offsets of pins in iomuxc0 are from 0xD000,
+ * so we set the base address to (0x4103D000 - 0xD000 = 0x4103)
+ */
+static void *base_mports = (void *)(0x280A1000);
+
+/*
+ * configures a single pad in the iomuxer
+ */
+void imx8ulp_iomux_setup_pad(iomux_cfg_t pad)
+{
+ u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+ u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+ u32 sel_input_ofs =
+ (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+ u32
[PATCH 19/37] arm: imx8ulp: Enable full L2 cache in SPL
From: Ye Li
SRAM2 is half L2 cache and default to SRAM after system boot.
To enable the full l2 cache (512KB), it needs to reset A35 to make
the change happen.
So re-implement the jump entry function in SPL:
1. configure the core0 reset vector to entry (ATF)
2. enable the L2 full cache
3. reset A35
So when core0 up, it runs into ATF. And we have 512KB L2 cache working.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 2 ++
arch/arm/mach-imx/imx8ulp/soc.c | 34
2 files changed, 36 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index 9f76bc85fc..29b87121ea 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -20,6 +20,8 @@
#define WDG3_RBASE 0x292aUL
+#define SIM1_BASE_ADDR 0x2929
+
#define CGC1_SOSCDIV_ADDR 0x292C0108
#define CGC1_FRODIV_ADDR 0x292C0208
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 8f34eccfc2..be7d3d7259 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -9,6 +9,8 @@
#include
#include
#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -289,3 +291,35 @@ int arch_cpu_init(void)
return 0;
}
+
+#if defined(CONFIG_SPL_BUILD)
+__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ debug("image entry point: 0x%lx\n", spl_image->entry_point);
+
+ /* Update SIM1 DGO8 for reset vector base */
+ writel((u32)spl_image->entry_point, SIM1_BASE_ADDR + 0x5c);
+
+ /* set update bit */
+ setbits_le32(SIM1_BASE_ADDR + 0x8, 0x1 << 24);
+
+ /* polling the ack */
+ while ((readl(SIM1_BASE_ADDR + 0x8) & (0x1 << 26)) == 0)
+ ;
+
+ /* clear the update */
+ clrbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 24));
+
+ /* clear the ack by set 1 */
+ setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
+
+ /* Enable the 512KB cache */
+ setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 4));
+
+ /* reset core */
+ setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 16));
+
+ while (1)
+ ;
+}
+#endif
--
2.30.0
[PATCH 13/37] net: fec_mxc: support i.MX8ULP
From: Peng Fan
Support i.MX8ULP in fec_mxc
Signed-off-by: Peng Fan
---
drivers/net/Kconfig | 2 +-
drivers/net/fec_mxc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index cf062fad4d..a443b499ba 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -314,7 +314,7 @@ config FEC_MXC_MDIO_BASE
config FEC_MXC
bool "FEC Ethernet controller"
- depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || VF610
+ depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP ||
VF610
help
This driver supports the 10/100 Fast Ethernet controller for
NXP i.MX processors.
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ec21157d71..57ba856915 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -628,7 +628,7 @@ static int fec_init(struct eth_device *dev, struct bd_info
*bd)
writel(0x, >eth->gaddr2);
/* Do not access reserved register */
- if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
+ if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() &&
!is_imx8ulp()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
--
2.30.0
[PATCH 17/37] drivers: mmc: fsl_esdhc_imx: support i.MX8ULP
From: Peng Fan
i.MX8ULP reuse same SDHC IP as i.MX8M, so follow i.MX8M code logic.
Signed-off-by: Peng Fan
---
drivers/mmc/Kconfig | 2 +-
drivers/mmc/fsl_esdhc_imx.c | 12
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 197aa82040..5c42e469b3 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -804,7 +804,7 @@ config FSL_ESDHC_IMX
config FSL_USDHC
bool "Freescale/NXP i.MX uSDHC controller support"
- depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT ||
TARGET_S32V234EVB
+ depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP ||
IMXRT || TARGET_S32V234EVB
select FSL_ESDHC_IMX
help
This enables the Ultra Secured Digital Host Controller enhancements
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index a4675838e5..4c7c2dd93c 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -291,7 +291,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
{
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
|| \
+ defined(CONFIG_IMX8ULP)
dma_addr_t addr;
#endif
uint wml_value;
@@ -304,7 +305,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(>wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
|| \
+ defined(CONFIG_IMX8ULP)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -341,7 +343,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(>wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
|| \
+ defined(CONFIG_IMX8ULP)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -406,7 +409,8 @@ static void check_and_invalidate_dcache_range
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
-#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
|| \
+ defined(CONFIG_IMX8ULP)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
--
2.30.0
[PATCH 14/37] pinctrl: Add pinctrl driver for imx8ulp
From: Ye Li
Add pinctrl driver for i.MX8ULP
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/pinctrl/nxp/Kconfig | 14 +
drivers/pinctrl/nxp/Makefile | 1 +
drivers/pinctrl/nxp/pinctrl-imx8ulp.c | 44 +++
3 files changed, 59 insertions(+)
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8ulp.c
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index ec55351e61..4fb0916a37 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -60,6 +60,20 @@ config PINCTRL_IMX7ULP
only parses the 'fsl,pins' property and configure related
registers.
+config PINCTRL_IMX8ULP
+ bool "IMX8ULP pinctrl driver"
+ depends on ARCH_IMX8ULP && PINCTRL_FULL
+ select DEVRES
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx8ulp pinctrl driver
+
+ This provides a simple pinctrl driver for i.MX8ULP SoC familiy.
+ This feature depends on device tree configuration. This driver
+ is different from the linux one, this is a simple implementation,
+ only parses the 'fsl,pins' property and configure related
+ registers.
+
config PINCTRL_IMX8
bool "IMX8 pinctrl driver"
depends on ARCH_IMX8 && PINCTRL_FULL
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index 066ca75b65..f2fe0d8efa 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o
obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o
obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
+obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
obj-$(CONFIG_PINCTRL_IMX8M)+= pinctrl-imx8m.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8ulp.c
b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c
new file mode 100644
index 00..3f15f1dd45
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#include
+#include
+#include
+
+#include "pinctrl-imx.h"
+
+static struct imx_pinctrl_soc_info imx8ulp_pinctrl_soc_info0 = {
+ .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CONFIG_IBE_OBE,
+};
+
+static struct imx_pinctrl_soc_info imx8ulp_pinctrl_soc_info1 = {
+ .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CONFIG_IBE_OBE,
+};
+
+static int imx8ulp_pinctrl_probe(struct udevice *dev)
+{
+ struct imx_pinctrl_soc_info *info =
+ (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+ return imx_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id imx8ulp_pinctrl_match[] = {
+ { .compatible = "fsl,imx8ulp-iomuxc0", .data =
(ulong)_pinctrl_soc_info0 },
+ { .compatible = "fsl,imx8ulp-iomuxc1", .data =
(ulong)_pinctrl_soc_info1 },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imx8ulp_pinctrl) = {
+ .name = "imx8ulp-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(imx8ulp_pinctrl_match),
+ .probe = imx8ulp_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+ .priv_auto = sizeof(struct imx_pinctrl_priv),
+ .ops = _pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.30.0
[PATCH 28/37] arm: imx8ulp: add trdc release request
From: Peng Fan
Add TRDC release request, then we could configure resources to be
accessible by A35 Domain.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 32389629ba..ad57c88674 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -341,17 +341,23 @@ static void set_core0_reset_vector(u32 entry)
setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
}
-static int release_xrdc(void)
+enum rdc_type {
+ RDC_TRDC,
+ RDC_XRDC,
+};
+
+static int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x2702UL;
struct imx8ulp_s400_msg msg;
int ret;
+ u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_RELEASE_RDC_REQ_CID;
- msg.data[0] = (0x78 << 8) | 0x2; /* A35 XRDC */
+ msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
mu_hal_init(s_mu_base);
mu_hal_sendmsg(s_mu_base, 0, *((u32 *)));
@@ -360,13 +366,12 @@ static int release_xrdc(void)
ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *));
if (!ret) {
ret = mu_hal_receivemsg(s_mu_base, 1, [0]);
- if (!ret)
- return ret;
+ if (!ret) {
+ if ((msg.data[0] & 0xff) == 0xd6)
+ return 0;
+ }
- if ((msg.data[0] & 0xff) == 0)
- return 0;
- else
- return -EIO;
+ return -EIO;
}
return ret;
@@ -420,8 +425,11 @@ int arch_cpu_init(void)
/* Disable wdog */
init_wdog();
+ if (get_boot_mode() == SINGLE_BOOT)
+ release_rdc(RDC_TRDC);
+
/* release xrdc, then allow A35 to write SRAM2 */
- release_xrdc();
+ release_rdc(RDC_XRDC);
xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
clock_init();
--
2.30.0
[PATCH 15/37] driver: serial: fsl_lpuart: support i.MX8ULP
From: Peng Fan
i.MX8ULP lpuart has same register layout as i.MX7ULP and i.MX8
Signed-off-by: Peng Fan
---
include/fsl_lpuart.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
index 511fb84367..18e5cc15d6 100644
--- a/include/fsl_lpuart.h
+++ b/include/fsl_lpuart.h
@@ -5,7 +5,7 @@
*/
#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
- defined(CONFIG_ARCH_IMXRT)
+ defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP)
struct lpuart_fsl_reg32 {
u32 verid;
u32 param;
--
2.30.0
[PATCH 37/37] arm: imx: add i.MX8ULP EVK support
From: Peng Fan
Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART
Note: upower API currently not included.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8ulp-emulator-u-boot.dtsi | 32 +
arch/arm/dts/imx8ulp-emulator.dts | 93 +
arch/arm/dts/imx8ulp-evk-u-boot.dtsi| 32 +
arch/arm/dts/imx8ulp-evk.dts| 204 +++
arch/arm/mach-imx/imx8ulp/Kconfig |7 +
board/freescale/imx8ulp_evk/Kconfig | 14 +
board/freescale/imx8ulp_evk/MAINTAINERS |6 +
board/freescale/imx8ulp_evk/Makefile|7 +
board/freescale/imx8ulp_evk/ddr_init.c | 207 +++
board/freescale/imx8ulp_evk/imx8ulp_evk.c | 67 +
board/freescale/imx8ulp_evk/lpddr4_timing.c | 1696 +++
board/freescale/imx8ulp_evk/spl.c | 146 ++
configs/imx8ulp_evk_defconfig | 103 ++
include/configs/imx8ulp_evk.h | 108 ++
14 files changed, 2722 insertions(+)
create mode 100644 arch/arm/dts/imx8ulp-emulator-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8ulp-emulator.dts
create mode 100644 arch/arm/dts/imx8ulp-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8ulp-evk.dts
create mode 100644 board/freescale/imx8ulp_evk/Kconfig
create mode 100644 board/freescale/imx8ulp_evk/MAINTAINERS
create mode 100644 board/freescale/imx8ulp_evk/Makefile
create mode 100644 board/freescale/imx8ulp_evk/ddr_init.c
create mode 100644 board/freescale/imx8ulp_evk/imx8ulp_evk.c
create mode 100644 board/freescale/imx8ulp_evk/lpddr4_timing.c
create mode 100644 board/freescale/imx8ulp_evk/spl.c
create mode 100644 configs/imx8ulp_evk_defconfig
create mode 100644 include/configs/imx8ulp_evk.h
diff --git a/arch/arm/dts/imx8ulp-emulator-u-boot.dtsi
b/arch/arm/dts/imx8ulp-emulator-u-boot.dtsi
new file mode 100644
index 00..21161520d8
--- /dev/null
+++ b/arch/arm/dts/imx8ulp-emulator-u-boot.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+&{/soc@0} {
+ u-boot,dm-spl;
+};
+
+_bridge3 {
+ u-boot,dm-spl;
+};
+
+_bridge4 {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_lpuart4 {
+ u-boot,dm-spl;
+};
+
+_mu {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8ulp-emulator.dts
b/arch/arm/dts/imx8ulp-emulator.dts
new file mode 100644
index 00..924078b361
--- /dev/null
+++ b/arch/arm/dts/imx8ulp-emulator.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8ulp.dtsi"
+
+/ {
+ model = "FSL i.MX8ULP Emulator";
+ compatible = "fsl,imx8ulp-emulator", "fsl,imx8ulp";
+
+ chosen {
+ stdout-path =
+ };
+};
+
+ {
+ /* console */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <_lpuart4>;
+ pinctrl-1 = <_lpuart4>;
+ status = "okay";
+};
+
+ {
+ pinctrl_lpuart4: lpuart4grp {
+ fsl,pins = <
+ MX8ULP_PAD_PTE2__LPUART4_TX 0x3
+ MX8ULP_PAD_PTE3__LPUART4_RX 0x3
+ >;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43
+ MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
+ MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
+ MX8ULP_PAD_PTD10__SDHC0_D0 0x43
+ MX8ULP_PAD_PTD9__SDHC0_D1 0x43
+ MX8ULP_PAD_PTD8__SDHC0_D2 0x43
+ MX8ULP_PAD_PTD7__SDHC0_D3 0x43
+ MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
+ >;
+ };
+
+ pinctrl_usdhc1_ptf: usdhc1ptfgrp {
+ fsl,pins = <
+ MX8ULP_PAD_PTF11__SDHC1_RESET_B 0x43
+ MX8ULP_PAD_PTF1__SDHC1_D0 0x43
+ MX8ULP_PAD_PTF0__SDHC1_D1 0x43
+ MX8ULP_PAD_PTF2__SDHC1_CLK 0x10042
+ MX8ULP_PAD_PTF3__SDHC1_CMD 0x43
+ MX8ULP_PAD_PTF4__SDHC1_D3 0x42
+ MX8ULP_PAD_PTF5__SDHC1_D2 0x42
+ >;
+ };
+};
+
+ {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <_usdhc0>;
+ pinctrl-1 = <_usdhc0>;
+ bus-width = <1>;
+ broken-cd;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <_usdhc1_ptf>;
+ pinctrl-1 = <_usdhc1_ptf>;
+ bus-width = <1>;
+ broken-cd;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+
+ flash0: mt35xu512aba@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <2900>;
+
[PATCH 32/37] arm: imx8ulp: Allocate DCNANO and MIPI_DSI to AD domain
From: Ye Li Configure DCNANO and MIPI_DSI to be controlled by AD for single boot Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 3fd49b220b..733654f7ba 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -628,6 +628,8 @@ int arch_cpu_init(void) setbits_le32(0x2802B044, BIT(7)); /* GPU 2D/3D to APD */ setbits_le32(0x2802B04C, BIT(1) | BIT(2)); + /* DCNANO and MIPI_DSI to APD */ + setbits_le32(0x2802B04C, BIT(1) | BIT(2) | BIT(3) | BIT(4)); } /* release xrdc, then allow A35 to write SRAM2 */ -- 2.30.0
[PATCH 35/37] driver: misc: imx8ulp: Add fuse driver for imx8ulp
From: Ye Li
This driver uses FSB to read some fuses, but not support program fuse.
It only works in SPL (secure mode), u-boot needs traps to ATF to
read them.
Some fuses can read from S400 API and others are from FSB.
Also support program some fuses via S400 API
Signed-off-by: Ye Li
---
drivers/misc/imx8ulp/Makefile | 1 +
drivers/misc/imx8ulp/fuse.c | 198 ++
2 files changed, 199 insertions(+)
create mode 100644 drivers/misc/imx8ulp/fuse.c
diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/imx8ulp/Makefile
index 1d792415d2..927cc55216 100644
--- a/drivers/misc/imx8ulp/Makefile
+++ b/drivers/misc/imx8ulp/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += s400_api.o imx8ulp_mu.o
+obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/imx8ulp/fuse.c
new file mode 100644
index 00..d1feb62ab5
--- /dev/null
+++ b/drivers/misc/imx8ulp/fuse.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FUSE_BANKS 64
+#define WORDS_PER_BANKS 8
+
+struct fsb_map_entry {
+ s32 fuse_bank;
+ u32 fuse_words;
+ bool redundancy;
+};
+
+struct s400_map_entry {
+ s32 fuse_bank;
+ u32 fuse_words;
+ u32 fuse_offset;
+ u32 s400_index;
+};
+
+struct fsb_map_entry fsb_mapping_table[] = {
+ { 3, 8 },
+ { 4, 8 },
+ { 5, 8 },
+ { 6, 8 },
+ { -1, 48 }, /* Reserve 48 words */
+ { 8, 4, true },
+ { 24, 4, true },
+ { 26, 4, true },
+ { 27, 4, true },
+ { 28, 8 },
+ { 29, 8 },
+ { 30, 8 },
+ { 31, 8 },
+ { 37, 8 },
+ { 38, 8 },
+ { 39, 8 },
+ { 40, 8 },
+ { 41, 8 },
+ { 42, 8 },
+ { 43, 8 },
+ { 44, 8 },
+ { 45, 8 },
+ { 46, 8 },
+};
+
+struct s400_map_entry s400_api_mapping_table[] = {
+ { 1, 8 }, /* LOCK */
+ { 2, 8 }, /* ECID */
+ { 7, 4, 0, 1 }, /* OTP_UNIQ_ID */
+ { 23, 1, 4, 2 }, /* OTFAD */
+};
+
+static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
+{
+ s32 size = ARRAY_SIZE(fsb_mapping_table);
+ s32 i, word_pos = 0;
+
+ /* map the fuse from ocotp fuse map to FSB*/
+ for (i = 0; i < size; i++) {
+ if (fsb_mapping_table[i].fuse_bank != -1 &&
+ fsb_mapping_table[i].fuse_bank == bank) {
+ break;
+ }
+
+ word_pos += fsb_mapping_table[i].fuse_words;
+ }
+
+ if (i == size)
+ return -1; /* Failed to find */
+
+ if (fsb_mapping_table[i].redundancy) {
+ *redundancy = true;
+ return (word >> 1) + word_pos;
+ }
+
+ *redundancy = false;
+ return word + word_pos;
+}
+
+static s32 map_s400_fuse_index(u32 bank, u32 word)
+{
+ s32 size = ARRAY_SIZE(s400_api_mapping_table);
+ s32 i;
+
+ /* map the fuse from ocotp fuse map to FSB*/
+ for (i = 0; i < size; i++) {
+ if (s400_api_mapping_table[i].fuse_bank != -1 &&
+ s400_api_mapping_table[i].fuse_bank == bank) {
+ if (word >= s400_api_mapping_table[i].fuse_offset &&
+ word < (s400_api_mapping_table[i].fuse_offset +
+ s400_api_mapping_table[i].fuse_words))
+ break;
+ }
+ }
+
+ if (i == size)
+ return -1; /* Failed to find */
+
+ if (s400_api_mapping_table[i].s400_index != 0)
+ return s400_api_mapping_table[i].s400_index;
+
+ return s400_api_mapping_table[i].fuse_bank * 8 + word;
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ s32 word_index;
+ bool redundancy;
+
+ if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ word_index = map_fsb_fuse_index(bank, word, );
+ if (word_index >= 0) {
+ *val = readl((ulong)FSB_BASE_ADDR + 0x800 + (word_index << 2));
+ if (redundancy)
+ *val = (*val >> ((word % 2) * 16)) & 0x;
+
+ return 0;
+ }
+
+ word_index = map_s400_fuse_index(bank, word);
+ if (word_index >= 0) {
+ u32 data[4];
+ u32 res, size = 4;
+ int ret;
+
+ /* Only UID return 4 words */
+ if (word_index != 1)
+ size = 1;
+
+ ret = ahab_read_common_fuse(word_index, data, size, );
+ if (ret) {
+ printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ if (word_index == 1) {
+ *val = data[word]; /* UID
[PATCH 30/37] arm: imx8ulp: Probe the S400 MU device in arch init
From: Ye Li
Need probe the S400 MU device in arch_cpu_init_dm, so we can use
S400 API in u-boot
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 35 -
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index a8791f4612..527a4e17d8 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -15,6 +15,12 @@
#include
#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -318,7 +324,18 @@ int dram_init(void)
#ifdef CONFIG_SERIAL_TAG
void get_board_serial(struct tag_serialnr *serialnr)
{
- /* TODO */
+ u32 uid[4];
+ u32 res;
+ int ret;
+
+ ret = ahab_read_common_fuse(1, uid, 4, );
+ if (ret)
+ printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+ else
+ printf("UID 0x%x,0x%x,0x%x,0x%x\n", uid[0], uid[1], uid[2],
uid[3]);
+
+ serialnr->low = uid[0];
+ serialnr->high = uid[3];
}
#endif
@@ -543,6 +560,22 @@ int arch_cpu_init(void)
return 0;
}
+int arch_cpu_init_dm(void)
+{
+ struct udevice *devp;
+ int node, ret;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"fsl,imx8ulp-mu");
+
+ ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, );
+ if (ret) {
+ printf("could not get S400 mu %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
#if defined(CONFIG_SPL_BUILD)
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
--
2.30.0
[PATCH 29/37] arm: imx8ulp: release trdc and assign lpav from RTD to APD
From: Peng Fan
Rlease LPAV from RTD to APD
Release gpu2D/3D to APD
Set TRDC MBC2 MEM1 for iomuxc0 access
Since upower depends AP/M33 SW to configure IOMUX for its PMIC i2c
and MODE pins. we have to open iomuxc0 access for A35 core (domain 7)
in single boot.
Signed-off-by: Peng Fan
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx8ulp/soc.c | 104 +++-
1 file changed, 103 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index ad57c88674..a8791f4612 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -377,6 +377,102 @@ static int release_rdc(enum rdc_type type)
return ret;
}
+struct mbc_mem_dom {
+ u32 mem_glbcfg[4];
+ u32 nse_blk_index;
+ u32 nse_blk_set;
+ u32 nse_blk_clr;
+ u32 nsr_blk_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MBC */
+ u32 mem0_blk_cfg_w[64];
+ u32 mem0_blk_nse_w[16];
+ u32 mem1_blk_cfg_w[8];
+ u32 mem1_blk_nse_w[2];
+ u32 mem2_blk_cfg_w[8];
+ u32 mem2_blk_nse_w[2];
+ u32 mem3_blk_cfg_w[8];
+ u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
+ u32 reserved[2];
+};
+
+struct trdc {
+ u8 res0[0x1000];
+ struct mbc_mem_dom mem_dom[4][8];
+};
+
+/* MBC[m]_[d]_MEM[s]_BLK_CFG_W[w] */
+int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, u32 perm)
+{
+ struct trdc *trdc_base = (struct trdc *)0x28031000U;
+ struct mbc_mem_dom *mbc_dom;
+ u32 *cfg_w, *nse_w;
+ u32 index, offset, val;
+
+ mbc_dom = _base->mem_dom[mbc_x][dom_x];
+
+ switch (mem_x) {
+ case 0:
+ cfg_w = _dom->mem0_blk_cfg_w[blk_x / 8];
+ nse_w = _dom->mem0_blk_nse_w[blk_x / 32];
+ break;
+ case 1:
+ cfg_w = _dom->mem1_blk_cfg_w[blk_x / 8];
+ nse_w = _dom->mem1_blk_nse_w[blk_x / 32];
+ break;
+ case 2:
+ cfg_w = _dom->mem2_blk_cfg_w[blk_x / 8];
+ nse_w = _dom->mem2_blk_nse_w[blk_x / 32];
+ break;
+ case 3:
+ cfg_w = _dom->mem3_blk_cfg_w[blk_x / 8];
+ nse_w = _dom->mem3_blk_nse_w[blk_x / 32];
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ index = blk_x % 8;
+ offset = index * 4;
+
+ val = readl((void __iomem *)cfg_w);
+
+ val &= ~(0xFU << offset);
+
+ if (perm == 0x7700) {
+ val |= (0x0 << offset);
+ writel(perm, (void __iomem *)cfg_w);
+ } else if (perm == 0x0077) {
+ val |= (0x8 << offset); /* nse bit set */
+ writel(val, (void __iomem *)cfg_w);
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int trdc_set_access(void)
+{
+ /*
+* CGC0: PBridge0 slot 47
+* trdc_mbc_set_access(2, 7, 0, 47, 0x7700);
+* For secure access, default single boot already support,
+* For non-secure access, need add in future per usecase.
+*/
+trdc_mbc_set_access(2, 7, 0, 49, 0x7700);
+trdc_mbc_set_access(2, 7, 0, 50, 0x7700);
+trdc_mbc_set_access(2, 7, 0, 51, 0x7700);
+trdc_mbc_set_access(2, 7, 0, 52, 0x7700);
+
+trdc_mbc_set_access(2, 7, 0, 47, 0x0077);
+
+/* iomuxc 0 */
+trdc_mbc_set_access(2, 7, 1, 33, 0x7700);
+
+ return 0;
+}
+
static void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access)
{
ulong xrdc_base = 0x292f, off;
@@ -425,8 +521,14 @@ int arch_cpu_init(void)
/* Disable wdog */
init_wdog();
- if (get_boot_mode() == SINGLE_BOOT)
+ if (get_boot_mode() == SINGLE_BOOT) {
release_rdc(RDC_TRDC);
+ trdc_set_access();
+ /* LPAV to APD */
+ setbits_le32(0x2802B044, BIT(7));
+ /* GPU 2D/3D to APD */
+ setbits_le32(0x2802B04C, BIT(1) | BIT(2));
+ }
/* release xrdc, then allow A35 to write SRAM2 */
release_rdc(RDC_XRDC);
--
2.30.0
[PATCH 26/37] arm: imx8ulp: release and configure XRDC at early phase
From: Ye Li
Since S400 will set the memory of SPL image to R/X. We can't write
to any data in SPL image.
1. Set the parameters save/restore only for u-boot, not for SPL. to
avoid write data.
2. Not use MU DM driver but directly call MU API to send release XRDC
to S400 at early phase.
3. Configure the SPL image memory of SRAM2 to writable (R/W/X)
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/mu_hal.h | 12
arch/arm/mach-imx/imx8ulp/lowlevel_init.S | 10 +--
arch/arm/mach-imx/imx8ulp/soc.c| 84 ++
drivers/misc/imx8ulp/imx8ulp_mu.c | 36 +-
4 files changed, 118 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/mu_hal.h
diff --git a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
b/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
new file mode 100644
index 00..10d966d5d4
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __IMX8ULP_MU_HAL_H__
+#define __IMX8ULP_MU_HAL_H__
+
+void mu_hal_init(ulong base);
+int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg);
+int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg);
+#endif
diff --git a/arch/arm/mach-imx/imx8ulp/lowlevel_init.S
b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S
index 7d81a75639..791c26407c 100644
--- a/arch/arm/mach-imx/imx8ulp/lowlevel_init.S
+++ b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S
@@ -16,17 +16,11 @@ rom_pointer:
.global save_boot_params
save_boot_params:
+#ifndef CONFIG_SPL_BUILD
/* The firmware provided ATAG/FDT address can be found in r2/x0 */
adr x0, rom_pointer
stp x1, x2, [x0], #16
stp x3, x4, [x0], #16
-
+#endif
/* Returns */
b save_boot_params_ret
-
-.global restore_boot_params
-restore_boot_params:
- adr x0, rom_pointer
- ldp x1, x2, [x0], #16
- ldp x3, x4, [x0], #16
- ret
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 044758157f..32389629ba 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -11,6 +11,10 @@
#include
#include
#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -337,9 +341,89 @@ static void set_core0_reset_vector(u32 entry)
setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
}
+static int release_xrdc(void)
+{
+ ulong s_mu_base = 0x2702UL;
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_RELEASE_RDC_REQ_CID;
+ msg.data[0] = (0x78 << 8) | 0x2; /* A35 XRDC */
+
+ mu_hal_init(s_mu_base);
+ mu_hal_sendmsg(s_mu_base, 0, *((u32 *)));
+ mu_hal_sendmsg(s_mu_base, 1, msg.data[0]);
+
+ ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *));
+ if (!ret) {
+ ret = mu_hal_receivemsg(s_mu_base, 1, [0]);
+ if (!ret)
+ return ret;
+
+ if ((msg.data[0] & 0xff) == 0)
+ return 0;
+ else
+ return -EIO;
+ }
+
+ return ret;
+}
+
+static void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access)
+{
+ ulong xrdc_base = 0x292f, off;
+ u32 mrgd[5];
+ u8 mrcfg, j, region_num;
+ u8 dsel;
+
+ mrcfg = readb(xrdc_base + 0x140 + mrc_index);
+ region_num = mrcfg & 0x1f;
+
+ for (j = 0; j < region_num; j++) {
+ off = 0x2000 + mrc_index * 0x200 + j * 0x20;
+
+ mrgd[0] = readl(xrdc_base + off);
+ mrgd[1] = readl(xrdc_base + off + 4);
+ mrgd[2] = readl(xrdc_base + off + 8);
+ mrgd[3] = readl(xrdc_base + off + 0xc);
+ mrgd[4] = readl(xrdc_base + off + 0x10);
+
+ debug("MRC [%u][%u]\n", mrc_index, j);
+ debug("0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
+ mrgd[0], mrgd[1], mrgd[2], mrgd[3], mrgd[4]);
+
+ /* hit */
+ if (addr >= mrgd[0] && addr <= mrgd[1]) {
+ /* find domain 7 DSEL */
+ dsel = (mrgd[2] >> 21) & 0x7;
+ if (dsel == 1) {
+ mrgd[4] &= ~0xFFF;
+ mrgd[4] |= (access & 0xFFF);
+ } else if (dsel == 2) {
+ mrgd[4] &= ~0xFFF;
+ mrgd[4] |= ((access & 0xFFF) << 16);
+ }
+
+ /* not handle other cases, since S400 only set ACCESS1
and 2 */
+ writel(mrgd[4], xrdc_base + off + 0x10);
+ return;
+ }
+ }
+}
+
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
[PATCH 27/37] arm: imx8ulp: add xrdc support
From: Peng Fan
There is xrdc inside i.MX8ULP, we need to configure permission to make
sure AP non-secure world could access the resources.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 2 +
arch/arm/mach-imx/imx8ulp/Makefile| 2 +-
arch/arm/mach-imx/imx8ulp/xrdc.c | 144 ++
3 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-imx/imx8ulp/xrdc.c
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index a8f632f45e..47ee46bdf4 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -13,4 +13,6 @@ extern unsigned long rom_pointer[];
ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
enum bt_mode get_boot_mode(void);
+int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
+int xrdc_config_pdac_openacc(u32 bridge, u32 index);
#endif
diff --git a/arch/arm/mach-imx/imx8ulp/Makefile
b/arch/arm/mach-imx/imx8ulp/Makefile
index 78c81d78bb..453589e6a2 100644
--- a/arch/arm/mach-imx/imx8ulp/Makefile
+++ b/arch/arm/mach-imx/imx8ulp/Makefile
@@ -4,4 +4,4 @@
#
obj-y += lowlevel_init.o
-obj-y += soc.o clock.o iomux.o pcc.o cgc.o
+obj-y += soc.o clock.o iomux.o pcc.o cgc.o xrdc.o
diff --git a/arch/arm/mach-imx/imx8ulp/xrdc.c b/arch/arm/mach-imx/imx8ulp/xrdc.c
new file mode 100644
index 00..7a098718da
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/xrdc.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define XRDC_ADDR 0x292f
+#define MRC_OFFSET 0x2000
+#define MRC_STEP 0x200
+
+#define SP(X) ((X) << 9)
+#define SU(X) ((X) << 6)
+#define NP(X) ((X) << 3)
+#define NU(X) ((X) << 0)
+
+#define RWX7
+#define RW 6
+#define R 4
+#define X 1
+
+#define D7SEL_CODE (SP(RW) | SU(RW) | NP(RWX) | NU(RWX))
+#define D6SEL_CODE (SP(RW) | SU(RW) | NP(RWX))
+#define D5SEL_CODE (SP(RW) | SU(RWX))
+#define D4SEL_CODE SP(RWX)
+#define D3SEL_CODE (SP(X) | SU(X) | NP(X) | NU(X))
+#define D0SEL_CODE 0
+
+#define D7SEL_DAT (SP(RW) | SU(RW) | NP(RW) | NU(RW))
+#define D6SEL_DAT (SP(RW) | SU(RW) | NP(RW))
+#define D5SEL_DAT (SP(RW) | SU(RW) | NP(R) | NU(R))
+#define D4SEL_DAT (SP(RW) | SU(RW))
+#define D3SEL_DAT SP(RW)
+
+union dxsel_perm {
+ struct {
+ u8 dx;
+ u8 perm;
+ };
+
+ u32 dom_perm;
+};
+
+int xrdc_config_mrc_dx_perm(u32 mrc_con, u32 region, u32 dom, u32 dxsel)
+{
+ ulong w2_addr;
+ u32 val = 0;
+
+ w2_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 +
0x8;
+
+ val = (readl(w2_addr) & (~(7 << (3 * dom | (dxsel << (3 * dom));
+ writel(val, w2_addr);
+
+ return 0;
+}
+
+int xrdc_config_mrc_w0_w1(u32 mrc_con, u32 region, u32 w0, u32 size)
+{
+ ulong w0_addr, w1_addr;
+
+ w0_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20;
+ w1_addr = w0_addr + 4;
+
+ if ((size % 32) != 0)
+ return -EINVAL;
+
+ writel(w0 & ~0x1f, w0_addr);
+ writel(w0 + size - 1, w1_addr);
+
+ return 0;
+}
+
+int xrdc_config_mrc_w3_w4(u32 mrc_con, u32 region, u32 w3, u32 w4)
+{
+ ulong w3_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region *
0x20 + 0xC;
+ ulong w4_addr = w3_addr + 4;
+
+ writel(w3, w3_addr);
+ writel(w4, w4_addr);
+
+ return 0;
+}
+
+int xrdc_config_pdac_openacc(u32 bridge, u32 index)
+{
+ ulong w0_addr;
+ u32 val;
+
+ switch (bridge) {
+ case 3:
+ w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
+ break;
+ case 4:
+ w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
+ break;
+ case 5:
+ w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
+ break;
+ default:
+ return -EINVAL;
+ }
+ writel(0xff, w0_addr);
+
+ val = readl(w0_addr + 4);
+ writel(val | BIT(31), w0_addr + 4);
+
+ return 0;
+}
+
+int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
+{
+ ulong w0_addr;
+ u32 val;
+
+ switch (bridge) {
+ case 3:
+ w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
+ break;
+ case 4:
+ w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
+ break;
+ case 5:
+ w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
+ break;
+ default:
+ return -EINVAL;
+ }
+ val = readl(w0_addr);
+ writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)),
[PATCH 25/37] drivers: misc: s400_api: Update API for fuse read and write
From: Ye Li
Add API to support fuse read and write
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx8ulp/s400_api.h | 7 +-
drivers/misc/imx8ulp/s400_api.c | 81
2 files changed, 87 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
index 41ad4002b1..c848f0dfb8 100644
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -14,8 +14,11 @@
#define AHAB_AUTH_OEM_CTNR_CID 0x87
#define AHAB_VERIFY_IMG_CID 0x88
#define AHAB_RELEASE_CTNR_CID 0x89
-#define AHAB_RELEASE_RDC_REQ_CID 0xC4
+#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91
#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95
+#define AHAB_READ_FUSE_REQ_CID 0x97
+#define AHAB_RELEASE_RDC_REQ_CID 0xC4
+#define AHAB_WRITE_FUSE_REQ_CID0xD6
#define S400_MAX_MSG 8U
@@ -32,5 +35,7 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
int ahab_verify_image(u32 img_id, u32 *response);
int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
+int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
+int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32
*response);
#endif
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
index 315221a463..d76a95febe 100644
--- a/drivers/misc/imx8ulp/s400_api.c
+++ b/drivers/misc/imx8ulp/s400_api.c
@@ -161,3 +161,84 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
return ret;
}
+
+int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32
*response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ if (!fuse_words) {
+ printf("Invalid parameters for fuse read\n");
+ return -EINVAL;
+ }
+
+ if ((fuse_id != 1 && fuse_num != 1) ||
+ (fuse_id == 1 && fuse_num != 4)) {
+ printf("Invalid fuse number parameter\n");
+ return -EINVAL;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_READ_FUSE_REQ_CID;
+ msg.data[0] = fuse_id;
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+ __func__, ret, fuse_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ fuse_words[0] = msg.data[1];
+ if (fuse_id == 1) {
+ /* OTP_UNIQ_ID */
+ fuse_words[1] = msg.data[2];
+ fuse_words[2] = msg.data[3];
+ fuse_words[3] = msg.data[4];
+ }
+
+ return ret;
+}
+
+int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 3;
+ msg.command = AHAB_WRITE_FUSE_REQ_CID;
+ msg.data[0] = (32 << 16) | (fuse_id << 5);
+ if (lock)
+ msg.data[0] |= (1 << 31);
+
+ msg.data[1] = fuse_val;
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+ __func__, ret, fuse_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
--
2.30.0
[PATCH 24/37] drivers: misc: imx8ulp: Update S400 API for release RDC
From: Ye Li
The RDC API is updated to add a field for XRDC or TRDC
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx8ulp/s400_api.h | 2 +-
drivers/misc/imx8ulp/s400_api.c | 7 +--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
index 30dab8be24..41ad4002b1 100644
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -27,7 +27,7 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
-int ahab_release_rdc(u8 core_id, u32 *response);
+int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response);
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
int ahab_verify_image(u32 img_id, u32 *response);
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
index 4047d6efee..315221a463 100644
--- a/drivers/misc/imx8ulp/s400_api.c
+++ b/drivers/misc/imx8ulp/s400_api.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int ahab_release_rdc(u8 core_id, u32 *response)
+int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
int size = sizeof(struct imx8ulp_s400_msg);
@@ -30,7 +30,10 @@ int ahab_release_rdc(u8 core_id, u32 *response)
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_RELEASE_RDC_REQ_CID;
- msg.data[0] = core_id;
+ if (xrdc)
+ msg.data[0] = (0x78 << 8) | core_id;
+ else
+ msg.data[0] = (0x74 << 8) | core_id;
ret = misc_call(dev, false, , size, , size);
if (ret)
--
2.30.0
[PATCH 23/37] drivers: misc: imx8ulp: Add S400 API for image authentication
From: Ye Li
Add S400 API for image authentication
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/s400_api.h | 8 +-
drivers/misc/imx8ulp/s400_api.c | 121 ++-
2 files changed, 127 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
index 3ba6b525c5..30dab8be24 100644
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -15,6 +15,7 @@
#define AHAB_VERIFY_IMG_CID 0x88
#define AHAB_RELEASE_CTNR_CID 0x89
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
+#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95
#define S400_MAX_MSG 8U
@@ -26,5 +27,10 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
-int ahab_release_rdc(u8 core_id);
+int ahab_release_rdc(u8 core_id, u32 *response);
+int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
+int ahab_release_container(u32 *response);
+int ahab_verify_image(u32 img_id, u32 *response);
+int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
+
#endif
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
index 82fd3117a4..4047d6efee 100644
--- a/drivers/misc/imx8ulp/s400_api.c
+++ b/drivers/misc/imx8ulp/s400_api.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int ahab_release_rdc(u8 core_id)
+int ahab_release_rdc(u8 core_id, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
int size = sizeof(struct imx8ulp_s400_msg);
@@ -37,5 +37,124 @@ int ahab_release_rdc(u8 core_id)
printf("Error: %s: ret %d, core id %u, response 0x%x\n",
__func__, ret, core_id, msg.data[0]);
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 3;
+ msg.command = AHAB_AUTH_OEM_CTNR_CID;
+ msg.data[0] = upper_32_bits(ctnr_addr);
+ msg.data[1] = lower_32_bits(ctnr_addr);
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, cntr_addr 0x%lx, response 0x%x\n",
+ __func__, ret, ctnr_addr, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_release_container(u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = AHAB_RELEASE_CTNR_CID;
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_verify_image(u32 img_id, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_VERIFY_IMG_CID;
+ msg.data[0] = 1 << img_id;
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, img_id %u, response 0x%x\n",
+ __func__, ret, img_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_FWD_LIFECYCLE_UP_REQ_CID;
+ msg.data[0] = life_cycle;
+
+ ret = misc_call(dev, false, , size, , size);
+ if (ret)
+ printf("Error: %s: ret %d, life_cycle 0x%x, response 0x%x\n",
+ __func__, ret, life_cycle, msg.data[0]);
+
+ if
[PATCH 20/37] arm: imx8ulp: disable wdog3
From: Peng Fan
Disable wdog3 which is configured by ROM
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 36 -
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index be7d3d7259..a1c229c4f0 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -144,9 +144,43 @@ int print_cpuinfo(void)
}
#endif
+#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
+#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
+#define REFRESH_WORD0 0xA602 /* 1st refresh word */
+#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
+
+static void disable_wdog(void __iomem *wdog_base)
+{
+ u32 val_cs = readl(wdog_base + 0x00);
+
+ if (!(val_cs & 0x80))
+ return;
+
+ dmb();
+ __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
+ __raw_writel(REFRESH_WORD1, (wdog_base + 0x04));
+ dmb();
+
+ if (!(val_cs & 800)) {
+ dmb();
+ __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04));
+ __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04));
+ dmb();
+
+ while (!(readl(wdog_base + 0x00) & 0x800))
+ ;
+ }
+ writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
+ writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
+ writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
+
+ while (!(readl(wdog_base + 0x00) & 0x400))
+ ;
+}
+
void init_wdog(void)
{
- /* TODO */
+ disable_wdog((void __iomem *)WDG3_RBASE);
}
void s_init(void)
--
2.30.0
[PATCH 21/37] arm: imx8ulp: Update the reset vector in u-boot
From: Ye Li
Because we have set reset vector to ATF in SPL, have to set it back
to ROM for any reset in u-boot
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 35 +
1 file changed, 22 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index a1c229c4f0..044758157f 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -318,21 +318,10 @@ void get_board_serial(struct tag_serialnr *serialnr)
}
#endif
-int arch_cpu_init(void)
+static void set_core0_reset_vector(u32 entry)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
- clock_init();
-
- return 0;
-}
-
-#if defined(CONFIG_SPL_BUILD)
-__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
-{
- debug("image entry point: 0x%lx\n", spl_image->entry_point);
-
/* Update SIM1 DGO8 for reset vector base */
- writel((u32)spl_image->entry_point, SIM1_BASE_ADDR + 0x5c);
+ writel(entry, SIM1_BASE_ADDR + 0x5c);
/* set update bit */
setbits_le32(SIM1_BASE_ADDR + 0x8, 0x1 << 24);
@@ -346,6 +335,26 @@ __weak void __noreturn jump_to_image_no_args(struct
spl_image_info *spl_image)
/* clear the ack by set 1 */
setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
+}
+
+int arch_cpu_init(void)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ clock_init();
+ } else {
+ /* reconfigure core0 reset vector to ROM */
+ set_core0_reset_vector(0x1000);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ debug("image entry point: 0x%lx\n", spl_image->entry_point);
+
+ set_core0_reset_vector((u32)spl_image->entry_point);
/* Enable the 512KB cache */
setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 4));
--
2.30.0
[PATCH 18/37] arm: imx8ulp: soc: Change to use CMC1 to get bootcfg
From: Ye Li
CMC1 also has a MR register for bootcfg
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx8ulp/soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 5d291f6b3a..8f34eccfc2 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -23,7 +23,7 @@ enum bt_mode get_boot_mode(void)
{
u32 bt0_cfg = 0;
- bt0_cfg = readl(CMC0_RBASE + 0x80);
+ bt0_cfg = readl(CMC1_BASE_ADDR + 0xa0);
bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
--
2.30.0
[PATCH 10/37] arm: imx8ulp: add container support
From: Ye Li
i.MX8ULP support using ROM API to load container image,
it use same ROM API as i.MX8MN/MP, and use same container format
as i.MX8QM/QXP.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 2 +
arch/arm/include/asm/mach-imx/image.h | 2 +
arch/arm/include/asm/mach-imx/sys_proto.h | 2 +-
arch/arm/mach-imx/Kconfig | 2 +-
arch/arm/mach-imx/image-container.c | 42 -
arch/arm/mach-imx/imx8ulp/soc.c | 2 +
arch/arm/mach-imx/spl_imx_romapi.c| 171 ++
7 files changed, 176 insertions(+), 47 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 8894611a0f..a8f632f45e 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -10,5 +10,7 @@
extern unsigned long rom_pointer[];
+ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
+ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
enum bt_mode get_boot_mode(void);
#endif
diff --git a/arch/arm/include/asm/mach-imx/image.h
b/arch/arm/include/asm/mach-imx/image.h
index 547beeb986..ee67ca96f4 100644
--- a/arch/arm/include/asm/mach-imx/image.h
+++ b/arch/arm/include/asm/mach-imx/image.h
@@ -64,4 +64,6 @@ struct generate_key_blob_hdr {
u8 algorithm;
u8 mode;
} __packed;
+
+int get_container_size(ulong addr, u16 *header_length);
#endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index ac1ab48a31..17b9140490 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -141,7 +141,7 @@ struct rproc_att {
u32 size; /* size of reg range */
};
-#ifdef CONFIG_IMX8M
+#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP)
struct rom_api {
u16 ver;
u16 tag;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 26bfc5ccc4..c089664375 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -161,7 +161,7 @@ config DDRMC_VF610_CALIBRATION
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
- depends on IMX8MN || IMX8MP
+ depends on IMX8MN || IMX8MP || IMX8ULP
config IMX_DCD_ADDR
hex "DCD Blocks location on the image"
diff --git a/arch/arm/mach-imx/image-container.c
b/arch/arm/mach-imx/image-container.c
index 9e18f6630f..c3f62872c6 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -19,8 +19,9 @@
#define QSPI_DEV 1
#define NAND_DEV 2
#define QSPI_NOR_DEV 3
+#define ROM_API_DEV4
-static int __get_container_size(ulong addr)
+int get_container_size(ulong addr, u16 *header_length)
{
struct container_hdr *phdr;
struct boot_img_t *img_entry;
@@ -34,7 +35,9 @@ static int __get_container_size(ulong addr)
return -EFAULT;
}
- max_offset = sizeof(struct container_hdr);
+ max_offset = phdr->length_lsb + (phdr->length_msb << 8);
+ if (header_length)
+ *header_length = max_offset;
img_entry = (struct boot_img_t *)(addr + sizeof(struct container_hdr));
for (i = 0; i < phdr->num_images; i++) {
@@ -60,7 +63,7 @@ static int __get_container_size(ulong addr)
return max_offset;
}
-static int get_container_size(void *dev, int dev_type, unsigned long offset)
+static int get_dev_container_size(void *dev, int dev_type, unsigned long
offset, u16 *header_length)
{
u8 *buf = malloc(CONTAINER_HDR_ALIGNMENT);
int ret = 0;
@@ -115,7 +118,17 @@ static int get_container_size(void *dev, int dev_type,
unsigned long offset)
memcpy(buf, (const void *)offset, CONTAINER_HDR_ALIGNMENT);
#endif
- ret = __get_container_size((ulong)buf);
+#ifdef CONFIG_SPL_BOOTROM_SUPPORT
+ if (dev_type == ROM_API_DEV) {
+ ret = spl_romapi_raw_seekable_read(offset,
CONTAINER_HDR_ALIGNMENT, buf);
+ if (!ret) {
+ printf("Read container image from ROM API failed\n");
+ return -EIO;
+ }
+ }
+#endif
+
+ ret = get_container_size((ulong)buf, header_length);
free(buf);
@@ -149,6 +162,8 @@ static unsigned long get_boot_device_offset(void *dev, int
dev_type)
offset = CONTAINER_HDR_NAND_OFFSET;
} else if (dev_type == QSPI_NOR_DEV) {
offset = CONTAINER_HDR_QSPI_OFFSET + 0x0800;
+ } else if (dev_type == ROM_API_DEV) {
+ offset = (unsigned long)dev;
}
return offset;
@@ -158,11 +173,12 @@ static int get_imageset_end(void *dev, int dev_type)
{
unsigned long offset1 = 0, offset2 = 0;
int value_container[2];
+ u16 hdr_length;
offset1 =
[PATCH 11/37] arm: imx: move container Kconfig under mach-imx
From: Peng Fan Since i.MX8 and i.MX8ULP reuse common container, so move the Kconfig public to both. Signed-off-by: Peng Fan --- arch/arm/mach-imx/Kconfig | 13 + arch/arm/mach-imx/imx8/Kconfig | 13 - 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index c089664375..653463ab46 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -172,3 +172,16 @@ config IMX_DCD_ADDR the ROM code to configure the device at early boot stage, is located. This information is shared with the user via mkimage -l just so the image can be signed. + +config SPL_LOAD_IMX_CONTAINER + bool "Enable SPL loading U-Boot as a i.MX Container image" + depends on SPL + help + This is to let SPL could load i.MX Container image + +config IMX_CONTAINER_CFG + string "i.MX Container config file" + depends on SPL + help + This is to specific the cfg file for generating container + image which will be loaded by SPL. diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 4e76612d05..4ad9ca8191 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -31,19 +31,6 @@ config IMX8QXP config SYS_SOC default "imx8" -config SPL_LOAD_IMX_CONTAINER - bool "Enable SPL loading U-Boot as a i.MX Container image" - depends on SPL - help - This is to let SPL could load i.MX8 Container image - -config IMX_CONTAINER_CFG - string "i.MX Container config file" - depends on SPL - help - This is to specific the cfg file for generating container - image which will be loaded by SPL. - config BOOTAUX_RESERVED_MEM_BASE hex "i.MX auxiliary core dram memory base" default 0 -- 2.30.0
[PATCH 09/37] arm: imx: parse-container: guard included header files
From: Peng Fan Guard included sci.h with CONFIG_AHAB_BOOT to avoid build failure for i.MX8ULP Signed-off-by: Peng Fan --- arch/arm/mach-imx/parse-container.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/parse-container.c b/arch/arm/mach-imx/parse-container.c index e4354bf930..039a4c7303 100644 --- a/arch/arm/mach-imx/parse-container.c +++ b/arch/arm/mach-imx/parse-container.c @@ -8,7 +8,9 @@ #include #include #include +#ifdef CONFIG_AHAB_BOOT #include +#endif #define SEC_SECURE_RAM_BASE0x3180UL #define SEC_SECURE_RAM_END_BASE(SEC_SECURE_RAM_BASE + 0xUL) -- 2.30.0
[PATCH 07/37] arm: imx8: Move container parser and image to mach-imx common folder
From: Ye Li
Since we will re-use the container parser on imx8ulp, move the codes
to mach-imx
Signed-off-by: Ye Li
---
arch/arm/mach-imx/Makefile| 4
arch/arm/mach-imx/{imx8/image.c => image-container.c} | 0
arch/arm/mach-imx/imx8/Makefile | 3 ---
arch/arm/mach-imx/{imx8 => }/parse-container.c| 0
4 files changed, 4 insertions(+), 3 deletions(-)
rename arch/arm/mach-imx/{imx8/image.c => image-container.c} (100%)
rename arch/arm/mach-imx/{imx8 => }/parse-container.c (100%)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 36224d8db9..0ef269563d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -68,6 +68,10 @@ obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o
endif
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o parse-container.o
+endif
+
PLUGIN = board/$(BOARDDIR)/plugin
ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
diff --git a/arch/arm/mach-imx/imx8/image.c
b/arch/arm/mach-imx/image-container.c
similarity index 100%
rename from arch/arm/mach-imx/imx8/image.c
rename to arch/arm/mach-imx/image-container.c
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
index bbb41adbe4..4ca4c14bdd 100644
--- a/arch/arm/mach-imx/imx8/Makefile
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -8,7 +8,4 @@ obj-y += cpu.o iomux.o misc.o lowlevel_init.o
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
obj-$(CONFIG_AHAB_BOOT) += ahab.o
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image.o parse-container.o
-endif
obj-$(CONFIG_IMX_SNVS_SEC_SC) += snvs_security_sc.o
diff --git a/arch/arm/mach-imx/imx8/parse-container.c
b/arch/arm/mach-imx/parse-container.c
similarity index 100%
rename from arch/arm/mach-imx/imx8/parse-container.c
rename to arch/arm/mach-imx/parse-container.c
--
2.30.0
[PATCH 08/37] arm: imx8: Move container image header file to mach-imx
From: Ye Li
Since the container is shared among i.MX platforms, move its header file
to mach-imx
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/{arch-imx8 => mach-imx}/image.h | 0
arch/arm/mach-imx/cmd_dek.c | 2 +-
arch/arm/mach-imx/image-container.c | 2 +-
arch/arm/mach-imx/imx8/ahab.c| 2 +-
arch/arm/mach-imx/parse-container.c | 2 +-
5 files changed, 4 insertions(+), 4 deletions(-)
rename arch/arm/include/asm/{arch-imx8 => mach-imx}/image.h (100%)
diff --git a/arch/arm/include/asm/arch-imx8/image.h
b/arch/arm/include/asm/mach-imx/image.h
similarity index 100%
rename from arch/arm/include/asm/arch-imx8/image.h
rename to arch/arm/include/asm/mach-imx/image.h
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index b10ead1942..b81c24d7ef 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -17,7 +17,7 @@
#include
#ifdef CONFIG_IMX_SECO_DEK_ENCAP
#include
-#include
+#include
#endif
#include
diff --git a/arch/arm/mach-imx/image-container.c
b/arch/arm/mach-imx/image-container.c
index 5abc0d3a39..9e18f6630f 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -11,7 +11,7 @@
#include
#include
#include
-#include
+#include
#include
#include
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index 6392fe267a..39721b0ac0 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -13,7 +13,7 @@
#include
#include
#include
-#include
+#include
#include
#include
diff --git a/arch/arm/mach-imx/parse-container.c
b/arch/arm/mach-imx/parse-container.c
index 375098902f..e4354bf930 100644
--- a/arch/arm/mach-imx/parse-container.c
+++ b/arch/arm/mach-imx/parse-container.c
@@ -7,7 +7,7 @@
#include
#include
#include
-#include
+#include
#include
#define SEC_SECURE_RAM_BASE0x3180UL
--
2.30.0
[PATCH 06/37] arm: imx: basic i.MX8ULP support
From: Peng Fan
Add basic i.MX8ULP support
For the MMU part, Using a simple way the calculate the MMU size to avoid
default heavy calcaulation. And align address and size in the table
settings to 2MB or 4GB as much as possible. So we can reduce the 4K page
allocations in MMU table which will spends much time in create the
page table
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/Makefile | 4 +-
arch/arm/include/asm/arch-imx8ulp/clock.h | 34
arch/arm/include/asm/arch-imx8ulp/ddr.h | 38 +
arch/arm/include/asm/arch-imx8ulp/gpio.h | 20 +++
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 131 +++
.../include/asm/arch-imx8ulp/imx8ulp-pins.h | 60 +++
arch/arm/mach-imx/Makefile| 1 +
arch/arm/mach-imx/imx8ulp/Makefile| 7 +
arch/arm/mach-imx/imx8ulp/clock.c | 27
arch/arm/mach-imx/imx8ulp/iomux.c | 4 +
arch/arm/mach-imx/imx8ulp/lowlevel_init.S | 32
arch/arm/mach-imx/imx8ulp/soc.c | 151 +-
12 files changed, 505 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/clock.h
create mode 100644 arch/arm/include/asm/arch-imx8ulp/ddr.h
create mode 100644 arch/arm/include/asm/arch-imx8ulp/gpio.h
create mode 100644 arch/arm/include/asm/arch-imx8ulp/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h
create mode 100644 arch/arm/mach-imx/imx8ulp/Makefile
create mode 100644 arch/arm/mach-imx/imx8ulp/clock.c
create mode 100644 arch/arm/mach-imx/imx8ulp/iomux.c
create mode 100644 arch/arm/mach-imx/imx8ulp/lowlevel_init.S
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 28b523b37c..c68e598a67 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -107,11 +107,11 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5
mx6 mx7 mx35 imx8m imx8 imxrt))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5
mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
libs-y += arch/arm/mach-imx/
endif
else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8
imxrt vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8
imx8ulp imxrt vf610))
libs-y += arch/arm/mach-imx/
endif
endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h
b/arch/arm/include/asm/arch-imx8ulp/clock.h
new file mode 100644
index 00..e145c33f01
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/clock.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef _ASM_ARCH_IMX8ULP_CLOCK_H
+#define _ASM_ARCH_IMX8ULP_CLOCK_H
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
+ MXC_AXI_CLK,
+ MXC_DDR_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_I2C_CLK,
+};
+
+u32 mxc_get_clock(enum mxc_clock clk);
+u32 get_lpuart_clk(void);
+#ifdef CONFIG_SYS_I2C_IMX_LPI2C
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
+u32 imx_get_i2cclk(unsigned int i2c_num);
+#endif
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable);
+#endif
+void init_clk_usdhc(u32 index);
+void clock_init(void);
+#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/ddr.h
b/arch/arm/include/asm/arch-imx8ulp/ddr.h
new file mode 100644
index 00..4544431b05
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/ddr.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8ULP_DDR_H
+#define __ASM_ARCH_IMX8ULP_DDR_H
+
+#include
+#include
+
+struct dram_cfg_param {
+ unsigned int reg;
+ unsigned int val;
+};
+
+struct dram_timing_info2 {
+ /* ddr controller config */
+ struct dram_cfg_param *ctl_cfg;
+ unsigned int ctl_cfg_num;
+ /* pi config */
+ struct dram_cfg_param *pi_cfg;
+ unsigned int pi_cfg_num;
+ /* phy freq1 config */
+ struct dram_cfg_param *phy_f1_cfg;
+ unsigned int phy_f1_cfg_num;
+ /* phy freq2 config */
+ struct dram_cfg_param *phy_f2_cfg;
+ unsigned int phy_f2_cfg_num;
+ /* initialized drate table */
+ unsigned int fsp_table[3];
+};
+
+extern struct dram_timing_info2 dram_timing;
+
+int ddr_init(struct dram_timing_info2 *dram_timing);
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/gpio.h
b/arch/arm/include/asm/arch-imx8ulp/gpio.h
new file mode 100644
index 00..b7563bb401
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/gpio.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8ULP_GPIO_H
+#define __ASM_ARCH_IMX8ULP_GPIO_H
+
+struct gpio_regs {
+
[PATCH 05/37] imx: imx8ulp: add get reset cause
From: Peng Fan
Add get reset cause function to show what triggerred reset.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8ulp/soc.c | 69 +
1 file changed, 69 insertions(+)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index e6ac5f8d25..383dbe6000 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -32,6 +32,73 @@ enum bt_mode get_boot_mode(void)
return LOW_POWER_BOOT;
}
+#define CMC_SRS_TAMPERBIT(31)
+#define CMC_SRS_SECURITY BIT(30)
+#define CMC_SRS_TZWDG BIT(29)
+#define CMC_SRS_JTAG_RST BIT(28)
+#define CMC_SRS_CORE1 BIT(16)
+#define CMC_SRS_LOCKUPBIT(15)
+#define CMC_SRS_SWBIT(14)
+#define CMC_SRS_WDG BIT(13)
+#define CMC_SRS_PIN_RESET BIT(8)
+#define CMC_SRS_WARM BIT(4)
+#define CMC_SRS_HVD BIT(3)
+#define CMC_SRS_LVD BIT(2)
+#define CMC_SRS_POR BIT(1)
+#define CMC_SRS_WUP BIT(0)
+
+static u32 reset_cause = -1;
+
+static char *get_reset_cause(char *ret)
+{
+ u32 cause1, cause = 0, srs = 0;
+ void __iomem *reg_ssrs = (void __iomem *)(SRC_BASE_ADDR + 0x88);
+ void __iomem *reg_srs = (void __iomem *)(SRC_BASE_ADDR + 0x80);
+
+ if (!ret)
+ return "null";
+
+ srs = readl(reg_srs);
+ cause1 = readl(reg_ssrs);
+
+ reset_cause = cause1;
+
+ cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
+
+ switch (cause) {
+ case CMC_SRS_POR:
+ sprintf(ret, "%s", "POR");
+ break;
+ case CMC_SRS_WUP:
+ sprintf(ret, "%s", "WUP");
+ break;
+ case CMC_SRS_WARM:
+ cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
+ CMC_SRS_JTAG_RST);
+ switch (cause) {
+ case CMC_SRS_WDG:
+ sprintf(ret, "%s", "WARM-WDG");
+ break;
+ case CMC_SRS_SW:
+ sprintf(ret, "%s", "WARM-SW");
+ break;
+ case CMC_SRS_JTAG_RST:
+ sprintf(ret, "%s", "WARM-JTAG");
+ break;
+ default:
+ sprintf(ret, "%s", "WARM-UNKN");
+ break;
+ }
+ break;
+ default:
+ sprintf(ret, "%s-%X", "UNKN", cause1);
+ break;
+ }
+
+ debug("[%X] SRS[%X] %X - ", cause1, srs, srs ^ cause1);
+ return ret;
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
const char *get_imx_type(u32 imxtype)
{
@@ -50,6 +117,8 @@ int print_cpuinfo(void)
(cpurev & 0x000F0) >> 4, (cpurev & 0xF) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 100);
+ printf("Reset cause: %s\n", get_reset_cause(cause));
+
printf("Boot mode: ");
switch (get_boot_mode()) {
case LOW_POWER_BOOT:
--
2.30.0
[PATCH 03/37] arm: imx: sys_proto: move boot mode define to common header
From: Peng Fan
These defines could be reused by i.MX8ULP, so move them
to common header.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 9 -
arch/arm/include/asm/mach-imx/sys_proto.h| 10 ++
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
index 0e4c8ad15d..0daa922fad 100644
--- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
@@ -8,14 +8,5 @@
#include
-#define BT0CFG_LPBOOT_MASK 0x1
-#define BT0CFG_DUALBOOT_MASK 0x2
-
-enum bt_mode {
- LOW_POWER_BOOT, /* LP_BT = 1 */
- DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */
- SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */
-};
-
enum boot_device get_boot_device(void);
#endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index ea746ae6ee..ac1ab48a31 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -174,6 +174,16 @@ enum boot_dev_type_e {
extern struct rom_api *g_rom_api;
#endif
+/* For i.MX ULP */
+#define BT0CFG_LPBOOT_MASK 0x1
+#define BT0CFG_DUALBOOT_MASK 0x2
+
+enum bt_mode {
+ LOW_POWER_BOOT, /* LP_BT = 1 */
+ DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */
+ SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */
+};
+
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
u32 get_cpu_speed_grade_hz(void);
--
2.30.0
[PATCH 04/37] arm: imx8ulp: support print cpu info
From: Peng Fan
Support print cpu info. the clock function has not been added, it will
be added in following patches.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 3 +
arch/arm/mach-imx/imx8ulp/soc.c | 59 +++
2 files changed, 62 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index cab12c218e..8894611a0f 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -8,4 +8,7 @@
#include
+extern unsigned long rom_pointer[];
+
+enum bt_mode get_boot_mode(void);
#endif
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index b3679aefcb..e6ac5f8d25 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -3,9 +3,68 @@
* Copyright 2021 NXP
*/
+#include
+#include
+#include
#include
+#include
u32 get_cpu_rev(void)
{
return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0;
}
+
+enum bt_mode get_boot_mode(void)
+{
+ u32 bt0_cfg = 0;
+
+ bt0_cfg = readl(CMC0_RBASE + 0x80);
+ bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
+
+ if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
+ /* No low power boot */
+ if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
+ return DUAL_BOOT;
+ else
+ return SINGLE_BOOT;
+ }
+
+ return LOW_POWER_BOOT;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+const char *get_imx_type(u32 imxtype)
+{
+ return "8ULP";
+}
+
+int print_cpuinfo(void)
+{
+ u32 cpurev;
+ char cause[18];
+
+ cpurev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
+ get_imx_type((cpurev & 0xFF000) >> 12),
+ (cpurev & 0x000F0) >> 4, (cpurev & 0xF) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 100);
+
+ printf("Boot mode: ");
+ switch (get_boot_mode()) {
+ case LOW_POWER_BOOT:
+ printf("Low power boot\n");
+ break;
+ case DUAL_BOOT:
+ printf("Dual boot\n");
+ break;
+ case SINGLE_BOOT:
+ default:
+ printf("Single boot\n");
+ break;
+ }
+
+ return 0;
+}
+#endif
+
--
2.30.0
[PATCH 02/37] arm: imx: add i.MX8ULP cpu type and helper
From: Peng Fan
Add i.MX8ULP cpu type and helpers.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx/cpu.h | 2 ++
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 11 +++
arch/arm/include/asm/mach-imx/sys_proto.h | 1 +
arch/arm/mach-imx/imx8ulp/soc.c | 11 +++
4 files changed, 25 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8ulp/sys_proto.h
create mode 100644 arch/arm/mach-imx/imx8ulp/soc.c
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index bb13e07b66..2969d1f9f9 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -50,6 +50,8 @@
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP0x92 /* dummy ID */
+#define MXC_CPU_IMX8ULP0xA1 /* dummy ID */
+
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
new file mode 100644
index 00..cab12c218e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __ARCH_IMX8ULP_SYS_PROTO_H
+#define __ARCH_NMX8ULP_SYS_PROTO_H
+
+#include
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index c7668ffc4d..ea746ae6ee 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -50,6 +50,7 @@ struct bd_info;
#define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD))
#define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL))
#define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
+#define is_imx8ulp() (is_cpu_type(MXC_CPU_IMX8ULP))
#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) ||
is_cpu_type(MXC_CPU_IMX8MML) ||\
is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
new file mode 100644
index 00..b3679aefcb
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+#include
+
+u32 get_cpu_rev(void)
+{
+ return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0;
+}
--
2.30.0
[PATCH 00/37] imx: add i.MX8ULP support
From: Peng Fan
The i.MX 8ULP crossover applications processor family brings
ultra-low power processing and advanced integrated security with
EdgeLockTM secure enclave to the intelligent edge.
This patchset is to add initial support for i.MX8ULP, with
core soc functions, clock, dtsi, and evk board.
Peng Fan (20):
arm: imx: add i.MX8ULP basic Kconfig option
arm: imx: add i.MX8ULP cpu type and helper
arm: imx: sys_proto: move boot mode define to common header
arm: imx8ulp: support print cpu info
imx: imx8ulp: add get reset cause
arm: imx: basic i.MX8ULP support
arm: imx: parse-container: guard included header files
arm: imx: move container Kconfig under mach-imx
net: fec_mxc: support i.MX8ULP
driver: serial: fsl_lpuart: support i.MX8ULP
arm: imx8ulp: add clock support
drivers: mmc: fsl_esdhc_imx: support i.MX8ULP
arm: imx8ulp: disable wdog3
arm: imx8ulp: add xrdc support
arm: imx8ulp: add trdc release request
arm: imx8ulp: release trdc and assign lpav from RTD to APD
arm: imx8ulp: add dummy imx_get_mac_from_fuse
arm: imx8ulp: add iomuxc support
arm: dts: add i.MX8ULP dtsi
arm: imx: add i.MX8ULP EVK support
Ye Li (17):
arm: imx8: Move container parser and image to mach-imx common folder
arm: imx8: Move container image header file to mach-imx
arm: imx8ulp: add container support
driver: misc: Add MU and S400 API to communicate with Sentinel
pinctrl: Add pinctrl driver for imx8ulp
arm: imx8ulp: soc: Change to use CMC1 to get bootcfg
arm: imx8ulp: Enable full L2 cache in SPL
arm: imx8ulp: Update the reset vector in u-boot
drivers: misc: s400_api: Update S400_SUCCESS_IND to 0xd6
drivers: misc: imx8ulp: Add S400 API for image authentication
drivers: misc: imx8ulp: Update S400 API for release RDC
drivers: misc: s400_api: Update API for fuse read and write
arm: imx8ulp: release and configure XRDC at early phase
arm: imx8ulp: Probe the S400 MU device in arch init
arm: iMX8ULP: Add boot device relevant functions
arm: imx8ulp: Allocate DCNANO and MIPI_DSI to AD domain
driver: misc: imx8ulp: Add fuse driver for imx8ulp
arch/arm/Kconfig | 10 +
arch/arm/Makefile |4 +-
arch/arm/dts/imx8ulp-emulator-u-boot.dtsi | 32 +
arch/arm/dts/imx8ulp-emulator.dts | 93 +
arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 32 +
arch/arm/dts/imx8ulp-evk.dts | 204 ++
arch/arm/dts/imx8ulp-pinfunc.h| 978 ++
arch/arm/dts/imx8ulp.dtsi | 706 +++
arch/arm/include/asm/arch-imx/cpu.h |2 +
arch/arm/include/asm/arch-imx8ulp/cgc.h | 130 ++
arch/arm/include/asm/arch-imx8ulp/clock.h | 41 +
arch/arm/include/asm/arch-imx8ulp/ddr.h | 38 +
arch/arm/include/asm/arch-imx8ulp/gpio.h | 20 +
arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 134 ++
.../include/asm/arch-imx8ulp/imx8ulp-pins.h | 60 +
arch/arm/include/asm/arch-imx8ulp/iomux.h | 82 +
arch/arm/include/asm/arch-imx8ulp/mu_hal.h| 12 +
arch/arm/include/asm/arch-imx8ulp/pcc.h | 139 ++
arch/arm/include/asm/arch-imx8ulp/s400_api.h | 41 +
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 19 +
arch/arm/include/asm/arch-mx7ulp/sys_proto.h |9 -
arch/arm/include/asm/global_data.h|5 +
.../asm/{arch-imx8 => mach-imx}/image.h |2 +
arch/arm/include/asm/mach-imx/sys_proto.h | 13 +-
arch/arm/mach-imx/Kconfig | 15 +-
arch/arm/mach-imx/Makefile|5 +
arch/arm/mach-imx/cmd_dek.c |2 +-
.../{imx8/image.c => image-container.c} | 44 +-
arch/arm/mach-imx/imx8/Kconfig| 13 -
arch/arm/mach-imx/imx8/Makefile |3 -
arch/arm/mach-imx/imx8/ahab.c |2 +-
arch/arm/mach-imx/imx8ulp/Kconfig | 23 +
arch/arm/mach-imx/imx8ulp/Makefile|7 +
arch/arm/mach-imx/imx8ulp/cgc.c | 459 +
arch/arm/mach-imx/imx8ulp/clock.c | 390
arch/arm/mach-imx/imx8ulp/iomux.c | 65 +
arch/arm/mach-imx/imx8ulp/lowlevel_init.S | 26 +
arch/arm/mach-imx/imx8ulp/pcc.c | 449 +
arch/arm/mach-imx/imx8ulp/soc.c | 685 +++
arch/arm/mach-imx/imx8ulp/xrdc.c | 144 ++
.../arm/mach-imx/{imx8 => }/parse-container.c |4 +-
arch/arm/mach-imx/spl_imx_romapi.c| 171 +-
board/freescale/imx8ulp_evk/Kconfig | 14 +
board/freescale/imx8ulp_evk/MAINTAINERS |6 +
board/freescale/imx8ulp_evk/Makefile |7 +
board/freescale/imx8ulp_evk/ddr_init.c| 207 ++
board/freescale/imx8ulp_evk/imx8ulp_evk.c | 67 +
board/freescale/imx8ulp_evk/lpddr4_timing.c | 1696 +
board/freescale/imx8ulp_evk/spl.c | 146 ++
configs/imx8ulp_evk_defconfig | 103 +
[PATCH 01/37] arm: imx: add i.MX8ULP basic Kconfig option
From: Peng Fan Add i.MX8ULP related basic Kconfig option, which will be used later. Signed-off-by: Peng Fan --- arch/arm/Kconfig | 10 ++ arch/arm/mach-imx/imx8ulp/Kconfig | 16 2 files changed, 26 insertions(+) create mode 100644 arch/arm/mach-imx/imx8ulp/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 76adf7fdb2..579a1b05a0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -846,6 +846,14 @@ config ARCH_IMX8M select SUPPORT_SPL imply CMD_DM +config ARCH_IMX8ULP + bool "NXP i.MX8ULP platform" + select ARM64 + select DM + select OF_CONTROL + select SUPPORT_SPL + imply CMD_DM + config ARCH_IMXRT bool "NXP i.MXRT platform" select CPU_V7M @@ -1900,6 +1908,8 @@ source "arch/arm/mach-imx/imx8/Kconfig" source "arch/arm/mach-imx/imx8m/Kconfig" +source "arch/arm/mach-imx/imx8ulp/Kconfig" + source "arch/arm/mach-imx/imxrt/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig" diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig new file mode 100644 index 00..167dbb3fb1 --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -0,0 +1,16 @@ +if ARCH_IMX8ULP + +config IMX8ULP + bool + select ARMV8_SPL_EXCEPTION_VECTORS + +config SYS_SOC + default "imx8ulp" + +choice + prompt "i.MX8ULP board select" + optional + +endchoice + +endif -- 2.30.0
[PATCH] imx: cmd: use struct cmd_tbl
From: Peng Fan
cmd_tbl_t is removed, need use struct cmd_tbl
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/cmd_mfgprot.c | 2 +-
arch/arm/mach-imx/priblob.c | 2 +-
cmd/cmd_fsl_caam.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c
index 1430f61909..47ae9bf1eb 100644
--- a/arch/arm/mach-imx/cmd_mfgprot.c
+++ b/arch/arm/mach-imx/cmd_mfgprot.c
@@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
* Returns zero on success, CMD_RET_USAGE in case of misuse and negative
* on error.
*/
-static int do_mfgprot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static int do_mfgprot(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
{
u8 *m_ptr, *dgst_ptr, *c_ptr, *d_ptr, *dst_ptr;
char *pubk, *sign, *sel;
diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c
index e253eddfdc..9b92eae781 100644
--- a/arch/arm/mach-imx/priblob.c
+++ b/arch/arm/mach-imx/priblob.c
@@ -15,7 +15,7 @@
#include
#include "../drivers/crypto/fsl_caam_internal.h"
-int do_priblob_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_priblob_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const
argv[])
{
writel((readl(CAAM_SCFGR) & 0xFFFC) | 3, CAAM_SCFGR);
printf("New priblob setting = 0x%x\n", readl(CAAM_SCFGR) & 0x3);
diff --git a/cmd/cmd_fsl_caam.c b/cmd/cmd_fsl_caam.c
index d41d672320..95133835d7 100644
--- a/cmd/cmd_fsl_caam.c
+++ b/cmd/cmd_fsl_caam.c
@@ -7,7 +7,7 @@
#include
#include
-static int do_caam(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_caam(struct cmd_tbl *cmdtp, int flag, int argc, char * const
argv[])
{
int ret, i;
--
2.30.0
[PATCH 2/2] driver: watchdog: enable wdt command by default
From: MengLi In latest u-boot code, watchdog feature is implemented, so enable wdt command by default. Signed-off-by: Meng Li --- configs/socfpga_stratix10_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 02d4ac0dae..0256afe511 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_WDT=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- 2.17.1
[PATCH 1/2] driver: watchdog: reset watchdog in designware_wdt_stop() function
From: MengLi
In uboot command line environment, watchdog is not able to be
stopped with below commands:
SOCFPGA_STRATIX10 # wdt dev watchdog@ffd00200
SOCFPGA_STRATIX10 # wdt stop
Refer to watchdog driver in linux kernel, it is also need to reset
watchdog after disable it so that the disable action takes effect.
Signed-off-by: Meng Li
---
drivers/watchdog/designware_wdt.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
index 12f09a7a39..63e89d38c4 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -92,10 +92,27 @@ static int designware_wdt_reset(struct udevice *dev)
static int designware_wdt_stop(struct udevice *dev)
{
struct designware_wdt_priv *priv = dev_get_priv(dev);
+ __maybe_unused int ret;
designware_wdt_reset(dev);
writel(0, priv->base + DW_WDT_CR);
+#if CONFIG_IS_ENABLED(DM_RESET)
+ struct reset_ctl_bulk resets;
+
+ ret = reset_get_bulk(dev, );
+ if (ret)
+ return ret;
+
+ ret = reset_assert_bulk();
+ if (ret)
+ return ret;
+
+ ret = reset_deassert_bulk();
+ if (ret)
+ return ret;
+#endif
+
return 0;
}
--
2.17.1
[PATCH] pwm: sifive: make set_config() and set_enable() work properly
The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work
properly due to the wrong implementations. It will cause the u-boot
PWM command to not work as expected. The bugs will be resolved in this
patch.
Signed-off-by: Vincent Chen
---
drivers/pwm/pwm-sifive.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
index 01212d6..b9813a3 100644
--- a/drivers/pwm/pwm-sifive.c
+++ b/drivers/pwm/pwm-sifive.c
@@ -38,6 +38,9 @@
#define PWM_SIFIVE_SIZE_PWMCMP 4
#define PWM_SIFIVE_CMPWIDTH 16
+#define PWM_SIFIVE_CHANNEL_ENABLE_VAL 0
+#define PWM_SIFIVE_CHANNEL_DISABLE_VAL 0x
+
DECLARE_GLOBAL_DATA_PTR;
struct pwm_sifive_regs {
@@ -77,7 +80,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint
channel,
*/
scale_pow = lldiv((uint64_t)priv->freq * period_ns, 10);
scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
- val |= FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
+ val |= (FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale) |
PWM_SIFIVE_PWMCFG_EN_ALWAYS);
/*
* The problem of output producing mixed setting as mentioned at top,
@@ -88,6 +91,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint
channel,
num = (u64)duty_ns * (1U << PWM_SIFIVE_CMPWIDTH);
frac = DIV_ROUND_CLOSEST_ULL(num, period_ns);
frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
+ frac = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac;
writel(val, priv->base + regs->cfg);
writel(frac, priv->base + regs->cmp0 + channel *
@@ -100,18 +104,15 @@ static int pwm_sifive_set_enable(struct udevice *dev,
uint channel, bool enable)
{
struct pwm_sifive_priv *priv = dev_get_priv(dev);
const struct pwm_sifive_regs *regs = >data->regs;
- u32 val;
debug("%s: Enable '%s'\n", __func__, dev->name);
- if (enable) {
- val = readl(priv->base + regs->cfg);
- val |= PWM_SIFIVE_PWMCFG_EN_ALWAYS;
- writel(val, priv->base + regs->cfg);
- } else {
- writel(0, priv->base + regs->cmp0 + channel *
- PWM_SIFIVE_SIZE_PWMCMP);
- }
+ if (enable)
+ writel(PWM_SIFIVE_CHANNEL_ENABLE_VAL, priv->base +
+ regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
+ else
+ writel(PWM_SIFIVE_CHANNEL_DISABLE_VAL, priv->base +
+ regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
return 0;
}
--
2.7.4
