On Tue, Sep 14, 2021 at 12:14:31PM +0530, Ruchika Gupta wrote:
> TCG EFI Protocol Specification defines the number_of_algorithms
> field in spec ID event to be equal to the number of active
> algorithms supported by the TPM device. In current implementation,
> this field is populated with the
On Sat, Sep 11, 2021 at 10:31:23PM +0800, Bin Meng wrote:
> Commit 47d73ba4f4a4 ("board: sifive: overwrite board_fdt_blob_setup in u-boot
> proper")
> added a board-specific implementation of board_fdt_blob_setup() which
> takes a pointer as the return value, but it does not return anything
> if
On Sat, Sep 11, 2021 at 01:20:01PM -0400, Sean Anderson wrote:
> Everything here sits in a while (true) loop. However, this introduces a
> couple of layers of indentation. We can simplify the code by introducing a
> single goto instead of using continue/break. This will also make adding
> loops in
On Sat, Sep 11, 2021 at 01:20:00PM -0400, Sean Anderson wrote:
> The PLL functions take ulong arguments for rate, but still check if that
> rate is negative (which is never true). The correct way to handle this is
> to use IS_ERR_VALUE (like is already done in k210_clk_set_rate). While
> we're at
On Sat, Sep 11, 2021 at 01:20:02PM -0400, Sean Anderson wrote:
> Having to copy-paste the same 3 lines makes adding new test cases
> error-prone. Use a macro.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Simon Glass
> ---
>
> (no changes since v1)
>
> test/dm/k210_pll.c | 30
In 92055e138f ("image: Drop if/elseif hash selection in calculate_hash()")
the FIT image hash verification code was simplified to use the hash API.
This broke verification of CRC32 hash FIT images (e.g NXP MC firmware)
as the hash API crc32 calculates in big endian (refer commit
74a18ee8a563,
On Sun, Sep 12, 2021 at 09:11:47PM +0200, Heinrich Schuchardt wrote:
> There should be a platform compiled with the new driver.
>
> Enable CONFIG_SYSRESET_SBI for all QEMU boards using SBI.
>
> If you want to test the SBI sysreset driver, disable
> CONFIG_SYSRESET_SYSCON.
>
> Signed-off-by:
Hi Stefan and Tom,
I finally managed to find a Disk Mini v2 Ethernet card and I will be
working on the DM conversion as soon as possible.
Please, let me know what is my deadline to complete this job ?
Simon
On Fri, Sep 10, 2021 at 06:41:14AM +0200, Stefan Roese wrote:
> Hi Simon,
>
> On
On Tue, Sep 14, 2021 at 12:13 PM Ramon Fried wrote:
>
> On Sun, Aug 15, 2021 at 5:09 PM Lyle Franklin wrote:
> >
> > From: Lyle Franklin
> > Date: Sun, 15 Aug 2021 07:17:14 -0400
> > Subject: [PATCH] Allow colon in PXE bootfile URLs
> >
> > - U-boot's PXE flow supports prefixing your bootfile
On Tue, Aug 24, 2021 at 3:01 PM Vladimir Oltean wrote:
>
> This snippet of code has a bothering "if (...) return 0" in it which
> assumes it is the last piece of code running in dsa_port_probe().
>
> This makes it difficult to add further code at the end of dsa_port_probe()
> which does not
On Tue, Aug 24, 2021 at 3:01 PM Vladimir Oltean wrote:
>
> No one is calling this function from outside felix_switch.c.
>
> Signed-off-by: Vladimir Oltean
> Reviewed-by: Ramon Fried
> Tested-by: Michael Walle
> ---
> drivers/net/mscc_eswitch/felix_switch.c | 2 +-
> 1 file changed, 1
On Tue, Aug 24, 2021 at 3:01 PM Vladimir Oltean wrote:
>
> Make sure that the link status returned by phy_startup() is propagated
> to the .start() method of struct eth_ops.
>
> Signed-off-by: Vladimir Oltean
> Reviewed-by: Ramon Fried
> Tested-by: Michael Walle
> ---
>
On Tue, Aug 24, 2021 at 3:01 PM Vladimir Oltean wrote:
>
> Some drivers might want to execute code for each port at probe time, as
> opposed to executing code just-in-time for the port selected for
> networking.
>
> To cater to that use case, introduce a .port_probe() callback method
> into the
On Tue, Aug 24, 2021 at 3:01 PM Vladimir Oltean wrote:
>
> DM DSA uses "err" for error code values, so use this consistently.
>
> Signed-off-by: Vladimir Oltean
> Reviewed-by: Ramon Fried
> Tested-by: Michael Walle
> ---
> net/dsa-uclass.c | 8
> 1 file changed, 4 insertions(+), 4
Add protection on presence and order of the phy node sub node
by using the mandatory reg information.
Signed-off-by: Patrick Delaunay
---
drivers/phy/phy-stm32-usbphyc.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/phy-stm32-usbphyc.c
The vbus-supply is an optional property of sub-node connector node.
and no more in the usb phyc node (in first proposed binding).
This regulator for USB VBUS may be needed for host mode.
See the latest kernel binding for details in
Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml.
On Tue, 14 Sep 2021 05:27:51 +0200
Marek Vasut wrote:
> Add dfu_alt_info option which allows specifying multiple SPI flashes
> as an alt info. The syntax is as follows:
>
> altname sf bus:cs[:speed[:mode]]
>
> Example:
> dfu_alt_info=qspi0 sf 0:0;qspi1 sf 0:1
>
> Signed-off-by: Marek Vasut
>
Hi Alexandru,
On 9/9/21 4:55 PM, Alexandru Gagniuc wrote:
u-boot v2021.10-rc2 Introduced support for booting from FIP images
(not to be confused with FIT) for stm32mp. I am also working on a
different boot flow based on u-boot's falcon mode. The changes to
accommodate the FIP mode inadvertently
On Tue, Sep 14, 2021 at 06:31:41AM +, Mathew McBride wrote:
> In 92055e138f ("image: Drop if/elseif hash selection in calculate_hash()")
> the FIT image hash verification code was simplified to use the hash API.
>
> This broke verification of CRC32 hash FIT images (e.g NXP MC firmware)
> as
On Tue, 14 Sep 2021 05:26:51 +0200
Marek Vasut wrote:
> Not all SPI flashes and controllers can do continuous transfer longer
> than 16 MiB, so perform the DFU read in 16 MiB chunks.
>
> Signed-off-by: Marek Vasut
> Cc: Lukasz Majewski
> ---
> drivers/dfu/dfu_sf.c | 14 --
> 1
On Tue, Sep 14, 2021 at 10:37:43AM +0200, Simon Guinot wrote:
> Hi Stefan and Tom,
>
> I finally managed to find a Disk Mini v2 Ethernet card and I will be
> working on the DM conversion as soon as possible.
>
> Please, let me know what is my deadline to complete this job ?
Great. So, the
Continue to use the "ssbl" name for GPT partition of secondary boot
stage = U-Boot for basic boot with SPL to avoid to disturb existing user.
The "fip" partition name is only used for TFA_BOOT with FIP, it is a TF-A
BL2 requirement; it the default configuration for STMicroelectronics
boards.
This board has not been converted to CONFIG_DM by the deadline.
Remove it. As this is the last armada100 platform, remove that support
as well.
Cc: Prafulla Wadaskar
Signed-off-by: Tom Rini
---
Changes in v2:
This is the last armada100 platform, remove all of that related code now
too.
---
Add a driver for Macronix raw NAND controller.
This patch referred from linux mxic_nand.c. The difference from the
linux version is described here.
1. In order to adapt to the uboot nand framework, add function
binding (cmdfunc, read_byte, read_buf, write_buf).
2. Added parsing command
TCG EFI Protocol Specification defines the number_of_algorithms
field in spec ID event to be equal to the number of active
algorithms supported by the TPM device. In current implementation,
this field is populated with the count of all algorithms supported
by the TPM which leads to incorrect spec
Hello dear U-Boot members,
We recently tried to add support for a nand Flash (Micron MT29F4G08ABAEAWP
among others) from U-Boot 2020.04 on an iMX6DL processor.
We try to configure the ECC strength to 16 bits through the DTSI but when the
U-Boot is started, the command mtd list returns that the
On Sun, Aug 15, 2021 at 5:09 PM Lyle Franklin wrote:
>
> From: Lyle Franklin
> Date: Sun, 15 Aug 2021 07:17:14 -0400
> Subject: [PATCH] Allow colon in PXE bootfile URLs
>
> - U-boot's PXE flow supports prefixing your bootfile name with an
> IP address to fetch from a server other than the DHCP
On 14.09.21 15:09, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline.
Remove it. As this is the last mx35 platform, remove that support as
well.
Cc: Stefano Babic
Signed-off-by: Tom Rini
---
Acked-by: Stefano Babic
Best regards,
Stefano Babic
--
Hi,
in our environment we get error on efi_selftest if one of several SSD
partitions isn't properly initialized (due to some other error, but
that's a different topic). I tried to track down to where the partitions
get registered for test but got a bit lost so I request advice from you.
On 9/14/21 4:06 AM, Masami Hiramatsu wrote:
From: Kazuhiko Sakamoto
Since 'this->int_status' is cleared by efi_net_get_status(), if user
Is it correct to clear int_status unconditionally in efi_net_get_status()?
Shouldn't two consecutive calls to EFI_SIMPLE_NETWORK.GetStatus() return
the
On 9/14/21 4:56 PM, Michael Lawnick wrote:
Hi,
in our environment we get error on efi_selftest if one of several SSD
partitions isn't properly initialized (due to some other error, but
that's a different topic). I tried to track down to where the partitions
get registered for test but got a bit
On Sun, Sep 12, 2021 at 11:26:45AM -0500, Samuel Holland wrote:
> bootm_low is used as a base address is used to allocate space for the
> FDT blob, initrd, cmdline, etc. when booting Linux. Set the default
> value for RISC-V to the start of the first DRAM bank, so platforms can
> get their DRAM
Before e2e95e5e254 ("spi: Update speed/mode on change") most systems
silently defaulted to SF bus mode 0. Now the mode is always updated,
which causes breakage. It seems most SF which are used as boot media
operate in bus mode 0, so switch that as the default.
This should fix booting at least on
On Tue, Sep 14, 2021 at 08:28:24PM +0200, Marek Vasut wrote:
> Before e2e95e5e254 ("spi: Update speed/mode on change") most systems
> silently defaulted to SF bus mode 0. Now the mode is always updated,
> which causes breakage. It seems most SF which are used as boot media
> operate in bus mode
On 9/14/21 10:45 PM, Tom Rini wrote:
On Tue, Sep 14, 2021 at 10:10:22PM +0200, Marek Vasut wrote:
On 9/14/21 9:19 PM, Tom Rini wrote:
On Tue, Sep 14, 2021 at 08:28:24PM +0200, Marek Vasut wrote:
Before e2e95e5e254 ("spi: Update speed/mode on change") most systems
silently defaulted to SF bus
On Wed, Sep 01, 2021 at 04:05:08PM +0300, Oleksandr Suvorov wrote:
> There are trivial typos in the Kconfig file. Fixed them.
> Also, fixed grammar in the descriptions with typos.
>
> Fixes: d56b4b1974 ("configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and
> CMD_UBIFS")
> Fixes: 7264f2928b
On Wed, Aug 18, 2021 at 05:49:02PM -0500, Alexandru Gagniuc wrote:
> We are not guaranteed to have the padding_pkcs_15_verify symbol since
> commit 92c960bc1d ("lib: rsa: Remove #ifdefs from rsa.h"), and
> commit 61416fe9df ("Kconfig: FIT_SIGNATURE should not select RSA_VERIFY")
>
> The
On Sat, Aug 28, 2021 at 12:13:05PM +0200, Heinrich Schuchardt wrote:
> If keydir is not provided but name is we want to use name as key_id.
>
> But with the current coding name is only used on its own if it is NULL
> and keydir is provided which never occurs.
>
> Fixes: 824ee745fbca ("lib/rsa:
The hash algorithm selection was streamlined in commit 92055e138f28
("image: Drop if/elseif hash selection in calculate_hash()"). Said
commit kept the call to cpu_to_uimage() to convert the CRC to big
endian format.
This would have been correct when calling crc32_wd(). However, the
->hash_func_ws
Hey all,
Alright, I'm a day late, but, here's v2021.10-rc4. We've had a few
regressions pop up of late, unfortunately. I've pushed the fix for
(what I believe are) existing FIT images showing a problem where we
calculated the crc32 wrong. And we're just now starting to figure out
the proper
On Tue, Sep 14, 2021 at 10:10:22PM +0200, Marek Vasut wrote:
> On 9/14/21 9:19 PM, Tom Rini wrote:
> > On Tue, Sep 14, 2021 at 08:28:24PM +0200, Marek Vasut wrote:
> >
> > > Before e2e95e5e254 ("spi: Update speed/mode on change") most systems
> > > silently defaulted to SF bus mode 0. Now the
On Tue, Sep 14, 2021 at 11:30:01PM +0200, Marek Vasut wrote:
> On 9/14/21 10:45 PM, Tom Rini wrote:
> > On Tue, Sep 14, 2021 at 10:10:22PM +0200, Marek Vasut wrote:
> > > On 9/14/21 9:19 PM, Tom Rini wrote:
> > > > On Tue, Sep 14, 2021 at 08:28:24PM +0200, Marek Vasut wrote:
> > > >
> > > > >
On Tue, Sep 14, 2021 at 03:53:33PM -0500, Alexandru Gagniuc wrote:
> The hash algorithm selection was streamlined in commit 92055e138f28
> ("image: Drop if/elseif hash selection in calculate_hash()"). Said
> commit kept the call to cpu_to_uimage() to convert the CRC to big
> endian format.
>
>
On Wed, Sep 08, 2021 at 07:06:48PM +0800, Yuan Fang wrote:
> From: Yuan Fang
>
> fix typo in pinctrl Kconfig file to avoid git commit failure on
> some commit hooks check.
>
> Signed-off-by: Yuan Fang
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Thu, Sep 02, 2021 at 06:45:32PM +0200, Michael Walle wrote:
> Nowadays, both boards boot using the TF-A BL1/BL2 and SPL isn't used at
> all. The property is not needed, remove it.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vladimir Oltean
On Thu, Sep 02, 2021 at 06:45:37PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vladimir Oltean
Hello Guys,
I am in the process of configuring u-boot so that I can boot an encrypted
zImage. I was looking for a guide or documentation to make sure my
understanding of what I need to do is correct. Could anyone point me in the
correct direction?
Thank you
Cedrick
I have a custom board using imx6ul and Spansion S25HS512T Flash. On the current
version of u-boot (2021.10.rc3) and I am guessing even previous ones the
Spansion flash is not functioning
=> sf probe
drivers/core/uclass.c:325-uclass_find_device_by_seq() 0
On Wed, Sep 15, 2021 at 10:07:23AM +0800, Peng Fan (OSS) wrote:
> Just wonder anyone using kgdb in U-Boot?
> And sharing the same uart with normal output?
The KGDB code is also likely broken and could be removed in a follow-up
patch. It is however in Kconfig currently.
--
Tom
signature.asc
On Thu, Sep 02, 2021 at 06:45:35PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vladimir Oltean
On Thu, Sep 02, 2021 at 06:45:36PM +0200, Michael Walle wrote:
> While inserting it into the new location, keep it sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vladimir Oltean
On Thu, Sep 02, 2021 at 06:45:38PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vladimir Oltean
On Thu, Sep 02, 2021 at 06:45:40PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vladimir Oltean
On Thu, Sep 02, 2021 at 06:45:39PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vladimir Oltean
On Thu, Sep 02, 2021 at 06:45:45PM +0200, Michael Walle wrote:
> Update the labels of the nodes to match the kernel ones.
>
> Signed-off-by: Michael Walle
> Reviewed-by: Vladimir Oltean
> Tested-by: Vladimir Oltean
> ---
> - gpio0: gpio@230 {
> + gpio1: gpio@230
On Thu, Sep 02, 2021 at 06:45:54PM +0200, Michael Walle wrote:
> To make the synchronization of the u-boot device tree with the one from
> linux easier, move the I/O window to the one which is specified in the
> linux device tree. The actual value shouldn't matter as long as it
> mapped to the
On Thu, Sep 02, 2021 at 06:45:55PM +0200, Michael Walle wrote:
> Disable the PCIe controllers by default, just like in the linux device
> tree. But there is one catch, for linux they are enabled in-place by the
> bootloader. Obviously, this doesn't work for the bootloader. Thus we
> explicitly
On Thu, Sep 02, 2021 at 06:45:57PM +0200, Michael Walle wrote:
> Now that everything is prepared, copy the fsl-ls1028a.dtsi from the
> linux kernel v5.14.
>
> Notable changes:
> - second watchdog added
> - the number of chip selects of the SPI controller is now correct and
>reflects what
Recent raspberry pi firmware has modified the behavior of GET_CLOCK_RATE
to return zero (0) when there is no previous call to SET_CLOCK_RATE.
This affects callers of bcm2835_get_mmc_clock and can lead to degraded
MMC performance.
Now, return the result of GET_MAX_CLOCK_RATE if GET_CLOCK_RATE is
Newer firmware can manage the SDCDIV clock divisor register, allowing
the divisor to scale with the core as necessary.
Leverage this ability if the firmware supports it.
Adapted from the following raspberrypi Linux kernel commit:
bcm2835-sdhost: Firmware manages the clock divisor
In rpi-firmware 25e2b597ebfb2495eab4816a276758dcc6ea21f1,
the GET_CLOCK_RATE mailbox property was changed to return the last
value set by SET_CLOCK_RATE.
https://github.com/raspberrypi/firmware/issues/1619#issuecomment-917025502
Due to this change in firmware behavior, bcm2835_get_mmc_clock now
Alpha sort the Amlogic dtb list (same as the kernel).
Signed-off-by: Christian Hewitt
---
arch/arm/dts/Makefile | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f0160d2dc0..461448c579 100644
---
This series alpha sorts the Amlogic Makefile, then adds
support for the Radxa Zero SBC using the device-tree
queued in the Amlogic maintainer tree for Linux 5.16.y
Patches are based on custodians/u-boot-amlogic-next
Christian Hewitt (4):
ARM: dts: sort Amlogic Makefile section
ARM: dts: add
On Sun, Sep 12, 2021 at 11:15:08AM +0800, Bin Meng wrote:
> The following warning is seen in cache-sifive-ccache.c in a 32-bit build:
>
> warning: cast to pointer from integer of different size
> [-Wint-to-pointer-cast]
>
> Fix by casting it with uintptr_t.
>
> Signed-off-by: Bin Meng
> ---
>
On Thu, Sep 02, 2021 at 06:45:41PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vladimir Oltean
On Thu, Sep 02, 2021 at 06:45:44PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> While at it fix the indentation.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by:
On Thu, Sep 02, 2021 at 06:45:53PM +0200, Michael Walle wrote:
> This property is unused in the layerscape PCIe controller driver and not
> present in the linux device tree. Remove it to be similarly.
>
> Signed-off-by: Michael Walle
> ---
Looks pretty much unused, indeed.
Reviewed-by:
On Thu, Sep 02, 2021 at 06:45:56PM +0200, Michael Walle wrote:
> The linux device tree hasn't set this property. To be similarly we remove
s/similarly/similar/
> it from the u-boot device tree, too. The second controller of the
> LS1028A has indeed no card detect pin.
Because it is an eMMC
Hi Heinrich,
This is obscure in the specification (I can not see any detailed
description about EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT).
If EFI_SIMPLE_NETWORK.GetStatus() returns only the hardware interrupt
state, it is an useless interface, because it doesn't sync to the
status of the packet
Add documentation bits for the Radxa Zero
Signed-off-by: Christian Hewitt
---
doc/board/amlogic/index.rst | 3 +-
doc/board/amlogic/radxa-zero.rst | 74
2 files changed, 76 insertions(+), 1 deletion(-)
create mode 100644 doc/board/amlogic/radxa-zero.rst
Import the initial dts queued for Linux 5.16.y
Signed-off-by: Christian Hewitt
---
arch/arm/dts/Makefile | 1 +
.../arm/dts/meson-g12a-radxa-zero-u-boot.dtsi | 7 +
arch/arm/dts/meson-g12a-radxa-zero.dts| 405 ++
3 files changed, 413
Add a defconfig for the Radxa Zero SBC, using an Amlogic S905Y2 chip.
Signed-off-by: Christian Hewitt
---
configs/radxa-zero_defconfig | 70
1 file changed, 70 insertions(+)
create mode 100644 configs/radxa-zero_defconfig
diff --git
On 2021/9/13 3:39, Oleksandr Suvorov wrote:
Move setting the default boot command to the
apalis/colibri_imx6_defconfig. It allows replacing the command
without code modification.
Signed-off-by: Oleksandr Suvorov
---
configs/apalis_imx6_defconfig | 1 +
configs/colibri_imx6_defconfig |
On 2021/9/11 4:19, Adam Ford wrote:
Somewhere along the line, the board stopped being able to boot.
Rather than just fixing the issue, let's fix the issue and migrate
to binman to eliminate a warning when using custom imx tools for
generating the binary.
Signed-off-by: Adam Ford
diff --git
On 2021/9/8 21:08, Heiko Thiery wrote:
Hi Peng,
I faced an issue with the I2C bus speed in SPL for the imx8mq. I
figured out that the bus frequency is set to about 1MHz. While digging
into that I found that the clk ID for the I2C is not returned for the
imx8mq correctly.
Can you confirm
On 2021/8/30 19:11, Oleksandr Suvorov wrote:
On Sun, Aug 29, 2021 at 10:55 PM Marek Vasut wrote:
On 8/29/21 9:39 PM, Oleksandr Suvorov wrote:
The BSP platform LmP supports the board NXP iMX8QM MEK. The
kernel size in LmP exceeds 32Mb. Increase the maximum size
of an uncompressed kernel to
The flash->mtd.name used to be nor%d before, now it is the type of the
SPI NOR like e.g. mt25ql02g. It is possible to find plenty of examples
of the former in U-Boot configs by searching for MTDIDS.*nor.*spi, while
the later is ambiguous if there are multiple flashes of the same type in
the system
On Thu, Sep 02, 2021 at 06:45:33PM +0200, Michael Walle wrote:
> To keep the device tree similar to the linux kernel one, we need to move
> all CCSR related devices into the /soc node. To keep the patches easy to
> review, we initially add an empty /soc node and populate it piece by
> piece.
>
>
On Thu, Sep 02, 2021 at 06:45:34PM +0200, Michael Walle wrote:
> Populate the /soc node with the first device node.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vladimir Oltean
On Thu, Sep 02, 2021 at 06:45:42PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> While at it fix the indentation.
>
> Signed-off-by: Michael Walle
> ---
>
On Thu, Sep 02, 2021 at 06:45:43PM +0200, Michael Walle wrote:
> While inserting it into the new location, keep it sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vladimir Oltean
On Thu, Sep 02, 2021 at 06:45:48PM +0200, Michael Walle wrote:
> The official devicetree bindings specifies spi-num-chipselects as the
> name. Use it.
>
> Signed-off-by: Michael Walle
> ---
Reviewed-by: Vladimir Oltean
On Thu, Sep 02, 2021 at 06:45:50PM +0200, Michael Walle wrote:
> The driver will look for a named resource "ecc-addr", but this isn't the
> official binding. In fact, the official device tree binding
> documentation doesn't mention any resource names at all. But it is safe
> to assume that it's
On Thu, Sep 02, 2021 at 06:45:58PM +0200, Michael Walle wrote:
> Copy the board device tree files from linux v5.14. On top of the v5.14
> dtbs the changes of these two patches are included here which are needed
> for u-boot:
>
>
Just wonder anyone using kgdb in U-Boot?
And sharing the same uart with normal output?
Thanks,
Peng
On 2021/9/14 5:24, Tom Rini wrote:
We have a few CONFIG options for KGDB that are not referenced, remove
them.
Signed-off-by: Tom Rini
---
README | 5 -
On 2021/9/12 5:14, Marek Vasut wrote:
Add option to extend the hardware partition to the maximum size by
using the '-' dash sign instead of $cnt parameter. This is useful
in case we want to switch the entire eMMC user area into pSLC mode,
especially in case the device may be populated with
Please resend with plain text.
On 2021/9/8 13:26, Arendt, Steffen wrote:
Enable clocks for SPI and QOS (Ethernet) for the imx8mp SoC
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index c77500bcce..1ab5587e4e 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++
On 2021/9/9 20:59, Heiko Thiery wrote:
Return the root clock values for MXC_CSPI_CLK, MXC_I2C_CLK,
MXC_UART_CLK and MXC_QSPI_CLK.
At least for the I2C clock the missing support leads to a wrong
configured I2C frequency. The expected value is 100kHz but the resulting
value is about 1MHz.
On 2021/8/17 14:32, Ye Li wrote:
Since SPL has initialized clocks for bus and core. We don't need to
set the default clocks for clock controller node.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mp-u-boot.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git
On 14/09/21 05:22AM, Marek Vasut wrote:
> Wait for the read/write transfer finish bit get actually cleared,
> this does not happen immediately on at least SoCFPGA Gen5.
>
> Signed-off-by: Marek Vasut
> Cc: Jagan Teki
> Cc: Vignesh R
> Cc: Pratyush Yadav
> ---
> drivers/spi/cadence_qspi_apb.c
On 9/14/21 7:46 PM, Pratyush Yadav wrote:
On 14/09/21 05:21AM, Marek Vasut wrote:
Both dummy.nbytes and dummy.buswidth may be zero. By not checking
the later, it is possible to trigger division by zero and a crash.
This does happen with tiny SPI NOR framework in SPL. Fix this by
adding the
On 9/14/21 7:42 PM, Pratyush Yadav wrote:
On 14/09/21 05:22AM, Marek Vasut wrote:
Wait for the read/write transfer finish bit get actually cleared,
this does not happen immediately on at least SoCFPGA Gen5.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Vignesh R
Cc: Pratyush Yadav
---
On 9/14/21 9:19 PM, Tom Rini wrote:
On Tue, Sep 14, 2021 at 08:28:24PM +0200, Marek Vasut wrote:
Before e2e95e5e254 ("spi: Update speed/mode on change") most systems
silently defaulted to SF bus mode 0. Now the mode is always updated,
which causes breakage. It seems most SF which are used as
On 14/09/21 05:21AM, Marek Vasut wrote:
> Both dummy.nbytes and dummy.buswidth may be zero. By not checking
> the later, it is possible to trigger division by zero and a crash.
> This does happen with tiny SPI NOR framework in SPL. Fix this by
> adding the check and returning zero dummy bytes in
On Sun, Sep 12, 2021 at 11:15:10AM +0800, Bin Meng wrote:
> dev_read_addr() returns a value of type fdt_addr_t which is a 64-bit
> address and plat->base is a pointer. In a 32-bit build, this causes the
> following warning seen when building sifive-gpio.c:
>
> warning: cast to pointer from
From: Takahiro Kuwano
The current S25FS512S support has following issues that need to be fixed.
- Non-uniform sectors by factory default. The setting needs to be
checked and assign erase hook as needed.
- Page size is wrongly advertised in SFDP.
- READ_1_1_2 (3Bh/3Ch), READ_1_1_4
On Sun, Sep 12, 2021 at 11:15:11AM +0800, Bin Meng wrote:
> The following warning is seen in ocores_i2c.c in a 32-bit build:
>
> warning: cast to pointer from integer of different size
> [-Wint-to-pointer-cast]
>
> Change to use dev_read_addr_ptr().
>
> Signed-off-by: Bin Meng
> ---
>
>
On Sun, Sep 12, 2021 at 11:15:09AM +0800, Bin Meng wrote:
> dev_read_addr() returns a value of type fdt_addr_t which is a 64-bit
> address and pd->va is a pointer. In a 32-bit build, this causes the
> following warning seen when building sifive-prci.c:
>
> warning: cast to pointer from integer
Hi Marek,
On 15.09.21 01:06, Marek Vasut wrote:
> The flash->mtd.name used to be nor%d before, now it is the type of the
> SPI NOR like e.g. mt25ql02g. It is possible to find plenty of examples
> of the former in U-Boot configs by searching for MTDIDS.*nor.*spi, while
> the later is ambiguous if
TCG PC Client spec requires to measure the SMBIOS
table that contain static configuration information
(e.g. Platform Manufacturer Enterprise Number assigned by IANA,
platform model number, Vendor and Device IDs for each SMBIOS table).
The device and environment dependent information such as
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