Re: [U-Boot] [PATCH 0/5] ARM: sheevaplug: refresh for 201410
Hi Prafulla,
Is there any chance for theses patches to be reviewed in time for next release ?
Can you get it reviewed by anyone else ?
Enjoy,
On 15/09/2014 06:36, drEagle wrote:
Hi Preafulla,
Any news about these patches ?
Regards,
On 09/09/2014 08:59, Prafulla Wadaskar wrote:
Hi Everybody,
Sorry for being inactive on the thread...
I will pull these patches and provide a pull request to albert soon...
Regards...
Prafulla . . .
-Original Message-
From: Nobuhiro Iwamatsu [mailto:iwama...@nigauri.org]
Sent: 09 September 2014 12:08
To: Albert ARIBAUD
Cc: U-Boot; Prafulla Wadaskar; Pantelis Antoniou;
Gerald Kerma; Tom Rini
Subject: Re: [PATCH 0/5] ARM: sheevaplug: refresh for
201410
Hi, Albert.
These patches are not taken for a long time.
If possible and Prafulla is OK, can you apply to u-
boot-arm directly?
Best regards,
Nobuhiro
2014-09-08 1:01 GMT+09:00 Gerald Kerma
drea...@doukki.net:
This serie of patches add some needed features to
sheevaplug
Gerald Kerma (5):
ARM: sheevaplug: change env location
ARM: sheevaplug: add MVSATA driver
ARM: sheevaplug: add MTD defaults
ARM: sheevaplug: redefine MTDPARTS
ARM: sheevaplug: add HUSH parser
include/configs/sheevaplug.h | 46
+++-
1 file changed, 41 insertions(+), 5 deletions(-)
--
1.9.1
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
signature.asc
Description: OpenPGP digital signature
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[U-Boot] [PATCH v2 2/3] README.clang: update FreeBSD instructions
The mentioned binutils port got removed while the patch was pending. As Ian pointed out there is another port providing the binutils for arm now. Update the instructions accordingly. Cc: i...@freebsd.org Cc: Tom Rini tr...@ti.com Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl --- doc/README.clang | 8 1 file changed, 4 insertions(+), 4 deletions(-) --- changes since v1: update the name of the scipt as well. diff --git a/doc/README.clang b/doc/README.clang index 9ad689f..52495d3 100644 --- a/doc/README.clang +++ b/doc/README.clang @@ -34,21 +34,21 @@ make HOSTCC=clang CC=clang -target $TRIPLET -mllvm -arm-use-movt=0 -no-integrat FreeBSD 11 (Current): Since llvm 3.4 is currently in the base system, the integrated as is -incapable of building U-Boot. Therefore gas from devel/arm-eabi-binutils +incapable of building U-Boot. Therefore gas from devel/arm-gnueabi-binutils is used instead. It needs a symlinks to be picked up correctly though: -ln -s /usr/local/bin/arm-eabi-as /usr/bin/arm-freebsd-eabi-as +ln -s /usr/local/bin/arm-gnueabi-freebsd-as /usr/bin/arm-freebsd-eabi-as # The following commands compile U-Boot using the clang xdev toolchain. # NOTE: CROSS_COMPILE and target differ on purpose! -export CROSS_COMPILE=arm-eabi- +export CROSS_COMPILE=arm-gnueabi-freebsd- gmake CC=clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0 rpi_b_defconfig gmake CC=clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd -no-integrated-as -mllvm -arm-use-movt=0 -j8 Given that u-boot will default to gcc, above commands can be simplified with a simple wrapper script, listed below. -/usr/local/bin/arm-eabi-gcc +/usr/local/bin/arm-gnueabi-freebsd-gcc --- #!/bin/sh -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] cm_fx6: Remove CONFIG_NETMASK
On 09/21/14 02:05, Fabio Estevam wrote: From: Fabio Estevam fabio.este...@freescale.com We should not hardcode CONFIG_NETMASK in the config file. That is correct no doubts. Signed-off-by: Fabio Estevam fabio.este...@freescale.com Cc'd Nikita, Acked-by: Igor Grinberg grinb...@compulab.co.il --- include/configs/cm_fx6.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 10d02b4..7cf241e 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -222,7 +222,6 @@ #define CONFIG_MII #define CONFIG_ETHPRIME FEC0 #define CONFIG_ARP_TIMEOUT 200UL -#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_NET_RETRY_COUNT 5 /* USB */ -- Regards, Igor. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 01/51] net: Remove unused CONFIG_DW_SEARCH_PHY from configs
From: Pavel Machek pa...@denx.de Remove this symbol from configs, since it's unused. Signed-off-by: Pavel Machek pa...@denx.de Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de Cc: Joe Hershberger joe.hershber...@gmail.com --- include/configs/axs101.h | 1 - include/configs/socfpga_cyclone5.h | 1 - 2 files changed, 2 deletions(-) V2: Drop this option globally from all configs diff --git a/include/configs/axs101.h b/include/configs/axs101.h index c22d6d0..1bf8390 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -125,7 +125,6 @@ */ #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_AUTONEG -#define CONFIG_DW_SEARCH_PHY #define CONFIG_NET_MULTI /* diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 5d145cd..39e9368 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -225,7 +225,6 @@ /* designware */ #define CONFIG_NET_MULTI #define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_DW_SEARCH_PHY #define CONFIG_MII #define CONFIG_PHY_GIGE #define CONFIG_DW_AUTONEG -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/51] net: dwc: Fix cache alignment issues
Fix remaining cache alignment issues in the DWC Ethernet driver. Please note that the cache handling in the driver is making the code hideous and thus the next patch cleans that up. In order to make this change reviewable though, the cleanup is split from it. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de Cc: Joe Hershberger joe.hershber...@gmail.com --- drivers/net/designware.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 7186e3b..aaf146d 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -303,7 +303,8 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) /* Flush data to be sent */ flush_dcache_range((unsigned long)desc_p-dmamac_addr, - (unsigned long)desc_p-dmamac_addr + length); + (unsigned long)desc_p-dmamac_addr + + roundup(length, ARCH_DMA_MINALIGN)); #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p-txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; @@ -372,7 +373,8 @@ static int dw_eth_recv(struct eth_device *dev) /* Flush only status field - others weren't changed */ flush_dcache_range((unsigned long)desc_p-txrx_status, (unsigned long)desc_p-txrx_status + - sizeof(desc_p-txrx_status)); + roundup(sizeof(desc_p-txrx_status), + ARCH_DMA_MINALIGN)); /* Test the wrap-around condition. */ if (++desc_num = CONFIG_RX_DESCR_NUM) -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/51] arm: socfpga: Complete the list of base addresses
From: Pavel Machek pa...@denx.de Add base addresses for all subsystems as documented in the Cyclone V HPS documentation. Signed-off-by: Pavel Machek pa...@denx.de Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de --- .../include/asm/arch-socfpga/socfpga_base_addrs.h | 40 ++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 2d3152d..cb062ac 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -7,16 +7,56 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 #define SOCFPGA_L3REGS_ADDRESS 0xff80 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb9 #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_SDR_ADDRESS 0xffc2 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 #define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 #define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 #define SOCFPGA_EMAC0_ADDRESS 0xff70 #define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_STM_ADDRESS 0xfc00 +#define SOCFPGA_DAP_ADDRESS 0xff00 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff20 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff40 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff50 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff60 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff90 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa0 +#define SOCFPGA_USB0_ADDRESS 0xffb0 +#define SOCFPGA_USB1_ADDRESS 0xffb4 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb8 +#define SOCFPGA_CAN0_ADDRESS 0xffc0 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe0 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff0 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_ROM_ADDRESS 0xfffd +#define SOCFPGA_OCRAM_ADDRESS 0x #endif /* _SOCFPGA_BASE_ADDRS_H_ */ -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 00/51] arm: socfpga: Usability fixes
This entire series is the second stab at making SoCFPGA usable with mainline U-Boot again. There are much fewer bits missing than in the last series, more cleanup happened and bugs were fixed. This allows me to use mainline U-Boot on my SoCFPGA systems. The big missing part is the SPL generation, which still needs a lot of additional work. We also miss the Cadence QSPI controller driver. This set contains patches for a few subsystems, which are utilized by the SoCFPGA, but the most part is the SoCFPGA chip support. This series now contains cleanup for the mayhem in drivers/fpga/altera.c code, which was terrible, but is now much better. Charles Manning (1): tools: socfpga: Add socfpga preloader signing to mkimage Chin Liang See (2): arm: socfpga: Enable DWMMC for SOCFPGA arm: socfpga: Enable SDMMC boot for SOCFPGA U-Boot Marek Vasut (32): net: dwc: Fix cache alignment issues net: dwc: Make the cache handling less cryptic mmc: dw_mmc: Fix cache alignment issue arm: socfpga: Clean up base address file arm: socfpga: sysmgr: Clean up system manager arm: socfpga: clock: Implant order into bit definitions arm: socfpga: clock: Drop nonsense inlining from clock manager code arm: socfpga: clock: Add missing stubs into board file arm: socfpga: clock: Trim down code duplication arm: socfpga: clock: Clean up bit definitions arm: socfpga: clock: Sync with reference code arm: socfpga: timer: Pull the timer reload value from config file arm: socfpga: reset: Add EMAC reset functions arm: socfpga: board: Align checkboard() output fpga: altera: Clean up the printing and debug fpga: altera: Clean up altera_validate function fpga: altera: More indentation trimdown fpga: altera: Move altera_validate to the top fpga: altera: Make altera_validate return normal values fpga: altera: Clean up enums in altera.h fpga: altera: Turn the switches into table lookup arm: socfpga: reset: Add function to reset FPGA bridges arm: socfpga: sysmgr: Add FPGA bits into system manager arm: cache: Add support for write-allocate D-Cache arm: socfpga: cache: Define cacheline size arm: socfpga: cache: Enable D-Cache arm: socfpga: cache: Enable PL310 L2 cache arm: socfpga: scu: Add SCU register file arm: socfpga: nic301: Add NIC-301 GPV register file arm: socfpga: pl310: Map SDRAM to 0x0 arm: socfpga: Move cache_enable to CPU code arm: socfpga: Use CMD_FS_GENERIC Pavel Machek (16): net: Remove unused CONFIG_DW_SEARCH_PHY from configs net: phy: Cleanup drivers/net/phy/micrel.c mmc: dw_mmc: cleanups arm: socfpga: Complete the list of base addresses arm: socfpga: Add watchdog disable for socfpga arm: socfpga: clock: Add code to read clock configuration arm: socfpga: mmc: Pick the clock from clock manager arm: socfpga: misc: Add proper ethernet initialization arm: socfpga: misc: Add SD controller init arm: socfpga: misc: Align print_cpuinfo() output arm: socfpga: board: Correctly set ATAG position arm: socfpga: fpga: Add SoCFPGA FPGA programming interface arm: socfpga: nic301: Add NIC-301 configuration code arm: socfpga: Add command to control HPS-FPGA bridges arm: socfpga: Clean up SoCFPGA configuration arm: socfpga: Split SoCFPGA configuration arch/arm/cpu/armv7/socfpga/Makefile| 3 +- arch/arm/cpu/armv7/socfpga/clock_manager.c | 340 - arch/arm/cpu/armv7/socfpga/fpga_manager.c | 78 + arch/arm/cpu/armv7/socfpga/misc.c | 235 +- arch/arm/cpu/armv7/socfpga/reset_manager.c | 67 arch/arm/cpu/armv7/socfpga/spl.c | 174 ++- arch/arm/cpu/armv7/socfpga/system_manager.c| 57 +++- arch/arm/cpu/armv7/socfpga/timer.c | 2 + arch/arm/include/asm/arch-socfpga/clock_manager.h | 306 --- arch/arm/include/asm/arch-socfpga/fpga_manager.h | 77 + arch/arm/include/asm/arch-socfpga/nic301.h | 195 arch/arm/include/asm/arch-socfpga/reset_manager.h | 9 + arch/arm/include/asm/arch-socfpga/scu.h| 23 ++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 62 +++- arch/arm/include/asm/arch-socfpga/system_manager.h | 111 +-- arch/arm/include/asm/system.h | 1 + arch/arm/lib/cache-cp15.c | 2 + board/altera/socfpga/pll_config.h | 3 + board/altera/socfpga/socfpga_cyclone5.c| 6 +- common/image.c | 1 + drivers/fpga/Makefile | 1 + drivers/fpga/altera.c | 308 --- drivers/fpga/socfpga.c | 301 ++ drivers/mmc/dw_mmc.c | 34 ++- drivers/mmc/socfpga_dw_mmc.c | 15 +- drivers/net/designware.c | 46 +-- drivers/net/phy/micrel.c
[U-Boot] [PATCH 07/51] tools: socfpga: Add socfpga preloader signing to mkimage
From: Charles Manning cdhmann...@gmail.com
Like many platforms, the Altera socfpga platform requires that the
preloader be signed in a certain way or the built-in boot ROM will
not boot the code.
This change automatically creates an appropriately signed preloader
from an SPL image.
The signed image includes a CRC which must, of course, be generated
with a CRC generator that the SoCFPGA boot ROM agrees with otherwise
the boot ROM will reject the image.
Unfortunately the CRC used in this boot ROM is not the same as the
Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a
CRC but is more correctly described as a checksum.
Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c.
Signed-off-by: Charles Manning cdhmann...@gmail.com
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
common/image.c | 1 +
include/image.h | 1 +
tools/Makefile | 1 +
tools/imagetool.c| 2 +
tools/imagetool.h| 1 +
tools/socfpgaimage.c | 255 +++
6 files changed, 261 insertions(+)
create mode 100644 tools/socfpgaimage.c
diff --git a/common/image.c b/common/image.c
index 38b56e3..085771c 100644
--- a/common/image.c
+++ b/common/image.c
@@ -138,6 +138,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_PBLIMAGE, pblimage, Freescale PBL Boot Image,},
{ IH_TYPE_RAMDISK,ramdisk,RAMDisk Image, },
{ IH_TYPE_SCRIPT, script, Script, },
+ { IH_TYPE_SOCFPGAIMAGE, socfpgaimage, Altera SOCFPGA
preloader,},
{ IH_TYPE_STANDALONE, standalone, Standalone Program, },
{ IH_TYPE_UBLIMAGE, ublimage, Davinci UBL image,},
{ IH_TYPE_MXSIMAGE, mxsimage, Freescale MXS Boot Image,},
diff --git a/include/image.h b/include/image.h
index 3401056..4347532 100644
--- a/include/image.h
+++ b/include/image.h
@@ -232,6 +232,7 @@ struct lmb;
#define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */
#define IH_TYPE_GPIMAGE17 /* TI Keystone GPHeader Image
*/
#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */
+#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */
/*
* Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 90e966d..2b05b20 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -87,6 +87,7 @@ dumpimage-mkimage-objs := aisimage.o \
os_support.o \
pblimage.o \
pbl_crc32.o \
+ socfpgaimage.o \
lib/sha1.o \
lib/sha256.o \
ublimage.o \
diff --git a/tools/imagetool.c b/tools/imagetool.c
index 32d6278..98717bd 100644
--- a/tools/imagetool.c
+++ b/tools/imagetool.c
@@ -47,6 +47,8 @@ void register_image_tool(imagetool_register_t image_register)
init_ubl_image_type();
/* Init Davinci AIS support */
init_ais_image_type();
+ /* Init Altera SOCFPGA support */
+ init_socfpga_image_type();
/* Init TI Keystone boot image generation/list support */
init_gpimage_type();
}
diff --git a/tools/imagetool.h b/tools/imagetool.h
index c8af0e8..8bce059 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -168,6 +168,7 @@ void init_mxs_image_type(void);
void init_fit_image_type(void);
void init_ubl_image_type(void);
void init_omap_image_type(void);
+void init_socfpga_image_type(void);
void init_gpimage_type(void);
void pbl_load_uboot(int fd, struct image_tool_params *mparams);
diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c
new file mode 100644
index 000..32fa09f
--- /dev/null
+++ b/tools/socfpgaimage.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2014 Charles Manning cdhmann...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Reference doc http://www.altera.com.cn/literature/hb/cyclone-v/cv_5400A.pdf
+ * Note this doc is not entirely accurate. Of particular interest to us is the
+ * header length field being in U32s and not bytes.
+ *
+ * Header is a structure of the following format.
+ * this is positioned at 0x40.
+ *
+ * Endian is LSB.
+ *
+ * Offset Length Usage
+ * ---
+ * 0x404 Validation word 0x31305341
+ * 0x441 Version (whatever, zero is fine)
+ * 0x451 Flags (unused, zero is fine)
+ * 0x462 Length (in units of u32, including the end checksum).
+ * 0x482 Zero
+ * 0x4A2 Checksum over the header. NB Not CRC32
+ *
+ * At the end of the code we have a 32-bit CRC checksum over whole binary
+ * excluding the CRC.
+ *
+ * Note that the CRC used here is **not** the
[U-Boot] [PATCH 02/51] net: phy: Cleanup drivers/net/phy/micrel.c
From: Pavel Machek pa...@denx.de
Old saying says that more than three exclamation marks in a row are
sign of mental disease. Cleanup micrel.c.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/phy/micrel.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 5d7e3be..507b9a3 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -25,8 +25,7 @@ static struct phy_driver KSZ804_driver = {
#ifndef CONFIG_PHY_MICREL_KSZ9021
/*
* I can't believe Micrel used the exact same part number
- * for the KSZ9021
- * Shame Micrel, Shame!
+ * for the KSZ9021. Shame Micrel, Shame!
*/
static struct phy_driver KS8721_driver = {
.name = Micrel KS8721BL,
@@ -40,7 +39,7 @@ static struct phy_driver KS8721_driver = {
#endif
-/**
+/*
* KSZ9021 - KSZ9031 common
*/
@@ -69,8 +68,8 @@ static int ksz90xx_startup(struct phy_device *phydev)
phydev-speed = SPEED_10;
return 0;
}
-#ifdef CONFIG_PHY_MICREL_KSZ9021
+#ifdef CONFIG_PHY_MICREL_KSZ9021
/*
* KSZ9021
*/
--
2.0.0
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[U-Boot] [PATCH 05/51] mmc: dw_mmc: cleanups
From: Pavel Machek pa...@denx.de
The dw_mmc driver was responding to errors with debug(). Change that
to prinf()/puts() respectively so that any errors are immediately
obvious. Also adjust english in comments.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Pantelis Antoniou pa...@antoniou-consulting.com
---
drivers/mmc/dw_mmc.c | 34 ++
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 0df30bc..785eed5 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -119,7 +119,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
*cmd,
while (dwmci_readl(host, DWMCI_STATUS) DWMCI_BUSY) {
if (get_timer(start) timeout) {
- printf(Timeout on data busy\n);
+ printf(%s: Timeout on data busy\n, __func__);
return TIMEOUT;
}
}
@@ -177,14 +177,24 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
*cmd,
}
}
- if (i == retry)
+ if (i == retry) {
+ printf(%s: Timeout.\n, __func__);
return TIMEOUT;
+ }
if (mask DWMCI_INTMSK_RTO) {
- debug(Response Timeout..\n);
+ /*
+* Timeout here is not necessarily fatal. (e)MMC cards
+* will splat here when they receive CMD55 as they do
+* not support this command and that is exactly the way
+* to tell them apart from SD cards. Thus, this output
+* below shall be debug(). eMMC cards also do not favor
+* CMD8, please keep that in mind.
+*/
+ debug(%s: Response Timeout.\n, __func__);
return TIMEOUT;
} else if (mask DWMCI_INTMSK_RE) {
- debug(Response Error..\n);
+ printf(%s: Response Error.\n, __func__);
return -1;
}
@@ -204,7 +214,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
*cmd,
do {
mask = dwmci_readl(host, DWMCI_RINTSTS);
if (mask (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
- debug(DATA ERROR!\n);
+ printf(%s: DATA ERROR!\n, __func__);
return -1;
}
} while (!(mask DWMCI_INTMSK_DTO));
@@ -232,16 +242,16 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
if ((freq == host-clock) || (freq == 0))
return 0;
/*
-* If host-get_mmc_clk didn't define,
+* If host-get_mmc_clk isn't defined,
* then assume that host-bus_hz is source clock value.
-* host-bus_hz should be set from user.
+* host-bus_hz should be set by user.
*/
if (host-get_mmc_clk)
sclk = host-get_mmc_clk(host);
else if (host-bus_hz)
sclk = host-bus_hz;
else {
- printf(Didn't get source clock value..\n);
+ printf(%s: Didn't get source clock value.\n, __func__);
return -EINVAL;
}
@@ -260,7 +270,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
do {
status = dwmci_readl(host, DWMCI_CMD);
if (timeout-- 0) {
- printf(TIMEOUT error!!\n);
+ printf(%s: Timeout!\n, __func__);
return -ETIMEDOUT;
}
} while (status DWMCI_CMD_START);
@@ -275,7 +285,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
do {
status = dwmci_readl(host, DWMCI_CMD);
if (timeout-- 0) {
- printf(TIMEOUT error!!\n);
+ printf(%s: Timeout!\n, __func__);
return -ETIMEDOUT;
}
} while (status DWMCI_CMD_START);
@@ -290,7 +300,7 @@ static void dwmci_set_ios(struct mmc *mmc)
struct dwmci_host *host = (struct dwmci_host *)mmc-priv;
u32 ctype, regs;
- debug(Buswidth = %d, clock: %d\n,mmc-bus_width, mmc-clock);
+ debug(Buswidth = %d, clock: %d\n, mmc-bus_width, mmc-clock);
dwmci_setup_bus(host, mmc-clock);
switch (mmc-bus_width) {
@@ -329,7 +339,7 @@ static int dwmci_init(struct mmc *mmc)
dwmci_writel(host, DWMCI_PWREN, 1);
if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
- debug(%s[%d] Fail-reset!!\n,__func__,__LINE__);
+ printf(%s[%d] Fail-reset!!\n, __func__, __LINE__);
[U-Boot] [PATCH 04/51] net: dwc: Make the cache handling less cryptic
Add a few new variables to make the cache handling less cryptic.
Add a variable for DMA and DATA descriptor start and end, so the
correctness of the code is easier to inspect.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Joe Hershberger joe.hershber...@gmail.com
Acked-by: Pavel Machek pa...@denx.de
---
drivers/net/designware.c | 48 +++-
1 file changed, 23 insertions(+), 25 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index aaf146d..9ded895 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -279,19 +279,21 @@ static int dw_eth_send(struct eth_device *dev, void
*packet, int length)
struct eth_dma_regs *dma_p = priv-dma_regs_p;
u32 desc_num = priv-tx_currdescnum;
struct dmamacdescr *desc_p = priv-tx_mac_descrtable[desc_num];
-
+ uint32_t desc_start = (uint32_t)desc_p;
+ uint32_t desc_end = desc_start +
+ roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+ uint32_t data_start = (uint32_t)desc_p-dmamac_addr;
+ uint32_t data_end = data_start +
+ roundup(length, ARCH_DMA_MINALIGN);
/*
* Strictly we only need to invalidate the txrx_status field
* for the following check, but on some platforms we cannot
-* invalidate only 4 bytes, so roundup to
-* ARCH_DMA_MINALIGN. This is safe because the individual
-* descriptors in the array are each aligned to
-* ARCH_DMA_MINALIGN.
+* invalidate only 4 bytes, so we flush the entire descriptor,
+* which is 16 bytes in total. This is safe because the
+* individual descriptors in the array are each aligned to
+* ARCH_DMA_MINALIGN and padded appropriately.
*/
- invalidate_dcache_range(
- (unsigned long)desc_p,
- (unsigned long)desc_p +
- roundup(sizeof(desc_p-txrx_status), ARCH_DMA_MINALIGN));
+ invalidate_dcache_range(desc_start, desc_end);
/* Check if the descriptor is owned by CPU */
if (desc_p-txrx_status DESC_TXSTS_OWNBYDMA) {
@@ -299,12 +301,10 @@ static int dw_eth_send(struct eth_device *dev, void
*packet, int length)
return -1;
}
- memcpy((void *)desc_p-dmamac_addr, packet, length);
+ memcpy(desc_p-dmamac_addr, packet, length);
/* Flush data to be sent */
- flush_dcache_range((unsigned long)desc_p-dmamac_addr,
- (unsigned long)desc_p-dmamac_addr +
- roundup(length, ARCH_DMA_MINALIGN));
+ flush_dcache_range(data_start, data_end);
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p-txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
@@ -322,8 +322,7 @@ static int dw_eth_send(struct eth_device *dev, void
*packet, int length)
#endif
/* Flush modified buffer descriptor */
- flush_dcache_range((unsigned long)desc_p,
- (unsigned long)desc_p + sizeof(struct dmamacdescr));
+ flush_dcache_range(desc_start, desc_end);
/* Test the wrap-around condition. */
if (++desc_num = CONFIG_TX_DESCR_NUM)
@@ -343,11 +342,14 @@ static int dw_eth_recv(struct eth_device *dev)
u32 status, desc_num = priv-rx_currdescnum;
struct dmamacdescr *desc_p = priv-rx_mac_descrtable[desc_num];
int length = 0;
+ uint32_t desc_start = (uint32_t)desc_p;
+ uint32_t desc_end = desc_start +
+ roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+ uint32_t data_start = (uint32_t)desc_p-dmamac_addr;
+ uint32_t data_end;
/* Invalidate entire buffer descriptor */
- invalidate_dcache_range((unsigned long)desc_p,
- (unsigned long)desc_p +
- sizeof(struct dmamacdescr));
+ invalidate_dcache_range(desc_start, desc_end);
status = desc_p-txrx_status;
@@ -358,9 +360,8 @@ static int dw_eth_recv(struct eth_device *dev)
DESC_RXSTS_FRMLENSHFT;
/* Invalidate received data */
- invalidate_dcache_range((unsigned long)desc_p-dmamac_addr,
- (unsigned long)desc_p-dmamac_addr +
- roundup(length, ARCH_DMA_MINALIGN));
+ data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(data_start, data_end);
NetReceive(desc_p-dmamac_addr, length);
@@ -371,10 +372,7 @@ static int dw_eth_recv(struct eth_device *dev)
desc_p-txrx_status |= DESC_RXSTS_OWNBYDMA;
/* Flush only status field - others weren't changed */
-
[U-Boot] [PATCH 11/51] arm: socfpga: sysmgr: Clean up system manager
Clean up the system manager register definition and add the missing
register definitions in place.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/system_manager.c| 18 ++--
arch/arm/include/asm/arch-socfpga/system_manager.h | 102 +++--
2 files changed, 86 insertions(+), 34 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
b/arch/arm/cpu/armv7/socfpga/system_manager.c
index d96521b..07c72e4 100644
--- a/arch/arm/cpu/armv7/socfpga/system_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2013 Altera Corporation www.altera.com
+ * Copyright (C) 2013 Altera Corporation www.altera.com
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -7,21 +7,23 @@
#include common.h
#include asm/io.h
#include asm/arch/system_manager.h
+#include asm/arch/fpga_manager.h
DECLARE_GLOBAL_DATA_PTR;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
/*
* Configure all the pin muxes
*/
void sysmgr_pinmux_init(void)
{
- unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
-
- const unsigned long *pval = sys_mgr_init_table;
- unsigned long i;
+ uint32_t regs = (uint32_t)sysmgr_regs-emacio[0];
+ int i;
- for (i = 0; i ARRAY_SIZE(sys_mgr_init_table);
- i++, offset += sizeof(unsigned long)) {
- writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+ for (i = 0; i ARRAY_SIZE(sys_mgr_init_table); i++) {
+ writel(sys_mgr_init_table[i], regs);
+ regs += sizeof(regs);
}
}
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
index 838d210..90d2720 100644
--- a/arch/arm/include/asm/arch-socfpga/system_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2013 Altera Corporation www.altera.com
+ * Copyright (C) 2013 Altera Corporation www.altera.com
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -16,72 +16,122 @@ extern unsigned long
sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
#endif
-
-#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
-
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
- drvsel) 0) 0x7) | (((smplsel) 3) 0x38))
-
struct socfpga_system_manager {
- u32 siliconid1;
+ /* System Manager Module */
+ u32 siliconid1; /* 0x00 */
u32 siliconid2;
u32 _pad_0x8_0xf[2];
- u32 wddbg;
+ u32 wddbg; /* 0x10 */
u32 bootinfo;
u32 hpsinfo;
u32 parityinj;
- u32 fpgaintfgrp_gbl;
+ /* FPGA Interface Group */
+ u32 fpgaintfgrp_gbl;/* 0x20 */
u32 fpgaintfgrp_indiv;
u32 fpgaintfgrp_module;
u32 _pad_0x2c_0x2f;
- u32 scanmgrgrp_ctrl;
+ /* Scan Manager Group */
+ u32 scanmgrgrp_ctrl;/* 0x30 */
u32 _pad_0x34_0x3f[3];
- u32 frzctrl_vioctrl;
+ /* Freeze Control Group */
+ u32 frzctrl_vioctrl;/* 0x40 */
u32 _pad_0x44_0x4f[3];
- u32 frzctrl_hioctrl;
+ u32 frzctrl_hioctrl;/* 0x50 */
u32 frzctrl_src;
u32 frzctrl_hwctrl;
u32 _pad_0x5c_0x5f;
- u32 emacgrp_ctrl;
+ /* EMAC Group */
+ u32 emacgrp_ctrl; /* 0x60 */
u32 emacgrp_l3master;
u32 _pad_0x68_0x6f[2];
- u32 dmagrp_ctrl;
+ /* DMA Controller Group */
+ u32 dmagrp_ctrl;/* 0x70 */
u32 dmagrp_persecurity;
u32 _pad_0x78_0x7f[2];
- u32 iswgrp_handoff[8];
- u32 _pad_0xa0_0xbf[8];
- u32 romcodegrp_ctrl;
+ /* Preloader (initial software) Group */
+ u32 iswgrp_handoff[8]; /* 0x80 */
+ u32 _pad_0xa0_0xbf[8]; /* 0xa0 */
+ /* Boot ROM Code Register Group */
+ u32 romcodegrp_ctrl;/* 0xc0 */
u32 romcodegrp_cpu1startaddr;
u32 romcodegrp_initswstate;
u32 romcodegrp_initswlastld;
- u32 romcodegrp_bootromswstate;
+ u32 romcodegrp_bootromswstate; /* 0xd0 */
u32 __pad_0xd4_0xdf[3];
- u32 romcodegrp_warmramgrp_enable;
+ /* Warm Boot from On-Chip RAM Group */
+ u32 romcodegrp_warmramgrp_enable; /* 0xe0 */
u32 romcodegrp_warmramgrp_datastart;
u32 romcodegrp_warmramgrp_length;
u32
[U-Boot] [PATCH 06/51] mmc: dw_mmc: Fix cache alignment issue
The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.
The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This approach does waste
space by inserting slop inbetween the descriptors, but it makes access
to the descriptors easy as the compiler does know the real size of the
structure. It also makes cache operations easy, since the size of the
structure is cache aligned and the structure start address is as well.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Pantelis Antoniou pa...@antoniou-consulting.com
---
include/dwmmc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/dwmmc.h b/include/dwmmc.h
index b67f11b..109f7c8 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -157,7 +157,7 @@ struct dwmci_idmac {
u32 cnt;
u32 addr;
u32 next_addr;
-};
+} __aligned(ARCH_DMA_MINALIGN);
static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
{
--
2.0.0
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/51] arm: socfpga: Clean up base address file
Sort the list of functional block addresses and fix indentation. No functional change. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de Acked-by: Pavel Machek pa...@denx.de --- .../include/asm/arch-socfpga/socfpga_base_addrs.h | 102 ++--- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index cb062ac..6534283 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -7,56 +7,56 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ -#define SOCFPGA_SDMMC_ADDRESS 0xff704000 -#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 -#define SOCFPGA_L3REGS_ADDRESS 0xff80 -#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb9 -#define SOCFPGA_UART0_ADDRESS 0xffc02000 -#define SOCFPGA_UART1_ADDRESS 0xffc03000 -#define SOCFPGA_SDR_ADDRESS 0xffc2 -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 -#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 -#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 -#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 -#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 -#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 -#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 -#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 -#define SOCFPGA_EMAC0_ADDRESS 0xff70 -#define SOCFPGA_EMAC1_ADDRESS 0xff702000 -#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 -#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 -#define SOCFPGA_STM_ADDRESS 0xfc00 -#define SOCFPGA_DAP_ADDRESS 0xff00 -#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff20 -#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff40 -#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff50 -#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff60 -#define SOCFPGA_QSPI_ADDRESS 0xff705000 -#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 -#define SOCFPGA_GPIO0_ADDRESS 0xff708000 -#define SOCFPGA_GPIO1_ADDRESS 0xff709000 -#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 -#define SOCFPGA_NANDDATA_ADDRESS 0xff90 -#define SOCFPGA_QSPIDATA_ADDRESS 0xffa0 -#define SOCFPGA_USB0_ADDRESS 0xffb0 -#define SOCFPGA_USB1_ADDRESS 0xffb4 -#define SOCFPGA_NANDREGS_ADDRESS 0xffb8 -#define SOCFPGA_CAN0_ADDRESS 0xffc0 -#define SOCFPGA_CAN1_ADDRESS 0xffc01000 -#define SOCFPGA_I2C0_ADDRESS 0xffc04000 -#define SOCFPGA_I2C1_ADDRESS 0xffc05000 -#define SOCFPGA_I2C2_ADDRESS 0xffc06000 -#define SOCFPGA_I2C3_ADDRESS 0xffc07000 -#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 -#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 -#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe0 -#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 -#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 -#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 -#define SOCFPGA_SPIM0_ADDRESS 0xfff0 -#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 -#define SOCFPGA_ROM_ADDRESS 0xfffd -#define SOCFPGA_OCRAM_ADDRESS 0x +#define SOCFPGA_STM_ADDRESS0xfc00 +#define SOCFPGA_DAP_ADDRESS0xff00 +#define SOCFPGA_EMAC0_ADDRESS 0xff70 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_L3REGS_ADDRESS 0xff80 +#define SOCFPGA_USB0_ADDRESS 0xffb0 +#define SOCFPGA_USB1_ADDRESS 0xffb4 +#define SOCFPGA_CAN0_ADDRESS 0xffc0 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SDR_ADDRESS0xffc2 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff0 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_SCANMGR_ADDRESS0xfff02000 +#define SOCFPGA_ROM_ADDRESS0xfffd +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_OCRAM_ADDRESS 0x +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff20 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff40 +#define
[U-Boot] [PATCH V2 10/51] arm: socfpga: Add watchdog disable for socfpga
From: Pavel Machek pa...@denx.de
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 10 ++
arch/arm/cpu/armv7/socfpga/reset_manager.c| 12
arch/arm/include/asm/arch-socfpga/reset_manager.h | 4
3 files changed, 26 insertions(+)
V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index ecae393..71ee912 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -8,6 +8,7 @@
#include asm/io.h
#include miiphy.h
#include netdev.h
+#include asm/arch/reset_manager.h
DECLARE_GLOBAL_DATA_PTR;
@@ -38,6 +39,15 @@ int overwrite_console(void)
int misc_init_r(void)
{
+ /*
+* If the HW watchdog is NOT enabled, make sure it is not running,
+* for example because it was enabled in the preloader. This might
+* trigger a watchdog-triggered reboot of Linux kernel later.
+*/
+#ifndef CONFIG_HW_WATCHDOG
+ socfpga_watchdog_reset();
+#endif
+
return 0;
}
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c
b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index e320c01..5d7aba4 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -14,6 +14,18 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
+void socfpga_watchdog_reset(void)
+{
+ /* assert reset for watchdog */
+ setbits_le32(reset_manager_base-per_mod_reset,
+1 RSTMGR_PERMODRST_L4WD0_LSB);
+
+ /* deassert watchdog from reset (watchdog in not running state) */
+ clrbits_le32(reset_manager_base-per_mod_reset,
+1 RSTMGR_PERMODRST_L4WD0_LSB);
+}
+
/*
* Write the reset manager register to cause reset
*/
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h
b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 3e95476..18506e6 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -10,6 +10,8 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+void socfpga_watchdog_reset(void);
+
struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -27,4 +29,6 @@ struct socfpga_reset_manager {
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
#endif
+#define RSTMGR_PERMODRST_L4WD0_LSB 6
+
#endif /* _RESET_MANAGER_H_ */
--
2.0.0
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[U-Boot] [PATCH 12/51] arm: socfpga: clock: Implant order into bit definitions
The bit definitions for clock manager are complete chaos. Implement
some basic logical order into them.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/include/asm/arch-socfpga/clock_manager.h | 166 +-
1 file changed, 99 insertions(+), 67 deletions(-)
diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h
b/arch/arm/include/asm/arch-socfpga/clock_manager.h
index babac0e..dea171e 100644
--- a/arch/arm/include/asm/arch-socfpga/clock_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h
@@ -103,96 +103,128 @@ struct socfpga_clock_manager {
u32 _pad_0xe0_0x200[72];
};
-#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x0200
+#define CLKMGR_CTRL_SAFEMODE_MASK 0x0001
+#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) 0) 0x0001)
+
+#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) 0) 0x0001)
+#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) 4) 0x0010)
+#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) 3) 0x0008)
+#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) 2) 0x0004)
+#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) 1) 0x0002)
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x0040
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x0080
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x0100
+
+/* Main PLL */
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) 0) 0x0001)
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) 16) 0x003f)
+#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) 1) 0x0002)
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) 3) 0xfff8)
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x0100
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) 2) 0x0004)
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x8000
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
+
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) 0) 0x01ff)
+
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x0010
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x0020
#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x0080
#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x0040
-#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x0020
-#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x0010
#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x0004
-#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
-#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x0200
+
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) 0) 0x0003)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) 2) 0x000c)
#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) 4) 0x0070)
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) 7) 0x0380)
+
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) 0) 0x0003)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) 2) 0x000c)
+
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) 0) 0x0007)
+
#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) 0) 0x0001)
#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) 1) 0x0002)
-#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) 4) 0x0030)
-#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) 2) 0x000c)
-#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) 0) 0x0003)
-#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) 16) 0x003f)
-#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) 3) 0xfff8)
-#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) 2) 0x0004)
-#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) 1) 0x0002)
-#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) 0) 0x0001)
-#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) 22) 0x00c0)
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x
+
+/* Per PLL */
#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) 16) 0x003f)
#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) 3) 0xfff8)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) 25) 0x7e00)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) 24) 0x0100)
-#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) 22) 0x00c0)
-#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) 16) 0x003f)
-#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) 3) 0xfff8)
-#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) 0) 0x01ff)
-#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) 0) 0x01ff)
-#define
[U-Boot] [PATCH V2 15/51] arm: socfpga: clock: Add code to read clock configuration
From: Pavel Machek pa...@denx.de
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/clock_manager.c| 226 +-
arch/arm/include/asm/arch-socfpga/clock_manager.h | 43 +++-
include/configs/socfpga_cyclone5.h| 1 +
3 files changed, 267 insertions(+), 3 deletions(-)
V2: Fixed the L4 MP clock divider and synced the clock code with latest
rocketboards codebase (thanks Dinh for pointing this out)
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index d032bbd..7a6b3b1 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -8,8 +8,10 @@
#include asm/io.h
#include asm/arch/clock_manager.h
+DECLARE_GLOBAL_DATA_PTR;
+
static const struct socfpga_clock_manager *clock_manager_base =
- (void *)SOCFPGA_CLKMGR_ADDRESS;
+ (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
#define CLKMGR_BYPASS_ENABLE 1
#define CLKMGR_BYPASS_DISABLE 0
@@ -358,3 +360,225 @@ void cm_basic_init(const cm_config_t *cfg)
writel(~0, clock_manager_base-per_pll.en);
writel(~0, clock_manager_base-sdr_pll.en);
}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ uint32_t reg, clock;
+
+ /* get the main VCO clock */
+ reg = readl(clock_manager_base-main_pll.vco);
+ clock = CONFIG_HPS_CLK_OSC1_HZ /
+ (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+ clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+ /* get the MPU clock */
+ reg = readl(clock_manager_base-altera.mpuclk);
+ clock /= (reg + 1);
+ reg = readl(clock_manager_base-main_pll.mpuclk);
+ clock /= (reg + 1);
+ return clock;
+}
+
+unsigned long cm_get_sdram_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ /* identify SDRAM PLL clock source */
+ reg = readl(clock_manager_base-sdr_pll.vco);
+ reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg);
+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
+ clock = CONFIG_HPS_CLK_OSC1_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+ clock = CONFIG_HPS_CLK_OSC2_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_F2S)
+ clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+
+ /* get the SDRAM VCO clock */
+ reg = readl(clock_manager_base-sdr_pll.vco);
+ clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1);
+ clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+ /* get the SDRAM (DDR_DQS) clock */
+ reg = readl(clock_manager_base-sdr_pll.ddrdqsclk);
+ reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg);
+ clock /= (reg + 1);
+
+ return clock;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ /* identify the source of L4 SP clock */
+ reg = readl(clock_manager_base-main_pll.l4src);
+ reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
+
+ if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
+ /* get the main VCO clock */
+ reg = readl(clock_manager_base-main_pll.vco);
+ clock = CONFIG_HPS_CLK_OSC1_HZ /
+ (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+ clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+ /* get the clock prior L4 SP divider (main clk) */
+ reg = readl(clock_manager_base-altera.mainclk);
+ clock /= (reg + 1);
+ reg = readl(clock_manager_base-main_pll.mainclk);
+ clock /= (reg + 1);
+ } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
+ /* identify PER PLL clock source */
+ reg = readl(clock_manager_base-per_pll.vco);
+ reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
+ clock = CONFIG_HPS_CLK_OSC1_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+ clock = CONFIG_HPS_CLK_OSC2_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_F2S)
+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+
+ /* get the PER VCO clock */
+ reg = readl(clock_manager_base-per_pll.vco);
+ clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
+ clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+ /* get the clock prior L4 SP divider (periph_base_clk) */
+ reg = readl(clock_manager_base-per_pll.perbaseclk);
+
[U-Boot] [PATCH 14/51] arm: socfpga: clock: Add missing stubs into board file
Add some stub defines, which are used by the clock code, but are missing from the auto-generated header file for the SoCFPGA family. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de Acked-by: Dinh Nguyen dingu...@opensource.altera.com Acked-by: Pavel Machek pa...@denx.de --- board/altera/socfpga/pll_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h index 9bd0442..f0f59a9 100644 --- a/board/altera/socfpga/pll_config.h +++ b/board/altera/socfpga/pll_config.h @@ -94,6 +94,9 @@ /* Info for driver */ #define CONFIG_HPS_CLK_OSC1_HZ (2500) +#define CONFIG_HPS_CLK_OSC2_HZ 0 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 #define CONFIG_HPS_CLK_MAINVCO_HZ (16) #define CONFIG_HPS_CLK_PERVCO_HZ (10) #ifdef CONFIG_SOCFPGA_ARRIA5 -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 13/51] arm: socfpga: clock: Drop nonsense inlining from clock manager code
The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler. Scrub this hint.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
---
arch/arm/cpu/armv7/socfpga/clock_manager.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index 158501a..d032bbd 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -30,7 +30,7 @@ static const struct socfpga_clock_manager *clock_manager_base
=
CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-static inline void cm_wait_for_lock(uint32_t mask)
+static void cm_wait_for_lock(uint32_t mask)
{
register uint32_t inter_val;
do {
@@ -39,7 +39,7 @@ static inline void cm_wait_for_lock(uint32_t mask)
}
/* function to poll in the fsm busy bit */
-static inline void cm_wait_for_fsm(void)
+static void cm_wait_for_fsm(void)
{
while (readl(clock_manager_base-stat) CLKMGR_STAT_BUSY)
;
@@ -49,22 +49,22 @@ static inline void cm_wait_for_fsm(void)
* function to write the bypass register which requires a poll of the
* busy bit
*/
-static inline void cm_write_bypass(uint32_t val)
+static void cm_write_bypass(uint32_t val)
{
writel(val, clock_manager_base-bypass);
cm_wait_for_fsm();
}
/* function to write the ctrl register which requires a poll of the busy bit */
-static inline void cm_write_ctrl(uint32_t val)
+static void cm_write_ctrl(uint32_t val)
{
writel(val, clock_manager_base-ctrl);
cm_wait_for_fsm();
}
/* function to write a clock register that has phase information */
-static inline void cm_write_with_phase(uint32_t value,
- uint32_t reg_address, uint32_t mask)
+static void cm_write_with_phase(uint32_t value,
+ uint32_t reg_address, uint32_t mask)
{
/* poll until phase is zero */
while (readl(reg_address) mask)
--
2.0.0
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[U-Boot] [PATCH 16/51] arm: socfpga: clock: Trim down code duplication
Pull out functions to read frequency of Main clock VCO and
PLL clock VCO as the code is duplicated multiple times.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
---
arch/arm/cpu/armv7/socfpga/clock_manager.c | 96 --
1 file changed, 38 insertions(+), 58 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index 7a6b3b1..ed2b419 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -361,7 +361,7 @@ void cm_basic_init(const cm_config_t *cfg)
writel(~0, clock_manager_base-sdr_pll.en);
}
-unsigned long cm_get_mpu_clk_hz(void)
+static unsigned int cm_get_main_vco_clk_hz(void)
{
uint32_t reg, clock;
@@ -371,6 +371,37 @@ unsigned long cm_get_mpu_clk_hz(void)
(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+ return clock;
+}
+
+static unsigned int cm_get_per_vco_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ /* identify PER PLL clock source */
+ reg = readl(clock_manager_base-per_pll.vco);
+ reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
+ clock = CONFIG_HPS_CLK_OSC1_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+ clock = CONFIG_HPS_CLK_OSC2_HZ;
+ else if (reg == CLKMGR_VCO_SSRC_F2S)
+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+
+ /* get the PER VCO clock */
+ reg = readl(clock_manager_base-per_pll.vco);
+ clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
+ clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+ return clock;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ uint32_t reg, clock;
+
+ clock = cm_get_main_vco_clk_hz();
+
/* get the MPU clock */
reg = readl(clock_manager_base-altera.mpuclk);
clock /= (reg + 1);
@@ -415,11 +446,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
- /* get the main VCO clock */
- reg = readl(clock_manager_base-main_pll.vco);
- clock = CONFIG_HPS_CLK_OSC1_HZ /
- (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
- clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+ clock = cm_get_main_vco_clk_hz();
/* get the clock prior L4 SP divider (main clk) */
reg = readl(clock_manager_base-altera.mainclk);
@@ -427,20 +454,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
reg = readl(clock_manager_base-main_pll.mainclk);
clock /= (reg + 1);
} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
- /* identify PER PLL clock source */
- reg = readl(clock_manager_base-per_pll.vco);
- reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
- if (reg == CLKMGR_VCO_SSRC_EOSC1)
- clock = CONFIG_HPS_CLK_OSC1_HZ;
- else if (reg == CLKMGR_VCO_SSRC_EOSC2)
- clock = CONFIG_HPS_CLK_OSC2_HZ;
- else if (reg == CLKMGR_VCO_SSRC_F2S)
- clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
-
- /* get the PER VCO clock */
- reg = readl(clock_manager_base-per_pll.vco);
- clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
- clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+ clock = cm_get_per_vco_clk_hz();
/* get the clock prior L4 SP divider (periph_base_clk) */
reg = readl(clock_manager_base-per_pll.perbaseclk);
@@ -466,30 +480,13 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
- /* get the main VCO clock */
- reg = readl(clock_manager_base-main_pll.vco);
- clock = CONFIG_HPS_CLK_OSC1_HZ /
- (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
- clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+ clock = cm_get_main_vco_clk_hz();
/* get the SDMMC clock */
reg = readl(clock_manager_base-main_pll.mainnandsdmmcclk);
clock /= (reg + 1);
} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
- /* identify PER PLL clock source */
- reg = readl(clock_manager_base-per_pll.vco);
- reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
- if (reg
[U-Boot] [PATCH 18/51] arm: socfpga: clock: Sync with reference code
Add the missing pieces from the reference clock code from Altera. This
puts the code on par with the Altera U-Boot fork for all but the SDRAM
self-refresh bits, which are not part of this patch.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/clock_manager.c| 42 ++-
arch/arm/include/asm/arch-socfpga/clock_manager.h | 3 ++
2 files changed, 29 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index 1cf0d77..d869f47 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -16,9 +16,16 @@ static const struct socfpga_clock_manager
*clock_manager_base =
static void cm_wait_for_lock(uint32_t mask)
{
register uint32_t inter_val;
+ uint32_t retry = 0;
do {
inter_val = readl(clock_manager_base-inter) mask;
- } while (inter_val != mask);
+ if (inter_val == mask)
+ retry++;
+ else
+ retry = 0;
+ if (retry = 10)
+ break;
+ } while (1);
}
/* function to poll in the fsm busy bit */
@@ -114,15 +121,15 @@ void cm_basic_init(const cm_config_t *cfg)
cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
CLKMGR_BYPASS_MAINPLL);
- /*
-* Put all plls VCO registers back to reset value.
-* Some code might have messed with them.
-*/
- writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
+ /* Put all plls VCO registers back to reset value. */
+ writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE
+ ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
clock_manager_base-main_pll.vco);
- writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
+ writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE
+ ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
clock_manager_base-per_pll.vco);
- writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
+ writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE
+ ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
clock_manager_base-sdr_pll.vco);
/*
@@ -147,14 +154,9 @@ void cm_basic_init(const cm_config_t *cfg)
* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
* with numerator and denominator.
*/
- writel(cfg-main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
- clock_manager_base-main_pll.vco);
-
- writel(cfg-peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
- clock_manager_base-per_pll.vco);
-
- writel(cfg-sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
- clock_manager_base-sdr_pll.vco);
+ writel(cfg-main_vco_base, clock_manager_base-main_pll.vco);
+ writel(cfg-peri_vco_base, clock_manager_base-per_pll.vco);
+ writel(cfg-sdram_vco_base, clock_manager_base-sdr_pll.vco);
/*
* Time starts here
@@ -189,6 +191,9 @@ void cm_basic_init(const cm_config_t *cfg)
writel(cfg-perqspiclk, clock_manager_base-per_pll.perqspiclk);
/* Peri pernandsdmmcclk */
+ writel(cfg-mainnandsdmmcclk,
+ clock_manager_base-main_pll.mainnandsdmmcclk);
+
writel(cfg-pernandsdmmcclk,
clock_manager_base-per_pll.pernandsdmmcclk);
@@ -318,6 +323,11 @@ void cm_basic_init(const cm_config_t *cfg)
writel(~0, clock_manager_base-main_pll.en);
writel(~0, clock_manager_base-per_pll.en);
writel(~0, clock_manager_base-sdr_pll.en);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
+ CLKMGR_INTER_MAINPLLLOST_MASK,
+ clock_manager_base-inter);
}
static unsigned int cm_get_main_vco_clk_hz(void)
diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h
b/arch/arm/include/asm/arch-socfpga/clock_manager.h
index bc91662..fa49f6a 100644
--- a/arch/arm/include/asm/arch-socfpga/clock_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h
@@ -135,6 +135,9 @@ struct socfpga_clock_manager {
#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x0100
#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x0080
#define CLKMGR_INTER_MAINPLLLOCKED_MASK0x0040
+#define CLKMGR_INTER_PERPLLLOST_MASK 0x0010
+#define CLKMGR_INTER_SDRPLLLOST_MASK 0x0020
+#define CLKMGR_INTER_MAINPLLLOST_MASK 0x0008
#define CLKMGR_STAT_BUSY (1 0)
--
2.0.0
___
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[U-Boot] [PATCH 17/51] arm: socfpga: clock: Clean up bit definitions
Clean up the clock code definitions so they are aligned with mainline
standards. There are no functional changes in this patch.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/clock_manager.c| 122 +++-
arch/arm/cpu/armv7/socfpga/spl.c | 174 +++-
arch/arm/include/asm/arch-socfpga/clock_manager.h | 330 --
3 files changed, 323 insertions(+), 303 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index ed2b419..1cf0d77 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -13,25 +13,6 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-#define CLKMGR_BYPASS_ENABLE 1
-#define CLKMGR_BYPASS_DISABLE 0
-#define CLKMGR_STAT_IDLE 0
-#define CLKMGR_STAT_BUSY 1
-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
-#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
-#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
-
-#define CLEAR_BGP_EN_PWRDN \
- (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
- CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
- CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-
-#define VCO_EN_BASE \
- (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
- CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
- CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-
static void cm_wait_for_lock(uint32_t mask)
{
register uint32_t inter_val;
@@ -130,14 +111,8 @@ void cm_basic_init(const cm_config_t *cfg)
writel(0, clock_manager_base-per_pll.en);
/* Put all plls in bypass */
- cm_write_bypass(
- CLKMGR_BYPASS_PERPLLSRC_SET(
- CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
- CLKMGR_BYPASS_SDRPLLSRC_SET(
- CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
- CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
- CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
- CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
+ cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
+ CLKMGR_BYPASS_MAINPLL);
/*
* Put all plls VCO registers back to reset value.
@@ -172,19 +147,14 @@ void cm_basic_init(const cm_config_t *cfg)
* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
* with numerator and denominator.
*/
- writel(cfg-main_vco_base | CLEAR_BGP_EN_PWRDN |
- CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
- clock_manager_base-main_pll.vco);
-
- writel(cfg-peri_vco_base | CLEAR_BGP_EN_PWRDN |
- CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
- clock_manager_base-per_pll.vco);
-
- writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
- cfg-sdram_vco_base | CLEAR_BGP_EN_PWRDN |
- CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
- clock_manager_base-sdr_pll.vco);
+ writel(cfg-main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
+ clock_manager_base-main_pll.vco);
+
+ writel(cfg-peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
+ clock_manager_base-per_pll.vco);
+
+ writel(cfg-sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
+ clock_manager_base-sdr_pll.vco);
/*
* Time starts here
@@ -234,18 +204,16 @@ void cm_basic_init(const cm_config_t *cfg)
/* Enable vco */
/* main pll vco */
- writel(cfg-main_vco_base | VCO_EN_BASE,
+ writel(cfg-main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
clock_manager_base-main_pll.vco);
/* periferal pll */
- writel(cfg-peri_vco_base | VCO_EN_BASE,
+ writel(cfg-peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
clock_manager_base-per_pll.vco);
/* sdram pll vco */
- writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
- cfg-sdram_vco_base | VCO_EN_BASE,
- clock_manager_base-sdr_pll.vco);
+ writel(cfg-sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+ clock_manager_base-sdr_pll.vco);
/* L3 MP and L3 SP */
writel(cfg-maindiv, clock_manager_base-main_pll.maindiv);
@@ -296,8 +264,8 @@ void cm_basic_init(const cm_config_t *cfg)
clock_manager_base-per_pll.vco);
/* assert sdram outresetall */
- writel(cfg-sdram_vco_base | VCO_EN_BASE|
- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
+
[U-Boot] [PATCH 19/51] arm: socfpga: mmc: Pick the clock from clock manager
From: Pavel Machek pa...@denx.de
Make the SoCFPGA MMC stub pick clock via the clock manager
frequency accessors instead of hard-coding the frequency.
Also fix calloc() misuse.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
---
drivers/mmc/socfpga_dw_mmc.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 1f96382..eb69aed 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -7,6 +7,7 @@
#include common.h
#include malloc.h
#include dwmmc.h
+#include errno.h
#include asm/arch/dwmmc.h
#include asm/arch/clock_manager.h
#include asm/arch/system_manager.h
@@ -44,12 +45,18 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
{
struct dwmci_host *host;
+ unsigned long clk = cm_get_mmc_controller_clk_hz();
+
+ if (clk == 0) {
+ printf(%s: MMC clock is zero!, __func__);
+ return -EINVAL;
+ }
/* calloc for zero init */
- host = calloc(sizeof(struct dwmci_host), 1);
+ host = calloc(1, sizeof(struct dwmci_host));
if (!host) {
- printf(dwmci_host calloc fail!\n);
- return -1;
+ printf(%s: calloc() failed!\n, __func__);
+ return -ENOMEM;
}
host-name = SOCFPGA DWMMC;
@@ -58,7 +65,7 @@ int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
host-clksel = socfpga_dwmci_clksel;
host-dev_index = index;
/* fixed clock divide by 4 which due to the SDMMC wrapper */
- host-bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ;
+ host-bus_hz = clk;
host-fifoth_val = MSIZE(0x2) |
RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);
--
2.0.0
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[U-Boot] [PATCH 20/51] arm: socfpga: timer: Pull the timer reload value from config file
The timer reload value is a property of the timer hardware and there is no reason for this to be configurable. Place this into the timer driver just like on the other hardware. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de Acked-by: Dinh Nguyen dingu...@opensource.altera.com Acked-by: Pavel Machek pa...@denx.de --- arch/arm/cpu/armv7/socfpga/timer.c | 2 ++ include/configs/socfpga_cyclone5.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c index 58fc789..253cde3 100644 --- a/arch/arm/cpu/armv7/socfpga/timer.c +++ b/arch/arm/cpu/armv7/socfpga/timer.c @@ -8,6 +8,8 @@ #include asm/io.h #include asm/arch/timer.h +#define TIMER_LOAD_VAL 0x + static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; /* diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 708309b..54343b8 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -195,8 +195,6 @@ /* This timer use eosc1 where the clock frequency is fixed * throughout any condition */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -/* reload value when timer count to zero */ -#define TIMER_LOAD_VAL 0x /* Timer info */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TIMER_RATE 240 -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 21/51] arm: socfpga: reset: Add EMAC reset functions
Add functions to reset the EMAC ethernet blocks. We cannot handle
two EMAC ethernet blocks yet, therefore the ifdefs. Once there is
hardware using both EMAC blocks, this ifdef will have to go.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Acked-by: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/reset_manager.c| 17 +
arch/arm/include/asm/arch-socfpga/reset_manager.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c
b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index 5d7aba4..badc569 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -49,3 +49,20 @@ void reset_deassert_peripherals_handoff(void)
{
writel(0, reset_manager_base-per_mod_reset);
}
+
+/* Change the reset state for EMAC 0 and EMAC 1 */
+void socfpga_emac_reset(int enable)
+{
+ const void *reset = reset_manager_base-per_mod_reset;
+
+ if (enable) {
+ setbits_le32(reset, 1 RSTMGR_PERMODRST_EMAC0_LSB);
+ setbits_le32(reset, 1 RSTMGR_PERMODRST_EMAC1_LSB);
+ } else {
+#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
+ clrbits_le32(reset, 1 RSTMGR_PERMODRST_EMAC0_LSB);
+#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
+ clrbits_le32(reset, 1 RSTMGR_PERMODRST_EMAC1_LSB);
+#endif
+ }
+}
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h
b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 18506e6..3c5ab40 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -10,6 +10,7 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+void socfpga_emac_reset(int enable);
void socfpga_watchdog_reset(void);
struct socfpga_reset_manager {
@@ -29,6 +30,8 @@ struct socfpga_reset_manager {
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
#endif
+#define RSTMGR_PERMODRST_EMAC0_LSB 0
+#define RSTMGR_PERMODRST_EMAC1_LSB 1
#define RSTMGR_PERMODRST_L4WD0_LSB 6
#endif /* _RESET_MANAGER_H_ */
--
2.0.0
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[U-Boot] [PATCH 22/51] arm: socfpga: misc: Add proper ethernet initialization
From: Pavel Machek pa...@denx.de
Add function to initialize the EMAC blocks upon board startup.
The preprocessor guards against building on SoCFPGA-VT and against
SPL build are not needed as those are handled implicitly via both
SPL framework and the socfpga_cyclone5.h config file, which will
not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT.
We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs.
Once there is hardware using both EMAC blocks, this ifdef will have
to go.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 58 --
arch/arm/include/asm/arch-socfpga/system_manager.h | 9
2 files changed, 52 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 71ee912..a23c8ed 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -9,15 +9,58 @@
#include miiphy.h
#include netdev.h
#include asm/arch/reset_manager.h
+#include asm/arch/system_manager.h
DECLARE_GLOBAL_DATA_PTR;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
int dram_init(void)
{
gd-ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_DESIGNWARE_ETH
+int cpu_eth_init(bd_t *bis)
+{
+#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
+ const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
+#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
+ const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
+#else
+#error Incorrect CONFIG_EMAC_BASE value!
+#endif
+
+ /* Initialize EMAC. This needs to be done at least once per boot. */
+
+ /*
+* Putting the EMAC controller to reset when configuring the PHY
+* interface select at System Manager
+*/
+ socfpga_emac_reset(1);
+
+ /* Clearing emac0 PHY interface select to 0 */
+ clrbits_le32(sysmgr_regs-emacgrp_ctrl,
+SYSMGR_EMACGRP_CTRL_PHYSEL_MASK physhift);
+
+ /* configure to PHY interface select choosed */
+ setbits_le32(sysmgr_regs-emacgrp_ctrl,
+SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII physhift);
+
+ /* Release the EMAC controller from reset */
+ socfpga_emac_reset(0);
+
+ /* initialize and register the emac */
+ return designware_initialize(CONFIG_EMAC_BASE,
+CONFIG_PHY_INTERFACE_MODE);
+}
+#endif
+
#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Print CPU information
@@ -50,18 +93,3 @@ int misc_init_r(void)
return 0;
}
-
-
-/*
- * DesignWare Ethernet initialization
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) !defined(CONFIG_SPL_BUILD)
- /* initialize and register the emac */
- return designware_initialize(CONFIG_EMAC_BASE,
-CONFIG_PHY_INTERFACE_MODE);
-#else
- return 0;
-#endif
-}
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
index 90d2720..071ec4f 100644
--- a/arch/arm/include/asm/arch-socfpga/system_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -134,4 +134,13 @@ struct socfpga_system_manager {
#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
drvsel) 0) 0x7) | (((smplsel) 3) 0x38))
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3
+
#endif /* _SYSTEM_MANAGER_H_ */
--
2.0.0
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[U-Boot] [PATCH 24/51] arm: socfpga: misc: Align print_cpuinfo() output
From: Pavel Machek pa...@denx.de
Cosmetic change to the print_cpuinfo() function output. Align the
output with the rest of initial output produced by U-Boot.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 092d2e2..1d878df 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -80,7 +80,7 @@ int cpu_mmc_init(bd_t *bis)
*/
int print_cpuinfo(void)
{
- puts(CPU : Altera SOCFPGA Platform\n);
+ puts(CPU: Altera SoCFPGA Platform\n);
return 0;
}
#endif
--
2.0.0
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[U-Boot] [PATCH 23/51] arm: socfpga: misc: Add SD controller init
From: Pavel Machek pa...@denx.de
Add CPU function to register and initialize the dw_mmc SD controller.
This allows us to use the HPS SDMMC block.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index a23c8ed..092d2e2 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -10,6 +10,7 @@
#include netdev.h
#include asm/arch/reset_manager.h
#include asm/arch/system_manager.h
+#include asm/arch/dwmmc.h
DECLARE_GLOBAL_DATA_PTR;
@@ -61,6 +62,18 @@ int cpu_eth_init(bd_t *bis)
}
#endif
+#ifdef CONFIG_DWMMC
+/*
+ * Initializes MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+ return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
+ CONFIG_HPS_SDMMC_BUSWIDTH, 0);
+}
+#endif
+
#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Print CPU information
--
2.0.0
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[U-Boot] [PATCH 25/51] arm: socfpga: board: Correctly set ATAG position
From: Pavel Machek pa...@denx.de
The bi_boot_params must point to offset 0x100 in DRAM. Make it so.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
board/altera/socfpga/socfpga_cyclone5.c | 4
1 file changed, 4 insertions(+)
diff --git a/board/altera/socfpga/socfpga_cyclone5.c
b/board/altera/socfpga/socfpga_cyclone5.c
index fb92852..bc8a87c 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -35,5 +35,9 @@ int board_early_init_f(void)
int board_init(void)
{
icache_enable();
+
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
return 0;
}
--
2.0.0
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[U-Boot] [PATCH 26/51] arm: socfpga: board: Align checkboard() output
Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Acked-by: Pavel Machek pa...@denx.de
---
board/altera/socfpga/socfpga_cyclone5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/altera/socfpga/socfpga_cyclone5.c
b/board/altera/socfpga/socfpga_cyclone5.c
index bc8a87c..4149842 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
int checkboard(void)
{
- puts(BOARD : Altera SOCFPGA Cyclone5 Board\n);
+ puts(BOARD: Altera SoCFPGA Cyclone5 Board\n);
return 0;
}
--
2.0.0
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Re: [U-Boot] [PATCH fix for v2014.10 0/5] USB keyboard: don't crash on usb reset
On Saturday, September 20, 2014 at 04:54:33 PM, Hans de Goede wrote: Hi Marek, Here is the second set of USB patches / fixes I've been working on, currently u-boot does really bad things (tm) when doing usb reset while using an usb keyboard. This set fixes this. Given that these fix really bad things (tm) I not only believe that these are suitable to go into v2014.10, but I also believe that they actually should :) Applied all, thanks a lot! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Misc. USB fixes
On Saturday, September 20, 2014 at 05:03:51 PM, Hans de Goede wrote: Hi Marek, And last 2 misc. fixes for USB for next. The first patch is self explanatory, the second patch is a result of me looking into why u-boot's usb scanning is so slww, not that it really helps there, but it is a tiny start. I've several other ideas how to speed things up, but those are more work, I've written them down for now, I've no idea if / when I'll have time to work on them. Applied both, thanks a lot! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH fix for v2014.10 1/5] usb: ehci: Properly set hub devnum and portnr with usb-1 hubs in the chain
On Saturday, September 20, 2014 at 04:51:22 PM, Hans de Goede wrote: For full / low speed devices we need to get the devnum and portnr of the tt, so of the first upstream usb-2 hub, not of the parent device (which may be a usb-1 hub). Signed-off-by: Hans de Goede hdego...@redhat.com Applied all, thanks a lot! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/7] Add a better USB keyboard polling method
On Saturday, September 20, 2014 at 05:01:05 PM, Hans de Goede wrote: Hi Marek, This time a patch-set for next :) Currently one can choose between 2 poll methods for usb keyboards, both of which are suboptimal. One option is to use control messages to get reports, which some devices (e.g. my kvm) do not like. The other option is to use interrupt urbs, but usb_submit_int_msg waits for the interrupt packet to show up, meaning that each poll takes 40 ms, slowing anything else down tremendously. This patch-sets adds a third method (only usable with ehci for now), which makes use of the int_queue concept in the ehci code. This allows us to submit an interrupt message, and then poll for the actual completion of this message giving us much lower latency then even the control message method (effectively this gives us 0 latency), while using standard interrupt messages which seems to keep keyboards much happier. I'd be happy to just pick V2 as it would be. The patches look really nice. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 27/51] fpga: altera: Clean up the printing and debug
Clean up the printf() statements and get rid of the PRINTF()
macro by replacing it with debug_cond().
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
drivers/fpga/altera.c | 117 +-
1 file changed, 58 insertions(+), 59 deletions(-)
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 6e34a8e..ed3f0c8 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -15,14 +15,8 @@
#include ACEX1K.h
#include stratixII.h
-/* Define FPGA_DEBUG to get debug printf's */
-/* #define FPGA_DEBUG */
-
-#ifdef FPGA_DEBUG
-#definePRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
+/* Define FPGA_DEBUG to 1 to get debug printf's */
+#define FPGA_DEBUG 0
/* Local Static Functions */
static int altera_validate (Altera_desc * desc, const char *fn);
@@ -32,36 +26,39 @@ int altera_load(Altera_desc *desc, const void *buf, size_t
bsize)
{
int ret_val = FPGA_FAIL;/* assume a failure */
- if (!altera_validate (desc, (char *)__FUNCTION__)) {
- printf (%s: Invalid device descriptor\n, __FUNCTION__);
+ if (!altera_validate (desc, (char *)__func__)) {
+ printf(%s: Invalid device descriptor\n, __func__);
} else {
switch (desc-family) {
case Altera_ACEX1K:
case Altera_CYC2:
#if defined(CONFIG_FPGA_ACEX1K)
- PRINTF (%s: Launching the ACEX1K Loader...\n,
- __FUNCTION__);
+ debug_cond(FPGA_DEBUG,
+ %s: Launching the ACEX1K Loader...\n,
+ __func__);
ret_val = ACEX1K_load (desc, buf, bsize);
#elif defined(CONFIG_FPGA_CYCLON2)
- PRINTF (%s: Launching the CYCLONE II Loader...\n,
- __FUNCTION__);
+ debug_cond(FPGA_DEBUG,
+ %s: Launching the CYCLONE II Loader...\n,
+ __func__);
ret_val = CYC2_load (desc, buf, bsize);
#else
- printf (%s: No support for ACEX1K devices.\n,
- __FUNCTION__);
+ printf(%s: No support for ACEX1K devices.\n,
+ __func__);
#endif
break;
#if defined(CONFIG_FPGA_STRATIX_II)
case Altera_StratixII:
- PRINTF (%s: Launching the Stratix II Loader...\n,
- __FUNCTION__);
+ debug_cond(FPGA_DEBUG,
+ %s: Launching the Stratix II Loader...\n,
+ __func__);
ret_val = StratixII_load (desc, buf, bsize);
break;
#endif
default:
- printf (%s: Unsupported family type, %d\n,
- __FUNCTION__, desc-family);
+ printf(%s: Unsupported family type, %d\n,
+ __func__, desc-family);
}
}
@@ -72,31 +69,33 @@ int altera_dump(Altera_desc *desc, const void *buf, size_t
bsize)
{
int ret_val = FPGA_FAIL;/* assume a failure */
- if (!altera_validate (desc, (char *)__FUNCTION__)) {
- printf (%s: Invalid device descriptor\n, __FUNCTION__);
+ if (!altera_validate (desc, (char *)__func__)) {
+ printf(%s: Invalid device descriptor\n, __func__);
} else {
switch (desc-family) {
case Altera_ACEX1K:
#if defined(CONFIG_FPGA_ACEX)
- PRINTF (%s: Launching the ACEX1K Reader...\n,
- __FUNCTION__);
+ debug_cond(FPGA_DEBUG,
+ %s: Launching the ACEX1K Reader...\n,
+ __func__);
ret_val = ACEX1K_dump (desc, buf, bsize);
#else
- printf (%s: No support for ACEX1K devices.\n,
- __FUNCTION__);
+ printf(%s: No support for ACEX1K devices.\n,
+ __func__);
#endif
break;
#if defined(CONFIG_FPGA_STRATIX_II)
case Altera_StratixII:
- PRINTF (%s: Launching the Stratix II Reader...\n,
- __FUNCTION__);
+ debug_cond(FPGA_DEBUG,
+ %s: Launching the Stratix II Reader...\n,
+
[U-Boot] [PATCH 28/51] fpga: altera: Clean up altera_validate function
Boldly go, where no programmer has gone before and just clean up
the indentation mayhem. No functional change.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
drivers/fpga/altera.c | 43 +--
1 file changed, 21 insertions(+), 22 deletions(-)
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index ed3f0c8..6394afe 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -195,32 +195,31 @@ int altera_info( Altera_desc *desc )
/* - */
-static int altera_validate (Altera_desc * desc, const char *fn)
+static int altera_validate(Altera_desc *desc, const char *fn)
{
- int ret_val = false;
-
- if (desc) {
- if ((desc-family min_altera_type)
- (desc-family max_altera_type)) {
- if ((desc-iface min_altera_iface_type)
- (desc-iface max_altera_iface_type)) {
- if (desc-size) {
- ret_val = true;
- } else {
- printf(%s: NULL part size\n, fn);
- }
- } else {
- printf(%s: Invalid Interface type, %d\n,
- fn, desc-iface);
- }
- } else {
- printf(%s: Invalid family type, %d\n, fn,
desc-family);
- }
- } else {
+ if (!desc) {
printf(%s: NULL descriptor!\n, fn);
+ return false;
}
- return ret_val;
+ if ((desc-family min_altera_type) ||
+ (desc-family max_altera_type)) {
+ printf(%s: Invalid family type, %d\n, fn, desc-family);
+ return false;
+ }
+
+ if ((desc-iface min_altera_iface_type) ||
+ (desc-iface max_altera_iface_type)) {
+ printf(%s: Invalid Interface type, %d\n, fn, desc-iface);
+ return false;
+ }
+
+ if (!desc-size) {
+ printf(%s: NULL part size\n, fn);
+ return false;
+ }
+
+ return true;
}
/* - */
--
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[U-Boot] [PATCH 32/51] fpga: altera: Clean up enums in altera.h
Get rid of the line-over-80 problems and zap the typedef that
went alongside those enums.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
include/altera.h | 76
1 file changed, 49 insertions(+), 27 deletions(-)
diff --git a/include/altera.h b/include/altera.h
index ae5f7ee..e266a64 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -10,35 +10,57 @@
#ifndef _ALTERA_H_
#define _ALTERA_H_
-typedef enum { /* typedef Altera_iface */
- min_altera_iface_type, /* insert all new types after this */
- passive_serial, /* serial data and external clock */
- passive_parallel_synchronous, /* parallel data */
- passive_parallel_asynchronous, /* parallel data */
- passive_serial_asynchronous,/* serial data w/ internal clock (not
used) */
- altera_jtag_mode, /* jtag/tap serial (not used ) */
- fast_passive_parallel, /* fast passive parallel (FPP) */
- fast_passive_parallel_security, /* fast passive parallel with security
(FPPS) */
- max_altera_iface_type /* insert all new types before this */
-} Altera_iface;/* end, typedef Altera_iface */
+enum altera_iface {
+ /* insert all new types after this */
+ min_altera_iface_type,
+ /* serial data and external clock */
+ passive_serial,
+ /* parallel data */
+ passive_parallel_synchronous,
+ /* parallel data */
+ passive_parallel_asynchronous,
+ /* serial data w/ internal clock (not used) */
+ passive_serial_asynchronous,
+ /* jtag/tap serial (not used ) */
+ altera_jtag_mode,
+ /* fast passive parallel (FPP) */
+ fast_passive_parallel,
+ /* fast passive parallel with security (FPPS) */
+ fast_passive_parallel_security,
+ /* insert all new types before this */
+ max_altera_iface_type,
+};
-typedef enum { /* typedef Altera_Family */
- min_altera_type,/* insert all new types after this */
- Altera_ACEX1K, /* ACEX1K Family */
- Altera_CYC2,/* CYCLONII Family */
- Altera_StratixII, /* StratixII Family */
-/* Add new models here */
- max_altera_type /* insert all new types before this */
-} Altera_Family; /* end, typedef Altera_Family */
+enum altera_family {
+ /* insert all new types after this */
+ min_altera_type,
+ /* ACEX1K Family */
+ Altera_ACEX1K,
+ /* CYCLONII Family */
+ Altera_CYC2,
+ /* StratixII Family */
+ Altera_StratixII,
-typedef struct { /* typedef Altera_desc */
- Altera_Family family; /* part type */
- Altera_ifaceiface; /* interface type */
- size_t size; /* bytes of data part can accept */
- void * iface_fns;/* interface function table */
- void * base; /* base interface address */
- int cookie; /* implementation specific cookie */
-} Altera_desc; /* end, typedef Altera_desc */
+ /* Add new models here */
+
+ /* insert all new types before this */
+ max_altera_type,
+};
+
+typedef struct {
+ /* part type */
+ enum altera_family family;
+ /* interface type */
+ enum altera_iface iface;
+ /* bytes of data part can accept */
+ size_t size;
+ /* interface function table */
+ void*iface_fns;
+ /* base interface address */
+ void*base;
+ /* implementation specific cookie */
+ int cookie;
+} Altera_desc;
/* Generic Altera Functions
*/
--
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[U-Boot] [PATCH 29/51] fpga: altera: More indentation trimdown
Further improve the indentation in the rest of the file, where
the indentation is initially a bit less brutal. There is no
functional change in this patch.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
drivers/fpga/altera.c | 238 +-
1 file changed, 120 insertions(+), 118 deletions(-)
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 6394afe..b0f323f 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -26,40 +26,41 @@ int altera_load(Altera_desc *desc, const void *buf, size_t
bsize)
{
int ret_val = FPGA_FAIL;/* assume a failure */
- if (!altera_validate (desc, (char *)__func__)) {
+ if (!altera_validate(desc, (char *)__func__)) {
printf(%s: Invalid device descriptor\n, __func__);
- } else {
- switch (desc-family) {
- case Altera_ACEX1K:
- case Altera_CYC2:
+ return FPGA_FAIL;
+ }
+
+ switch (desc-family) {
+ case Altera_ACEX1K:
+ case Altera_CYC2:
#if defined(CONFIG_FPGA_ACEX1K)
- debug_cond(FPGA_DEBUG,
- %s: Launching the ACEX1K Loader...\n,
- __func__);
- ret_val = ACEX1K_load (desc, buf, bsize);
+ debug_cond(FPGA_DEBUG,
+ %s: Launching the ACEX1K Loader...\n,
+ __func__);
+ ret_val = ACEX1K_load (desc, buf, bsize);
#elif defined(CONFIG_FPGA_CYCLON2)
- debug_cond(FPGA_DEBUG,
- %s: Launching the CYCLONE II Loader...\n,
- __func__);
- ret_val = CYC2_load (desc, buf, bsize);
+ debug_cond(FPGA_DEBUG,
+ %s: Launching the CYCLONE II Loader...\n,
+ __func__);
+ ret_val = CYC2_load (desc, buf, bsize);
#else
- printf(%s: No support for ACEX1K devices.\n,
- __func__);
+ printf(%s: No support for ACEX1K devices.\n,
+ __func__);
#endif
- break;
+ break;
#if defined(CONFIG_FPGA_STRATIX_II)
- case Altera_StratixII:
- debug_cond(FPGA_DEBUG,
- %s: Launching the Stratix II Loader...\n,
- __func__);
- ret_val = StratixII_load (desc, buf, bsize);
- break;
+ case Altera_StratixII:
+ debug_cond(FPGA_DEBUG,
+ %s: Launching the Stratix II Loader...\n,
+ __func__);
+ ret_val = StratixII_load (desc, buf, bsize);
+ break;
#endif
- default:
- printf(%s: Unsupported family type, %d\n,
- __func__, desc-family);
- }
+ default:
+ printf(%s: Unsupported family type, %d\n,
+ __func__, desc-family);
}
return ret_val;
@@ -71,125 +72,126 @@ int altera_dump(Altera_desc *desc, const void *buf,
size_t bsize)
if (!altera_validate (desc, (char *)__func__)) {
printf(%s: Invalid device descriptor\n, __func__);
- } else {
- switch (desc-family) {
- case Altera_ACEX1K:
+ return FPGA_FAIL;
+ }
+
+ switch (desc-family) {
+ case Altera_ACEX1K:
#if defined(CONFIG_FPGA_ACEX)
- debug_cond(FPGA_DEBUG,
- %s: Launching the ACEX1K Reader...\n,
- __func__);
- ret_val = ACEX1K_dump (desc, buf, bsize);
+ debug_cond(FPGA_DEBUG,
+ %s: Launching the ACEX1K Reader...\n,
+ __func__);
+ ret_val = ACEX1K_dump (desc, buf, bsize);
#else
- printf(%s: No support for ACEX1K devices.\n,
- __func__);
+ printf(%s: No support for ACEX1K devices.\n,
+ __func__);
#endif
- break;
+ break;
#if defined(CONFIG_FPGA_STRATIX_II)
- case Altera_StratixII:
- debug_cond(FPGA_DEBUG,
- %s: Launching the Stratix II Reader...\n,
- __func__);
- ret_val = StratixII_dump (desc, buf, bsize);
- break;
+ case Altera_StratixII:
+ debug_cond(FPGA_DEBUG,
+
[U-Boot] [PATCH 31/51] fpga: altera: Make altera_validate return normal values
Make the function return either 0 or -EINVAL, that is, normal
expected error codes and success codes instead of true/false
nonsense.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
drivers/fpga/altera.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 9e9df50..941e7c8 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -12,38 +12,38 @@
* Altera FPGA support
*/
#include common.h
+#include errno.h
#include ACEX1K.h
#include stratixII.h
/* Define FPGA_DEBUG to 1 to get debug printf's */
#define FPGA_DEBUG 0
-/* Local Static Functions */
static int altera_validate(Altera_desc *desc, const char *fn)
{
if (!desc) {
printf(%s: NULL descriptor!\n, fn);
- return false;
+ return -EINVAL;
}
if ((desc-family min_altera_type) ||
(desc-family max_altera_type)) {
printf(%s: Invalid family type, %d\n, fn, desc-family);
- return false;
+ return -EINVAL;
}
if ((desc-iface min_altera_iface_type) ||
(desc-iface max_altera_iface_type)) {
printf(%s: Invalid Interface type, %d\n, fn, desc-iface);
- return false;
+ return -EINVAL;
}
if (!desc-size) {
printf(%s: NULL part size\n, fn);
- return false;
+ return -EINVAL;
}
- return true;
+ return 0;
}
/* - */
@@ -51,7 +51,7 @@ int altera_load(Altera_desc *desc, const void *buf, size_t
bsize)
{
int ret_val = FPGA_FAIL;/* assume a failure */
- if (!altera_validate(desc, (char *)__func__)) {
+ if (altera_validate(desc, (char *)__func__)) {
printf(%s: Invalid device descriptor\n, __func__);
return FPGA_FAIL;
}
@@ -95,7 +95,7 @@ int altera_dump(Altera_desc *desc, const void *buf, size_t
bsize)
{
int ret_val = FPGA_FAIL;/* assume a failure */
- if (!altera_validate (desc, (char *)__func__)) {
+ if (altera_validate(desc, (char *)__func__)) {
printf(%s: Invalid device descriptor\n, __func__);
return FPGA_FAIL;
}
@@ -133,7 +133,7 @@ int altera_info(Altera_desc *desc)
{
int ret_val = FPGA_FAIL;
- if (!altera_validate (desc, (char *)__func__)) {
+ if (altera_validate (desc, (char *)__func__)) {
printf(%s: Invalid device descriptor\n, __func__);
return FPGA_FAIL;
}
--
2.0.0
___
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[U-Boot] [PATCH 35/51] arm: socfpga: reset: Add function to reset FPGA bridges
Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state during startup.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Acked-by: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/reset_manager.c| 38 +++
arch/arm/include/asm/arch-socfpga/reset_manager.h | 2 ++
2 files changed, 40 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c
b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index badc569..1d3a95d 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -8,6 +8,7 @@
#include common.h
#include asm/io.h
#include asm/arch/reset_manager.h
+#include asm/arch/fpga_manager.h
DECLARE_GLOBAL_DATA_PTR;
@@ -50,6 +51,43 @@ void reset_deassert_peripherals_handoff(void)
writel(0, reset_manager_base-per_mod_reset);
}
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+void socfpga_bridges_reset(int enable)
+{
+ /* For SoCFPGA-VT, this is NOP. */
+}
+#else
+
+#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
+#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
+#define L3REGS_REMAP_OCRAM_MASK0x01
+
+void socfpga_bridges_reset(int enable)
+{
+ const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
+ L3REGS_REMAP_HPS2FPGA_MASK |
+ L3REGS_REMAP_OCRAM_MASK;
+
+ if (enable) {
+ /* brdmodrst */
+ writel(0x, reset_manager_base-brg_mod_reset);
+ } else {
+ /* Check signal from FPGA. */
+ if (fpgamgr_poll_fpga_ready()) {
+ /* FPGA not ready. Wait for watchdog timeout. */
+ printf(%s: fpga not ready, hanging.\n, __func__);
+ hang();
+ }
+
+ /* brdmodrst */
+ writel(0, reset_manager_base-brg_mod_reset);
+
+ /* Remap the bridges into memory map */
+ writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
+ }
+}
+#endif
+
/* Change the reset state for EMAC 0 and EMAC 1 */
void socfpga_emac_reset(int enable)
{
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h
b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 3c5ab40..1857b80 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -10,6 +10,8 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+void socfpga_bridges_reset(int enable);
+
void socfpga_emac_reset(int enable);
void socfpga_watchdog_reset(void);
--
2.0.0
___
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[U-Boot] [PATCH 36/51] arm: socfpga: sysmgr: Add FPGA bits into system manager
Add missing system manager bits from Altera U-Boot to make the code
comparable. These are the bits which depend on the FPGA manager.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/system_manager.c | 39 +
1 file changed, 39 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
b/arch/arm/cpu/armv7/socfpga/system_manager.c
index 07c72e4..11f7bad 100644
--- a/arch/arm/cpu/armv7/socfpga/system_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -15,6 +15,43 @@ static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
/*
+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
+ */
+static void populate_sysmgr_fpgaintf_module(void)
+{
+ uint32_t handoff_val = 0;
+
+ /* ISWGRP_HANDOFF_FPGAINTF */
+ writel(0, sysmgr_regs-iswgrp_handoff[2]);
+
+ /* Enable the signal for those HPS peripherals that use FPGA. */
+ if (readl(sysmgr_regs-nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_NAND;
+ if (readl(sysmgr_regs-rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_EMAC1;
+ if (readl(sysmgr_regs-sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SDMMC;
+ if (readl(sysmgr_regs-rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_EMAC0;
+ if (readl(sysmgr_regs-spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SPIM0;
+ if (readl(sysmgr_regs-spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SPIM1;
+
+ /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
+ based on pinmux setting */
+ setbits_le32(sysmgr_regs-iswgrp_handoff[2], handoff_val);
+
+ handoff_val = readl(sysmgr_regs-iswgrp_handoff[2]);
+ if (fpgamgr_test_fpga_ready()) {
+ /* Enable the required signals only */
+ writel(handoff_val, sysmgr_regs-fpgaintfgrp_module);
+ }
+}
+
+/*
* Configure all the pin muxes
*/
void sysmgr_pinmux_init(void)
@@ -26,4 +63,6 @@ void sysmgr_pinmux_init(void)
writel(sys_mgr_init_table[i], regs);
regs += sizeof(regs);
}
+
+ populate_sysmgr_fpgaintf_module();
}
--
2.0.0
___
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[U-Boot] [PATCH 37/51] arm: cache: Add support for write-allocate D-Cache
Add configuration for the write-allocate mode of L1 D-Cache on ARM.
This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA .
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Acked-by: Pavel Machek pa...@denx.de
---
arch/arm/include/asm/system.h | 1 +
arch/arm/lib/cache-cp15.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index d51ba66..ca2d44f 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -185,6 +185,7 @@ enum dcache_option {
DCACHE_OFF = 0x12,
DCACHE_WRITETHROUGH = 0x1a,
DCACHE_WRITEBACK = 0x1e,
+ DCACHE_WRITEALLOC = 0x16,
};
/* Size of an MMU section */
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 3e62d58..2155fe8 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -73,6 +73,8 @@ __weak void dram_bank_mmu_setup(int bank)
i++) {
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+ set_section_dcache(i, DCACHE_WRITEALLOC);
#else
set_section_dcache(i, DCACHE_WRITEBACK);
#endif
--
2.0.0
___
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[U-Boot] [PATCH 33/51] fpga: altera: Turn the switches into table lookup
Add a table of FPGA family with matching functions associated with
it and make all the code just look up the family in that table and
call the associated function instead of the horrible switch voodoo
which was duplicated all over the place.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
drivers/fpga/altera.c | 171 ++
1 file changed, 60 insertions(+), 111 deletions(-)
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 941e7c8..fd2b4f0 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -19,6 +19,26 @@
/* Define FPGA_DEBUG to 1 to get debug printf's */
#define FPGA_DEBUG 0
+static const struct altera_fpga {
+ enum altera_family family;
+ const char *name;
+ int (*load)(Altera_desc *, const void *, size_t);
+ int (*dump)(Altera_desc *, const void *, size_t);
+ int (*info)(Altera_desc *);
+} altera_fpga[] = {
+#if defined(CONFIG_FPGA_ACEX1K)
+ { Altera_ACEX1K, ACEX1K, ACEX1K_load, ACEX1K_dump, ACEX1K_info },
+ { Altera_CYC2, ACEX1K, ACEX1K_load, ACEX1K_dump, ACEX1K_info },
+#elif defined(CONFIG_FPGA_CYCLON2)
+ { Altera_ACEX1K, CycloneII, CYC2_load, CYC2_dump, CYC2_info },
+ { Altera_CYC2, CycloneII, CYC2_load, CYC2_dump, CYC2_info },
+#endif
+#if defined(CONFIG_FPGA_STRATIX_II)
+ { Altera_StratixII, StratixII, StratixII_load,
+ StratixII_dump, StratixII_info },
+#endif
+};
+
static int altera_validate(Altera_desc *desc, const char *fn)
{
if (!desc) {
@@ -46,113 +66,65 @@ static int altera_validate(Altera_desc *desc, const char
*fn)
return 0;
}
-/* - */
-int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
+static const struct altera_fpga *
+altera_desc_to_fpga(Altera_desc *desc, const char *fn)
{
- int ret_val = FPGA_FAIL;/* assume a failure */
+ int i;
- if (altera_validate(desc, (char *)__func__)) {
- printf(%s: Invalid device descriptor\n, __func__);
- return FPGA_FAIL;
+ if (altera_validate(desc, fn)) {
+ printf(%s: Invalid device descriptor\n, fn);
+ return NULL;
}
- switch (desc-family) {
- case Altera_ACEX1K:
- case Altera_CYC2:
-#if defined(CONFIG_FPGA_ACEX1K)
- debug_cond(FPGA_DEBUG,
- %s: Launching the ACEX1K Loader...\n,
- __func__);
- ret_val = ACEX1K_load (desc, buf, bsize);
-#elif defined(CONFIG_FPGA_CYCLON2)
- debug_cond(FPGA_DEBUG,
- %s: Launching the CYCLONE II Loader...\n,
- __func__);
- ret_val = CYC2_load (desc, buf, bsize);
-#else
- printf(%s: No support for ACEX1K devices.\n,
- __func__);
-#endif
- break;
+ for (i = 0; i ARRAY_SIZE(altera_fpga); i++) {
+ if (desc-family == altera_fpga[i].family)
+ break;
+ }
-#if defined(CONFIG_FPGA_STRATIX_II)
- case Altera_StratixII:
- debug_cond(FPGA_DEBUG,
- %s: Launching the Stratix II Loader...\n,
- __func__);
- ret_val = StratixII_load (desc, buf, bsize);
- break;
-#endif
- default:
- printf(%s: Unsupported family type, %d\n,
- __func__, desc-family);
+ if (i == ARRAY_SIZE(altera_fpga)) {
+ printf(%s: Unsupported family type, %d\n, fn, desc-family);
+ return NULL;
}
- return ret_val;
+ return altera_fpga[i];
}
-int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
+int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
{
- int ret_val = FPGA_FAIL;/* assume a failure */
+ const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
- if (altera_validate(desc, (char *)__func__)) {
- printf(%s: Invalid device descriptor\n, __func__);
+ if (!fpga)
return FPGA_FAIL;
- }
- switch (desc-family) {
- case Altera_ACEX1K:
-#if defined(CONFIG_FPGA_ACEX)
- debug_cond(FPGA_DEBUG,
- %s: Launching the ACEX1K Reader...\n,
- __func__);
- ret_val = ACEX1K_dump (desc, buf, bsize);
-#else
- printf(%s: No support for ACEX1K devices.\n,
- __func__);
-#endif
- break;
+ debug_cond(FPGA_DEBUG, %s: Launching the %s Loader...\n,
[U-Boot] [PATCH V2 34/51] arm: socfpga: fpga: Add SoCFPGA FPGA programming interface
From: Pavel Machek pa...@denx.de
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/Makefile | 3 +-
arch/arm/cpu/armv7/socfpga/fpga_manager.c| 78 ++
arch/arm/cpu/armv7/socfpga/misc.c| 37 +++
arch/arm/include/asm/arch-socfpga/fpga_manager.h | 77 ++
drivers/fpga/Makefile| 1 +
drivers/fpga/altera.c| 3 +
drivers/fpga/socfpga.c | 301 +++
include/altera.h | 6 +
8 files changed, 505 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/fpga_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/fpga_manager.h
create mode 100644 drivers/fpga/socfpga.c
V2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support.
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index eb33f2c..8b6e108 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -8,5 +8,6 @@
#
obj-y := lowlevel_init.o
-obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
+obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
+ fpga_manager.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/fpga_manager.c
b/arch/arm/cpu/armv7/socfpga/fpga_manager.c
new file mode 100644
index 000..43fd2fe
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/fpga_manager.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2012 Altera Corporation www.altera.com
+ * All rights reserved.
+ *
+ * This file contains only support functions used also by the SoCFPGA
+ * platform code, the real meat is located in drivers/fpga/socfpga.c .
+ *
+ * SPDX-License-Identifier:BSD-3-Clause
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch/fpga_manager.h
+#include asm/arch/reset_manager.h
+#include asm/arch/system_manager.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timeout count */
+#define FPGA_TIMEOUT_CNT 0x100
+
+static struct socfpga_fpga_manager *fpgamgr_regs =
+ (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+/* Check whether FPGA Init_Done signal is high */
+static int is_fpgamgr_initdone_high(void)
+{
+ unsigned long val;
+
+ val = readl(fpgamgr_regs-gpio_ext_porta);
+ return val FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
+}
+
+/* Get the FPGA mode */
+int fpgamgr_get_mode(void)
+{
+ unsigned long val;
+
+ val = readl(fpgamgr_regs-stat);
+ return val FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int fpgamgr_test_fpga_ready(void)
+{
+ /* Check for init done signal */
+ if (!is_fpgamgr_initdone_high())
+ return 0;
+
+ /* Check again to avoid false glitches */
+ if (!is_fpgamgr_initdone_high())
+ return 0;
+
+ if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
+ return 0;
+
+ return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int fpgamgr_poll_fpga_ready(void)
+{
+ unsigned long i;
+
+ /* If FPGA is blank, wait till WD invoke warm reset */
+ for (i = 0; i FPGA_TIMEOUT_CNT; i++) {
+ /* check for init done signal */
+ if (!is_fpgamgr_initdone_high())
+ continue;
+ /* check again to avoid false glitches */
+ if (!is_fpgamgr_initdone_high())
+ continue;
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 1d878df..8c30b61 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -6,6 +6,7 @@
#include common.h
#include asm/io.h
+#include altera.h
#include miiphy.h
#include netdev.h
#include asm/arch/reset_manager.h
@@ -93,8 +94,44 @@ int overwrite_console(void)
}
#endif
+#ifdef CONFIG_FPGA
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+ {
+ /* Family */
+ Altera_SoCFPGA,
+ /* Interface type */
+ fast_passive_parallel,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* No device function table */
+
[U-Boot] [PATCH 30/51] fpga: altera: Move altera_validate to the top
Move the function to the top of the file to avoid forward declaration.
No functional change.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
drivers/fpga/altera.c | 58 +++
1 file changed, 26 insertions(+), 32 deletions(-)
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index b0f323f..9e9df50 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -19,7 +19,32 @@
#define FPGA_DEBUG 0
/* Local Static Functions */
-static int altera_validate (Altera_desc * desc, const char *fn);
+static int altera_validate(Altera_desc *desc, const char *fn)
+{
+ if (!desc) {
+ printf(%s: NULL descriptor!\n, fn);
+ return false;
+ }
+
+ if ((desc-family min_altera_type) ||
+ (desc-family max_altera_type)) {
+ printf(%s: Invalid family type, %d\n, fn, desc-family);
+ return false;
+ }
+
+ if ((desc-iface min_altera_iface_type) ||
+ (desc-iface max_altera_iface_type)) {
+ printf(%s: Invalid Interface type, %d\n, fn, desc-iface);
+ return false;
+ }
+
+ if (!desc-size) {
+ printf(%s: NULL part size\n, fn);
+ return false;
+ }
+
+ return true;
+}
/* - */
int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
@@ -194,34 +219,3 @@ int altera_info(Altera_desc *desc)
return ret_val;
}
-
-/* - */
-
-static int altera_validate(Altera_desc *desc, const char *fn)
-{
- if (!desc) {
- printf(%s: NULL descriptor!\n, fn);
- return false;
- }
-
- if ((desc-family min_altera_type) ||
- (desc-family max_altera_type)) {
- printf(%s: Invalid family type, %d\n, fn, desc-family);
- return false;
- }
-
- if ((desc-iface min_altera_iface_type) ||
- (desc-iface max_altera_iface_type)) {
- printf(%s: Invalid Interface type, %d\n, fn, desc-iface);
- return false;
- }
-
- if (!desc-size) {
- printf(%s: NULL part size\n, fn);
- return false;
- }
-
- return true;
-}
-
-/* - */
--
2.0.0
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[U-Boot] [PATCH 39/51] arm: socfpga: cache: Enable D-Cache
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Acked-by: Pavel Machek pa...@denx.de
---
board/altera/socfpga/socfpga_cyclone5.c | 1 +
include/configs/socfpga_cyclone5.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/altera/socfpga/socfpga_cyclone5.c
b/board/altera/socfpga/socfpga_cyclone5.c
index 4149842..6b98277 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -35,6 +35,7 @@ int board_early_init_f(void)
int board_init(void)
{
icache_enable();
+ dcache_enable();
/* Address of boot parameters for ATAG (if ATAG is used) */
gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index 76979b1..de60bb2 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -18,7 +18,6 @@
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
-#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_USE_IRQ
#define CONFIG_MISC_INIT_R
@@ -26,6 +25,7 @@
#define CONFIG_SOCFPGA
#define CONFIG_CLOCKS
+#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
#define CONFIG_SYS_CACHELINE_SIZE 32
/* base address for .text section */
--
2.0.0
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[U-Boot] [PATCH 40/51] arm: socfpga: cache: Enable PL310 L2 cache
Enable the PL310 L2 cache controller support for the SoCFPGA. With the cache related issues resolved, this is safe to be done. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de Acked-by: Pavel Machek pa...@denx.de --- include/configs/socfpga_cyclone5.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index de60bb2..c8986d9 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -27,6 +27,8 @@ #define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 38/51] arm: socfpga: cache: Define cacheline size
The Cortex-A9 has 32-byte long L1 cachelines. Define this value. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de Acked-by: Pavel Machek pa...@denx.de --- include/configs/socfpga_cyclone5.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 54343b8..76979b1 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -26,6 +26,8 @@ #define CONFIG_SOCFPGA #define CONFIG_CLOCKS +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TEXT_BASE 0x0840 -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 41/51] arm: socfpga: scu: Add SCU register file
Add the Snoop Control Unit register definition file.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Acked-by: Pavel Machek pa...@denx.de
---
arch/arm/include/asm/arch-socfpga/scu.h | 23 +++
1 file changed, 23 insertions(+)
create mode 100644 arch/arm/include/asm/arch-socfpga/scu.h
diff --git a/arch/arm/include/asm/arch-socfpga/scu.h
b/arch/arm/include/asm/arch-socfpga/scu.h
new file mode 100644
index 000..7a5b074
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/scu.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Marek Vasut ma...@denx.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __SOCFPGA_SCU_H__
+#define __SOCFPGA_SCU_H__
+
+struct scu_registers {
+ u32 ctrl; /* 0x00 */
+ u32 cfg;
+ u32 cpsr;
+ u32 iassr;
+ u32 _pad_0x10_0x3c[12]; /* 0x10 */
+ u32 fsar; /* 0x40 */
+ u32 fear;
+ u32 _pad_0x48_0x50[2];
+ u32 acr;/* 0x54 */
+ u32 sacr;
+};
+
+#endif /* __SOCFPGA_SCU_H__ */
--
2.0.0
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[U-Boot] [PATCH 42/51] arm: socfpga: nic301: Add NIC-301 GPV register file
Add register definition for the NIC-301 used on SoCFPGA.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Acked-by: Pavel Machek pa...@denx.de
---
arch/arm/include/asm/arch-socfpga/nic301.h | 195 +
1 file changed, 195 insertions(+)
create mode 100644 arch/arm/include/asm/arch-socfpga/nic301.h
diff --git a/arch/arm/include/asm/arch-socfpga/nic301.h
b/arch/arm/include/asm/arch-socfpga/nic301.h
new file mode 100644
index 000..3c8ab31
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/nic301.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2014 Marek Vasut ma...@denx.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef_NIC301_REGISTERS_H_
+#define_NIC301_REGISTERS_H_
+
+struct nic301_registers {
+ u32 remap; /* 0x0 */
+ /* Security Register Group */
+ u32 _pad_0x4_0x8[1];
+ u32 l4main;
+ u32 l4sp;
+ u32 l4mp; /* 0x10 */
+ u32 l4osc1;
+ u32 l4spim;
+ u32 stm;
+ u32 lwhps2fpgaregs; /* 0x20 */
+ u32 _pad_0x24_0x28[1];
+ u32 usb1;
+ u32 nanddata;
+ u32 _pad_0x30_0x80[20];
+ u32 usb0; /* 0x80 */
+ u32 nandregs;
+ u32 qspidata;
+ u32 fpgamgrdata;
+ u32 hps2fpgaregs; /* 0x90 */
+ u32 acp;
+ u32 rom;
+ u32 ocram;
+ u32 sdrdata;/* 0xA0 */
+ u32 _pad_0xa4_0x1fd0[1995];
+ /* ID Register Group */
+ u32 periph_id_4;/* 0x1FD0 */
+ u32 _pad_0x1fd4_0x1fe0[3];
+ u32 periph_id_0;/* 0x1FE0 */
+ u32 periph_id_1;
+ u32 periph_id_2;
+ u32 periph_id_3;
+ u32 comp_id_0; /* 0x1FF0 */
+ u32 comp_id_1;
+ u32 comp_id_2;
+ u32 comp_id_3;
+ u32 _pad_0x2000_0x2008[2];
+ /* L4 MAIN */
+ u32 l4main_fn_mod_bm_iss;
+ u32 _pad_0x200c_0x3008[1023];
+ /* L4 SP */
+ u32 l4sp_fn_mod_bm_iss;
+ u32 _pad_0x300c_0x4008[1023];
+ /* L4 MP */
+ u32 l4mp_fn_mod_bm_iss;
+ u32 _pad_0x400c_0x5008[1023];
+ /* L4 OSC1 */
+ u32 l4osc_fn_mod_bm_iss;
+ u32 _pad_0x500c_0x6008[1023];
+ /* L4 SPIM */
+ u32 l4spim_fn_mod_bm_iss;
+ u32 _pad_0x600c_0x7008[1023];
+ /* STM */
+ u32 stm_fn_mod_bm_iss;
+ u32 _pad_0x700c_0x7108[63];
+ u32 stm_fn_mod;
+ u32 _pad_0x710c_0x8008[959];
+ /* LWHPS2FPGA */
+ u32 lwhps2fpga_fn_mod_bm_iss;
+ u32 _pad_0x800c_0x8108[63];
+ u32 lwhps2fpga_fn_mod;
+ u32 _pad_0x810c_0xa008[1983];
+ /* USB1 */
+ u32 usb1_fn_mod_bm_iss;
+ u32 _pad_0xa00c_0xa044[14];
+ u32 usb1_ahb_cntl;
+ u32 _pad_0xa048_0xb008[1008];
+ /* NANDDATA */
+ u32 nanddata_fn_mod_bm_iss;
+ u32 _pad_0xb00c_0xb108[63];
+ u32 nanddata_fn_mod;
+ u32 _pad_0xb10c_0x20008[21439];
+ /* USB0 */
+ u32 usb0_fn_mod_bm_iss;
+ u32 _pad_0x2000c_0x20044[14];
+ u32 usb0_ahb_cntl;
+ u32 _pad_0x20048_0x21008[1008];
+ /* NANDREGS */
+ u32 nandregs_fn_mod_bm_iss;
+ u32 _pad_0x2100c_0x21108[63];
+ u32 nandregs_fn_mod;
+ u32 _pad_0x2110c_0x22008[959];
+ /* QSPIDATA */
+ u32 qspidata_fn_mod_bm_iss;
+ u32 _pad_0x2200c_0x22044[14];
+ u32 qspidata_ahb_cntl;
+ u32 _pad_0x22048_0x23008[1008];
+ /* FPGAMGRDATA */
+ u32 fpgamgrdata_fn_mod_bm_iss;
+ u32 _pad_0x2300c_0x23040[13];
+ u32 fpgamgrdata_wr_tidemark;/* 0x23040 */
+ u32 _pad_0x23044_0x23108[49];
+ u32 fn_mod;
+ u32 _pad_0x2310c_0x24008[959];
+ /* HPS2FPGA */
+ u32 hps2fpga_fn_mod_bm_iss;
+ u32 _pad_0x2400c_0x24040[13];
+ u32 hps2fpga_wr_tidemark; /* 0x24040 */
+ u32 _pad_0x24044_0x24108[49];
+ u32 hps2fpga_fn_mod;
+ u32 _pad_0x2410c_0x25008[959];
+ /* ACP */
+ u32 acp_fn_mod_bm_iss;
+ u32 _pad_0x2500c_0x25108[63];
+ u32 acp_fn_mod;
+ u32 _pad_0x2510c_0x26008[959];
+ /* Boot ROM */
+ u32 bootrom_fn_mod_bm_iss;
+ u32 _pad_0x2600c_0x26108[63];
+ u32 bootrom_fn_mod;
+ u32 _pad_0x2610c_0x27008[959];
+ /* On-chip RAM */
+ u32 ocram_fn_mod_bm_iss;
+ u32
[U-Boot] [PATCH 44/51] arm: socfpga: nic301: Add NIC-301 configuration code
From: Pavel Machek pa...@denx.de
Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA .
The code sets the access permissions for the CPU to the AMBA slaves such
that the CPU can access them in both secure and non-secure mode.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index d3e1150..e0c7dc1 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -13,6 +13,7 @@
#include asm/arch/system_manager.h
#include asm/arch/dwmmc.h
#include asm/arch/nic301.h
+#include asm/arch/scu.h
#include asm/pl310.h
DECLARE_GLOBAL_DATA_PTR;
@@ -23,6 +24,8 @@ static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+static struct scu_registers *scu_regs =
+ (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
int dram_init(void)
{
@@ -133,8 +136,31 @@ static void socfpga_fpga_add(void)
static inline void socfpga_fpga_add(void) {}
#endif
+/*
+ * Convert all NIC-301 AMBA slaves from secure to non-secure
+ */
+static void socfpga_nic301_slave_ns(void)
+{
+ writel(0x1, nic301_regs-lwhps2fpgaregs);
+ writel(0x1, nic301_regs-hps2fpgaregs);
+ writel(0x1, nic301_regs-acp);
+ writel(0x1, nic301_regs-rom);
+ writel(0x1, nic301_regs-ocram);
+ writel(0x1, nic301_regs-sdrdata);
+}
+
int misc_init_r(void)
{
+ socfpga_bridges_reset(1);
+ socfpga_nic301_slave_ns();
+
+ /*
+* Private components security:
+* U-Boot : configure private timer, global timer and cpu component
+* access as non secure for kernel stage (as required by Linux)
+*/
+ setbits_le32(scu_regs-sacr, 0xfff);
+
/* Configure the L2 controller to make SDRAM start at 0 */
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
writel(0x2, nic301_regs-remap);
--
2.0.0
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[U-Boot] [PATCH 43/51] arm: socfpga: pl310: Map SDRAM to 0x0
Configure the PL310 address filter to make sure DRAM is mapped to 0x0.
This code also configures the remap register of NIC-301 and sets the
required 'mpuzero' bit.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 8c30b61..d3e1150 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -12,11 +12,17 @@
#include asm/arch/reset_manager.h
#include asm/arch/system_manager.h
#include asm/arch/dwmmc.h
+#include asm/arch/nic301.h
+#include asm/pl310.h
DECLARE_GLOBAL_DATA_PTR;
+static struct pl310_regs *const pl310 =
+ (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+static struct nic301_registers *nic301_regs =
+ (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
int dram_init(void)
{
@@ -129,6 +135,14 @@ static inline void socfpga_fpga_add(void) {}
int misc_init_r(void)
{
+ /* Configure the L2 controller to make SDRAM start at 0 */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+ writel(0x2, nic301_regs-remap);
+#else
+ writel(0x1, nic301_regs-remap); /* remap.mpuzero */
+ writel(0x1, pl310-pl310_addr_filter_start);
+#endif
+
/* Add device descriptor to FPGA device table */
socfpga_fpga_add();
--
2.0.0
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[U-Boot] [PATCH 45/51] arm: socfpga: Enable DWMMC for SOCFPGA
From: Chin Liang See cl...@altera.com Enable the DesignWare MMC controller driver support for SOCFPGA Cyclone5 dev kit Signed-off-by: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Pavel Machek pa...@denx.de Cc: Marek Vasut ma...@denx.de Cc: Tom Rini tr...@ti.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Wolfgang Denk w...@denx.de --- include/configs/socfpga_cyclone5.h | 16 1 file changed, 16 insertions(+) diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index c8986d9..0da7059 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -251,6 +251,22 @@ /* Clocks source frequency to watchdog timer */ #define CONFIG_DW_WDT_CLOCK_KHZ25000 +/* + * MMC support + */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_SOCFPGA_DWMMC +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH1024 +#define CONFIG_SOCFPGA_DWMMC_DRVSEL3 +#define CONFIG_SOCFPGA_DWMMC_SMPSEL0 +/* using smaller max blk cnt to avoid flooding the limited stack we have */ +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +#endif /* CONFIG_MMC */ /* * SPL Second Program Loader aka Initial Software -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 48/51] arm: socfpga: Add command to control HPS-FPGA bridges
From: Pavel Machek pa...@denx.de
Add command to enable and disable the bridges between HPS and FPGA.
This patch does have a checkpatch issue with the assembler portion,
checkpatch correctly complains that there should be no whitespace
before quoted newline. I do not agree that fixing this specific
checkpatch issue will improve the readability, thus this one is not
addressed.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Marek Vasut ma...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Wolfgang Denk w...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 75 +++
1 file changed, 75 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 85aaf92..ff799f3 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -22,6 +22,8 @@ static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+static struct socfpga_reset_manager *reset_manager_base =
+ (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static struct scu_registers *scu_regs =
@@ -159,8 +161,14 @@ static void socfpga_nic301_slave_ns(void)
writel(0x1, nic301_regs-sdrdata);
}
+static uint32_t iswgrp_handoff[8];
+
int misc_init_r(void)
{
+ int i;
+ for (i = 0; i 8; i++) /* Cache initial SW setting regs */
+ iswgrp_handoff[i] = readl(sysmgr_regs-iswgrp_handoff[i]);
+
socfpga_bridges_reset(1);
socfpga_nic301_slave_ns();
@@ -193,3 +201,70 @@ int misc_init_r(void)
return 0;
}
+
+static void socfpga_sdram_apply_static_cfg(void)
+{
+ const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
+ const uint32_t applymask = 0x8;
+ uint32_t val = readl(staticcfg) | applymask;
+
+ /*
+* SDRAM staticcfg register specific:
+* When applying the register setting, the CPU must not access
+* SDRAM. Luckily for us, we can abuse i-cache here to help us
+* circumvent the SDRAM access issue. The idea is to make sure
+* that the code is in one full i-cache line by branching past
+* it and back. Once it is in the i-cache, we execute the core
+* of the code and apply the register settings.
+*
+* The code below uses 7 instructions, while the Cortex-A9 has
+* 32-byte cachelines, thus the limit is 8 instructions total.
+*/
+ asm volatile(
+ .align 5 \n
+ b 2f \n
+ 1: str %0, [%1]\n
+ dsb \n
+ isb \n
+ b 3f \n
+ 2: b 1b \n
+ 3: nop \n
+ : : r(val), r(staticcfg) : memory, cc);
+}
+
+int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ argv++;
+
+ switch (*argv[0]) {
+ case 'e': /* Enable */
+ writel(iswgrp_handoff[2], sysmgr_regs-fpgaintfgrp_module);
+ socfpga_sdram_apply_static_cfg();
+ writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
+ writel(iswgrp_handoff[0], reset_manager_base-brg_mod_reset);
+ writel(iswgrp_handoff[1], nic301_regs-remap);
+ break;
+ case 'd': /* Disable */
+ writel(0, sysmgr_regs-fpgaintfgrp_module);
+ writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
+ socfpga_sdram_apply_static_cfg();
+ writel(0, reset_manager_base-brg_mod_reset);
+ writel(1, nic301_regs-remap);
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ bridge, 2, 1, do_bridge,
+ SoCFPGA HPS FPGA bridge control,
+ enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n
+ bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA
bridges\n
+
+);
--
2.0.0
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[U-Boot] [PATCH 46/51] arm: socfpga: Enable SDMMC boot for SOCFPGA U-Boot
From: Chin Liang See cl...@altera.com
Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit.
Enable the bootz command as zImage is used instead uImage.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Marek Vasut ma...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Wolfgang Denk w...@denx.de
---
include/configs/socfpga_cyclone5.h | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index 0da7059..ac08e7a 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -93,6 +93,8 @@
#include config_cmd_default.h
/* FAT file system support */
#define CONFIG_CMD_FAT
+/* bootz command support */
+#define CONFIG_CMD_BOOTZ
/*
@@ -117,24 +119,36 @@
#define CONFIG_SYS_PROMPT_HUSH_PS2
#define CONFIG_CMD_RUN
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_BOOTCOMMAND run ramboot
+#else
+#define CONFIG_BOOTCOMMAND run mmcload; run mmcboot
+#endif
/*
* arguments passed to the bootm command. The value of
* CONFIG_BOOTARGS goes into the environment value bootargs.
* Do note the value will overide also the chosen node in FDT blob.
*/
-#define CONFIG_BOOTARGS console=ttyS0,57600,mem=256M@0x0
+#define CONFIG_BOOTARGS console=ttyS0, __stringify(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
verify=n\0 \
loadaddr= __stringify(CONFIG_SYS_LOAD_ADDR) \0 \
ramboot=setenv bootargs CONFIG_BOOTARGS ; \
bootm ${loadaddr} - ${fdt_addr}\0 \
- bootimage=uImage\0 \
+ bootimage=zImage\0 \
fdt_addr=100\0 \
- fsloadcmd=ext2load\0 \
- bootm ${loadaddr} - ${fdt_addr}\0 \
+ fdtimage=socfpga.dtb\0 \
+ fsloadcmd=ext2load\0 \
+ bootm ${loadaddr} - ${fdt_addr}\0 \
+ mmcroot=/dev/mmcblk0p2\0 \
+ mmcboot=setenv bootargs CONFIG_BOOTARGS \
+root=${mmcroot} rw rootwait; \
+ bootz ${loadaddr} - ${fdt_addr}\0 \
+ mmcload=mmc rescan; \
+ fatload mmc 0:1 ${loadaddr} ${bootimage}; \
+ fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0 \
qspiroot=/dev/mtdblock0\0 \
qspirootfstype=jffs2\0 \
qspiboot=setenv bootargs CONFIG_BOOTARGS \
--
2.0.0
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[U-Boot] [PATCH 50/51] arm: socfpga: Split SoCFPGA configuration
From: Pavel Machek pa...@denx.de Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de --- include/configs/socfpga_cyclone5.h| 211 ++ include/configs/socfpga_cyclone5_common.h | 196 +++ 2 files changed, 207 insertions(+), 200 deletions(-) create mode 100644 include/configs/socfpga_cyclone5_common.h diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index da313fd..0974d6f 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -1,26 +1,16 @@ /* - * Copyright (C) 2012 Altera Corporation www.altera.com + * Copyright (C) 2014 Marek Vasut ma...@denx.de * * SPDX-License-Identifier:GPL-2.0+ */ -#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ -#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ +#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ +#define __CONFIG_SOCFPGA_CYCLONE5_H__ #include asm/arch/socfpga_base_addrs.h #include ../../board/altera/socfpga/pinmux_config.h #include ../../board/altera/socfpga/iocsr_config.h #include ../../board/altera/socfpga/pll_config.h -#define CONFIG_SYS_GENERIC_BOARD - -/* Virtual target or real hardware */ -#undef CONFIG_SOCFPGA_VIRTUAL_TARGET - -#define CONFIG_ARMV7 -#define CONFIG_SYS_THUMB_BUILD - -#define CONFIG_SOCFPGA - /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH #include config_cmd_default.h @@ -46,44 +36,8 @@ #define CONFIG_REGEX /* Enable regular expression support */ -/* - * High level configuration - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MISC_INIT_R -#define CONFIG_SYS_NO_FLASH -#define CONFIG_CLOCKS - -#define CONFIG_FIT -#define CONFIG_OF_LIBFDT -#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Memory configurations - */ +/* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x4000 /* 1GiB on SoCDK */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x0 -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - -#define CONFIG_SYS_INIT_RAM_ADDR 0x -#define CONFIG_SYS_INIT_RAM_SIZE (0x1 - 0x100) -#define CONFIG_SYS_INIT_SP_ADDR\ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TEXT_BASE 0x0840 -#else -#define CONFIG_SYS_TEXT_BASE 0x0140 -#endif /* Booting Linux */ #define CONFIG_BOOTDELAY 3 @@ -97,42 +51,8 @@ #define CONFIG_LOADADDR0x8000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 1024/* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE/* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Cache - */ -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS - -/* - * Ethernet on SoC (EMAC) - */ -#if defined(CONFIG_CMD_NET) !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -#define CONFIG_DESIGNWARE_ETH -#define CONFIG_NET_MULTI -#define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_MII -#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) -#define CONFIG_PHYLIB -#define CONFIG_PHY_GIGE - +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) #define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS #define CONFIG_PHY_INTERFACE_MODE
[U-Boot] [PATCH 51/51] arm: socfpga: Use CMD_FS_GENERIC
Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the
filesystem type into the environment.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
include/configs/socfpga_cyclone5.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index 0974d6f..f325038 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -26,6 +26,7 @@
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
@@ -86,8 +87,8 @@
root=${mmcroot} rw rootwait; \
bootz ${loadaddr} - ${fdt_addr}\0 \
mmcload=mmc rescan; \
- fatload mmc 0:1 ${loadaddr} ${bootimage}; \
- fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0 \
+ load mmc 0:1 ${loadaddr} ${bootimage}; \
+ load mmc 0:1 ${fdt_addr} ${fdtimage}\0 \
qspiroot=/dev/mtdblock0\0 \
qspirootfstype=jffs2\0 \
qspiboot=setenv bootargs CONFIG_BOOTARGS \
--
2.0.0
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[U-Boot] [PATCH 49/51] arm: socfpga: Clean up SoCFPGA configuration
From: Pavel Machek pa...@denx.de Reorganize and cleanup the configuration file for SoCFPGA. There is no functional change after this cleanup. This was necessary, since the file was a wild mess and it was impossible to make sense of it's content, let alone change something without breaking some other thing. This patch puts the contents on par with regular U-Boot standards. Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER and CONFIG_USE_IRQ, which is undefined by default. Finally, do logical reordering of the defines in the file so it's much more readable. The reordering was also necessary for the splitting as the initial one was messy. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de --- include/configs/socfpga_cyclone5.h | 406 + 1 file changed, 188 insertions(+), 218 deletions(-) diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index ac08e7a..da313fd 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -1,319 +1,289 @@ /* - * Copyright (C) 2012 Altera Corporation www.altera.com + * Copyright (C) 2012 Altera Corporation www.altera.com * * SPDX-License-Identifier:GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ +#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ #include asm/arch/socfpga_base_addrs.h #include ../../board/altera/socfpga/pinmux_config.h #include ../../board/altera/socfpga/iocsr_config.h #include ../../board/altera/socfpga/pll_config.h -/* - * High level configuration - */ +#define CONFIG_SYS_GENERIC_BOARD + /* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_ARMV7 -#undef CONFIG_USE_IRQ +#define CONFIG_SYS_THUMB_BUILD -#define CONFIG_MISC_INIT_R -#define CONFIG_SINGLE_BOOTLOADER #define CONFIG_SOCFPGA -#define CONFIG_CLOCKS -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include config_cmd_default.h +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG -/* base address for .text section */ -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TEXT_BASE 0x0840 -#else -#define CONFIG_SYS_TEXT_BASE 0x0140 -#endif -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_USB -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT SOCFPGA_CYCLONE5 # -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_REGEX /* Enable regular expression support */ /* - * Display CPU and Board Info + * High level configuration */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO - -/* - * Enable early stage initialization at C environment - */ #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CLOCKS -/* flat device tree */ +#define CONFIG_FIT #define CONFIG_OF_LIBFDT -/* skip updating the FDT blob */ -#define CONFIG_FDT_BLOB_SKIP_UPDATE -/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ -#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) +#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) -#define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (__malloc_start)) -#define CONFIG_SYS_SPL_MALLOC_SIZE (__malloc_end - __malloc_start) +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* - * Memory allocation (MALLOC) + * Memory configurations */ -/* Room required on the stack for the environment data */ -#define CONFIG_ENV_SIZE1024 -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define PHYS_SDRAM_1_SIZE 0x4000 /* 1GiB on SoCDK */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x0 +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
[U-Boot] [PATCH 47/51] arm: socfpga: Move cache_enable to CPU code
Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Marek Vasut ma...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Wolfgang Denk w...@denx.de
---
arch/arm/cpu/armv7/socfpga/misc.c | 10 ++
board/altera/socfpga/socfpga_cyclone5.c | 3 ---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index e0c7dc1..85aaf92 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -33,6 +33,16 @@ int dram_init(void)
return 0;
}
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+
/*
* DesignWare Ethernet initialization
*/
diff --git a/board/altera/socfpga/socfpga_cyclone5.c
b/board/altera/socfpga/socfpga_cyclone5.c
index 6b98277..0f81d89 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -34,9 +34,6 @@ int board_early_init_f(void)
*/
int board_init(void)
{
- icache_enable();
- dcache_enable();
-
/* Address of boot parameters for ATAG (if ATAG is used) */
gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
--
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[U-Boot] [PATCH 2/3] arm: socfpga: config: Enable USB support
Enable support for the DWC2 USB controller. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de --- include/configs/socfpga_cyclone5_common.h | 8 1 file changed, 8 insertions(+) diff --git a/include/configs/socfpga_cyclone5_common.h b/include/configs/socfpga_cyclone5_common.h index 49504dc..3f8f91f 100644 --- a/include/configs/socfpga_cyclone5_common.h +++ b/include/configs/socfpga_cyclone5_common.h @@ -157,6 +157,14 @@ #define CONFIG_BAUDRATE115200 /* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_STORAGE +#endif + +/* * U-Boot environment */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] usb: dwc2: Add driver for Synopsis DWC2 USB IP block
From: Oleksandr Tymoshenko go...@bluezbox.com
This is the USB host controller used on the Altera SoCFPGA and Raspbery Pi.
This code has three checkpatch warnings, but to make sure it stays at least
readable and clear, these are not fixed. These bugs are in the USB request
handling combinatorial logic, so any abstracting of those is out of question.
Tested on DENX MCV (Altera SoCFPGA 5CSFXC6C6U23C8N) and RPi B+ (BCM2835).
Signed-off-by: Oleksandr Tymoshenko go...@bluezbox.com
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
README| 3 +
drivers/usb/host/Makefile | 3 +
drivers/usb/host/dwc2.c | 952 ++
drivers/usb/host/dwc2.h | 784 ++
include/usb.h | 3 +-
5 files changed, 1744 insertions(+), 1 deletion(-)
create mode 100644 drivers/usb/host/dwc2.c
create mode 100644 drivers/usb/host/dwc2.h
diff --git a/README b/README
index 0a0f528..ba23b32 100644
--- a/README
+++ b/README
@@ -1453,6 +1453,9 @@ The following options need to be configured:
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
txfilltuning field in the EHCI controller on reset.
+ CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
+ HW module registers
+
- USB Device:
Define the below if you wish to use the USB console.
Once firmware is rebuilt from a serial console issue the
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c4f5157..c9d2ed5 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -45,3 +45,6 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
+
+# designware
+obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
new file mode 100644
index 000..aede53b
--- /dev/null
+++ b/drivers/usb/host/dwc2.c
@@ -0,0 +1,952 @@
+/*
+ * Copyright (C) 2012 Oleksandr Tymoshenko go...@freebsd.org
+ * Copyright (C) 2014 Marek Vasut ma...@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include common.h
+#include errno.h
+#include usb.h
+#include malloc.h
+#include usbroothubdes.h
+#include asm/io.h
+
+#include dwc2.h
+
+static int wait_for_bit(void *reg, const uint32_t mask, bool set)
+{
+ unsigned int timeout = 100;
+ uint32_t val;
+
+ while (--timeout) {
+ val = readl(reg);
+ if (!set)
+ val = ~val;
+
+ if ((val mask) == mask)
+ return 0;
+
+ udelay(1);
+ }
+
+ printf(%s: Timeout (reg=%p mask=%08x wait_set=%i)\n,
+ __func__, reg, mask, set);
+
+ return -ETIMEDOUT;
+}
+
+/**
+ * Initializes the FSLSPClkSel field of the HCFG register
+ * depending on the PHY type.
+ */
+static void init_fslspclksel(struct dwc2_core_regs *regs)
+{
+ uint32_t phyclk;
+#ifdef CONFIG_DWC2_ULPI_FS_LS
+ uint32_t hwcfg2 = readl(regs-ghwcfg2);
+ uint32_t hval = (ghwcfg2 DWC2_HWCFG2_HS_PHY_TYPE_MASK)
+ DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
+ uint32_t fval = (ghwcfg2 DWC2_HWCFG2_FS_PHY_TYPE_MASK)
+ DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
+
+ if ((hval == 2) (fval == 1))
+ phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
+ else
+#endif
+
+#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+ phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
+#else
+ /* High speed PHY running at full speed or high speed */
+ phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
+#endif
+
+ clrsetbits_le32(regs-host_regs.hcfg,
+ DWC2_HCFG_FSLSPCLKSEL_MASK,
+ phyclk DWC2_HCFG_FSLSPCLKSEL_OFFSET);
+}
+
+/**
+ * Flush a Tx FIFO.
+ *
+ * @param regs Programming view of DWC_otg controller.
+ * @param num Tx FIFO to flush.
+ */
+static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
+{
+ writel(DWC2_GRSTCTL_TXFFLSH | (num DWC2_GRSTCTL_TXFNUM_OFFSET),
+ regs-grstctl);
+ wait_for_bit(regs-grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
+
+ /* Wait for 3 PHY Clocks */
+ udelay(1);
+}
+
+/**
+ * Flush Rx FIFO.
+ *
+ * @param regs Programming view of DWC_otg controller.
+ */
+static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
+{
+ writel(DWC2_GRSTCTL_RXFFLSH, regs-grstctl);
+ wait_for_bit(regs-grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
+
+ /* Wait for 3 PHY Clocks */
+ udelay(1);
+}
+
+/**
+ * Do core
[U-Boot] [PATCH 0/3] usb: dwc2: Add and enable DWC2 driver
This series adds reworked DWC2 USB driver based on work from Oleksandr. This series also enables that driver on Altera SoCFPGA Cyclone V SoC and RPi B+ . The patch 2/3 in this series depends on another series, but as this series is targetting next, that would be no problem or it can be skipped. The dep is [PATCH 00/51] arm: socfpga: Usability fixes . Marek Vasut (2): arm: socfpga: config: Enable USB support arm: rpi: Enable USB support on RPi Oleksandr Tymoshenko (1): usb: dwc2: Add driver for Synopsis DWC2 USB IP block README| 3 + drivers/usb/host/Makefile | 3 + drivers/usb/host/dwc2.c | 952 ++ drivers/usb/host/dwc2.h | 784 include/configs/rpi_b.h | 15 +- include/configs/socfpga_cyclone5_common.h | 8 + include/usb.h | 3 +- 7 files changed, 1761 insertions(+), 7 deletions(-) create mode 100644 drivers/usb/host/dwc2.c create mode 100644 drivers/usb/host/dwc2.h Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] arm: rpi: Enable USB support on RPi
Enable DWC2 USB, storage and ethernet support. Tested on RPi B+. Signed-off-by: Marek Vasut ma...@denx.de Cc: Stephen Warren swar...@wwwdotorg.org Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@altera.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Wolfgang Denk w...@denx.de Cc: Pavel Machek pa...@denx.de --- include/configs/rpi_b.h | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index 2d69809..9a53232 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -124,13 +124,7 @@ /* Some things don't make sense on this HW or yet */ #undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS #undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_MII -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_PING /* Environment */ #define ENV_DEVICE_SETTINGS \ @@ -181,4 +175,13 @@ #define CONFIG_BOOTDELAY 2 +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_DWC2_REG_ADDR 0x2098 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#endif + #endif -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3] ARM: mx6: Add support for Kosagi Novena
Add support for the Kosagi Novena board. Currently supported are:
- I2C busses
- FEC Ethernet
- MMC0, MMC1, Booting from MMC
- SATA
- USB ports
- USB Ethernet
Signed-off-by: Marek Vasut ma...@denx.de
---
arch/arm/Kconfig | 4 +
board/kosagi/novena/Kconfig | 23 ++
board/kosagi/novena/Makefile | 11 +
board/kosagi/novena/novena.c | 348 +
board/kosagi/novena/novena_spl.c | 529 +++
board/kosagi/novena/setup.cfg| 47
configs/novena_defconfig | 4 +
include/configs/imx6_spl.h | 2 +-
include/configs/novena.h | 302 ++
9 files changed, 1270 insertions(+), 2 deletions(-)
create mode 100644 board/kosagi/novena/Kconfig
create mode 100644 board/kosagi/novena/Makefile
create mode 100644 board/kosagi/novena/novena.c
create mode 100644 board/kosagi/novena/novena_spl.c
create mode 100644 board/kosagi/novena/setup.cfg
create mode 100644 configs/novena_defconfig
create mode 100644 include/configs/novena.h
V2: - Drop the tegra_keyboard_init() comment altogether
- Immediatelly return from the SD controller probe function on failure
- Rename PFUZE100_PMIC to just PFUZE100
- Fix the IMX OTP support with CMD_FUSE
V3: - Zap rootpath builtin env variable
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 106aed9..4da1923 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -411,6 +411,9 @@ config TARGET_GW_VENTANA
config TARGET_HUMMINGBOARD
bool Support hummingboard
+config TARGET_KOSAGI_NOVENA
+ bool Support Kosagi Novena
+
config TARGET_TQMA6
bool TQ Systems TQMa6 board
@@ -637,6 +640,7 @@ source board/imx31_phycore/Kconfig
source board/isee/igep0033/Kconfig
source board/jornada/Kconfig
source board/karo/tx25/Kconfig
+source board/kosagi/novena/Kconfig
source board/logicpd/imx27lite/Kconfig
source board/logicpd/imx31_litekit/Kconfig
source board/mpl/vcma9/Kconfig
diff --git a/board/kosagi/novena/Kconfig b/board/kosagi/novena/Kconfig
new file mode 100644
index 000..4e52be9
--- /dev/null
+++ b/board/kosagi/novena/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_KOSAGI_NOVENA
+
+config SYS_CPU
+ string
+ default armv7
+
+config SYS_BOARD
+ string
+ default novena
+
+config SYS_VENDOR
+ string
+ default kosagi
+
+config SYS_SOC
+ string
+ default mx6
+
+config SYS_CONFIG_NAME
+ string
+ default novena
+
+endif
diff --git a/board/kosagi/novena/Makefile b/board/kosagi/novena/Makefile
new file mode 100644
index 000..f67bbc9
--- /dev/null
+++ b/board/kosagi/novena/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2014 Marek Vasut ma...@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := novena.o
+else
+obj-y := novena_spl.o
+endif
diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c
new file mode 100644
index 000..49f5428
--- /dev/null
+++ b/board/kosagi/novena/novena.c
@@ -0,0 +1,348 @@
+/*
+ * Novena board support
+ *
+ * Copyright (C) 2014 Marek Vasut ma...@denx.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/errno.h
+#include asm/gpio.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/crm_regs.h
+#include asm/arch/imx-regs.h
+#include asm/arch/iomux.h
+#include asm/arch/mxc_hdmi.h
+#include asm/arch/sys_proto.h
+#include asm/imx-common/boot_mode.h
+#include asm/imx-common/iomux-v3.h
+#include asm/imx-common/mxc_i2c.h
+#include asm/imx-common/sata.h
+#include asm/imx-common/video.h
+#include fsl_esdhc.h
+#include i2c.h
+#include input.h
+#include ipu_pixfmt.h
+#include linux/fb.h
+#include linux/input.h
+#include malloc.h
+#include micrel.h
+#include miiphy.h
+#include mmc.h
+#include netdev.h
+#include power/pmic.h
+#include power/pfuze100_pmic.h
+#include stdio_dev.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14)
+#define NOVENA_SD_CD IMX_GPIO_NR(1, 4)
+#define NOVENA_USB_HUB_RESET IMX_GPIO_NR(7, 12)
+
+/*
+ * GPIO button
+ */
+#ifdef CONFIG_KEYBOARD
+static struct input_config button_input;
+
+static int novena_gpio_button_read_keys(struct input_config *input)
+{
+ int key = KEY_ENTER;
+ if (gpio_get_value(NOVENA_BUTTON_GPIO))
+ return 0;
+ input_send_keycodes(button_input, key, 1);
+ return 1;
+}
+
+static int novena_gpio_button_getc(struct stdio_dev *dev)
+{
+ return input_getc(button_input);
+}
+static int novena_gpio_button_tstc(struct stdio_dev *dev)
+{
+ return input_tstc(button_input);
+}
+
+static int novena_gpio_button_init(struct stdio_dev *dev)
+{
+ gpio_direction_input(NOVENA_BUTTON_GPIO);
+ input_set_delays(button_input, 250, 250);
+ return 0;
+}
+
+int drv_keyboard_init(void)
+{
+ int error;
+ struct stdio_dev dev = {
+ .name = button,
+ .flags = DEV_FLAGS_INPUT |
Re: [U-Boot] [PATCH] ARM: mx6: Add support for Kosagi Novena
On Tuesday, September 16, 2014 at 01:00:11 PM, Stefano Babic wrote: On 30/08/2014 16:20, Marek Vasut wrote: On Saturday, August 30, 2014 at 03:55:48 PM, Fabio Estevam wrote: On Sat, Aug 30, 2014 at 9:40 AM, Marek Vasut ma...@denx.de wrote: On Friday, August 29, 2014 at 07:08:54 PM, Fabio Estevam wrote: [...] +/* Extra U-Boot environment. */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + fdt_high=0x\0 \ + initrd_high=0x\0 \ + consdev=ttymxc1\0 \ + baudrate=115200\0 \ + bootdev=/dev/mmcblk0p1\0 \ + rootdev=/dev/mmcblk0p2\0 \ + netdev=eth0\0 \ + rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0 \ This seems to be a too specific rootpath name. Not everyone will use this same rootpath. You're right, but what kind of sane default do you suggest ? The user will overwrite this anyway ... I would say just get rid of this default rootpath entry. Users will have to add their own ipaddr, serverip and rootpath anyway. Sure, but having some default value is better than having all the scripts broken because the variable is not set at all, right ? No, I do not think so. If it is broken, a user must check for it and set it to an appropriate name. The path is even wrong if another ELDK version is used. I would suggest, as Fabio did, to drop it. I disagree, but V3 is out so it should be OK. Can we get this into .10 release ,since it's been on the list for so long ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] cm_fx6: Remove CONFIG_NETMASK
Hi Fabio, On 21/09/14 02:05, Fabio Estevam wrote: From: Fabio Estevam fabio.este...@freescale.com We should not hardcode CONFIG_NETMASK in the config file. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- Acked-by: Nikita Kiryanov nik...@compulab.co.il -- Regards, Nikita Kiryanov ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7] ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote: BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI. Signed-off-by: Chen-Yu Tsai w...@csie.org Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] ARM: sun6i: Add base address for the new controllers in A31
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote: From: Oliver Schinagl oli...@schinagl.nl A31 has several new and changed memory address. This patch adds them. Signed-off-by: Oliver Schinagl oli...@schinagl.nl Signed-off-by: Hans de Goede hdego...@redhat.com Signed-off-by: Chen-Yu Tsai w...@csie.org Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] u-boot-atmel/master - u-boot-arm/master
Hi Andreas, On Fri, 19 Sep 2014 08:32:28 +0200, Andreas Bießmann andreas.de...@googlemail.com wrote: Dear Albert Aribaud, please pull the following changes into u-boot-arm/master. The following changes since commit 9170818a4e004af7893fa0113f6e5b4afafded55: kconfiglib: change SPDX-License-Identifier to ISC (2014-09-17 21:03:18 -0400) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to 015b18c642d9b0f92d1b35f6d6ed73a6a0b29675: ARM: at91sam9rlek: convert to generic board support (2014-09-19 00:11:24 +0200) Bo Shen (7): ARM: atmel: sama5d3xek: add nor flash init function ARM: atmel: sama5d3xek: enable NOR flash support ARM: atmel: sama5d3: add timings register ARM: atmel: use pcr to enable or disable peripheral clock ARM: atmel: add pcr related definition USB: ohci-at91: use pcr to enable or disable clock USB: ehci-atmel: use pcr to enable or disable clock Boris BREZILLON (1): mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECC Wu, Josh (3): mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc register ARM: at91sam9n12ek: convert to generic board support ARM: at91sam9rlek: convert to generic board support arch/arm/cpu/armv7/at91/clock.c | 24 +-- arch/arm/include/asm/arch-at91/at91_pmc.h|6 ++- arch/arm/include/asm/arch-at91/clk.h |1 + arch/arm/include/asm/arch-at91/sama5d3.h |1 + arch/arm/include/asm/arch-at91/sama5d3_smc.h |3 +- board/atmel/sama5d3xek/sama5d3xek.c | 58 ++ drivers/mtd/nand/atmel_nand.c| 22 +- drivers/mtd/nand/atmel_nand_ecc.h|3 ++ drivers/usb/host/ehci-atmel.c|8 drivers/usb/host/ohci-at91.c |8 ++-- include/configs/at91sam9n12ek.h |1 + include/configs/at91sam9rlek.h |2 + include/configs/sama5d3xek.h | 13 +- 13 files changed, 129 insertions(+), 21 deletions(-) Applied to u-boot-arm/master, thanks! (7 boards fail to build after like before this PR, namely openrd_client tricorder_flash tricorder cm_fx6 openrd_ultimate trimslice openrd_base, all of which are accounted for) Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] arm: goni: make board generic
Hi Robert, On 17 September 2014 02:03, Robert Baldyga r.bald...@samsung.com wrote: Define CONFIG_SYS_GENERIC_BOARD to make board generic. Signed-off-by: Robert Baldyga r.bald...@samsung.com Please see this patch too: http://patchwork.ozlabs.org/patch/389163/ Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 01/13] dm: Move pre-reloc init earlier to cope with board_early_init_f()
On 3 September 2014 17:36, Simon Glass s...@chromium.org wrote: In order to support GPIO access in board_early_init_f() we must set up driver model before this function is called. In any case, earlier is better since driver model is (or will become) a key function for most init. Signed-off-by: Simon Glass s...@chromium.org Applied to dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 02/13] Set up stdio earlier when using driver model
On 3 September 2014 17:37, Simon Glass s...@chromium.org wrote: Since driver model registers itself with the stdio subsystem, and we want to avoid delayed registration and other complexity associated with the current serial console, move the stdio subsystem init earlier when driver model is used for serial. This simplifies the implementation. Should there be any problems with this approach they can be dealt with as boards are converted over to use driver model for serial. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 03/13] dm: Make driver model available before board_init()
On 3 September 2014 17:37, Simon Glass s...@chromium.org wrote: For some boards board_init() will change GPIOs, so we need to have driver model available before then. Adjust the board init to arrange this, but enable it for driver model only, just to be safe. This does create additional #ifdef logic, but it is safer than trying to make a pervasive change which may cause some boards to break. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 04/13] dm: tegra: Set up a pre-reloc malloc()
On 3 September 2014 17:37, Simon Glass s...@chromium.org wrote: Allocate 1KB so that driver model can operate before relocation. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 05/13] tegra: Convert tegra GPIO driver to use driver model
On 3 September 2014 17:37, Simon Glass s...@chromium.org wrote: This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature. The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices. The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc. Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 01/14] serial: Set up the 'priv' pointer when creating a serial device
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: The stdio_dev structure has a private pointer for its creator, but it is not set up by the serial system. Set it to point to the serial device so that it can be found by code called by stdio. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 02/14] dm: fdt: Add a function to look up a chosen node
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: Within /chosen we may have a node which points to another node, similar to how /aliases works. Add a helper function to do this lookup. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 03/14] dm: Adjust lists_bind_fdt() to return the bound device
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: Allow the caller to find out the device that was bound in response to this call. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 04/14] dm: Add a uclass for serial devices
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: Serial devices support simple byte input/output and a few operations to find out whether data is available. Add a basic uclass for serial devices to be used by drivers that are converted to driver model. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 05/14] sandbox: Convert serial driver to use driver model
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: Adjust the sandbox serial driver to use the new driver model uclass. The driver works much as before, but within the new framework. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 06/14] sandbox: serial: Support a coloured console
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: The current sandbox serial driver is a pretty trivial example and does not have the featues that might be needed for other board serial drivers. To help provide a better example, add a text colour property to the device tree for sandbox. This uses platform data, a device tree node, driver private data and a remove() method. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 07/14] sandbox: dts: Add a serial console node
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: If the sandbox device tree is provided to U-Boot (with the -d flag) then it will use the device tree version in preference to the built-in device. The only difference is the colour. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 10/14] dm: serial: Move baud rate calculation to ns16550.c
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 11/14] dm: serial: Collect common baud rate code in ns16550
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 12/14] dm: serial: Add driver model support for ns16550
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 13/14] tegra: dts: Add serial port details
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: Some Tegra device tree files do not include information about the serial ports. Add this and also add information about the input clock speed. The console alias needs to be set up to indicate which port is used for the console. Also add a binding file since this is missing. Series-changes; 5 - Add full serial port nodes from Linux tree (commit fc9d4dbe) - Use /chosen/stdout-path instead of /aliases/console to specify the console Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 14/14] dm: tegra: Enable driver model for serial
On 4 September 2014 16:27, Simon Glass s...@chromium.org wrote: Use driver model for serial ports. Since Tegra now uses driver model for serial, adjust the definition of V_NS16550_CLK so that it is clear that this is only used for SPL. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot-dm/master and now in mainline. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-ti/master
Hi Tom, On Thu, 18 Sep 2014 08:34:22 -0400, Tom Rini tr...@ti.com wrote: Hello, The following changes since commit c292adae170fa8c27dca75963bdb0a9afc640e57: Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' (2014-09-17 23:35:34 +0200) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to 3aae66e2a74ac89724d16b6e8908dcd0d2825eeb: am335x_evm: Add boot script support to am335x_evm (2014-09-17 21:06:56 -0400) Guillaume GARDET (2): OMAP4: Use generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage'. am335x_evm: Add boot script support to am335x_evm Murali Karicheri (1): ARM: keystone: ddr3: workaround for ddr3a/3b memory issue arch/arm/cpu/armv7/keystone/ddr3.c| 75 + arch/arm/include/asm/arch-keystone/ddr3.h |1 + arch/arm/include/asm/arch-keystone/hardware.h |2 + board/ti/ks2_evm/ddr3_k2hk.c |4 ++ include/configs/am335x_evm.h | 29 ++ include/configs/ti_omap4_common.h |4 +- 6 files changed, 102 insertions(+), 13 deletions(-) Applied to u-boot-arm/master, thanks! (still 7 boards fail building: openrd_client tricorder_flash tricorder cm_fx6 openrd_ultimate trimslice openrd_base) Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] ARM: sun6i: Add support for the new power control module found on the A31
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Oliver Schinagl oli...@schinagl.nl
To setup clocks and control voltages.
perhaps add ... For P2WI and PIO, since that is apparently what it is
doing?
HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
HdG: Make the prcm code only deal with the prcm, remove axp221 bits
I suppose these comments aren't really meaningful in the final commit
message, probably better to drop them.
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
Typo in Allwiner
+ reg_val = readl(prcm-apb0_gate);
+ reg_val |= PRCM_APB0_GATE_P2WI | PRCM_APB0_GATE_PIO;
+ writel(reg_val, prcm-apb0_gate);
+
+ reg_val = readl(prcm-apb0_reset);
+ reg_val |= PRCM_APB0_RESET_P2WI | PRCM_APB0_RESET_PIO;
+ writel(reg_val, prcm-apb0_reset);
I think these should both use the setbits helper.
Ian.
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[U-Boot] Pul request: u-boot-arm/master
Hi Tom, The following changes since commit 9170818a4e004af7893fa0113f6e5b4afafded55: kconfiglib: change SPDX-License-Identifier to ISC (2014-09-17 21:03:18 -0400) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to 2a8c9c86b92a9ccee3c27286de317e19bb0530b3: Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' (2014-09-21 16:56:44 +0200) Albert ARIBAUD (1): Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' Bo Shen (7): ARM: atmel: sama5d3xek: add nor flash init function ARM: atmel: sama5d3xek: enable NOR flash support ARM: atmel: sama5d3: add timings register ARM: atmel: use pcr to enable or disable peripheral clock ARM: atmel: add pcr related definition USB: ohci-at91: use pcr to enable or disable clock USB: ehci-atmel: use pcr to enable or disable clock Boris BREZILLON (1): mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECC Guillaume GARDET (2): OMAP4: Use generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage'. am335x_evm: Add boot script support to am335x_evm Murali Karicheri (1): ARM: keystone: ddr3: workaround for ddr3a/3b memory issue Wu, Josh (3): mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc register ARM: at91sam9n12ek: convert to generic board support ARM: at91sam9rlek: convert to generic board support arch/arm/cpu/armv7/at91/clock.c | 24 +++-- arch/arm/cpu/armv7/keystone/ddr3.c| 75 +++ arch/arm/include/asm/arch-at91/at91_pmc.h | 6 ++- arch/arm/include/asm/arch-at91/clk.h | 1 + arch/arm/include/asm/arch-at91/sama5d3.h | 1 + arch/arm/include/asm/arch-at91/sama5d3_smc.h | 3 +- arch/arm/include/asm/arch-keystone/ddr3.h | 1 + arch/arm/include/asm/arch-keystone/hardware.h | 2 + board/atmel/sama5d3xek/sama5d3xek.c | 58 + board/ti/ks2_evm/ddr3_k2hk.c | 4 ++ drivers/mtd/nand/atmel_nand.c | 22 drivers/mtd/nand/atmel_nand_ecc.h | 3 ++ drivers/usb/host/ehci-atmel.c | 8 +++ drivers/usb/host/ohci-at91.c | 8 +-- include/configs/am335x_evm.h | 29 +++ include/configs/at91sam9n12ek.h | 1 + include/configs/at91sam9rlek.h| 2 + include/configs/sama5d3xek.h | 13 - include/configs/ti_omap4_common.h | 4 +- 19 files changed, 231 insertions(+), 34 deletions(-) Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] usb: ehci: Move interrupt packet length check to create_int_queue
Hi,
On 09/20/2014 07:42 PM, Michael Trimarchi wrote:
Hi
On Sat, Sep 20, 2014 at 5:01 PM, Hans de Goede hdego...@redhat.com wrote:
Preperation patch to use create_int_queue outside of ehci-hcd.c .
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/usb/host/ehci-hcd.c | 36 +++-
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 20830d7..cf3e3c0 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1163,6 +1163,23 @@ create_int_queue(struct usb_device *dev, unsigned
long pipe, int queuesize,
struct int_queue *result = NULL;
int i;
+ /*
+* Interrupt transfers requiring several transactions are not
supported
+* because bInterval is ignored.
+*
+* Also, ehci_submit_async() relies on wMaxPacketSize being a power
of 2
+* = PKT_ALIGN if several qTDs are required, while the USB
+* specification does not constrain this for interrupt transfers.
That
+* means that ehci_submit_async() would support interrupt transfers
+* requiring several transactions only as long as the transfer size
does
+* not require more than a single qTD.
+*/
+ if (elementsize usb_maxpacket(dev, pipe)) {
+ printf(%s: xfers requiring several transactions are not
supported.\n,
+ __func__);
+ return NULL;
+ }
+
debug(Enter create_int_queue\n);
if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
debug(non-interrupt pipe (type=%lu), usb_pipetype(pipe));
@@ -1384,24 +1401,9 @@ submit_int_msg(struct usb_device *dev, unsigned long
pipe, void *buffer,
debug(dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d,
dev, pipe, buffer, length, interval);
- /*
-* Interrupt transfers requiring several transactions are not
supported
-* because bInterval is ignored.
-*
-* Also, ehci_submit_async() relies on wMaxPacketSize being a power
of 2
-* = PKT_ALIGN if several qTDs are required, while the USB
-* specification does not constrain this for interrupt transfers.
That
-* means that ehci_submit_async() would support interrupt transfers
-* requiring several transactions only as long as the transfer size
does
-* not require more than a single qTD.
-*/
- if (length usb_maxpacket(dev, pipe)) {
- printf(%s: Interrupt transfers requiring several
- transactions are not supported.\n, __func__);
- return -1;
- }
-
queue = create_int_queue(dev, pipe, 1, length, buffer);
+ if (!queue)
+ return -1;
Can you return a more consistent error code?
I'm just moving code around, and returning the same error code as before. Surely
changing the error code belongs in another patch ?
Regards,
Hans
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Re: [U-Boot] [PATCH 6/7] usb: kbd: Cache pipe, interval and packetsize
Hi,
On 09/20/2014 07:53 PM, Michael Trimarchi wrote:
Hi
On Sat, Sep 20, 2014 at 5:01 PM, Hans de Goede hdego...@redhat.com wrote:
Instead of looking them up every time we need them.
split subject and patch description
Signed-off-by: Hans de Goede hdego...@redhat.com
---
common/usb_kbd.c | 34 +-
1 file changed, 13 insertions(+), 21 deletions(-)
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index cb869ac..85ee1c8 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -99,6 +99,10 @@ static const unsigned char usb_kbd_arrow[] = {
#define USB_KBD_BOOT_REPORT_SIZE 8
struct usb_kbd_pdata {
+ unsigned long intpipe;
unsigned int intpipe ??
usb pipe-s are unsigned long everywhere in u-boot.
Regards,
Hans
Michael
+ int intpktsize;
+ int intinterval;
+
uint32_trepeat_delay;
uint32_tusb_in_pointer;
@@ -305,23 +309,11 @@ static int usb_kbd_irq(struct usb_device *dev)
static inline void usb_kbd_poll_for_event(struct usb_device *dev)
{
#ifdefined(CONFIG_SYS_USB_EVENT_POLL)
- struct usb_interface *iface;
- struct usb_endpoint_descriptor *ep;
- struct usb_kbd_pdata *data;
- int pipe;
- int maxp;
-
- /* Get the pointer to USB Keyboard device pointer */
- data = dev-privptr;
- iface = dev-config.if_desc[0];
- ep = iface-ep_desc[0];
- pipe = usb_rcvintpipe(dev, ep-bEndpointAddress);
+ struct usb_kbd_pdata *data = dev-privptr;
/* Submit a interrupt transfer request */
- maxp = usb_maxpacket(dev, pipe);
- usb_submit_int_msg(dev, pipe, data-new[0],
- min(maxp, USB_KBD_BOOT_REPORT_SIZE),
- ep-bInterval);
+ usb_submit_int_msg(dev, data-intpipe, data-new[0],
data-intpktsize,
+ data-intinterval);
usb_kbd_irq_worker(dev);
#elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP)
@@ -389,7 +381,6 @@ static int usb_kbd_probe(struct usb_device *dev,
unsigned int ifnum)
struct usb_interface *iface;
struct usb_endpoint_descriptor *ep;
struct usb_kbd_pdata *data;
- int pipe, maxp;
if (dev-descriptor.bNumConfigurations != 1)
return 0;
@@ -438,8 +429,10 @@ static int usb_kbd_probe(struct usb_device *dev,
unsigned int ifnum)
/* Set IRQ handler */
dev-irq_handle = usb_kbd_irq;
- pipe = usb_rcvintpipe(dev, ep-bEndpointAddress);
- maxp = usb_maxpacket(dev, pipe);
+ data-intpipe = usb_rcvintpipe(dev, ep-bEndpointAddress);
+ data-intpktsize = min(usb_maxpacket(dev, data-intpipe),
+ USB_KBD_BOOT_REPORT_SIZE);
+ data-intinterval = ep-bInterval;
/* We found a USB Keyboard, install it. */
usb_set_protocol(dev, iface-desc.bInterfaceNumber, 0);
@@ -448,9 +441,8 @@ static int usb_kbd_probe(struct usb_device *dev,
unsigned int ifnum)
usb_set_idle(dev, iface-desc.bInterfaceNumber, REPEAT_RATE, 0);
debug(USB KBD: enable interrupt pipe...\n);
- if (usb_submit_int_msg(dev, pipe, data-new,
- min(maxp, USB_KBD_BOOT_REPORT_SIZE),
- ep-bInterval) 0) {
+ if (usb_submit_int_msg(dev, data-intpipe, data-new,
data-intpktsize,
+ data-intinterval) 0) {
printf(Failed to get keyboard state from device
%04x:%04x\n,
dev-descriptor.idVendor, dev-descriptor.idProduct);
/* Abort, we don't want to use that non-functional keyboard.
*/
--
2.1.0
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Re: [U-Boot] [PATCH 4/7] ARM: sun6i: Add clock support
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote: +#ifdef CONFIG_SPL_BUILD Since there is no SPL support this is dead code right now, correct? I'm wondering whether we should leave it out of mainline until the SPL stuff is done, so SPL will be upstreamed all at once. What do others think? + /* Set PLL ldo voltage without this PLL6 does not work properly */ Is this here the doing it 3 times bit? If that's deliberate then please say so explicitly. e.g. Set PLL LDO voltage 3 times, without ... etc), if it's not deliberate then please fix ;-) I'm assuming this is one of those no docs, allwinner code did it but nobody knows why it works scenarios. Of course if the reason is known/doc'd then please add a reference. + writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) | + PRCM_PLL_CTRL_LDO_KEY, prcm-pll_ctrl1); + writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) | + PRCM_PLL_CTRL_LDO_KEY, prcm-pll_ctrl1); + writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140), + prcm-pll_ctrl1); [...] Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/7] ARM: sunxi-mmc: Add mmc support for sun6i / A31
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdego...@redhat.com
Signed-off-by: Hans de Goede hdego...@redhat.com
[w...@csie.org: use setbits_le32 for reset control, drop obsolete changes,
squash sunxi-mmc: sun6i has its fifo at a different address]
Signed-off-by: Chen-Yu Tsai w...@csie.org
Adding CC to Pantelis (MMC custodian).
Pantelis, once you are happy with this I propose we take this via the
sunxi tree along with the rest of the series.
For my part I only have nitpicks:
---
arch/arm/include/asm/arch-sunxi/mmc.h | 2 --
drivers/mmc/sunxi_mmc.c | 9 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h
b/arch/arm/include/asm/arch-sunxi/mmc.h
index 53196e3..bafde4b 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -42,8 +42,6 @@ struct sunxi_mmc {
u32 idie; /* 0x8c internal DMA interrupt enable */
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
- u32 res1[26];
- u32 fifo; /* 0x100 FIFO access address */
This seems unrelated to the stated purpose of the commit, should
probably be a separate cleanup.
};
#define SUNXI_MMC_CLK_POWERSAVE (0x1 17)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index d4e574f..b035bba 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -57,7 +57,11 @@ static int mmc_resource_init(int sdc_no)
printf(Wrong mmc number %d\n, sdc_no);
return -1;
}
+#ifdef CONFIG_SUN6I
+ mmchost-database = (unsigned int)mmchost-reg + 0x200;
+#else
mmchost-database = (unsigned int)mmchost-reg + 0x100;
+#endif
Adding a #define to ./include/configs/sun?i.h would be preferred, I
think.
Ian.
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Re: [U-Boot] [PATCH 6/7] ARM: sun6i: Setup the A31 UART0 muxing
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote: From: Maxime Ripard maxime.rip...@free-electrons.com Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com Signed-off-by: Hans de Goede hdego...@redhat.com [w...@csie.org: commit message was ARM: sunxi: Setup the A31 UART0 muxing] Signed-off-by: Chen-Yu Tsai w...@csie.org Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/7] ARM: sunxi: Add basic A31 support
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote: From: Maxime Ripard maxime.rip...@free-electrons.com Add a new sun6i machine that doesn't do much for now. Can you briefly outline here what it _does_ do, please. The actual code looks ok to me. There is some possibility we might consolidate some of these Kconfig options, or at least move them to the sunxi Kconfig. We can cross the bridge when we come to it though. Any links to some info about the Colombus? Is it the WITS development kit which google found for me? Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/7] ARM: sunxi: Add basic A31 support
Hi Ian, On Sun, Sep 21, 2014 at 07:51:17PM +0100, Ian Campbell wrote: On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote: From: Maxime Ripard maxime.rip...@free-electrons.com Add a new sun6i machine that doesn't do much for now. Can you briefly outline here what it _does_ do, please. When I contributed this patch, it was only having the UART support, but judging from the rest of the patches Chen-Yu sent, I guess it does a bit more than that now, especially MMC. The actual code looks ok to me. There is some possibility we might consolidate some of these Kconfig options, or at least move them to the sunxi Kconfig. We can cross the bridge when we come to it though. Any links to some info about the Colombus? Is it the WITS development kit which google found for me? It is. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] usb: ehci: Move interrupt packet length check to create_int_queue
On Sunday, September 21, 2014 at 07:53:35 PM, Hans de Goede wrote:
Hi,
[...]
- if (length usb_maxpacket(dev, pipe)) {
- printf(%s: Interrupt transfers requiring several
- transactions are not supported.\n, __func__);
- return -1;
- }
-
queue = create_int_queue(dev, pipe, 1, length, buffer);
+ if (!queue)
+ return -1;
Can you return a more consistent error code?
I'm just moving code around, and returning the same error code as before.
Surely changing the error code belongs in another patch ?
Yes, full ACK. This is exactly a prime examply where squashing two fixes into
one patch would break bisectability absolutely perfectly.
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 2/7] usb: ehci: Move interrupt packet length check to create_int_queue
Hi Marek
On Sun, Sep 21, 2014 at 9:36 PM, Marek Vasut ma...@denx.de wrote:
On Sunday, September 21, 2014 at 07:53:35 PM, Hans de Goede wrote:
Hi,
[...]
- if (length usb_maxpacket(dev, pipe)) {
- printf(%s: Interrupt transfers requiring several
- transactions are not supported.\n, __func__);
- return -1;
- }
-
queue = create_int_queue(dev, pipe, 1, length, buffer);
+ if (!queue)
+ return -1;
Can you return a more consistent error code?
I'm just moving code around, and returning the same error code as before.
Surely changing the error code belongs in another patch ?
Yes, full ACK. This is exactly a prime examply where squashing two fixes into
one patch would break bisectability absolutely perfectly.
Agree on separated patch, I have just ask if Hans can do in the
patches queue. Marek, thanks for the lesson. Anyway seems that in USB
part we have already several -1 return.
Michael
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 2/7] usb: ehci: Move interrupt packet length check to create_int_queue
On Sunday, September 21, 2014 at 10:00:24 PM, Michael Trimarchi wrote:
Hi Marek
On Sun, Sep 21, 2014 at 9:36 PM, Marek Vasut ma...@denx.de wrote:
On Sunday, September 21, 2014 at 07:53:35 PM, Hans de Goede wrote:
Hi,
[...]
- if (length usb_maxpacket(dev, pipe)) {
- printf(%s: Interrupt transfers requiring several
- transactions are not supported.\n,
__func__); - return -1;
- }
-
queue = create_int_queue(dev, pipe, 1, length, buffer);
+ if (!queue)
+ return -1;
Can you return a more consistent error code?
I'm just moving code around, and returning the same error code as
before. Surely changing the error code belongs in another patch ?
Yes, full ACK. This is exactly a prime examply where squashing two fixes
into one patch would break bisectability absolutely perfectly.
Agree on separated patch, I have just ask if Hans can do in the
patches queue. Marek, thanks for the lesson. Anyway seems that in USB
part we have already several -1 return.
You know how it goes, patches are welcome ;-)
Best regards,
Marek Vasut
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