[U-Boot] [PATCH 1/5] ARM: uniphier: set DTB file name to fdt_file environment

[Masahiro Yamada]

When we want to boot Linux with a DTB file downloaded from a TFTP
server or somewhere, we need to know the file name to be downloaded.

Assume the U-Boot configuration is shared among some similar boards.
If they are similar enough, the difference only appears in device
trees.  The build procedure would be like this:

 - Board A:  make foo_common_defconfig && make DEVICE_TREE=foo_board_a
 - Board B:  make foo_common_defconfig && make DEVICE_TREE=foo_board_b
 - Board C:  make foo_common_defconfig && make DEVICE_TREE=foo_board_c

In this case, the U-Boot image contains nothing about the DTB file name
it is running with.  (CONFIG_DEFAULT_DEVICE_TREE is not helpful for this
purpose because it is painful to change it from "make menuconfig" for
each board.)

This commit allows to lookup the DTB file name based on the compatible
string and set it to "fdt_file" environment.  Then "tftpboot $fdt_file"
will download the file we want.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/board_late_init.c | 35 
 1 file changed, 35 insertions(+)

diff --git a/arch/arm/mach-uniphier/board_late_init.c 
b/arch/arm/mach-uniphier/board_late_init.c
index a7530eb..c2a3261 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include <../drivers/mtd/nand/denali.h>
@@ -25,6 +26,38 @@ static void nand_denali_wp_disable(void)
 #endif
 }
 
+struct uniphier_fdt_file {
+   const char *compatible;
+   const char *file_name;
+};
+
+static const struct uniphier_fdt_file uniphier_fdt_files[] = {
+   { "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", },
+   { "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", },
+   { "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", },
+   { "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", },
+   { "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", },
+   { "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", },
+   { "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", },
+   { "socionext,proxstream2-gentil", "uniphier-proxstream2-gentil.dtb", },
+   { "socionext,proxstream2-vodka", "uniphier-proxstream2-vodka.dtb", },
+};
+
+static void uniphier_set_fdt_file(void)
+{
+   DECLARE_GLOBAL_DATA_PTR;
+   int i;
+
+   /* lookup DTB file name based on the compatible string */
+   for (i = 0; i < ARRAY_SIZE(uniphier_fdt_files); i++) {
+   if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+   uniphier_fdt_files[i].compatible)) {
+   setenv("fdt_file", uniphier_fdt_files[i].file_name);
+   return;
+   }
+   }
+}
+
 int board_late_init(void)
 {
puts("MODE:  ");
@@ -48,5 +81,7 @@ int board_late_init(void)
return -1;
}
 
+   uniphier_set_fdt_file();
+
return 0;
 }
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] image: check "bootm_low" and "bootm_size" if "initrd_high" is missing

[Masahiro Yamada]

To boot Linux, we should prevent Initramdisk and FDT from going too
high.

Currently, boot_relocate_fdt() checks "fdt_high" environment first,
and then falls back to getenv_bootm_mapsize() + getenv_bootm_low()
if "fdt_high" is missing.

On the other hand, boot_ramdisk_high() only checks "initrd_high" to
get the address limit for the Initramdisk.  We also want to let this
case fall back to getenv_bootm_mapsize() + getenv_bootm_low().

Signed-off-by: Masahiro Yamada 
---

 common/image.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/common/image.c b/common/image.c
index c36927f..d63d9e0 100644
--- a/common/image.c
+++ b/common/image.c
@@ -1113,8 +1113,7 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, 
ulong rd_len,
if (initrd_high == ~0)
initrd_copy_to_ram = 0;
} else {
-   /* not set, no restrictions to load high */
-   initrd_high = ~0;
+   initrd_high = getenv_bootm_mapsize() + getenv_bootm_low();
}
 
 
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 2/7] ARM: uniphier: call uniphier_get_board_param() without FDT blob

[Masahiro Yamada]

Move "gd->fdt_blob" from the caller to the callee so that this
function can be used more easily.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/boards.c| 7 +--
 arch/arm/mach-uniphier/include/mach/init.h | 2 +-
 arch/arm/mach-uniphier/init/init.c | 4 +---
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index 812c58f..f328143 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -4,10 +4,13 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#include 
 #include 
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
 static const struct uniphier_board_data ph1_sld3_data = {
.dram_ch0_base  = 0x8000,
@@ -116,12 +119,12 @@ static const struct uniphier_board_id uniphier_boards[] = 
{
 #endif
 };
 
-const struct uniphier_board_data *uniphier_get_board_param(const void *fdt)
+const struct uniphier_board_data *uniphier_get_board_param(void)
 {
int i;
 
for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) {
-   if (!fdt_node_check_compatible(fdt, 0,
+   if (!fdt_node_check_compatible(gd->fdt_blob, 0,
   uniphier_boards[i].compatible))
return uniphier_boards[i].param;
}
diff --git a/arch/arm/mach-uniphier/include/mach/init.h 
b/arch/arm/mach-uniphier/include/mach/init.h
index 5108edd..27ae27d 100644
--- a/arch/arm/mach-uniphier/include/mach/init.h
+++ b/arch/arm/mach-uniphier/include/mach/init.h
@@ -20,7 +20,7 @@ struct uniphier_board_data {
unsigned int  dram_freq;
 };
 
-const struct uniphier_board_data *uniphier_get_board_param(const void *fdt);
+const struct uniphier_board_data *uniphier_get_board_param(void);
 
 int ph1_sld3_init(const struct uniphier_board_data *bd);
 int ph1_ld4_init(const struct uniphier_board_data *bd);
diff --git a/arch/arm/mach-uniphier/init/init.c 
b/arch/arm/mach-uniphier/init/init.c
index bbfc8e5..eda169e 100644
--- a/arch/arm/mach-uniphier/init/init.c
+++ b/arch/arm/mach-uniphier/init/init.c
@@ -9,13 +9,11 @@
 #include 
 #include 
 
-DECLARE_GLOBAL_DATA_PTR;
-
 void spl_board_init(void)
 {
const struct uniphier_board_data *param;
 
-   param = uniphier_get_board_param(gd->fdt_blob);
+   param = uniphier_get_board_param();
if (!param)
hang();
 
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 0/7] ARM: uniphier: misc changes for v2016.01-rc3

[Masahiro Yamada]

Masahiro Yamada (7):
  ARM: uniphier: add functions to get SoC model/revision
  ARM: uniphier: call uniphier_get_board_param() without FDT blob
  ARM: uniphier: split ProXstream2 board data and change DDR frequency
  ARM: uniphier: compile uniphier_get_board_param() for U-Boot proper
  ARM: uniphier: add macros and revision code for sLD11 and LD10
  ARM: uniphier: display model number all the time on boot up
  ARM: uniphier: merge umc/ and ddrphy/ into a single directory

 arch/arm/mach-uniphier/Makefile|  4 ++--
 arch/arm/mach-uniphier/boards.c| 27 ++
 arch/arm/mach-uniphier/cpu_info.c  |  9 ++--
 arch/arm/mach-uniphier/ddrphy/Makefile |  7 --
 arch/arm/mach-uniphier/dram/Makefile   | 10 
 .../{ddrphy => dram}/ddrphy-ph1-ld4.c  |  0
 .../{ddrphy => dram}/ddrphy-ph1-pro4.c |  0
 .../{ddrphy => dram}/ddrphy-ph1-sld8.c |  0
 .../{ddrphy => dram}/ddrphy-training.c |  0
 arch/arm/mach-uniphier/{umc => dram}/umc-ph1-ld4.c |  0
 .../arm/mach-uniphier/{umc => dram}/umc-ph1-pro4.c |  0
 .../arm/mach-uniphier/{umc => dram}/umc-ph1-sld8.c |  0
 arch/arm/mach-uniphier/include/mach/init.h |  2 +-
 arch/arm/mach-uniphier/include/mach/soc_info.h | 15 +++-
 arch/arm/mach-uniphier/init/init.c |  4 +---
 arch/arm/mach-uniphier/soc_info.c  | 22 ++
 arch/arm/mach-uniphier/umc/Makefile|  7 --
 17 files changed, 79 insertions(+), 28 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/ddrphy/Makefile
 create mode 100644 arch/arm/mach-uniphier/dram/Makefile
 rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-ld4.c (100%)
 rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-pro4.c (100%)
 rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-sld8.c (100%)
 rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-training.c (100%)
 rename arch/arm/mach-uniphier/{umc => dram}/umc-ph1-ld4.c (100%)
 rename arch/arm/mach-uniphier/{umc => dram}/umc-ph1-pro4.c (100%)
 rename arch/arm/mach-uniphier/{umc => dram}/umc-ph1-sld8.c (100%)
 delete mode 100644 arch/arm/mach-uniphier/umc/Makefile

-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 4/7] ARM: uniphier: compile uniphier_get_board_param() for U-Boot proper

[Masahiro Yamada]

Compile this file for U-Boot proper as well as SPL, so that the
U-Boot proper can call uniphier_get_board_param().

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index b597a13..86929a2 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -6,7 +6,6 @@ ifdef CONFIG_SPL_BUILD
 
 obj-y += lowlevel_init.o
 obj-y += init_page_table.o
-obj-y += boards.o
 
 obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
@@ -33,6 +32,7 @@ obj-y += pinctrl/ clk/
 endif
 
 obj-y += timer.o
+obj-y += boards.o
 obj-y += soc_info.o
 obj-y += boot-mode/
 
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/7] ARM: uniphier: add functions to get SoC model/revision

[Masahiro Yamada]

We sometimes have to implement different code depending on the SoC
revision.  This commit adds functions to get the model/revision
number.

Note:
  Model number: incremented on major changes of the SoC
  Revision number: incremented on minor changes of the SoC

The "Model 2" exists for PH1-sLD3, ProXstream2/PH1-LD6b.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/include/mach/soc_info.h |  3 +++
 arch/arm/mach-uniphier/soc_info.c  | 12 
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/mach-uniphier/include/mach/soc_info.h 
b/arch/arm/mach-uniphier/include/mach/soc_info.h
index 623e7ef..6e25baa 100644
--- a/arch/arm/mach-uniphier/include/mach/soc_info.h
+++ b/arch/arm/mach-uniphier/include/mach/soc_info.h
@@ -60,4 +60,7 @@ static inline enum uniphier_soc_id uniphier_get_soc_type(void)
 }
 #endif
 
+int uniphier_get_soc_model(void);
+int uniphier_get_soc_revision(void);
+
 #endif /* __MACH_SOC_INFO_H__ */
diff --git a/arch/arm/mach-uniphier/soc_info.c 
b/arch/arm/mach-uniphier/soc_info.c
index 3e8e7f4..a4010eb 100644
--- a/arch/arm/mach-uniphier/soc_info.c
+++ b/arch/arm/mach-uniphier/soc_info.c
@@ -59,3 +59,15 @@ enum uniphier_soc_id uniphier_get_soc_type(void)
return ret;
 }
 #endif
+
+int uniphier_get_soc_model(void)
+{
+   return (readl(SG_REVISION) & SG_REVISION_MODEL_MASK) >>
+   SG_REVISION_MODEL_SHIFT;
+}
+
+int uniphier_get_soc_revision(void)
+{
+   return (readl(SG_REVISION) & SG_REVISION_REV_MASK) >>
+   SG_REVISION_REV_SHIFT;
+}
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 3/7] ARM: uniphier: split ProXstream2 board data and change DDR frequency

[Masahiro Yamada]

The DDR3 memory chips on ProXstream2 boards support up to 2133 MHz,
while only up to 1866MHz on PH1-LD6b boards.

Split the board data structure and change the DDR frequency of
ProXstream2 boards to 2133 MHz.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/boards.c | 20 +---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index f328143..d075a11 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -74,8 +74,7 @@ static const struct uniphier_board_data ph1_pro5_data = {
 };
 #endif
 
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
-   defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
 static const struct uniphier_board_data proxstream2_data = {
.dram_ch0_base  = 0x8000,
.dram_ch0_size  = 0x4000,
@@ -86,6 +85,21 @@ static const struct uniphier_board_data proxstream2_data = {
.dram_ch2_base  = 0xe000,
.dram_ch2_size  = 0x2000,
.dram_ch2_width = 16,
+   .dram_freq  = 2133,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+static const struct uniphier_board_data ph1_ld6b_data = {
+   .dram_ch0_base  = 0x8000,
+   .dram_ch0_size  = 0x4000,
+   .dram_ch0_width = 32,
+   .dram_ch1_base  = 0xc000,
+   .dram_ch1_size  = 0x2000,
+   .dram_ch1_width = 32,
+   .dram_ch2_base  = 0xe000,
+   .dram_ch2_size  = 0x2000,
+   .dram_ch2_width = 16,
.dram_freq  = 1866,
 };
 #endif
@@ -115,7 +129,7 @@ static const struct uniphier_board_id uniphier_boards[] = {
{ "socionext,proxstream2", _data, },
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
-   { "socionext,ph1-ld6b", _data, },
+   { "socionext,ph1-ld6b", _ld6b_data, },
 #endif
 };
 
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 0/5] ARM: uniphier: consolidate defconfig files

[Masahiro Yamada]

Masahiro Yamada (5):
  ARM: uniphier: set DTB file name to fdt_file environment
  ARM: uniphier: drop fdt_file from CONFIG_EXTRA_ENV_SETTINGS
  ARM: uniphier: merge ph1_ld4_defconfig and ph1_sld8_defconfig
  ARM: uniphier: support ProXstream2, PH1-LD6b boards in single
defconfig
  ARM: uniphier: rename defconfig files

 MAINTAINERS|  2 +-
 arch/arm/mach-uniphier/board_late_init.c   | 35 +
 configs/ph1_sld8_defconfig | 30 --
 ...1_ld4_defconfig => uniphier_ld4_sld8_defconfig} |  1 +
 ...{ph1_pro4_defconfig => uniphier_pro4_defconfig} |  0
 ...{ph1_pro5_defconfig => uniphier_pro5_defconfig} |  0
 ...ld6b_defconfig => uniphier_pxs2_ld6b_defconfig} |  3 +-
 ...{ph1_sld3_defconfig => uniphier_sld3_defconfig} |  0
 doc/README.uniphier| 36 --
 include/configs/uniphier.h |  1 -
 10 files changed, 59 insertions(+), 49 deletions(-)
 delete mode 100644 configs/ph1_sld8_defconfig
 rename configs/{ph1_ld4_defconfig => uniphier_ld4_sld8_defconfig} (95%)
 rename configs/{ph1_pro4_defconfig => uniphier_pro4_defconfig} (100%)
 rename configs/{ph1_pro5_defconfig => uniphier_pro5_defconfig} (100%)
 rename configs/{ph1_ld6b_defconfig => uniphier_pxs2_ld6b_defconfig} (88%)
 rename configs/{ph1_sld3_defconfig => uniphier_sld3_defconfig} (100%)

-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 6/7] ARM: uniphier: display model number all the time on boot up

[Masahiro Yamada]

Both "Model 1" and "Model 2" are supported for ProXstream2 and
PH1-LD6b boards.  It is useful to show the model number in the
boot banner.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/cpu_info.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/mach-uniphier/cpu_info.c 
b/arch/arm/mach-uniphier/cpu_info.c
index acfb06d..935b209 100644
--- a/arch/arm/mach-uniphier/cpu_info.c
+++ b/arch/arm/mach-uniphier/cpu_info.c
@@ -54,8 +54,7 @@ int print_cpuinfo(void)
return -1;
}
 
-   if (model > 1)
-   printf(" model %d", model);
+   printf(" model %d", model);
 
printf(" (rev. %d)\n", rev);
 
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 7/7] ARM: uniphier: merge umc/ and ddrphy/ into a single directory

[Masahiro Yamada]

The UMC (Universal Memory Controller) and the DDR PHY block are
highly related to each other.  It is better to have both code in the
same directory.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Makefile   |  2 +-
 arch/arm/mach-uniphier/ddrphy/Makefile|  7 ---
 arch/arm/mach-uniphier/dram/Makefile  | 10 ++
 arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-ld4.c  |  0
 arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-pro4.c |  0
 arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-sld8.c |  0
 arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-training.c |  0
 arch/arm/mach-uniphier/{umc => dram}/umc-ph1-ld4.c|  0
 arch/arm/mach-uniphier/{umc => dram}/umc-ph1-pro4.c   |  0
 arch/arm/mach-uniphier/{umc => dram}/umc-ph1-sld8.c   |  0
 arch/arm/mach-uniphier/umc/Makefile   |  7 ---
 11 files changed, 11 insertions(+), 15 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/ddrphy/Makefile
 create mode 100644 arch/arm/mach-uniphier/dram/Makefile
 rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-ld4.c (100%)
 rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-pro4.c (100%)
 rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-sld8.c (100%)
 rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-training.c (100%)
 rename arch/arm/mach-uniphier/{umc => dram}/umc-ph1-ld4.c (100%)
 rename arch/arm/mach-uniphier/{umc => dram}/umc-ph1-pro4.c (100%)
 rename arch/arm/mach-uniphier/{umc => dram}/umc-ph1-sld8.c (100%)
 delete mode 100644 arch/arm/mach-uniphier/umc/Makefile

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 86929a2..5b19f93 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -7,7 +7,7 @@ ifdef CONFIG_SPL_BUILD
 obj-y += lowlevel_init.o
 obj-y += init_page_table.o
 
-obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/
+obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ dram/
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
 
 obj-$(CONFIG_DEBUG_LL) += debug_ll.o
diff --git a/arch/arm/mach-uniphier/ddrphy/Makefile 
b/arch/arm/mach-uniphier/ddrphy/Makefile
deleted file mode 100644
index d0f4bd3..000
--- a/arch/arm/mach-uniphier/ddrphy/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)+= ddrphy-training.o ddrphy-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)   += ddrphy-training.o ddrphy-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)   += ddrphy-training.o ddrphy-ph1-sld8.o
diff --git a/arch/arm/mach-uniphier/dram/Makefile 
b/arch/arm/mach-uniphier/dram/Makefile
new file mode 100644
index 000..d3a767b
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/Makefile
@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)+= umc-ph1-ld4.o \
+  ddrphy-training.o ddrphy-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)   += umc-ph1-pro4.o \
+  ddrphy-training.o ddrphy-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)   += umc-ph1-sld8.o \
+  ddrphy-training.o ddrphy-ph1-sld8.o
diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c 
b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
similarity index 100%
rename from arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c
rename to arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c 
b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
similarity index 100%
rename from arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c
rename to arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c 
b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
similarity index 100%
rename from arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c
rename to arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c 
b/arch/arm/mach-uniphier/dram/ddrphy-training.c
similarity index 100%
rename from arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
rename to arch/arm/mach-uniphier/dram/ddrphy-training.c
diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c 
b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
similarity index 100%
rename from arch/arm/mach-uniphier/umc/umc-ph1-ld4.c
rename to arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c 
b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
similarity index 100%
rename from arch/arm/mach-uniphier/umc/umc-ph1-pro4.c
rename to arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c 
b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
similarity index 100%
rename from arch/arm/mach-uniphier/umc/umc-ph1-sld8.c
rename to 

[U-Boot] [PATCH 5/7] ARM: uniphier: add macros and revision IDs for sLD11 and LD10

[Masahiro Yamada]

These are new SoCs from Socionext Inc.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/cpu_info.c  |  6 ++
 arch/arm/mach-uniphier/include/mach/soc_info.h | 12 +++-
 arch/arm/mach-uniphier/soc_info.c  | 10 ++
 3 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-uniphier/cpu_info.c 
b/arch/arm/mach-uniphier/cpu_info.c
index 5d9ed84..acfb06d 100644
--- a/arch/arm/mach-uniphier/cpu_info.c
+++ b/arch/arm/mach-uniphier/cpu_info.c
@@ -43,6 +43,12 @@ int print_cpuinfo(void)
case 0x2F:
puts("PH1-LD6b (MN2WS0320)");
break;
+   case 0x31:
+   puts("PH1-sLD11 ()");
+   break;
+   case 0x32:
+   puts("PH1-LD10 ()");
+   break;
default:
printf("Unknown Processor ID (0x%x)\n", revision);
return -1;
diff --git a/arch/arm/mach-uniphier/include/mach/soc_info.h 
b/arch/arm/mach-uniphier/include/mach/soc_info.h
index 6e25baa..3cfd1e9 100644
--- a/arch/arm/mach-uniphier/include/mach/soc_info.h
+++ b/arch/arm/mach-uniphier/include/mach/soc_info.h
@@ -15,6 +15,8 @@ enum uniphier_soc_id {
SOC_UNIPHIER_PH1_PRO5,
SOC_UNIPHIER_PROXSTREAM2,
SOC_UNIPHIER_PH1_LD6B,
+   SOC_UNIPHIER_PH1_SLD11,
+   SOC_UNIPHIER_PH1_LD10,
SOC_UNIPHIER_UNKNOWN,
 };
 
@@ -25,7 +27,9 @@ enum uniphier_soc_id {
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) +  \
-   IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+   IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + \
+   IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD11) + \
+   IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD10)
 
 #define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1)
 
@@ -55,6 +59,12 @@ static inline enum uniphier_soc_id 
uniphier_get_soc_type(void)
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
return SOC_UNIPHIER_PH1_LD6B;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD11)
+   return SOC_UNIPHIER_PH1_SLD11;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD10)
+   return SOC_UNIPHIER_PH1_LD10;
+#endif
 
return SOC_UNIPHIER_UNKNOWN;
 }
diff --git a/arch/arm/mach-uniphier/soc_info.c 
b/arch/arm/mach-uniphier/soc_info.c
index a4010eb..6cdeae6 100644
--- a/arch/arm/mach-uniphier/soc_info.c
+++ b/arch/arm/mach-uniphier/soc_info.c
@@ -51,6 +51,16 @@ enum uniphier_soc_id uniphier_get_soc_type(void)
ret = SOC_UNIPHIER_PH1_LD6B;
break;
 #endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD11
+   case 0x31:
+   ret = SOC_UNIPHIER_PH1_SLD11;
+   break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD10
+   case 0x32:
+   ret = SOC_UNIPHIER_PH1_LD10;
+   break;
+#endif
default:
ret = SOC_UNIPHIER_UNKNOWN;
break;
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 2/5] ARM: uniphier: drop fdt_file from CONFIG_EXTRA_ENV_SETTINGS

[Masahiro Yamada]

Now this environment is run-time set to the DTB name U-Boot is really
running with.  Drop the static define.

Signed-off-by: Masahiro Yamada 
---

 include/configs/uniphier.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 0562598..b1106de 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -193,7 +193,6 @@
"fdt_addr=0x0010\0" \
"fdt_addr_r=0x8410\0" \
"fdt_size=0x8000\0" \
-   "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"kernel_addr=0x0020\0" \
"kernel_addr_r=0x8420\0" \
"kernel_size=0x0080\0" \
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 4/5] ARM: uniphier: support ProXstream2, PH1-LD6b boards in single defconfig

[Masahiro Yamada]

These boards are similar enough to be supported in a single defconfig
file.  Distinguish one from another by "DEVICE_TREE" from the command
line.  The how-to-build in doc/README.uniphier should be also updated.

Signed-off-by: Masahiro Yamada 
---

 .../{ph1_ld6b_defconfig => uniphier_pxs2_ld6b_defconfig}   |  3 ++-
 doc/README.uniphier| 14 +-
 2 files changed, 11 insertions(+), 6 deletions(-)
 rename configs/{ph1_ld6b_defconfig => uniphier_pxs2_ld6b_defconfig} (88%)

diff --git a/configs/ph1_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig
similarity index 88%
rename from configs/ph1_ld6b_defconfig
rename to configs/uniphier_pxs2_ld6b_defconfig
index bbcb344..f8cb794 100644
--- a/configs/ph1_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -1,10 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PROXSTREAM2=y
 CONFIG_ARCH_UNIPHIER_PH1_LD6B=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x8400
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld6b-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
diff --git a/doc/README.uniphier b/doc/README.uniphier
index 68cc05d..7562e6f 100644
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@@ -48,14 +48,18 @@ PH1-Pro5:
 $ make ph1_pro5_defconfig
 $ make CROSS_COMPILE=arm-linux-gnueabi-
 
-ProXstream2:
-$ make pxs2_defconfig
-$ make CROSS_COMPILE=arm-linux-gnueabi-
+ProXstream2 Gentil board:
+$ make uniphier_pxs2_ld6b_defconfig
+$ make CROSS_COMPILE=arm-linux-gnueabi- 
DEVICE_TREE=uniphier-proxstream2-gentil
 
-PH1-LD6b:
-$ make ph1_ld6b_defconfig
+ProXstream2 Vodka board:
+$ make uniphier_pxs2_ld6b_defconfig
 $ make CROSS_COMPILE=arm-linux-gnueabi-
 
+PH1-LD6b reference board:
+$ make uniphier_pxs2_ld6b_defconfig
+$ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld6b-ref
+
 You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-"
 to use your favorite compiler.
 
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] who is official MAINTAINER for MPC83xx?

[Robert P. J. Day]

  i CCed alleged MPC83xx maintainer kim.phill...@freescale.com
yesterday on my patch, but that CC bounced with "unknown user" error,
is there a newer maintainer for that platform?

rday

-- 


Robert P. J. Day Ottawa, Ontario, CANADA
http://crashcourse.ca

Twitter:   http://twitter.com/rpjday
LinkedIn:   http://ca.linkedin.com/in/rpjday


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 5/5] ARM: uniphier: rename rest of defconfig files

[Masahiro Yamada]

Rename rest of defconfig files of UniPhier SoC family to have the
prefix uniphier_.

Signed-off-by: Masahiro Yamada 
---

 MAINTAINERS |  1 -
 configs/{ph1_pro4_defconfig => uniphier_pro4_defconfig} |  0
 configs/{ph1_pro5_defconfig => uniphier_pro5_defconfig} |  0
 configs/{ph1_sld3_defconfig => uniphier_sld3_defconfig} |  0
 doc/README.uniphier | 12 ++--
 5 files changed, 6 insertions(+), 7 deletions(-)
 rename configs/{ph1_pro4_defconfig => uniphier_pro4_defconfig} (100%)
 rename configs/{ph1_pro5_defconfig => uniphier_pro5_defconfig} (100%)
 rename configs/{ph1_sld3_defconfig => uniphier_sld3_defconfig} (100%)

diff --git a/MAINTAINERS b/MAINTAINERS
index 18d8fce..5b3c93a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -161,7 +161,6 @@ M:  Masahiro Yamada 
 S: Maintained
 T: git git://git.denx.de/u-boot-uniphier.git
 F: arch/arm/mach-uniphier/
-F: configs/ph1_*_defconfig
 F: configs/uniphier_*_defconfig
 N: uniphier
 
diff --git a/configs/ph1_pro4_defconfig b/configs/uniphier_pro4_defconfig
similarity index 100%
rename from configs/ph1_pro4_defconfig
rename to configs/uniphier_pro4_defconfig
diff --git a/configs/ph1_pro5_defconfig b/configs/uniphier_pro5_defconfig
similarity index 100%
rename from configs/ph1_pro5_defconfig
rename to configs/uniphier_pro5_defconfig
diff --git a/configs/ph1_sld3_defconfig b/configs/uniphier_sld3_defconfig
similarity index 100%
rename from configs/ph1_sld3_defconfig
rename to configs/uniphier_sld3_defconfig
diff --git a/doc/README.uniphier b/doc/README.uniphier
index 7562e6f..f0f5346 100644
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@@ -28,8 +28,8 @@ Tested toolchains
 Compile the source
 --
 
-PH1-sLD3:
-$ make ph1_sld3_defconfig
+PH1-sLD3 reference board:
+$ make uniphier_sld3_defconfig
 $ make CROSS_COMPILE=arm-linux-gnueabi-
 
 PH1-LD4 reference board:
@@ -40,12 +40,12 @@ PH1-sLD8 reference board:
 $ make uniphier_ld4_sld8_defconfig
 $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-sld8-ref
 
-PH1-Pro4:
-$ make ph1_pro4_defconfig
+PH1-Pro4 reference board:
+$ make uniphier_pro4_defconfig
 $ make CROSS_COMPILE=arm-linux-gnueabi-
 
-PH1-Pro5:
-$ make ph1_pro5_defconfig
+PH1-Pro5 4KBOX Board:
+$ make uniphier_pro5_defconfig
 $ make CROSS_COMPILE=arm-linux-gnueabi-
 
 ProXstream2 Gentil board:
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 3/5] ARM: uniphier: merge ph1_ld4_defconfig and ph1_sld8_defconfig

[Masahiro Yamada]

These two are similar enough to be merged into a single
defconfig file.  Distinguish one from another by "DEVICE_TREE"
from the command line.  The how-to-build in doc/README.uniphier
should be also updated.

Signed-off-by: Masahiro Yamada 
---

 MAINTAINERS|  1 +
 configs/ph1_sld8_defconfig | 30 --
 ...1_ld4_defconfig => uniphier_ld4_sld8_defconfig} |  1 +
 doc/README.uniphier| 12 -
 4 files changed, 8 insertions(+), 36 deletions(-)
 delete mode 100644 configs/ph1_sld8_defconfig
 rename configs/{ph1_ld4_defconfig => uniphier_ld4_sld8_defconfig} (95%)

diff --git a/MAINTAINERS b/MAINTAINERS
index 394be1e..18d8fce 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -162,6 +162,7 @@ S:  Maintained
 T: git git://git.denx.de/u-boot-uniphier.git
 F: arch/arm/mach-uniphier/
 F: configs/ph1_*_defconfig
+F: configs/uniphier_*_defconfig
 N: uniphier
 
 ARM ZYNQ
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
deleted file mode 100644
index 4474ec3..000
--- a/configs/ph1_sld8_defconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ARCH_UNIPHIER_PH1_SLD8=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x8400
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_NAND_DENALI=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_UNIPHIER_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/ph1_ld4_defconfig b/configs/uniphier_ld4_sld8_defconfig
similarity index 95%
rename from configs/ph1_ld4_defconfig
rename to configs/uniphier_ld4_sld8_defconfig
index 2ddd1eb..ee3cbad 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ARCH_UNIPHIER_PH1_LD4=y
+CONFIG_ARCH_UNIPHIER_PH1_SLD8=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x8400
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
diff --git a/doc/README.uniphier b/doc/README.uniphier
index 57b947b..68cc05d 100644
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@@ -32,18 +32,18 @@ PH1-sLD3:
 $ make ph1_sld3_defconfig
 $ make CROSS_COMPILE=arm-linux-gnueabi-
 
-PH1-LD4:
-$ make ph1_ld4_defconfig
+PH1-LD4 reference board:
+$ make uniphier_ld4_sld8_defconfig
 $ make CROSS_COMPILE=arm-linux-gnueabi-
 
+PH1-sLD8 reference board:
+$ make uniphier_ld4_sld8_defconfig
+$ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-sld8-ref
+
 PH1-Pro4:
 $ make ph1_pro4_defconfig
 $ make CROSS_COMPILE=arm-linux-gnueabi-
 
-PH1-sLD8:
-$ make ph1_sld8_defconfig
-$ make CROSS_COMPILE=arm-linux-gnueabi-
-
 PH1-Pro5:
 $ make ph1_pro5_defconfig
 $ make CROSS_COMPILE=arm-linux-gnueabi-
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] ATAGS for Tegra, Sunxi, etc.

[Hans de Goede]

Hi,

On 17-12-15 10:21, Ian Campbell wrote:

On Thu, 2015-12-17 at 07:40 +0100, Karsten Merker wrote:

On Thu, Dec 17, 2015 at 01:59:57PM +0900, Masahiro Yamada wrote:

2015-12-17 13:58 GMT+09:00 Masahiro Yamada :

Hi,

I noticed some well-maintained new SoC families still
define CONFIG_CMDLINE_TAG.


For example,

[...]

include/configs/sunxi-common.h

  #define CONFIG_SETUP_MEMORY_TAGS
  #define CONFIG_CMDLINE_TAG
  #define CONFIG_INITRD_TAG
  #define CONFIG_SERIAL_TAG



Do they still use ATAGS, not device tree?


Sunxi uses devicetree for mainline kernels, but AFAIK ATAG
support is necessary to enable booting legacy vendor kernels.
There is still new sunxi-based hardware sold today that comes
with legacy 3.4-based kernels.


That legacy kernel is FEX (allwinners own description blob) based, I don't
know to what extent that involves ATAGs in some way though.

There are also people who use the 3.4 based fork from linux-sunxi.org, but
I don't know if that is DT or ATAGS or FEX.

A dependency on CONFIG_OLD_SUNXI_KERNEL_COMPAT might be an option depending
on what the kernels need, Hans probably knows better than I do.


The 3.4 based kernels use both ATAGS for things like memory size, and fex
for other hw config info.

I'm not in favor of wrapping things in CONFIG_OLD_SUNXI_KERNEL_COMPAT, because
recent 3.4 based kernels can boot without that, and I believe that removing
the ATAG support will break this, without really buying us much.

Regards,

Hans
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/3] freescale/qixis: Add support for booting from SD/QSPI

[Gong Qianyu]

1.Use "qixis_reset sd" to boot from SD
2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support
3.Use "qixis_reset qspi" to boot from QSPI flash

On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be
pin-multiplexed. So the switches are different between SD boot with
IFC support and SD boot with QSPI support. The default booting from
SD is with IFC support.

Signed-off-by: Gong Qianyu 
---
 board/freescale/common/qixis.c | 36 
 1 file changed, 36 insertions(+)

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 9f6b0e7..8642fec 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -216,6 +216,39 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #else
printf("Not implemented\n");
 #endif
+   } else if (strcmp(argv[1], "sd") == 0) {
+#ifdef QIXIS_LBMAP_SD
+   QIXIS_WRITE(rst_ctl, 0x30);
+   QIXIS_WRITE(rcfg_ctl, 0);
+   set_lbmap(QIXIS_LBMAP_SD);
+   set_rcw_src(QIXIS_RCW_SRC_SD);
+   QIXIS_WRITE(rcfg_ctl, 0x20);
+   QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+   printf("Not implemented\n");
+#endif
+   } else if (strcmp(argv[1], "sd_qspi") == 0) {
+#ifdef QIXIS_LBMAP_SD_QSPI
+   QIXIS_WRITE(rst_ctl, 0x30);
+   QIXIS_WRITE(rcfg_ctl, 0);
+   set_lbmap(QIXIS_LBMAP_SD_QSPI);
+   set_rcw_src(QIXIS_RCW_SRC_SD);
+   QIXIS_WRITE(rcfg_ctl, 0x20);
+   QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+   printf("Not implemented\n");
+#endif
+   } else if (strcmp(argv[1], "qspi") == 0) {
+#ifdef QIXIS_LBMAP_QSPI
+   QIXIS_WRITE(rst_ctl, 0x30);
+   QIXIS_WRITE(rcfg_ctl, 0);
+   set_lbmap(QIXIS_LBMAP_QSPI);
+   set_rcw_src(QIXIS_RCW_SRC_QSPI);
+   QIXIS_WRITE(rcfg_ctl, 0x20);
+   QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+   printf("Not implemented\n");
+#endif
} else if (strcmp(argv[1], "watchdog") == 0) {
static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
  "1min", "2min", "4min", "8min"};
@@ -255,6 +288,9 @@ U_BOOT_CMD(
"- hard reset to default bank\n"
"qixis_reset altbank - reset to alternate bank\n"
"qixis_reset nand - reset to nand\n"
+   "qixis_reset sd - reset to sd\n"
+   "qixis_reset sd_qspi - reset to sd with qspi support\n"
+   "qixis_reset qspi - reset to qspi\n"
"qixis watchdog  - set the watchdog period\n"
"   period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
"qixis_reset dump - display the QIXIS registers\n"
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] ATAGS for Tegra, Sunxi, etc.

[Ian Campbell]

On Thu, 2015-12-17 at 07:40 +0100, Karsten Merker wrote:
> On Thu, Dec 17, 2015 at 01:59:57PM +0900, Masahiro Yamada wrote:
> > 2015-12-17 13:58 GMT+09:00 Masahiro Yamada  > om>:
> > > Hi,
> > > 
> > > I noticed some well-maintained new SoC families still
> > > define CONFIG_CMDLINE_TAG.
> > > 
> > > 
> > > For example,
> [...]
> > > include/configs/sunxi-common.h
> > > 
> > >  #define CONFIG_SETUP_MEMORY_TAGS
> > >  #define CONFIG_CMDLINE_TAG
> > >  #define CONFIG_INITRD_TAG
> > >  #define CONFIG_SERIAL_TAG
> 
> > > Do they still use ATAGS, not device tree?
> 
> Sunxi uses devicetree for mainline kernels, but AFAIK ATAG
> support is necessary to enable booting legacy vendor kernels.
> There is still new sunxi-based hardware sold today that comes
> with legacy 3.4-based kernels.

That legacy kernel is FEX (allwinners own description blob) based, I don't
know to what extent that involves ATAGs in some way though.

There are also people who use the 3.4 based fork from linux-sunxi.org, but
I don't know if that is DT or ATAGS or FEX.

A dependency on CONFIG_OLD_SUNXI_KERNEL_COMPAT might be an option depending
on what the kernels need, Hans probably knows better than I do.

Ian.

> CCing Hans de Goede and Ian Cambell (sunxi maintainers).

> 
> Regards,
> Karsten
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [RFC] board_f: generalize code for case of no relocation

[Bin Meng]

Hi Alexey,

On Thu, Dec 17, 2015 at 3:13 AM, Alexey Brodkin
 wrote:
> Hi Bin,
>
> On Tue, 2015-12-15 at 20:45 +0800, Bin Meng wrote:
>> On Tue, Dec 15, 2015 at 6:06 PM, Alexey Brodkin
>>  wrote:
>> > Current implementation of disabled relocation only works for EFI.
>> >
>> > In case of GD_FLG_SKIP_RELOC jump_to_copy() will return instead of
>> > jumping further in board_init_r() etc. And jump_to_copy() being the last
>> > call in init_sequence_f when returning simply triggers hang() in
>> > board_init_f(). Well for everything except ARM, SANDBOX and EFI_APP.
>> >
>> > Not sure why ARM and SANBOX are here - I would assume it's all on
>> > purpose but as for EFI_APP this is an essential need for getting out of
>> > board_init_f() and jumping in board_init_r() immediately afterwards, see
>> > efi_main().
>> >
>> > But what if in case of no relocation we jump in board_init_r() right
>> > from jump_to_copy()? In that case we remove one ifdef from
>> > board_init_f() and leave a chance to seamlessly re-use disabled
>> > relocation for other (non-EFI) cases.
>> >
>> > Signed-off-by: Alexey Brodkin 
>> > ---
>> >
>> > Note I didn't test it for EFI because I don't know how to do that in
>> > simulation, please let me know if there's a simple way to do it.
>> >
>>
>> Does doc/README.efi not help?
>
> Yeah thanks for that obvious pointer.
> Still it requires some extra steps like obtaining/building EFI BIOS etc.
> Anyways I'll try to get this setup up and running.
>
>>
>> > But I did test it for ARC boards (with additional patches) that enable
>> > disabled relocation - these patches to follow once something similar to
>> > my proposal here is implemented.
>> >
>>
>> Reviewed-by: Bin Meng 
>>
>> Tested on QEMU, booting u-boot-app.efi with EFI firmware
>> Tested-by: Bin Meng 
>>
>> >  common/board_f.c  | 11 ---
>> >  lib/efi/efi_app.c |  2 +-
>> >  2 files changed, 9 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/common/board_f.c b/common/board_f.c
>> > index eac7c5e..2d60ed9 100644
>> > --- a/common/board_f.c
>> > +++ b/common/board_f.c
>> > @@ -720,8 +720,14 @@ static int setup_reloc(void)
>> >
>> >  static int jump_to_copy(void)
>> >  {
>> > +   /*
>> > +* In case of no relocation nothing to do between "running from 
>> > flash"
>> > +* (init_f) and "running from ram" (init_r), so just jumping in
>> > +* board_init_r().
>> > +*/
>> > if (gd->flags & GD_FLG_SKIP_RELOC)
>> > -   return 0;
>> > +   board_init_r((gd_t *)gd, gd->relocaddr);
>
> I tried to do more complicated things compared to booting in console
> like "usb start" and at that point faced an unexpected problem.
>
> The thing is usually in between board_init_f() and board_init_r()
> we do a couple of things, most important for us here is stack pointer
> update. See in board_init_f() we use init stack which is usually
> (for most of arches except x86) is located at hardcoded address
> CONFIG_SYS_INIT_SP_ADDR which might easily point to quite limited special
> memory like on-chip SRAM or (which is the case) be in the very beginning of
> RAM.
>
> This init stack as said above could be quite small - just enough for every
> everything in board_init_f(). But when something heavy is executed what may
> easily happen (and that happens for me on "usb start") - we'll get in 
> unexpected
> memory location. In my case I'm hitting non-existing memory which precedes
> DDR. And that was quite fortunate because I was hitting exception and so
> was able to figure out what's wrong.
>
> For me solution was in stack-pointer update right before calling 
> board_init_r()
> in my start.S. And that required another line addition to jump_to_copy():
> So now I'm having this:
> -->8-
> if (gd->flags & GD_FLG_SKIP_RELOC) {
> board_init_f_stack_update(gd->start_addr_sp); <-- Updating SP
> board_init_r((gd_t *)gd, gd->relocaddr);
> }
> -->8-
>
> I'm not sure if all that makes sense for x86 EFI but would like to know
> your opinion if potential run out out stack may happen there as well.
>

For u-boot-app.efi, the stack is allocated by the EFI firmware, so I
think we are fine here. If we change its SP without making the EFI
firmware aware, I believe subsequent call to EFI boot services will
fail.

Regards,
Bin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] Problems with USB 3 hubs

[Aaron Williams]

Hi all,

I maintain U-Boot for the Cavium Octeon series of 64-bit MIPS processors 
and have been experiencing problems with USB 3 hubs with XHCI.


If I plug in a USB 3 thumb drive into a USB 3 hub it is not seen. After 
fixing numerous endian issues USB 3 thumb drives are fully supported via 
XHCI as long as there is no USB hub in the path.


Delving into the XHCI and USB hub code it appears that there is no 
proper support for USB 3 hubs which have a number of differences from 
USB 2. Is any work going on in this area?


For example, the hub descriptor format has changed as well as the BOS 
descriptor. I'm looking at the Linux XHCI and hub code and see a lot of 
USB 3 changes not present in U-Boot.


I have been backporting a lot of the support to our current bootloader 
code base which is based on the 7/2013 release.


I might add that I found a lot of issues in the USB code, especially 
XHCI that are endian related since our Octeon processors are running in 
big endian mode, plus the fact that DMA addresses are not the same as 
pointer addresses, plus the USB code is not 64-bit friendly.


While I can gladly share my code and changes, we currently are not using 
the latest release, nor will I have time to upgrade to it for at least 
several months due to too many other projects on my plate (it doesn't 
help matters that we don't use git internally for U-Boot).


At some point I would love to get our code base merged in but this will 
be a significant effort due to the sheer amount of code involved.


-Aaron

--
Aaron Williams
Software Engineer
Cavium, Inc.
(408) 943-7198  (510) 789-8988 (cell)

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 2/3] armv8/ls1043aqds: fix qixis_reset command issue

[Gong Qianyu]

Signed-off-by: Gong Qianyu 
---
 include/configs/ls1043aqds.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 4aeb238..346a858 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -195,7 +195,7 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_SHIFT  0
 #define QIXIS_LBMAP_DFLTBANK   0x00
 #define QIXIS_LBMAP_ALTBANK0x04
-#define QIXIS_RST_CTL_RESET0x44
+#define QIXIS_RST_CTL_RESET0x41
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 3/3] armv8/ls1043aqds: enable qixis_reset command to boot from NAND/SD

[Gong Qianyu]

Signed-off-by: Gong Qianyu 
---
 include/configs/ls1043aqds.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 346a858..58c7144 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -195,6 +195,10 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_SHIFT  0
 #define QIXIS_LBMAP_DFLTBANK   0x00
 #define QIXIS_LBMAP_ALTBANK0x04
+#define QIXIS_LBMAP_NAND   0x09
+#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_RCW_SRC_NAND 0x106
+#define QIXIS_RCW_SRC_SD   0x040
 #define QIXIS_RST_CTL_RESET0x41
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 0/3] QIXIS related patches

[Gong Qianyu]

Hi all,

Here are three QIXIS related patches. I have tested on LS1043AQDS board.
Please help to review. Thanks!








Regards,
Qianyu
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 06/57] x86: ivybridge: Set up the LPC device using driver model

[Bin Meng]

Hi Simon,

On Wed, Dec 16, 2015 at 2:57 AM, Simon Glass  wrote:
> Hi Bin,
>
> On 13 December 2015 at 05:52, Bin Meng  wrote:
>> Hi Simon,
>>
>> On Tue, Dec 8, 2015 at 11:38 AM, Simon Glass  wrote:
>>> Find the LPC device in arch_cpu_init_dm() as a first step to converting
>>> this code to use driver model. Probing the LPC will probe its parent (the
>>> PCH) automatically, so make sure that probing the PCH does nothing before
>>> relocation.
>>>
>>> Signed-off-by: Simon Glass 
>>> ---
>>>
>>>  arch/x86/cpu/ivybridge/bd82x6x.c | 3 +++
>>>  arch/x86/cpu/ivybridge/cpu.c | 6 +-
>>>  arch/x86/cpu/ivybridge/lpc.c | 6 ++
>>>  arch/x86/dts/chromebook_link.dts | 1 +
>>>  4 files changed, 15 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c 
>>> b/arch/x86/cpu/ivybridge/bd82x6x.c
>>> index abd59da..be39bcd 100644
>>> --- a/arch/x86/cpu/ivybridge/bd82x6x.c
>>> +++ b/arch/x86/cpu/ivybridge/bd82x6x.c
>>> @@ -64,6 +64,9 @@ static int bd82x6x_probe(struct udevice *dev)
>>> int sata_node, gma_node;
>>> int ret;
>>>
>>> +   if (!(gd->flags & GD_FLG_RELOC))
>>> +   return 0;
>>> +
>>> hose = pci_bus_to_hose(0);
>>> lpc_enable(PCH_LPC_DEV);
>>> lpc_init(hose, PCH_LPC_DEV);
>>> diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
>>> index 0387444..fd7e1fc 100644
>>> --- a/arch/x86/cpu/ivybridge/cpu.c
>>> +++ b/arch/x86/cpu/ivybridge/cpu.c
>>> @@ -126,7 +126,7 @@ int arch_cpu_init_dm(void)
>>>  {
>>> const void *blob = gd->fdt_blob;
>>> struct pci_controller *hose;
>>> -   struct udevice *bus;
>>> +   struct udevice *bus, *dev;
>>> int node;
>>> int ret;
>>>
>>> @@ -141,6 +141,10 @@ int arch_cpu_init_dm(void)
>>> /* TODO(s...@chromium.org): Get rid of gd->hose */
>>> gd->hose = hose;
>>>
>>> +   ret = uclass_first_device(UCLASS_LPC, );
>>> +   if (!dev)
>>> +   return -ENODEV;
>>> +
>>> node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
>>> if (node < 0)
>>> return -ENOENT;
>>> diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
>>> index 3efd3e8..04a7451 100644
>>> --- a/arch/x86/cpu/ivybridge/lpc.c
>>> +++ b/arch/x86/cpu/ivybridge/lpc.c
>>> @@ -568,6 +568,11 @@ void lpc_enable(pci_dev_t dev)
>>> setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
>>>  }
>>>
>>> +static int bd82x6x_lpc_probe(struct udevice *dev)
>>> +{
>>> +   return 0;
>>> +}
>>> +
>>>  static const struct udevice_id bd82x6x_lpc_ids[] = {
>>> { .compatible = "intel,bd82x6x-lpc" },
>>> { }
>>> @@ -577,4 +582,5 @@ U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
>>> .name   = "lpc",
>>> .id = UCLASS_LPC,
>>> .of_match   = bd82x6x_lpc_ids,
>>> +   .probe  = bd82x6x_lpc_probe,
>>>  };
>>> diff --git a/arch/x86/dts/chromebook_link.dts 
>>> b/arch/x86/dts/chromebook_link.dts
>>> index 4d158da..7a009db 100644
>>> --- a/arch/x86/dts/chromebook_link.dts
>>> +++ b/arch/x86/dts/chromebook_link.dts
>>> @@ -223,6 +223,7 @@
>>> compatible = "intel,bd82x6x-lpc";
>>> #address-cells = <1>;
>>> #size-cells = <0>;
>>> +   u-boot,dm-pre-reloc;
>>> cros-ec@200 {
>>> compatible = "google,cros-ec";
>>> reg = <0x204 1 0x200 1 0x880 0x80>;
>>> --
>>
>> The codes look good to me, but I have one question: what is the LPC
>> uclass for? My understanding is that we already have the PCH uclass,
>> which is for the bridge. LPC uclass seems to be duplicated. We can
>> have cros-ec directly attached to the PCH node in the device tree.
>
> I was going to mention that in the cover letter.
>
> At present I have the northbridge as 0,0,0 device. The PCH is at
> 0,1f,0. Looking at the Intel datasheets the LPC is one of the pieces
> in the PCH. SPI is another piece. So I came up with having the PCH as
> the parent device and LPC and SPI as children.
>

But LPC is using the same PCI configuration space registers (b.d.f =
0.1f.0) as PCH for the programming interface, not like SPI which is
I/O space. With LPC uclass, we put LPC as the child node of the PCH
node, so if we access LPC configuration space registers, we end up
using LPC's parent device as the parameter for the DM PCI APIs. This
looks odd to me.

This unfortunately affects IRQ router as well, if we put IRQ router as
the child node under PCH. Can we just merge all of these into one PCH
uclass?

Regards,
Bin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 4/7] dm: Expand the uclass for Peripheral Controller Hubs (PCH)

[Bin Meng]

Hi Simon,

On Thu, Dec 17, 2015 at 12:09 PM, Simon Glass  wrote:
> Hi Bin,
>
> On 8 December 2015 at 06:23, Bin Meng  wrote:
>> Hi Simon,
>>
>> On Tue, Dec 1, 2015 at 12:11 PM, Simon Glass  wrote:
>>> A Peripheral Controller Hub is an Intel concept - it is like the peripherals
>>
>> I believe the name is Platform Controller Hub.
>>
>>> on an SoC and is often in a separate chip from the CPU. Even when it is not
>>> it is addressed and used differently. The chip is typically found on the
>>
>> "Even when it is not" (a separate chip) "it is addressed and used
>> differently"? I feel it should be "it is addressed and used the same'?
>>
>>> first PCI device.
>>
>> This indicates b.d.f = 0.0.0, but for registers like RCBA, SPI base,
>> those are actually on the LPC device (b.d.f = 0.1f.0). Maybe we can
>> say: the chip is typically found on the first PCI bus and integrates
>> multiple devices?
>>
>>>
>>> We have a very simple uclass to support PCHs. Add a few operations, such as
>>> setting up the devices on the PCH and finding the SPI controller base
>>> address. Also move it into drivers/pch/ since we will be adding a few PCH
>>> drivers.
>>>
>>> Signed-off-by: Simon Glass 
>>> ---
>>>
>>>  arch/x86/lib/Makefile  |  1 -
>>>  drivers/Makefile   |  1 +
>>>  drivers/pch/Makefile   |  5 +++
>>>  {arch/x86/lib => drivers/pch}/pch-uclass.c | 32 +++
>>>  include/pch.h  | 66 
>>> ++
>>>  5 files changed, 104 insertions(+), 1 deletion(-)
>>>  create mode 100644 drivers/pch/Makefile
>>>  rename {arch/x86/lib => drivers/pch}/pch-uclass.c (53%)
>>>  create mode 100644 include/pch.h
>>>
>>> diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
>>> index cd5ecb6..43792bc 100644
>>> --- a/arch/x86/lib/Makefile
>>> +++ b/arch/x86/lib/Makefile
>>> @@ -24,7 +24,6 @@ obj-$(CONFIG_I8254_TIMER) += i8254.o
>>>  ifndef CONFIG_DM_PCI
>>>  obj-$(CONFIG_PCI) += pci_type1.o
>>>  endif
>>> -obj-y  += pch-uclass.o
>>>  obj-y  += pirq_routing.o
>>>  obj-y  += relocate.o
>>>  obj-y += physmem.o
>>> diff --git a/drivers/Makefile b/drivers/Makefile
>>> index c9031f2..acc6af9 100644
>>> --- a/drivers/Makefile
>>> +++ b/drivers/Makefile
>>> @@ -51,6 +51,7 @@ obj-y += hwmon/
>>>  obj-y += misc/
>>>  obj-y += pcmcia/
>>>  obj-y += dfu/
>>> +obj-$(CONFIG_X86) += pch/
>>>  obj-y += rtc/
>>>  obj-y += sound/
>>>  obj-y += timer/
>>> diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
>>> new file mode 100644
>>> index 000..d69a99c
>>> --- /dev/null
>>> +++ b/drivers/pch/Makefile
>>> @@ -0,0 +1,5 @@
>>> +#
>>> +# SPDX-License-Identifier: GPL-2.0+
>>> +#
>>> +
>>> +obj-y += pch-uclass.o
>>> diff --git a/arch/x86/lib/pch-uclass.c b/drivers/pch/pch-uclass.c
>>> similarity index 53%
>>> rename from arch/x86/lib/pch-uclass.c
>>> rename to drivers/pch/pch-uclass.c
>>> index 20dfa81..09a0107 100644
>>> --- a/arch/x86/lib/pch-uclass.c
>>> +++ b/drivers/pch/pch-uclass.c
>>> @@ -7,10 +7,42 @@
>>>
>>>  #include 
>>>  #include 
>>> +#include 
>>>  #include 
>>>
>>>  DECLARE_GLOBAL_DATA_PTR;
>>>
>>> +int pch_init(struct udevice *dev)
>>> +{
>>> +   struct pch_ops *ops = pch_get_ops(dev);
>>> +
>>> +   if (!ops->init)
>>> +   return -ENOSYS;
>>> +
>>> +   return ops->init(dev);
>>> +}
>>> +
>>> +int pch_get_sbase(struct udevice *dev, ulong *sbasep)
>>> +{
>>> +   struct pch_ops *ops = pch_get_ops(dev);
>>> +
>>> +   *sbasep = 0;
>>> +   if (!ops->get_sbase)
>>> +   return -ENOSYS;
>>> +
>>> +   return ops->get_sbase(dev, sbasep);
>>> +}
>>> +
>>> +int pch_get_version(struct udevice *dev)
>>> +{
>>> +   struct pch_ops *ops = pch_get_ops(dev);
>>> +
>>> +   if (!ops->get_version)
>>> +   return -ENOSYS;
>>> +
>>> +   return ops->get_version(dev);
>>> +}
>>> +
>>>  static int pch_uclass_post_bind(struct udevice *bus)
>>>  {
>>> /*
>>> diff --git a/include/pch.h b/include/pch.h
>>> new file mode 100644
>>> index 000..98bb5f2
>>> --- /dev/null
>>> +++ b/include/pch.h
>>> @@ -0,0 +1,66 @@
>>> +/*
>>> + * Copyright (c) 2015 Google, Inc
>>> + * Written by Simon Glass 
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + */
>>> +
>>> +#ifndef __pch_h
>>> +#define __pch_h
>>> +
>>> +struct pch_ops {
>>> +   /**
>>> +* init() - set up the PCH devices
>>> +*
>>> +* This makes sure that all the devices are ready for use. They are
>>> +* not actually started, just set up so that they can be probed.
>>> +*/
>>> +   int (*init)(struct udevice *dev);
>>
>> Do we need create such an init op? Should this be done in the driver's
>> probe routine?
>
> The PCH is modelled in ivybridge as the device at address 0,0,0. I
> have found that we need to do the init in two stages, so this is the
> reason for the 

Re: [U-Boot] [PATCH v2 2/3] serial: uartlite: Add support for debug console

[Michal Simek]

On 17.12.2015 14:29, Thomas Chou wrote:
> Hi Michal,
> 
> On 2015年12月17日 20:00, Michal Simek wrote:
>> Add support for debug console.
>>
>> Signed-off-by: Michal Simek 
>> ---
>>
>> Changes in v2:
>> - Add needed header from the first patch
>> - Remove WATCHDOG_RESET call
>> - Extend commit description
>>
>>   drivers/serial/Kconfig|  7 +++
>>   drivers/serial/serial_xuartlite.c | 26 ++
>>   2 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
>> index 1fc287ee98ec..f1e221799b81 100644
>> --- a/drivers/serial/Kconfig
>> +++ b/drivers/serial/Kconfig
>> @@ -92,6 +92,13 @@ config DEBUG_UART_S5P
>> will need to provide parameters to make this work. The driver
>> will
>> be available until the real driver-model serial is running.
>>
>> +config DEBUG_UART_UARTLITE
>> +bool "Xilinx Uartlite"
>> +help
>> +  Select this to enable a debug UART using the serial_uartlite
>> driver.
>> +  You will need to provide parameters to make this work. The
>> driver will
>> +  be available until the real driver-model serial is running.
>> +
>>   config DEBUG_UART_ZYNQ
>>   bool "Xilinx Zynq"
>>   help
>> diff --git a/drivers/serial/serial_xuartlite.c
>> b/drivers/serial/serial_xuartlite.c
>> index 8225d9a320a5..f42b11eae102 100644
>> --- a/drivers/serial/serial_xuartlite.c
>> +++ b/drivers/serial/serial_xuartlite.c
>> @@ -114,3 +114,29 @@ U_BOOT_DRIVER(serial_uartlite) = {
>>   .ops= _serial_ops,
>>   .flags = DM_FLAG_PRE_RELOC,
>>   };
>> +
>> +#ifdef CONFIG_DEBUG_UART_UARTLITE
>> +
>> +#include 
>> +
>> +void _debug_uart_init(void)
> 
> Still missing, static inline
> 
> Otherwise,
> Reviewed-by: Thomas Chou 

I have sent separate patch for it and keep it here unchanged that's why
it is not here.

I can send you like if you like but I think you will find it out.

Thanks,
Michal

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/3] serial: uartlite: Move driver to DM

[Thomas Chou]

Hi Michal,

On 2015年12月17日 20:00, Michal Simek wrote:

Enable SPL DM too.

Signed-off-by: Michal Simek 
---

Changes in v2:
- Remove unneeded headers
- Use get_dev_addr instead of fdtdec_get_addr
- Use platdata instead of private data
- Add opb compatible string to be in sync with Linux
- Add binding documentation

  arch/microblaze/Kconfig|   1 +
  configs/microblaze-generic_defconfig   |   2 +
  .../serial/xilinx_uartlite.txt |  13 ++
  doc/driver-model/serial-howto.txt  |   1 -
  drivers/serial/serial_xuartlite.c  | 170 -
  5 files changed, 78 insertions(+), 109 deletions(-)
  create mode 100644 doc/device-tree-bindings/serial/xilinx_uartlite.txt

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 604f6815af5b..30ea484f48aa 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -13,6 +13,7 @@ config TARGET_MICROBLAZE_GENERIC
select SUPPORT_SPL
select OF_CONTROL
select DM
+   select DM_SERIAL

  endchoice

diff --git a/configs/microblaze-generic_defconfig 
b/configs/microblaze-generic_defconfig
index 54aa3ef3d26f..5df080b6a87c 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -1,9 +1,11 @@
  CONFIG_MICROBLAZE=y
  CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
  CONFIG_TARGET_MICROBLAZE_GENERIC=y
  CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
  CONFIG_SPL=y
  CONFIG_SYS_PROMPT="U-Boot-mONStR> "
  CONFIG_CMD_GPIO=y
  # CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_CONTROL=y
  CONFIG_OF_EMBED=y
diff --git a/doc/device-tree-bindings/serial/xilinx_uartlite.txt 
b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
new file mode 100644
index ..d15753c8c380
--- /dev/null
+++ b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
@@ -0,0 +1,13 @@
+Binding for Xilinx Uartlite Controller
+
+Required properties:
+- compatible : should be "xlnx,xps-uartlite-1.00.a", or 
"xlnx,opb-uartlite-1.00.b"
+- reg: Should contain UART controller registers location and length.
+- interrupts: Should contain UART controller interrupts.
+
+Example:
+   serial@4060 {
+   compatible = "xlnx,xps-uartlite-1.00.a";
+   interrupts = <1 0>;
+   reg = <0x4060 0x1>;
+   };
diff --git a/doc/driver-model/serial-howto.txt 
b/doc/driver-model/serial-howto.txt
index 76ad629ef9cb..381a2a084562 100644
--- a/doc/driver-model/serial-howto.txt
+++ b/doc/driver-model/serial-howto.txt
@@ -18,7 +18,6 @@ is time for maintainers to start converting over the 
remaining serial drivers:
 serial_pxa.c
 serial_s3c24x0.c
 serial_sa1100.c
-   serial_xuartlite.c
 usbtty.c

  You should complete this by the end of January 2016.
diff --git a/drivers/serial/serial_xuartlite.c 
b/drivers/serial/serial_xuartlite.c
index 988438e75471..8225d9a320a5 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -1,5 +1,5 @@
  /*
- * (C) Copyright 2008-2011 Michal Simek 
+ * (C) Copyright 2008 - 2015 Michal Simek 
   * Clean driver and add xilinx constant from header file
   *
   * (C) Copyright 2004 Atmark Techno, Inc.
@@ -10,11 +10,15 @@

  #include 
  #include 
+#include 
  #include 
  #include 
  #include 

+DECLARE_GLOBAL_DATA_PTR;
+
  #define SR_TX_FIFO_FULL   0x08 /* transmit FIFO full */
+#define SR_TX_FIFO_EMPTY   0x04 /* transmit FIFO empty */
  #define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
  #define SR_RX_FIFO_FULL   0x02 /* receive FIFO full */

@@ -28,135 +32,85 @@ struct uartlite {
unsigned int control;
  };

-static struct uartlite *userial_ports[4] = {
-#ifdef XILINX_UARTLITE_BASEADDR
-   [0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR1
-   [1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR2
-   [2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR3
-   [3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
-#endif
+struct uartlite_platdata {
+   struct uartlite *regs;
  };

-static void uartlite_serial_putc(const char c, const int port)
+static int uartlite_serial_putc(struct udevice *dev, const char ch)
  {
-   struct uartlite *regs = userial_ports[port];
+   struct uartlite_platdata *plat = dev_get_platdata(dev);
+   struct uartlite *regs = plat->regs;

-   if (c == '\n')
-   uartlite_serial_putc('\r', port);
+   if (in_be32(>status) & SR_TX_FIFO_FULL)
+   return -EAGAIN;

-   while (in_be32(>status) & SR_TX_FIFO_FULL)
-   ;
-   out_be32(>tx_fifo, c & 0xff);
-}
+   out_be32(>tx_fifo, ch & 0xff);

-static void uartlite_serial_puts(const char *s, const int port)
-{
-   while (*s)
-   

[U-Boot] [PATCH] serial-howto: remove altera_jtag_uart and altera_uart from the list

[Thomas Chou]

Since both altera_jtag_uart and altera_uart are converted to driver
model, remove them from the list of drivers remaining to convert.

Signed-off-by: Thomas Chou 
---
 doc/driver-model/serial-howto.txt | 2 --
 1 file changed, 2 deletions(-)

diff --git a/doc/driver-model/serial-howto.txt 
b/doc/driver-model/serial-howto.txt
index 76ad629..4706d56 100644
--- a/doc/driver-model/serial-howto.txt
+++ b/doc/driver-model/serial-howto.txt
@@ -4,8 +4,6 @@ How to port a serial driver to driver model
 About 16 of 33 serial drivers have been converted as at September 2015. It
 is time for maintainers to start converting over the remaining serial drivers:
 
-   altera_jtag_uart.c
-   altera_uart.c
arm_dcc.c
lpc32xx_hsuart.c
mcfuart.c
-- 
2.5.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 2/3] serial: uartlite: Add support for debug console

[Thomas Chou]

Hi Michal,

On 2015年12月17日 20:00, Michal Simek wrote:

Add support for debug console.

Signed-off-by: Michal Simek 
---

Changes in v2:
- Add needed header from the first patch
- Remove WATCHDOG_RESET call
- Extend commit description

  drivers/serial/Kconfig|  7 +++
  drivers/serial/serial_xuartlite.c | 26 ++
  2 files changed, 33 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1fc287ee98ec..f1e221799b81 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -92,6 +92,13 @@ config DEBUG_UART_S5P
  will need to provide parameters to make this work. The driver will
  be available until the real driver-model serial is running.

+config DEBUG_UART_UARTLITE
+   bool "Xilinx Uartlite"
+   help
+ Select this to enable a debug UART using the serial_uartlite driver.
+ You will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
  config DEBUG_UART_ZYNQ
bool "Xilinx Zynq"
help
diff --git a/drivers/serial/serial_xuartlite.c 
b/drivers/serial/serial_xuartlite.c
index 8225d9a320a5..f42b11eae102 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -114,3 +114,29 @@ U_BOOT_DRIVER(serial_uartlite) = {
.ops= _serial_ops,
.flags = DM_FLAG_PRE_RELOC,
  };
+
+#ifdef CONFIG_DEBUG_UART_UARTLITE
+
+#include 
+
+void _debug_uart_init(void)


Still missing, static inline

Otherwise,
Reviewed-by: Thomas Chou 


+{
+   struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
+
+   out_be32(>control, 0);
+   out_be32(>control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+   in_be32(>control);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+   struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
+
+   while (in_be32(>status) & SR_TX_FIFO_FULL)
+   ;
+
+   out_be32(>tx_fifo, ch & 0xff);
+}
+
+DEBUG_UART_FUNCS
+#endif



Best regards,
Thomas
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 0/5] Add wait_for_bit()

[LEMIEUX, SYLVAIN]

> From: Mateusz Kulikowski [mailto:mateusz.kulikow...@gmail.com]
> Sent: 16-Dec-15 4:59 PM
> To: u-boot@lists.denx.de; Marek Vasut; LEMIEUX, SYLVAIN; Joe Hershberger
> Cc: Mateusz Kulikowski
> Subject: [PATCH v2 0/5] Add wait_for_bit()
>
> Changes in V2:
> - wait_bit.o is always compiled in
> - Removed CONFIG_LIB_WAIT_BIT from configs/Kconfigs
> - Constified arguments to wait_bit
> - Removed check for CONFIG_... in drivers
> - Added tested-by to ohci-lp32xx
> @Sylvain Lemieux: I didn't changed driver logic with v2,
> so allowed myself to add your tested-by directly.

No problem, thanks

>
> Tested on:
>  - USB driver on Dragonboard (not yet in mainline)
>  - Infinite sleep (if timeout/interruption works)
> Build tested on single board for each driver/commit:
> - hikey
> - zynq_microzed
> - platinum
>

...

>
> --
> 2.5.0




This e-mail contains privileged and confidential information intended for the 
use of the addressees named above. If you are not the intended recipient of 
this e-mail, you are hereby notified that you must not disseminate, copy or 
take any action in respect of any information contained in it. If you have 
received this e-mail in error, please notify the sender immediately by e-mail 
and immediately destroy this e-mail and its attachments.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] axs103: add support of generic OHCI USB 1.1 controller

[Alexey Brodkin]

Hi Marek,

On Thu, 2015-12-17 at 05:01 +0100, Marek Vasut wrote:
> On Wednesday, December 16, 2015 at 08:54:11 PM, Alexey Brodkin wrote:
> > Hi Marek,
> 
> Hi!
> 
> > On Wed, 2015-12-16 at 17:52 +0100, Marek Vasut wrote:
> > > On Wednesday, December 16, 2015 at 05:05:15 PM, Alexey Brodkin wrote:
> > > > This commit adds support of USB 1.1 storage media on AXS103 board.
> > > > For some yet unknown reason USB 2.0 doesn't work on AXS103 board
> > > > issuing messages like this:
> > > > >8---
> > > > AXS# usb start
> > > > starting USB...
> > > > USB0:   USB EHCI 1.00
> > > > scanning bus 0 for devices... EHCI timed out on TD - token=0x80008c80
> > > > unable to get device descriptor (error=-1)
> > > > 1 USB Device(s) found
> > > > >8---
> > > 
> > > Try defining CONFIG_EHCI_IS_TDI , that _might_ help.
> > 
> > Thanks for that tip but it made no difference to me.
> > I need to look deeper into that problem.
> 
> I remember seeing that stuff multiple times before, but it might be a 
> different 
> issue. It was usually triggered by some sort of corruption during the 
> transfer.
> On ARM, that was often caused by cache issues.

Believe me I know how much of a grief caches bring so the first thing I do
when seeing unexpected behavior I disable caches :)

> > Just a bit of a context here.
> > I'm playing with ARC SP board which consists of 2 parts:
> >  [1] Baseboard with all peripherals and their connectors
> >  [2] Daughterboard with CPU and DDR
> > 
> > Baseboard is connected to CPU-board via AXI tunnel.
> > 
> > And when CPU-board is the one with ASIC based on ARC770
> > that runs at 700 MHz I see USB 2.0 working perfectly fine.
> > 
> > But if I use CPU-board that sports FPGA with ARC HS38 CPU
> > running at 75 MHz I see the first asynchronous tarnsaction
> > on US 2.0 never happens.
> 
> Connect signaltap or chipscope ? :)

Well I don't have either of those tools sitting on my desk but
if absolutely required I'll do that :)

> > In particular in ehci_submit_async() after we enable async. schedule
> > setting CMD_ASE command STS_ASS gets set but then token's status
> > stays active forever i.e. following is always true:
> > ->8-
> > QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE
> > ->8-
> > 
> > Note USB host controller, phy and usb dongle are exactly the same.
> > And USB 1.1 (OHCI) works perfectly fine at the same time.
> 
> Try adding #define DEBUG at the first line of common/usb.c , so we can get 
> some 
> more debugging info. Also adding the same into common/usb_hub.c helps.

Did that and here's my log:

->8-
starting USB...
USB0:   ehci_register: dev='ehci@0xe004', ctrl=9fd94100, hccr=e004, 
hcor=e0040010, init=0
Register  NbrPorts 1
USB EHCI 1.00
scanning bus 0 for devices... ehci_submit_control_msg: dev='ehci@0xe004', 
udev=9fd7c000, udev->dev='ehci@0xe004000
req=6 (0x6), type=128 (0x80), value=256, index=0
USB_DT_DEVICE request
ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000, 
udev->dev='ehci@0xe004', portnr=0
req=5 (0x5), type=0 (0x0), value=1, index=0
USB_REQ_SET_ADDRESS
Len is 0
ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000, 
udev->dev='ehci@0xe004', portnr=0
req=6 (0x6), type=128 (0x80), value=256, index=0
USB_DT_DEVICE request
ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000, 
udev->dev='ehci@0xe004', portnr=0
req=6 (0x6), type=128 (0x80), value=512, index=0
USB_DT_CONFIG config
ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000, 
udev->dev='ehci@0xe004', portnr=0
req=6 (0x6), type=128 (0x80), value=512, index=0
USB_DT_CONFIG config
ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000, 
udev->dev='ehci@0xe004', portnr=0
req=9 (0x9), type=0 (0x0), value=1, index=0
USB_REQ_SET_CONFIGURATION
Len is 0
ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000, 
udev->dev='ehci@0xe004', portnr=0
req=6 (0x6), type=128 (0x80), value=768, index=0
USB_DT_STRING config
ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000, 
udev->dev='ehci@0xe004', portnr=0
req=6 (0x6), type=128 (0x80), value=769, index=1
USB_DT_STRING config
ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000, 
udev->dev='ehci@0xe004', portnr=0
req=6 (0x6), type=128 (0x80), value=770, index=1
USB_DT_STRING config
ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd94380, 
udev->dev='usb_hub', portnr=0
req=6 (0x6), type=160 (0xa0), value=10496, index=0
USB_DT_HUB config
ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd94380, 
udev->dev='usb_hub', portnr=0
req=6 (0x6), type=160 (0xa0), value=10496, index=0
USB_DT_HUB config
ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd94380, 
udev->dev='usb_hub', portnr=0
req=0 (0x0), type=160 (0xa0), value=0, index=0
ehci_submit_control_msg: 

Re: [U-Boot] ATAGS for Tegra, Sunxi, etc.

[Tom Rini]

On Thu, Dec 17, 2015 at 10:26:07AM +0100, Hans de Goede wrote:
> Hi,
> 
> On 17-12-15 10:21, Ian Campbell wrote:
> >On Thu, 2015-12-17 at 07:40 +0100, Karsten Merker wrote:
> >>On Thu, Dec 17, 2015 at 01:59:57PM +0900, Masahiro Yamada wrote:
> >>>2015-12-17 13:58 GMT+09:00 Masahiro Yamada  >>>om>:
> Hi,
> 
> I noticed some well-maintained new SoC families still
> define CONFIG_CMDLINE_TAG.
> 
> 
> For example,
> >>[...]
> include/configs/sunxi-common.h
> 
>   #define CONFIG_SETUP_MEMORY_TAGS
>   #define CONFIG_CMDLINE_TAG
>   #define CONFIG_INITRD_TAG
>   #define CONFIG_SERIAL_TAG
> >>
> Do they still use ATAGS, not device tree?
> >>
> >>Sunxi uses devicetree for mainline kernels, but AFAIK ATAG
> >>support is necessary to enable booting legacy vendor kernels.
> >>There is still new sunxi-based hardware sold today that comes
> >>with legacy 3.4-based kernels.
> >
> >That legacy kernel is FEX (allwinners own description blob) based, I don't
> >know to what extent that involves ATAGs in some way though.
> >
> >There are also people who use the 3.4 based fork from linux-sunxi.org, but
> >I don't know if that is DT or ATAGS or FEX.
> >
> >A dependency on CONFIG_OLD_SUNXI_KERNEL_COMPAT might be an option depending
> >on what the kernels need, Hans probably knows better than I do.
> 
> The 3.4 based kernels use both ATAGS for things like memory size, and fex
> for other hw config info.
> 
> I'm not in favor of wrapping things in CONFIG_OLD_SUNXI_KERNEL_COMPAT, because
> recent 3.4 based kernels can boot without that, and I believe that removing
> the ATAG support will break this, without really buying us much.

+1.  ATAG is also used iirc for some other operating systems, still.

-- 
Tom


signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 08/14] net: emaclite: Remove XEL_TSR_XMIT_ACTIVE_MASK flag

[Michal Simek]

This flag is not documented anywhere in the latest documentation that's
why this patch removes it.

Signed-off-by: Michal Simek 
Acked-by: Joe Hershberger 
---

Changes in v2: None

 drivers/net/xilinx_emaclite.c | 15 ++-
 1 file changed, 2 insertions(+), 13 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index b0c26354e2e2..b6f3acae5a01 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -33,8 +33,6 @@
 #define XEL_TSR_XMIT_BUSY_MASK 0x0001UL
 /* Xmit interrupt enable bit */
 #define XEL_TSR_XMIT_IE_MASK   0x0008UL
-/* Buffer is active, SW bit only */
-#define XEL_TSR_XMIT_ACTIVE_MASK   0x8000UL
 /* Program the MAC address */
 #define XEL_TSR_PROGRAM_MASK   0x0002UL
 /* define for programming the MAC address into the EMAC Lite */
@@ -427,10 +425,7 @@ static int emaclite_send(struct eth_device *dev, void 
*ptr, int len)
 
/* Determine if the expected buffer address is empty */
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
-   if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
-   && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
-   & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
-
+   if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
if (emaclite->txpp)
emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
 
@@ -441,8 +436,6 @@ static int emaclite_send(struct eth_device *dev, void *ptr, 
int len)
(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
reg |= XEL_TSR_XMIT_BUSY_MASK;
-   if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
-   reg |= XEL_TSR_XMIT_ACTIVE_MASK;
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
return 0;
}
@@ -452,9 +445,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, 
int len)
baseaddress ^= XEL_BUFFER_OFFSET;
/* Determine if the expected buffer address is empty */
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
-   if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
-   && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
-   & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
+   if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
debug("Send packet from 0x%x\n", baseaddress);
/* Write the frame to the buffer */
xemaclite_alignedwrite(ptr, baseaddress, len);
@@ -463,8 +454,6 @@ static int emaclite_send(struct eth_device *dev, void *ptr, 
int len)
XEL_TPLR_LENGTH_MASK_LO)));
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
reg |= XEL_TSR_XMIT_BUSY_MASK;
-   if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
-   reg |= XEL_TSR_XMIT_ACTIVE_MASK;
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
return 0;
}
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 3/3] serial: uartlite: Add uartlite to Kconfig

[Thomas Chou]

Hi Michal,

On 2015年12月17日 20:00, Michal Simek wrote:

- Move config option out of board file.
- Remove uartlite address from config file

Signed-off-by: Michal Simek 
---

Changes in v2: None

  board/xilinx/microblaze-generic/xparameters.h | 4 
  configs/microblaze-generic_defconfig  | 1 +
  drivers/serial/Kconfig| 7 +++
  include/configs/microblaze-generic.h  | 7 +--
  4 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/board/xilinx/microblaze-generic/xparameters.h 
b/board/xilinx/microblaze-generic/xparameters.h
index 8ba146cb88db..11b3c9a4846e 100644
--- a/board/xilinx/microblaze-generic/xparameters.h
+++ b/board/xilinx/microblaze-generic/xparameters.h
@@ -28,10 +28,6 @@
  #define XILINX_TIMER_BASEADDR 0x41c0
  #define XILINX_TIMER_IRQ  0

-/* Uart pheriphery is RS232_Uart */
-#define XILINX_UARTLITE_BASEADDR   0x4060
-#define XILINX_UARTLITE_BAUDRATE   115200
-
  /* IIC pheriphery is IIC_EEPROM */
  #define XILINX_IIC_0_BASEADDR 0x4080
  #define XILINX_IIC_0_FREQ 10
diff --git a/configs/microblaze-generic_defconfig 
b/configs/microblaze-generic_defconfig
index 5df080b6a87c..9a7bb915466f 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -9,3 +9,4 @@ CONFIG_CMD_GPIO=y
  # CONFIG_CMD_SETEXPR is not set
  CONFIG_SPL_OF_CONTROL=y
  CONFIG_OF_EMBED=y
+CONFIG_XILINX_UARTLITE=y
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f1e221799b81..ddf49ba9cef3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -230,4 +230,11 @@ config UNIPHIER_SERIAL
  If you have a UniPhier based board and want to use the on-chip
  serial ports, say Y to this option. If unsure, say N.

+config XILINX_UARTLITE
+   bool "Xilinx Uarlite support"
+   depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+   help
+ If you have a Xilinx based board and want to use the uartlite
+ serial ports, say Y to this option. If unsure, say N.
+
  endmenu
diff --git a/include/configs/microblaze-generic.h 
b/include/configs/microblaze-generic.h
index 10ac8328b8ff..6e3c80b14350 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -37,10 +37,7 @@
  # define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

-#ifdef XILINX_UARTLITE_BASEADDR
-# define CONFIG_XILINX_UARTLITE
-# define CONFIG_SERIAL_BASEXILINX_UARTLITE_BASEADDR
-#elif XILINX_UART16550_BASEADDR
+#if XILINX_UART16550_BASEADDR
  # define CONFIG_SYS_NS16550_SERIAL
  # if defined(__MICROBLAZEEL__)
  #  define CONFIG_SYS_NS16550_REG_SIZE -4
@@ -51,8 +48,6 @@
  # define CONFIG_SYS_NS16550_COM1 \
((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
  # define CONFIG_SYS_NS16550_CLK   XILINX_UART16550_CLOCK_HZ
-#else
-# error Undefined uart
  #endif

  /* setting reset address */



Reviewed-by: Thomas Chou 

Best regards,
Thomas
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] common: usb: Adding delay after set configuration to support legacy devices

[Sriram Dash]

We faced random enumeration failure issue for USB sticks on XHCI driver,
specifically the legacy i.e. USB 2.0 storage devices. It seems they do not
respond to a USB string descriptor submission within the allowed U-Boot
timeout, which is just after sending set configuration.

USB stick where this this problem has been noticed are:
SanDisk U3 Cruzer Micro 0875530C9FC38749 (Vendor: 0x0781, Product 0x5406)

This problem has been reproduced on the Freescale LS2080A, and expected to be
hit for any platform with XHCI controller using legacy USB 2.0 devices.

This patch solves the above problem by:
Adding 10 ms delay after set configuration and let the device to settle down

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 common/usb.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/usb.c b/common/usb.c
index 700bfc3..c624a88 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1104,6 +1104,7 @@ int usb_select_config(struct usb_device *dev)
"len %d, status %lX\n", dev->act_len, dev->status);
return err;
}
+   mdelay(10); /* Let the SET_CONFIGURATION settle */
debug("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n",
  dev->descriptor.iManufacturer, dev->descriptor.iProduct,
  dev->descriptor.iSerialNumber);
-- 
2.1.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/3] serial: uartlite: Move driver to DM

[Michal Simek]

On 17.12.2015 14:37, Thomas Chou wrote:
> Hi Michal,
> 
> On 2015年12月17日 20:00, Michal Simek wrote:
>> Enable SPL DM too.
>>
>> Signed-off-by: Michal Simek 
>> ---
>>
>> Changes in v2:
>> - Remove unneeded headers
>> - Use get_dev_addr instead of fdtdec_get_addr
>> - Use platdata instead of private data
>> - Add opb compatible string to be in sync with Linux
>> - Add binding documentation
>>
>>   arch/microblaze/Kconfig|   1 +
>>   configs/microblaze-generic_defconfig   |   2 +
>>   .../serial/xilinx_uartlite.txt |  13 ++
>>   doc/driver-model/serial-howto.txt  |   1 -
>>   drivers/serial/serial_xuartlite.c  | 170
>> -
>>   5 files changed, 78 insertions(+), 109 deletions(-)
>>   create mode 100644 doc/device-tree-bindings/serial/xilinx_uartlite.txt
>>
>> diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
>> index 604f6815af5b..30ea484f48aa 100644
>> --- a/arch/microblaze/Kconfig
>> +++ b/arch/microblaze/Kconfig
>> @@ -13,6 +13,7 @@ config TARGET_MICROBLAZE_GENERIC
>>   select SUPPORT_SPL
>>   select OF_CONTROL
>>   select DM
>> +select DM_SERIAL
>>
>>   endchoice
>>
>> diff --git a/configs/microblaze-generic_defconfig
>> b/configs/microblaze-generic_defconfig
>> index 54aa3ef3d26f..5df080b6a87c 100644
>> --- a/configs/microblaze-generic_defconfig
>> +++ b/configs/microblaze-generic_defconfig
>> @@ -1,9 +1,11 @@
>>   CONFIG_MICROBLAZE=y
>>   CONFIG_SPL_SYS_MALLOC_SIMPLE=y
>> +CONFIG_SPL_DM=y
>>   CONFIG_TARGET_MICROBLAZE_GENERIC=y
>>   CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
>>   CONFIG_SPL=y
>>   CONFIG_SYS_PROMPT="U-Boot-mONStR> "
>>   CONFIG_CMD_GPIO=y
>>   # CONFIG_CMD_SETEXPR is not set
>> +CONFIG_SPL_OF_CONTROL=y
>>   CONFIG_OF_EMBED=y
>> diff --git a/doc/device-tree-bindings/serial/xilinx_uartlite.txt
>> b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
>> new file mode 100644
>> index ..d15753c8c380
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
>> @@ -0,0 +1,13 @@
>> +Binding for Xilinx Uartlite Controller
>> +
>> +Required properties:
>> +- compatible : should be "xlnx,xps-uartlite-1.00.a", or
>> "xlnx,opb-uartlite-1.00.b"
>> +- reg: Should contain UART controller registers location and length.
>> +- interrupts: Should contain UART controller interrupts.
>> +
>> +Example:
>> +serial@4060 {
>> +compatible = "xlnx,xps-uartlite-1.00.a";
>> +interrupts = <1 0>;
>> +reg = <0x4060 0x1>;
>> +};
>> diff --git a/doc/driver-model/serial-howto.txt
>> b/doc/driver-model/serial-howto.txt
>> index 76ad629ef9cb..381a2a084562 100644
>> --- a/doc/driver-model/serial-howto.txt
>> +++ b/doc/driver-model/serial-howto.txt
>> @@ -18,7 +18,6 @@ is time for maintainers to start converting over the
>> remaining serial drivers:
>>  serial_pxa.c
>>  serial_s3c24x0.c
>>  serial_sa1100.c
>> -   serial_xuartlite.c
>>  usbtty.c
>>
>>   You should complete this by the end of January 2016.
>> diff --git a/drivers/serial/serial_xuartlite.c
>> b/drivers/serial/serial_xuartlite.c
>> index 988438e75471..8225d9a320a5 100644
>> --- a/drivers/serial/serial_xuartlite.c
>> +++ b/drivers/serial/serial_xuartlite.c
>> @@ -1,5 +1,5 @@
>>   /*
>> - * (C) Copyright 2008-2011 Michal Simek 
>> + * (C) Copyright 2008 - 2015 Michal Simek 
>>* Clean driver and add xilinx constant from header file
>>*
>>* (C) Copyright 2004 Atmark Techno, Inc.
>> @@ -10,11 +10,15 @@
>>
>>   #include 
>>   #include 
>> +#include 
>>   #include 
>>   #include 
>>   #include 
>>
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>>   #define SR_TX_FIFO_FULL0x08 /* transmit FIFO full */
>> +#define SR_TX_FIFO_EMPTY0x04 /* transmit FIFO empty */
>>   #define SR_RX_FIFO_VALID_DATA0x01 /* data in receive FIFO */
>>   #define SR_RX_FIFO_FULL0x02 /* receive FIFO full */
>>
>> @@ -28,135 +32,85 @@ struct uartlite {
>>   unsigned int control;
>>   };
>>
>> -static struct uartlite *userial_ports[4] = {
>> -#ifdef XILINX_UARTLITE_BASEADDR
>> -[0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
>> -#endif
>> -#ifdef XILINX_UARTLITE_BASEADDR1
>> -[1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
>> -#endif
>> -#ifdef XILINX_UARTLITE_BASEADDR2
>> -[2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
>> -#endif
>> -#ifdef XILINX_UARTLITE_BASEADDR3
>> -[3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
>> -#endif
>> +struct uartlite_platdata {
>> +struct uartlite *regs;
>>   };
>>
>> -static void uartlite_serial_putc(const char c, const int port)
>> +static int uartlite_serial_putc(struct udevice *dev, const char ch)
>>   {
>> -struct uartlite *regs = userial_ports[port];
>> +struct uartlite_platdata *plat = dev_get_platdata(dev);
>> +struct uartlite *regs = plat->regs;
>>
>> -if (c == '\n')
>> -

Re: [U-Boot] [PATCH] common: usb: Adding delay after set configuration to support legacy devices

[Marek Vasut]

On Thursday, December 17, 2015 at 10:21:37 AM, Sriram Dash wrote:
> We faced random enumeration failure issue for USB sticks on XHCI driver,
> specifically the legacy i.e. USB 2.0 storage devices. It seems they do not
> respond to a USB string descriptor submission within the allowed U-Boot
> timeout, which is just after sending set configuration.
> 
> USB stick where this this problem has been noticed are:
> SanDisk U3 Cruzer Micro 0875530C9FC38749 (Vendor: 0x0781, Product 0x5406)
> 
> This problem has been reproduced on the Freescale LS2080A, and expected to
> be hit for any platform with XHCI controller using legacy USB 2.0 devices.
> 
> This patch solves the above problem by:
> Adding 10 ms delay after set configuration and let the device to settle
> down
> 
> Signed-off-by: Sriram Dash 
> Signed-off-by: Rajesh Bhagat 
> ---
>  common/usb.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/common/usb.c b/common/usb.c
> index 700bfc3..c624a88 100644
> --- a/common/usb.c
> +++ b/common/usb.c
> @@ -1104,6 +1104,7 @@ int usb_select_config(struct usb_device *dev)
>   "len %d, status %lX\n", dev->act_len, dev->status);
>   return err;
>   }
> + mdelay(10); /* Let the SET_CONFIGURATION settle */
>   debug("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n",
> dev->descriptor.iManufacturer, dev->descriptor.iProduct,
> dev->descriptor.iSerialNumber);

I suppose this should be isolated to USB 3.0 hosts, otherwise it will cause
slowdown on USB < 3.0 hosts as well and that's unwelcome.

Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] axs103: add support of generic OHCI USB 1.1 controller

[Marek Vasut]

On Thursday, December 17, 2015 at 02:32:26 PM, Alexey Brodkin wrote:
> Hi Marek,
> 
> On Thu, 2015-12-17 at 05:01 +0100, Marek Vasut wrote:
> > On Wednesday, December 16, 2015 at 08:54:11 PM, Alexey Brodkin wrote:
> > > Hi Marek,
> > 
> > Hi!
> > 
> > > On Wed, 2015-12-16 at 17:52 +0100, Marek Vasut wrote:
> > > > On Wednesday, December 16, 2015 at 05:05:15 PM, Alexey Brodkin wrote:
> > > > > This commit adds support of USB 1.1 storage media on AXS103 board.
> > > > > For some yet unknown reason USB 2.0 doesn't work on AXS103 board
> > > > > issuing messages like this:
> > > > > >8---
> > > > > AXS# usb start
> > > > > starting USB...
> > > > > USB0:   USB EHCI 1.00
> > > > > scanning bus 0 for devices... EHCI timed out on TD -
> > > > > token=0x80008c80 unable to get device descriptor (error=-1)
> > > > > 1 USB Device(s) found
> > > > > >8---
> > > > 
> > > > Try defining CONFIG_EHCI_IS_TDI , that _might_ help.
> > > 
> > > Thanks for that tip but it made no difference to me.
> > > I need to look deeper into that problem.
> > 
> > I remember seeing that stuff multiple times before, but it might be a
> > different issue. It was usually triggered by some sort of corruption
> > during the transfer. On ARM, that was often caused by cache issues.
> 
> Believe me I know how much of a grief caches bring so the first thing I do
> when seeing unexpected behavior I disable caches :)
> 
> > > Just a bit of a context here.
> > > 
> > > I'm playing with ARC SP board which consists of 2 parts:
> > >  [1] Baseboard with all peripherals and their connectors
> > >  [2] Daughterboard with CPU and DDR
> > > 
> > > Baseboard is connected to CPU-board via AXI tunnel.
> > > 
> > > And when CPU-board is the one with ASIC based on ARC770
> > > that runs at 700 MHz I see USB 2.0 working perfectly fine.
> > > 
> > > But if I use CPU-board that sports FPGA with ARC HS38 CPU
> > > running at 75 MHz I see the first asynchronous tarnsaction
> > > on US 2.0 never happens.
> > 
> > Connect signaltap or chipscope ? :)
> 
> Well I don't have either of those tools sitting on my desk but
> if absolutely required I'll do that :)
> 
> > > In particular in ehci_submit_async() after we enable async. schedule
> > > setting CMD_ASE command STS_ASS gets set but then token's status
> > > stays active forever i.e. following is always true:
> > > ->8-
> > > QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE
> > > ->8-
> > > 
> > > Note USB host controller, phy and usb dongle are exactly the same.
> > > And USB 1.1 (OHCI) works perfectly fine at the same time.
> > 
> > Try adding #define DEBUG at the first line of common/usb.c , so we can
> > get some more debugging info. Also adding the same into common/usb_hub.c
> > helps.
> 
> Did that and here's my log:
> 
> ->8-
> starting USB...
> USB0:   ehci_register: dev='ehci@0xe004', ctrl=9fd94100, hccr=e004,
> hcor=e0040010, init=0 Register  NbrPorts 1
> USB EHCI 1.00
> scanning bus 0 for devices... ehci_submit_control_msg:
> dev='ehci@0xe004', udev=9fd7c000, udev->dev='ehci@0xe004000 req=6
> (0x6), type=128 (0x80), value=256, index=0
> USB_DT_DEVICE request
> ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> udev->dev='ehci@0xe004', portnr=0 req=5 (0x5), type=0 (0x0), value=1,
> index=0
> USB_REQ_SET_ADDRESS
> Len is 0
> ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> udev->dev='ehci@0xe004', portnr=0 req=6 (0x6), type=128 (0x80),
> value=256, index=0
> USB_DT_DEVICE request
> ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> udev->dev='ehci@0xe004', portnr=0 req=6 (0x6), type=128 (0x80),
> value=512, index=0
> USB_DT_CONFIG config
> ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> udev->dev='ehci@0xe004', portnr=0 req=6 (0x6), type=128 (0x80),
> value=512, index=0
> USB_DT_CONFIG config
> ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> udev->dev='ehci@0xe004', portnr=0 req=9 (0x9), type=0 (0x0), value=1,
> index=0
> USB_REQ_SET_CONFIGURATION
> Len is 0
> ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> udev->dev='ehci@0xe004', portnr=0 req=6 (0x6), type=128 (0x80),
> value=768, index=0
> USB_DT_STRING config
> ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> udev->dev='ehci@0xe004', portnr=0 req=6 (0x6), type=128 (0x80),
> value=769, index=1
> USB_DT_STRING config
> ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> udev->dev='ehci@0xe004', portnr=0 req=6 (0x6), type=128 (0x80),
> value=770, index=1
> USB_DT_STRING config
> ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd94380,
> udev->dev='usb_hub', portnr=0 req=6 (0x6), type=160 (0xa0), value=10496,
> index=0
> USB_DT_HUB config
> ehci_submit_control_msg: 

Re: [U-Boot] [PATCH v4 05/16] spi: Add support for dual and quad mode

[Jagan Teki]

On 17 December 2015 at 12:19, Jagan Teki  wrote:
>
> On Dec 17, 2015 12:01 PM, "Mugunthan V N"  wrote:
>>
>> On Tuesday 15 December 2015 01:43 PM, Jagan Teki wrote:
>> > On 15 December 2015 at 13:22, Mugunthan V N  wrote:
>> >> spi bus can support dual and quad wire data transfers for tx and
>> >> rx. So defining dual and quad modes for both tx and rx. Also add
>> >> support to parse bus width used for spi tx and rx transfers.
>> >>
>> >> Signed-off-by: Mugunthan V N 
>> >> Reviewed-by: Simon Glass 
>> >> Reviewed-by: Tom Rini 
>> >> ---
>> >>
>> >> Changes from v3->v4
>> >> * used op_mode_{t/r}x to hold flash tx/rx modes.
>> >>
>> >> This has been tested on am437x-sk evm logs [1] and pushed a
>> >> branch for others to test [2]
>> >>
>> >> [1] - http://pastebin.ubuntu.com/14024895/
>> >> [2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git
>> >> dm-qspi-v4
>> >>
>> >> ---
>> >
>> > Please rebase it on master, there is some changes regarding SPI_TX_*
>> > and also please send the whole series with next version, it easy for
>> > me to quantify all at once and pick.
>> >
>>
>> Okay, will send v4 as a separate series. The branch which I pushed is
>> based on u-boot/master only.
>
> Just wait will ping you back, I have some updated patches need to push.

Please use u-boot-spi/next   - If possible please verify quad support
I have added few changes for setting up quad bit.

thanks!
-- 
Jagan.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] ATAGS for Tegra, Sunxi, etc.

[Stephen Warren]

On 12/16/2015 09:59 PM, Masahiro Yamada wrote:

+ To: U-Boot ML

I forgot to send this to ML.




2015-12-17 13:58 GMT+09:00 Masahiro Yamada :

Hi,

I noticed some well-maintained new SoC families still
define CONFIG_CMDLINE_TAG.


For example,

include/configs/tegra-common.h

   #define CONFIG_CMDLINE_TAG  /* enable passing of ATAGs */


IIRC, Tegra support in U-Boot was added in the days before DT was a 
thing, or a widespread thing at least. (Oh, happy days!) I imagine that 
the config option was simply never removed since there was no specific 
need to do so.


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v1 00/14] Initial Microchip PIC32MZ[DA] Support

[Purna Chandra Mandal]

This patch series adds support for Microchip PIC32MZ[DA] MIPS micro-controller 
platform.
All drivers required to boot from MMC micro-SD card and network are included in 
it; pinctrl,
clock, serial, SDHCI, gpio, Ethernet. This series been tested on PIC32MZ[DA] 
Starter Kit.

A tree with these changes are available at [0].

[0] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v1


Cristian Birsan (1):
  MIPS: pic32: Add driver for Microchip PIC32 internal flash controller.

Purna Chandra Mandal (11):
  drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
  MIPS: Add support for Microchip PIC32MZ[DA] SoC family.
  board: Add Microchip PIC32MZ[DA]-Starter-Kit board.
  board: pic32mzdask: add flash support for environments.
  MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO.
  drivers: gpio: add driver for Microchip PIC32 GPIO controller.
  drivers: net: phy: add SMSC LAN8740 Phy support.
  drivers: net: add Microchip PIC32 ethernet controller driver.
  board: Add gpio and ethernet support to pic32mzdask board.
  board: add SDHCI support for PIC32MZDASK board.
  board: pic32mzdask: Customize U-Boot environments for OS boot.

Sandeep Sheriker Mallikarjun (1):
  drivers: mmc: PIC32MZ[DA] SDHCI workaround when JTAG is not connected.

Sorin-Andrei Pistirica (1):
  drivers: mmc: add driver for Microchip PIC32 SDHCI controller.

 arch/mips/dts/Makefile   |   2 +-
 arch/mips/dts/pic32mzda.dtsi | 162 
 arch/mips/dts/pic32mzda_sk.dts   |  50 +++
 arch/mips/include/asm/arch-pic32/pic32.h |   3 +
 arch/mips/include/asm/gpio.h |   1 +
 arch/mips/mach-pic32/Kconfig |  23 +-
 arch/mips/mach-pic32/Makefile|   5 +-
 arch/mips/mach-pic32/cpu.c   | 121 +-
 arch/mips/mach-pic32/flash.c | 471 ++
 arch/mips/mach-pic32/lowlevel_init.S |  41 ++
 arch/mips/mach-pic32/reset.c |  22 ++
 board/microchip/pic32mzda/Kconfig|  13 +
 board/microchip/pic32mzda/MAINTAINERS|   6 +
 board/microchip/pic32mzda/Makefile   |   7 +
 board/microchip/pic32mzda/README |  22 ++
 board/microchip/pic32mzda/config.mk  |   4 +
 board/microchip/pic32mzda/ddr.c  | 389 +++
 board/microchip/pic32mzda/ddr.h  |  46 +++
 board/microchip/pic32mzda/pic32mzda.c|  41 ++
 configs/pic32mzdask_defconfig|  33 ++
 drivers/clk/Makefile |   1 +
 drivers/clk/clk-pic32.c  | 413 
 drivers/gpio/Kconfig |   7 +
 drivers/gpio/Makefile|   2 +-
 drivers/gpio/pic32_gpio.c| 164 
 drivers/mmc/Kconfig  |   6 +
 drivers/mmc/Makefile |   2 +-
 drivers/mmc/pic32_sdhci.c| 110 ++
 drivers/mmc/sdhci.c  |  12 +
 drivers/net/Kconfig  |   7 +
 drivers/net/Makefile |   1 +
 drivers/net/phy/smsc.c   |  10 +
 drivers/net/pic32_eth.c  | 648 +++
 drivers/net/pic32_eth.h  | 184 +
 drivers/net/pic32_mdio.c | 143 +++
 include/configs/pic32mzdask.h| 216 +++
 include/flash.h  |   5 +-
 37 files changed, 3386 insertions(+), 7 deletions(-)
 create mode 100644 arch/mips/dts/pic32mzda.dtsi
 create mode 100644 arch/mips/dts/pic32mzda_sk.dts
 create mode 100644 arch/mips/include/asm/gpio.h
 create mode 100644 arch/mips/mach-pic32/flash.c
 create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
 create mode 100644 arch/mips/mach-pic32/reset.c
 create mode 100644 board/microchip/pic32mzda/Kconfig
 create mode 100644 board/microchip/pic32mzda/MAINTAINERS
 create mode 100644 board/microchip/pic32mzda/Makefile
 create mode 100644 board/microchip/pic32mzda/README
 create mode 100644 board/microchip/pic32mzda/config.mk
 create mode 100644 board/microchip/pic32mzda/ddr.c
 create mode 100644 board/microchip/pic32mzda/ddr.h
 create mode 100644 board/microchip/pic32mzda/pic32mzda.c
 create mode 100644 configs/pic32mzdask_defconfig
 create mode 100644 drivers/clk/clk-pic32.c
 create mode 100644 drivers/gpio/pic32_gpio.c
 create mode 100644 drivers/mmc/pic32_sdhci.c
 create mode 100644 drivers/net/pic32_eth.c
 create mode 100644 drivers/net/pic32_eth.h
 create mode 100644 drivers/net/pic32_mdio.c
 create mode 100644 include/configs/pic32mzdask.h

-- 
1.8.3.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL

[Marek Vasut]

On Thursday, December 17, 2015 at 04:36:20 PM, Tim Harvey wrote:
> On Wed, Dec 16, 2015 at 6:40 AM, Marek Vasut  wrote:
> > Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
> > fine-tunes the behavior of the MMDC controller in order to improve
> > the signal integrity and memory stability.
> > 
> > Signed-off-by: Marek Vasut 
> > Cc: Stefano Babic 
> 
> Marek,
> 
> This is great - this would be a great addition to U-Boot IMX6 SPL.
> 
> You must have forgotten to post a dependent patch that adds some of
> the registers to mmdc_p_regs. If you can post that I can run this
> through some testing.

What exactly is missing please ? I am using this on Novena for a while
without issues.

> Also, in a follow-on post we should add some
> more verbiage about how long this takes to perform (I believe you told
> me ~10ms) and where to refer in the IMX6 RM's for the steps followed.

Freescale AN4467 is the right thing ... I mean NXP AN4467 of course.

Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] arm: socfpga: Fixed Phy not found error. Fixed QSPI flash not found error Disabled Hardware watch dog by default. Updated MMC clock.

[Marek Vasut]

On Thursday, December 17, 2015 at 07:59:34 AM, ShengjiangWu wrote:
> Hi Marek Vasut,

Hi,

> I will submit it later, thanks for your reminder.

Thanks.

Also, please do not top-post and please keep the entire Cc list intact.
Also keep the ML in the list.

> Best Regards
> Shengjiang Wu
> 
> 
> 
> 
> -- Original --
> From:  "marex";;
> Date:  Thu, Dec 17, 2015 11:46 AM
> To:  "ShengjiangWu";
> Cc:  "u-boot";
> "shengjiangwu"; "clsee";
> "dinguyen";
> "dinh.linux"; "pavel";
> "sr"; Subject:  Re: [PATCH] arm: socfpga: Fixed Phy not found
> error.   Fixed QSPI flash not found error  
> Disabled Hardware watch dog by default.   Updated MMC clock.
> 
> On Thursday, December 17, 2015 at 04:25:28 AM, ShengjiangWu wrote:
> > arm: socfpga: Fixed Phy not found error.
> > 
> >   Fixed QSPI flash not found error
> >   Disabled Hardware watch dog by default.
> >   Updated MMC clock.
> 
> Fix your mailer please.
> 
> > Updated pinmux and clock for EMAC1 and QSPI flash.
> > U-BOOT-2015-10 can run on Cyclone V SoC Development
> > Kit (SoCDK) with this fix.
> > 
> > Signed-off-by: swu 
> > Cc: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Dinh Nguyen 
> > Cc: Pavel Machek 
> > Cc: Marek Vasut 
> > Cc: Stefan Roese 
> 
> Please repost the patch using git send-email , details are at [1] and the
> process is very similar to Linux.
> 
> I briefly skimmed across the patch. I don't understand why do you replace
> almost the entire pinmux just to fix ethernet issue. (ethernet works on
> SoCDK I believe, which is another odd thing).
> 
> Furthermore, if you're fixing multiple things, split them into multiple
> patches.
> 
> Finally, do not disable HW watchdog.
> 
> [1] www.denx.de/wiki/U-Boot/Patches
> 
> Best regards,
> Marek Vasut

Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] U boot 2016 rc2 in a Q8 A13 tablet not recognize keyboard.

[far5893]

2016 rc2 version compiled against q8 A13 tablet configuration.

SD boot.


Usb detect give: failed,-96

error when a keyboard is connected.

But recognize mass storage (an empty key memory).


IBM Usb Keyboard model SK-8809-2D full working with original android.



Silviop
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL

[Tim Harvey]

On Wed, Dec 16, 2015 at 6:40 AM, Marek Vasut  wrote:
> Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
> fine-tunes the behavior of the MMDC controller in order to improve
> the signal integrity and memory stability.
>
> Signed-off-by: Marek Vasut 
> Cc: Stefano Babic 

Marek,

This is great - this would be a great addition to U-Boot IMX6 SPL.

You must have forgotten to post a dependent patch that adds some of
the registers to mmdc_p_regs. If you can post that I can run this
through some testing. Also, in a follow-on post we should add some
more verbiage about how long this takes to perform (I believe you told
me ~10ms) and where to refer in the IMX6 RM's for the steps followed.

Regards,

Tim
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] Problems with USB 3 hubs

[Marek Vasut]

On Thursday, December 17, 2015 at 10:12:08 AM, Aaron Williams wrote:
> Hi all,

Hi Aaron,

> I maintain U-Boot for the Cavium Octeon series of 64-bit MIPS processors
> and have been experiencing problems with USB 3 hubs with XHCI.
> 
> If I plug in a USB 3 thumb drive into a USB 3 hub it is not seen. After
> fixing numerous endian issues USB 3 thumb drives are fully supported via
> XHCI as long as there is no USB hub in the path.
> 
> Delving into the XHCI and USB hub code it appears that there is no
> proper support for USB 3 hubs which have a number of differences from
> USB 2. Is any work going on in this area?

Not to my knowledge, sorry.

> For example, the hub descriptor format has changed as well as the BOS
> descriptor. I'm looking at the Linux XHCI and hub code and see a lot of
> USB 3 changes not present in U-Boot.
> 
> I have been backporting a lot of the support to our current bootloader
> code base which is based on the 7/2013 release.
> 
> I might add that I found a lot of issues in the USB code, especially
> XHCI that are endian related since our Octeon processors are running in
> big endian mode, plus the fact that DMA addresses are not the same as
> pointer addresses, plus the USB code is not 64-bit friendly.

I see, I suspect the code was mostly tested on ARMv7 which is why those
issues went undetected.

> While I can gladly share my code and changes, we currently are not using
> the latest release, nor will I have time to upgrade to it for at least
> several months due to too many other projects on my plate (it doesn't
> help matters that we don't use git internally for U-Boot).

Is it possible for you to boot latest mainline U-Boot on octeon, fix the
issues, submit the fixes and then backport them?

> At some point I would love to get our code base merged in but this will
> be a significant effort due to the sheer amount of code involved.

Patches are welcome :)

> -Aaron

Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/3] serial: uartlite: Move driver to DM

[Simon Glass]

Hi Michal,

On 17 December 2015 at 06:58, Michal Simek  wrote:
> On 17.12.2015 14:37, Thomas Chou wrote:
>> Hi Michal,
>>
>> On 2015年12月17日 20:00, Michal Simek wrote:
>>> Enable SPL DM too.
>>>
>>> Signed-off-by: Michal Simek 
>>> ---
>>>
>>> Changes in v2:
>>> - Remove unneeded headers
>>> - Use get_dev_addr instead of fdtdec_get_addr
>>> - Use platdata instead of private data
>>> - Add opb compatible string to be in sync with Linux
>>> - Add binding documentation
>>>
>>>   arch/microblaze/Kconfig|   1 +
>>>   configs/microblaze-generic_defconfig   |   2 +
>>>   .../serial/xilinx_uartlite.txt |  13 ++
>>>   doc/driver-model/serial-howto.txt  |   1 -
>>>   drivers/serial/serial_xuartlite.c  | 170
>>> -
>>>   5 files changed, 78 insertions(+), 109 deletions(-)
>>>   create mode 100644 doc/device-tree-bindings/serial/xilinx_uartlite.txt
>>>
>>> diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
>>> index 604f6815af5b..30ea484f48aa 100644
>>> --- a/arch/microblaze/Kconfig
>>> +++ b/arch/microblaze/Kconfig
>>> @@ -13,6 +13,7 @@ config TARGET_MICROBLAZE_GENERIC
>>>   select SUPPORT_SPL
>>>   select OF_CONTROL
>>>   select DM
>>> +select DM_SERIAL
>>>
>>>   endchoice
>>>
>>> diff --git a/configs/microblaze-generic_defconfig
>>> b/configs/microblaze-generic_defconfig
>>> index 54aa3ef3d26f..5df080b6a87c 100644
>>> --- a/configs/microblaze-generic_defconfig
>>> +++ b/configs/microblaze-generic_defconfig
>>> @@ -1,9 +1,11 @@
>>>   CONFIG_MICROBLAZE=y
>>>   CONFIG_SPL_SYS_MALLOC_SIMPLE=y
>>> +CONFIG_SPL_DM=y
>>>   CONFIG_TARGET_MICROBLAZE_GENERIC=y
>>>   CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
>>>   CONFIG_SPL=y
>>>   CONFIG_SYS_PROMPT="U-Boot-mONStR> "
>>>   CONFIG_CMD_GPIO=y
>>>   # CONFIG_CMD_SETEXPR is not set
>>> +CONFIG_SPL_OF_CONTROL=y
>>>   CONFIG_OF_EMBED=y
>>> diff --git a/doc/device-tree-bindings/serial/xilinx_uartlite.txt
>>> b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
>>> new file mode 100644
>>> index ..d15753c8c380
>>> --- /dev/null
>>> +++ b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
>>> @@ -0,0 +1,13 @@
>>> +Binding for Xilinx Uartlite Controller
>>> +
>>> +Required properties:
>>> +- compatible : should be "xlnx,xps-uartlite-1.00.a", or
>>> "xlnx,opb-uartlite-1.00.b"
>>> +- reg: Should contain UART controller registers location and length.
>>> +- interrupts: Should contain UART controller interrupts.
>>> +
>>> +Example:
>>> +serial@4060 {
>>> +compatible = "xlnx,xps-uartlite-1.00.a";
>>> +interrupts = <1 0>;
>>> +reg = <0x4060 0x1>;
>>> +};
>>> diff --git a/doc/driver-model/serial-howto.txt
>>> b/doc/driver-model/serial-howto.txt
>>> index 76ad629ef9cb..381a2a084562 100644
>>> --- a/doc/driver-model/serial-howto.txt
>>> +++ b/doc/driver-model/serial-howto.txt
>>> @@ -18,7 +18,6 @@ is time for maintainers to start converting over the
>>> remaining serial drivers:
>>>  serial_pxa.c
>>>  serial_s3c24x0.c
>>>  serial_sa1100.c
>>> -   serial_xuartlite.c
>>>  usbtty.c
>>>
>>>   You should complete this by the end of January 2016.
>>> diff --git a/drivers/serial/serial_xuartlite.c
>>> b/drivers/serial/serial_xuartlite.c
>>> index 988438e75471..8225d9a320a5 100644
>>> --- a/drivers/serial/serial_xuartlite.c
>>> +++ b/drivers/serial/serial_xuartlite.c
>>> @@ -1,5 +1,5 @@
>>>   /*
>>> - * (C) Copyright 2008-2011 Michal Simek 
>>> + * (C) Copyright 2008 - 2015 Michal Simek 
>>>* Clean driver and add xilinx constant from header file
>>>*
>>>* (C) Copyright 2004 Atmark Techno, Inc.
>>> @@ -10,11 +10,15 @@
>>>
>>>   #include 
>>>   #include 
>>> +#include 
>>>   #include 
>>>   #include 
>>>   #include 
>>>
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>>   #define SR_TX_FIFO_FULL0x08 /* transmit FIFO full */
>>> +#define SR_TX_FIFO_EMPTY0x04 /* transmit FIFO empty */
>>>   #define SR_RX_FIFO_VALID_DATA0x01 /* data in receive FIFO */
>>>   #define SR_RX_FIFO_FULL0x02 /* receive FIFO full */
>>>
>>> @@ -28,135 +32,85 @@ struct uartlite {
>>>   unsigned int control;
>>>   };
>>>
>>> -static struct uartlite *userial_ports[4] = {
>>> -#ifdef XILINX_UARTLITE_BASEADDR
>>> -[0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
>>> -#endif
>>> -#ifdef XILINX_UARTLITE_BASEADDR1
>>> -[1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
>>> -#endif
>>> -#ifdef XILINX_UARTLITE_BASEADDR2
>>> -[2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
>>> -#endif
>>> -#ifdef XILINX_UARTLITE_BASEADDR3
>>> -[3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
>>> -#endif
>>> +struct uartlite_platdata {
>>> +struct uartlite *regs;
>>>   };
>>>
>>> -static void uartlite_serial_putc(const char c, const int port)
>>> +static int uartlite_serial_putc(struct udevice *dev, 

Re: [U-Boot] [PATCH] axs103: add support of generic OHCI USB 1.1 controller

[Alexey Brodkin]

Hi Marek,

On Thu, 2015-12-17 at 16:08 +0100, Marek Vasut wrote:
> On Thursday, December 17, 2015 at 02:32:26 PM, Alexey Brodkin wrote:
> > Hi Marek,
> > 
> > On Thu, 2015-12-17 at 05:01 +0100, Marek Vasut wrote:
> > > On Wednesday, December 16, 2015 at 08:54:11 PM, Alexey Brodkin wrote:
> > > > Hi Marek,
> > > 
> > > Hi!
> > > 
> > > > On Wed, 2015-12-16 at 17:52 +0100, Marek Vasut wrote:
> > > > > On Wednesday, December 16, 2015 at 05:05:15 PM, Alexey Brodkin wrote:
> > > > > > This commit adds support of USB 1.1 storage media on AXS103 board.
> > > > > > For some yet unknown reason USB 2.0 doesn't work on AXS103 board
> > > > > > issuing messages like this:
> > > > > > >8---
> > > > > > AXS# usb start
> > > > > > starting USB...
> > > > > > USB0:   USB EHCI 1.00
> > > > > > scanning bus 0 for devices... EHCI timed out on TD -
> > > > > > token=0x80008c80 unable to get device descriptor (error=-1)
> > > > > > 1 USB Device(s) found
> > > > > > >8---
> > > > > 
> > > > > Try defining CONFIG_EHCI_IS_TDI , that _might_ help.
> > > > 
> > > > Thanks for that tip but it made no difference to me.
> > > > I need to look deeper into that problem.
> > > 
> > > I remember seeing that stuff multiple times before, but it might be a
> > > different issue. It was usually triggered by some sort of corruption
> > > during the transfer. On ARM, that was often caused by cache issues.
> > 
> > Believe me I know how much of a grief caches bring so the first thing I do
> > when seeing unexpected behavior I disable caches :)
> > 
> > > > Just a bit of a context here.
> > > > 
> > > > I'm playing with ARC SP board which consists of 2 parts:
> > > >  [1] Baseboard with all peripherals and their connectors
> > > >  [2] Daughterboard with CPU and DDR
> > > > 
> > > > Baseboard is connected to CPU-board via AXI tunnel.
> > > > 
> > > > And when CPU-board is the one with ASIC based on ARC770
> > > > that runs at 700 MHz I see USB 2.0 working perfectly fine.
> > > > 
> > > > But if I use CPU-board that sports FPGA with ARC HS38 CPU
> > > > running at 75 MHz I see the first asynchronous tarnsaction
> > > > on US 2.0 never happens.
> > > 
> > > Connect signaltap or chipscope ? :)
> > 
> > Well I don't have either of those tools sitting on my desk but
> > if absolutely required I'll do that :)
> > 
> > > > In particular in ehci_submit_async() after we enable async. schedule
> > > > setting CMD_ASE command STS_ASS gets set but then token's status
> > > > stays active forever i.e. following is always true:
> > > > ->8-
> > > > QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE
> > > > ->8-
> > > > 
> > > > Note USB host controller, phy and usb dongle are exactly the same.
> > > > And USB 1.1 (OHCI) works perfectly fine at the same time.
> > > 
> > > Try adding #define DEBUG at the first line of common/usb.c , so we can
> > > get some more debugging info. Also adding the same into common/usb_hub.c
> > > helps.
> > 
> > Did that and here's my log:
> > 
> > ->8-
> > starting USB...
> > USB0:   ehci_register: dev='ehci@0xe004', ctrl=9fd94100, hccr=e004,
> > hcor=e0040010, init=0 Register  NbrPorts 1
> > USB EHCI 1.00
> > scanning bus 0 for devices... ehci_submit_control_msg:
> > dev='ehci@0xe004', udev=9fd7c000, udev->dev='ehci@0xe004000 req=6
> > (0x6), type=128 (0x80), value=256, index=0
> > USB_DT_DEVICE request
> > ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> > udev->dev='ehci@0xe004', portnr=0 req=5 (0x5), type=0 (0x0), value=1,
> > index=0
> > USB_REQ_SET_ADDRESS
> > Len is 0
> > ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> > udev->dev='ehci@0xe004', portnr=0 req=6 (0x6), type=128 (0x80),
> > value=256, index=0
> > USB_DT_DEVICE request
> > ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> > udev->dev='ehci@0xe004', portnr=0 req=6 (0x6), type=128 (0x80),
> > value=512, index=0
> > USB_DT_CONFIG config
> > ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> > udev->dev='ehci@0xe004', portnr=0 req=6 (0x6), type=128 (0x80),
> > value=512, index=0
> > USB_DT_CONFIG config
> > ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> > udev->dev='ehci@0xe004', portnr=0 req=9 (0x9), type=0 (0x0), value=1,
> > index=0
> > USB_REQ_SET_CONFIGURATION
> > Len is 0
> > ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> > udev->dev='ehci@0xe004', portnr=0 req=6 (0x6), type=128 (0x80),
> > value=768, index=0
> > USB_DT_STRING config
> > ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> > udev->dev='ehci@0xe004', portnr=0 req=6 (0x6), type=128 (0x80),
> > value=769, index=1
> > USB_DT_STRING config
> > ehci_submit_control_msg: dev='ehci@0xe004', udev=9fd7c000,
> > udev->dev='ehci@0xe004', portnr=0 

Re: [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL

[Tim Harvey]

On Wed, Dec 16, 2015 at 7:00 AM, Eric Nelson  wrote:
> Hi Marek,
>
> On 12/16/2015 07:40 AM, Marek Vasut wrote:
>> Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
>> fine-tunes the behavior of the MMDC controller in order to improve
>> the signal integrity and memory stability.
>>
>
> I'm glad to see that others are interested in this.
>
> I've been working on something similar, but struggling to have time
> to finish and clean it up:
> https://github.com/ericnelsonaz/u-boot/tree/memcal-pass1
>
> My aim is/was a bit different though, and aims to be a replacement for
> the DDR stress tool, which is cumbersome to use.

Eric,

I would love to see a series posted that adds IMX6 MMDC calibration
and stress test to U-Boot. I agree the Freescale code is very
difficult to use and I don't trust what its doing. I'm currently
seeing the Freescale DDR3 stress test fail on 8Gb density memory and I
am not convinced its not a problem with their code (yet I haven't had
time to pick through it with a fine toothed comb and compare with how
I setup the MMDC in U-Boot).

Regards,

Tim
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL

[Eric Nelson]

Hi Tim,

On 12/17/2015 08:39 AM, Tim Harvey wrote:
> On Wed, Dec 16, 2015 at 7:00 AM, Eric Nelson  wrote:
>> Hi Marek,
>>
>> On 12/16/2015 07:40 AM, Marek Vasut wrote:
>>> Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
>>> fine-tunes the behavior of the MMDC controller in order to improve
>>> the signal integrity and memory stability.
>>>
>>
>> I'm glad to see that others are interested in this.
>>
>> I've been working on something similar, but struggling to have time
>> to finish and clean it up:
>> https://github.com/ericnelsonaz/u-boot/tree/memcal-pass1
>>
>> My aim is/was a bit different though, and aims to be a replacement for
>> the DDR stress tool, which is cumbersome to use.
> 
> Eric,
> 
> I would love to see a series posted that adds IMX6 MMDC calibration
> and stress test to U-Boot. 

Will do. Some other demands on my time will push this into next
week (and Christmas) though.

I'll try to get an RFC version out before the holiday though, (after
reviewing Marek's patch).

> I agree the Freescale code is very difficult to use and I don't trust
> what its doing.

It's always tough to trust code that you can't see and discuss.

Because it's a pain to run, I also suspect that many (most) boards
are running with calibration gathered from a small set of boards,
and I've seen lots of board->board variation.

Something that can be run using imx_usb can make the process of
gathering data much easier.

The board->board variations hint that Marek's on the right track and
that calibration really should be done at run-time.

> I'm currently seeing the Freescale DDR3 stress test
> fail on 8Gb density memory and I am not convinced its not a problem
> with their code (yet I haven't had time to pick through it with a fine
> toothed comb and compare with how I setup the MMDC in U-Boot).
> 

I haven't seen any issues with 8GiB densities, but have only tested
on a small set of board designs (primarily Nitrogen6_max).

Regards,


Eric
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] spi: sf: add support for throughput mesurement of sf read/write

[Jagan Teki]

On 17 December 2015 at 13:26, Mugunthan V N  wrote:
> On Thursday 17 December 2015 12:43 PM, Jagan Teki wrote:
>> On 17 December 2015 at 12:33, Mugunthan V N  wrote:
>>> Jagan
>>>
>>> On Tuesday 27 October 2015 07:24 PM, Mugunthan V N wrote:
 This patch adds time measurement and throughput calculation for
 sf read/write commands.

 The output of sf read changes from

 ---8<---
 SF: 4096 bytes @ 0x0 Read: OK
 --->8---

 to

 ---8<---
 SF: 4096 bytes @ 0x0 Read: OK in 6 ms (666 KiB/s)
 --->8---

 Signed-off-by: Mugunthan V N 
>>
>> Was it similar to 'sf update' ? please check it once.
>>
>
> sf update out similar but also uses progressive output, in read/write
> case it can't be done. The final throughput measurement is similar on
> both update and read/write.

True, that's what if we need a progressed throughput just use 'sf
update' else normal 'sf read/write' It's look not good to me to add
extra code on top of generic commands. What ever we wanted to extend
features let's added it on 'sf update' than sf read/write, Sorry.

thanks!
-- 
Jagan.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL

[Tim Harvey]

On Thu, Dec 17, 2015 at 7:40 AM, Marek Vasut  wrote:
> On Thursday, December 17, 2015 at 04:36:20 PM, Tim Harvey wrote:
>> On Wed, Dec 16, 2015 at 6:40 AM, Marek Vasut  wrote:
>> > Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
>> > fine-tunes the behavior of the MMDC controller in order to improve
>> > the signal integrity and memory stability.
>> >
>> > Signed-off-by: Marek Vasut 
>> > Cc: Stefano Babic 
>>
>> Marek,
>>
>> This is great - this would be a great addition to U-Boot IMX6 SPL.
>>
>> You must have forgotten to post a dependent patch that adds some of
>> the registers to mmdc_p_regs. If you can post that I can run this
>> through some testing.
>
> What exactly is missing please ? I am using this on Novena for a while
> without issues.

sorry my bad... forgot I was on an old branch. All is good.

I will run some boards with this through some stress testing and review.

Tim
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v1 01/14] drivers: clk: Add clock driver for Microchip PIC32 microcontroller

[Purna Chandra Mandal]

This driver implements basic clock modules available in PIC32MZ[DA]
platforms.

Signed-off-by: Purna Chandra Mandal 
---

 drivers/clk/Makefile|   1 +
 drivers/clk/clk-pic32.c | 413 
 2 files changed, 414 insertions(+)
 create mode 100644 drivers/clk/clk-pic32.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4a6a4a8..3c84e08 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
+obj-$(CONFIG_MACH_PIC32) += clk-pic32.o
diff --git a/drivers/clk/clk-pic32.c b/drivers/clk/clk-pic32.c
new file mode 100644
index 000..4ebeee1
--- /dev/null
+++ b/drivers/clk/clk-pic32.c
@@ -0,0 +1,413 @@
+/*
+ * Copyright (C) 2015 Purna Chandra Mandal 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Primary oscillator */
+#define SYS_POSC_CLK_HZ2400
+
+/* Fixed clk rate */
+#define SYS_FRC_CLK_HZ800
+
+/* PLL */
+#define ICLK_MASK0x0080
+#define PLLIDIV_MASK0x0007
+#define PLLODIV_MASK0x0007
+#define CUROSC_MASK0x0007
+#define PLLMUL_MASK0x007F
+#define FRCDIV_MASK0x0007
+
+/* PBCLK */
+#define PBDIV_MASK0x0007
+
+/* SYSCLK MUX */
+#define SCLK_SRC_FRC10
+#define SCLK_SRC_SPLL1
+#define SCLK_SRC_POSC2
+#define SCLK_SRC_FRC27
+
+/* Reference Oscillator Control Reg fields */
+#define REFO_SEL_MASK0x0f
+#define REFO_SEL_SHIFT0
+#define REFO_ACTIVE0x0100
+#define REFO_DIVSW_EN0x0200
+#define REFO_OE0x1000
+#define REFO_ON0x8000
+#define REFO_DIV_SHIFT16
+#define REFO_DIV_MASK0x7fff
+
+/* Reference Oscillator Trim Register Fields */
+#define REFO_TRIM_REG0x10
+#define REFO_TRIM_MASK0x1ff
+#define REFO_TRIM_SHIFT23
+#define REFO_TRIM_MAX511
+
+#define ROCLK_SRC_SCLK0x0
+#define ROCLK_SRC_SPLL0x7
+#define ROCLK_SRC_ROCLKI0x8
+
+/* Memory PLL */
+#define MPLL_IDIV0x03
+#define MPLL_MULT0x32
+#define MPLL_ODIV10x02
+#define MPLL_ODIV20x01
+#define MPLL_VREG_RDY0x0080
+#define MPLL_RDY0x8000
+#define MPLL_IDIV_SHIFT0
+#define MPLL_MULT_SHIFT8
+#define MPLL_ODIV1_SHIFT24
+#define MPLL_ODIV2_SHIFT27
+
+static ulong pic32_get_pll_rate(void)
+{
+ulong plliclk, v;
+u32 iclk, idiv, odiv, mult;
+
+v = readl(SPLLCON);
+iclk = (v & ICLK_MASK);
+idiv = ((v >> 8) & PLLIDIV_MASK) + 1;
+odiv = ((v >> 24) & PLLODIV_MASK);
+mult = ((v >> 16) & PLLMUL_MASK) + 1;
+
+plliclk = iclk ? SYS_FRC_CLK_HZ : SYS_POSC_CLK_HZ;
+
+if (odiv < 2)
+odiv = 2;
+else if (odiv < 5)
+odiv = (1 << odiv);
+else
+odiv = 32;
+
+return ((plliclk / idiv) * mult) / odiv;
+}
+
+static ulong pic32_get_sysclk(void)
+{
+ulong hz;
+ulong div, frcdiv;
+ulong v  = readl(OSCCON);
+ulong curr_osc;
+
+/* get clk source */
+v = readl(OSCCON);
+curr_osc = (v >> 12) & CUROSC_MASK;
+switch (curr_osc) {
+case SCLK_SRC_FRC1:
+case SCLK_SRC_FRC2:
+frcdiv = ((v >> 24) & FRCDIV_MASK);
+div = ((1 << frcdiv) + 1) + (128 * (frcdiv == 7));
+hz = SYS_FRC_CLK_HZ / div;
+break;
+
+case SCLK_SRC_SPLL:
+hz = pic32_get_pll_rate();
+break;
+
+case SCLK_SRC_POSC:
+hz = SYS_POSC_CLK_HZ;
+break;
+
+default:
+hz = 0;
+printf("clk: unknown sclk_src.\n");
+break;
+}
+
+return hz;
+}
+
+static ulong pic32_get_pbclk(int bus)
+{
+ulong div, clk_freq;
+void __iomem *reg;
+
+clk_freq = pic32_get_sysclk();
+
+reg = (void __iomem *)PB1DIV + (bus * 0x10);
+div = (readl(reg) & PBDIV_MASK) + 1;
+
+return clk_freq / div;
+}
+
+static ulong pic32_get_cpuclk(void)
+{
+return pic32_get_pbclk(6);
+}
+
+static ulong pic32_set_refclk(int bus, int parent_rate, int rate, int 
parent_id)
+{
+void __iomem *reg;
+u32 div, trim, v;
+u64 frac;
+ulong base;
+
+/* calculate dividers,
+ *   rate = parent_rate / [2 * (div + (trim / 512))]
+ */
+if (parent_rate <= rate) {
+div = 0;
+trim = 0;
+} else {
+div = parent_rate / (rate << 1);
+frac = parent_rate;
+frac <<= 8;
+do_div(frac, rate);
+frac -= (u64)(div << 9);
+trim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : (u32)frac;
+}
+
+reg = (void __iomem *)(REFO1CON + bus * 0x20);
+
+/* disable clk */
+writel(REFO_ON | REFO_OE, reg + _CLR_OFFSET);
+
+/* wait till previous src change is active */
+base = get_timer(0);
+for (;;) {
+v = 

Re: [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL

[Marek Vasut]

On Thursday, December 17, 2015 at 05:15:46 PM, Tim Harvey wrote:
> On Thu, Dec 17, 2015 at 7:40 AM, Marek Vasut  wrote:
> > On Thursday, December 17, 2015 at 04:36:20 PM, Tim Harvey wrote:
> >> On Wed, Dec 16, 2015 at 6:40 AM, Marek Vasut  wrote:
> >> > Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
> >> > fine-tunes the behavior of the MMDC controller in order to improve
> >> > the signal integrity and memory stability.
> >> > 
> >> > Signed-off-by: Marek Vasut 
> >> > Cc: Stefano Babic 
> >> 
> >> Marek,
> >> 
> >> This is great - this would be a great addition to U-Boot IMX6 SPL.
> >> 
> >> You must have forgotten to post a dependent patch that adds some of
> >> the registers to mmdc_p_regs. If you can post that I can run this
> >> through some testing.
> > 
> > What exactly is missing please ? I am using this on Novena for a while
> > without issues.
> 
> sorry my bad... forgot I was on an old branch. All is good.
> 
> I will run some boards with this through some stress testing and review.

Whew! OKi, thanks!

Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v1 11/18] drivers: gpio: add driver for Microchip PIC32 GPIO controller.

[Purna Chandra Mandal]

PIC32 has ten independently programmable ports and each one with 16 pins.
These pins can be configured and used as GPIO, if they are not used by
any other peripherals.

Signed-off-by: Purna Chandra Mandal 
---

 drivers/gpio/Kconfig  |   7 ++
 drivers/gpio/Makefile |   2 +-
 drivers/gpio/pic32_gpio.c | 164 ++
 3 files changed, 172 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpio/pic32_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e60e9fd..13e9a6a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -83,4 +83,11 @@ config VYBRID_GPIO
 help
   Say yes here to support Vybrid vf610 GPIOs.
 
+config PIC32_GPIO
+bool "Microchip PIC32 GPIO driver"
+depends on DM_GPIO
+default y if MACH_PIC32
+help
+  Say yes here to support Microchip PIC32 GPIOs.
+
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb4fd25..845a6d4 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO)+= stm32_gpio.o
 obj-$(CONFIG_ZYNQ_GPIO)+= zynq_gpio.o
 obj-$(CONFIG_VYBRID_GPIO)+= vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)+= hi6220_gpio.o
-
+obj-$(CONFIG_PIC32_GPIO)+= pic32_gpio.o
diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c
new file mode 100644
index 000..60b423e
--- /dev/null
+++ b/drivers/gpio/pic32_gpio.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2015 Microchip Technology Inc
+ * Purna Chandra Mandal 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Peripheral Pin Control */
+struct pic32_gpio_regs {
+struct pic32_reg_atomic ansel;
+struct pic32_reg_atomic tris;
+struct pic32_reg_atomic port;
+struct pic32_reg_atomic lat;
+struct pic32_reg_atomic open_drain;
+struct pic32_reg_atomic cnpu;
+struct pic32_reg_atomic cnpd;
+struct pic32_reg_atomic cncon;
+};
+
+enum {
+MICROCHIP_GPIO_DIR_OUT,
+MICROCHIP_GPIO_DIR_IN,
+MICROCHIP_GPIOS_PER_BANK = 16,
+};
+
+struct pic32_gpio_priv {
+struct pic32_gpio_regs *regs;
+char name[2];
+};
+
+static int pic32_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+struct pic32_gpio_priv *priv = dev_get_priv(dev);
+
+return !!(readl(>regs->port.raw) & BIT(offset));
+}
+
+static int pic32_gpio_set_value(struct udevice *dev, unsigned offset,
+int value)
+{
+struct pic32_gpio_priv *priv = dev_get_priv(dev);
+int mask = BIT(offset);
+
+if (value)
+writel(mask, >regs->port.set);
+else
+writel(mask, >regs->port.clr);
+
+return 0;
+}
+
+static int pic32_gpio_direction(struct udevice *dev, unsigned offset)
+{
+struct pic32_gpio_priv *priv = dev_get_priv(dev);
+
+if (readl(>regs->ansel.raw) & BIT(offset))
+return -1;
+
+if (readl(>regs->tris.raw) & BIT(offset))
+return MICROCHIP_GPIO_DIR_IN;
+else
+return MICROCHIP_GPIO_DIR_OUT;
+}
+
+static int pic32_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+struct pic32_gpio_priv *priv = dev_get_priv(dev);
+int mask = BIT(offset);
+
+writel(mask, >regs->ansel.clr);
+writel(mask, >regs->tris.set);
+
+return 0;
+}
+
+static int pic32_gpio_direction_output(struct udevice *dev,
+   unsigned offset, int value)
+{
+struct pic32_gpio_priv *priv = dev_get_priv(dev);
+int mask = BIT(offset);
+
+writel(mask, >regs->ansel.clr);
+writel(mask, >regs->tris.clr);
+
+pic32_gpio_set_value(dev, offset, value);
+return 0;
+}
+
+static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+struct fdtdec_phandle_args *args)
+{
+desc->offset = args->args[0];
+desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+return 0;
+}
+
+static int pic32_gpio_probe(struct udevice *dev)
+{
+struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+struct pic32_gpio_priv *priv = dev_get_priv(dev);
+char *end;
+int bank;
+
+priv->regs = (struct pic32_gpio_regs *)dev_get_addr(dev);
+uc_priv->gpio_count = MICROCHIP_GPIOS_PER_BANK;
+end = strrchr(dev->name, '@');
+bank = trailing_strtoln(dev->name, end);
+priv->name[0] = 'A' + bank;
+uc_priv->bank_name = priv->name;
+
+return 0;
+}
+
+static int pic32_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+int ret = GPIOF_UNUSED;
+
+switch (pic32_gpio_direction(dev, offset)) {
+case MICROCHIP_GPIO_DIR_OUT:
+ret = GPIOF_OUTPUT;
+break;
+case MICROCHIP_GPIO_DIR_IN:
+ret = GPIOF_INPUT;
+break;
+default:
+ret = GPIOF_UNUSED;
+break;
+}
+return ret;
+}
+
+static const struct dm_gpio_ops gpio_pic32_ops = {
+.direction_input= 

[U-Boot] [PATCH v1 12/18] drivers: net: phy: add SMSC LAN8740 Phy support.

[Purna Chandra Mandal]

Add SMSC LAN8740 Phy support required for PIC32MZ[DA] devices.

Signed-off-by: Purna Chandra Mandal 
---

 drivers/net/phy/smsc.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index bfd9815..34986a2 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -69,11 +69,21 @@ static struct phy_driver lan8710_driver = {
 .shutdown = _shutdown,
 };
 
+static struct phy_driver lan8740_driver = {
+.name = "SMSC LAN8740",
+.uid = 0x0007c110,
+.mask = 0x0,
+.features = PHY_BASIC_FEATURES,
+.config = _config_aneg,
+.startup = _startup,
+.shutdown = _shutdown,
+};
 int phy_smsc_init(void)
 {
 phy_register(_driver);
 phy_register(_driver);
 phy_register(_driver);
+phy_register(_driver);
 
 return 0;
 }
-- 
1.8.3.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v1 03/18] drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.

[Purna Chandra Mandal]

This driver implements basic clock modules found in PIC32MZ[DA]
family processors.

Signed-off-by: Purna Chandra Mandal 
---

 drivers/clk/Makefile|   1 +
 drivers/clk/clk-pic32.c | 413 
 2 files changed, 414 insertions(+)
 create mode 100644 drivers/clk/clk-pic32.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4a6a4a8..3c84e08 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
+obj-$(CONFIG_MACH_PIC32) += clk-pic32.o
diff --git a/drivers/clk/clk-pic32.c b/drivers/clk/clk-pic32.c
new file mode 100644
index 000..4ebeee1
--- /dev/null
+++ b/drivers/clk/clk-pic32.c
@@ -0,0 +1,413 @@
+/*
+ * Copyright (C) 2015 Purna Chandra Mandal 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Primary oscillator */
+#define SYS_POSC_CLK_HZ2400
+
+/* Fixed clk rate */
+#define SYS_FRC_CLK_HZ800
+
+/* PLL */
+#define ICLK_MASK0x0080
+#define PLLIDIV_MASK0x0007
+#define PLLODIV_MASK0x0007
+#define CUROSC_MASK0x0007
+#define PLLMUL_MASK0x007F
+#define FRCDIV_MASK0x0007
+
+/* PBCLK */
+#define PBDIV_MASK0x0007
+
+/* SYSCLK MUX */
+#define SCLK_SRC_FRC10
+#define SCLK_SRC_SPLL1
+#define SCLK_SRC_POSC2
+#define SCLK_SRC_FRC27
+
+/* Reference Oscillator Control Reg fields */
+#define REFO_SEL_MASK0x0f
+#define REFO_SEL_SHIFT0
+#define REFO_ACTIVE0x0100
+#define REFO_DIVSW_EN0x0200
+#define REFO_OE0x1000
+#define REFO_ON0x8000
+#define REFO_DIV_SHIFT16
+#define REFO_DIV_MASK0x7fff
+
+/* Reference Oscillator Trim Register Fields */
+#define REFO_TRIM_REG0x10
+#define REFO_TRIM_MASK0x1ff
+#define REFO_TRIM_SHIFT23
+#define REFO_TRIM_MAX511
+
+#define ROCLK_SRC_SCLK0x0
+#define ROCLK_SRC_SPLL0x7
+#define ROCLK_SRC_ROCLKI0x8
+
+/* Memory PLL */
+#define MPLL_IDIV0x03
+#define MPLL_MULT0x32
+#define MPLL_ODIV10x02
+#define MPLL_ODIV20x01
+#define MPLL_VREG_RDY0x0080
+#define MPLL_RDY0x8000
+#define MPLL_IDIV_SHIFT0
+#define MPLL_MULT_SHIFT8
+#define MPLL_ODIV1_SHIFT24
+#define MPLL_ODIV2_SHIFT27
+
+static ulong pic32_get_pll_rate(void)
+{
+ulong plliclk, v;
+u32 iclk, idiv, odiv, mult;
+
+v = readl(SPLLCON);
+iclk = (v & ICLK_MASK);
+idiv = ((v >> 8) & PLLIDIV_MASK) + 1;
+odiv = ((v >> 24) & PLLODIV_MASK);
+mult = ((v >> 16) & PLLMUL_MASK) + 1;
+
+plliclk = iclk ? SYS_FRC_CLK_HZ : SYS_POSC_CLK_HZ;
+
+if (odiv < 2)
+odiv = 2;
+else if (odiv < 5)
+odiv = (1 << odiv);
+else
+odiv = 32;
+
+return ((plliclk / idiv) * mult) / odiv;
+}
+
+static ulong pic32_get_sysclk(void)
+{
+ulong hz;
+ulong div, frcdiv;
+ulong v  = readl(OSCCON);
+ulong curr_osc;
+
+/* get clk source */
+v = readl(OSCCON);
+curr_osc = (v >> 12) & CUROSC_MASK;
+switch (curr_osc) {
+case SCLK_SRC_FRC1:
+case SCLK_SRC_FRC2:
+frcdiv = ((v >> 24) & FRCDIV_MASK);
+div = ((1 << frcdiv) + 1) + (128 * (frcdiv == 7));
+hz = SYS_FRC_CLK_HZ / div;
+break;
+
+case SCLK_SRC_SPLL:
+hz = pic32_get_pll_rate();
+break;
+
+case SCLK_SRC_POSC:
+hz = SYS_POSC_CLK_HZ;
+break;
+
+default:
+hz = 0;
+printf("clk: unknown sclk_src.\n");
+break;
+}
+
+return hz;
+}
+
+static ulong pic32_get_pbclk(int bus)
+{
+ulong div, clk_freq;
+void __iomem *reg;
+
+clk_freq = pic32_get_sysclk();
+
+reg = (void __iomem *)PB1DIV + (bus * 0x10);
+div = (readl(reg) & PBDIV_MASK) + 1;
+
+return clk_freq / div;
+}
+
+static ulong pic32_get_cpuclk(void)
+{
+return pic32_get_pbclk(6);
+}
+
+static ulong pic32_set_refclk(int bus, int parent_rate, int rate, int 
parent_id)
+{
+void __iomem *reg;
+u32 div, trim, v;
+u64 frac;
+ulong base;
+
+/* calculate dividers,
+ *   rate = parent_rate / [2 * (div + (trim / 512))]
+ */
+if (parent_rate <= rate) {
+div = 0;
+trim = 0;
+} else {
+div = parent_rate / (rate << 1);
+frac = parent_rate;
+frac <<= 8;
+do_div(frac, rate);
+frac -= (u64)(div << 9);
+trim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : (u32)frac;
+}
+
+reg = (void __iomem *)(REFO1CON + bus * 0x20);
+
+/* disable clk */
+writel(REFO_ON | REFO_OE, reg + _CLR_OFFSET);
+
+/* wait till previous src change is active */
+base = get_timer(0);
+for (;;) {
+v = 

[U-Boot] [PATCH v1 05/18] drivers: serial: add driver for Microchip PIC32 UART controller.

[Purna Chandra Mandal]

From: Paul Thacker 

Signed-off-by: Paul Thacker 
Signed-off-by: Purna Chandra Mandal 
---

 drivers/serial/Kconfig|  13 +++
 drivers/serial/Makefile   |   1 +
 drivers/serial/serial_pic32.c | 220 ++
 3 files changed, 234 insertions(+)
 create mode 100644 drivers/serial/serial_pic32.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1fc287e..9763ea1 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -107,6 +107,14 @@ config DEBUG_UART_APBUART
   will need to provide parameters to make this work. The driver will
   be available until the real driver model serial is running.
 
+config DEBUG_UART_PIC32
+bool "Microchip PIC32"
+help
+  Select this to enable a debug UART using the serial_pic32 driver. You
+  will need to provide parameters to make this work. The driver will
+  be available until the real driver model serial is running.
+
+
 endchoice
 
 config DEBUG_UART_BASE
@@ -223,4 +231,9 @@ config UNIPHIER_SERIAL
   If you have a UniPhier based board and want to use the on-chip
   serial ports, say Y to this option. If unsure, say N.
 
+config PIC32_SERIAL
+bool "Support for Microchip PIC32 on-chip UART"
+help
+  Support for the UART found on Microchip PIC32 SoC's.
+
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index dd87147..57cd38b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
+obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
new file mode 100644
index 000..01c62e7
--- /dev/null
+++ b/drivers/serial/serial_pic32.c
@@ -0,0 +1,220 @@
+/*
+ * (c) 2015 Paul Thacker 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_ENABLEBIT(15)
+#define UART_ENABLE_RXBIT(12)
+#define UART_ENABLE_TXBIT(10)
+#define UART_RX_DATA_AVAILBIT(0)
+#define UART_RX_OERRBIT(1)
+#define UART_TX_FULLBIT(9)
+
+/* UART Control */
+#define U_BASE(x)(x)
+#define U_MODE(x)   U_BASE(x)
+#define U_MODECLR(x)(U_MODE(x) + _CLR_OFFSET)
+#define U_MODESET(x)(U_MODE(x) + _SET_OFFSET)
+#define U_STA(x)(U_BASE(x) + 0x10)
+#define U_STACLR(x) (U_STA(x) + _CLR_OFFSET)
+#define U_STASET(x) (U_STA(x) + _SET_OFFSET)
+#define U_TXREG(x)  (U_BASE(x) + 0x20)
+#define U_RXREG(x)  (U_BASE(x) + 0x30)
+#define U_BRG(x)(U_BASE(x) + 0x40)
+
+struct pic32_uart_priv {
+void __iomem *regs;
+ulong uartclk;
+};
+
+static void pic32_serial_setbrg(void __iomem *regs, ulong uart_clk, u32 baud)
+{
+writel(0, U_BRG(regs));
+writel((uart_clk / baud / 16) - 1, U_BRG(regs));
+udelay(100);
+}
+
+/*
+ * Initialize the serial port with the given baudrate.
+ * The settings are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int pic32_serial_init(void __iomem *regs, ulong clk, u32 baudrate)
+{
+/* disable and clear mode */
+writel(0, U_MODE(regs));
+writel(0, U_STA(regs));
+
+/* set baud rate generator */
+pic32_serial_setbrg(regs, clk, baudrate);
+
+/* enable the UART for TX and RX */
+writel(UART_ENABLE_TX | UART_ENABLE_RX, U_STASET(regs));
+
+/* enable the UART */
+writel(UART_ENABLE, U_MODESET(regs));
+return 0;
+}
+
+/* Output a single byte to the serial port */
+static void pic32_serial_putc(void __iomem *regs, const char c)
+{
+/* if \n, then add a \r */
+if (c == '\n')
+pic32_serial_putc(regs, '\r');
+
+/* Wait for Tx FIFO not full */
+while (readl(U_STA(regs)) & UART_TX_FULL)
+;
+
+/* stuff the tx buffer with the character */
+writel(c, U_TXREG(regs));
+}
+
+/* Test whether a character is in the RX buffer */
+static int pic32_serial_tstc(void __iomem *regs)
+{
+/* check if rcv buf overrun error has occurred */
+if (readl(U_STA(regs)) & UART_RX_OERR) {
+readl(U_RXREG(regs));
+
+/* clear OERR to keep receiving */
+writel(UART_RX_OERR, U_STACLR(regs));
+}
+
+if (readl(U_STA(regs)) & UART_RX_DATA_AVAIL)
+return 1;/* yes, there is data in rcv buffer */
+else
+return 0;/* no data in rcv buffer */
+}
+
+/*
+ * Read a single byte from the rx buffer.
+ * Blocking: waits until a character is received, then returns.
+ * Return the character read directly from the UART's receive register.
+ *
+ */
+static int 

[U-Boot] [PATCH v1 18/18] board: pic32mzdask: Customize default environments for OS boot.

[Purna Chandra Mandal]

Add custom environment variables and commands to help boot
from micro-SD card and/or from network (TFTP protocol).

Signed-off-by: Purna Chandra Mandal 

---

 include/configs/pic32mzdask.h | 43 +++
 1 file changed, 43 insertions(+)

diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 94e73e3..c903113 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -169,5 +169,48 @@
 #define CONFIG_BOOTDELAY5 /* autoboot after X seconds */
 #undefCONFIG_BOOTARGS
 
+#define CONFIG_EXTRA_ENV_SETTINGS\
+"loadaddr="__stringify(CONFIG_SYS_LOAD_ADDR)"\0"\
+"uenvfile=uEnv.txt\0"\
+"uenvaddr="__stringify(CONFIG_SYS_ENV_ADDR)"\0"\
+"scriptfile=boot.scr\0"\
+"ubootfile=u-boot.bin\0"\
+"importbootenv= "\
+"env import -t -r ${uenvaddr} ${filesize};\0"\
+\
+"tftploadenv=tftp ${uenvaddr} ${uenvfile} \0"\
+"tftploadscr=tftp ${uenvaddr} ${scriptfile} \0"\
+"tftploadub=tftp ${loadaddr} ${ubootfile} \0"\
+\
+"mmcloadenv=fatload mmc 0 ${uenvaddr} ${uenvfile}\0"\
+"mmcloadscr=fatload mmc 0 ${uenvaddr} ${scriptfile}\0"\
+"mmcloadub=fatload mmc 0 ${loadaddr} ${ubootfile}\0"\
+\
+"flashub=protect off bank 1; "\
+"erase.b 0x9d004000 0x9d0f3fff; "\
+"cp.b ${loadaddr} 0x9d004000 ${filesize}; "\
+"cmp.b ${loadaddr} 0x9d004000 ${filesize}; "\
+"protect on bank 1; \0"\
+\
+"loadbootenv=run mmcloadenv || run tftploadenv\0"\
+"loadbootscr=run mmcloadscr || run tftploadscr\0"\
+"bootcmd_root= "\
+"if run loadbootenv; then "\
+"echo Loaded environment ${uenvfile}; "\
+"run importbootenv; "\
+"fi; "\
+"if test -n \"${bootcmd_uenv}\" ; then "\
+"echo Running bootcmd_uenv ...; "\
+"run bootcmd_uenv; "\
+"fi; "\
+"if run loadbootscr; then "\
+"echo Jumping to ${scriptfile}; "\
+"source ${uenvaddr}; "\
+"fi; "\
+"echo Custom environment or script not found. "\
+"Aborting auto booting...; \0"\
+""
+
+#define CONFIG_BOOTCOMMAND"run bootcmd_root"
 #define CONFIG_MEMSIZE_IN_BYTES/* pass 'memsize=' in bytes */
 #endif/* __PIC32MZDASK_CONFIG_H */
-- 
1.8.3.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v1 17/18] board: add SDHCI support for PIC32MZDASK board.

[Purna Chandra Mandal]

Add SDHCI and file system (FAT, EXT2, EXT4) support to enable
OS (Linux) boot from micro-SD card.

Signed-off-by: Purna Chandra Mandal 
---

 arch/mips/dts/pic32mzda.dtsi   | 11 +++
 arch/mips/dts/pic32mzda_sk.dts |  7 +++
 configs/pic32mzdask_defconfig  |  2 ++
 include/configs/pic32mzdask.h  | 27 +++
 4 files changed, 47 insertions(+)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index cf76825..3ae54c3 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -148,4 +148,15 @@
 phy-mode = "rmii";
 status = "disabled";
 };
+
+sdhci: sdhci@1f8ec000 {
+compatible = "microchip,pic32mzda-sdhci";
+reg = <0xbf8ec000 0x100>;
+interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
+bus-width = <4>;
+cap-sd-highspeed;
+clock-freq-min-max = <2500>,<2500>;
+clock-irq-pins = <1>,<1>;
+status = "disabled";
+};
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index 38ef9c0..db1dde9 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -23,6 +23,9 @@
 };
 
  {
+microchip,refo2-frequency = <5000>;
+microchip,refo4-frequency = <2500>;
+microchip,refo5-frequency = <4000>;
 status = "okay";
 u-boot,dm-pre-reloc;
 };
@@ -41,3 +44,7 @@
 reset-gpios = < 15 0>;
 status = "okay";
 };
+
+ {
+status = "okay";
+};
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index d74d169..3079387 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -29,3 +29,5 @@ CONFIG_DM_ETH=y
 CONFIG_PHYLIB=y
 CONFIG_NETDEVICES=y
 CONFIG_PIC32_ETH=y
+CONFIG_DM_MMC=y
+CONFIG_PIC32_SDHCI=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 8e5c31b..94e73e3 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -127,6 +127,33 @@
  */
 #define CONFIG_OF_LIBFDT1
 
+/*---
+ * SDHC Configuration
+ */
+#define CONFIG_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_MMC
+
+/*---
+ * File System Configuration
+ */
+/* FAT FS */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_FAT
+
+/* EXT4 FS */
+#define CONFIG_FS_EXT4
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
 /* -
  * Environment
  */
-- 
1.8.3.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v1 00/18] Initial Microchip PIC32MZ[DA] Support

[Purna Chandra Mandal]

This patch series adds support for Microchip PIC32MZ[DA] MIPS microcontroller 
platform.
All drivers required to boot from MMC micro-SD card and network are included in 
it; pinctrl,
clock, serial, SDHCI, gpio, ethernet. This series been tested on PIC32MZ[DA] 
Starter Kit.

A tree with these changes are available at [0].

[0] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v1


Cristian Birsan (1):
  MIPS: pic32: Add driver for Microchip PIC32 internal flash controller.

Paul Thacker (1):
  drivers: serial: add driver for Microchip PIC32 UART controller.

Purna Chandra Mandal (14):
  MIPS: Prepare device-tree support.
  MIPS: initial infrastructure for Microchip PIC32 architecture.
  drivers: pinctrl: Add pinctrl driver for Microchip PIC32.
  drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
  MIPS: Add support for Microchip PIC32MZ[DA] SoC family.
  board: Add Microchip PIC32MZ[DA]-Starter-Kit board.
  board: pic32mzdask: add flash support for environments.
  MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO.
  drivers: gpio: add driver for Microchip PIC32 GPIO controller.
  drivers: net: phy: add SMSC LAN8740 Phy support.
  drivers: net: add Microchip PIC32 ethernet controller driver.
  board: Add gpio and ethernet support to pic32mzdask board.
  board: add SDHCI support for PIC32MZDASK board.
  board: pic32mzdask: Customize U-Boot environments for OS boot.

Sandeep Sheriker Mallikarjun (1):
  drivers: mmc: PIC32MZ[DA] SDHCI errata fix when JTAG is not connected.

Andrei Pistirica (1):
  drivers: mmc: add driver for Microchip PIC32 SDHCI controller.

 arch/Kconfig |   1 +
 arch/mips/Kconfig|   5 +
 arch/mips/Makefile   |   1 +
 arch/mips/config.mk  |   3 +
 arch/mips/dts/.gitignore |   1 +
 arch/mips/dts/Makefile   |  16 +
 arch/mips/dts/include/dt-bindings|   1 +
 arch/mips/dts/pic32mzda.dtsi | 162 
 arch/mips/dts/pic32mzda_sk.dts   |  50 +++
 arch/mips/dts/skeleton.dtsi  |  21 +
 arch/mips/include/asm/arch-pic32/clock.h |  31 ++
 arch/mips/include/asm/arch-pic32/pic32.h | 148 +++
 arch/mips/include/asm/gpio.h |   1 +
 arch/mips/mach-pic32/Kconfig |  41 ++
 arch/mips/mach-pic32/Makefile|  10 +
 arch/mips/mach-pic32/config.mk   |   8 +
 arch/mips/mach-pic32/cpu.c   | 132 +++
 arch/mips/mach-pic32/flash.c | 471 ++
 arch/mips/mach-pic32/lowlevel_init.S |  41 ++
 arch/mips/mach-pic32/reset.c |  22 ++
 board/microchip/pic32mzda/Kconfig|  13 +
 board/microchip/pic32mzda/MAINTAINERS|   6 +
 board/microchip/pic32mzda/Makefile   |   7 +
 board/microchip/pic32mzda/README |  22 ++
 board/microchip/pic32mzda/config.mk  |   4 +
 board/microchip/pic32mzda/ddr.c  | 389 +++
 board/microchip/pic32mzda/ddr.h  |  46 +++
 board/microchip/pic32mzda/pic32mzda.c|  41 ++
 configs/pic32mzdask_defconfig|  33 ++
 drivers/clk/Makefile |   1 +
 drivers/clk/clk-pic32.c  | 413 
 drivers/gpio/Kconfig |   7 +
 drivers/gpio/Makefile|   2 +-
 drivers/gpio/pic32_gpio.c| 164 
 drivers/mmc/Kconfig  |   6 +
 drivers/mmc/Makefile |   2 +-
 drivers/mmc/pic32_sdhci.c| 110 ++
 drivers/mmc/sdhci.c  |  12 +
 drivers/net/Kconfig  |   7 +
 drivers/net/Makefile |   1 +
 drivers/net/phy/smsc.c   |  10 +
 drivers/net/pic32_eth.c  | 648 +++
 drivers/net/pic32_eth.h  | 184 +
 drivers/net/pic32_mdio.c | 143 +++
 drivers/pinctrl/Kconfig  |   6 +
 drivers/pinctrl/Makefile |   1 +
 drivers/pinctrl/pinctrl_pic32.c  | 173 +
 drivers/serial/Kconfig   |  13 +
 drivers/serial/Makefile  |   1 +
 drivers/serial/serial_pic32.c| 220 +++
 dts/Makefile |   2 +-
 include/configs/pic32mzdask.h| 216 +++
 include/flash.h  |   5 +-
 53 files changed, 4070 insertions(+), 4 deletions(-)
 create mode 100644 arch/mips/dts/.gitignore
 create mode 100644 arch/mips/dts/Makefile
 create mode 12 arch/mips/dts/include/dt-bindings
 create mode 100644 arch/mips/dts/pic32mzda.dtsi
 create mode 100644 arch/mips/dts/pic32mzda_sk.dts
 create mode 100644 arch/mips/dts/skeleton.dtsi
 create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
 create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h
 create mode 100644 arch/mips/include/asm/gpio.h
 create mode 100644 

Re: [U-Boot] [PATCH v2 1/3] serial: uartlite: Move driver to DM

[Michal Simek]

On 17.12.2015 16:27, Simon Glass wrote:
> Hi Michal,
> 
> On 17 December 2015 at 06:58, Michal Simek  wrote:
>> On 17.12.2015 14:37, Thomas Chou wrote:
>>> Hi Michal,
>>>
>>> On 2015年12月17日 20:00, Michal Simek wrote:
 Enable SPL DM too.

 Signed-off-by: Michal Simek 
 ---

 Changes in v2:
 - Remove unneeded headers
 - Use get_dev_addr instead of fdtdec_get_addr
 - Use platdata instead of private data
 - Add opb compatible string to be in sync with Linux
 - Add binding documentation

   arch/microblaze/Kconfig|   1 +
   configs/microblaze-generic_defconfig   |   2 +
   .../serial/xilinx_uartlite.txt |  13 ++
   doc/driver-model/serial-howto.txt  |   1 -
   drivers/serial/serial_xuartlite.c  | 170
 -
   5 files changed, 78 insertions(+), 109 deletions(-)
   create mode 100644 doc/device-tree-bindings/serial/xilinx_uartlite.txt

 diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
 index 604f6815af5b..30ea484f48aa 100644
 --- a/arch/microblaze/Kconfig
 +++ b/arch/microblaze/Kconfig
 @@ -13,6 +13,7 @@ config TARGET_MICROBLAZE_GENERIC
   select SUPPORT_SPL
   select OF_CONTROL
   select DM
 +select DM_SERIAL

   endchoice

 diff --git a/configs/microblaze-generic_defconfig
 b/configs/microblaze-generic_defconfig
 index 54aa3ef3d26f..5df080b6a87c 100644
 --- a/configs/microblaze-generic_defconfig
 +++ b/configs/microblaze-generic_defconfig
 @@ -1,9 +1,11 @@
   CONFIG_MICROBLAZE=y
   CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 +CONFIG_SPL_DM=y
   CONFIG_TARGET_MICROBLAZE_GENERIC=y
   CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
   CONFIG_SPL=y
   CONFIG_SYS_PROMPT="U-Boot-mONStR> "
   CONFIG_CMD_GPIO=y
   # CONFIG_CMD_SETEXPR is not set
 +CONFIG_SPL_OF_CONTROL=y
   CONFIG_OF_EMBED=y
 diff --git a/doc/device-tree-bindings/serial/xilinx_uartlite.txt
 b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
 new file mode 100644
 index ..d15753c8c380
 --- /dev/null
 +++ b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
 @@ -0,0 +1,13 @@
 +Binding for Xilinx Uartlite Controller
 +
 +Required properties:
 +- compatible : should be "xlnx,xps-uartlite-1.00.a", or
 "xlnx,opb-uartlite-1.00.b"
 +- reg: Should contain UART controller registers location and length.
 +- interrupts: Should contain UART controller interrupts.
 +
 +Example:
 +serial@4060 {
 +compatible = "xlnx,xps-uartlite-1.00.a";
 +interrupts = <1 0>;
 +reg = <0x4060 0x1>;
 +};
 diff --git a/doc/driver-model/serial-howto.txt
 b/doc/driver-model/serial-howto.txt
 index 76ad629ef9cb..381a2a084562 100644
 --- a/doc/driver-model/serial-howto.txt
 +++ b/doc/driver-model/serial-howto.txt
 @@ -18,7 +18,6 @@ is time for maintainers to start converting over the
 remaining serial drivers:
  serial_pxa.c
  serial_s3c24x0.c
  serial_sa1100.c
 -   serial_xuartlite.c
  usbtty.c

   You should complete this by the end of January 2016.
 diff --git a/drivers/serial/serial_xuartlite.c
 b/drivers/serial/serial_xuartlite.c
 index 988438e75471..8225d9a320a5 100644
 --- a/drivers/serial/serial_xuartlite.c
 +++ b/drivers/serial/serial_xuartlite.c
 @@ -1,5 +1,5 @@
   /*
 - * (C) Copyright 2008-2011 Michal Simek 
 + * (C) Copyright 2008 - 2015 Michal Simek 
* Clean driver and add xilinx constant from header file
*
* (C) Copyright 2004 Atmark Techno, Inc.
 @@ -10,11 +10,15 @@

   #include 
   #include 
 +#include 
   #include 
   #include 
   #include 

 +DECLARE_GLOBAL_DATA_PTR;
 +
   #define SR_TX_FIFO_FULL0x08 /* transmit FIFO full */
 +#define SR_TX_FIFO_EMPTY0x04 /* transmit FIFO empty */
   #define SR_RX_FIFO_VALID_DATA0x01 /* data in receive FIFO */
   #define SR_RX_FIFO_FULL0x02 /* receive FIFO full */

 @@ -28,135 +32,85 @@ struct uartlite {
   unsigned int control;
   };

 -static struct uartlite *userial_ports[4] = {
 -#ifdef XILINX_UARTLITE_BASEADDR
 -[0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
 -#endif
 -#ifdef XILINX_UARTLITE_BASEADDR1
 -[1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
 -#endif
 -#ifdef XILINX_UARTLITE_BASEADDR2
 -[2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
 -#endif
 -#ifdef XILINX_UARTLITE_BASEADDR3
 -[3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
 -#endif
 +struct 

Re: [U-Boot] dm: Introduce SPI-NOR framework

[Jagan Teki]

Hi Simon,

On 15 December 2015 at 03:44, Simon Glass  wrote:
> Hi Jagan,
>
> On 11 December 2015 at 09:57, Jagan Teki  wrote:
>> Hi Simon,
>>
>> On 11 December 2015 at 07:35, Simon Glass  wrote:
>>> Hi Jagan,
>>>
>>> On 8 December 2015 at 08:36, Jagan Teki  wrote:
 Hi Simon,

 On 8 December 2015 at 08:22, Simon Glass  wrote:
> Hi Jagan,
>
> On 3 December 2015 at 03:10, Jagan Teki  wrote:
>> Hi Simon,
>>
>> I re-phrase all the question from previous thread and continue in this 
>> for
>> more discussion on spi-nor development.
>>
>>> Is it intended that SPI flash should be a driver for the MTD uclass?
>>> Others would be NAND and CFI. From what I can tell MTD has the same
>>> operations as SPI flash (erase, read, write) and adds a lot more.
>>>
>>> Or is SPI flash really a separate uclass from MTD, with SPI flash
>>> being at a higher level?
>>
>> Based on my "sf: MTD support" series SPI flash is a separate uclass from 
>> MTD
>> and it uses mtd_info operations.
>>
 cmd_sf
 ===
 MTD
 ===
 spi-nor or spi-flash
 ===
 "spi-nor to spi drivers" and spi-nor controller driver
 ===
>>> Your diagram above suggests that MTD calls into SPI NOR or SPI flash,
>>> but when I look at (for exampe) spi_flash_erase(), it is calling
>>> mtd_erase(), suggesting that it is above MTD in the software stack,
>>> the opposite of your diagram above.
>>>
>>
>> Will explain this clearly in below description.
>>
>>> Conceptually this seems problematic.
>>>
>>> SPI flash is a uclass and supports driver model. It has operations,
>>> etc. Your patches remove the operations in favour of calling MTD. But
>>> MTD does not support driver model. This is getting really messy.
>>>
>>
>> Will explain this clearly in below description.
>>
>>
>> Introducing SPI-NOR:
>> 
>>
>> Some of the spi drivers or spi controllers at drivers/spi/*
>> not a real spi controllers, unlike normal spi controllers
>> those operates varienty of spi devices among spi-nor flash is
>> one of them but instead these were specially designed for
>> to operate spi-nor flash devices - these are spi-nor controllers.
>> example: drivers/spi/fsl_qspi.c
>>
>> The problem with these were sitting at drivers/spi is entire
>> spi layer becomes spi-nor flash oriented which is absolutely
>> wrong indication where spi layer gets effected more with
>> flash operations - So this SPI-NOR will resolve this issue
>> by separating all spi-nor flash operations from spi layer
>> and by creating a generic layer called SPI-NOR core where it
>> deals with all SPI-NOR flash activities. The basic idea is
>> taken from Linux spi-nor framework.
>>
>> SPI-NOR Block diagram:
>> *
>>
>> =
>> cmd_sf.c
>> ===
>> spi_flash.h
>> ===
>> mtdcore.c
>> ===
>> spi-nor.c
>> 
>> m25p80.c fsl_qspi.c
>> ==   ===
>> spi-uclass   spi-nor hw
>> ==   ===
>> spi_drivers
>> ===
>> spi-bus hw
>> ==
>>
>> Note:
>> - spi-nor.c is a common core for m25p80.c which is a spi-nor to spi 
>> driver
>> interface layer and for fsl_qspi.c which is a typical spi-nor
>> controller driver.
>> - Challenging task is about probe.
>>
>> SPI-NOR Development plan:
>> *
>>
>> a) Adding MTD core support:
>>From command point of view the spi-flash is like a mtd device having
>> erase/write/read ops with offset, addr and size, but from lower layers 
>> the
>> spi-flash becomes either spi-nor or spi-nand so they have their own 
>> specific
>> features like struct spi_nor {}.
>>
>>This is the reason for calling MTD from command layer and the lower 
>> layer
>> as SPI_NOR uclass.
>>
>> b) Drop spi_flash uclass:
>>Since spi_flash is a generic term for serial flash devices among
>>these spi-nor and spi-nand are the real device categories so add
>>driver model to these categories.
>>
>> I sent the series [1] for above a) and b)
>
> It doesn't look like that series drops the SPI flash uclass.

 Yes, I have not dropped SPI flash uclass fully on the series only ops.

>
>>
>> c) Add spi-nor support (mean Adding SPI-NOR dm drivers) the next step.
>
> I think this is what I am missing. If you are moving to SPI NOR, what
> is the API? Is it the roughly the same as the 

[U-Boot] [PATCH v1 01/18] MIPS: Prepare device-tree support.

[Purna Chandra Mandal]

Signed-off-by: Purna Chandra Mandal 
---

 arch/Kconfig  |  1 +
 arch/mips/config.mk   |  3 +++
 arch/mips/dts/.gitignore  |  1 +
 arch/mips/dts/Makefile| 16 
 arch/mips/dts/include/dt-bindings |  1 +
 arch/mips/dts/skeleton.dtsi   | 21 +
 dts/Makefile  |  2 +-
 7 files changed, 44 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/.gitignore
 create mode 100644 arch/mips/dts/Makefile
 create mode 12 arch/mips/dts/include/dt-bindings
 create mode 100644 arch/mips/dts/skeleton.dtsi

diff --git a/arch/Kconfig b/arch/Kconfig
index 6489cc9..589fc47 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -54,6 +54,7 @@ config MIPS
 select HAVE_PRIVATE_LIBGCC
 select HAVE_GENERIC_BOARD
 select SYS_GENERIC_BOARD
+select SUPPORT_OF_CONTROL
 
 config NDS32
 bool "NDS32 architecture"
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 52e28f2..d4d688e 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -70,3 +70,6 @@ PLATFORM_RELFLAGS+= -ffunction-sections 
-fdata-sections
 LDFLAGS_FINAL+= --gc-sections -pie
 OBJCOPYFLAGS+= -j .text -j .rodata -j .data -j .got
 OBJCOPYFLAGS+= -j .u_boot_list -j .rel.dyn -j .padding
+ifdef CONFIG_OF_EMBED
+OBJCOPYFLAGS+= -j .dtb.init.rodata
+endif
diff --git a/arch/mips/dts/.gitignore b/arch/mips/dts/.gitignore
new file mode 100644
index 000..b60ed20
--- /dev/null
+++ b/arch/mips/dts/.gitignore
@@ -0,0 +1 @@
+*.dtb
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
new file mode 100644
index 000..724b5d2
--- /dev/null
+++ b/arch/mips/dts/Makefile
@@ -0,0 +1,16 @@
+#
+# SPDX-License-Identifier:GPL-2.0+
+#
+
+#dtb-$(CONFIG_XXX) += xxx.dtb
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS +=
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+@:
+
+clean-files := *.dtb
diff --git a/arch/mips/dts/include/dt-bindings 
b/arch/mips/dts/include/dt-bindings
new file mode 12
index 000..0cecb3d
--- /dev/null
+++ b/arch/mips/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../include/dt-bindings
\ No newline at end of file
diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi
new file mode 100644
index 000..ad41546
--- /dev/null
+++ b/arch/mips/dts/skeleton.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value.  The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+#address-cells = <1>;
+#size-cells = <1>;
+
+chosen {
+};
+
+aliases {
+};
+
+memory {
+device_type = "memory";
+reg = <0 0>;
+};
+};
diff --git a/dts/Makefile b/dts/Makefile
index d3122aa..5c3a01f 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -45,4 +45,4 @@ dtbs: $(obj)/dt.dtb
 clean-files := dt.dtb.S
 
 # Let clean descend into dts directories
-subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts 
../arch/x86/dts
+subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts 
../arch/x86/dts ../arch/mips/dts
-- 
1.8.3.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v1 02/18] MIPS: initial infrastructure for Microchip PIC32 architecture.

[Purna Chandra Mandal]

Signed-off-by: Purna Chandra Mandal 
---

 arch/mips/Kconfig|   5 ++
 arch/mips/Makefile   |   1 +
 arch/mips/include/asm/arch-pic32/clock.h |  31 +++
 arch/mips/include/asm/arch-pic32/pic32.h | 145 +++
 arch/mips/mach-pic32/Kconfig |  20 +
 arch/mips/mach-pic32/Makefile|   7 ++
 arch/mips/mach-pic32/config.mk   |   8 ++
 arch/mips/mach-pic32/cpu.c   |  13 +++
 8 files changed, 230 insertions(+)
 create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
 create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h
 create mode 100644 arch/mips/mach-pic32/Kconfig
 create mode 100644 arch/mips/mach-pic32/Makefile
 create mode 100644 arch/mips/mach-pic32/config.mk
 create mode 100644 arch/mips/mach-pic32/cpu.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7f7e258..2a707e2 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -51,6 +51,10 @@ config TARGET_PB1X00
 select SUPPORTS_CPU_MIPS32_R2
 select SYS_MIPS_CACHE_INIT_RAM_LOAD
 
+config MACH_PIC32
+bool "Support Microchip PIC32"
+select OF_CONTROL
+select DM
 
 endchoice
 
@@ -59,6 +63,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 43f0f5c..8b7c7e3 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -8,3 +8,4 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
+libs-$(CONFIG_MACH_PIC32) += arch/mips/mach-pic32/
diff --git a/arch/mips/include/asm/arch-pic32/clock.h 
b/arch/mips/include/asm/arch-pic32/clock.h
new file mode 100644
index 000..6a4270d
--- /dev/null
+++ b/arch/mips/include/asm/arch-pic32/clock.h
@@ -0,0 +1,31 @@
+/*
+ * (c) 2015 Purna Chandra Mandal purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_CLOCK_H_
+#define __PIC32_CLOCK_H_
+
+/* clk */
+enum {
+BASECLK,
+PLLCLK,
+MPLL,
+SYSCLK,
+PB1CLK,
+PB2CLK,
+PB3CLK,
+PB4CLK,
+PB5CLK,
+PB6CLK,
+PB7CLK,
+REF1CLK,
+REF2CLK,
+REF3CLK,
+REF4CLK,
+REF5CLK,
+};
+
+#endif/* __PIC32_CLOCK_H_ */
diff --git a/arch/mips/include/asm/arch-pic32/pic32.h 
b/arch/mips/include/asm/arch-pic32/pic32.h
new file mode 100644
index 000..4f2084f
--- /dev/null
+++ b/arch/mips/include/asm/arch-pic32/pic32.h
@@ -0,0 +1,145 @@
+/*
+ * (c) 2015 Paul Thacker 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_REGS_H__
+#define __PIC32_REGS_H__
+
+#define _CLR_OFFSET(0x4)
+#define _SET_OFFSET(0x8)
+#define _INV_OFFSET(0xc)
+
+/* System Configuration */
+#define PIC32_CFG_BASE(x) 0xbf80
+#define CFGCON(PIC32_CFG_BASE(x))
+#define DEVID(PIC32_CFG_BASE(x) + 0x0020)
+#define SYSKEY(PIC32_CFG_BASE(x) + 0x0030)
+#define PMD1(PIC32_CFG_BASE(x) + 0x0040)
+#define PMD7(PIC32_CFG_BASE(x) + 0x00a0)
+#define CFGEBIA(PIC32_CFG_BASE(x) + 0x00c0)
+#define CFGEBIC(PIC32_CFG_BASE(x) + 0x00d0)
+#define CFGPG(PIC32_CFG_BASE(x) + 0x00e0)
+#define CFGMPLL(PIC32_CFG_BASE(x) + 0x0100)
+
+/* Clock & Reset */
+#define RESET_BASE0xbf80
+
+/* Non Volatile Memory (NOR flash) */
+#define PIC32_NVM_BASE  (RESET_BASE + 0x0600)
+
+/* Reset Control Registers */
+#define RSWRST(RESET_BASE + 0x1250)
+
+/* Oscillator Configuration */
+#define OSCCON(RESET_BASE + 0x1200)
+#define SPLLCON(RESET_BASE + 0x1220)
+#define REFO1CON(RESET_BASE + 0x1280)
+#define REFO1TRIM(RESET_BASE + 0x1290)
+#define PB1DIV(RESET_BASE + 0x1340)
+
+/* Peripheral PORTA-PORTK / PORT0-PORT9 */
+enum {
+PIC32_PORT_A = 0,
+PIC32_PORT_B = 1,
+PIC32_PORT_C = 2,
+PIC32_PORT_D = 3,
+PIC32_PORT_E = 4,
+PIC32_PORT_F = 5,
+PIC32_PORT_G = 6,
+PIC32_PORT_H = 7,
+PIC32_PORT_J = 8, /* no PORT_I */
+PIC32_PORT_K = 9,
+PIC32_PORT_MAX
+};
+
+/* Peripheral Pin Select Input */
+#define PPS_IN_BASE0xbf80
+#define U1RXR(PPS_IN_BASE + 0x1468)
+#define U2RXR(PPS_IN_BASE + 0x1470)
+#define SDI1R(PPS_IN_BASE + 0x149c)
+#define SDI2R(PPS_IN_BASE + 0x14a8)
+
+/* Peripheral Pin Select Output */
+#define PPS_OUT_BASE0xbf801500
+#define PPS_OUT(prt, pi)(PPS_OUT_BASE + prt) * 16) + (pi)) << 2))
+#define RPA14RPPS_OUT(PIC32_PORT_A, 14)
+#define RPB0RPPS_OUT(PIC32_PORT_B, 0)
+#define RPB14RPPS_OUT(PIC32_PORT_B, 14)
+#define RPD0RPPS_OUT(PIC32_PORT_D, 0)
+#define RPD3RPPS_OUT(PIC32_PORT_D, 3)
+#define RPG8RPPS_OUT(PIC32_PORT_G, 8)
+#define RPG9RPPS_OUT(PIC32_PORT_G, 9)
+
+/* Peripheral Pin Control */
+#define 

[U-Boot] [PATCH v1 04/18] drivers: pinctrl: Add pinctrl driver for Microchip PIC32.

[Purna Chandra Mandal]

Signed-off-by: Purna Chandra Mandal 
---

 drivers/pinctrl/Kconfig |   6 ++
 drivers/pinctrl/Makefile|   1 +
 drivers/pinctrl/pinctrl_pic32.c | 173 
 3 files changed, 180 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl_pic32.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 57e6142..a4acaf3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -131,6 +131,12 @@ config PINCTRL_SANDBOX
   actually does nothing but print debug messages when pinctrl
   operations are invoked.
 
+config PIC32_PINCTRL
+bool "Microchip PIC32 pin-control driver"
+depends on DM && MACH_PIC32
+help
+  Support pin multiplexing control on Microchip PIC32 SoCs.
+
 endif
 
 source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 70d25dc..b4f4650 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_PINCTRL_SANDBOX)+= pinctrl-sandbox.o
 
 obj-$(CONFIG_ARCH_UNIPHIER)+= uniphier/
+obj-$(CONFIG_PIC32_PINCTRL)+= pinctrl_pic32.o
diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c
new file mode 100644
index 000..fdf436c
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_pic32.c
@@ -0,0 +1,173 @@
+/*
+ * Pinctrl driver for Microchip PIC32 SoCs
+ * Copyright (c) 2015 Microchip Technology Inc.
+ * Written by Purna Chandra Mandal 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+PERIPH_ID_UART1,
+PERIPH_ID_UART2,
+PERIPH_ID_ETH,
+PERIPH_ID_USB,
+PERIPH_ID_SDHCI,
+PERIPH_ID_I2C1,
+PERIPH_ID_I2C2,
+PERIPH_ID_SPI1,
+PERIPH_ID_SPI2,
+PERIPH_ID_SQI,
+};
+
+static void _eth_pin_config(void)
+{
+/*
+ * PORT D pin configuration settings
+ *
+ * Reg   Bit  I/ODig/Ana
+ * EMDC  RD11 Output Digital
+ * ETXEN RD6  Output Digital
+ *
+ */
+writel(0x0840, ANSELCLR(PIC32_PORT_D));  /* set to digital mode */
+writel(0x0840, TRISCLR(PIC32_PORT_D));   /* set to output mode  */
+
+/*
+ * PORT H pin configuration settings
+ *
+ * RegBit  I/ODig/Ana   PullUp/Down
+ * ECRSDV RH13 Input  Digital
+ * ERXD0  RH8  Input  Digital   Down
+ * ERXD1  RH5  Input  Digital   Down
+ */
+writel(0x2120, ANSELCLR(PIC32_PORT_H));  /* set to digital mode */
+writel(0x2120, TRISSET(PIC32_PORT_H));   /* set to input mode */
+
+/*
+ * PORT J pin configuration settings
+ *
+ * Reg Bit  I/ODig/Ana
+ * EREFCLK RJ11 Input  Digital
+ * ETXD1   RJ9  Output Digital
+ * ETXD0   RJ8  Output Digital
+ * EMDIO   RJ1  Input  Digital
+ *
+ */
+writel(0x0b02, ANSELCLR(PIC32_PORT_J)); /* set to digital mode */
+writel(0x0300, TRISCLR(PIC32_PORT_J));  /* set pins to output mode  */
+writel(0x0802, TRISSET(PIC32_PORT_J));  /* set pins to input mode  */
+
+/*
+ * PORT F pin configuration settings
+ * RegBit  I/ODig/Ana
+ * ERXERR RF3  Input  Digital
+ */
+writel(0x10, ANSELCLR(PIC32_PORT_F));  /* set to digital mode */
+writel(0x10, TRISSET(PIC32_PORT_F));   /* set to input mode */
+}
+
+static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+switch (func) {
+case PERIPH_ID_UART2:
+/* PPS for U2 RX/TX */
+writel(0x0002, RPG9R); /* G9 */
+writel(0x0005, U2RXR); /* B0 */
+/* digital mode */
+writel(0x0001, ANSELCLR(PIC32_PORT_B));
+writel(0x0200, ANSELCLR(PIC32_PORT_G));
+break;
+case PERIPH_ID_ETH:
+_eth_pin_config();
+break;
+case PERIPH_ID_SDHCI:
+break;
+case PERIPH_ID_USB:
+break;
+default:
+debug("%s: unknown-unhandled case\n", __func__);
+break;
+}
+
+return 0;
+}
+
+static int pic32_pinctrl_get_periph_id(struct udevice *dev,
+   struct udevice *periph)
+{
+int ret;
+u32 cell[2];
+
+ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+   "interrupts", cell, ARRAY_SIZE(cell));
+if (ret < 0)
+return -EINVAL;
+
+/* interrupt number */
+switch (cell[0]) {
+case 112 ... 114:
+return PERIPH_ID_UART1;
+case 145 ... 147:
+return PERIPH_ID_UART2;
+case 109 ... 111:
+return PERIPH_ID_SPI1;
+case 142 ... 144:
+return PERIPH_ID_SPI2;
+case 115 ... 117:
+return PERIPH_ID_I2C1;
+case 148 ... 150:
+return PERIPH_ID_I2C2;
+case 132 ... 133:
+return PERIPH_ID_USB;
+case 169:
+return PERIPH_ID_SQI;
+case 191:
+return PERIPH_ID_SDHCI;
+case 153:
+return 

[U-Boot] [PATCH v1 15/18] drivers: mmc: add driver for Microchip PIC32, SDHCI controller.

[Purna Chandra Mandal]

From: Andrei Pistirica 

This driver implements platform specific glue and fix-ups for SDHCI host 
controller.

Signed-off-by: Andrei Pistirica 
Signed-off-by: Purna Chandra Mandal 
---

 drivers/mmc/Kconfig   |   6 +++
 drivers/mmc/Makefile  |   2 +-
 drivers/mmc/pic32_sdhci.c | 110 ++
 3 files changed, 117 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mmc/pic32_sdhci.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index ceae7bc..0b6f54b 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -31,4 +31,10 @@ config SH_SDHI
 help
   Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs 
platform
 
+config PIC32_SDHCI
+bool "Microchip PIC32 on-chip SDHCI support"
+depends on DM_MMC && MACH_PIC32
+help
+  Support for the on-chip SDHCI support on Microchip PIC32 platforms.
+
 endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 5d35705..c9c3e3e 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -48,4 +48,4 @@ obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
 else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
-
+obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c
new file mode 100644
index 000..4fe0825
--- /dev/null
+++ b/drivers/mmc/pic32_sdhci.c
@@ -0,0 +1,110 @@
+/*
+ * Support of SDHCI devices for Microchip PIC32 SoC.
+ *
+ * Copyright (C) 2015 Microchip Technology Inc.
+ * Andrei Pistirica 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* SDHCI capabilities bits */
+#define SDHCI_CAPS_SLOT_TYPE_MASK0xC000
+#define  SLOT_TYPE_REMOVABLE0x0
+#define  SLOT_TYPE_EMBEDDED0x1
+#define  SLOT_TYPE_SHARED_BUS0x2
+
+/* SDHCI Shared Bus Control */
+#define SDHCI_SHARED_BUS_CTRL0xE0
+#define  SDHCI_SHARED_BUS_NR_CLK_PINS_MASK0x7
+#define  SDHCI_SHARED_BUS_NR_IRQ_PINS_MASK0x30
+#define  SDHCI_SHARED_BUS_CLK_PINS0x10
+#define  SDHCI_SHARED_BUS_IRQ_PINS0x14
+
+static int pic32_sdhci_set_shared(struct sdhci_host *host, u32 clk, u32 irq)
+{
+unsigned int caps;
+u32 bus, caps_slot_type;
+u32 clk_pins, irq_pins;
+
+/* Card slot connected on shared bus? */
+caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+caps_slot_type = ((caps & SDHCI_CAPS_SLOT_TYPE_MASK) >> 30);
+if (caps_slot_type != SLOT_TYPE_SHARED_BUS)
+return 0;
+
+bus = sdhci_readl(host, SDHCI_SHARED_BUS_CTRL);
+clk_pins = (bus & SDHCI_SHARED_BUS_NR_CLK_PINS_MASK) >> 0;
+irq_pins = (bus & SDHCI_SHARED_BUS_NR_IRQ_PINS_MASK) >> 4;
+
+/* Select first clock */
+if (clk_pins & clk)
+bus |= (clk << SDHCI_SHARED_BUS_CLK_PINS);
+
+/* Select first interrupt */
+if (irq_pins & irq)
+bus |= (irq << SDHCI_SHARED_BUS_IRQ_PINS);
+
+sdhci_writel(host, bus, SDHCI_SHARED_BUS_CTRL);
+return 0;
+}
+
+static int pic32_sdhci_probe(struct udevice *dev)
+{
+struct sdhci_host *host = dev_get_priv(dev);
+u32 minmax[2], shared_clk_irq[2];
+int ret;
+
+ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+   "clock-freq-min-max", minmax, 2);
+if (ret)
+goto _out;
+
+ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+   "clock-irq-pins", shared_clk_irq, 2);
+if (!ret)
+ret = pic32_sdhci_set_shared(host, shared_clk_irq[1],
+ shared_clk_irq[0]);
+
+if (ret)
+goto _out;
+
+return add_sdhci(host, minmax[1], minmax[0]);
+
+_out:
+return ret;
+}
+
+
+static int pic32_sdhci_ofdata_to_platdata(struct udevice *dev)
+{
+struct sdhci_host *host = dev_get_priv(dev);
+
+host->name= (char *)dev->name;
+host->ioaddr= (void *)dev_get_addr(dev);
+host->quirks= SDHCI_QUIRK_NO_HISPD_BIT;
+host->bus_width= fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+"bus-width", 4);
+return 0;
+}
+static const struct udevice_id pic32_sdhci_ids[] = {
+{ .compatible = "microchip,pic32mzda-sdhci" },
+{ }
+};
+
+U_BOOT_DRIVER(pic32_sdhci_drv) = {
+.name= "pic32_sdhci",
+.id= UCLASS_MMC,
+.of_match= pic32_sdhci_ids,
+.probe= pic32_sdhci_probe,
+.ofdata_to_platdata= pic32_sdhci_ofdata_to_platdata,
+.priv_auto_alloc_size= sizeof(struct sdhci_host),
+};
-- 
1.8.3.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v1 16/18] drivers: mmc: PIC32MZ[DA] SDHCI errata fix when JTAG is not connected.

[Purna Chandra Mandal]

From: Sandeep Sheriker Mallikarjun 

In PIC32MZ[DA] SoC JTAG and Card_Detect signal are muxed. These created one h/w 
bug;
SDHCI will not detect micro-SD card if JTAG is not connected. To fix this 
errata,
 - set Card_Detect_Signal_Selection bit in SDHC HostControl register and
 - clear CardDetectTestLevel bit in SDHC HostControl register.

Signed-off-by: Sandeep Sheriker Mallikarjun 

Signed-off-by: Purna Chandra Mandal 
---

 drivers/mmc/sdhci.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 02d71b9..f32fe67 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -424,6 +424,18 @@ static void sdhci_set_ios(struct mmc *mmc)
 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
 ctrl &= ~SDHCI_CTRL_HISPD;
 
+#if defined(CONFIG_PIC32_SDHCI)
+/*
+* In PIC32MZ[DA] due to h/w bug SDHCI fails detecting card when JTAG
+* is not connected.
+* To work-around this problem:
+*  - set Card_Detect_Signal_Selection bit in SDHCI_Host_Control register
+*  - clear Card_Detect_Test_Level bit in SDHCI_Host_Control register
+*/
+ctrl |= SDHCI_CTRL_CD_TEST;
+ctrl &= ~SDHCI_CTRL_CD_TEST_INS;
+#endif
+
 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 }
 
-- 
1.8.3.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v1 01/18] MIPS: Prepare device-tree support.

[Purna Chandra Mandal]

On 12/17/2015 11:17 PM, Marek Vasut wrote:
> On Thursday, December 17, 2015 at 06:28:08 PM, Purna Chandra Mandal wrote:
>> Signed-off-by: Purna Chandra Mandal 
>> ---
>>
>>  arch/Kconfig  |  1 +
>>  arch/mips/config.mk   |  3 +++
>>  arch/mips/dts/.gitignore  |  1 +
>>  arch/mips/dts/Makefile| 16 
>>  arch/mips/dts/include/dt-bindings |  1 +
>>  arch/mips/dts/skeleton.dtsi   | 21 +
>>  dts/Makefile  |  2 +-
>>  7 files changed, 44 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/mips/dts/.gitignore
>>  create mode 100644 arch/mips/dts/Makefile
>>  create mode 12 arch/mips/dts/include/dt-bindings
>>  create mode 100644 arch/mips/dts/skeleton.dtsi
>>
>> diff --git a/arch/Kconfig b/arch/Kconfig
>> index 6489cc9..589fc47 100644
>> --- a/arch/Kconfig
>> +++ b/arch/Kconfig
>> @@ -54,6 +54,7 @@ config MIPS
>>  select HAVE_PRIVATE_LIBGCC
>>  select HAVE_GENERIC_BOARD
>>  select SYS_GENERIC_BOARD
>> +select SUPPORT_OF_CONTROL
>>
>>  config NDS32
>>  bool "NDS32 architecture"
>> diff --git a/arch/mips/config.mk b/arch/mips/config.mk
>> index 52e28f2..d4d688e 100644
>> --- a/arch/mips/config.mk
>> +++ b/arch/mips/config.mk
>> @@ -70,3 +70,6 @@ PLATFORM_RELFLAGS+= -ffunction-sections
>> -fdata-sections LDFLAGS_FINAL+= --gc-sections -pie
>>  OBJCOPYFLAGS+= -j .text -j .rodata -j .data -j .got
>>  OBJCOPYFLAGS+= -j .u_boot_list -j .rel.dyn -j .padding
>> +ifdef CONFIG_OF_EMBED
>> +OBJCOPYFLAGS+= -j .dtb.init.rodata
>> +endif
>> diff --git a/arch/mips/dts/.gitignore b/arch/mips/dts/.gitignore
>> new file mode 100644
>> index 000..b60ed20
>> --- /dev/null
>> +++ b/arch/mips/dts/.gitignore
>> @@ -0,0 +1 @@
>> +*.dtb
>> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
>> new file mode 100644
>> index 000..724b5d2
>> --- /dev/null
>> +++ b/arch/mips/dts/Makefile
>> @@ -0,0 +1,16 @@
>> +#
>> +# SPDX-License-Identifier:GPL-2.0+
>> +#
>> +
>> +#dtb-$(CONFIG_XXX) += xxx.dtb
> XXX ?

ack. will remove.

>> +targets += $(dtb-y)
>> +
>> +# Add any required device tree compiler flags here
>> +DTC_FLAGS +=
>> +
>> +PHONY += dtbs
>> +dtbs: $(addprefix $(obj)/, $(dtb-y))
>> +@:
>> +
>> +clean-files := *.dtb
>> diff --git a/arch/mips/dts/include/dt-bindings
>> b/arch/mips/dts/include/dt-bindings new file mode 12
>> index 000..0cecb3d
>> --- /dev/null
>> +++ b/arch/mips/dts/include/dt-bindings
>> @@ -0,0 +1 @@
>> +../../../../include/dt-bindings
>> \ No newline at end of file
>> diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi
>> new file mode 100644
>> index 000..ad41546
>> --- /dev/null
>> +++ b/arch/mips/dts/skeleton.dtsi
>> @@ -0,0 +1,21 @@
>> +/*
>> + * Skeleton device tree; the bare minimum needed to boot; just include and
>> + * add a compatible value.  The bootloader will typically populate the
>> memory + * node.
>> + */
>> +
>> +/ {
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +
>> +chosen {
>> +};
>> +
>> +aliases {
>> +};
>> +
>> +memory {
>> +device_type = "memory";
>> +reg = <0 0>;
>> +};
> You don't need any of these nodes, do you ?

ack. This is skeleton code copied from arm, might be needed by others. will 
remove as not needed by me.

>> +};
>> diff --git a/dts/Makefile b/dts/Makefile
>> index d3122aa..5c3a01f 100644
>> --- a/dts/Makefile
>> +++ b/dts/Makefile
>> @@ -45,4 +45,4 @@ dtbs: $(obj)/dt.dtb
>>  clean-files := dt.dtb.S
>>
>>  # Let clean descend into dts directories
>> -subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts
>> ../arch/x86/dts +subdir- += ../arch/arm/dts ../arch/microblaze/dts
>> ../arch/sandbox/dts ../arch/x86/dts ../arch/mips/dts

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] u-boot 2016.01-rc2 detects BeagleBone Black incorrectly

[Matwey V. Kornilov]

2015-12-17 3:53 GMT+03:00 Robert Nelson :
> Hi Matwey
>
> On Sat, Dec 12, 2015 at 3:14 AM, Matwey V. Kornilov
>  wrote:
>> Hello,
>>
>> I am running 2016.01-rc on BBB (Embest replica)
>>
>> printenv shows the following:
>>
>> findfdt=if test $board_name = A335BONE; then setenv fdtfile
>> am335x-bone.dtb; fi; if test $board_name = A335BNLT; then if test
>> $board_rev = BBG1; then setenv fdtfile am335x-bonegreen.dtb; else setenv
>> fdtfile am335x-boneblack.dtb; fi; fi; if test $board_name = A33515BB;
>> then setenv fdtfile am335x-evm.dtb; fi; if test $board_name = A335X_SK;
>> then setenv fdtfile am335x-evmsk.dtb; fi; if test $fdtfile = undefined;
>> then echo WARNING: Could not determine device tree to use; fi;
>>
>> after findfdt has been run,
>>
>> fdtfile=am335x-bonegreen.dtb
>>
>> But it is not correct. My $board_rev is the following, I have no idea
>> why does it contain line break.
>>
>> board_name=A335BNLT
>> board_rev=t\
>
> Yuck, another variation!  Can you do me a favor and dump the eeprom:
>
> https://github.com/beagleboard/image-builder/blob/master/readme.md
>
> Download and run:
>
> wget 
> https://raw.githubusercontent.com/RobertCNelson/boot-scripts/master/device/bone/tester/show-eeprom.sh
>
> sudo /bin/bash show-eeprom.sh

# sudo /bin/bash show-eeprom.sh
eeprom: [�U3�A335BNLTt
ue]
eeprom raw: [  aa 55 33 ee 41 33 33 35  42 4e 4c 54 74 0a 75
65  |.U3.A335BNLTt.ue|]


>
> It uses hexdump and compatible with bb.org' 3.8/4.1/etc..
>
> The green should only trigger on: 0x1a 0x00 0x00 0x00
>
> http://git.denx.de/?p=u-boot.git;a=blobdiff;f=board/ti/am335x/board.c;h=f56d17ec58e17a6532b5df649249b4038b475897;hp=f0cb1e204ad550622df7848a993f1eb2f173bc43;hb=dfd1bb4ec89e8b1e87f0605af2345ad6dcf777da;hpb=e4aa8edb6e5cae256a5c5a3c5cd30e05e8f5a2b4
>
> Regards,
>
> --
> Robert Nelson
> https://rcn-ee.com/



-- 
With best regards,
Matwey V. Kornilov
http://blog.matwey.name
xmpp://0x2...@jabber.ru
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v1 05/18] drivers: serial: add driver for Microchip PIC32 UART controller.

[Marek Vasut]

On Thursday, December 17, 2015 at 06:29:32 PM, Purna Chandra Mandal wrote:

Hi!

Minor nits below.

btw do we expect MIPS to become maintained in U-Boot? That's nice :)

[...]

> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index dd87147..57cd38b 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o
>  obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
>  obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
>  obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
> +obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
> 
>  ifndef CONFIG_SPL_BUILD
>  obj-$(CONFIG_USB_TTY) += usbtty.o
> diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
> new file mode 100644
> index 000..01c62e7
> --- /dev/null
> +++ b/drivers/serial/serial_pic32.c
> @@ -0,0 +1,220 @@
> +/*
> + * (c) 2015 Paul Thacker 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + *
> + */
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_ENABLEBIT(15)
> +#define UART_ENABLE_RXBIT(12)
> +#define UART_ENABLE_TXBIT(10)
> +#define UART_RX_DATA_AVAILBIT(0)
> +#define UART_RX_OERRBIT(1)
> +#define UART_TX_FULLBIT(9)
> +
> +/* UART Control */
> +#define U_BASE(x)(x)
> +#define U_MODE(x)   U_BASE(x)
> +#define U_MODECLR(x)(U_MODE(x) + _CLR_OFFSET)
> +#define U_MODESET(x)(U_MODE(x) + _SET_OFFSET)
> +#define U_STA(x)(U_BASE(x) + 0x10)
> +#define U_STACLR(x) (U_STA(x) + _CLR_OFFSET)
> +#define U_STASET(x) (U_STA(x) + _SET_OFFSET)
> +#define U_TXREG(x)  (U_BASE(x) + 0x20)
> +#define U_RXREG(x)  (U_BASE(x) + 0x30)
> +#define U_BRG(x)(U_BASE(x) + 0x40)

Why don't you just use uart_priv->regs + PIC32_REGISTER_OFFSET in the code?
The U_BASE is redundant and so is UMODE.

> +struct pic32_uart_priv {
> +void __iomem *regs;
> +ulong uartclk;
> +};
> +
> +static void pic32_serial_setbrg(void __iomem *regs, ulong uart_clk, u32
> baud) +{
> +writel(0, U_BRG(regs));
> +writel((uart_clk / baud / 16) - 1, U_BRG(regs));
> +udelay(100);
> +}
> +
> +/*
> + * Initialize the serial port with the given baudrate.
> + * The settings are always 8 data bits, no parity, 1 stop bit, no start
> bits. + */
> +static int pic32_serial_init(void __iomem *regs, ulong clk, u32 baudrate)
> +{
> +/* disable and clear mode */
> +writel(0, U_MODE(regs));
> +writel(0, U_STA(regs));
> +
> +/* set baud rate generator */
> +pic32_serial_setbrg(regs, clk, baudrate);
> +
> +/* enable the UART for TX and RX */
> +writel(UART_ENABLE_TX | UART_ENABLE_RX, U_STASET(regs));
> +
> +/* enable the UART */
> +writel(UART_ENABLE, U_MODESET(regs));
> +return 0;
> +}
> +
> +/* Output a single byte to the serial port */
> +static void pic32_serial_putc(void __iomem *regs, const char c)
> +{
> +/* if \n, then add a \r */
> +if (c == '\n')
> +pic32_serial_putc(regs, '\r');
> +
> +/* Wait for Tx FIFO not full */
> +while (readl(U_STA(regs)) & UART_TX_FULL)
> +;
> +
> +/* stuff the tx buffer with the character */
> +writel(c, U_TXREG(regs));
> +}
> +
> +/* Test whether a character is in the RX buffer */
> +static int pic32_serial_tstc(void __iomem *regs)
> +{
> +/* check if rcv buf overrun error has occurred */
> +if (readl(U_STA(regs)) & UART_RX_OERR) {
> +readl(U_RXREG(regs));
> +
> +/* clear OERR to keep receiving */
> +writel(UART_RX_OERR, U_STACLR(regs));
> +}
> +
> +if (readl(U_STA(regs)) & UART_RX_DATA_AVAIL)
> +return 1;/* yes, there is data in rcv buffer */
> +else
> +return 0;/* no data in rcv buffer */

return readl() & UART_RX_DATA_AVAIL; is sufficient here.

> +}
> +
> +/*
> + * Read a single byte from the rx buffer.
> + * Blocking: waits until a character is received, then returns.
> + * Return the character read directly from the UART's receive register.
> + *
> + */
> +static int pic32_serial_getc(void __iomem *regs)
> +{
> +/* wait here until data is available */
> +while (!pic32_serial_tstc(regs))
> +;
> +
> +/* read the character from the rcv buffer */
> +return readl(U_RXREG(regs));

return readl() & 0xff, since the return value is a signed integer.

> +}

[...]

> +U_BOOT_DRIVER(pic32_serial) = {
> +.name= "pic32-uart",
> +.id= UCLASS_SERIAL,
> +.of_match= pic32_uart_ids,
> +.probe= pic32_uart_probe,
> +.ops= _uart_ops,
> +.flags= DM_FLAG_PRE_RELOC,
> +.ofdata_to_platdata = pic32_uart_ofdata_to_platdata,
> +.platdata_auto_alloc_size = sizeof(struct pic32_uart_priv),

Is there some problem with tab/space conversion going on in here?

> +};
> +

[...]

Re: [U-Boot] [PATCH v1 05/18] drivers: serial: add driver for Microchip PIC32 UART controller.

[Purna Chandra Mandal]

On 12/17/2015 11:22 PM, Marek Vasut wrote:
> On Thursday, December 17, 2015 at 06:29:32 PM, Purna Chandra Mandal wrote:
>
> Hi!
>
> Minor nits below.
>
> btw do we expect MIPS to become maintained in U-Boot? That's nice :)
>
> [...]
>
>> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
>> index dd87147..57cd38b 100644
>> --- a/drivers/serial/Makefile
>> +++ b/drivers/serial/Makefile
>> @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o
>>  obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
>>  obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
>>  obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
>> +obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
>>
>>  ifndef CONFIG_SPL_BUILD
>>  obj-$(CONFIG_USB_TTY) += usbtty.o
>> diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
>> new file mode 100644
>> index 000..01c62e7
>> --- /dev/null
>> +++ b/drivers/serial/serial_pic32.c
>> @@ -0,0 +1,220 @@
>> +/*
>> + * (c) 2015 Paul Thacker 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + *
>> + */
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define UART_ENABLEBIT(15)
>> +#define UART_ENABLE_RXBIT(12)
>> +#define UART_ENABLE_TXBIT(10)
>> +#define UART_RX_DATA_AVAILBIT(0)
>> +#define UART_RX_OERRBIT(1)
>> +#define UART_TX_FULLBIT(9)
>> +
>> +/* UART Control */
>> +#define U_BASE(x)(x)
>> +#define U_MODE(x)   U_BASE(x)
>> +#define U_MODECLR(x)(U_MODE(x) + _CLR_OFFSET)
>> +#define U_MODESET(x)(U_MODE(x) + _SET_OFFSET)
>> +#define U_STA(x)(U_BASE(x) + 0x10)
>> +#define U_STACLR(x) (U_STA(x) + _CLR_OFFSET)
>> +#define U_STASET(x) (U_STA(x) + _SET_OFFSET)
>> +#define U_TXREG(x)  (U_BASE(x) + 0x20)
>> +#define U_RXREG(x)  (U_BASE(x) + 0x30)
>> +#define U_BRG(x)(U_BASE(x) + 0x40)
> Why don't you just use uart_priv->regs + PIC32_REGISTER_OFFSET in the code?
> The U_BASE is redundant and so is UMODE.

ack. Will update.

>> +struct pic32_uart_priv {
>> +void __iomem *regs;
>> +ulong uartclk;
>> +};
>> +
>> +static void pic32_serial_setbrg(void __iomem *regs, ulong uart_clk, u32
>> baud) +{
>> +writel(0, U_BRG(regs));
>> +writel((uart_clk / baud / 16) - 1, U_BRG(regs));
>> +udelay(100);
>> +}
>> +
>> +/*
>> + * Initialize the serial port with the given baudrate.
>> + * The settings are always 8 data bits, no parity, 1 stop bit, no start
>> bits. + */
>> +static int pic32_serial_init(void __iomem *regs, ulong clk, u32 baudrate)
>> +{
>> +/* disable and clear mode */
>> +writel(0, U_MODE(regs));
>> +writel(0, U_STA(regs));
>> +
>> +/* set baud rate generator */
>> +pic32_serial_setbrg(regs, clk, baudrate);
>> +
>> +/* enable the UART for TX and RX */
>> +writel(UART_ENABLE_TX | UART_ENABLE_RX, U_STASET(regs));
>> +
>> +/* enable the UART */
>> +writel(UART_ENABLE, U_MODESET(regs));
>> +return 0;
>> +}
>> +
>> +/* Output a single byte to the serial port */
>> +static void pic32_serial_putc(void __iomem *regs, const char c)
>> +{
>> +/* if \n, then add a \r */
>> +if (c == '\n')
>> +pic32_serial_putc(regs, '\r');
>> +
>> +/* Wait for Tx FIFO not full */
>> +while (readl(U_STA(regs)) & UART_TX_FULL)
>> +;
>> +
>> +/* stuff the tx buffer with the character */
>> +writel(c, U_TXREG(regs));
>> +}
>> +
>> +/* Test whether a character is in the RX buffer */
>> +static int pic32_serial_tstc(void __iomem *regs)
>> +{
>> +/* check if rcv buf overrun error has occurred */
>> +if (readl(U_STA(regs)) & UART_RX_OERR) {
>> +readl(U_RXREG(regs));
>> +
>> +/* clear OERR to keep receiving */
>> +writel(UART_RX_OERR, U_STACLR(regs));
>> +}
>> +
>> +if (readl(U_STA(regs)) & UART_RX_DATA_AVAIL)
>> +return 1;/* yes, there is data in rcv buffer */
>> +else
>> +return 0;/* no data in rcv buffer */
> return readl() & UART_RX_DATA_AVAIL; is sufficient here.

ack.

>> +}
>> +
>> +/*
>> + * Read a single byte from the rx buffer.
>> + * Blocking: waits until a character is received, then returns.
>> + * Return the character read directly from the UART's receive register.
>> + *
>> + */
>> +static int pic32_serial_getc(void __iomem *regs)
>> +{
>> +/* wait here until data is available */
>> +while (!pic32_serial_tstc(regs))
>> +;
>> +
>> +/* read the character from the rcv buffer */
>> +return readl(U_RXREG(regs));
> return readl() & 0xff, since the return value is a signed integer.

ack.

>> +}
> [...]
>
>> +U_BOOT_DRIVER(pic32_serial) = {
>> +.name= "pic32-uart",
>> +.id= UCLASS_SERIAL,
>> +.of_match= pic32_uart_ids,
>> +.probe= pic32_uart_probe,
>> +.ops= _uart_ops,
>> +.flags= DM_FLAG_PRE_RELOC,
>> +   

Re: [U-Boot] [PATCH v1 07/18] board: Add Microchip PIC32MZ[DA] Starter Kit board.

[Marek Vasut]

On Thursday, December 17, 2015 at 06:30:38 PM, Purna Chandra Mandal wrote:
[...]

> diff --git a/board/microchip/pic32mzda/config.mk
> b/board/microchip/pic32mzda/config.mk new file mode 100644
> index 000..a12e712
> --- /dev/null
> +++ b/board/microchip/pic32mzda/config.mk
> @@ -0,0 +1,4 @@
> +#
> +# Microchip PIC32MZ[DA] board (PIC32 SoC powered by MIPS M14KEc CPU)
> +#
> +CONFIG_SYS_TEXT_BASE = 0x9d004000
> diff --git a/board/microchip/pic32mzda/ddr.c
> b/board/microchip/pic32mzda/ddr.c new file mode 100644
> index 000..31a44fa
> --- /dev/null
> +++ b/board/microchip/pic32mzda/ddr.c
> @@ -0,0 +1,389 @@
> +/*
> + * (c) 2015 Paul Thacker 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + *
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "ddr.h"
> +
> +/* macros */
> +#define hc_clk_dly(dly)\
> +(max_t(u32, (DIV_ROUND_UP((dly), CLK_PERIOD)), 2) - 2)
> +
> +/* Host Commands */
> +#define IDLE_NOP0x00FF
> +#define PRECH_ALL_CMD0x00FFF401
> +#define REF_CMD0x00FFF801
> +#define LOAD_MODE_CMD0x00FFF001
> +#define CKE_LOW0x00FFEFFE
> +
> +#define NUM_HOST_CMDS12
> +
> +/* DDR address decoding */
> +#define COL_HI_RSHFT0
> +#define COL_HI_MASK0
> +#define COL_LO_MASK((1 << COL_BITS) - 1)
> +
> +#define BA_RSHFTCOL_BITS
> +#define BANK_ADDR_MASK((1 << BA_BITS) - 1)
> +
> +#define ROW_ADDR_RSHIFT(BA_RSHFT + BA_BITS)
> +#define ROW_ADDR_MASK((1 << ROW_BITS) - 1)
> +
> +#define CS_ADDR_RSHIFT0
> +#define CS_ADDR_MASK0
> +
> +/* MPLL freq is 400MHz */
> +#define CLK_PERIOD  2500/* 2500 psec */
> +#define CTRL_CLK_PERIOD (CLK_PERIOD * 2)
> +
> +/* Arbiter */
> +#define NUM_AGENTS  5
> +#define MIN_LIM_WIDTH   5
> +#define RQST_PERIOD_WIDTH   8
> +#define MIN_CMDACPT_WIDTH   8
> +
> +#define EN_AUTO_PRECH   0
> +#define SB_PRI  1
> +#define BIG_ENDIAN  0
> +#define HALF_RATE_MODE  1
> +
> +/*
> / +/* DDR definitions */
> +/*
> / +
> +/* DDR Address Mapping: CS, ROW, BA, COL */
> +#define COL_BITS10
> +#define ROW_BITS13
> +#define BA_BITS3
> +#define CS_BITS1

OK, so how many copies of this code will we have by the end of the day ?
One for each board ? That ain't gonna work ...

> +/* DDR constants */
> +#define BL2/* Burst length in cycles */
> +
> +/* default CAS latency for all speed grades */
> +#define RL5
> +
> +/* default write latency for all speed grades = CL-1 */
> +#define WL4
> +
> +#define MAX_BURST3
> +
> +/* NOTE: DDR data from Micron MT47H64M16HR-3 data sheet */
> +#define tRFC_MIN127500/* psec */
> +#define tWR15000/* psec */
> +#define tRP12500/* psec */
> +#define tRCD12500/* psec */
> +#define tRRD7500/* psec */

This is board specific, but the code is not I believe. So the common code
should go into drivers/ddr/

> +/* tRRD_TCK is a minimum of 2 clk periods, regardless of clk freq */
> +#define tRRD_TCK2
> +#define tWTR7500/* psec */

[...]

> +/* ODT Config */
> +writel(0x, DDR2ODTCFG);
> +writel(0x0001, DDR2ODTENCFG);/* WREN on CS */
> +
> +writel(((RL - 3) << 8) | ((WL - 3) << 12) | (2 << 16) | (3 << 20),
> +   DDR2ODTCFG);
> +
> +/* TODO: resolve differences in NXTDATRQDLY, NXDATAVDLY and RDATENDLY
> */ +writel(/*(WL - 1)*/2 | (/*((RL + 1) & 0x0F)*/4  << 4) |
> +   (/*(RL - 1)*/2 << 16) |
> +   (MAX_BURST << 24) | (7 << 28) | (BIG_ENDIAN << 31),
> +   DDR2XFERCFG);

Fixme please ;-)

> +/* DRAM Initialization */
> +/* bring CKE high after reset and wait 400 nsec */
> +writel(IDLE_NOP, DDR2CMD10);
> +writel((0x00 | (0x00 << 8) | (hc_clk_dly(40) << 11)),
> +   DDR2CMD20);
> +
> +/* issue precharge all command */
> +writel(PRECH_ALL_CMD, DDR2CMD10 + 0x04);
> +writel((0x04 | (0x00 << 8) | (hc_clk_dly(tRP + CLK_PERIOD) << 11)),
> +   DDR2CMD20 + 0x04);
> +
> +/* initialize EMR2 */
> +writel(LOAD_MODE_CMD, DDR2CMD10 + 0x08);
> +writel((0x00 | (0x02 << 8) | (hc_clk_dly(tMRD * CLK_PERIOD) << 11)),
> +   DDR2CMD20 + 0x08);

[...]

> +writel(0x1B, DDR2CMDISSUE);
> +writel(0x01, DDR2MEMCON);
> +
> +while (readl(DDR2CMDISSUE) & 0x10)
> +;

Use the wait_for_bit() function here and for the other unbounded while loop 
below. This will add timeout to the wait, so your code will not get stuck in
an endless loop.

> +writel(0x03, DDR2MEMCON);
> +
> +/* SCL Start */
> +writel(SCL_START | SCL_EN, DDR2SCLSTART);
> +
> +/* Wait for SCL byte 

[U-Boot] [PATCH v1 14/18] board: Add gpio and ethernet support to pic32mzdask board.

[Purna Chandra Mandal]

Add GPIO and network (DHCP. BOOTP, TFTP protocol) support.

Signed-off-by: Purna Chandra Mandal 
---

 arch/mips/dts/pic32mzda.dtsi   | 92 ++
 arch/mips/dts/pic32mzda_sk.dts |  5 +++
 configs/pic32mzdask_defconfig  |  9 +
 include/configs/pic32mzdask.h  | 22 ++
 4 files changed, 128 insertions(+)

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 1333573..cf76825 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -5,12 +5,26 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#include 
 #include 
 #include "skeleton.dtsi"
 
 / {
 compatible = "microchip,pic32mzda", "microchip,pic32mz";
 
+aliases {
+gpio0 = 
+gpio1 = 
+gpio2 = 
+gpio3 = 
+gpio4 = 
+gpio5 = 
+gpio6 = 
+gpio7 = 
+gpio8 = 
+gpio9 = 
+};
+
 cpus {
 cpu@0 {
 compatible = "mips,mips14kc";
@@ -56,4 +70,82 @@
   <0xbf801500 0x200>; /* out */
 status = "disabled";
 };
+
+gpioA: gpio0@1f86 {
+compatible = "microchip,gpio-bank";
+reg = <0xbf86 0x24>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+
+gpioB: gpio1@1f860100 {
+compatible = "microchip,gpio-bank";
+reg = <0xbf860100 0x24>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+
+gpioC: gpio2@1f860200 {
+compatible = "microchip,gpio-bank";
+reg = <0xbf860200 0x24>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+
+gpioD: gpio3@1f860300 {
+compatible = "microchip,gpio-bank";
+reg = <0xbf860300 0x24>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+
+gpioE: gpio4@1f860400 {
+compatible = "microchip,gpio-bank";
+reg = <0xbf860400 0x24>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+
+gpioF: gpio5@1f860500 {
+compatible = "microchip,gpio-bank";
+reg = <0xbf860500 0x24>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+
+gpioG: gpio6@1f860600 {
+compatible = "microchip,gpio-bank";
+reg = <0xbf860600 0x24>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+
+gpioH: gpio7@1f860700 {
+compatible = "microchip,gpio-bank";
+reg = <0xbf860700 0x24>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+
+gpioJ: gpio8@1f860800 {
+compatible = "microchip,gpio-bank";
+reg = <0xbf860800 0x24>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+
+gpioK: gpio9@1f860900 {
+compatible = "microchip,gpio-bank";
+reg = <0xbf860900 0x24>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+
+ethernet: ethernet@1f882000 {
+compatible = "microchip,pic32mzda-eth";
+reg = <0xbf882000 0x1000>;
+interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
+phy-mode = "rmii";
+status = "disabled";
+};
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index 99e7f64..38ef9c0 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -36,3 +36,8 @@
 status = "okay";
 u-boot,dm-pre-reloc;
 };
+
+ {
+reset-gpios = < 15 0>;
+status = "okay";
+};
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index df06f8b..d74d169 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="dask # "
+CONFIG_CMD_NET=y
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_SUPPORT_OF_CONTROL=y
@@ -20,3 +21,11 @@ CONFIG_CLK=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_PIC32_PINCTRL=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_PIC32_GPIO=y
+CONFIG_NET=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_PIC32_ETH=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 89925f6..8e5c31b 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -100,6 +100,28 @@
 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_CMDLINE_EDITING1
 
+/*---
+ * Networking Configuration
+ */
+#define CONFIG_MII
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_PHY_ADDR0 /* LAN87XX */
+#define CONFIG_ARP_TIMEOUT500 /* millisec */
+#define CONFIG_NET_RETRY_COUNT20
+#define CONFIG_SYS_RX_ETH_BUFFER8
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
 /*
  * Handover flattened device tree (dtb file) to Linux kernel
  */
-- 
1.8.3.1

[U-Boot] [PATCH v1 13/18] drivers: net: add Microchip PIC32 ethernet controller driver

[Purna Chandra Mandal]

This driver implements MAC and MII layer of PIC32 ethernet controller.
This controller is capable of handling 100/10mbps full/half duplex
ethernet communication. Network data transfer is handled by internal DMA engine.

Signed-off-by: Purna Chandra Mandal 
---

 drivers/net/Kconfig  |   7 +
 drivers/net/Makefile |   1 +
 drivers/net/pic32_eth.c  | 648 +++
 drivers/net/pic32_eth.h  | 184 ++
 drivers/net/pic32_mdio.c | 143 +++
 5 files changed, 983 insertions(+)
 create mode 100644 drivers/net/pic32_eth.c
 create mode 100644 drivers/net/pic32_eth.h
 create mode 100644 drivers/net/pic32_mdio.c

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 6905cc0..2d7bf7c 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -107,4 +107,11 @@ config ZYNQ_GEM
 help
   This MAC is presetn in Xilinx Zynq and ZynqMP SoCs.
 
+config PIC32_ETH
+bool "Microchip PIC32 Ethernet Support"
+depends on MACH_PIC32
+help
+  This driver implements 10/100 Mbps Ethernet and MAC layer for
+  Microchip PIC32 microcontrollers.
+
 endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 150470c..33a81ee 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -72,3 +72,4 @@ obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
 obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
 obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
+obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c
new file mode 100644
index 000..ba499fb
--- /dev/null
+++ b/drivers/net/pic32_eth.c
@@ -0,0 +1,648 @@
+/*
+ * (c) 2015 Purna Chandra Mandal 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pic32_eth.h"
+
+/* local definitions */
+#define MAX_RX_BUF_SIZE1536
+#define MAX_RX_DESCRPKTBUFSRX
+#define MAX_TX_DESCR2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pic32eth_device {
+struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
+struct eth_dma_desc txd_ring[MAX_TX_DESCR];
+struct pic32_ectl_regs *ectl_regs;
+struct pic32_emac_regs *emac_regs;
+struct phy_device *phydev;
+phy_interface_t phyif;
+u32 phy_id; /* PHY addr */
+u32 rxd_idx; /* index of RX desc to read */
+struct gpio_desc rst_gpio;
+};
+
+__attribute__ ((weak)) void board_netphy_reset(void *dev)
+{
+struct pic32eth_device *pedev = (struct pic32eth_device *)dev;
+
+if (!dm_gpio_is_valid(>rst_gpio))
+return;
+
+/* phy reset */
+dm_gpio_set_value(>rst_gpio, 0);
+udelay(300);
+dm_gpio_set_value(>rst_gpio, 1);
+udelay(300);
+}
+
+/* Initialize mii(MDIO) interface, discover which PHY is
+ * attached to the device, and configure it properly.
+ */
+static int _mdio_init(struct pic32eth_device *pedev)
+{
+struct pic32_ectl_regs *ectl_p = pedev->ectl_regs;
+struct pic32_emac_regs *emac_p = pedev->emac_regs;
+
+board_netphy_reset(pedev);
+
+/* disable RX, TX & all transactions */
+writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, _p->con1.clr);
+
+/* wait until not BUSY */
+while (readl(_p->stat.raw) & ETHSTAT_BUSY)
+;
+
+/* turn controller ON to access PHY over MII */
+writel(ETHCON_ON, _p->con1.set);
+
+udelay(DELAY_10MSEC);
+
+/* reset MAC */
+writel(EMAC_SOFTRESET, _p->cfg1.set); /* reset assert */
+udelay(DELAY_10MSEC);
+writel(EMAC_SOFTRESET, _p->cfg1.clr); /* reset deassert */
+
+/* initialize MDIO/MII */
+if (pedev->phyif == PHY_INTERFACE_MODE_RMII) {
+writel(EMAC_RMII_RESET, _p->supp.set);
+udelay(DELAY_10MSEC);
+writel(EMAC_RMII_RESET, _p->supp.clr);
+}
+
+return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)_p->mii);
+}
+
+static int _phy_init(struct pic32eth_device *pedev, void *dev)
+{
+struct mii_dev *mii;
+
+mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
+
+/* find & connect PHY */
+pedev->phydev = phy_connect(mii, pedev->phy_id,
+dev, pedev->phyif);
+if (!pedev->phydev) {
+printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
+return 0;
+}
+
+/* Wait for phy to complete reset */
+udelay(DELAY_10MSEC);
+
+/* configure supported modes */
+pedev->phydev->supported = SUPPORTED_10baseT_Half |
+   SUPPORTED_10baseT_Full |
+   SUPPORTED_100baseT_Half |
+   SUPPORTED_100baseT_Full |
+   SUPPORTED_Autoneg;
+
+pedev->phydev->advertising = ADVERTISED_10baseT_Half |
+ ADVERTISED_10baseT_Full |
+ ADVERTISED_100baseT_Half |
+ ADVERTISED_100baseT_Full |
+ ADVERTISED_Autoneg;
+
+pedev->phydev->autoneg = AUTONEG_ENABLE;
+
+ 

Re: [U-Boot] u-boot 2016.01-rc2 detects BeagleBone Black incorrectly

[Robert Nelson]

On Thu, Dec 17, 2015 at 11:54 AM, Matwey V. Kornilov
 wrote:
> 2015-12-17 3:53 GMT+03:00 Robert Nelson :
>> Hi Matwey
>>
>> On Sat, Dec 12, 2015 at 3:14 AM, Matwey V. Kornilov
>>  wrote:
>>> Hello,
>>>
>>> I am running 2016.01-rc on BBB (Embest replica)
>>>
>>> printenv shows the following:
>>>
>>> findfdt=if test $board_name = A335BONE; then setenv fdtfile
>>> am335x-bone.dtb; fi; if test $board_name = A335BNLT; then if test
>>> $board_rev = BBG1; then setenv fdtfile am335x-bonegreen.dtb; else setenv
>>> fdtfile am335x-boneblack.dtb; fi; fi; if test $board_name = A33515BB;
>>> then setenv fdtfile am335x-evm.dtb; fi; if test $board_name = A335X_SK;
>>> then setenv fdtfile am335x-evmsk.dtb; fi; if test $fdtfile = undefined;
>>> then echo WARNING: Could not determine device tree to use; fi;
>>>
>>> after findfdt has been run,
>>>
>>> fdtfile=am335x-bonegreen.dtb
>>>
>>> But it is not correct. My $board_rev is the following, I have no idea
>>> why does it contain line break.
>>>
>>> board_name=A335BNLT
>>> board_rev=t\
>>
>> Yuck, another variation!  Can you do me a favor and dump the eeprom:
>>
>> https://github.com/beagleboard/image-builder/blob/master/readme.md
>>
>> Download and run:
>>
>> wget 
>> https://raw.githubusercontent.com/RobertCNelson/boot-scripts/master/device/bone/tester/show-eeprom.sh
>>
>> sudo /bin/bash show-eeprom.sh
>
> # sudo /bin/bash show-eeprom.sh
> eeprom: [�U3�A335BNLTt
> ue]
> eeprom raw: [  aa 55 33 ee 41 33 33 35  42 4e 4c 54 74 0a 75
> 65  |.U3.A335BNLTt.ue|]

ah, it's tripping on the "." = "0a" character..

Do you happen to remember where you purchased it and what it was
called.. (for git commit)

This patch should work:

https://gist.github.com/RobertCNelson/21f44591c78daed7c637

Please test,

and i've added it to our table:

https://github.com/RobertCNelson/omap-image-builder/commit/620ebf627d3df8c693845bef07af232aa289ff41

Regards,

-- 
Robert Nelson
https://rcn-ee.com/
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v1 06/18] MIPS: Add support for Microchip PIC32MZ[DA] SoC family.

[Purna Chandra Mandal]

Signed-off-by: Purna Chandra Mandal 
---

 arch/mips/dts/pic32mzda.dtsi |  59 +++
 arch/mips/include/asm/arch-pic32/pic32.h |   3 +
 arch/mips/mach-pic32/Kconfig |  16 +++-
 arch/mips/mach-pic32/Makefile|   2 +-
 arch/mips/mach-pic32/cpu.c   | 121 ++-
 arch/mips/mach-pic32/lowlevel_init.S |  41 +++
 arch/mips/mach-pic32/reset.c |  22 ++
 7 files changed, 261 insertions(+), 3 deletions(-)
 create mode 100644 arch/mips/dts/pic32mzda.dtsi
 create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
 create mode 100644 arch/mips/mach-pic32/reset.c

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
new file mode 100644
index 000..1333573
--- /dev/null
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2015 Microchip Technology, Inc.
+ * Purna Chandra Mandal, 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include "skeleton.dtsi"
+
+/ {
+compatible = "microchip,pic32mzda", "microchip,pic32mz";
+
+cpus {
+cpu@0 {
+compatible = "mips,mips14kc";
+};
+};
+
+clock: clk@1f801200 {
+compatible = "microchip,pic32mzda_clk";
+reg = <0xbf801200 0x1000>;
+};
+
+uart1: serial@1f822000 {
+compatible = "microchip,pic32mzda-uart";
+reg = <0xbf822000 0x50>;
+interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
+status = "disabled";
+};
+
+uart2: serial@1f822200 {
+compatible = "microchip,pic32mzda-uart";
+reg = <0xbf822200 0x50>;
+interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
+status = "disabled";
+};
+
+uart6: serial@1f822a00 {
+compatible = "microchip,pic32mzda-uart";
+reg = <0xbf822a00 0x50>;
+interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
+status = "disabled";
+};
+
+evic: interrupt-controller@1f81 {
+compatible = "microchip,pic32mzda-evic";
+interrupt-controller;
+#interrupt-cells = <2>;
+reg = <0xbf81 0x1000>;
+};
+
+pinctrl: pinctrl@1f801400 {
+compatible = "microchip,pic32mzda-pinctrl";
+reg = <0xbf801400 0x100>, /* in  */
+  <0xbf801500 0x200>; /* out */
+status = "disabled";
+};
+};
diff --git a/arch/mips/include/asm/arch-pic32/pic32.h 
b/arch/mips/include/asm/arch-pic32/pic32.h
index 4f2084f..d3f428f 100644
--- a/arch/mips/include/asm/arch-pic32/pic32.h
+++ b/arch/mips/include/asm/arch-pic32/pic32.h
@@ -142,4 +142,7 @@ struct pic32_reg_atomic {
 u32 inv;
 };
 
+/* Core */
+char *get_core_name(void);
+
 #endif/* __PIC32_REGS_H__ */
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
index e4eaf5c..9983131 100644
--- a/arch/mips/mach-pic32/Kconfig
+++ b/arch/mips/mach-pic32/Kconfig
@@ -2,11 +2,23 @@ menu "Microchip PIC32 platforms"
 depends on MACH_PIC32
 
 config SYS_SOC
-default "none"
+default "pic32mzda" if SOC_PIC32MZDA
 
 choice
 prompt "PIC32 SoC select"
 
+config SOC_PIC32MZDA
+bool "Microchip PIC32MZ[DA] family"
+select SUPPORTS_LITTLE_ENDIAN
+select SUPPORTS_CPU_MIPS32_R1
+select SUPPORTS_CPU_MIPS32_R2
+select SYS_MIPS_CACHE_INIT_RAM_LOAD
+select DM_SERIAL
+select PIC32_SERIAL
+select PIC32_PINCTRL
+help
+  This supports Microchip PIC32MZ[DA] family of microcontrollers.
+
 endchoice
 
 choice
@@ -16,5 +28,7 @@ endchoice
 
 config PIC32_SUPPORTS_FDT_BOOT
 bool "FDT Boot"
+select MIPS_BOOT_FDT
+select MIPS_BOOT_CMDLINE_LEGACY
 
 endmenu
diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
index cb42607..03d5f27 100644
--- a/arch/mips/mach-pic32/Makefile
+++ b/arch/mips/mach-pic32/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:  GPL-2.0+
 #
 
-obj-y = cpu.o
+obj-y = cpu.o reset.o lowlevel_init.o
\ No newline at end of file
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
index 58fd3ab..f95beae 100644
--- a/arch/mips/mach-pic32/cpu.c
+++ b/arch/mips/mach-pic32/cpu.c
@@ -6,8 +6,127 @@
  *
  */
 #include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
 
-phys_size_t initdram(int board_type)
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong clk_get_cpu_rate(void)
+{
+int ret;
+struct udevice *dev;
+
+ret = uclass_get_device(UCLASS_CLK, 0, );
+if (ret) {
+panic("uclass-clk: device not found\n");
+return 0;
+}
+
+return clk_get_rate(dev);
+}
+
+/* initialize prefetch module related to cpu_clk */
+static void init_prefetch(void)
+{
+int v, nr_waits;
+ulong rate;
+
+rate = clk_get_cpu_rate();
+
+/* calc and apply waits based on dynamic ECC */
+v = (readl(CFGCON) >> 4) & 0x03;
+if (v < 2) {
+if (rate < 6600)
+nr_waits = 0;
+else if (rate < 13300)
+nr_waits = 

Re: [U-Boot] [PATCH v1 01/18] MIPS: Prepare device-tree support.

[Marek Vasut]

On Thursday, December 17, 2015 at 06:28:08 PM, Purna Chandra Mandal wrote:
> Signed-off-by: Purna Chandra Mandal 
> ---
> 
>  arch/Kconfig  |  1 +
>  arch/mips/config.mk   |  3 +++
>  arch/mips/dts/.gitignore  |  1 +
>  arch/mips/dts/Makefile| 16 
>  arch/mips/dts/include/dt-bindings |  1 +
>  arch/mips/dts/skeleton.dtsi   | 21 +
>  dts/Makefile  |  2 +-
>  7 files changed, 44 insertions(+), 1 deletion(-)
>  create mode 100644 arch/mips/dts/.gitignore
>  create mode 100644 arch/mips/dts/Makefile
>  create mode 12 arch/mips/dts/include/dt-bindings
>  create mode 100644 arch/mips/dts/skeleton.dtsi
> 
> diff --git a/arch/Kconfig b/arch/Kconfig
> index 6489cc9..589fc47 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -54,6 +54,7 @@ config MIPS
>  select HAVE_PRIVATE_LIBGCC
>  select HAVE_GENERIC_BOARD
>  select SYS_GENERIC_BOARD
> +select SUPPORT_OF_CONTROL
> 
>  config NDS32
>  bool "NDS32 architecture"
> diff --git a/arch/mips/config.mk b/arch/mips/config.mk
> index 52e28f2..d4d688e 100644
> --- a/arch/mips/config.mk
> +++ b/arch/mips/config.mk
> @@ -70,3 +70,6 @@ PLATFORM_RELFLAGS+= -ffunction-sections
> -fdata-sections LDFLAGS_FINAL+= --gc-sections -pie
>  OBJCOPYFLAGS+= -j .text -j .rodata -j .data -j .got
>  OBJCOPYFLAGS+= -j .u_boot_list -j .rel.dyn -j .padding
> +ifdef CONFIG_OF_EMBED
> +OBJCOPYFLAGS+= -j .dtb.init.rodata
> +endif
> diff --git a/arch/mips/dts/.gitignore b/arch/mips/dts/.gitignore
> new file mode 100644
> index 000..b60ed20
> --- /dev/null
> +++ b/arch/mips/dts/.gitignore
> @@ -0,0 +1 @@
> +*.dtb
> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
> new file mode 100644
> index 000..724b5d2
> --- /dev/null
> +++ b/arch/mips/dts/Makefile
> @@ -0,0 +1,16 @@
> +#
> +# SPDX-License-Identifier:GPL-2.0+
> +#
> +
> +#dtb-$(CONFIG_XXX) += xxx.dtb

XXX ?

> +targets += $(dtb-y)
> +
> +# Add any required device tree compiler flags here
> +DTC_FLAGS +=
> +
> +PHONY += dtbs
> +dtbs: $(addprefix $(obj)/, $(dtb-y))
> +@:
> +
> +clean-files := *.dtb
> diff --git a/arch/mips/dts/include/dt-bindings
> b/arch/mips/dts/include/dt-bindings new file mode 12
> index 000..0cecb3d
> --- /dev/null
> +++ b/arch/mips/dts/include/dt-bindings
> @@ -0,0 +1 @@
> +../../../../include/dt-bindings
> \ No newline at end of file
> diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi
> new file mode 100644
> index 000..ad41546
> --- /dev/null
> +++ b/arch/mips/dts/skeleton.dtsi
> @@ -0,0 +1,21 @@
> +/*
> + * Skeleton device tree; the bare minimum needed to boot; just include and
> + * add a compatible value.  The bootloader will typically populate the
> memory + * node.
> + */
> +
> +/ {
> +#address-cells = <1>;
> +#size-cells = <1>;
> +
> +chosen {
> +};
> +
> +aliases {
> +};
> +
> +memory {
> +device_type = "memory";
> +reg = <0 0>;
> +};

You don't need any of these nodes, do you ?

> +};
> diff --git a/dts/Makefile b/dts/Makefile
> index d3122aa..5c3a01f 100644
> --- a/dts/Makefile
> +++ b/dts/Makefile
> @@ -45,4 +45,4 @@ dtbs: $(obj)/dt.dtb
>  clean-files := dt.dtb.S
> 
>  # Let clean descend into dts directories
> -subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts
> ../arch/x86/dts +subdir- += ../arch/arm/dts ../arch/microblaze/dts
> ../arch/sandbox/dts ../arch/x86/dts ../arch/mips/dts
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] who is official MAINTAINER for MPC83xx?

[Sinan Akman]

  Hi Robert

On 17/12/15 03:21 AM, Robert P. J. Day wrote:


   i CCed alleged MPC83xx maintainer kim.phill...@freescale.com
yesterday on my patch, but that CC bounced with "unknown user" error,
is there a newer maintainer for that platform?


  There is no maintainer for MPC83xx AFAIK at this time (Kim is no
longer with FSL). I have a set of mpc83xx boards that I could test
out new patches for. I am cc'ing to Stefan as we discussed something
similar briefly sometimes ago.

  Regards
  Sinan Akman
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v1 07/18] board: Add Microchip PIC32MZ[DA] Starter Kit board.

[Purna Chandra Mandal]

This adds support for Microchip PIC32MZ[DA] Starter Kit board
based on a PIC32MZ[DA] family of microcontrollers.

Signed-off-by: Purna Chandra Mandal 
---

 arch/mips/dts/Makefile|   2 +-
 arch/mips/dts/pic32mzda_sk.dts|  38 
 arch/mips/mach-pic32/Kconfig  |   7 +
 board/microchip/pic32mzda/Kconfig |  13 ++
 board/microchip/pic32mzda/MAINTAINERS |   6 +
 board/microchip/pic32mzda/Makefile|   7 +
 board/microchip/pic32mzda/README  |  22 ++
 board/microchip/pic32mzda/config.mk   |   4 +
 board/microchip/pic32mzda/ddr.c   | 389 ++
 board/microchip/pic32mzda/ddr.h   |  46 
 board/microchip/pic32mzda/pic32mzda.c |  41 
 configs/pic32mzdask_defconfig |  22 ++
 include/configs/pic32mzdask.h | 110 ++
 13 files changed, 706 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/pic32mzda_sk.dts
 create mode 100644 board/microchip/pic32mzda/Kconfig
 create mode 100644 board/microchip/pic32mzda/MAINTAINERS
 create mode 100644 board/microchip/pic32mzda/Makefile
 create mode 100644 board/microchip/pic32mzda/README
 create mode 100644 board/microchip/pic32mzda/config.mk
 create mode 100644 board/microchip/pic32mzda/ddr.c
 create mode 100644 board/microchip/pic32mzda/ddr.h
 create mode 100644 board/microchip/pic32mzda/pic32mzda.c
 create mode 100644 configs/pic32mzdask_defconfig
 create mode 100644 include/configs/pic32mzdask.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 724b5d2..b513918 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier:GPL-2.0+
 #
 
-#dtb-$(CONFIG_XXX) += xxx.dtb
+dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
new file mode 100644
index 000..99e7f64
--- /dev/null
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2015 Purna Chandra Mandal, purna.man...@microchip.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "pic32mzda.dtsi"
+
+/ {
+model = "Microchip PIC32MZDASK";
+compatible = "microchip,pic32mzdask", "microchip,pic32mzda";
+
+aliases {
+console = 
+serial0 = 
+};
+
+chosen {
+stdout-path = "serial0:115200n8";
+};
+};
+
+ {
+status = "okay";
+u-boot,dm-pre-reloc;
+};
+
+ {
+status = "okay";
+u-boot,dm-pre-reloc;
+};
+
+ {
+status = "okay";
+u-boot,dm-pre-reloc;
+};
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
index 9983131..f82df37 100644
--- a/arch/mips/mach-pic32/Kconfig
+++ b/arch/mips/mach-pic32/Kconfig
@@ -24,6 +24,12 @@ endchoice
 choice
 prompt "Board select"
 
+config TARGET_PIC32MZDASK
+bool "Microchip PIC32MZ[DA] Starter Kit"
+depends on SOC_PIC32MZDA
+help
+  This supports Microchip PIC32MZ[DA] Starter Kit.
+
 endchoice
 
 config PIC32_SUPPORTS_FDT_BOOT
@@ -31,4 +37,5 @@ config PIC32_SUPPORTS_FDT_BOOT
 select MIPS_BOOT_FDT
 select MIPS_BOOT_CMDLINE_LEGACY
 
+source "board/microchip/pic32mzda/Kconfig"
 endmenu
diff --git a/board/microchip/pic32mzda/Kconfig 
b/board/microchip/pic32mzda/Kconfig
new file mode 100644
index 000..8acb393
--- /dev/null
+++ b/board/microchip/pic32mzda/Kconfig
@@ -0,0 +1,13 @@
+
+if TARGET_PIC32MZDASK
+
+config SYS_BOARD
+default "pic32mzda"
+
+config SYS_VENDOR
+default "microchip"
+
+config SYS_CONFIG_NAME
+default "pic32mzdask"
+
+endif
diff --git a/board/microchip/pic32mzda/MAINTAINERS 
b/board/microchip/pic32mzda/MAINTAINERS
new file mode 100644
index 000..c934f1a
--- /dev/null
+++ b/board/microchip/pic32mzda/MAINTAINERS
@@ -0,0 +1,6 @@
+PIC32MZDASK BOARD
+M:Purna Chandra Mandal 
+S:Maintained
+F:board/microchip/pic32mzda/
+F:include/configs/pic32mzdask.h
+F:configs/pic32mzdask_defconfig
diff --git a/board/microchip/pic32mzda/Makefile 
b/board/microchip/pic32mzda/Makefile
new file mode 100644
index 000..93733b4
--- /dev/null
+++ b/board/microchip/pic32mzda/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.man...@microchip.com.
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+obj-y := pic32mzda.o ddr.o
diff --git a/board/microchip/pic32mzda/README b/board/microchip/pic32mzda/README
new file mode 100644
index 000..ccf6dcb
--- /dev/null
+++ b/board/microchip/pic32mzda/README
@@ -0,0 +1,22 @@
+/*
+ * (c) 2015 Purna Chandra Mandal 
+ */
+
+PIC32MZ[DA] Starter-Kit
+
+PIC32MZ[DA] Starter Kit is based on PIC32MZ[DA] family of micro-controller.
+This family is powered by MIPS M14KEC 32bit general purpose core with advanced
+microcontroller features and peripherals.
+
+This processor boots with proprietary stage1 bootloader running from on-chip
+boot-flash. Stage1 

[U-Boot] [PATCH v1 08/18] MIPS: pic32: Add driver for Microchip PIC32 flash controller.

[Purna Chandra Mandal]

From: Cristian Birsan 

Signed-off-by: Cristian Birsan 
Signed-off-by: Purna Chandra Mandal 
---

 arch/mips/mach-pic32/Makefile |   5 +-
 arch/mips/mach-pic32/flash.c  | 471 ++
 include/flash.h   |   5 +-
 3 files changed, 479 insertions(+), 2 deletions(-)
 create mode 100644 arch/mips/mach-pic32/flash.c

diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
index 03d5f27..3a621c3 100644
--- a/arch/mips/mach-pic32/Makefile
+++ b/arch/mips/mach-pic32/Makefile
@@ -4,4 +4,7 @@
 # SPDX-License-Identifier:  GPL-2.0+
 #
 
-obj-y = cpu.o reset.o lowlevel_init.o
\ No newline at end of file
+obj-y = cpu.o reset.o lowlevel_init.o
+ifndef CONFIG_SYS_NO_FLASH
+obj-y += flash.o
+endif
\ No newline at end of file
diff --git a/arch/mips/mach-pic32/flash.c b/arch/mips/mach-pic32/flash.c
new file mode 100644
index 000..b3c1e0a
--- /dev/null
+++ b/arch/mips/mach-pic32/flash.c
@@ -0,0 +1,471 @@
+/*
+ * Copyright (C) 2015
+ * Cristian Birsan 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+#ifndef CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#endif
+
+#ifndef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZECONFIG_ENV_SECT_SIZE
+#endif
+
+#ifndef CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+#endif
+#endif
+
+/* NVM Controller registers */
+#define NVMCON(PIC32_NVM_BASE + 0x00)
+#define NVMCONCLR(NVMCON + _CLR_OFFSET)
+#define NVMCONSET(NVMCON + _SET_OFFSET)
+#define NVMKEY(PIC32_NVM_BASE + 0x10)
+#define NVMADDR(PIC32_NVM_BASE + 0x20)
+#define NVMDATA0(PIC32_NVM_BASE + 0x30)
+
+/* NVM Operations */
+#define NVMOP_NOP0x
+#define NVMOP_WORD_WRITE0x0001
+#define NVMOP_PAGE_ERASE0x0004
+
+/* NVM Programming Control Register*/
+#define NVMCON_WREN0x4000
+#define NVMCON_WR0x8000
+#define NVMCON_WRERR0x2000
+#define NVMCON_LVDERR0x1000
+
+/*---
+ */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size(vu_long *addr, flash_info_t *info)
+{
+short i;
+ulong base = (ulong)addr;
+ulong sector_offset;
+
+/* On chip flash ID */
+switch (info->flash_id & FLASH_VENDMASK) {
+case FLASH_MAN_MCHP:
+break;
+default:
+/* no or unknown flash*/
+printf("unknown manufacturer: 0x%lx\n",
+   info->flash_id & FLASH_VENDMASK);
+info->flash_id = FLASH_UNKNOWN;
+info->sector_count = 0;
+info->size = 0;
+return 0;
+}
+
+switch (info->flash_id & FLASH_TYPEMASK) {
+case FLASH_MCHP100T:
+info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+info->size = CONFIG_SYS_FLASH_SIZE;
+sector_offset = info->size / info->sector_count;
+break;
+default:
+info->flash_id = FLASH_UNKNOWN;
+return 0;/* => no or unknown flash */
+}
+
+/* set up sector start address table */
+for (i = 0; i < info->sector_count; i++) {
+info->start[i] = base;
+base += sector_offset;
+/* protect each sector by default */
+info->protect[i] = 1;
+}
+
+/* Disable Flash Write/Erase operations */
+writel(NVMCON_WREN, NVMCONCLR);
+
+if (info->flash_id != FLASH_UNKNOWN)
+addr = (vu_long *)info->start[0];
+
+return info->size;
+}
+
+/*---
+ */
+void flash_print_info(flash_info_t *info)
+{
+int i;
+
+if (info->flash_id == FLASH_UNKNOWN) {
+printf("missing or unknown FLASH type\n");
+return;
+}
+
+switch (info->flash_id & FLASH_VENDMASK) {
+case FLASH_MAN_MCHP:
+printf("Microchip ");
+break;
+default:
+printf("Unknown Vendor ");
+break;
+}
+
+switch (info->flash_id & FLASH_TYPEMASK) {
+case FLASH_MCHP100T:
+printf("Internal (8 Mbit, 64 x 16k)\n");
+break;
+default:
+printf("Unknown Chip Type\n");
+break;
+}
+
+printf("  Size: %ld MB in %d Sectors\n",
+   info->size >> 20, info->sector_count);
+
+printf("  Sector Start Addresses:");
+for (i = 0; i < info->sector_count; ++i) {
+if ((i % 5) == 0)
+printf("\n   ");
+
+printf(" %08lX%s", info->start[i],
+   info->protect[i] ? " (RO)" : " ");
+}
+printf("\n");
+}
+
+static inline void flash_initiate_operation(void)
+{
+/* Unlock sequence */
+writel(0x, NVMKEY);
+writel(0xAA996655, NVMKEY);
+writel(0x556699AA, 

[U-Boot] [PATCH v1 09/18] board: pic32mzdask: add flash support for environments.

[Purna Chandra Mandal]

Add flash chip information and environment location (for environment in flash).

Signed-off-by: Purna Chandra Mandal 
---

 include/configs/pic32mzdask.h | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 9f867ed..89925f6 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -75,7 +75,19 @@
 /*-
  * FLASH configuration
  */
-#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS2  /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT64 /* max number of sectors */
+#define CONFIG_SYS_FLASH_SIZE(1 << 20) /* 1M, size of one bank */
+#define PHYS_FLASH_10x1D00 /* Flash Bank #1 */
+#define PHYS_FLASH_20x1D10 /* Flash Bank #2 */
+#define CONFIG_SYS_FLASH_BANKS_LIST{PHYS_FLASH_1, PHYS_FLASH_2}
+#define CONFIG_SYS_FLASH_BASEPHYS_FLASH_1
+#define PHYS_FLASH_SECT_SIZE\
+(CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_SECT)
+
+/* FLASH erase/programming timeout (in ticks) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT(2 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT(25 * CONFIG_SYS_HZ)
 
 /*
  * Console Configuration
@@ -96,8 +108,10 @@
 /* -
  * Environment
  */
-#define CONFIG_ENV_IS_NOWHERE1
+#define CONFIG_ENV_IS_IN_FLASH1
+#define CONFIG_ENV_SECT_SIZE0x4000 /* 16K(one sector) for env */
 #define CONFIG_ENV_SIZE0x4000
+#define CONFIG_ENV_ADDR0x9d0fc000 /* Last sector from Bank 0 */
 
 /* -
  * Board boot configuration
-- 
1.8.3.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v1 10/18] MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO.

[Purna Chandra Mandal]

With CONFIG_CMD_GPIO compilation reports error.
common/cmd_gpio.c:13:22: fatal error: asm/gpio.h: No such file or directory
 #include 
  ^
Signed-off-by: Purna Chandra Mandal 

---

 arch/mips/include/asm/gpio.h | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 arch/mips/include/asm/gpio.h

diff --git a/arch/mips/include/asm/gpio.h b/arch/mips/include/asm/gpio.h
new file mode 100644
index 000..306ab4c
--- /dev/null
+++ b/arch/mips/include/asm/gpio.h
@@ -0,0 +1 @@
+#include 
-- 
1.8.3.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL

[Nikolay Dimitrov]

Hi Marek,

On 12/16/2015 04:40 PM, Marek Vasut wrote:

Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
fine-tunes the behavior of the MMDC controller in order to improve
the signal integrity and memory stability.


Great work!

Regards,
Nikolay
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL

[Marek Vasut]

On Thursday, December 17, 2015 at 10:32:03 PM, Nikolay Dimitrov wrote:
> Hi Marek,
> 
> On 12/16/2015 04:40 PM, Marek Vasut wrote:
> > Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
> > fine-tunes the behavior of the MMDC controller in order to improve
> > the signal integrity and memory stability.
> 
> Great work!

Thanks, I am flattered :)

Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] spi: sf: add support for throughput mesurement of sf read/write

[Stefan Roese]

On 17.12.2015 17:44, Jagan Teki wrote:

On 17 December 2015 at 13:26, Mugunthan V N  wrote:

On Thursday 17 December 2015 12:43 PM, Jagan Teki wrote:

On 17 December 2015 at 12:33, Mugunthan V N  wrote:

Jagan

On Tuesday 27 October 2015 07:24 PM, Mugunthan V N wrote:

This patch adds time measurement and throughput calculation for
sf read/write commands.

The output of sf read changes from

---8<---
SF: 4096 bytes @ 0x0 Read: OK
--->8---

to

---8<---
SF: 4096 bytes @ 0x0 Read: OK in 6 ms (666 KiB/s)
--->8---

Signed-off-by: Mugunthan V N 


Was it similar to 'sf update' ? please check it once.



sf update out similar but also uses progressive output, in read/write
case it can't be done. The final throughput measurement is similar on
both update and read/write.


True, that's what if we need a progressed throughput just use 'sf
update' else normal 'sf read/write' It's look not good to me to add
extra code on top of generic commands. What ever we wanted to extend
features let's added it on 'sf update' than sf read/write, Sorry.


If I need to measure the time of commands, I use the "time"
command ("time sf write ...") by enabling it via CONFIG_CMD_TIME.
This provides all the needed information to detect performance
changes.

Thanks,
Stefan
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] who is official MAINTAINER for MPC83xx?

[Stefan Roese]

On 17.12.2015 19:07, Sinan Akman wrote:


   Hi Robert

On 17/12/15 03:21 AM, Robert P. J. Day wrote:


   i CCed alleged MPC83xx maintainer kim.phill...@freescale.com
yesterday on my patch, but that CC bounced with "unknown user" error,
is there a newer maintainer for that platform?


   There is no maintainer for MPC83xx AFAIK at this time (Kim is no
longer with FSL). I have a set of mpc83xx boards that I could test
out new patches for. I am cc'ing to Stefan as we discussed something
similar briefly sometimes ago.


Yes. And I think we can now safely assume, that Kim will not
continue to maintain the MPC83xx boards. As we've not heard
from him for quite a while and he's not working for FSL
any more.

IIRC, then you Sinan volunteered to take over this custodianship?
Is this still the case? I'm adding Tom to Cc, so that we can
discuss and perhaps decide this custodianship takeover on the
list.

Thanks,
Stefan

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board

[Chin Liang See]

Hi Shengjiang,

On Fri, 2015-12-18 at 15:13 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[0-13] for RGMII1.
> Updated EMAC1 clock.
> 
> Signed-off-by: shengjiangwu 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Marek Vasut 
> Cc: Stefan Roese 

Thanks for the patch.

> ---
>  board/altera/cyclone5-socdk/qts/pinmux_config.h |   28 +++--
> --
>  board/altera/cyclone5-socdk/qts/pll_config.h|4 ++--
>  2 files changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> index 33cf1fd..442b1e0 100644
> --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
>   0, /* GENERALIO29 */
>   0, /* GENERALIO30 */
>   0, /* GENERALIO31 */
> - 0, /* MIXED1IO0 */
> - 1, /* MIXED1IO1 */
> - 1, /* MIXED1IO2 */
> - 1, /* MIXED1IO3 */
> - 1, /* MIXED1IO4 */
> - 0, /* MIXED1IO5 */
> - 0, /* MIXED1IO6 */
> - 0, /* MIXED1IO7 */
> - 1, /* MIXED1IO8 */
> - 1, /* MIXED1IO9 */
> - 1, /* MIXED1IO10 */
> - 1, /* MIXED1IO11 */
> - 0, /* MIXED1IO12 */
> - 0, /* MIXED1IO13 */
> + 2, /* MIXED1IO0 */
> + 2, /* MIXED1IO1 */
> + 2, /* MIXED1IO2 */
> + 2, /* MIXED1IO3 */
> + 2, /* MIXED1IO4 */
> + 2, /* MIXED1IO5 */
> + 2, /* MIXED1IO6 */
> + 2, /* MIXED1IO7 */
> + 2, /* MIXED1IO8 */
> + 2, /* MIXED1IO9 */
> + 2, /* MIXED1IO10 */
> + 2, /* MIXED1IO11 */
> + 2, /* MIXED1IO12 */
> + 2, /* MIXED1IO13 */
>   0, /* MIXED1IO14 */
>   1, /* MIXED1IO15 */
>   1, /* MIXED1IO16 */
> diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
> b/board/altera/cyclone5-socdk/qts/pll_config.h
> index 3d621ed..42905f4 100644
> --- a/board/altera/cyclone5-socdk/qts/pll_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pll_config.h
> @@ -31,7 +31,7 @@
>  #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
>  #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
>  #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
> -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
> +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
>  #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
>  #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
>  #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
> @@ -65,7 +65,7 @@
>  #define CONFIG_HPS_CLK_PERVCO_HZ 10
>  #define CONFIG_HPS_CLK_SDRVCO_HZ 6
>  #define CONFIG_HPS_CLK_EMAC0_HZ 25000
> -#define CONFIG_HPS_CLK_EMAC1_HZ 25000
> +#define CONFIG_HPS_CLK_EMAC1_HZ 5000

I believe the EMAC1 clock is still 250MHz which result of 25MHz *
(79+1) / (1+1) / (3+1).

Thanks
Chin Liang

>  #define CONFIG_HPS_CLK_USBCLK_HZ 2
>  #define CONFIG_HPS_CLK_NAND_HZ 5000
>  #define CONFIG_HPS_CLK_SDMMC_HZ 2
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board

[Chin Liang See]

Hi Shengjiangm

On Fri, 2015-12-18 at 07:39 +, 圣江 吴 wrote:
> Hi Chin,
> 
> I will check it.
> 
> Best Regards
> ShengjiangWu
> 

To ease reading, we will put comment below previous comments. 

In the mean time, opensource will always use plaintext email. FYI, I
use evoluation to handle email communication instead of company default
outlook. Or you can use gmail if you email software don't support
plaintext.

Thanks
Chin Liang


> On Dec 17, 2015, at 11:28 PM, Chin Liang See 
> wrote:
> 
> > Hi Shengjiang,
> > 
> > On Fri, 2015-12-18 at 15:13 +0800, shengjiangwu wrote:
> > > Updated pinmux group MIXED1IO[0-13] for RGMII1.
> > > Updated EMAC1 clock.
> > > Signed-off-by: shengjiangwu 
> > > Cc: Chin Liang See 
> > > Cc: Dinh Nguyen 
> > > Cc: Dinh Nguyen 
> > > Cc: Pavel Machek 
> > > Cc: Marek Vasut 
> > > Cc: Stefan Roese 
> > Thanks for the patch.
> > 
> > > ---
> > > board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++-
> > > -
> > > --
> > > board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
> > > 2 files changed, 16 insertions(+), 16 deletions(-)
> > > diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > index 33cf1fd..442b1e0 100644
> > > --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> > > @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
> > >0, /* GENERALIO29 */
> > >  0, /* GENERALIO30 */
> > >  0, /* GENERALIO31 */
> > > -  0, /* MIXED1IO0 */
> > > -  1, /* MIXED1IO1 */
> > > -  1, /* MIXED1IO2 */
> > > -  1, /* MIXED1IO3 */
> > > -  1, /* MIXED1IO4 */
> > > -  0, /* MIXED1IO5 */
> > > -  0, /* MIXED1IO6 */
> > > -  0, /* MIXED1IO7 */
> > > -  1, /* MIXED1IO8 */
> > > -  1, /* MIXED1IO9 */
> > > -  1, /* MIXED1IO10 */
> > > -1, /* MIXED1IO11 */
> > > -0, /* MIXED1IO12 */
> > > -0, /* MIXED1IO13 */
> > > +2, /* MIXED1IO0 */
> > > +  2, /* MIXED1IO1 */
> > > +  2, /* MIXED1IO2 */
> > > +  2, /* MIXED1IO3 */
> > > +  2, /* MIXED1IO4 */
> > > +  2, /* MIXED1IO5 */
> > > +  2, /* MIXED1IO6 */
> > > +  2, /* MIXED1IO7 */
> > > +  2, /* MIXED1IO8 */
> > > +  2, /* MIXED1IO9 */
> > > +  2, /* MIXED1IO10 */
> > > +2, /* MIXED1IO11 */
> > > +2, /* MIXED1IO12 */
> > > +2, /* MIXED1IO13 */
> > >0, /* MIXED1IO14 */
> > >1, /* MIXED1IO15 */
> > >1, /* MIXED1IO16 */
> > > diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
> > > b/board/altera/cyclone5-socdk/qts/pll_config.h
> > > index 3d621ed..42905f4 100644
> > > --- a/board/altera/cyclone5-socdk/qts/pll_config.h
> > > +++ b/board/altera/cyclone5-socdk/qts/pll_config.h
> > > @@ -31,7 +31,7 @@
> > > #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
> > > #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
> > > #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
> > > -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
> > > +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
> > > #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
> > > #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
> > > #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
> > > @@ -65,7 +65,7 @@
> > > #define CONFIG_HPS_CLK_PERVCO_HZ 10
> > > #define CONFIG_HPS_CLK_SDRVCO_HZ 6
> > > #define CONFIG_HPS_CLK_EMAC0_HZ 25000
> > > -#define CONFIG_HPS_CLK_EMAC1_HZ 25000
> > > +#define CONFIG_HPS_CLK_EMAC1_HZ 5000
> > I believe the EMAC1 clock is still 250MHz which result of 25MHz *
> > (79+1) / (1+1) / (3+1).
> > 
> > Thanks
> > Chin Liang
> > 
> > > #define CONFIG_HPS_CLK_USBCLK_HZ 2
> > > #define CONFIG_HPS_CLK_NAND_HZ 5000
> > > #define CONFIG_HPS_CLK_SDMMC_HZ 2
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 00/11] zap: Do not use macros that are equivalent to IS_ENABLED(CONFIG_...)

[Marek Vasut]

On Friday, December 18, 2015 at 03:04:59 AM, Masahiro Yamada wrote:
> Please stop such coding habit as follows:
> 
>   #ifdef CONFIG_FOO
>   #  define ENABLE_FOO   1
>   #else
>   #  define ENABLE_FOO   0
>   #endif

Oh yes, this is horrible, kill this with fire :)

> Use IS_ENABLED(CONFIG_FOO), instead.
> 
> 
> 
> Masahiro Yamada (11):
>   image: zap IMAGE_ENABLE_RAMDISK_HIGH
>   image: zap IMAGE_ENABLE_OF_LIBFDT
>   image: zap IMAGE_BOOT_GET_CMDLINE
>   image: zap IMAGE_OF_BOARD_SETUP
>   image: zap IMAGE_OF_SYSTEM_SETUP
>   ARM: bootm: BOOTM_ENABLE_SERIAL_TAG
>   ARM: bootm: BOOTM_ENABLE_CMDLINE_TAG
>   ARM: bootm: BOOTM_ENABLE_REVISION_TAG
>   ARM: bootm: BOOTM_ENABLE_MEMORY_TAG
>   ARM: bootm: BOOTM_ENABLE_INITRD_TAG
>   ARM: bootm: drop redundant #ifdef conditional
> 
>  arch/arc/lib/bootm.c |  2 +-
>  arch/arm/include/asm/bootm.h | 22 --
>  arch/arm/lib/bootm.c | 16 +++-
>  common/image-fdt.c   |  6 +++---
>  common/image.c   | 10 +-
>  include/image.h  | 30 --
>  6 files changed, 16 insertions(+), 70 deletions(-)

Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] ARM: uniphier: allow to run zImage rather than uImage

[Masahiro Yamada]

UniPhier SoC family adopt ARM Multi-platform in Linux since the first
upstreaming.  Because CONFIG_ARM_PATCH_PHYS_VIRT is defined, the
kernel image is completely position-independent.  There is no reason
to decide the load address on compile time, but it is up to the boot
loader.  Now, zImage is handier than uImage, also it allows to skip
the relocation of the kernel image.

Signed-off-by: Masahiro Yamada 
---

 include/configs/uniphier.h | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index b1106de..463c687 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -188,13 +188,14 @@
"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
"bootm $fit_addr_r\0"
 #else
-#define CONFIG_BOOTFILE"uImage"
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_BOOTFILE"zImage"
 #define LINUXBOOT_ENV_SETTINGS \
"fdt_addr=0x0010\0" \
"fdt_addr_r=0x8410\0" \
"fdt_size=0x8000\0" \
"kernel_addr=0x0020\0" \
-   "kernel_addr_r=0x8420\0" \
+   "kernel_addr_r=0x80208000\0" \
"kernel_size=0x0080\0" \
"ramdisk_addr=0x00a0\0" \
"ramdisk_addr_r=0x84a0\0" \
@@ -203,15 +204,15 @@
"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
"setexpr fdt_addr $nor_base + $fdt_addr &&" \
-   "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
+   "bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \
"nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
-   "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
+   "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
"tftpboot $fdt_addr_r $fdt_file &&" \
-   "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
+   "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
 #endif
 
 #defineCONFIG_EXTRA_ENV_SETTINGS   \
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] who is official MAINTAINER for MPC83xx?

[Sinan Akman]

  Hi Stefan

Stefan Roese wrote:

On 17.12.2015 19:07, Sinan Akman wrote:


   Hi Robert

On 17/12/15 03:21 AM, Robert P. J. Day wrote:


   i CCed alleged MPC83xx maintainer kim.phill...@freescale.com
yesterday on my patch, but that CC bounced with "unknown user" error,
is there a newer maintainer for that platform?


   There is no maintainer for MPC83xx AFAIK at this time (Kim is no
longer with FSL). I have a set of mpc83xx boards that I could test
out new patches for. I am cc'ing to Stefan as we discussed something
similar briefly sometimes ago.


Yes. And I think we can now safely assume, that Kim will not
continue to maintain the MPC83xx boards. As we've not heard
from him for quite a while and he's not working for FSL
any more.

IIRC, then you Sinan volunteered to take over this custodianship?
Is this still the case? I'm adding Tom to Cc, so that we can
discuss and perhaps decide this custodianship takeover on the
list.


  I actually rather volunteered to help out with testing as I seemed
to have access to a good collection of mpx83xxx based reference boards.
I only took maintainership of mpc837xerdb recently after we moved with
generic board support.

  I feel there might be some others with higher level of contributions
and related experience and might be interested in the custodianship.
I am cc'ing to Dirk as well as I know he had worked on mpc83xx code
quite a bit. Let's see if there is any other volunteers first.

  Regards
  Sinan Akman


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Chin Liang See]

Hi Shengjiang,

On Fri, 2015-12-18 at 15:21 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
> 
> Signed-off-by: shengjiangwu 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Marek Vasut 
> Cc: Stefan Roese 
> ---
>  board/altera/cyclone5-socdk/qts/pinmux_config.h |   12 ++--
>  board/altera/cyclone5-socdk/qts/pll_config.h|4 ++--
>  2 files changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> index 442b1e0..06783dc 100644
> --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> @@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
>   2, /* MIXED1IO12 */
>   2, /* MIXED1IO13 */
>   0, /* MIXED1IO14 */
> - 1, /* MIXED1IO15 */
> - 1, /* MIXED1IO16 */
> - 1, /* MIXED1IO17 */
> - 1, /* MIXED1IO18 */
> - 0, /* MIXED1IO19 */
> - 0, /* MIXED1IO20 */
> + 3, /* MIXED1IO15 */
> + 3, /* MIXED1IO16 */
> + 3, /* MIXED1IO17 */
> + 3, /* MIXED1IO18 */
> + 3, /* MIXED1IO19 */
> + 3, /* MIXED1IO20 */
>   0, /* MIXED1IO21 */
>   0, /* MIXED2IO0 */
>   0, /* MIXED2IO1 */
> diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
> b/board/altera/cyclone5-socdk/qts/pll_config.h
> index 42905f4..eccc705 100644
> --- a/board/altera/cyclone5-socdk/qts/pll_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pll_config.h
> @@ -14,7 +14,7 @@
>  #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
>  #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
>  #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
> -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
> +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
>  #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
>  #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
>  #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
> @@ -32,7 +32,7 @@
>  #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
>  #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
>  #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
> -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
> +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1

Let's not change this as we are using mainpll for QSPI clock. Besides
that, the QSPI perpll will yield 500MHz which exceed the 400MHz max
clock.

Thanks
Chin Liang


>  #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
>  #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
>  #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/3] serial: uartlite: Move driver to DM

[Michal Simek]

On 18.12.2015 00:35, Thomas Chou wrote:
> Hi Michal,
> 
> On 2015年12月17日 21:58, Michal Simek wrote:
>> On 17.12.2015 14:37, Thomas Chou wrote:
>>> Hi Michal,
>>>
>>> On 2015年12月17日 20:00, Michal Simek wrote:
 Enable SPL DM too.

 Signed-off-by: Michal Simek 
 ---

 Changes in v2:
 - Remove unneeded headers
 - Use get_dev_addr instead of fdtdec_get_addr
 - Use platdata instead of private data
 - Add opb compatible string to be in sync with Linux
 - Add binding documentation

arch/microblaze/Kconfig|   1 +
configs/microblaze-generic_defconfig   |   2 +
.../serial/xilinx_uartlite.txt |  13 ++
doc/driver-model/serial-howto.txt  |   1 -
drivers/serial/serial_xuartlite.c  | 170
 -
5 files changed, 78 insertions(+), 109 deletions(-)
create mode 100644
 doc/device-tree-bindings/serial/xilinx_uartlite.txt

 diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
 index 604f6815af5b..30ea484f48aa 100644
 --- a/arch/microblaze/Kconfig
 +++ b/arch/microblaze/Kconfig
 @@ -13,6 +13,7 @@ config TARGET_MICROBLAZE_GENERIC
select SUPPORT_SPL
select OF_CONTROL
select DM
 +select DM_SERIAL

endchoice

 diff --git a/configs/microblaze-generic_defconfig
 b/configs/microblaze-generic_defconfig
 index 54aa3ef3d26f..5df080b6a87c 100644
 --- a/configs/microblaze-generic_defconfig
 +++ b/configs/microblaze-generic_defconfig
 @@ -1,9 +1,11 @@
CONFIG_MICROBLAZE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 +CONFIG_SPL_DM=y
CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SPL=y
CONFIG_SYS_PROMPT="U-Boot-mONStR> "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
 +CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
 diff --git a/doc/device-tree-bindings/serial/xilinx_uartlite.txt
 b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
 new file mode 100644
 index ..d15753c8c380
 --- /dev/null
 +++ b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
 @@ -0,0 +1,13 @@
 +Binding for Xilinx Uartlite Controller
 +
 +Required properties:
 +- compatible : should be "xlnx,xps-uartlite-1.00.a", or
 "xlnx,opb-uartlite-1.00.b"
 +- reg: Should contain UART controller registers location and length.
 +- interrupts: Should contain UART controller interrupts.
 +
 +Example:
 +serial@4060 {
 +compatible = "xlnx,xps-uartlite-1.00.a";
 +interrupts = <1 0>;
 +reg = <0x4060 0x1>;
 +};
 diff --git a/doc/driver-model/serial-howto.txt
 b/doc/driver-model/serial-howto.txt
 index 76ad629ef9cb..381a2a084562 100644
 --- a/doc/driver-model/serial-howto.txt
 +++ b/doc/driver-model/serial-howto.txt
 @@ -18,7 +18,6 @@ is time for maintainers to start converting over the
 remaining serial drivers:
   serial_pxa.c
   serial_s3c24x0.c
   serial_sa1100.c
 -   serial_xuartlite.c
   usbtty.c

You should complete this by the end of January 2016.
 diff --git a/drivers/serial/serial_xuartlite.c
 b/drivers/serial/serial_xuartlite.c
 index 988438e75471..8225d9a320a5 100644
 --- a/drivers/serial/serial_xuartlite.c
 +++ b/drivers/serial/serial_xuartlite.c
 @@ -1,5 +1,5 @@
/*
 - * (C) Copyright 2008-2011 Michal Simek 
 + * (C) Copyright 2008 - 2015 Michal Simek 
 * Clean driver and add xilinx constant from header file
 *
 * (C) Copyright 2004 Atmark Techno, Inc.
 @@ -10,11 +10,15 @@

#include 
#include 
 +#include 
#include 
#include 
#include 

 +DECLARE_GLOBAL_DATA_PTR;
 +
#define SR_TX_FIFO_FULL0x08 /* transmit FIFO full */
 +#define SR_TX_FIFO_EMPTY0x04 /* transmit FIFO empty */
#define SR_RX_FIFO_VALID_DATA0x01 /* data in receive FIFO */
#define SR_RX_FIFO_FULL0x02 /* receive FIFO full */

 @@ -28,135 +32,85 @@ struct uartlite {
unsigned int control;
};

 -static struct uartlite *userial_ports[4] = {
 -#ifdef XILINX_UARTLITE_BASEADDR
 -[0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
 -#endif
 -#ifdef XILINX_UARTLITE_BASEADDR1
 -[1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
 -#endif
 -#ifdef XILINX_UARTLITE_BASEADDR2
 -[2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
 -#endif
 -#ifdef XILINX_UARTLITE_BASEADDR3
 -[3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
 -#endif
 +struct 

Re: [U-Boot] [PATCH v2 1/3] serial: uartlite: Move driver to DM

[Thomas Chou]

Hi Michal,

On 2015年12月17日 21:58, Michal Simek wrote:

On 17.12.2015 14:37, Thomas Chou wrote:

Hi Michal,

On 2015年12月17日 20:00, Michal Simek wrote:

Enable SPL DM too.

Signed-off-by: Michal Simek 
---

Changes in v2:
- Remove unneeded headers
- Use get_dev_addr instead of fdtdec_get_addr
- Use platdata instead of private data
- Add opb compatible string to be in sync with Linux
- Add binding documentation

   arch/microblaze/Kconfig|   1 +
   configs/microblaze-generic_defconfig   |   2 +
   .../serial/xilinx_uartlite.txt |  13 ++
   doc/driver-model/serial-howto.txt  |   1 -
   drivers/serial/serial_xuartlite.c  | 170
-
   5 files changed, 78 insertions(+), 109 deletions(-)
   create mode 100644 doc/device-tree-bindings/serial/xilinx_uartlite.txt

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 604f6815af5b..30ea484f48aa 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -13,6 +13,7 @@ config TARGET_MICROBLAZE_GENERIC
   select SUPPORT_SPL
   select OF_CONTROL
   select DM
+select DM_SERIAL

   endchoice

diff --git a/configs/microblaze-generic_defconfig
b/configs/microblaze-generic_defconfig
index 54aa3ef3d26f..5df080b6a87c 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -1,9 +1,11 @@
   CONFIG_MICROBLAZE=y
   CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
   CONFIG_TARGET_MICROBLAZE_GENERIC=y
   CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
   CONFIG_SPL=y
   CONFIG_SYS_PROMPT="U-Boot-mONStR> "
   CONFIG_CMD_GPIO=y
   # CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_CONTROL=y
   CONFIG_OF_EMBED=y
diff --git a/doc/device-tree-bindings/serial/xilinx_uartlite.txt
b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
new file mode 100644
index ..d15753c8c380
--- /dev/null
+++ b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
@@ -0,0 +1,13 @@
+Binding for Xilinx Uartlite Controller
+
+Required properties:
+- compatible : should be "xlnx,xps-uartlite-1.00.a", or
"xlnx,opb-uartlite-1.00.b"
+- reg: Should contain UART controller registers location and length.
+- interrupts: Should contain UART controller interrupts.
+
+Example:
+serial@4060 {
+compatible = "xlnx,xps-uartlite-1.00.a";
+interrupts = <1 0>;
+reg = <0x4060 0x1>;
+};
diff --git a/doc/driver-model/serial-howto.txt
b/doc/driver-model/serial-howto.txt
index 76ad629ef9cb..381a2a084562 100644
--- a/doc/driver-model/serial-howto.txt
+++ b/doc/driver-model/serial-howto.txt
@@ -18,7 +18,6 @@ is time for maintainers to start converting over the
remaining serial drivers:
  serial_pxa.c
  serial_s3c24x0.c
  serial_sa1100.c
-   serial_xuartlite.c
  usbtty.c

   You should complete this by the end of January 2016.
diff --git a/drivers/serial/serial_xuartlite.c
b/drivers/serial/serial_xuartlite.c
index 988438e75471..8225d9a320a5 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -1,5 +1,5 @@
   /*
- * (C) Copyright 2008-2011 Michal Simek 
+ * (C) Copyright 2008 - 2015 Michal Simek 
* Clean driver and add xilinx constant from header file
*
* (C) Copyright 2004 Atmark Techno, Inc.
@@ -10,11 +10,15 @@

   #include 
   #include 
+#include 
   #include 
   #include 
   #include 

+DECLARE_GLOBAL_DATA_PTR;
+
   #define SR_TX_FIFO_FULL0x08 /* transmit FIFO full */
+#define SR_TX_FIFO_EMPTY0x04 /* transmit FIFO empty */
   #define SR_RX_FIFO_VALID_DATA0x01 /* data in receive FIFO */
   #define SR_RX_FIFO_FULL0x02 /* receive FIFO full */

@@ -28,135 +32,85 @@ struct uartlite {
   unsigned int control;
   };

-static struct uartlite *userial_ports[4] = {
-#ifdef XILINX_UARTLITE_BASEADDR
-[0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR1
-[1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR2
-[2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR3
-[3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
-#endif
+struct uartlite_platdata {
+struct uartlite *regs;
   };

-static void uartlite_serial_putc(const char c, const int port)
+static int uartlite_serial_putc(struct udevice *dev, const char ch)
   {
-struct uartlite *regs = userial_ports[port];
+struct uartlite_platdata *plat = dev_get_platdata(dev);
+struct uartlite *regs = plat->regs;

-if (c == '\n')
-uartlite_serial_putc('\r', port);
+if (in_be32(>status) & SR_TX_FIFO_FULL)
+return -EAGAIN;

-while (in_be32(>status) & SR_TX_FIFO_FULL)
-;
-out_be32(>tx_fifo, c & 0xff);
-}
+out_be32(>tx_fifo, ch & 0xff);

-static void uartlite_serial_puts(const char *s, const int port)
-{
-while (*s)
-

[U-Boot] [PATCH v2 2/3] serial: uartlite: Add support for debug console

[Michal Simek]

Add support for debug console.

Signed-off-by: Michal Simek 
---

Changes in v2:
- Add needed header from the first patch
- Remove WATCHDOG_RESET call
- Extend commit description

 drivers/serial/Kconfig|  7 +++
 drivers/serial/serial_xuartlite.c | 26 ++
 2 files changed, 33 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1fc287ee98ec..f1e221799b81 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -92,6 +92,13 @@ config DEBUG_UART_S5P
  will need to provide parameters to make this work. The driver will
  be available until the real driver-model serial is running.
 
+config DEBUG_UART_UARTLITE
+   bool "Xilinx Uartlite"
+   help
+ Select this to enable a debug UART using the serial_uartlite driver.
+ You will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
 config DEBUG_UART_ZYNQ
bool "Xilinx Zynq"
help
diff --git a/drivers/serial/serial_xuartlite.c 
b/drivers/serial/serial_xuartlite.c
index 8225d9a320a5..f42b11eae102 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -114,3 +114,29 @@ U_BOOT_DRIVER(serial_uartlite) = {
.ops= _serial_ops,
.flags = DM_FLAG_PRE_RELOC,
 };
+
+#ifdef CONFIG_DEBUG_UART_UARTLITE
+
+#include 
+
+void _debug_uart_init(void)
+{
+   struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
+
+   out_be32(>control, 0);
+   out_be32(>control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+   in_be32(>control);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+   struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
+
+   while (in_be32(>status) & SR_TX_FIFO_FULL)
+   ;
+
+   out_be32(>tx_fifo, ch & 0xff);
+}
+
+DEBUG_UART_FUNCS
+#endif
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 3/3] serial: uartlite: Add uartlite to Kconfig

[Michal Simek]

- Move config option out of board file.
- Remove uartlite address from config file

Signed-off-by: Michal Simek 
---

Changes in v2: None

 board/xilinx/microblaze-generic/xparameters.h | 4 
 configs/microblaze-generic_defconfig  | 1 +
 drivers/serial/Kconfig| 7 +++
 include/configs/microblaze-generic.h  | 7 +--
 4 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/board/xilinx/microblaze-generic/xparameters.h 
b/board/xilinx/microblaze-generic/xparameters.h
index 8ba146cb88db..11b3c9a4846e 100644
--- a/board/xilinx/microblaze-generic/xparameters.h
+++ b/board/xilinx/microblaze-generic/xparameters.h
@@ -28,10 +28,6 @@
 #define XILINX_TIMER_BASEADDR  0x41c0
 #define XILINX_TIMER_IRQ   0
 
-/* Uart pheriphery is RS232_Uart */
-#define XILINX_UARTLITE_BASEADDR   0x4060
-#define XILINX_UARTLITE_BAUDRATE   115200
-
 /* IIC pheriphery is IIC_EEPROM */
 #define XILINX_IIC_0_BASEADDR  0x4080
 #define XILINX_IIC_0_FREQ  10
diff --git a/configs/microblaze-generic_defconfig 
b/configs/microblaze-generic_defconfig
index 5df080b6a87c..9a7bb915466f 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -9,3 +9,4 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
+CONFIG_XILINX_UARTLITE=y
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f1e221799b81..ddf49ba9cef3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -230,4 +230,11 @@ config UNIPHIER_SERIAL
  If you have a UniPhier based board and want to use the on-chip
  serial ports, say Y to this option. If unsure, say N.
 
+config XILINX_UARTLITE
+   bool "Xilinx Uarlite support"
+   depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+   help
+ If you have a Xilinx based board and want to use the uartlite
+ serial ports, say Y to this option. If unsure, say N.
+
 endmenu
diff --git a/include/configs/microblaze-generic.h 
b/include/configs/microblaze-generic.h
index 10ac8328b8ff..6e3c80b14350 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -37,10 +37,7 @@
 # define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
-#ifdef XILINX_UARTLITE_BASEADDR
-# define CONFIG_XILINX_UARTLITE
-# define CONFIG_SERIAL_BASEXILINX_UARTLITE_BASEADDR
-#elif XILINX_UART16550_BASEADDR
+#if XILINX_UART16550_BASEADDR
 # define CONFIG_SYS_NS16550_SERIAL
 # if defined(__MICROBLAZEEL__)
 #  define CONFIG_SYS_NS16550_REG_SIZE  -4
@@ -51,8 +48,6 @@
 # define CONFIG_SYS_NS16550_COM1 \
((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
 # define CONFIG_SYS_NS16550_CLKXILINX_UART16550_CLOCK_HZ
-#else
-# error Undefined uart
 #endif
 
 /* setting reset address */
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 1/3] serial: uartlite: Move driver to DM

[Michal Simek]

Enable SPL DM too.

Signed-off-by: Michal Simek 
---

Changes in v2:
- Remove unneeded headers
- Use get_dev_addr instead of fdtdec_get_addr
- Use platdata instead of private data
- Add opb compatible string to be in sync with Linux
- Add binding documentation

 arch/microblaze/Kconfig|   1 +
 configs/microblaze-generic_defconfig   |   2 +
 .../serial/xilinx_uartlite.txt |  13 ++
 doc/driver-model/serial-howto.txt  |   1 -
 drivers/serial/serial_xuartlite.c  | 170 -
 5 files changed, 78 insertions(+), 109 deletions(-)
 create mode 100644 doc/device-tree-bindings/serial/xilinx_uartlite.txt

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 604f6815af5b..30ea484f48aa 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -13,6 +13,7 @@ config TARGET_MICROBLAZE_GENERIC
select SUPPORT_SPL
select OF_CONTROL
select DM
+   select DM_SERIAL
 
 endchoice
 
diff --git a/configs/microblaze-generic_defconfig 
b/configs/microblaze-generic_defconfig
index 54aa3ef3d26f..5df080b6a87c 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -1,9 +1,11 @@
 CONFIG_MICROBLAZE=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
 CONFIG_TARGET_MICROBLAZE_GENERIC=y
 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
 CONFIG_SPL=y
 CONFIG_SYS_PROMPT="U-Boot-mONStR> "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
diff --git a/doc/device-tree-bindings/serial/xilinx_uartlite.txt 
b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
new file mode 100644
index ..d15753c8c380
--- /dev/null
+++ b/doc/device-tree-bindings/serial/xilinx_uartlite.txt
@@ -0,0 +1,13 @@
+Binding for Xilinx Uartlite Controller
+
+Required properties:
+- compatible : should be "xlnx,xps-uartlite-1.00.a", or 
"xlnx,opb-uartlite-1.00.b"
+- reg: Should contain UART controller registers location and length.
+- interrupts: Should contain UART controller interrupts.
+
+Example:
+   serial@4060 {
+   compatible = "xlnx,xps-uartlite-1.00.a";
+   interrupts = <1 0>;
+   reg = <0x4060 0x1>;
+   };
diff --git a/doc/driver-model/serial-howto.txt 
b/doc/driver-model/serial-howto.txt
index 76ad629ef9cb..381a2a084562 100644
--- a/doc/driver-model/serial-howto.txt
+++ b/doc/driver-model/serial-howto.txt
@@ -18,7 +18,6 @@ is time for maintainers to start converting over the 
remaining serial drivers:
serial_pxa.c
serial_s3c24x0.c
serial_sa1100.c
-   serial_xuartlite.c
usbtty.c
 
 You should complete this by the end of January 2016.
diff --git a/drivers/serial/serial_xuartlite.c 
b/drivers/serial/serial_xuartlite.c
index 988438e75471..8225d9a320a5 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2008-2011 Michal Simek 
+ * (C) Copyright 2008 - 2015 Michal Simek 
  * Clean driver and add xilinx constant from header file
  *
  * (C) Copyright 2004 Atmark Techno, Inc.
@@ -10,11 +10,15 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define SR_TX_FIFO_FULL0x08 /* transmit FIFO full */
+#define SR_TX_FIFO_EMPTY   0x04 /* transmit FIFO empty */
 #define SR_RX_FIFO_VALID_DATA  0x01 /* data in receive FIFO */
 #define SR_RX_FIFO_FULL0x02 /* receive FIFO full */
 
@@ -28,135 +32,85 @@ struct uartlite {
unsigned int control;
 };
 
-static struct uartlite *userial_ports[4] = {
-#ifdef XILINX_UARTLITE_BASEADDR
-   [0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR1
-   [1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR2
-   [2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
-#endif
-#ifdef XILINX_UARTLITE_BASEADDR3
-   [3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
-#endif
+struct uartlite_platdata {
+   struct uartlite *regs;
 };
 
-static void uartlite_serial_putc(const char c, const int port)
+static int uartlite_serial_putc(struct udevice *dev, const char ch)
 {
-   struct uartlite *regs = userial_ports[port];
+   struct uartlite_platdata *plat = dev_get_platdata(dev);
+   struct uartlite *regs = plat->regs;
 
-   if (c == '\n')
-   uartlite_serial_putc('\r', port);
+   if (in_be32(>status) & SR_TX_FIFO_FULL)
+   return -EAGAIN;
 
-   while (in_be32(>status) & SR_TX_FIFO_FULL)
-   ;
-   out_be32(>tx_fifo, c & 0xff);
-}
+   out_be32(>tx_fifo, ch & 0xff);
 
-static void uartlite_serial_puts(const char *s, const int port)
-{
-   while (*s)
-   uartlite_serial_putc(*s++, port);
+   return 0;
 }
 
-static int 

[U-Boot] [PATCH v2 02/11] net: axi_emac: Show phy address instead of register content

[Michal Simek]

Fix debug message.

Signed-off-by: Michal Simek 
Acked-by: Joe Hershberger 
---

Changes in v2: None

 drivers/net/xilinx_axi_emac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 994affa66fc4..f08823008908 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -243,7 +243,7 @@ static int setup_phy(struct eth_device *dev)
/* Found a valid PHY address */
priv->phyaddr = i;
debug("axiemac: Found valid phy address, %x\n",
-   phyreg);
+ i);
break;
}
}
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot