Re: [U-Boot] [PATCH 2/2] sunxi: A64: enable USB support

[Amit Tomer]

Hello!

>
> Since the driver is dm-driven this config not need.

I tried not to use this config but then driver don't get compiled.

You're talking about   CONFIG_USB_EHCI and CONFIG_USB_EHCI_SUNXI, right ?

Thanks
Amit.
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Re: [U-Boot] [PATCH] pci: Move CONFIG_PCI_PNP to Kconfig

[Tom Rini]

On Tue, Oct 25, 2016 at 09:08:04AM +0800, Bin Meng wrote:
> Hi Tom,
> 
> On Mon, Oct 17, 2016 at 7:50 PM, Tom Rini  wrote:
> > On Sun, Oct 16, 2016 at 11:35:18PM -0700, Bin Meng wrote:
> >
> >> Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig
> >> to use that.
> >>
> >> Signed-off-by: Bin Meng 
> >>
> >> ---
> >>
> >> Changes in v2:
> >> - Change PCI_PNP to "depends on" and "default y" if PCI || DM_PCI
> >
> > Thanks!
> >
> > [snip]
> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> >> index 9a7c187..5252250 100644
> >> --- a/drivers/pci/Kconfig
> >> +++ b/drivers/pci/Kconfig
> >> @@ -18,6 +18,13 @@ config DM_PCI_COMPAT
> >> measure when porting a board to use driver model for PCI. Once the
> >> board is fully supported, this option should be disabled.
> >>
> >> +config PCI_PNP
> >> + bool "Enable Plug & Play support for PCI"
> >> + depends on PCI || DM_PCI
> >> + default y if PCI || DM_PCI
> >
> > This should just be default y since we depend on those two options
> > directly.  I'll just fix it up when applying.
> >
> > Reviewed-by: Tom Rini 
> >
> 
> Will this be picked up for the v2016.11 release?

PCI itself needs to be fully migrated first, it exists in
arch/sandbox/Kconfig which is why this patch doesn't totally blow up,
but it does get a lot of build failures :)

-- 
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Re: [U-Boot] [PATCH] pci: Move CONFIG_PCI_PNP to Kconfig

[Bin Meng]

Hi Tom,

On Mon, Oct 17, 2016 at 7:50 PM, Tom Rini  wrote:
> On Sun, Oct 16, 2016 at 11:35:18PM -0700, Bin Meng wrote:
>
>> Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig
>> to use that.
>>
>> Signed-off-by: Bin Meng 
>>
>> ---
>>
>> Changes in v2:
>> - Change PCI_PNP to "depends on" and "default y" if PCI || DM_PCI
>
> Thanks!
>
> [snip]
>> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> index 9a7c187..5252250 100644
>> --- a/drivers/pci/Kconfig
>> +++ b/drivers/pci/Kconfig
>> @@ -18,6 +18,13 @@ config DM_PCI_COMPAT
>> measure when porting a board to use driver model for PCI. Once the
>> board is fully supported, this option should be disabled.
>>
>> +config PCI_PNP
>> + bool "Enable Plug & Play support for PCI"
>> + depends on PCI || DM_PCI
>> + default y if PCI || DM_PCI
>
> This should just be default y since we depend on those two options
> directly.  I'll just fix it up when applying.
>
> Reviewed-by: Tom Rini 
>

Will this be picked up for the v2016.11 release?

Regards,
Bin
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[U-Boot] [RFC PATCH] lib/timer: initialize timebase_l/timebase_h

[Andre Przywara]

On systems using the generic timer routines defined in lib/time.c we
use timebase_l and timebase_h fields from the gd to detect wraparounds
in our tick counter. The tick calculcation algorithm silently assumes
that a long is only 32 bits, which leads to wrong results when timebase_h
is not 0 on 64-bit systems.
As one possible fix lets initialize timebase_h (and timebase_l) to 0, so
on 64-bit systems timebase_h will never(TM) be bigger than 0 and thus
cannot spoil timebase_l by being ORed into it.

This fixes occasional timeout issues on the Pine64 (and possibly other
ARM64 systems).

Signed-off-by: Andre Przywara 
---
Hi,

I am bit puzzled what the proper fix is, this one is the easiest I could
come up with. Not sure if the gd should be zeroed normally (and it's just
broken on sunxi/arm64 because of some linker issues) or whether we really
forgot to initialize those fields and just got away with it.
Other fixes I tried are implementing get_ticks() in armv8/generic_timer.c
or fixing the generic get_ticks() implementation by using
"#if BITS_PER_LONG < 64" in the function to shortcut the code on 64-bit
systems.
Please have your say on what's best.

Cheers,
Andre.

P.S. "Never" above seems to be 195 years assuming a worst-case 3GHz
arch timer.

 lib/time.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/time.c b/lib/time.c
index f37150f..b77d134 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -109,6 +109,8 @@ static uint64_t notrace tick_to_time(uint64_t tick)
 
 int __weak timer_init(void)
 {
+   gd->timebase_l = 0;
+   gd->timebase_h = 0;
return 0;
 }
 
-- 
2.8.2

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Re: [U-Boot] [PATCH 1/2] travis-ci: set env vars to name jobs

[Tom Rini]

On Mon, Oct 24, 2016 at 05:18:24PM -0600, Stephen Warren wrote:
> On 10/24/2016 05:03 PM, Tom Rini wrote:
> >On Mon, Oct 24, 2016 at 04:41:48PM -0600, Stephen Warren wrote:
> >
> >>From: Stephen Warren 
> >>
> >>Travis CI names sub-jobs after the first environment variable that is set
> >>for a script. This doesn't produce meaningful results for any of the non-
> >>buildman jobs. Add a dummy variable to give the jobs meaningful names.
> >>
> >>Signed-off-by: Stephen Warren 
> >
> >I'm not sure.  This un-does in part killing off TEST_CMD as a hook.  At
> >the end of the day, imho, what is important from travis-ci are the
> >emails it sends (which are starting and pass/fail/interrupted) and the
> >other notifications.
> 
> I don't believe I've ever received emails from Travis, although I
> haven't used it in a while so perhaps it's a new feature.

Ah, https://docs.travis-ci.com/user/notifications#Email-notifications
explains and it's setup by default to not spam uninterested parties.
Which I think in turn means it also doesn't email interested parties
easily, sadly.

> Either way, I do like to look at the web UI to watch/check status
> sometimes, and certainly would after a failure to track down the
> problem, and this change makes the job list there possible to
> interpret, whereas it isn't without it:
> 
> https://travis-ci.org/swarren/u-boot/builds/170278972

Yeah, I spent a lot of time with the UI when I was doing the last
series.  And since it is indeed harder to get email notifications than I
would like, this makes sense too.

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH V4 1/8] tools: imximage: add plugin support

[Peng Fan]

Hi Stefano,
On Mon, Oct 24, 2016 at 04:05:53PM +0200, Stefano Babic wrote:
>Hi Peng,
>
>On 11/10/2016 08:29, Peng Fan wrote:
>> Add plugin support for imximage.
>> 
>> Define CONFIG_USE_IMXIMG_PLUGIN in defconfig to enable using plugin.
>> 
>> Signed-off-by: Peng Fan 
>> Cc: Stefano Babic 
>> Cc: Eric Nelson 
>> Cc: Ye Li 
>> Reviewed-by: Tom Rini 
>> ---
>> 
>
>I have just the same issue as with Jagan's patches. Due to recent
>changes, we need to unset a couple of defines in defconfig (ull without
>plugin is already fixed).
>
>This means:
>
>diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig
>b/configs/mx6ull_14x14_evk_plugin_defconfig
>index ff15c8e..095e48d 100644
>--- a/configs/mx6ull_14x14_evk_plugin_defconfig
>+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
>@@ -25,6 +25,8 @@ CONFIG_DM_GPIO=y
> CONFIG_DM_74X164=y
> CONFIG_DM_I2C=y
> CONFIG_DM_MMC=y
>+# CONFIG_BLK is not set
>+# CONFIG_DM_MMC_OPS is not set
> CONFIG_PINCTRL=y
> CONFIG_PINCTRL_IMX6=y
> CONFIG_DM_REGULATOR=y
>
>
>If you agree, I will make the change by applying it.

Yeah. Please help do this.

Thanks,
Peng.
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Re: [U-Boot] [PATCH 1/2] travis-ci: set env vars to name jobs

[Stephen Warren]

On 10/24/2016 05:03 PM, Tom Rini wrote:

On Mon, Oct 24, 2016 at 04:41:48PM -0600, Stephen Warren wrote:


From: Stephen Warren 

Travis CI names sub-jobs after the first environment variable that is set
for a script. This doesn't produce meaningful results for any of the non-
buildman jobs. Add a dummy variable to give the jobs meaningful names.

Signed-off-by: Stephen Warren 


I'm not sure.  This un-does in part killing off TEST_CMD as a hook.  At
the end of the day, imho, what is important from travis-ci are the
emails it sends (which are starting and pass/fail/interrupted) and the
other notifications.


I don't believe I've ever received emails from Travis, although I 
haven't used it in a while so perhaps it's a new feature.


Either way, I do like to look at the web UI to watch/check status 
sometimes, and certainly would after a failure to track down the 
problem, and this change makes the job list there possible to interpret, 
whereas it isn't without it:


https://travis-ci.org/swarren/u-boot/builds/170278972
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Re: [U-Boot] [PATCH 1/2] travis-ci: set env vars to name jobs

[Tom Rini]

On Mon, Oct 24, 2016 at 04:41:48PM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> Travis CI names sub-jobs after the first environment variable that is set
> for a script. This doesn't produce meaningful results for any of the non-
> buildman jobs. Add a dummy variable to give the jobs meaningful names.
> 
> Signed-off-by: Stephen Warren 

I'm not sure.  This un-does in part killing off TEST_CMD as a hook.  At
the end of the day, imho, what is important from travis-ci are the
emails it sends (which are starting and pass/fail/interrupted) and the
other notifications.

On the other hand it does seem to be common practice to do something
along these lines. So, in the end, I don't know.

-- 
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Re: [U-Boot] [PATCH 1/5] arm: dts: exynos4x12: fix the minor things

[Tom Rini]

On Mon, Oct 24, 2016 at 03:08:53PM +0900, Jaehoon Chung wrote:

> Fixed the minor things.
> 1. Removed '`' thing in comments
> 2. Fix the wrong interrupts value from 77 to 131
> 
> Signed-off-by: Jaehoon Chung 
> ---
>  arch/arm/dts/exynos4x12.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

For this and the rest of the series, are these problems present in the
Linux Kernel or are you backporting fixes?  If backporting you should
note that, thanks.

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Re: [U-Boot] [PATCH 2/2] travis-ci: remove duplicate build

[Tom Rini]

On Mon, Oct 24, 2016 at 04:41:49PM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> There were two sub-jobs to build arm1136. Remove the duplicate.
> 
> Signed-off-by: Stephen Warren 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 1/2] drivers: USB: OHCI: allow compilation for 64-bit targets

[André Przywara]

On 24/10/16 09:20, Jagan Teki wrote:
> On Sun, Oct 23, 2016 at 3:22 AM, André Przywara  
> wrote:
>> On 22/10/16 18:10, Jagan Teki wrote:
>>
>> Hi,
>>
>>> On Fri, Oct 21, 2016 at 6:54 AM, Andre Przywara  
>>> wrote:
 OHCI has a known limitation of allowing only 32-bit DMA buffer
 addresses, so we have a lot of u32 variables around, which are assigned
 to pointers and vice versa. This obviously creates issues with 64-bit
 systems, so the compiler complains here and there.
 To allow compilation for 64-bit boards which use only memory below 4GB
 anyway (and to avoid more invasive fixes), adjust some casts and types
 and assume that the EDs and TDs are all located in the lower 4GB.
 This fixes compilation of the OHCI driver for the Pine64.

 Signed-off-by: Andre Przywara 
 ---
  drivers/usb/host/ohci-hcd.c   | 21 +++--
  drivers/usb/host/ohci-sunxi.c |  2 +-
  drivers/usb/host/ohci.h   | 11 +++
  3 files changed, 19 insertions(+), 15 deletions(-)

 diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
 index ccbfc02..0f6d03e 100644
 --- a/drivers/usb/host/ohci-hcd.c
 +++ b/drivers/usb/host/ohci-hcd.c
 @@ -682,7 +682,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
 ed->hwNextED = 0;
 flush_dcache_ed(ed);
 if (ohci->ed_controltail == NULL)
 -   ohci_writel(ed, >regs->ed_controlhead);
 +   ohci_writel((uintptr_t)ed, 
 >regs->ed_controlhead);
 else
 ohci->ed_controltail->hwNextED =
m32_swap((unsigned 
 long)ed);
 @@ -700,7 +700,7 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
 ed->hwNextED = 0;
 flush_dcache_ed(ed);
 if (ohci->ed_bulktail == NULL)
 -   ohci_writel(ed, >regs->ed_bulkhead);
 +   ohci_writel((uintptr_t)ed, 
 >regs->ed_bulkhead);
 else
 ohci->ed_bulktail->hwNextED =
m32_swap((unsigned 
 long)ed);
 @@ -753,7 +753,7 @@ static void periodic_unlink(struct ohci *ohci, 
 volatile struct ed *ed,

 /* ED might have been unlinked through another path */
 while (*ed_p != 0) {
 -   if (((struct ed *)
 +   if (((struct ed *)(uintptr_t)
 m32_swap((unsigned long)ed_p)) == 
 ed) {
 *ed_p = ed->hwNextED;
 aligned_ed_p = (unsigned long)ed_p;
 @@ -762,7 +762,7 @@ static void periodic_unlink(struct ohci *ohci, 
 volatile struct ed *ed,
 aligned_ed_p + ARCH_DMA_MINALIGN);
 break;
 }
 -   ed_p = &(((struct ed *)
 +   ed_p = &(((struct ed *)(uintptr_t)
  m32_swap((unsigned 
 long)ed_p))->hwNextED);
 }
 }
 @@ -798,7 +798,7 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi)
 if (ohci->ed_controltail == ed) {
 ohci->ed_controltail = ed->ed_prev;
 } else {
 -   ((ed_t *)m32_swap(
 +   ((ed_t *)(uintptr_t)m32_swap(
 *((__u32 *)>hwNextED)))->ed_prev = 
 ed->ed_prev;
 }
 break;
 @@ -819,7 +819,7 @@ static int ep_unlink(ohci_t *ohci, ed_t *edi)
 if (ohci->ed_bulktail == ed) {
 ohci->ed_bulktail = ed->ed_prev;
 } else {
 -   ((ed_t *)m32_swap(
 +   ((ed_t *)(uintptr_t)m32_swap(
  *((__u32 *)>hwNextED)))->ed_prev = 
 ed->ed_prev;
 }
 break;
 @@ -914,12 +914,13 @@ static void td_fill(ohci_t *ohci, unsigned int info,

 /* fill the old dummy TD */
 td = urb_priv->td [index] =
 -(td_t *)(m32_swap(urb_priv->ed->hwTailP) & 
 ~0xf);
 +(td_t *)(uintptr_t)
 +(m32_swap(urb_priv->ed->hwTailP) & ~0xf);

 td->ed = urb_priv->ed;
 td->next_dl_td = NULL;
 td->index = index;
 -   td->data = (__u32)data;
 +   td->data = (uintptr_t)data;
  #ifdef OHCI_FILL_TRACE
 if 

Re: [U-Boot] [PATCH v2] powerpc/t2080: CPU erratum A-007907

[york sun]

On 10/24/2016 01:48 PM, Darwin Dingel wrote:
> Core hang occurs when using L1 stashes. Workaround is to disable L1
> stashes so software uses L2 cache for stashes instead.
>
> Reviewed-by: Chris Packham 
> Signed-off-by: Darwin Dingel 
> Cc: York Sun 
> ---
> Changes for v2:
> - Enabled for T4240 and B4860
>

Thanks for doing this.
The subject should be updated to not specific to T2080, if you respin 
this patch for any reason.

>  arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +++-
>  arch/powerpc/cpu/mpc85xx/cpu_init.c   | 7 +++
>  arch/powerpc/include/asm/config_mpc85xx.h | 3 +++
>  arch/powerpc/include/asm/processor.h  | 1 +
>  4 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
> b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> index 3b06ae4..197eb2f 100644
> --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> @@ -329,7 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int 
> argc, char * const argv[])
>  #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
>   puts("Work-around for Erratum A009663 enabled\n");
>  #endif
> -
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
> + puts("Work-around for Erratum A007907 enabled\n");
> +#endif
>   return 0;
>  }
>
> diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
> b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> index 53b3729..0e744f0 100644
> --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
> +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> @@ -775,6 +775,13 @@ int cpu_init_r(void)
>   sync();
>   }
>  #endif
> +
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
> + flush_dcache();
> + mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
> + sync();
> +#endif
> +

My erratum document shows a second step is to insert sync instruction 
before each dcbtls CT=0 or dcbtstls CT=0. I only see dcbtls used in 
start.S and no referendce to dcbtstls at all. I will consult the design 
team to confirm if the second step.

York

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Re: [U-Boot] [PATCH v2 8/8] travis-ci: Add test.py for various qemu platforms

[Tom Rini]

On Mon, Oct 24, 2016 at 04:21:36PM -0600, Stephen Warren wrote:
[snip]
> BTW, does/can Travis save the test-log.html from the test.py
> invocations? That would make debugging any failures a little easier.

I'm far from a travis "expert".  But the real nice thing about it is
that you can hook up and test via github.  It took maybe 2 minutes to
get my u-boot clone going in travis-ci so I could test things out, and
that's something I want to emphasize in -rc3 is how easy it is to get a
lot more coverage with minimal effort.

So since a script clause is just a bit of bash commands basically, some
sort of quick wrapper or maybe just pass in -s to test.py since another
nice thing is that the web view will collapse output from each step?

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[U-Boot] [PATCH 1/2] travis-ci: set env vars to name jobs

[Stephen Warren]

From: Stephen Warren 

Travis CI names sub-jobs after the first environment variable that is set
for a script. This doesn't produce meaningful results for any of the non-
buildman jobs. Add a dummy variable to give the jobs meaningful names.

Signed-off-by: Stephen Warren 
---
 .travis.yml | 24 +++-
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index d65c5705875f..a172180a9953 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -160,30 +160,42 @@ matrix:
 
 # QA jobs for code analytics
 # static code analysis with cppcheck (we can add --enable=all later)
-- script:
+- env:
+- JOB="cppcheck"
+  script:
 - cppcheck --force --quiet --inline-suppr .
 # search for TODO within source tree
-- script:
+- env:
+- JOB="grep TODO"
+  script:
 - grep -r TODO .
 # search for FIXME within source tree
-- script:
+- env:
+- JOB="grep FIXME HACK"
+  script:
 - grep -r FIXME .
 # search for HACK within source tree and ignore HACKKIT board
   script:
 - grep -r HACK . | grep -v HACKKIT
 # some statistics about the code base
-- script:
+- env:
+- JOB="sloccount"
+  script:
 - sloccount .
 # test/py
-- script:
+- env:
+- JOB="test.py sandbox"
+  script:
 - ./test/py/test.py --bd sandbox --build
 - env:
+- JOB="test.py ARM"
 - CROSS_COMPILE="/usr/bin/arm-linux-gnueabihf-"
   script:
 - ./test/py/test.py --bd vexpress_ca15_tc2 --id qemu --build;
   ./test/py/test.py --bd vexpress_ca9x4 --id qemu --build;
   ./test/py/test.py --bd integratorcp_cm926ejs --id qemu --build;
 - env:
+- JOB="test.py MIPS"
 - TOOLCHAIN="mips"
   
CROSS_COMPILE="${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-"
   script:
@@ -192,10 +204,12 @@ matrix:
   ./test/py/test.py --bd qemu_mips64 --build -k 'not sleep';
   ./test/py/test.py --bd qemu_mips64el --build -k 'not sleep';
 - env:
+- JOB="test.py PowerPC"
 - CROSS_COMPILE="/usr/bin/powerpc-linux-gnu-"
   script:
 - ./test/py/test.py --bd qemu-ppce500 --build -k 'not sleep'
 - env:
+- JOB="test.py x86-64"
 - TOOLCHAIN="x86_64"
   BUILD_ROM=yes
   
CROSS_COMPILE="${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-"
-- 
2.10.1

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[U-Boot] [PATCH 2/2] travis-ci: remove duplicate build

[Stephen Warren]

From: Stephen Warren 

There were two sub-jobs to build arm1136. Remove the duplicate.

Signed-off-by: Stephen Warren 
---
 .travis.yml | 2 --
 1 file changed, 2 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index a172180a9953..00be5ff20396 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -85,8 +85,6 @@ matrix:
 - env:
 - BUILDMAN="arm1136"
 - env:
-- BUILDMAN="arm1136"
-- env:
 - BUILDMAN="arm1176"
 - env:
 - BUILDMAN="arm720t"
-- 
2.10.1

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[U-Boot] [RFC PATCH v1] mvebu: db-88f6820-amc: Enable FIT support

[Chris Packham]

Signed-off-by: Chris Packham 
---
I'm keen to see this for the 88f6820-amc at least but I did wonder if it
should be enabled for more of the mvebu boards? Marvell don't really
make use of FIT images in their SDKs but I personally find them
incredibly useful. It adds about 32KiB to the final image but I think
it's well worth it.

 configs/db-88f6820-amc_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index b9f0ec3e07e6..ba624494ce30 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -8,6 +8,8 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTDELAY=3
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
-- 
2.10.1

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Re: [U-Boot] [PATCH] arm: dts: Pine64: add Ethernet alias

[André Przywara]

On 21/10/16 11:28, Hans de Goede wrote:
> Hi,
> 
> On 21-10-16 12:06, Andre Przywara wrote:
>> Hi,
>>
>> On 21/10/16 10:31, Jagan Teki wrote:
>>> On Fri, Oct 21, 2016 at 5:41 AM, Andre Przywara
>>>  wrote:
 The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
 missing an alias entry to trigger the driver instantiation by U-Boot.
 Add the line to point U-Boot to the Ethernet DT node.
 This enables TFTP boot on the Pine64.

 Signed-off-by: Andre Przywara 
 ---
  arch/arm/dts/sun50i-a64-pine64-common.dtsi | 1 +
  1 file changed, 1 insertion(+)

 diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
 b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
 index d5a7249..c0fde44 100644
 --- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
 +++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
 @@ -46,6 +46,7 @@

 aliases {
 serial0 = 
 +   ethernet0 = 
>>>
>>> I think alias doesn’t require for probing emac, it will straight away
>>> probed like
>>>
 dm tree
>>> 
>>> eth [ + ] ethernet@01c3
>>>
>>> Did you find any issue while detecting eth?
>>
>> Yes, it just didn't work ;-) I don't have a board here, but can post the
>> error message later tonight.


Net:   phy interface7

Error: ethernet@01c3 address not set.
No ethernet found.


>> In fact I was wondering about that already, maybe it's worth
>> investigating this further.

So the reason is that CONFIG_NET_RANDOM_ETHADDR isn't defined, so
without the DT alias triggering the SID MAC generation there will be
_no_ MAC address at all, which makes the driver give up.
AFAIK on the A64 the MAC generation from the SID serial number works
just fine, so we should in any case add the alias.

I can resend the patch with an amended commit message.

Cheers,
Andre.

>>
>> But aside from that I think the MAC address calculation based on the SID
>> serial number does not get triggered without an alias, so we need this
>> line anyway.
> 
> Correct, the MAC address code relies on the alias.
> 
> Regards,
> 
> Hans
> 

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Re: [U-Boot] [PATCH v2 8/8] travis-ci: Add test.py for various qemu platforms

[Stephen Warren]

On 10/22/2016 06:56 AM, Tom Rini wrote:

On Fri, Oct 21, 2016 at 12:24:07PM -0600, Stephen Warren wrote:

On 10/20/2016 01:40 PM, Tom Rini wrote:

- Add a PPA for a more recent qemu (required for PowerPC to work)
- Add tests to run test.py for various QEMU platforms.  This relies on
 swarren's uboot-test-hooks repository to provide the abstractions.



+ # Clone uboot-test-hooks
+ - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git 
/tmp/uboot-test-hooks


Does it make sense to rely on my copy of the repo being around all
the time? I have no intention of removing it, but when I created it
I'd assumed others would create their own clones for their own
infra-structure. I wonder if all the dependencies for U-Boot's
testing should be hosted on U-Boot infra-structure?


A good point.  The way I've been thinking of it is that we also need a
repo with as many and varied configs as possible, which has become yours
:).  That said, we could move a copy of this over to the u-boot account
on github if you'd like.


I think it's fine for now.


That all said, this should be fine; just something to ponder.


+ - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`


It may be useful to add the following too:

- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`

That way, if we ever need per-board test configuration files, the
path to access them will already be available.


A good point.  I think we could get the network tests going, maybe with
a little re-work to dynamically hash the file from the host side?  But
that's an aside.


Yes, assuming qemu networking works, I expect that would be possible. 
Yes, I think it'd be pretty easy to dynamically create a test download 
file and calculate the CRC from the per-board Python config files.



+- env:
+- CROSS_COMPILE="/usr/bin/arm-linux-gnueabihf-"
+  script:
+- ./test/py/test.py --bd vexpress_ca15_tc2 --id qemu --build;
+  ./test/py/test.py --bd vexpress_ca9x4 --id qemu --build;
+  ./test/py/test.py --bd integratorcp_cm926ejs --id qemu --build;


Does it make sense to make that 3 separate scripts? I assume that
would (a) allow the individual status of the 3 test.py invocations
to be seen separately (b) might allow/cause travis-ci to run them in
parallel; I'm not sure if this Travis config file is a sequential
list of commands, or a list of potentially parallel actions.


So, the way travis-ci works is that you can (and we do) split tasks up
to run in parallel.  The hunk above is a series to run in sequence on
the same host. The downside to moving this to parallel is the amount of
duplication you need in each stanza.


The duplication doesn't seem like a terribly big deal given it will 
allow finer-grained status on the main per-build page.


> We could fix that (at least in the

case of non-buildman-fetched toolchains) if test.py used buildman to
build, as that will determine CROSS_COMPILE correctly from the default
.buildman file we create earlier on.  Thanks!


I'll look into whether that's possible.

BTW, does/can Travis save the test-log.html from the test.py 
invocations? That would make debugging any failures a little easier.

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Re: [U-Boot] efi: Use device device path type Messaging for network interface node

[Alexander Graf]

> When adding network interface node use Messaging device path with
> subtype MAC Address and device's MAC address as a value instead
> of Media Device path type with subtype File Path and path "Net"
> 
> Signed-off-by: Oleksandr Tymoshenko 
> Cc: Alexander Graf 

Thanks, applied to efi-next

Alex

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[U-Boot] [PATCH v2] powerpc/t2080: CPU erratum A-007907

[Darwin Dingel]

Core hang occurs when using L1 stashes. Workaround is to disable L1
stashes so software uses L2 cache for stashes instead.

Reviewed-by: Chris Packham 
Signed-off-by: Darwin Dingel 
Cc: York Sun 
---
Changes for v2:
- Enabled for T4240 and B4860

 arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +++-
 arch/powerpc/cpu/mpc85xx/cpu_init.c   | 7 +++
 arch/powerpc/include/asm/config_mpc85xx.h | 3 +++
 arch/powerpc/include/asm/processor.h  | 1 +
 4 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3b06ae4..197eb2f 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -329,7 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
puts("Work-around for Erratum A009663 enabled\n");
 #endif
-
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+   puts("Work-around for Erratum A007907 enabled\n");
+#endif
return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 53b3729..0e744f0 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -775,6 +775,13 @@ int cpu_init_r(void)
sync();
}
 #endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+   flush_dcache();
+   mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
+   sync();
+#endif
+ 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
/*
 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 6d845e8..c2bf44b 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -642,6 +642,7 @@
 #define CONFIG_SYS_NUM_FM2_10GEC   2
 #define CONFIG_NUM_DDR_CONTROLLERS 3
 #define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A007907
 #else
 #define CONFIG_SYS_NUM_FM1_DTSEC   6
 #define CONFIG_SYS_NUM_FM1_10GEC   1
@@ -748,6 +749,7 @@
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_SRIO_LIODN
+#define CONFIG_SYS_FSL_ERRATUM_A007907
 #else
 #define CONFIG_MAX_CPUS2
 #define CONFIG_MAX_DSP_CPUS2
@@ -910,6 +912,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007907
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
diff --git a/arch/powerpc/include/asm/processor.h 
b/arch/powerpc/include/asm/processor.h
index fdfca90..6f9b297 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -501,6 +501,7 @@
 #define   L1CSR1_ICE   0x0001  /* Instruction Cache Enable */
 #define SPRN_L1CSR20x25e   /* L1 Data Cache Control and Status Register 2 
*/
 #define   L1CSR2_DCWS  0x4000  /* Data Cache Write Shadow */
+#define   L1CSR2_DCSTASHID  0x03ff /* Data Cache Stash ID */
 #define SPRN_L2CSR00x3f9   /* L2 Data Cache Control and Status Register 0 
*/
 #define   L2CSR0_L2E   0x8000  /* L2 Cache Enable */
 #define   L2CSR0_L2PE  0x4000  /* L2 Cache Parity/ECC Enable */
-- 
2.10.1

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Re: [U-Boot] [PATCH] dm: mmc: socfpga: fix MMC_OPS support

[Simon Glass]

On 24 October 2016 at 10:24, Sylvain Lesne  wrote:
>
> Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with
> CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at
> runtime.
>
> This adds the missing fields in the driver declaration.
>
> Signed-off-by: Sylvain Lesne 
> ---
>
> Hi,
>
> I might be missing something, but with the latest master, on a
> socfpga board, I get the following failure:
>
> U-Boot SPL 2016.11-rc2-00072-g869588d-dirty (Oct 24 2016 - 17:18:22)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC1
> spl: partition error
> MMC: block number 0xx exceeds max(0xx)
> mmc_load_image_raw_sector: mmc block read error
> SPL: failed to boot from all boot devices
> ### ERROR ### Please RESET the board ###
>
> After some digging, it seems that the socfpga_dw_mmc driver slipped
> through the cracks during some steps of the DM conversion, so I
> added the missing fields of the driver declaration, mimicking what's
> done in the other dw_mmc_* drivers, and it works on my board.
>
> (Also, this is kind of unrelated, but it looks like the error
> message 'MMC: block number 0xx exceeds max(0xx)' has a formatting
> issue!)
>
> ---
>  drivers/mmc/socfpga_dw_mmc.c | 2 ++
>  1 file changed, 2 insertions(+)


Reviewed-by: Simon Glass 

The formatting issue may be due to tiny-printf.

- Simon
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Re: [U-Boot] [PATCH 3/5][v2] armv8: fsl-layerscape : Check SVR for initializing TZASC

[york sun]

On 10/24/2016 01:33 AM, Priyanka Jain wrote:
> LS2080 SoC and its personalities does not support TZASC
> But other new SoCs like LS2088A, LS1088A supports TASC
>
> Hence, skip initializing TZASC for Ls2080A based on SVR
>
> Signed-off-by: Priyanka Jain 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |   19 ++-
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h |6 ++
>  3 files changed, 28 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
> b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> index 3274cad..82b7696 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> @@ -10,6 +10,8 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>  #ifdef CONFIG_MP
>  #include 
>  #endif
> @@ -137,6 +139,15 @@ ENTRY(lowlevel_init)
>  #endif
>
>  #ifdef CONFIG_FSL_TZASC_400
> + bl  svr_dev_id  /* get high 16 bits of SVR */
> + /*
> +  * LS2080 and its personalities does not support TZASC
> +  * So skip TZASC related operations
> +  */
> + ldr x1, =SVR_DEV_LS2080A
> + cmp x0, x1

It will be better to consolidate the get_svr() function to implemente in 
assembly code.

> + b.eq1f
> +

Please clarify, before this patch the code runs through this section for 
LS2080A but actually it has no effect, correct?

York

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Re: [U-Boot] [PATCH] powerpc/t2080: CPU erratum A-007907

[Darwin Dingel]

Hi York,

We are not sure yet if we're exactly hitting this core hang issue but we might 
as well implement the workaround just in case.


Cheers,
Darwin


From: york sun 
Sent: Saturday, 22 October 2016 9:00 a.m.
To: Darwin Dingel; u-boot@lists.denx.de
Subject: Re: [PATCH] powerpc/t2080: CPU erratum A-007907

On 10/18/2016 09:28 PM, Darwin Dingel wrote:
> Core hang occurs when using L1 stashes. Workaround is to disable L1
> stashes so software uses L2 cache for stashes instead.
>

This patch is missing the signed-off-by signature from the author.

> Reviewed-by: Chris Packham 
> Cc: York Sun 
> ---
>  arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +++-
>  arch/powerpc/cpu/mpc85xx/cpu_init.c   | 7 +++
>  arch/powerpc/include/asm/config_mpc85xx.h | 1 +
>  arch/powerpc/include/asm/processor.h  | 1 +
>  4 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
> b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> index 3b06ae4..197eb2f 100644
> --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> @@ -329,7 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int 
> argc, char * const argv[])
>  #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
>   puts("Work-around for Erratum A009663 enabled\n");
>  #endif
> -
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
> + puts("Work-around for Erratum A007907 enabled\n");
> +#endif
>   return 0;
>  }
>
> diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
> b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> index 53b3729..0e744f0 100644
> --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
> +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> @@ -775,6 +775,13 @@ int cpu_init_r(void)
>   sync();
>   }
>  #endif
> +
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
> + flush_dcache();
> + mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));

Have you hit this erratum? Does this workaround seem to be effective?

> + sync();
> +#endif
> +
>  #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
>   /*
>* A-005812 workaround sets bit 32 of SPR 976 for SoCs running
> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
> b/arch/powerpc/include/asm/config_mpc85xx.h
> index 6d845e8..3d0ce2e 100644
> --- a/arch/powerpc/include/asm/config_mpc85xx.h
> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
> @@ -910,6 +910,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
>  #define CONFIG_SYS_FSL_ERRATUM_A006593
>  #define CONFIG_SYS_FSL_ERRATUM_A007186
>  #define CONFIG_SYS_FSL_ERRATUM_A006379
> +#define CONFIG_SYS_FSL_ERRATUM_A007907

Can you enable this erratum workaround to T4240 and B4860 as well?

York

>  #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
>  #define CONFIG_SYS_FSL_SFP_VER_3_0
>
> diff --git a/arch/powerpc/include/asm/processor.h 
> b/arch/powerpc/include/asm/processor.h
> index fdfca90..6f9b297 100644
> --- a/arch/powerpc/include/asm/processor.h
> +++ b/arch/powerpc/include/asm/processor.h
> @@ -501,6 +501,7 @@
>  #define   L1CSR1_ICE 0x0001  /* Instruction Cache Enable */
>  #define SPRN_L1CSR2  0x25e   /* L1 Data Cache Control and Status Register 2 
> */
>  #define   L1CSR2_DCWS0x4000  /* Data Cache Write 
> Shadow */
> +#define   L1CSR2_DCSTASHID  0x03ff   /* Data Cache Stash ID */
>  #define SPRN_L2CSR0  0x3f9   /* L2 Data Cache Control and Status Register 0 
> */
>  #define   L2CSR0_L2E 0x8000  /* L2 Cache Enable */
>  #define   L2CSR0_L2PE0x4000  /* L2 Cache Parity/ECC 
> Enable */
>

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Re: [U-Boot] [PATCH] dm: mmc: socfpga: fix MMC_OPS support

[Marek Vasut]

On 10/24/2016 06:24 PM, Sylvain Lesne wrote:
> Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with
> CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at
> runtime.
> 
> This adds the missing fields in the driver declaration.
> 
> Signed-off-by: Sylvain Lesne 
> ---

Nice catch, thanks.

Acked-by: Marek Vasut 

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH] powerpc/t2080: CPU erratum A-007907

[Darwin Dingel]

Core hang occurs when using L1 stashes. Workaround is to disable L1
stashes so software uses L2 cache for stashes instead.

Reviewed-by: Chris Packham 
Signed-off-by: Darwin Dingel 
Cc: York Sun 
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +++-
 arch/powerpc/cpu/mpc85xx/cpu_init.c   | 7 +++
 arch/powerpc/include/asm/config_mpc85xx.h | 3 +++
 arch/powerpc/include/asm/processor.h  | 1 +
 4 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3b06ae4..197eb2f 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -329,7 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
puts("Work-around for Erratum A009663 enabled\n");
 #endif
-
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+   puts("Work-around for Erratum A007907 enabled\n");
+#endif
return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 53b3729..0e744f0 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -775,6 +775,13 @@ int cpu_init_r(void)
sync();
}
 #endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+   flush_dcache();
+   mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
+   sync();
+#endif
+ 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
/*
 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 6d845e8..c2bf44b 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -642,6 +642,7 @@
 #define CONFIG_SYS_NUM_FM2_10GEC   2
 #define CONFIG_NUM_DDR_CONTROLLERS 3
 #define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A007907
 #else
 #define CONFIG_SYS_NUM_FM1_DTSEC   6
 #define CONFIG_SYS_NUM_FM1_10GEC   1
@@ -748,6 +749,7 @@
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_SRIO_LIODN
+#define CONFIG_SYS_FSL_ERRATUM_A007907
 #else
 #define CONFIG_MAX_CPUS2
 #define CONFIG_MAX_DSP_CPUS2
@@ -910,6 +912,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007907
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
diff --git a/arch/powerpc/include/asm/processor.h 
b/arch/powerpc/include/asm/processor.h
index fdfca90..6f9b297 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -501,6 +501,7 @@
 #define   L1CSR1_ICE   0x0001  /* Instruction Cache Enable */
 #define SPRN_L1CSR20x25e   /* L1 Data Cache Control and Status Register 2 
*/
 #define   L1CSR2_DCWS  0x4000  /* Data Cache Write Shadow */
+#define   L1CSR2_DCSTASHID  0x03ff /* Data Cache Stash ID */
 #define SPRN_L2CSR00x3f9   /* L2 Data Cache Control and Status Register 0 
*/
 #define   L2CSR0_L2E   0x8000  /* L2 Cache Enable */
 #define   L2CSR0_L2PE  0x4000  /* L2 Cache Parity/ECC Enable */
-- 
2.10.1

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[U-Boot] [PATCH] drivers/pci/Kconfig: Add PCI

[Tom Rini]

Add 'PCI' as a menu option and migrate all existing users.

Signed-off-by: Tom Rini 
---
Tegra is in a funny spot here.  TEGRA_COMMON will select DM_PCI and
DM_PCICOMPAT.  But adding PCI to the list here results in the following:
   aarch64: (for 61/61 boards) all +217.7 data +24.8 rodata +47.9 text +145.0
p2571  : all +4426 data +504 rodata +974 text +2948
e2220-1170 : all +4426 data +504 rodata +974 text +2948
p2371- : all +4426 data +504 rodata +974 text +2948
   arm: (for 557/557 boards) all +96.9 bss +0.1 data +7.2 rodata +23.7 
spl/u-boot-spl:all +0.1 spl/u-boot-spl:rodata +0.1 spl/u-boot-spl:text +0.0 
text +65.9
whistler   : all +3914 bss +28 data +288 rodata +934 
spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +2664
paz00  : all +3908 bss +16 data +280 rodata +952 text +2660
colibri_t30: all +3898 bss +12 data +280 rodata +934 
spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +2672
venice2: all +3862 bss +28 data +288 rodata +934 
spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +2612
plutux : all +3850 bss +32 data +280 rodata +934 
spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +2604
nyan-big   : all +3852 bss -4 data +296 rodata +952 text +2608
dalmore: all +3846 bss +12 data +288 rodata +934 
spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +2612
seaboard   : all +3848 bss +8 data +288 rodata +952 text +2600
medcom-wide: all +3848 bss +16 data +280 rodata +952 text +2600
harmony: all +3848 bss +8 data +288 rodata +952 text +2600
tec-ng : all +3842 bss +8 data +288 rodata +934 
spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +2612
ventana: all +3844 bss -48 data +280 rodata +952 text +2660
colibri_t20: all +3836 bss -4 data +288 rodata +952 text +2600
tec: all +3784 bss -48 data +280 rodata +952 text +2600

Because prior to this patch they did not set PCI and thus what code was
build here was largely discarded at link time.  One or two of the above
look to fall in to the case where PCI_TEGRA should be off, but not all.
What should we do about this?

 arch/arm/mach-tegra/Kconfig  |  1 +
 arch/sandbox/Kconfig |  7 ---
 configs/BSC9131RDB_NAND_SYSCLK100_defconfig  |  1 +
 configs/BSC9131RDB_NAND_defconfig|  1 +
 configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig  |  1 +
 configs/BSC9131RDB_SPIFLASH_defconfig|  1 +
 configs/M5475AFE_defconfig   |  1 +
 configs/M5475BFE_defconfig   |  1 +
 configs/M5475CFE_defconfig   |  1 +
 configs/M5475DFE_defconfig   |  1 +
 configs/M5475EFE_defconfig   |  1 +
 configs/M5475FFE_defconfig   |  1 +
 configs/M5475GFE_defconfig   |  1 +
 configs/M5485AFE_defconfig   |  1 +
 configs/M5485BFE_defconfig   |  1 +
 configs/M5485CFE_defconfig   |  1 +
 configs/M5485DFE_defconfig   |  1 +
 configs/M5485EFE_defconfig   |  1 +
 configs/M5485FFE_defconfig   |  1 +
 configs/M5485GFE_defconfig   |  1 +
 configs/M5485HFE_defconfig   |  1 +
 configs/MPC832XEMDS_ATM_defconfig|  1 +
 configs/MPC832XEMDS_HOST_33_defconfig|  2 +-
 configs/MPC832XEMDS_HOST_66_defconfig|  2 +-
 configs/MPC832XEMDS_SLAVE_defconfig  |  2 +-
 configs/MPC832XEMDS_defconfig|  1 +
 configs/MPC8349EMDS_defconfig|  1 +
 configs/MPC837XEMDS_HOST_defconfig   |  1 -
 configs/MPC837XEMDS_defconfig|  1 +
 configs/O2D300_defconfig |  1 +
 configs/O2DNT2_RAMBOOT_defconfig |  1 +
 configs/O2DNT2_defconfig |  1 +
 configs/O2D_defconfig|  1 +
 configs/O2I_defconfig|  1 +
 configs/O2MNT_O2M110_defconfig   |  1 +
 configs/O2MNT_O2M112_defconfig   |  1 +
 configs/O2MNT_O2M113_defconfig   |  1 +
 configs/O2MNT_defconfig  |  1 +
 configs/O3DNT_defconfig  |  1 +
 configs/PATI_defconfig   |  1 +
 configs/TQM823L_LCD_defconfig|  1 +
 configs/TQM823L_defconfig|  1 +
 configs/TQM823M_defconfig|  1 +
 

Re: [U-Boot] [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release secondary cores

[york sun]

On 10/24/2016 08:49 AM, york@nxp.com wrote:
> On 10/24/2016 01:33 AM, Priyanka Jain wrote:
>> NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
>> But other new SoCs like LS2088A, LS1088A release secondary
>> cores one by one to avoid power spike.
>>
>> Update code to release secondary cores based on SoC SVR
>> Add code to release cores one by one for non LS2080A SoCs
>>
>> Signed-off-by: Priyanka Jain 
>> Signed-off-by: Raghav Dogra 
>> Signed-off-by: Prabhakar Kushwaha 
>> ---
>>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c |2 +-
>>  arch/arm/cpu/armv8/fsl-layerscape/cpu.h |1 +
>>  arch/arm/cpu/armv8/fsl-layerscape/mp.c  |   59
>> --
>>  3 files changed, 57 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> index ce04e48..15d157c 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> @@ -190,7 +190,7 @@ void enable_caches(void)
>>  }
>>  #endif
>>
>> -static inline u32 initiator_type(u32 cluster, int init_id)
>> +inline u32 initiator_type(u32 cluster, int init_id)
>>  {
>>  struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
>>  u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> index 8072f3c..a05f8aa 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> @@ -5,4 +5,5 @@
>>   */
>>
>>  int fsl_qoriq_core_to_cluster(unsigned int core);
>> +u32 initiator_type(u32 cluster, int init_id);
>>  u32 cpu_mask(void);
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> index f607c39..5cf080f 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> @@ -9,6 +9,8 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include "cpu.h"
>> +#include 
>>
>>  DECLARE_GLOBAL_DATA_PTR;
>>
>> @@ -22,11 +24,30 @@ phys_addr_t determine_mp_bootpg(void)
>>  return (phys_addr_t)_boot_code;
>>  }
>>
>> +#ifdef CONFIG_FSL_LSCH3
>> +void wake_secondary_core_n(int cluster, int core, int cluster_cores)
>> +{
>> +struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
>> +struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
>> +u32 mpidr = 0;
>> +
>> +mpidr = ((cluster << 8) | core);
>> +gur_out32(>scratchrw[6], mpidr);
>
> What's the definition of each bit for scratchrw[6]? Before this patch,
> secondary cores only check if it is zero.
>
>> +asm volatile("dsb st" : : : "memory");
>> +rst->brrl |= 1 << ((cluster * cluster_cores) + core);
>> +asm volatile("dsb st" : : : "memory");
>> +while (gur_in32(>scratchrw[6]) != 0)
>> +;
>
> Does each secondary core clear this register after it starts to run?
>

Priyanka,

I got hold of the architect for the bootrom. I understand the story 
behind the release one-by-one now. It would be better if you can add 
some comments for scratchrw[6] for its expected behaviour.

York

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Re: [U-Boot] [PATCH 0/5][v2] Update LS2080A SoC code to support LS2088A SoC

[york sun]

On 10/24/2016 01:32 AM, Priyanka Jain wrote:
> From: Priyanka Jain 
>
> LS2088A is similar to LS2080A SoC with some differences like
> 1)Timer controller offset is different
> 2)It has A72 cores
> 3)Process to release secondary cores is different
> 4)LS2088A SoC has TZASC controller
>
> In preparation of using same binary for LS2088A and LS2080A as both
> are using same development boards. code is update to detect difference
> based on SVR at runtime
>
>
> Priyanka Jain (5):
>   armv8: lsch3: Use SVR based timer base address detection
>   armv8: fsl-layerscape: Update TZASC registers type
>   armv8: fsl-layerscape : Check SVR for initializing TZASC
>   armv8: fsl-layerscape: Add NXP LS2088A SoC support
>   armv8/fsl-lsch3: Update code to release secondary cores

Priyanka,

Does PCIe work for you? It doesn't work for my test. The same binary 
works for LS2080ARDB/LS2085ARDB. Do you have other patches? I noticed 
several internal commits related to LS2088A PCIe. Do we need them?

York
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[U-Boot] [PATCH] efi: Use device device path type Messaging for network interface node

[Oleksandr Tymoshenko]

When adding network interface node use Messaging device path with
subtype MAC Address and device's MAC address as a value instead
of Media Device path type with subtype File Path and path "Net"

Signed-off-by: Oleksandr Tymoshenko 
Cc: Alexander Graf 
---
 include/efi_api.h| 13 +
 lib/efi_loader/efi_net.c | 17 +
 2 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/include/efi_api.h b/include/efi_api.h
index bdb600e..5c3836a 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -268,6 +268,19 @@ struct efi_device_path {
u16 length;
 };
 
+struct efi_mac_addr {
+   u8 addr[32];
+};
+
+#define DEVICE_PATH_TYPE_MESSAGING_DEVICE  0x03
+#  define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR0x0b
+
+struct efi_device_path_mac_addr {
+   struct efi_device_path dp;
+   struct efi_mac_addr mac;
+   u8 if_type;
+};
+
 #define DEVICE_PATH_TYPE_MEDIA_DEVICE  0x04
 #  define DEVICE_PATH_SUB_TYPE_FILE_PATH   0x04
 
diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
index 3796496..604ac6e 100644
--- a/lib/efi_loader/efi_net.c
+++ b/lib/efi_loader/efi_net.c
@@ -27,7 +27,8 @@ struct efi_net_obj {
struct efi_simple_network net;
struct efi_simple_network_mode net_mode;
/* Device path to the network adapter */
-   struct efi_device_path_file_path dp[2];
+   struct efi_device_path_mac_addr dp_mac;
+   struct efi_device_path_file_path dp_end;
/* PXE struct to transmit dhcp data */
struct efi_pxe pxe;
struct efi_pxe_mode pxe_mode;
@@ -205,7 +206,7 @@ static efi_status_t EFIAPI efi_net_open_dp(void *handle, 
efi_guid_t *protocol,
struct efi_simple_network *net = handle;
struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
 
-   *protocol_interface = netobj->dp;
+   *protocol_interface = >dp_mac;
 
return EFI_SUCCESS;
 }
@@ -236,11 +237,10 @@ void efi_net_set_dhcp_ack(void *pkt, int len)
 int efi_net_register(void **handle)
 {
struct efi_net_obj *netobj;
-   struct efi_device_path_file_path dp_net = {
-   .dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
-   .dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+   struct efi_device_path_mac_addr dp_net = {
+   .dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE,
+   .dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR,
.dp.length = sizeof(dp_net),
-   .str = { 'N', 'e', 't' },
};
struct efi_device_path_file_path dp_end = {
.dp.type = DEVICE_PATH_TYPE_END,
@@ -279,8 +279,9 @@ int efi_net_register(void **handle)
netobj->net.receive = efi_net_receive;
netobj->net.mode = >net_mode;
netobj->net_mode.state = EFI_NETWORK_STARTED;
-   netobj->dp[0] = dp_net;
-   netobj->dp[1] = dp_end;
+   netobj->dp_mac = dp_net;
+   netobj->dp_end = dp_end;
+   memcpy(netobj->dp_mac.mac.addr, eth_get_ethaddr(), 6);
memcpy(netobj->net_mode.current_address.mac_addr, eth_get_ethaddr(), 6);
netobj->net_mode.max_packet_size = PKTSIZE;
 
-- 
2.7.4

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Re: [U-Boot] [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release secondary cores

[york sun]

On 10/24/2016 01:33 AM, Priyanka Jain wrote:
> NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
> But other new SoCs like LS2088A, LS1088A release secondary
> cores one by one to avoid power spike.
>
> Update code to release secondary cores based on SoC SVR
> Add code to release cores one by one for non LS2080A SoCs
>

Have you observed the power spike when releasing them together? They 
only run very short before entering "wfe". Why wasn't it a problem for 
any other multi-core SoCs?

York
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Re: [U-Boot] [PATCH 4/5][v2] armv8: fsl-layerscape: Add NXP LS2088A SoC support

[york sun]

On 10/24/2016 01:33 AM, Priyanka Jain wrote:
>
> diff --git a/board/freescale/ls2080a/MAINTAINERS 
> b/board/freescale/ls2080a/MAINTAINERS
> index c8dac99..de137ef 100644
> --- a/board/freescale/ls2080a/MAINTAINERS
> +++ b/board/freescale/ls2080a/MAINTAINERS
> @@ -1,5 +1,5 @@
>  LS2080A BOARD
> -M:   York Sun 
> +M:   York Sun , Priyanka Jain 

You can drop my name for this board if you can maintain it. I don't use 
the emulator as much as you do now.

York
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Re: [U-Boot] MMC boot / mvebu / clearfog

[Christoph Egger]

Hi!

Christoph Egger  writes:
> Indeeed, the following patch fixes MMC booting for me (and most
> certainly breaks SD card booting)

It actually seems to be somewhat more difficult. It worked because I had
a old u-boot image at mmcblk0 at offset 1 block and a new u-boot at
mmcblk0boot0. (old ~ before removing the +1). I guess u-boot gets loaded
from the mmc0boot0 device (which is also where the SPL is from) and as
soon as the post-SPL u-boot tries to access it's own bytes it falls over
to mmcblk0.

I have a working setup by

  dd if=u-boot-spl.kwb of=/dev/mmcblk0boot0 bs=512
  dd if=u-boot-spl.kwb of=/dev/mmcblk0  bs=512 seek=1 skip=1

(skipping the first sector to keep the MBR alive and assuming it only
contains SPL code anyway)

  Christoph

-- 
9FED 5C6C E206 B70A 5857  70CA 9655 22B9 D49A E731
Debian Developer | Lisp Hacker | CaCert Assurer


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[U-Boot] [PATCH] dm: mmc: socfpga: fix MMC_OPS support

[Sylvain Lesne]

Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with
CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at
runtime.

This adds the missing fields in the driver declaration.

Signed-off-by: Sylvain Lesne 
---

Hi,

I might be missing something, but with the latest master, on a
socfpga board, I get the following failure:

U-Boot SPL 2016.11-rc2-00072-g869588d-dirty (Oct 24 2016 - 17:18:22)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from MMC1
spl: partition error
MMC: block number 0xx exceeds max(0xx)
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

After some digging, it seems that the socfpga_dw_mmc driver slipped 
through the cracks during some steps of the DM conversion, so I 
added the missing fields of the driver declaration, mimicking what's 
done in the other dw_mmc_* drivers, and it works on my board.

(Also, this is kind of unrelated, but it looks like the error 
message 'MMC: block number 0xx exceeds max(0xx)' has a formatting 
issue!)

---
 drivers/mmc/socfpga_dw_mmc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 5a3a4ff..0a22e58 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -151,7 +151,9 @@ U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
.id = UCLASS_MMC,
.of_match   = socfpga_dwmmc_ids,
.ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
+   .ops= _dwmci_ops,
.bind   = socfpga_dwmmc_bind,
.probe  = socfpga_dwmmc_probe,
.priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
+   .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
 };
-- 
1.9.1

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Re: [U-Boot] [PATCH] armv8/ls1043a: Add the OCRAM initialization

[york sun]

On 10/23/2016 06:59 AM, Prabhakar Kushwaha wrote:
> Hi York,
>
>
>> -Original Message-
>> From: york sun
>> Sent: Saturday, October 22, 2016 1:39 AM
>> To: Prabhakar Kushwaha ; Pratiyush Srivastava
>> ; u-boot@lists.denx.de; Mingkai Hu
>> 
>> Cc: Hou Zhiqiang 
>> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization
>>
>> On 10/16/2016 10:35 PM, Prabhakar Kushwaha wrote:
>>> Hi Mingkai,
>>>
 -Original Message-
 From: Pratiyush Srivastava [mailto:pratiyush.srivast...@nxp.com]
 Sent: Wednesday, October 12, 2016 5:46 PM
 To: u-boot@lists.denx.de
 Cc: york sun ; Prabhakar Kushwaha
 ; Pratiyush Srivastava
 ; Hou Zhiqiang
>> 
 Subject: [PATCH] armv8/ls1043a: Add the OCRAM initialization

 Clear the content to zero and the ECC error bit of OCRAM1/2.

 The OCRAM must be initialized to ZERO by the unit of 8-Byte before
 accessing it, or else it will generate ECC error. And the IBR has
 accessed the OCRAM before this initialization, so the ECC error
 status bit should to be cleared.

 Signed-off-by: Pratiyush Srivastava 
 Signed-off-by: Hou Zhiqiang 
 Signed-off-by: Prabhakar Kushwaha 
 ---
>>>
>>> This requirement is for both ls1043 and ls1088a.  was this patch taken care
>> during ls1043a upstreaming
>>> If not, how it is being taken care for ls1043a.  Same approach can be used 
>>> for
>> ls1088a
>>>
>>
>> I wonder why we don't see ECC errors before this patch. We have LS1043A
>> boots on NAND, SD.
>>
>
> OCRAM has a requirement of initializing before first time "read".
> If user reads OCRAM before **initializing**; ECC error will come.  (u-boot is 
> not handling this error for now).
>
> I can only guess the reason of not seeing this error as OCRAM never read 
> before any write.
> Even in case of Stack, data is first written and then read.
>

Is there a case you want to read from OCRAM before writing anything to 
it? Why don't we need to do so for SPL or LSCH3?

York


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Re: [U-Boot] [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to config.h

[york sun]

On 10/23/2016 07:04 AM, Prabhakar Kushwaha wrote:
> Hi York,
>
>> -Original Message-
>> From: york sun
>> Sent: Friday, October 21, 2016 7:55 PM
>> To: Prabhakar Kushwaha ; u-
>> b...@lists.denx.de
>> Cc: o...@buserror.net
>> Subject: Re: [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to
>> config.h
>>
>> On 10/20/2016 11:37 PM, Prabhakar Kushwaha wrote:
>>> Migration of IFC_BANK_COUNT from Kconfig to config.h avoids adding
>>> SoC name in Kconfig as Dependencies. It will help in having
>>> all SoC related defines in config.h - easy to maintain.
>>>
>>
>> Prabhakar,
>>
>> Why do you want to go back to config.h? I think we are going with
>> Kconfig. Having everything in one config file conflicts with Kconfig.
>> The former has centralized config per SoC, the latter has centralized
>> config per feature.
>>
>
> There are 2 reason for this
>
> 1) in File arch/arm/cpu/armv8/fsl-layerscape/Kconfig, "depends" row will keep 
> on increasing with SoC.
> And if I add new field CONFIG_SYS_FSL_IFC_CLK_DIV, similar entry will be done 
> and it will also keep on increasing with SoC.
> I want to avoid it.
>
> config SYS_FSL_IFC_BANK_COUNT
>   int "Maximum banks of Integrated flash controller"
>   depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A

The "depends" line can be rewritten with HAS_* feature macro.

>   default 4 if ARCH_LS1043A
>   default 4 if ARCH_LS1046A
>   default 8 if ARCH_LS2080A

You can simplify the "default 4" for all and only use different number 
for others.

>
> 2) There is no file similar to  " arch/arm/cpu/armv8/fsl-layerscape/Kconfig" 
> for powerpc platform. So how to add new " CONFIG SYS_FSL_IFC_CLK_DIV" with 
> different values per SoC.
>This problem will come for defining other clocks for " armv8/fsl-lsch3: 
> consolidate the clock system initialization"
>

We will convert powerpc as well.

York

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[U-Boot] Please pull from u-boot-i2c

[Heiko Schocher]

Hello Tom,

please pull from u-boot-i2c.git master

The following changes since commit 5ac5861c4ba851b473e6a24940b412b397627d8d:

  travis-ci: Add test.py for various qemu platforms (2016-10-24 08:06:29 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-i2c.git master

for you to fetch changes up to b03380805b5a184b7017dc428a53c8e1e9c9f99c:

  i2c: designware: Avoid overwriting the cmd_data register (2016-10-24 18:15:47 
+0200)


Marek Vasut (1):
  i2c: designware: Avoid overwriting the cmd_data register

 drivers/i2c/designware_i2c.c | 23 +--
 1 file changed, 17 insertions(+), 6 deletions(-)

bye,
Heiko
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Re: [U-Boot] [PATCH v2 4/4] configs: am57xx: Enable fastboot

[Tom Rini]

On Mon, Oct 24, 2016 at 06:41:13PM +0300, Sam Protsenko wrote:

> Signed-off-by: Sam Protsenko 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH v2 3/4] configs: am57xx: Enable download gadget

[Tom Rini]

On Mon, Oct 24, 2016 at 06:41:12PM +0300, Sam Protsenko wrote:

> Enable USB download gadget (needed for fastboot support) and all
> dependencies.
> 
> Signed-off-by: Sam Protsenko 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH v2 1/4] fastboot: Add CONFIG_FASTBOOT_USB_DEV option

[Tom Rini]

On Mon, Oct 24, 2016 at 06:41:10PM +0300, Sam Protsenko wrote:

> Some boards (like AM57x EVM) has USB OTG controller other than 0. So in
> order to use correct controller number in compiled environment we should
> define CONFIG_FASTBOOT_USB_DEV option.
> 
> For example, when doing "fastboot reboot-bootloader" we want to enter
> fastboot mode automatically. But to do so we need to provide controller
> number to "fastboot" command. If this procedure is defined in some config
> which is common to bunch of boards, and boards have different USB
> controller numbers, we can't just hardcode "fastboot 0" in the
> environment. We need to use configurable option, which this patch adds.
> 
> Signed-off-by: Sam Protsenko 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH v2 2/4] ti_omap5_common: Respect USB controller number in fastboot

[Tom Rini]

On Mon, Oct 24, 2016 at 06:41:11PM +0300, Sam Protsenko wrote:

> On "fastboot reboot-bootloader" we check "dofastboot" variable and do
> "fastboot 0" command in U-Boot if it's 1. But there are boards which have
> USB controller number other than 0, so it should be respected when
> performing "fastboot" command.
> 
> This patch reuses CONFIG_FASTBOOT_USB_DEV option toprovide correct USB
> controller number to "fastboot" command.
> 
> Signed-off-by: Sam Protsenko 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release secondary cores

[york sun]

On 10/24/2016 01:33 AM, Priyanka Jain wrote:
> NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
> But other new SoCs like LS2088A, LS1088A release secondary
> cores one by one to avoid power spike.
>
> Update code to release secondary cores based on SoC SVR
> Add code to release cores one by one for non LS2080A SoCs
>
> Signed-off-by: Priyanka Jain 
> Signed-off-by: Raghav Dogra 
> Signed-off-by: Prabhakar Kushwaha 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c |2 +-
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.h |1 +
>  arch/arm/cpu/armv8/fsl-layerscape/mp.c  |   59 --
>  3 files changed, 57 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index ce04e48..15d157c 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -190,7 +190,7 @@ void enable_caches(void)
>  }
>  #endif
>
> -static inline u32 initiator_type(u32 cluster, int init_id)
> +inline u32 initiator_type(u32 cluster, int init_id)
>  {
>   struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
>   u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h 
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> index 8072f3c..a05f8aa 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> @@ -5,4 +5,5 @@
>   */
>
>  int fsl_qoriq_core_to_cluster(unsigned int core);
> +u32 initiator_type(u32 cluster, int init_id);
>  u32 cpu_mask(void);
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> index f607c39..5cf080f 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> @@ -9,6 +9,8 @@
>  #include 
>  #include 
>  #include 
> +#include "cpu.h"
> +#include 
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -22,11 +24,30 @@ phys_addr_t determine_mp_bootpg(void)
>   return (phys_addr_t)_boot_code;
>  }
>
> +#ifdef CONFIG_FSL_LSCH3
> +void wake_secondary_core_n(int cluster, int core, int cluster_cores)
> +{
> + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> + struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
> + u32 mpidr = 0;
> +
> + mpidr = ((cluster << 8) | core);
> + gur_out32(>scratchrw[6], mpidr);

What's the definition of each bit for scratchrw[6]? Before this patch, 
secondary cores only check if it is zero.

> + asm volatile("dsb st" : : : "memory");
> + rst->brrl |= 1 << ((cluster * cluster_cores) + core);
> + asm volatile("dsb st" : : : "memory");
> + while (gur_in32(>scratchrw[6]) != 0)
> + ;

Does each secondary core clear this register after it starts to run?

York
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Re: [U-Boot] [PATCH 1/2] mx6sabresd: Add Falcon mode support

[Fabio Estevam]

On Mon, Oct 24, 2016 at 2:00 PM, Stefano Babic  wrote:

> It was already applied, but I have just pushed to the server today.

Excellent, I can see the patches there now. Thanks!
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Re: [U-Boot] [PATCH 1/2] mx6sabresd: Add Falcon mode support

[Stefano Babic]

On 24/10/2016 17:26, Fabio Estevam wrote:
> Hi Stefano,
> 
> On Tue, Oct 11, 2016 at 12:05 PM, Fabio Estevam  wrote:
>> On Tue, Oct 11, 2016 at 11:09 AM, Diego Dorta  wrote:
>>> Allow i.MX6Q Sabre SD to load the kernel and dtb via SPL in Falcon mode.
>>>
>>> Based on the Falcon mode code for MX6 Gateworks Ventana board.
>>>
>>> Signed-off-by: Diego Dorta 
>>
>> Reviewed-by: Fabio Estevam 
> 
> Does this series look good for you? Could it be applied?

It was already applied, but I have just pushed to the server today.

Regards,
Stefano

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Re: [U-Boot] [PATCH 2/4] ti_omap5_common: Respect USB controller number in fastboot

[Sam Protsenko]

On Fri, Oct 21, 2016 at 2:19 PM, Tom Rini  wrote:
> On Thu, Oct 20, 2016 at 06:58:29PM +0300, Sam Protsenko wrote:
>
>> On "fastboot reboot-bootloader" we check "dofastboot" variable and do
>> "fastboot 0" command in U-Boot if it's 1. But there are boards which have
>> USB controller number other than 0, so it should be respected when
>> performing "fastboot" command.
>>
>> This patch reuses CONFIG_FASTBOOT_USB_DEV option toprovide correct USB
>> controller number to "fastboot" command.
>>
>> Signed-off-by: Sam Protsenko 
>> ---
>>  include/configs/ti_omap5_common.h | 6 +-
>>  1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/configs/ti_omap5_common.h 
>> b/include/configs/ti_omap5_common.h
>> index 29b7d96..144a880 100644
>> --- a/include/configs/ti_omap5_common.h
>> +++ b/include/configs/ti_omap5_common.h
>> @@ -110,11 +110,15 @@
>>   DFUARGS \
>>   NETARGS \
>>
>> +#ifndef CONFIG_FASTBOOT_USB_DEV
>> +#define CONFIG_FASTBOOT_USB_DEV 0
>> +#endif
>
> We don't need this hunk, it will always be defined now.
>

Tom,

I fixed that and resent the whole patchset. Please reexamine v2.

Thanks.

> --
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[U-Boot] [PATCH v2 3/4] configs: am57xx: Enable download gadget

[Sam Protsenko]

Enable USB download gadget (needed for fastboot support) and all
dependencies.

Signed-off-by: Sam Protsenko 
---
Changes in v2: None

 configs/am57xx_evm_defconfig  | 9 +
 configs/am57xx_evm_nodt_defconfig | 9 +
 configs/am57xx_hs_evm_defconfig   | 9 +
 3 files changed, 27 insertions(+)

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 5acd4e7..89e927e 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -59,5 +59,14 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am57xx_evm_nodt_defconfig 
b/configs/am57xx_evm_nodt_defconfig
index 9588a55..73e541d 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -36,5 +36,14 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index a80e882..b25e21b 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -54,5 +54,14 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_SPL_OF_LIBFDT=y
-- 
2.9.3

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[U-Boot] [PATCH v2 2/4] ti_omap5_common: Respect USB controller number in fastboot

[Sam Protsenko]

On "fastboot reboot-bootloader" we check "dofastboot" variable and do
"fastboot 0" command in U-Boot if it's 1. But there are boards which have
USB controller number other than 0, so it should be respected when
performing "fastboot" command.

This patch reuses CONFIG_FASTBOOT_USB_DEV option toprovide correct USB
controller number to "fastboot" command.

Signed-off-by: Sam Protsenko 
---
Changes in v2:
  - Remove unnecessary check for CONFIG_FASTBOOT_USB_DEV

 include/configs/ti_omap5_common.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/configs/ti_omap5_common.h 
b/include/configs/ti_omap5_common.h
index 29b7d96..b85fae3 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -114,7 +114,8 @@
"if test ${dofastboot} -eq 1; then " \
"echo Boot fastboot requested, resetting dofastboot ...;" \
"setenv dofastboot 0; saveenv;" \
-   "echo Booting into fastboot ...; fastboot 0;" \
+   "echo Booting into fastboot ...; " \
+   "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " \
"fi;" \
"run findfdt; " \
"run envboot; " \
-- 
2.9.3

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[U-Boot] [PATCH v2 0/4] am57xx: Add fastboot support

[Sam Protsenko]

This patch series adds fastboot support for AM57x EVM boards.

As AM57x EVM USB controller index is 1 (as opposed to regular 0), some
changes had to be done to deal with this.

Changes in v2:
  - PATCH 2/4: Remove unnecessary check for CONFIG_FASTBOOT_USB_DEV in
ti_omap5_common.h

Sam Protsenko (4):
  fastboot: Add CONFIG_FASTBOOT_USB_DEV option
  ti_omap5_common: Respect USB controller number in fastboot
  configs: am57xx: Enable download gadget
  configs: am57xx: Enable fastboot

 cmd/fastboot/Kconfig  |  8 
 configs/am57xx_evm_defconfig  | 18 ++
 configs/am57xx_evm_nodt_defconfig | 18 ++
 configs/am57xx_hs_evm_defconfig   | 18 ++
 include/configs/ti_omap5_common.h |  3 ++-
 5 files changed, 64 insertions(+), 1 deletion(-)

-- 
2.9.3

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[U-Boot] [PATCH v2 4/4] configs: am57xx: Enable fastboot

[Sam Protsenko]

Signed-off-by: Sam Protsenko 
---
Changes in v2: None

 configs/am57xx_evm_defconfig  | 9 +
 configs/am57xx_evm_nodt_defconfig | 9 +
 configs/am57xx_hs_evm_defconfig   | 9 +
 3 files changed, 27 insertions(+)

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 89e927e..888a2fd 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -16,6 +16,15 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_DMA_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_BUF_ADDR=0x8200
+CONFIG_FASTBOOT_BUF_SIZE=0x2f00
+CONFIG_FASTBOOT_USB_DEV=1
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/am57xx_evm_nodt_defconfig 
b/configs/am57xx_evm_nodt_defconfig
index 73e541d..9da40bb 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -9,6 +9,15 @@ CONFIG_SPL=y
 CONFIG_SPL_DMA_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_BUF_ADDR=0x8200
+CONFIG_FASTBOOT_BUF_SIZE=0x2f00
+CONFIG_FASTBOOT_USB_DEV=1
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index b25e21b..e27b214 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -17,6 +17,15 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_DMA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_BUF_ADDR=0x8200
+CONFIG_FASTBOOT_BUF_SIZE=0x2f00
+CONFIG_FASTBOOT_USB_DEV=1
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
-- 
2.9.3

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[U-Boot] [PATCH v2 1/4] fastboot: Add CONFIG_FASTBOOT_USB_DEV option

[Sam Protsenko]

Some boards (like AM57x EVM) has USB OTG controller other than 0. So in
order to use correct controller number in compiled environment we should
define CONFIG_FASTBOOT_USB_DEV option.

For example, when doing "fastboot reboot-bootloader" we want to enter
fastboot mode automatically. But to do so we need to provide controller
number to "fastboot" command. If this procedure is defined in some config
which is common to bunch of boards, and boards have different USB
controller numbers, we can't just hardcode "fastboot 0" in the
environment. We need to use configurable option, which this patch adds.

Signed-off-by: Sam Protsenko 
---
Changes in v2: None

 cmd/fastboot/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/cmd/fastboot/Kconfig b/cmd/fastboot/Kconfig
index 5d2facc..d555d0a 100644
--- a/cmd/fastboot/Kconfig
+++ b/cmd/fastboot/Kconfig
@@ -41,6 +41,14 @@ config FASTBOOT_BUF_SIZE
  downloads. This buffer should be as large as possible for a
  platform. Define this to the size available RAM for fastboot.
 
+config FASTBOOT_USB_DEV
+   int "USB controller number"
+   default 0
+   help
+ Some boards have USB OTG controller other than 0. Define this
+ option so it can be used in compiled environment (e.g. in
+ CONFIG_BOOTCOMMAND).
+
 config FASTBOOT_FLASH
bool "Enable FASTBOOT FLASH command"
help
-- 
2.9.3

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Re: [U-Boot] [PATCH 1/5] armv8: lsch3: Use SVR based timer base address detection

[york sun]

On 10/23/2016 11:29 PM, Priyanka Jain wrote:
>
>
>> -Original Message-
>> From: york sun
>> Sent: Thursday, October 20, 2016 10:46 AM
>> To: Prabhakar Kushwaha ; u-
>> b...@lists.denx.de
>> Cc: Priyanka Jain 
>> Subject: Re: [PATCH 1/5] armv8: lsch3: Use SVR based timer base address
>> detection
>>
>> On 10/19/2016 10:28 PM, Prabhakar Kushwaha wrote:
>>> Hi York
>>>
 -Original Message-
 From: Priyanka Jain [mailto:priyanka.j...@nxp.com]
 Sent: Wednesday, October 19, 2016 3:07 PM
 To: u-boot@lists.denx.de
 Cc: Priyanka Jain ; Prabhakar Kushwaha
 
 Subject: [PATCH 1/5] armv8: lsch3: Use SVR based timer base address
 detection

 Timer base address has been changed from LS2080A SoC to new SoCs like
 LS2088A, LS1088A.

 Use SVR based timer base address detection to avoid compile time #ifdef.

 Signed-off-by: Priyanka Jain 
 Signed-off-by: Prabhakar Kushwaha 
 ---
  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|   14 +-
  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |3 ++-
  2 files changed, 15 insertions(+), 2 deletions(-)

 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
 b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
 index b7a2e0c..ce04e48 100644
 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
 +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
 @@ -424,8 +424,10 @@ int arch_early_init_r(void)

  int timer_init(void)
  {
 -  u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 +  u32 __iomem *cntcr;
  #ifdef CONFIG_FSL_LSCH3
 +  struct ccsr_gur __iomem *gur = (void
 *)(CONFIG_SYS_FSL_GUTS_ADDR);
 +  u32 svr, ver;
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
>> #endif
 #ifdef CONFIG_LS2080A @@ -439,6 +441,16 @@ int timer_init(void)
 #endif

  #ifdef CONFIG_FSL_LSCH3
 +  svr = gur_in32(>svr);
 +  ver = SVR_SOC_VER(svr);
 +  if ((ver == SVR_LS2080A) || (ver == SVR_LS2040A) ||
 +  (ver == SVR_LS2085A) || (ver == SVR_LS2045A))
 +  cntcr = (u32 *)LS2080A_LS2085A_TIMER_ADDR;
 +  else
 +#endif
 +  cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 +
 +#ifdef CONFIG_FSL_LSCH3
/* Enable timebase for all clusters.
 * It is safe to do so even some clusters are not enabled.
 */
 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
 b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
 index 7acba27..e6cdfcb 100644
 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
 +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
 @@ -23,7 +23,8 @@
  #define CONFIG_SYS_IFC_ADDR   (CONFIG_SYS_IMMR
>> +
 0x0124)
  #define CONFIG_SYS_NS16550_COM1
>>  (CONFIG_SYS_IMMR +
 0x011C0500)
  #define CONFIG_SYS_NS16550_COM2
>>  (CONFIG_SYS_IMMR +
 0x011C0600)
 -#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d
 +#define LS2080A_LS2085A_TIMER_ADDR0x023d
>>>
>>> Is this ok to define new constant without CONFIG_?
>>> Only problem, it is not consistent with existing defines.
>>>
>>
>> Prabhakar,
>>
>> I opinion on this is
>>
>> 1) Let's check if a Kconfig option is better for it If yes, let's convert it 
>> to
>> Kconfig. If not, go to 2)
>>
>> 2) Let's use a different name space for the macros.
>> I suggest to use SYS_FSL_* for fixed value for our hardware.
>>
>> York
>
> LS2080A_LS2085A_TIMER_ADDR is defining the timer controller (register) offset.
> Kconfig option does not look to be very helpful here.
> I am thinking of renaming this to "SYS_FSL_LS2080A_LS2085A_TIMER_ADDR"
>
> Please confirm if this is fine.
>

Sorry for late reply. The new name is OK. Please consider to change 
other existing CONFIG_* macros to SYS_FSL_* space, and remove them from 
the white list.

York
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Re: [U-Boot] [PATCH 1/2] mx6sabresd: Add Falcon mode support

[Fabio Estevam]

Hi Stefano,

On Tue, Oct 11, 2016 at 12:05 PM, Fabio Estevam  wrote:
> On Tue, Oct 11, 2016 at 11:09 AM, Diego Dorta  wrote:
>> Allow i.MX6Q Sabre SD to load the kernel and dtb via SPL in Falcon mode.
>>
>> Based on the Falcon mode code for MX6 Gateworks Ventana board.
>>
>> Signed-off-by: Diego Dorta 
>
> Reviewed-by: Fabio Estevam 

Does this series look good for you? Could it be applied?

Thanks
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Re: [U-Boot] Please pull u-boot-fdt

[Tom Rini]

On Sun, Oct 23, 2016 at 09:01:17PM -0600, Simon Glass wrote:

> Hi Tom,
> 
> Here's another patch syncing up with libfdt upstream. Maxime suggest
> that this should go in now.
> 
> 
> The following changes since commit 3431b392ad50ff37fa3d6e7715c6a99c74d692dc:
> 
>   Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
> (2016-10-19 07:48:16 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-fdt.git
> 
> for you to fetch changes up to 610db7058f1d9ed668aef7692f8f90f05e0923f8:
> 
>   libfdt: Sync overlay with upstream (2016-10-23 12:08:48 -0700)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] api: storage: Avoid enumeration for non-configured subsystem

[Tom Rini]

On Wed, Oct 19, 2016 at 05:19:47PM +0200, Emmanuel Vadot wrote:

> If a subsystem wasn't configured, avoid enumeration.
> 
> Signed-off-by: Emmanuel Vadot 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2] tools: moveconfig: support wildcards in --defconfigs file

[Tom Rini]

On Wed, Oct 19, 2016 at 02:39:54PM +0900, Masahiro Yamada wrote:

> Supporting shell-style wildcards for the --defconfigs option will be
> useful to run the moveconfig tool against a specific platform.  For
> example, "uniphier*" in the file passed by --defconfigs option will
> be expanded to defconfig files that start with "uniphier".  This is
> easier than listing out all defconfig files you are interested in.
> 
> Signed-off-by: Masahiro Yamada 
> Reviewed-by: Joe Hershberger 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Fix codying style broken by recent libfdt sync

[Tom Rini]

On Mon, Oct 17, 2016 at 08:43:01PM +0900, Masahiro Yamada wrote:

> Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist
> functions") broke codying style in some places especially
> by inserting an extra whitespace before fdt_stringlist_count().
> 
> Signed-off-by: Masahiro Yamada 
> Acked-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,v2,2/2] libfdt: fix fdt_stringlist_search()

[Tom Rini]

On Mon, Oct 17, 2016 at 08:22:34PM +0900, Masahiro Yamada wrote:

> If fdt_getprop() fails, negative error code should be returned.
> 
> [ DTC commit: daa75e8fa5942caa8e97931aed3a1ee0b7edd74b ]
> 
> Signed-off-by: Masahiro Yamada 
> Signed-off-by: David Gibson 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,v2,1/2] libfdt: fix fdt_stringlist_count()

[Tom Rini]

On Mon, Oct 17, 2016 at 08:22:33PM +0900, Masahiro Yamada wrote:

> If fdt_getprop() fails, negative error code should be returned.
> 
> [ DTC commit: e28eff5b787adb3f461d1653598818b2f1f25a73 ]
> 
> Signed-off-by: Masahiro Yamada 
> Signed-off-by: David Gibson 

Applied to u-boot/master, thanks!

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Re: [U-Boot] power: twl6030: fix code refactoring

[Tom Rini]

On Thu, Oct 13, 2016 at 01:47:53PM +0300, Nicolae Rosia wrote:

> From: Nicolae Rosia 
> 
> Commit a85362fb3e1fc7833723accddbbae431091d06b8 refactored the code
> but the register read ended up in the wrong if branch.
> Currently, the else branch checks a variable which is always 0.
> 
> Signed-off-by: Nicolae Rosia 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 3/3] ext4: Only write journal entries for modified blocks in unlink_filename

[Tom Rini]

On Sun, Oct 09, 2016 at 08:15:28PM +0200, Stefan Brüns wrote:

> Instead of creating a journal entry for each directory block, even
> if the block is unmodified, only log the modified block.
> 
> Signed-off-by: Stefan Brüns 
> Reviewed-by: Tom Rini 
> Reviewed-by: Lukasz Majewski 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 2/3] ext4: Fix handling of direntlen in unlink_filename

[Tom Rini]

On Sun, Oct 09, 2016 at 08:15:27PM +0200, Stefan Brüns wrote:

> The direntlen checks were quite bogus, i.e. the loop termination used
> "len + offset == blocksize" (exact match only), and checked for a
> direntlen less than 0. The latter can never happen as the len is
> unsigned, this has been reported by Coverity, CID 153384.
> 
> Use the same code as in search_dir for directory traversal. This code
> has the correct checks for direntlen >= sizeof(struct dirent), and
> offset < blocksize.
> 
> Signed-off-by: Stefan Brüns 
> Reported-by: Coverity (CID: 153383, 153384)
> Reviewed-by: Tom Rini 
> Reviewed-by: Lukasz Majewski 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,1/3] ext4: cleanup unlink_filename function

[Tom Rini]

On Sun, Oct 09, 2016 at 08:15:26PM +0200, Stefan Brüns wrote:

> Use the same variable names as in search_dir, to make purpose of variables
> more obvious.
> 
> Signed-off-by: Stefan Brüns 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v2 8/8] travis-ci: Add test.py for various qemu platforms

[Tom Rini]

On Thu, Oct 20, 2016 at 03:40:20PM -0400, Tom Rini wrote:

> - Add a PPA for a more recent qemu (required for PowerPC to work)
> - Add tests to run test.py for various QEMU platforms.  This relies on
>   swarren's uboot-test-hooks repository to provide the abstractions.
> 
> Signed-off-by: Tom Rini 

After adding in Stephen's suggested edit, applied to u-boot/master,
thanks!

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Re: [U-Boot] [PATCH 7/8] travis-ci: Drop 'TEST_CMD'

[Tom Rini]

On Thu, Oct 20, 2016 at 03:26:05PM -0400, Tom Rini wrote:

> We don't need to use TEST_CMD in order to run tests.  We need a BUILDMAN
> and TOOLCHAIN variable to avoid having to duplicate logic or write some
> wrapper function.  But this makes the tests harder as we add more
> complex examples.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 6/8] travis-ci: Add more architectures

[Tom Rini]

On Thu, Oct 20, 2016 at 03:26:04PM -0400, Tom Rini wrote:

> We can now build for microblaze, sh4 and xtensa.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 5/8] travis-ci: Update toolchain and buildman usage

[Tom Rini]

On Thu, Oct 20, 2016 at 03:26:03PM -0400, Tom Rini wrote:

> - Drop the 'cache' line, travis-ci says to not cache apt packages (and
>   does not).
> - Get the Ubuntu provided toolchain for ARM and PowerPC.
> - Add more toolchain options that buildman can fetch.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 4/8] travis-ci: Do not make buildman warnings fatal

[Tom Rini]

On Thu, Oct 20, 2016 at 03:26:02PM -0400, Tom Rini wrote:

> We currently will always see a number of warnings due to device tree
> issues.  These (and other warnings) should not make the build be marked
> as failure so catch exit status 129 specifically and return 0 in that
> case.
> 
> Cc: Heiko Schocher 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 3/8] travis-ci: Use a git URI for dtc.git

[Tom Rini]

On Thu, Oct 20, 2016 at 03:26:01PM -0400, Tom Rini wrote:

> Currently we fail to fetch the dtc.git tree due to an SSL issue within
> the travis-ci environment.  The easiest fix here is to switch to a git
> URI.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 2/8] travis-ci: Switch to Ubuntu 14.04 'Trusty Tahr'

[Tom Rini]

On Thu, Oct 20, 2016 at 03:26:00PM -0400, Tom Rini wrote:

> In order to make other various improvements, update to the latest
> environment travis-ci supports.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v7 00/21] imx6: Add Engicam i.CoreM6 QDL support

[Jagan Teki]

On Mon, Oct 24, 2016 at 7:31 PM, Stefano Babic  wrote:
> On 24/10/2016 15:15, Jagan Teki wrote:
>> On Mon, Oct 24, 2016 at 6:04 PM, Stefano Babic  wrote:
>>> Hi Jagan,
>
>>>
>>> Please wait, I am confused. You have sent a complete V8, but as far as I
>>> understand the oinly changes are reported above (Patch 14/15).
>>>
>>> However, even if I have not tested, this would break bisecting, because
>>> patch 4/23 introduces the board and building with that commit leads to
>>> the error. So changes should be respective in patch 4 for mmc and patch
>>> 21 for NAND taking as reference V8.
>>
>> Yes, I've added 14/23 and 15/23 for new changes so the previous 14/21
>> becomes 16/23 now and the only missing one is 21/23. So I will update
>> this 21/23 for v9. Hope this make clear for you.
>
> It is ok if you feel better to send V9 - what I meant it is just that
> entries for CONFIG_DM_MM and CONFIG_DM_MMC_OPS should be done in the
> same patch where the defconfig is added to avoid breaking bisecting.

OK, then I will send the 14/23 with squash of 14/23 and 15/23 to 16/23
and 21/23 v9.
Does it fine?

thanks!
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Hyderabad, India.
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Re: [U-Boot] efi_loader: fix depends on line of EFI_LOADER

[Alexander Graf]

> This line is shown as
> 
>depends on (ARM64 ||\302\240ARM) && OF_LIBFDT
> 
> on my Emacs.  Use ASCII characters only.
> 
> Assuming it is (ARM64 || ARM), remove the redundancy.
> Unlike Linux, CONFIG_ARM includes CONFIG_ARM64 in U-Boot.
> 
> Signed-off-by: Masahiro Yamada 

Thanks, applied to efi-next

Alex

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Re: [U-Boot] [PATCH V4 1/8] tools: imximage: add plugin support

[Stefano Babic]

Hi Peng,

On 11/10/2016 08:29, Peng Fan wrote:
> Add plugin support for imximage.
> 
> Define CONFIG_USE_IMXIMG_PLUGIN in defconfig to enable using plugin.
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> Cc: Eric Nelson 
> Cc: Ye Li 
> Reviewed-by: Tom Rini 
> ---
> 

I have just the same issue as with Jagan's patches. Due to recent
changes, we need to unset a couple of defines in defconfig (ull without
plugin is already fixed).

This means:

diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig
b/configs/mx6ull_14x14_evk_plugin_defconfig
index ff15c8e..095e48d 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -25,6 +25,8 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_74X164=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_REGULATOR=y


If you agree, I will make the change by applying it.

Best regards,
Stefano


> V4:
>  Max 64KB for plugin code.
>  
> V3:
>  Fix compile error.
> 
>  V2:
>   Drop the CONFIG_USE_PLUGIN, make plugin always support in imximage.
> 
>  tools/imximage.c | 283 
> +++
>  tools/imximage.h |   7 +-
>  2 files changed, 230 insertions(+), 60 deletions(-)
> 
> diff --git a/tools/imximage.c b/tools/imximage.c
> index 092d550..615a64e 100644
> --- a/tools/imximage.c
> +++ b/tools/imximage.c
> @@ -27,6 +27,7 @@ static table_entry_t imximage_cmds[] = {
>   {CMD_CHECK_BITS_CLR,"CHECK_BITS_CLR",   "Reg Check bits clr", },
>   {CMD_CSF,   "CSF",   "Command Sequence File", },
>   {CMD_IMAGE_VERSION, "IMAGE_VERSION","image version",  },
> + {CMD_PLUGIN,"PLUGIN",   "file plugin_addr",  },
>   {-1,"", "",   },
>  };
>  
> @@ -80,6 +81,9 @@ static uint32_t imximage_ivt_offset = UNDEFINED;
>  static uint32_t imximage_csf_size = UNDEFINED;
>  /* Initial Load Region Size */
>  static uint32_t imximage_init_loadsize;
> +static uint32_t imximage_iram_free_start;
> +static uint32_t imximage_plugin_size;
> +static uint32_t plugin_image;
>  
>  static set_dcd_val_t set_dcd_val;
>  static set_dcd_param_t set_dcd_param;
> @@ -118,7 +122,11 @@ static uint32_t detect_imximage_version(struct 
> imx_header *imx_hdr)
>  
>   /* Try to detect V2 */
>   if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
> - (hdr_v2->dcd_table.header.tag == DCD_HEADER_TAG))
> + (hdr_v2->data.dcd_table.header.tag == DCD_HEADER_TAG))
> + return IMXIMAGE_V2;
> +
> + if ((fhdr_v2->header.tag == IVT_HEADER_TAG) &&
> + hdr_v2->boot_data.plugin)
>   return IMXIMAGE_V2;
>  
>   return IMXIMAGE_VER_INVALID;
> @@ -165,7 +173,7 @@ static struct dcd_v2_cmd *gd_last_cmd;
>  static void set_dcd_param_v2(struct imx_header *imxhdr, uint32_t dcd_len,
>   int32_t cmd)
>  {
> - dcd_v2_t *dcd_v2 = >header.hdr_v2.dcd_table;
> + dcd_v2_t *dcd_v2 = >header.hdr_v2.data.dcd_table;
>   struct dcd_v2_cmd *d = gd_last_cmd;
>   struct dcd_v2_cmd *d2;
>   int len;
> @@ -261,21 +269,23 @@ static void set_dcd_rst_v1(struct imx_header *imxhdr, 
> uint32_t dcd_len,
>  static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
>   char *name, int lineno)
>  {
> - dcd_v2_t *dcd_v2 = >header.hdr_v2.dcd_table;
> - struct dcd_v2_cmd *d = gd_last_cmd;
> - int len;
> -
> - if (!d)
> - d = _v2->dcd_cmd;
> - len = be16_to_cpu(d->write_dcd_command.length);
> - if (len > 4)
> - d = (struct dcd_v2_cmd *)(((char *)d) + len);
> -
> - len = (char *)d - (char *)_v2->header;
> -
> - dcd_v2->header.tag = DCD_HEADER_TAG;
> - dcd_v2->header.length = cpu_to_be16(len);
> - dcd_v2->header.version = DCD_VERSION;
> + if (!imxhdr->header.hdr_v2.boot_data.plugin) {
> + dcd_v2_t *dcd_v2 = >header.hdr_v2.data.dcd_table;
> + struct dcd_v2_cmd *d = gd_last_cmd;
> + int len;
> +
> + if (!d)
> + d = _v2->dcd_cmd;
> + len = be16_to_cpu(d->write_dcd_command.length);
> + if (len > 4)
> + d = (struct dcd_v2_cmd *)(((char *)d) + len);
> +
> + len = (char *)d - (char *)_v2->header;
> +
> + dcd_v2->header.tag = DCD_HEADER_TAG;
> + dcd_v2->header.length = cpu_to_be16(len);
> + dcd_v2->header.version = DCD_VERSION;
> + }
>  }
>  
>  static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
> @@ -317,24 +327,94 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, 
> uint32_t dcd_len,
>   fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
>   fhdr_v2->header.version = IVT_VERSION; 

Re: [U-Boot] [PATCH v7 00/21] imx6: Add Engicam i.CoreM6 QDL support

[Stefano Babic]

On 24/10/2016 15:15, Jagan Teki wrote:
> On Mon, Oct 24, 2016 at 6:04 PM, Stefano Babic  wrote:
>> Hi Jagan,

>>
>> Please wait, I am confused. You have sent a complete V8, but as far as I
>> understand the oinly changes are reported above (Patch 14/15).
>>
>> However, even if I have not tested, this would break bisecting, because
>> patch 4/23 introduces the board and building with that commit leads to
>> the error. So changes should be respective in patch 4 for mmc and patch
>> 21 for NAND taking as reference V8.
> 
> Yes, I've added 14/23 and 15/23 for new changes so the previous 14/21
> becomes 16/23 now and the only missing one is 21/23. So I will update
> this 21/23 for v9. Hope this make clear for you.

It is ok if you feel better to send V9 - what I meant it is just that
entries for CONFIG_DM_MM and CONFIG_DM_MMC_OPS should be done in the
same patch where the defconfig is added to avoid breaking bisecting.

Regards,
Stefano

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Re: [U-Boot] [PATCH v7 00/21] imx6: Add Engicam i.CoreM6 QDL support

[Jagan Teki]

On Mon, Oct 24, 2016 at 6:04 PM, Stefano Babic  wrote:
> Hi Jagan,
>
> On 24/10/2016 14:09, Jagan Teki wrote:
>> Hi Stefano,
>>
>> On Mon, Oct 24, 2016 at 5:31 PM, Stefano Babic  wrote:
>>> Hi Jagan,
>>>
>>> On 24/10/2016 13:46, Jagan Teki wrote:
>>>
>
> No, this is not the correct way to do. We should stick with the patches
> sent to ML and included in patchworks. They are documented and I cannot
> (that means, all custodians are not allowed) to simply pick up patches
> from somewhere else.

 True, but I am not saying you to just apply the branch. My intention
 was to check the new changes from your side so-that will send the
 series to ML again.
>>>
>>> ok
>>>

>
> It is enough that we agree about issue and solution. I had already
> tested with the following patch:
>
> diff --git a/configs/imx6qdl_icore_mmc_defconfig
> b/configs/imx6qdl_icore_mmc_defconfig
> index 221ea7e..c947e10 100644
> --- a/configs/imx6qdl_icore_mmc_defconfig
> +++ b/configs/imx6qdl_icore_mmc_defconfig
> @@ -6,6 +6,8 @@ CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
>  CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
>  CONFIG_SYS_PROMPT="icorem6qdl> "
>  CONFIG_SPL=y
> +# CONFIG_BLK is not set
> +# CONFIG_DM_MMC_OPS is not set
>  CONFIG_BOOTDELAY=3
>  CONFIG_BOARD_EARLY_INIT_F=y
>  CONFIG_DISPLAY_CPUINFO=y
> diff --git a/configs/imx6qdl_icore_nand_defconfig

 nand_defconfig doesn't require this change.

>>>
>>> It is what I had expected, but fsl_esdhc is built even in the NAND
>>> configuration. There is omething else enabling (not in defconfig).
>>>
>>> In fact, dropping the two lines, I get the error again for
>>> imx6qdl_icore_nand.
>>>
>>> The reason is that even if MMC is not set, as far I can see,  these are
>>> automatically set:
>>>
>>> CONFIG_DM_MMC=y
>>> CONFIG_DM_MMC_OPS=y
>>
>> Ohh, Ok, This is because mx6_common.h by default enabling the MMC.
>
> Right.
>
>> So I will update these on nand support patch[1]  and send the single
>> patch, is that OK?
>>
>> [1] [PATCH v8 21/23] imx6: icorem6: Add NAND support
>>
>
> Please wait, I am confused. You have sent a complete V8, but as far as I
> understand the oinly changes are reported above (Patch 14/15).
>
> However, even if I have not tested, this would break bisecting, because
> patch 4/23 introduces the board and building with that commit leads to
> the error. So changes should be respective in patch 4 for mmc and patch
> 21 for NAND taking as reference V8.

Yes, I've added 14/23 and 15/23 for new changes so the previous 14/21
becomes 16/23 now and the only missing one is 21/23. So I will update
this 21/23 for v9. Hope this make clear for you.

thanks!
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Re: [U-Boot] [PATCH v7 00/21] imx6: Add Engicam i.CoreM6 QDL support

[Stefano Babic]

Hi Jagan,

On 24/10/2016 14:09, Jagan Teki wrote:
> Hi Stefano,
> 
> On Mon, Oct 24, 2016 at 5:31 PM, Stefano Babic  wrote:
>> Hi Jagan,
>>
>> On 24/10/2016 13:46, Jagan Teki wrote:
>>

 No, this is not the correct way to do. We should stick with the patches
 sent to ML and included in patchworks. They are documented and I cannot
 (that means, all custodians are not allowed) to simply pick up patches
 from somewhere else.
>>>
>>> True, but I am not saying you to just apply the branch. My intention
>>> was to check the new changes from your side so-that will send the
>>> series to ML again.
>>
>> ok
>>
>>>

 It is enough that we agree about issue and solution. I had already
 tested with the following patch:

 diff --git a/configs/imx6qdl_icore_mmc_defconfig
 b/configs/imx6qdl_icore_mmc_defconfig
 index 221ea7e..c947e10 100644
 --- a/configs/imx6qdl_icore_mmc_defconfig
 +++ b/configs/imx6qdl_icore_mmc_defconfig
 @@ -6,6 +6,8 @@ CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
  CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
  CONFIG_SYS_PROMPT="icorem6qdl> "
  CONFIG_SPL=y
 +# CONFIG_BLK is not set
 +# CONFIG_DM_MMC_OPS is not set
  CONFIG_BOOTDELAY=3
  CONFIG_BOARD_EARLY_INIT_F=y
  CONFIG_DISPLAY_CPUINFO=y
 diff --git a/configs/imx6qdl_icore_nand_defconfig
>>>
>>> nand_defconfig doesn't require this change.
>>>
>>
>> It is what I had expected, but fsl_esdhc is built even in the NAND
>> configuration. There is omething else enabling (not in defconfig).
>>
>> In fact, dropping the two lines, I get the error again for
>> imx6qdl_icore_nand.
>>
>> The reason is that even if MMC is not set, as far I can see,  these are
>> automatically set:
>>
>> CONFIG_DM_MMC=y
>> CONFIG_DM_MMC_OPS=y
> 
> Ohh, Ok, This is because mx6_common.h by default enabling the MMC.

Right.

> So I will update these on nand support patch[1]  and send the single
> patch, is that OK?
> 
> [1] [PATCH v8 21/23] imx6: icorem6: Add NAND support
> 

Please wait, I am confused. You have sent a complete V8, but as far as I
understand the oinly changes are reported above (Patch 14/15).

However, even if I have not tested, this would break bisecting, because
patch 4/23 introduces the board and building with that commit leads to
the error. So changes should be respective in patch 4 for mmc and patch
21 for NAND taking as reference V8.

Best regards,
Stefano Babic



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[U-Boot] [PATCH] mx6sabresd: Make Ethernet functional again

[Fabio Estevam]

From: Fabio Estevam 

Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate
config for AR8031") ethernet does not work on mx6sabresd.

This commit correctly assigns ar8031_config() as the configuration
function for AR8031 in the same way as done in the Linux kernel.

However, on mx6sabresd design we need some additional configuration,
such as enabling the 125 MHz AR8031 output that needs to be done
in the board file.

This also aligns with the same method that the kernel performs
the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c.

Signed-off-by: Fabio Estevam 
---
 board/freescale/mx6sabresd/mx6sabresd.c | 33 +
 1 file changed, 33 insertions(+)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c 
b/board/freescale/mx6sabresd/mx6sabresd.c
index e58c03c..a5c2b86 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -360,6 +360,39 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+   unsigned short val;
+
+   /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+   phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+   phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+   phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+   val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+   val &= 0xffe3;
+   val |= 0x18;
+   phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+   /* introduce tx clock delay */
+   phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+   val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+   val |= 0x0100;
+   phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+   return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+   ar8031_phy_fixup(phydev);
+
+   if (phydev->drv->config)
+   phydev->drv->config(phydev);
+
+   return 0;
+}
+
 #if defined(CONFIG_VIDEO_IPUV3)
 static void disable_lvds(struct display_info_t const *dev)
 {
-- 
2.7.4

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Re: [U-Boot] [PATCH v7 00/21] imx6: Add Engicam i.CoreM6 QDL support

[Jagan Teki]

Hi Stefano,

On Mon, Oct 24, 2016 at 5:31 PM, Stefano Babic  wrote:
> Hi Jagan,
>
> On 24/10/2016 13:46, Jagan Teki wrote:
>
>>>
>>> No, this is not the correct way to do. We should stick with the patches
>>> sent to ML and included in patchworks. They are documented and I cannot
>>> (that means, all custodians are not allowed) to simply pick up patches
>>> from somewhere else.
>>
>> True, but I am not saying you to just apply the branch. My intention
>> was to check the new changes from your side so-that will send the
>> series to ML again.
>
> ok
>
>>
>>>
>>> It is enough that we agree about issue and solution. I had already
>>> tested with the following patch:
>>>
>>> diff --git a/configs/imx6qdl_icore_mmc_defconfig
>>> b/configs/imx6qdl_icore_mmc_defconfig
>>> index 221ea7e..c947e10 100644
>>> --- a/configs/imx6qdl_icore_mmc_defconfig
>>> +++ b/configs/imx6qdl_icore_mmc_defconfig
>>> @@ -6,6 +6,8 @@ CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
>>>  CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
>>>  CONFIG_SYS_PROMPT="icorem6qdl> "
>>>  CONFIG_SPL=y
>>> +# CONFIG_BLK is not set
>>> +# CONFIG_DM_MMC_OPS is not set
>>>  CONFIG_BOOTDELAY=3
>>>  CONFIG_BOARD_EARLY_INIT_F=y
>>>  CONFIG_DISPLAY_CPUINFO=y
>>> diff --git a/configs/imx6qdl_icore_nand_defconfig
>>
>> nand_defconfig doesn't require this change.
>>
>
> It is what I had expected, but fsl_esdhc is built even in the NAND
> configuration. There is omething else enabling (not in defconfig).
>
> In fact, dropping the two lines, I get the error again for
> imx6qdl_icore_nand.
>
> The reason is that even if MMC is not set, as far I can see,  these are
> automatically set:
>
> CONFIG_DM_MMC=y
> CONFIG_DM_MMC_OPS=y

Ohh, Ok, This is because mx6_common.h by default enabling the MMC.
So I will update these on nand support patch[1]  and send the single
patch, is that OK?

[1] [PATCH v8 21/23] imx6: icorem6: Add NAND support

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U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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[U-Boot] [PATCH v8 23/23] imx6: icorem6: Add default mtd nand partition table

[Jagan Teki]

From: Jagan Teki 

icorem6qdl> mtdparts

device nand0 , # parts = 6
0: spl 0x0020  0x  0
1: uboot   0x0020  0x0020  0
2: env 0x0010  0x0040  0
3: kernel  0x0040  0x0050  0
4: dtb 0x0010  0x0090  0
5: rootfs  0x1f60  0x00a0  0

Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 include/configs/imx6qdl_icore.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h
index 6e33ec3..f8a1263 100644
--- a/include/configs/imx6qdl_icore.h
+++ b/include/configs/imx6qdl_icore.h
@@ -129,6 +129,8 @@
 # define CONFIG_CMD_MTDPARTS
 # define CONFIG_MTD_PARTITIONS
 # define MTDIDS_DEFAULT"nand0=nand"
+# define MTDPARTS_DEFAULT  "mtdparts=nand:2m(spl),2m(uboot)," \
+   "1m(env),4m(kernel),1m(dtb),-(rootfs)"
 
 # define CONFIG_APBH_DMA
 # define CONFIG_APBH_DMA_BURST
-- 
2.7.4

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Re: [U-Boot] [PATCH 1/5] armv8: lsch3: Use SVR based timer base address detection

[Priyanka Jain]

> -Original Message-
> From: york sun
> Sent: Thursday, October 20, 2016 10:46 AM
> To: Prabhakar Kushwaha ; u-
> b...@lists.denx.de
> Cc: Priyanka Jain 
> Subject: Re: [PATCH 1/5] armv8: lsch3: Use SVR based timer base address
> detection
> 
> On 10/19/2016 10:28 PM, Prabhakar Kushwaha wrote:
> > Hi York
> >
> >> -Original Message-
> >> From: Priyanka Jain [mailto:priyanka.j...@nxp.com]
> >> Sent: Wednesday, October 19, 2016 3:07 PM
> >> To: u-boot@lists.denx.de
> >> Cc: Priyanka Jain ; Prabhakar Kushwaha
> >> 
> >> Subject: [PATCH 1/5] armv8: lsch3: Use SVR based timer base address
> >> detection
> >>
> >> Timer base address has been changed from LS2080A SoC to new SoCs like
> >> LS2088A, LS1088A.
> >>
> >> Use SVR based timer base address detection to avoid compile time #ifdef.
> >>
> >> Signed-off-by: Priyanka Jain 
> >> Signed-off-by: Prabhakar Kushwaha 
> >> ---
> >>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|   14 +-
> >>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |3 ++-
> >>  2 files changed, 15 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> index b7a2e0c..ce04e48 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> @@ -424,8 +424,10 @@ int arch_early_init_r(void)
> >>
> >>  int timer_init(void)
> >>  {
> >> -  u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
> >> +  u32 __iomem *cntcr;
> >>  #ifdef CONFIG_FSL_LSCH3
> >> +  struct ccsr_gur __iomem *gur = (void
> >> *)(CONFIG_SYS_FSL_GUTS_ADDR);
> >> +  u32 svr, ver;
> >>u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
> #endif
> >> #ifdef CONFIG_LS2080A @@ -439,6 +441,16 @@ int timer_init(void)
> >> #endif
> >>
> >>  #ifdef CONFIG_FSL_LSCH3
> >> +  svr = gur_in32(>svr);
> >> +  ver = SVR_SOC_VER(svr);
> >> +  if ((ver == SVR_LS2080A) || (ver == SVR_LS2040A) ||
> >> +  (ver == SVR_LS2085A) || (ver == SVR_LS2045A))
> >> +  cntcr = (u32 *)LS2080A_LS2085A_TIMER_ADDR;
> >> +  else
> >> +#endif
> >> +  cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
> >> +
> >> +#ifdef CONFIG_FSL_LSCH3
> >>/* Enable timebase for all clusters.
> >> * It is safe to do so even some clusters are not enabled.
> >> */
> >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >> index 7acba27..e6cdfcb 100644
> >> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >> @@ -23,7 +23,8 @@
> >>  #define CONFIG_SYS_IFC_ADDR   (CONFIG_SYS_IMMR
> +
> >> 0x0124)
> >>  #define CONFIG_SYS_NS16550_COM1
>   (CONFIG_SYS_IMMR +
> >> 0x011C0500)
> >>  #define CONFIG_SYS_NS16550_COM2
>   (CONFIG_SYS_IMMR +
> >> 0x011C0600)
> >> -#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d
> >> +#define LS2080A_LS2085A_TIMER_ADDR0x023d
> >
> > Is this ok to define new constant without CONFIG_?
> > Only problem, it is not consistent with existing defines.
> >
> 
> Prabhakar,
> 
> I opinion on this is
> 
> 1) Let's check if a Kconfig option is better for it If yes, let's convert it 
> to
> Kconfig. If not, go to 2)
> 
> 2) Let's use a different name space for the macros.
> I suggest to use SYS_FSL_* for fixed value for our hardware.
> 
> York

LS2080A_LS2085A_TIMER_ADDR is defining the timer controller (register) offset.
Kconfig option does not look to be very helpful here.
I am thinking of renaming this to "SYS_FSL_LS2080A_LS2085A_TIMER_ADDR"

Please confirm if this is fine.

Priyanka
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[U-Boot] [PATCH v8 20/23] mtd: nand: Kconfig: Add NAND_MXS entry

[Jagan Teki]

From: Jagan Teki 

Added kconfig for NAND_MXS driver.

Cc: Scott Wood 
Cc: Simon Glass 
Cc: Fabio Estevam 
Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/nand/Kconfig | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 5ce7d6d..df154bf 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -80,6 +80,13 @@ config NAND_ARASAN
  controller. This uses the hardware ECC for read and
  write operations.
 
+config NAND_MXS
+   bool "MXS NAND support"
+   depends on MX6
+   help
+ This enables NAND driver for the NAND flash controller on the
+ MXS processors.
+
 comment "Generic NAND options"
 
 # Enhance depends when converting drivers to Kconfig which use this config
-- 
2.7.4

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[U-Boot] [PATCH v8 22/23] imx6: icorem6: Enable MTD device support

[Jagan Teki]

From: Jagan Teki 

Enable MTD device, partition and command support.

Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 include/configs/imx6qdl_icore.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h
index cd3aa43..6e33ec3 100644
--- a/include/configs/imx6qdl_icore.h
+++ b/include/configs/imx6qdl_icore.h
@@ -124,6 +124,12 @@
 # define CONFIG_SYS_NAND_U_BOOT_START  CONFIG_SYS_TEXT_BASE
 # define CONFIG_SYS_NAND_U_BOOT_OFFS   0x20
 
+/* MTD device */
+# define CONFIG_MTD_DEVICE
+# define CONFIG_CMD_MTDPARTS
+# define CONFIG_MTD_PARTITIONS
+# define MTDIDS_DEFAULT"nand0=nand"
+
 # define CONFIG_APBH_DMA
 # define CONFIG_APBH_DMA_BURST
 # define CONFIG_APBH_DMA_BURST8
-- 
2.7.4

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[U-Boot] [PATCH v8 21/23] imx6: icorem6: Add NAND support

[Jagan Teki]

From: Jagan Teki 

Add NAND support for Engicam i.CoreM6 qdl board.

Boot Log:


U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43)
Trying to boot from NAND
NAND : 512 MiB

U-Boot 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43 +0530)

CPU:   Freescale i.MX6SOLO rev1.3 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 55C
Reset cause: WDOG
Model: Engicam i.CoreM6 DualLite/Solo Starter Kit
DRAM:  256 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0
icorem6qdl>

Cc: Scott Wood 
Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 board/engicam/icorem6/icorem6.c  | 63 
 configs/imx6qdl_icore_nand_defconfig | 37 +
 include/configs/imx6qdl_icore.h  | 25 +-
 3 files changed, 124 insertions(+), 1 deletion(-)
 create mode 100644 configs/imx6qdl_icore_nand_defconfig

diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index a370c8b..c152007 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -101,6 +101,66 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_NAND_MXS
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+   PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+iomux_v3_cfg_t gpmi_pads[] = {
+   IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE  | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE  | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B  | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
+   IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+   IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+};
+
+static void setup_gpmi_nand(void)
+{
+   struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   /* config gpmi nand iomux */
+   SETUP_IOMUX_PADS(gpmi_pads);
+
+   /* gate ENFC_CLK_ROOT clock first,before clk source switch */
+   clrbits_le32(_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+   /* config gpmi and bch clock to 100 MHz */
+   clrsetbits_le32(_ccm->cs2cdr,
+   MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+   MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+   MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+   MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+   MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+   MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+   /* enable ENFC_CLK_ROOT clock */
+   setbits_le32(_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+   /* enable gpmi and bch clock gating */
+   setbits_le32(_ccm->CCGR4,
+MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+   /* enable apbh clock gating */
+   setbits_le32(_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
 int board_early_init_f(void)
 {
SETUP_IOMUX_PADS(uart4_pads);
@@ -113,6 +173,9 @@ int board_init(void)
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_NAND_MXS
+   setup_gpmi_nand();
+#endif
return 0;
 }
 
diff --git a/configs/imx6qdl_icore_nand_defconfig 
b/configs/imx6qdl_icore_nand_defconfig
new file mode 100644
index 000..8ac3099
--- /dev/null
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6Q_ICORE=y

[U-Boot] [PATCH v8 18/23] arm: dts: imx6q: Add pinctrl defines

[Jagan Teki]

From: Jagan Teki 

Add imx6q pinctrl defines support from Linux.

Here is the last commit:
"ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ"
(sha1: d8c765e0d1ddbd5032c2491c82cc9660c2f0e7f2)

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6q-pinfunc.h | 1047 ++
 1 file changed, 1047 insertions(+)
 create mode 100644 arch/arm/dts/imx6q-pinfunc.h

diff --git a/arch/arm/dts/imx6q-pinfunc.h b/arch/arm/dts/imx6q-pinfunc.h
new file mode 100644
index 000..9fc6120
--- /dev/null
+++ b/arch/arm/dts/imx6q-pinfunc.h
@@ -0,0 +1,1047 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6Q_PINFUNC_H
+#define __DTS_IMX6Q_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * 
+ */
+#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1  0x04c 0x360 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B  0x04c 0x360 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS  0x04c 0x360 0x7c8 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT1__KEY_COL7   0x04c 0x360 0x8f0 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2  0x050 0x364 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B  0x050 0x364 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD   0x050 0x364 0x7b8 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6   0x050 0x364 0x8f8 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0  0x054 0x368 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO0x054 0x368 0x82c 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD   0x054 0x368 0x7b4 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7   0x054 0x368 0x8fc 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT  0x054 0x368 0x000 0x6 0x0
+#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA   0x058 0x36c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0
+#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO190x058 0x36c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x058 0x36c 0x000 0x7 0x0
+#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY  0x05c 0x370 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO200x05c 0x370 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG   0x060 0x374 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO210x060 0x374 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA   0x064 0x378 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO220x064 0x378 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE   0x068 0x37c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO230x068 0x37c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA0x06c 0x380 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x06c 0x380 0x858 0x1 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY  0x070 0x384 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO250x070 0x384 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE  0x074 0x388 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x074 0x388 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK   0x074 0x388 0x83c 0x7 0x0
+#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG   0x078 0x38c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO270x078 0x38c 0x000 

[U-Boot] [PATCH v8 19/23] arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/Dual

[Jagan Teki]

From: Jagan Teki 

i.CoreM6 Quad/Dual modules are system on module solutions
manufactured by Engicam with following characteristics:
CPU   NXP i.MX6 DQ, 800MHz
RAM   1GB, 32, 64 bit, DDR3-800/1066
NAND  SLC,512MB
Power supply  Single 5V
MAX LCD RES   FULLHD

and more info at
http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/Makefile|  3 ++-
 arch/arm/dts/imx6q-icore.dts | 59 
 board/engicam/icorem6/README |  9 ++-
 3 files changed, 69 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/imx6q-icore.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9ddfb83..61eb852 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -283,7 +283,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
bk4r1.dtb
 
 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
-   imx6dl-icore.dtb
+   imx6dl-icore.dtb \
+   imx6q-icore.dtb
 
 dtb-$(CONFIG_MX7) += imx7-colibri.dtb
 
diff --git a/arch/arm/dts/imx6q-icore.dts b/arch/arm/dts/imx6q-icore.dts
new file mode 100644
index 000..025f543
--- /dev/null
+++ b/arch/arm/dts/imx6q-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+   model = "Engicam i.CoreM6 Quad/Dual Starter Kit";
+   compatible = "engicam,imx6-icore", "fsl,imx6q";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README
index c264a94..12d1e21 100644
--- a/board/engicam/icorem6/README
+++ b/board/engicam/icorem6/README
@@ -1,12 +1,19 @@
 How to use U-Boot on Engicam i.CoreM6 DualLite/Solo and Quad/Dual Starter Kit:
 -
 
-- Build U-Boot for Engicam i.CoreM6 QDL:
+- Configure U-Boot for Engicam i.CoreM6 QDL:
 
 $ make mrproper
 $ make icorem6qdl_mmc_defconfig
+
+- Build for i.CoreM6 DualLite/Solo
+
 $ make
 
+- Build for i.CoreM6 Quad/Dual
+
+$ make DEVICE_TREE=imx6q-icore
+
 This will generate the SPL image called SPL and the u-boot-dtb.img.
 
 - Flash the SPL image into the micro SD card:
-- 
2.7.4

___
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[U-Boot] [PATCH v8 16/23] engicam: icorem6: Add DM_GPIO, DM_MMC support

[Jagan Teki]

From: Jagan Teki 

Add DM_GPIO, DM_MMC support for u-boot and disable for SPL.

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/cpu/armv7/mx6/Kconfig  |   2 +
 board/engicam/icorem6/icorem6.c | 142 
 include/configs/imx6qdl_icore.h |   4 ++
 3 files changed, 78 insertions(+), 70 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index e2431a8..762a581 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -100,6 +100,8 @@ config TARGET_MX6Q_ICORE
select MX6QDL
select OF_CONTROL
select DM
+   select DM_GPIO
+   select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
 
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index a23cb7e..a370c8b 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -7,8 +7,6 @@
  */
 
 #include 
-#include 
-#include 
 #include 
 #include 
 
@@ -29,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |   \
PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
-   PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
-   PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |\
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
@@ -55,70 +49,6 @@ static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-   IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-   IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
-};
-
-#ifdef CONFIG_FSL_ESDHC
-#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
-
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
-   {USDHC1_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-   struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-   int ret = 0;
-
-   switch (cfg->esdhc_base) {
-   case USDHC1_BASE_ADDR:
-   ret = !gpio_get_value(USDHC1_CD_GPIO);
-   break;
-   }
-
-   return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-   int i, ret;
-
-   /*
-   * According to the board_mmc_init() the following map is done:
-   * (U-boot device node)(Physical Port)
-   * mmc0  USDHC1
-   */
-   for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-   switch (i) {
-   case 0:
-   SETUP_IOMUX_PADS(usdhc1_pads);
-   gpio_direction_input(USDHC1_CD_GPIO);
-   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-   break;
-   default:
-   printf("Warning - USDHC%d controller not supporting\n",
-  i + 1);
-   return 0;
-   }
-
-   ret = fsl_esdhc_initialize(bis, _cfg[i]);
-   if (ret) {
-   printf("Warning: failed to initialize mmc dev %d\n", i);
-   return ret;
-   }
-   }
-
-   return 0;
-}
-#endif
-
 #ifdef CONFIG_FEC_MXC
 #define ENET_PHY_RST   IMX_GPIO_NR(7, 12)
 static int setup_fec(void)
@@ -200,6 +130,78 @@ int dram_init(void)
 #include 
 #include 
 
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include 
+#include 
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+   PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
+   PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+   IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+   

Re: [U-Boot] [PATCH v7 00/21] imx6: Add Engicam i.CoreM6 QDL support

[Stefano Babic]

Hi Jagan,

On 24/10/2016 13:46, Jagan Teki wrote:

>>
>> No, this is not the correct way to do. We should stick with the patches
>> sent to ML and included in patchworks. They are documented and I cannot
>> (that means, all custodians are not allowed) to simply pick up patches
>> from somewhere else.
> 
> True, but I am not saying you to just apply the branch. My intention
> was to check the new changes from your side so-that will send the
> series to ML again.

ok

> 
>>
>> It is enough that we agree about issue and solution. I had already
>> tested with the following patch:
>>
>> diff --git a/configs/imx6qdl_icore_mmc_defconfig
>> b/configs/imx6qdl_icore_mmc_defconfig
>> index 221ea7e..c947e10 100644
>> --- a/configs/imx6qdl_icore_mmc_defconfig
>> +++ b/configs/imx6qdl_icore_mmc_defconfig
>> @@ -6,6 +6,8 @@ CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
>>  CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
>>  CONFIG_SYS_PROMPT="icorem6qdl> "
>>  CONFIG_SPL=y
>> +# CONFIG_BLK is not set
>> +# CONFIG_DM_MMC_OPS is not set
>>  CONFIG_BOOTDELAY=3
>>  CONFIG_BOARD_EARLY_INIT_F=y
>>  CONFIG_DISPLAY_CPUINFO=y
>> diff --git a/configs/imx6qdl_icore_nand_defconfig
> 
> nand_defconfig doesn't require this change.
> 

It is what I had expected, but fsl_esdhc is built even in the NAND
configuration. There is omething else enabling (not in defconfig).

In fact, dropping the two lines, I get the error again for
imx6qdl_icore_nand.

The reason is that even if MMC is not set, as far I can see,  these are
automatically set:

CONFIG_DM_MMC=y
CONFIG_DM_MMC_OPS=y

>> b/configs/imx6qdl_icore_nand_defconfig
>> index 8ac3099..55650bb 100644
>> --- a/configs/imx6qdl_icore_nand_defconfig
>> +++ b/configs/imx6qdl_icore_nand_defconfig
>> @@ -6,6 +6,8 @@ CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
>>  CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
>>  CONFIG_SYS_PROMPT="icorem6qdl> "
>>  CONFIG_SPL=y
>> +# CONFIG_BLK is not set
>> +# CONFIG_DM_MMC_OPS is not set
>>  CONFIG_BOOTDELAY=3
>>  CONFIG_BOARD_EARLY_INIT_F=y
>>  CONFIG_DISPLAY_CPUINFO=y
> 
> thanks!
> 


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[U-Boot] [PATCH v8 17/23] arm: dts: Add devicetree for i.MX6Q

[Jagan Teki]

From: Jagan Teki 

Add i.MX6Q dtsi support from Linux.

Here is the last commit:
"ARM: dts: add gpio-ranges property to iMX GPIO controllers"
(sha1: bb728d662bed0fe91b152550e640cb3f6caa972c)

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6q.dtsi | 300 
 1 file changed, 300 insertions(+)
 create mode 100644 arch/arm/dts/imx6q.dtsi

diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
new file mode 100644
index 000..c30c836
--- /dev/null
+++ b/arch/arm/dts/imx6q.dtsi
@@ -0,0 +1,300 @@
+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include 
+#include "imx6q-pinfunc.h"
+#include "imx6qdl.dtsi"
+
+/ {
+   aliases {
+   ipu1 = 
+   spi4 = 
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   operating-points = <
+   /* kHzuV */
+   120 1275000
+   996000  125
+   852000  125
+   792000  1175000
+   396000  975000
+   >;
+   fsl,soc-operating-points = <
+   /* ARM kHz  SOC-PU uV */
+   120 1275000
+   996000  125
+   852000  125
+   792000  1175000
+   396000  1175000
+   >;
+   clock-latency = <61036>; /* two CLK32 periods */
+   clocks = < IMX6QDL_CLK_ARM>,
+< IMX6QDL_CLK_PLL2_PFD2_396M>,
+< IMX6QDL_CLK_STEP>,
+< IMX6QDL_CLK_PLL1_SW>,
+< IMX6QDL_CLK_PLL1_SYS>;
+   clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+   arm-supply = <_arm>;
+   pu-supply = <_pu>;
+   soc-supply = <_soc>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <2>;
+   next-level-cache = <>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <3>;
+   next-level-cache = <>;
+   };
+   };
+
+   soc {
+   ocram: sram@0090 {
+   compatible = "mmio-sram";
+   reg = <0x0090 0x4>;
+   clocks = < IMX6QDL_CLK_OCRAM>;
+   };
+
+   aips-bus@0200 { /* AIPS1 */
+   spba-bus@0200 {
+   ecspi5: ecspi@02018000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "fsl,imx6q-ecspi", 
"fsl,imx51-ecspi";
+   reg = <0x02018000 0x4000>;
+   interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < IMX6Q_CLK_ECSPI5>,
+< IMX6Q_CLK_ECSPI5>;
+   clock-names = "ipg", "per";
+   dmas = < 11 7 1>, < 12 7 2>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+   };
+
+   iomuxc: iomuxc@020e {
+   compatible = "fsl,imx6q-iomuxc";
+   };
+   };
+
+   sata: sata@0220 

[U-Boot] [PATCH v8 12/23] arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/Solo

[Jagan Teki]

From: Jagan Teki 

i.CoreM6 DualLite/Solo modules are system on module solutions
manufactured by Engicam with following characteristics:
CPU   NXP i.MX6 DL, 800MHz
RAM   1GB, 32, 64 bit, DDR3-800/1066
NAND  SLC,512MB
Power supply  Single 5V
MAX LCD RES   FULLHD

and more info at
http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/cpu/armv7/mx6/Kconfig  |   1 +
 arch/arm/dts/Makefile   |   3 +-
 arch/arm/dts/imx6dl-icore.dts   |  59 +++
 arch/arm/dts/imx6qdl-icore.dtsi | 196 
 board/engicam/icorem6/README|   6 +-
 configs/imx6qdl_icore_mmc_defconfig |   1 +
 6 files changed, 262 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/dts/imx6dl-icore.dts
 create mode 100644 arch/arm/dts/imx6qdl-icore.dtsi

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 5d549bd..e2431a8 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -98,6 +98,7 @@ config TARGET_MX6QARM2
 config TARGET_MX6Q_ICORE
bool "Support Engicam i.Core"
select MX6QDL
+   select OF_CONTROL
select DM
select DM_THERMAL
select SUPPORT_SPL
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8458f6b..9ddfb83 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -282,7 +282,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
pcm052.dtb \
bk4r1.dtb
 
-dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb
+dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
+   imx6dl-icore.dtb
 
 dtb-$(CONFIG_MX7) += imx7-colibri.dtb
 
diff --git a/arch/arm/dts/imx6dl-icore.dts b/arch/arm/dts/imx6dl-icore.dts
new file mode 100644
index 000..aec332c
--- /dev/null
+++ b/arch/arm/dts/imx6dl-icore.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+   model = "Engicam i.CoreM6 DualLite/Solo Starter Kit";
+   compatible = "engicam,imx6-icore", "fsl,imx6dl";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi
new file mode 100644
index 000..f424cd5
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-icore.dtsi
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of 

[U-Boot] [PATCH v8 14/23] configs: imx6qdl: Enable CONFIG_BLK if DM_MMC

[Jagan Teki]

From: Jagan Teki 

Enable CONFIG_BLK only when DM_MMC enabled, this changes
as per the commit
"dm: blk: Enable CONFIG_BLK if DM_MMC is enabled"
(sha1: 896a74f615d6ffcbbcbec1505b19ed3280fe7873)

Cc: Peng Fan 
Cc: Stefano Babic 
Signed-off-by: Jagan Teki 
---
 configs/imx6qdl_icore_mmc_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/imx6qdl_icore_mmc_defconfig 
b/configs/imx6qdl_icore_mmc_defconfig
index 221ea7e..b1d59d1 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -13,6 +13,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTO_COMPLETE=y
 CONFIG_SYS_MAXARGS=32
 # CONFIG_CMD_IMLS is not set
+# CONFIG_BLK is not set
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MII=y
-- 
2.7.4

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[U-Boot] [PATCH v8 15/23] configs: imx6qdl: Enable CONFIG_DM_MMC_OPS if DM_MMC

[Jagan Teki]

From: Jagan Teki 

Enable CONFIG_DM_MMC_OPS only when DM_MMC enabled,
this changes as per the commit
"dm: mmc: Enable DM_MMC_OPS by default with DM_MMC"
(sha1: 252788b4eda852e0195e1903e55480b4bf4fea9d)

Cc: Peng Fan 
Cc: Stefano Babic 
Signed-off-by: Jagan Teki 
---
 configs/imx6qdl_icore_mmc_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/imx6qdl_icore_mmc_defconfig 
b/configs/imx6qdl_icore_mmc_defconfig
index b1d59d1..fcf4934 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -14,6 +14,7 @@ CONFIG_AUTO_COMPLETE=y
 CONFIG_SYS_MAXARGS=32
 # CONFIG_CMD_IMLS is not set
 # CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MII=y
-- 
2.7.4

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[U-Boot] [PATCH v8 13/23] imx6q: icorem6: Enable pinctrl driver

[Jagan Teki]

From: Jagan Teki 

Enable imx6 pinctrl driver support for i.CoreM6.

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 configs/imx6qdl_icore_mmc_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/imx6qdl_icore_mmc_defconfig 
b/configs/imx6qdl_icore_mmc_defconfig
index 6786daf..221ea7e 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -30,6 +30,8 @@ CONFIG_FEC_MXC=y
 CONFIG_MXC_UART=y
 CONFIG_NETDEVICES=y
 CONFIG_IMX_THERMAL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-- 
2.7.4

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[U-Boot] [PATCH v8 10/23] arm: dts: imx6dl: Add pinctrl defines

[Jagan Teki]

From: Jagan Teki 

Add imx6dl pinctrl defines support from Linux.

Here is the last commit:
"ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ"
(sha1: d8c765e0d1ddbd5032c2491c82cc9660c2f0e7f2)

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6dl-pinfunc.h | 1091 +
 1 file changed, 1091 insertions(+)
 create mode 100644 arch/arm/dts/imx6dl-pinfunc.h

diff --git a/arch/arm/dts/imx6dl-pinfunc.h b/arch/arm/dts/imx6dl-pinfunc.h
new file mode 100644
index 000..0ead323
--- /dev/null
+++ b/arch/arm/dts/imx6dl-pinfunc.h
@@ -0,0 +1,1091 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6DL_PINFUNC_H
+#define __DTS_IMX6DL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * 
+ */
+#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO  0x04c 0x360 0x7f8 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA0x04c 0x360 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA0x04c 0x360 0x8fc 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28   0x04c 0x360 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07  0x04c 0x360 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS0x050 0x364 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0   0x050 0x364 0x800 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA0x050 0x364 0x8fc 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA0x050 0x364 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29   0x050 0x364 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08  0x050 0x364 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08   0x054 0x368 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA0x054 0x368 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA0x054 0x368 0x914 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30   0x054 0x368 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09  0x054 0x368 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09   0x058 0x36c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA0x058 0x36c 0x914 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA0x058 0x36c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31   0x058 0x36c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10  0x058 0x36c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10   0x05c 0x370 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA0x05c 0x370 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA0x05c 0x370 0x91c 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00   0x05c 0x370 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11  0x05c 0x370 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11   0x060 0x374 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA0x060 0x374 0x91c 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA0x060 0x374 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01   0x060 0x374 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12  0x060 0x374 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12   0x064 0x378 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B  0x064 0x378 0x910 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B  0x064 0x378 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02   0x064 0x378 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13  0x064 0x378 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13   0x068 0x37c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B  0x068 0x37c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B  0x068 

[U-Boot] [PATCH v8 11/23] dt-bindings: clock: imx6qdl: Add clock defines

[Jagan Teki]

From: Jagan Teki 

Add imx6qdl clock header defines support from Linux.

"clk: imx: Add clock support for imx6qp"
(sha1: ee36027427c769b0b9e5e205fe43aced93d6aa66)

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 include/dt-bindings/clock/imx6qdl-clock.h | 274 ++
 1 file changed, 274 insertions(+)
 create mode 100644 include/dt-bindings/clock/imx6qdl-clock.h

diff --git a/include/dt-bindings/clock/imx6qdl-clock.h 
b/include/dt-bindings/clock/imx6qdl-clock.h
new file mode 100644
index 000..2905033
--- /dev/null
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
+#define __DT_BINDINGS_CLOCK_IMX6QDL_H
+
+#define IMX6QDL_CLK_DUMMY  0
+#define IMX6QDL_CLK_CKIL   1
+#define IMX6QDL_CLK_CKIH   2
+#define IMX6QDL_CLK_OSC3
+#define IMX6QDL_CLK_PLL2_PFD0_352M 4
+#define IMX6QDL_CLK_PLL2_PFD1_594M 5
+#define IMX6QDL_CLK_PLL2_PFD2_396M 6
+#define IMX6QDL_CLK_PLL3_PFD0_720M 7
+#define IMX6QDL_CLK_PLL3_PFD1_540M 8
+#define IMX6QDL_CLK_PLL3_PFD2_508M 9
+#define IMX6QDL_CLK_PLL3_PFD3_454M 10
+#define IMX6QDL_CLK_PLL2_198M  11
+#define IMX6QDL_CLK_PLL3_120M  12
+#define IMX6QDL_CLK_PLL3_80M   13
+#define IMX6QDL_CLK_PLL3_60M   14
+#define IMX6QDL_CLK_TWD15
+#define IMX6QDL_CLK_STEP   16
+#define IMX6QDL_CLK_PLL1_SW17
+#define IMX6QDL_CLK_PERIPH_PRE 18
+#define IMX6QDL_CLK_PERIPH2_PRE19
+#define IMX6QDL_CLK_PERIPH_CLK2_SEL20
+#define IMX6QDL_CLK_PERIPH2_CLK2_SEL   21
+#define IMX6QDL_CLK_AXI_SEL22
+#define IMX6QDL_CLK_ESAI_SEL   23
+#define IMX6QDL_CLK_ASRC_SEL   24
+#define IMX6QDL_CLK_SPDIF_SEL  25
+#define IMX6QDL_CLK_GPU2D_AXI  26
+#define IMX6QDL_CLK_GPU3D_AXI  27
+#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
+#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
+#define IMX6QDL_CLK_GPU3D_SHADER_SEL   30
+#define IMX6QDL_CLK_IPU1_SEL   31
+#define IMX6QDL_CLK_IPU2_SEL   32
+#define IMX6QDL_CLK_LDB_DI0_SEL33
+#define IMX6QDL_CLK_LDB_DI1_SEL34
+#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL   35
+#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL   36
+#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL   37
+#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL   38
+#define IMX6QDL_CLK_IPU1_DI0_SEL   39
+#define IMX6QDL_CLK_IPU1_DI1_SEL   40
+#define IMX6QDL_CLK_IPU2_DI0_SEL   41
+#define IMX6QDL_CLK_IPU2_DI1_SEL   42
+#define IMX6QDL_CLK_HSI_TX_SEL 43
+#define IMX6QDL_CLK_PCIE_AXI_SEL   44
+#define IMX6QDL_CLK_SSI1_SEL   45
+#define IMX6QDL_CLK_SSI2_SEL   46
+#define IMX6QDL_CLK_SSI3_SEL   47
+#define IMX6QDL_CLK_USDHC1_SEL 48
+#define IMX6QDL_CLK_USDHC2_SEL 49
+#define IMX6QDL_CLK_USDHC3_SEL 50
+#define IMX6QDL_CLK_USDHC4_SEL 51
+#define IMX6QDL_CLK_ENFC_SEL   52
+#define IMX6QDL_CLK_EIM_SEL53
+#define IMX6QDL_CLK_EIM_SLOW_SEL   54
+#define IMX6QDL_CLK_VDO_AXI_SEL55
+#define IMX6QDL_CLK_VPU_AXI_SEL56
+#define IMX6QDL_CLK_CKO1_SEL   57
+#define IMX6QDL_CLK_PERIPH 58
+#define IMX6QDL_CLK_PERIPH259
+#define IMX6QDL_CLK_PERIPH_CLK260
+#define IMX6QDL_CLK_PERIPH2_CLK2   61
+#define IMX6QDL_CLK_IPG62
+#define IMX6QDL_CLK_IPG_PER63
+#define IMX6QDL_CLK_ESAI_PRED  64
+#define IMX6QDL_CLK_ESAI_PODF  65
+#define IMX6QDL_CLK_ASRC_PRED  66
+#define IMX6QDL_CLK_ASRC_PODF  67
+#define IMX6QDL_CLK_SPDIF_PRED 68
+#define IMX6QDL_CLK_SPDIF_PODF 69
+#define IMX6QDL_CLK_CAN_ROOT   70
+#define IMX6QDL_CLK_ECSPI_ROOT 71
+#define IMX6QDL_CLK_GPU2D_CORE_PODF72
+#define 

[U-Boot] [PATCH v8 09/23] arm: dts: Add devicetree for i.MX6DQL

[Jagan Teki]

From: Jagan Teki 

Add i.MX6DQL dtsi support from Linux.

Here is the last commit:
"ARM: dts: imx6qdl: Fix SPDIF regression"
(sha1: f065e9e4addd75c21bb976bb2558648bf4f61de6)

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6qdl.dtsi | 1281 +
 1 file changed, 1281 insertions(+)
 create mode 100644 arch/arm/dts/imx6qdl.dtsi

diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
new file mode 100644
index 000..b13b0b2
--- /dev/null
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -0,0 +1,1281 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include 
+#include 
+
+#include "skeleton.dtsi"
+
+/ {
+   aliases {
+   ethernet0 = 
+   can0 = 
+   can1 = 
+   gpio0 = 
+   gpio1 = 
+   gpio2 = 
+   gpio3 = 
+   gpio4 = 
+   gpio5 = 
+   gpio6 = 
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   ipu0 = 
+   mmc0 = 
+   mmc1 = 
+   mmc2 = 
+   mmc3 = 
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   spi0 = 
+   spi1 = 
+   spi2 = 
+   spi3 = 
+   usbphy0 = 
+   usbphy1 = 
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ckil {
+   compatible = "fsl,imx-ckil", "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+
+   ckih1 {
+   compatible = "fsl,imx-ckih1", "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   osc {
+   compatible = "fsl,imx-osc", "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <2400>;
+   };
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+   ranges;
+
+   dma_apbh: dma-apbh@0011 {
+   compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+   reg = <0x0011 0x2000>;
+   interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
+<0 13 IRQ_TYPE_LEVEL_HIGH>,
+<0 13 IRQ_TYPE_LEVEL_HIGH>,
+<0 13 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+   #dma-cells = <1>;
+   dma-channels = <4>;
+   clocks = < IMX6QDL_CLK_APBH_DMA>;
+   };
+
+   gpmi: gpmi-nand@00112000 {
+   compatible = "fsl,imx6q-gpmi-nand";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+   reg-names = "gpmi-nand", "bch";
+   interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-names = "bch";
+   clocks = < IMX6QDL_CLK_GPMI_IO>,
+< IMX6QDL_CLK_GPMI_APB>,
+< IMX6QDL_CLK_GPMI_BCH>,
+< IMX6QDL_CLK_GPMI_BCH_APB>,
+< IMX6QDL_CLK_PER1_BCH>;
+   clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+ "gpmi_bch_apb", "per1_bch";
+   dmas = <_apbh 0>;
+   dma-names = "rx-tx";
+   status = "disabled";
+   };
+
+   hdmi: hdmi@012 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0012 0x9000>;
+   interrupts = <0 115 0x04>;
+   gpr = <>;
+   clocks = < IMX6QDL_CLK_HDMI_IAHB>,
+< 

[U-Boot] [PATCH v8 08/23] arm: dts: Add devicetree for i.MX6DL

[Jagan Teki]

From: Jagan Teki 

Add i.MX6DL dtsi support from Linux.

Here is the last commit:
"ARM: dts: add gpio-ranges property to iMX GPIO controllers"
(sha1: bb728d662bed0fe91b152550e640cb3f6caa972c)

Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 arch/arm/dts/imx6dl.dtsi | 133 +++
 1 file changed, 133 insertions(+)
 create mode 100644 arch/arm/dts/imx6dl.dtsi

diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
new file mode 100644
index 000..9a4c22c
--- /dev/null
+++ b/arch/arm/dts/imx6dl.dtsi
@@ -0,0 +1,133 @@
+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include 
+#include "imx6dl-pinfunc.h"
+#include "imx6qdl.dtsi"
+
+/ {
+   aliases {
+   i2c3 = 
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   operating-points = <
+   /* kHzuV */
+   996000  125
+   792000  1175000
+   396000  115
+   >;
+   fsl,soc-operating-points = <
+   /* ARM kHz  SOC-PU uV */
+   996000  1175000
+   792000  1175000
+   396000  1175000
+   >;
+   clock-latency = <61036>; /* two CLK32 periods */
+   clocks = < IMX6QDL_CLK_ARM>,
+< IMX6QDL_CLK_PLL2_PFD2_396M>,
+< IMX6QDL_CLK_STEP>,
+< IMX6QDL_CLK_PLL1_SW>,
+< IMX6QDL_CLK_PLL1_SYS>;
+   clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+   arm-supply = <_arm>;
+   pu-supply = <_pu>;
+   soc-supply = <_soc>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <>;
+   };
+   };
+
+   soc {
+   ocram: sram@0090 {
+   compatible = "mmio-sram";
+   reg = <0x0090 0x2>;
+   clocks = < IMX6QDL_CLK_OCRAM>;
+   };
+
+   aips1: aips-bus@0200 {
+   iomuxc: iomuxc@020e {
+   compatible = "fsl,imx6dl-iomuxc";
+   };
+
+   pxp: pxp@020f {
+   reg = <0x020f 0x4000>;
+   interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+   };
+
+   epdc: epdc@020f4000 {
+   reg = <0x020f4000 0x4000>;
+   interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+   };
+
+   lcdif: lcdif@020f8000 {
+   reg = <0x020f8000 0x4000>;
+   interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+   };
+   };
+
+   aips2: aips-bus@0210 {
+   i2c4: i2c@021f8000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+   reg = <0x021f8000 0x4000>;
+   interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < IMX6DL_CLK_I2C4>;
+   status = "disabled";
+   };
+   };
+   };
+
+   display-subsystem {
+   compatible = "fsl,imx-display-subsystem";
+   ports = <_di0>, <_di1>;
+   };
+
+   gpu-subsystem {
+   compatible = "fsl,imx-gpu-subsystem";
+   cores = <_2d>, <_3d>;
+   };
+};
+
+ {
+   compatible = "fsl,imx6dl-gpt";
+};
+
+ {
+   compatible = "fsl,imx6dl-hdmi";
+};
+
+ {
+   clocks = < IMX6QDL_CLK_LDB_DI0_SEL>, < 

[U-Boot] [PATCH v8 04/23] arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support

[Jagan Teki]

From: Jagan Teki 

Boot Log for i.CoreM6 DualLite/Solo Starter Kit:
---

U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1

U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)

CPU:   Freescale i.MX6SOLO rev1.3 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 31C
Reset cause: POR
DRAM:  256 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
switch to partitions #0, OK
mmc0 is current device
reading boot.scr
** Unable to read file boot.scr **
reading zImage
6741808 bytes read in 341 ms (18.9 MiB/s)
Booting from mmc ...
reading imx6dl-icore.dtb
30600 bytes read in 19 ms (1.5 MiB/s)
   Booting using the fdt blob at 0x1800
   Using Device Tree in place at 1800, end 1800a787

Starting kernel ...

[0.00] Booting Linux on physical CPU 0x0

Boot Log for i.CoreM6 Quad/Dual Starter Kit:


U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1

U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)

CPU:   Freescale i.MX6Q rev1.2 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 28C
Reset cause: POR
DRAM:  512 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
icorem6qdl>

Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Acked-by: Peng Fan 
Signed-off-by: Jagan Teki 
---
 arch/arm/cpu/armv7/mx6/Kconfig  |   8 +
 arch/arm/include/asm/imx-common/sys_proto.h |   2 +
 board/engicam/icorem6/Kconfig   |  12 +
 board/engicam/icorem6/MAINTAINERS   |   6 +
 board/engicam/icorem6/Makefile  |   6 +
 board/engicam/icorem6/README|  31 +++
 board/engicam/icorem6/icorem6.c | 400 
 configs/imx6qdl_icore_mmc_defconfig |  35 +++
 include/configs/imx6qdl_icore.h | 120 +
 9 files changed, 620 insertions(+)
 create mode 100644 board/engicam/icorem6/Kconfig
 create mode 100644 board/engicam/icorem6/MAINTAINERS
 create mode 100644 board/engicam/icorem6/Makefile
 create mode 100644 board/engicam/icorem6/README
 create mode 100644 board/engicam/icorem6/icorem6.c
 create mode 100644 configs/imx6qdl_icore_mmc_defconfig
 create mode 100644 include/configs/imx6qdl_icore.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index d851b26..5d549bd 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -95,6 +95,13 @@ config TARGET_MX6CUBOXI
 config TARGET_MX6QARM2
bool "mx6qarm2"
 
+config TARGET_MX6Q_ICORE
+   bool "Support Engicam i.Core"
+   select MX6QDL
+   select DM
+   select DM_THERMAL
+   select SUPPORT_SPL
+
 config TARGET_MX6QSABREAUTO
bool "mx6qsabreauto"
select DM
@@ -225,6 +232,7 @@ source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
+source "board/engicam/icorem6/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
diff --git a/arch/arm/include/asm/imx-common/sys_proto.h 
b/arch/arm/include/asm/imx-common/sys_proto.h
index 6ace8bb..005435a 100644
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -30,8 +30,10 @@
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || 
is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
+#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
 
diff --git a/board/engicam/icorem6/Kconfig b/board/engicam/icorem6/Kconfig
new file mode 100644
index 000..6d62f0e
--- /dev/null
+++ b/board/engicam/icorem6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6Q_ICORE
+
+config SYS_BOARD
+   default "icorem6"
+
+config SYS_VENDOR
+   default "engicam"
+
+config SYS_CONFIG_NAME
+   default "imx6qdl_icore"
+
+endif
diff --git a/board/engicam/icorem6/MAINTAINERS 
b/board/engicam/icorem6/MAINTAINERS
new file 

[U-Boot] [PATCH v8 05/23] net: Kconfig: Add FEC_MXC entry

[Jagan Teki]

From: Jagan Teki 

Added kconfig for FEC_MXC driver.

Cc: Joe Hershberger 
Cc: Simon Glass 
Cc: Fabio Estevam 
Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 drivers/net/Kconfig | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 302c005..7b9961d 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -129,6 +129,13 @@ config ETHOC
help
  This MAC is present in OpenRISC and Xtensa XTFPGA boards.
 
+config FEC_MXC
+   bool "FEC Ethernet controller"
+   depends on MX6
+   help
+ This driver supports the 10/100 Fast Ethernet controller for
+ NXP i.MX processors.
+
 config MVPP2
bool "Marvell Armada 375 network interface support"
depends on ARMADA_375
-- 
2.7.4

___
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[U-Boot] [PATCH v8 07/23] imx: s/docs\/README.imximage/doc\/README.imximage/g

[Jagan Teki]

From: Jagan Teki 

Fixed typo for doc/README.imximage on respective imximage.cfg files.

Cc: Tom Rini 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Acked-by: Peng Fan 
Signed-off-by: Jagan Teki 
---
 board/barco/titanium/imximage.cfg   | 2 +-
 board/ccv/xpress/imximage.cfg   | 2 +-
 board/denx/m53evk/imximage.cfg  | 2 +-
 board/freescale/mx6sabresd/mx6dlsabresd.cfg | 2 +-
 board/freescale/mx6slevk/imximage.cfg   | 2 +-
 board/freescale/mx6ullevk/imximage.cfg  | 2 +-
 board/freescale/mx7dsabresd/imximage.cfg| 2 +-
 board/freescale/s32v234evb/s32v234evb.cfg   | 2 +-
 board/freescale/vf610twr/imximage.cfg   | 2 +-
 board/phytec/pcm052/imximage.cfg| 2 +-
 board/technexion/pico-imx6ul/imximage.cfg   | 2 +-
 board/toradex/colibri_imx7/imximage.cfg | 2 +-
 board/toradex/colibri_vf/imximage.cfg   | 2 +-
 board/warp/imximage.cfg | 2 +-
 board/warp7/imximage.cfg| 2 +-
 15 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/board/barco/titanium/imximage.cfg 
b/board/barco/titanium/imximage.cfg
index 7219256..4fb6982 100644
--- a/board/barco/titanium/imximage.cfg
+++ b/board/barco/titanium/imximage.cfg
@@ -7,7 +7,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/ccv/xpress/imximage.cfg b/board/ccv/xpress/imximage.cfg
index 92167c9..d98bc36 100644
--- a/board/ccv/xpress/imximage.cfg
+++ b/board/ccv/xpress/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/denx/m53evk/imximage.cfg b/board/denx/m53evk/imximage.cfg
index 4cd002c..c0e2602 100644
--- a/board/denx/m53evk/imximage.cfg
+++ b/board/denx/m53evk/imximage.cfg
@@ -4,7 +4,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg 
b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
index f35f22e..be9f87f 100644
--- a/board/freescale/mx6sabresd/mx6dlsabresd.cfg
+++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6slevk/imximage.cfg 
b/board/freescale/mx6slevk/imximage.cfg
index c77bbde..024de9c 100644
--- a/board/freescale/mx6slevk/imximage.cfg
+++ b/board/freescale/mx6slevk/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6ullevk/imximage.cfg 
b/board/freescale/mx6ullevk/imximage.cfg
index 4604b62..3ae4912 100644
--- a/board/freescale/mx6ullevk/imximage.cfg
+++ b/board/freescale/mx6ullevk/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx7dsabresd/imximage.cfg 
b/board/freescale/mx7dsabresd/imximage.cfg
index 76574ff..c2b3a8c 100644
--- a/board/freescale/mx7dsabresd/imximage.cfg
+++ b/board/freescale/mx7dsabresd/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/s32v234evb/s32v234evb.cfg 
b/board/freescale/s32v234evb/s32v234evb.cfg
index 6017a40..6449ef2 100644
--- a/board/freescale/s32v234evb/s32v234evb.cfg
+++ b/board/freescale/s32v234evb/s32v234evb.cfg
@@ -5,7 +5,7 @@
  */
 
 /*
- * 

[U-Boot] [PATCH v8 06/23] imx6: icorem6: Add ENET support

[Jagan Teki]

From: Jagan Teki 

Add enet support for engicam icorem6 qdl starter kit.
- Add pinmux settings
- Add board_eth_init

TFTP log:

Net:   FEC [PRIME]
Hit any key to stop autoboot:  0
icorem6qdl> tftpboot {fdt_addr} imx6dl-icore.dtb
Using FEC device
TFTP from server 192.168.2.96; our IP address is 192.168.2.75
Filename 'imx6dl-icore.dtb'.
Load address: 0x0
Loading: ##
 1.3 MiB/s
done
Bytes transferred = 28976 (7130 hex)
CACHE: Misaligned operation at range [, 7130]
icorem6qdl>

Cc: Joe Hershberger 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
Acked-by: Joe Hershberger 
---
 board/engicam/icorem6/icorem6.c | 72 +
 configs/imx6qdl_icore_mmc_defconfig |  4 +++
 include/configs/imx6qdl_icore.h | 12 +++
 3 files changed, 88 insertions(+)

diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index 1856972..a23cb7e 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -9,12 +9,15 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include 
 #include 
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -30,11 +33,28 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |   \
PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |\
+   PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
+   PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
 static iomux_v3_cfg_t const uart4_pads[] = {
IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
+static iomux_v3_cfg_t const enet_pads[] = {
+   IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL | 
PAD_CTL_SRE_FAST)),
+   IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+   IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
 static iomux_v3_cfg_t const usdhc1_pads[] = {
IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -99,6 +119,58 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_FEC_MXC
+#define ENET_PHY_RST   IMX_GPIO_NR(7, 12)
+static int setup_fec(void)
+{
+   struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+   struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+   s32 timeout = 10;
+   u32 reg = 0;
+   int ret;
+
+   /* Enable fec clock */
+   setbits_le32(>CCGR1, MXC_CCM_CCGR1_ENET_MASK);
+
+   /* use 50MHz */
+   ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+   if (ret)
+   return ret;
+
+   /* Enable PLLs */
+   reg = readl(>pll_enet);
+   reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
+   writel(reg, >pll_enet);
+   reg = readl(>pll_enet);
+   reg |= BM_ANADIG_PLL_SYS_ENABLE;
+   while (timeout--) {
+   if (readl(>pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
+   break;
+   }
+   if (timeout <= 0)
+   return -EIO;
+   reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
+   writel(reg, >pll_enet);
+
+   /* reset the phy */
+   gpio_direction_output(ENET_PHY_RST, 0);
+   udelay(1);
+   gpio_set_value(ENET_PHY_RST, 1);
+
+   return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+   int ret;
+
+   SETUP_IOMUX_PADS(enet_pads);
+   setup_fec();
+
+   return ret = cpu_eth_init(bis);
+}
+#endif
+
 int board_early_init_f(void)
 {
SETUP_IOMUX_PADS(uart4_pads);
diff --git a/configs/imx6qdl_icore_mmc_defconfig 
b/configs/imx6qdl_icore_mmc_defconfig
index ced6b10..c2c2fe8 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -14,6 +14,8 @@ CONFIG_SYS_MAXARGS=32
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_CACHE=y
@@ -23,7 +25,9 @@ CONFIG_CMD_EXT4_WRITE=y
 

[U-Boot] [PATCH v8 03/23] config: Move CONFIG_DEFAULT_FDT_FILE to defconfigs

[Jagan Teki]

From: Jagan Teki 

- Add DEFAULT_FDT_FILE kconfig entry
- Move CONFIG_DEFAULT_FDT_FILE from include/configs to defconfigs

Cc: Tom Rini 
Cc: Simon Glass 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 common/Kconfig   | 5 +
 configs/dms-ba16-1g_defconfig| 1 +
 configs/dms-ba16_defconfig   | 1 +
 configs/ge_b450v3_defconfig  | 1 +
 configs/ge_b650v3_defconfig  | 1 +
 configs/ge_b850v3_defconfig  | 1 +
 configs/mx25pdk_defconfig| 1 +
 configs/mx53ard_defconfig| 1 +
 configs/pico-imx6ul_defconfig| 1 +
 configs/tqma6q_mba6_mmc_defconfig| 1 +
 configs/tqma6q_mba6_spi_defconfig| 1 +
 configs/tqma6s_mba6_mmc_defconfig| 1 +
 configs/tqma6s_mba6_spi_defconfig| 1 +
 configs/tqma6s_wru4_mmc_defconfig| 1 +
 configs/zc5202_defconfig | 1 +
 configs/zc5601_defconfig | 1 +
 include/configs/advantech_dms-ba16.h | 1 -
 include/configs/ge_bx50v3.h  | 4 
 include/configs/mx25pdk.h| 2 --
 include/configs/mx53ard.h| 2 --
 include/configs/pico-imx6ul.h| 2 --
 include/configs/tqma6_mba6.h | 6 --
 include/configs/tqma6_wru4.h | 2 --
 include/configs/zc5202.h | 2 --
 include/configs/zc5601.h | 2 --
 25 files changed, 20 insertions(+), 23 deletions(-)

diff --git a/common/Kconfig b/common/Kconfig
index 1198f26..6d835ca 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -203,6 +203,11 @@ config IDENT_STRING
help
  This options adds the board specific name to u-boot version.
 
+config DEFAULT_FDT_FILE
+   string "Default fdt file"
+   help
+ This option is used to set the default fdt file to boot OS.
+
 config SYS_NO_FLASH
bool "Disable support for parallel NOR flash"
default n
diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig
index db5adcf..8e26837 100644
--- a/configs/dms-ba16-1g_defconfig
+++ b/configs/dms-ba16-1g_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_ADVANTECH_DMS_BA16=y
+CONFIG_DEFAULT_FDT_FILE="imx6q-dms-ba16.dtb"
 CONFIG_SYS_DDR_1G=y
 CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig
index e36f3dc..fec0a1c 100644
--- a/configs/dms-ba16_defconfig
+++ b/configs/dms-ba16_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_ADVANTECH_DMS_BA16=y
+CONFIG_DEFAULT_FDT_FILE="imx6q-dms-ba16.dtb"
 CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index 8577167..4a5322d 100644
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B450V3=y
+CONFIG_DEFAULT_FDT_FILE="/boot/imx6q-b450v3.dtb"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index c5f391e..ecf4449 100644
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B650V3=y
+CONFIG_DEFAULT_FDT_FILE="/boot/imx6q-b650v3.dtb"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index 2c5aa05..004c9d0 100644
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B850V3=y
+CONFIG_DEFAULT_FDT_FILE="/boot/imx6q-b850v3.dtb"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
index b4afb05..c3ab7c2 100644
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX25PDK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx25-pdk.dtb"
 CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index 7a62c2b..fe0f106 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53ARD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx53-ard.dtb"
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index 1aaf868..dba67bb 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6ul/imximage.cfg"

[U-Boot] [PATCH v8 02/23] thermal: Kconfig: Add IMX_THERMAL entry

[Jagan Teki]

From: Jagan Teki 

Added kconfig for IMX_THERMAL driver.

Cc: Simon Glass 
Cc: Fabio Estevam 
Cc: Stefano Babic 
Cc: Peng Fan 
Cc: Matteo Lisi 
Cc: Michael Trimarchi 
Signed-off-by: Jagan Teki 
---
 drivers/thermal/Kconfig | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 8e22ea7..f0ffbb3 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -5,3 +5,16 @@ config DM_THERMAL
  temperature sensors to permit warnings, speed throttling or even
  automatic power-off when the temperature gets too high or low. Other
  devices may be discrete but connected on a suitable bus.
+
+if DM_THERMAL
+
+config IMX_THERMAL
+   bool "Temperature sensor driver for Freescale i.MX SoCs"
+   depends on MX6
+   help
+ Support for Temperature Monitor (TEMPMON) found on Freescale i.MX 
SoCs.
+  It supports one critical trip point and one passive trip point.  The
+  cpufreq is used as the cooling device to throttle CPUs when the
+  passive trip is crossed.
+
+endif # if DM_THERMAL
-- 
2.7.4

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