Re: [U-Boot] [PATCH v1 3/3] spi: mxs_spi: DM conversion

[Jagan Teki]

+ add relevant board maintainers

On Thu, Apr 26, 2018 at 10:20 PM, Akash Gajjar  wrote:
> This patch adds support for DM to the mxs spi driver.
>
> Some TODOs are left over for later, These would be enhancements to the
> original functionality, and can come later.
>
> The legacy functionality is present in this version, so old boards in the tree
> is working with legacy SPI driver functionality.
>
> Signed-off-by: Akash Gajjar 
> ---
>  drivers/spi/Kconfig|  12 +-
>  drivers/spi/mxs_spi.c  | 257 
> +++--
>  include/dm/platform_data/spi_mxs.h |  18 +++
>  3 files changed, 186 insertions(+), 101 deletions(-)
>  create mode 100644 include/dm/platform_data/spi_mxs.h
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index ec92b84..5d3e152 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -106,6 +106,12 @@ config MVEBU_A3700_SPI
>   used to access the SPI NOR flash on platforms embedding this
>   Marvell IP core.
>
> +config MXS_SPI
> +   bool "MXS SPI Driver"
> +   help
> + Enable the MXS SPI controller driver. This driver can be used
> + on the i.MX23 and i.MX28 SoCs.
> +
>  config PIC32_SPI
> bool "Microchip PIC32 SPI driver"
> depends on MACH_PIC32
> @@ -299,12 +305,6 @@ config MXC_SPI
>   Enable the MXC SPI controller driver. This driver can be used
>   on various i.MX SoCs such as i.MX31/35/51/6/7.
>
> -config MXS_SPI
> -   bool "MXS SPI Driver"
> -   help
> - Enable the MXS SPI controller driver. This driver can be used
> - on the i.MX23 and i.MX28 SoCs.
> -
>  config OMAP3_SPI
> bool "McSPI driver for OMAP"
> help
> diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
> index 790db78..b48ecbf 100644
> --- a/drivers/spi/mxs_spi.c
> +++ b/drivers/spi/mxs_spi.c
> @@ -1,6 +1,9 @@
>  /*
>   * Freescale i.MX28 SPI driver
>   *
> + * Support for device model:
> + * Copyright (C) 2018 Akash Gajjar 
> + *
>   * Copyright (C) 2011 Marek Vasut 
>   * on behalf of DENX Software Engineering GmbH
>   *
> @@ -20,6 +23,8 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>
>  #defineMXS_SPI_MAX_TIMEOUT 100
>  #defineMXS_SPI_PORT_OFFSET 0x2000
> @@ -28,93 +33,14 @@
>
>  #define MXSSSP_SMALL_TRANSFER  512
>
> -struct mxs_spi_slave {
> -   struct spi_slaveslave;
> -   uint32_tmax_khz;
> -   uint32_tmode;
> -   struct mxs_ssp_regs *regs;
> +struct mxs_spi_priv {
> +   struct mxs_ssp_regs *regs;
> +   u32 max_khz;
> +   u32 mode;
> +   u32 bus;
> +   u32 cs;

I think we can't maintain this private structure since we have
platdata both in DT and PLATDATA. just assign regs to plat->regs or
any other members.

>  };
>
> -static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
> -{
> -   return container_of(slave, struct mxs_spi_slave, slave);
> -}
> -
> -void spi_init(void)
> -{
> -}
> -
> -int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> -{
> -   /* MXS SPI: 4 ports and 3 chip selects maximum */
> -   if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
> -   return 0;
> -   else
> -   return 1;
> -}

No, we need to maintain this with .cs_info

> -
> -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> - unsigned int max_hz, unsigned int mode)
> -{
> -   struct mxs_spi_slave *mxs_slave;
> -
> -   if (!spi_cs_is_valid(bus, cs)) {
> -   printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
> -   return NULL;
> -   }
> -
> -   mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
> -   if (!mxs_slave)
> -   return NULL;
> -
> -   if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
> -   goto err_init;
> -
> -   mxs_slave->max_khz = max_hz / 1000;
> -   mxs_slave->mode = mode;
> -   mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
> -
> -   return &mxs_slave->slave;
> -
> -err_init:
> -   free(mxs_slave);
> -   return NULL;
> -}
> -
> -void spi_free_slave(struct spi_slave *slave)
> -{
> -   struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
> -   free(mxs_slave);
> -}
> -
> -int spi_claim_bus(struct spi_slave *slave)
> -{
> -   struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
> -   struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
> -   uint32_t reg = 0;
> -
> -   mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
> -
> -   writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
> -  SSP_CTRL0_BUS_WIDTH_ONE_BIT,
> -  &ssp_regs->hw_ssp_ctrl0);
> -
> -   reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
> -   reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
> -   reg |= (mxs_slave->mo

Re: [U-Boot] [PATCH v1 2/3] spi: sh_spi: DM conversion

[Jagan Teki]

+ add relevant board mainatiners

On Thu, Apr 26, 2018 at 10:18 PM, Akash Gajjar  wrote:
> This patch adds support for DM to the sh_spi driver. legacy driver support is
> removed.
>
> Some TODOs are left over for later, These would be enhancements to the
> original functionality, and can come later. The legacy functionality is
> removed in this version.
>
> This patch is not tested on board as well compile tested yet.
>
> Signed-off-by: Akash Gajjar 
> ---
>  drivers/spi/Kconfig   |  12 +--
>  drivers/spi/sh_spi.c  | 214 
> +-
>  drivers/spi/sh_spi.h  |   3 +-
>  include/dm/platform_data/spi_sh.h |  20 
>  4 files changed, 147 insertions(+), 102 deletions(-)
>  create mode 100644 include/dm/platform_data/spi_sh.h
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index ec92b84..be6ad22 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -155,6 +155,12 @@ config SANDBOX_SPI
> };
>   };
>
> +config SH_SPI
> +   bool "SuperH SPI driver"
> +   help
> + Enable the SuperH SPI controller driver. This driver can be used
> + on various SuperH SoCs, such as SH7757.
> +
>  config STM32_QSPI
> bool "STM32F7 QSPI driver"
> depends on STM32F7
> @@ -253,12 +259,6 @@ config DAVINCI_SPI
> help
>   Enable the Davinci SPI driver
>
> -config SH_SPI
> -   bool "SuperH SPI driver"
> -   help
> - Enable the SuperH SPI controller driver. This driver can be used
> - on various SuperH SoCs, such as SH7757.
> -
>  config SH_QSPI
> bool "Renesas Quad SPI driver"
> help
> diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
> index fe394e3..b308ec8 100644
> --- a/drivers/spi/sh_spi.c
> +++ b/drivers/spi/sh_spi.c
> @@ -1,6 +1,10 @@
>  /*
>   * SH SPI driver
>   *
> + * Support for device model:
> + * Copyright (C) 2018  Akash Gajjar 
> + * Harshit Shah 
> + *
>   * Copyright (C) 2011-2012 Renesas Solutions Corp.
>   *
>   * SPDX-License-Identifier:GPL-2.0
> @@ -11,6 +15,8 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>  #include "sh_spi.h"
>
>  static void sh_spi_write(unsigned long data, unsigned long *reg)
> @@ -41,15 +47,15 @@ static void sh_spi_clear_bit(unsigned long val, unsigned 
> long *reg)
> sh_spi_write(tmp, reg);
>  }
>
> -static void clear_fifo(struct sh_spi *ss)
> +static void clear_fifo(struct sh_spi_regs *regs)
>  {
> -   sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
> -   sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
> +   sh_spi_set_bit(SH_SPI_RSTF, ®s->cr2);
> +   sh_spi_clear_bit(SH_SPI_RSTF, ®s->cr2);
>  }
>
> -static int recvbuf_wait(struct sh_spi *ss)
> +static int recvbuf_wait(struct sh_spi_regs *regs)
>  {
> -   while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
> +   while (sh_spi_read(®s->cr1) & SH_SPI_RBE) {
> if (ctrlc())
> return 1;
> udelay(10);
> @@ -57,9 +63,9 @@ static int recvbuf_wait(struct sh_spi *ss)
> return 0;
>  }
>
> -static int write_fifo_empty_wait(struct sh_spi *ss)
> +static int write_fifo_empty_wait(struct sh_spi_regs *regs)
>  {
> -   while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
> +   while (!(sh_spi_read(®s->cr1) & SH_SPI_TBE)) {
> if (ctrlc())
> return 1;
> udelay(10);
> @@ -67,11 +73,7 @@ static int write_fifo_empty_wait(struct sh_spi *ss)
> return 0;
>  }
>
> -void spi_init(void)
> -{
> -}
> -
> -static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
> +static void sh_spi_set_cs(struct sh_spi_regs *regs, unsigned int cs)
>  {
> unsigned long val = 0;
>
> @@ -80,85 +82,53 @@ static void sh_spi_set_cs(struct sh_spi *ss, unsigned int 
> cs)
> if (cs & 0x02)
> val |= SH_SPI_SSS1;
>
> -   sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
> -   sh_spi_set_bit(val, &ss->regs->cr4);
> +   sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, ®s->cr4);
> +   sh_spi_set_bit(val, ®s->cr4);
>  }
>
> -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> -   unsigned int max_hz, unsigned int mode)
> +static void __spi_setup(struct sh_spi_regs *regs, uint cs)
>  {
> -   struct sh_spi *ss;
> -
> -   if (!spi_cs_is_valid(bus, cs))
> -   return NULL;
> -
> -   ss = spi_alloc_slave(struct sh_spi, bus, cs);
> -   if (!ss)
> -   return NULL;
> -
> -   ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
> -
> +   /* initialize spi */
> +   regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;

wrong, we have plat->regs

> /* SPI sycle stop */
> -   sh_spi_write(0xfe, &ss->regs->cr1);
> +   sh_spi_write(0xfe, ®s->cr1);
> /* CR1 init */
> -   sh_spi_write(0x00, &ss->regs->cr1);
> +   sh_spi_write(0x00, ®s

Re: [U-Boot] [PATCH v1 1/3] spi: sh_qspi: DM conversion

[Jagan Teki]

On Thu, Apr 26, 2018 at 10:16 PM, Akash Gajjar  wrote:
> This patch adds support for DM to the sh_qspi SPI driver.
>
> The legacy functionality is removed in this version, so old boards in
> the tree is not working with legacy SPI driver functionality.
> Some TODOs are left over for later, These would be enhancements to the
> original functionality, and can come later.
>
> This patch is not tested on board as well compile tested yet.
>
> Signed-off-by: Akash Gajjar 
> ---
>  drivers/spi/sh_qspi.c  | 199 
> ++---
>  include/dm/platform_data/qspi_sh.h |  20 
>  2 files changed, 119 insertions(+), 100 deletions(-)
>  create mode 100644 include/dm/platform_data/qspi_sh.h
>
> diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
> index 5075be3..5fdd52e 100644
> --- a/drivers/spi/sh_qspi.c
> +++ b/drivers/spi/sh_qspi.c
> @@ -1,6 +1,10 @@
>  /*
>   * SH QSPI (Quad SPI) driver
>   *
> + * Support for device model:
> + * Copyright (C) 2018 Akash Gajjar 
> + *   Harshit Shah 
> + *
>   * Copyright (C) 2013 Renesas Electronics Corporation
>   * Copyright (C) 2013 Nobuhiro Iwamatsu 
>   *
> @@ -14,6 +18,8 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>
>  /* SH QSPI register bit masks _ */
>  #define SPCR_MSTR  0x08
> @@ -67,151 +73,90 @@ struct sh_qspi_regs {
> u32 spbmul3;
>  };
>
> -struct sh_qspi_slave {
> -   struct spi_slaveslave;
> -   struct sh_qspi_regs *regs;
> +struct sh_qspi_priv {
> +   struct sh_qspi_regs *regs;
>  };
>
> -static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
> -{
> -   return container_of(slave, struct sh_qspi_slave, slave);
> -}
> -
> -static void sh_qspi_init(struct sh_qspi_slave *ss)
> +static int __sh_qspi_setup(struct sh_qspi_priv *priv)

Use the old function name, it has meaning on it like sh hw init.

>  {
> /* QSPI initialize */
> +   priv->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
> +
> /* Set master mode only */
> -   writeb(SPCR_MSTR, &ss->regs->spcr);
> +   writeb(SPCR_MSTR, &priv->regs->spcr);
>
> /* Set SSL signal level */
> -   writeb(0x00, &ss->regs->sslp);
> +   writeb(0x00, &priv->regs->sslp);
>
> /* Set MOSI signal value when transfer is in idle state */
> -   writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
> +   writeb(SPPCR_IO3FV | SPPCR_IO2FV, &priv->regs->sppcr);
>
> /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
> -   writeb(0x01, &ss->regs->spbr);
> +   writeb(0x01, &priv->regs->spbr);
>
> /* Disable Dummy Data Transmission */
> -   writeb(0x00, &ss->regs->spdcr);
> +   writeb(0x00, &priv->regs->spdcr);
>
> /* Set clock delay value */
> -   writeb(0x00, &ss->regs->spckd);
> +   writeb(0x00, &priv->regs->spckd);
>
> /* Set SSL negation delay value */
> -   writeb(0x00, &ss->regs->sslnd);
> +   writeb(0x00, &priv->regs->sslnd);
>
> /* Set next-access delay value */
> -   writeb(0x00, &ss->regs->spnd);
> +   writeb(0x00, &priv->regs->spnd);
>
> /* Set equence command */
> -   writew(SPCMD_INIT2, &ss->regs->spcmd0);
> +   writew(SPCMD_INIT2, &priv->regs->spcmd0);
>
> /* Reset transfer and receive Buffer */
> -   setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
> +   setbits_8(&priv->regs->spbfcr, SPBFCR_TXRST | SPBFCR_RXRST);
>
> /* Clear transfer and receive Buffer control bit */
> -   clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
> +   clrbits_8(&priv->regs->spbfcr, SPBFCR_TXRST | SPBFCR_RXRST);
>
> /* Set equence control method. Use equence0 only */
> -   writeb(0x00, &ss->regs->spscr);
> +   writeb(0x00, &priv->regs->spscr);
>
> /* Enable SPI function */
> -   setbits_8(&ss->regs->spcr, SPCR_SPE);
> -}
> -
> -int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> -{
> -   return 1;
> -}
> -
> -void spi_cs_activate(struct spi_slave *slave)
> -{
> -   struct sh_qspi_slave *ss = to_sh_qspi(slave);
> -
> -   /* Set master mode only */
> -   writeb(SPCR_MSTR, &ss->regs->spcr);
> -
> -   /* Set command */
> -   writew(SPCMD_INIT1, &ss->regs->spcmd0);
> -
> -   /* Reset transfer and receive Buffer */
> -   setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
> -
> -   /* Clear transfer and receive Buffer control bit */
> -   clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
> -
> -   /* Set equence control method. Use equence0 only */
> -   writeb(0x00, &ss->regs->spscr);
> -
> -   /* Enable SPI function */
> -   setbits_8(&ss->regs->spcr, SPCR_SPE);
> -}
> -
> -void spi_cs_deactivate(struct spi_slave *slave)
> -{
> -   struct sh_qspi_slave *ss = to_sh_qspi(slave);
> -
> -   /* Disable SPI Function */
> -   clrbits_8(&ss->regs->spcr, SPCR_SPE);
> -}
> -
> -void spi_init(void)
> -{
> -  

Re: [U-Boot] [PATCH] tools: zynqmpbif: Add support for load=after

[Michal Simek]

On 26.4.2018 18:46, Alexander Graf wrote:
> On 04/26/2018 06:33 PM, Michal Simek wrote:
>> On 26.4.2018 13:37, Alexander Graf wrote:
>>> Some times it's handy to have a partition loaded immediately after
>>> the end of the previous blob. The most obvious example for this is
>>> a U-Boot binary (coming from .elf) and a device tree file.
>>>
>>> This patch adds that logic. With this, the following bif snippet
>>> does what you would expect:
>>>
>>>    [destination_cpu=a5x-0, exception_level=el-2] u-boot.elf
>>>    [load=after] u-boot.dtb
>>>
>>> converts to
>>>
>>>    FSBL payload on CPU a5x-0 (PS):
>>>  Offset : 0x00590500
>>>  Size   : 577768 (0x8d0e8) bytes
>>>  Load   : 0x0800
>>>  Attributes : EL2
>>>  Checksum   : 0xefca2cad
>>>    FSBL payload on CPU none (PS):
>>>  Offset : 0x0061d640
>>>  Size   : 129760 (0x1fae0) bytes
>>>  Load   : 0x0808d0e8 (entry=0x)
>>>  Attributes : EL3
>>>  Checksum   : 0xf7dd3d49
>>>
>>> Signed-off-by: Alexander Graf 
>>> ---
>>>   tools/zynqmpbif.c | 15 +++
>>>   1 file changed, 15 insertions(+)
>>>
>>> diff --git a/tools/zynqmpbif.c b/tools/zynqmpbif.c
>>> index 6c8f66055d..47c233c15f 100644
>>> --- a/tools/zynqmpbif.c
>>> +++ b/tools/zynqmpbif.c
>>> @@ -42,6 +42,7 @@ enum bif_flag {
>>>   BIF_FLAG_PUF_FILE,
>>>   BIF_FLAG_AARCH32,
>>>   BIF_FLAG_PART_OWNER_UBOOT,
>>> +    BIF_FLAG_LOAD_AFTER,
>>>     /* Internal flags */
>>>   BIF_FLAG_BIT_FILE,
>>> @@ -151,6 +152,11 @@ static char *parse_load(char *line, struct
>>> bif_entry *bf)
>>>   {
>>>   char *endptr;
>>>   +    if (!strncmp(line, "after", strlen("after"))) {
>>> +    bf->flags |= (1ULL << BIF_FLAG_LOAD_AFTER);
>>> +    return line + strlen("after");
>>> +    }
>>> +
>>>   bf->load = strtoll(line, &endptr, 0);
>>>     return endptr;
>>> @@ -336,6 +342,15 @@ static int bif_add_part(struct bif_entry *bf,
>>> const char *data, size_t len)
>>>   if (r)
>>>   return r;
>>>   +    if (bf->flags & (1ULL << BIF_FLAG_LOAD_AFTER) &&
>>> +    bif_output.last_part) {
>>> +    struct partition_header *p = bif_output.last_part;
>>> +    uint64_t load = le64_to_cpu(p->load_address);
>>> +
>>> +    load += le32_to_cpu(p->len) * 4;
>>> +    parthdr.load_address = cpu_to_le64(load);
>>> +    }
>>> +
>>>   parthdr.offset = cpu_to_le32(bf->offset / 4);
>>>     if (bf->flags & (1ULL << BIF_FLAG_BOOTLOADER)) {
>>>
>> As we have discussed over IRC this is out of current bif supported
>> options and load option with OF_SEPARATE/OF_BOARD should be used instead.
>> Some platforms are using CONFIG_SYS_FDT_BASE for that.
>> Generic solution for that would be good because right now is fdt_blob is
>> at &_end.
> 
> Yes, the &_end is what this patch enables to map in bif.
> 
>> At least like this.
>>
>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>> index 320ee1dc56b3..4262ac0677d3 100644
>> --- a/lib/fdtdec.c
>> +++ b/lib/fdtdec.c
>> @@ -1292,8 +1292,12 @@ __weak void *board_fdt_blob_setup(void)
>>  else
>>  fdt_blob = (ulong *)&__bss_end;
>>   #else
>> +#ifndef CONFIG_SYS_FDT_BASE
>>  /* FDT is at end of image */
>>  fdt_blob = (ulong *)&_end;
>> +#else
>> +   fdt_blob = CONFIG_SYS_FDT_BASE;
>> +#endif
> 
> I agree that this is an alternative approach to this, but I like it much
> less :). It just feels wrong to hard code random addresses to load
> things from when everything is easy enough to pull out dynamically.
> 
> I'd much rather prefer to extend the official bif syntax with this. If
> we can't have that, I guess the next "best" option is to just create a
> combined .bin file and manually set the load/entry address from the elf
> header in my boot.bin generation script.

I don't think this is going to happen for zynqmp and will see what can
be done for next gen. But my guess is that chance is quite low.

That's how it is done for OF_SEPARATE today
  cat u-boot-nodtb.bin dts/dt.dtb > u-boot-dtb.bin
  cp u-boot-dtb.bin u-boot.bin

It means the same will be in your script.

Thanks,
Michal



> 
> 
> Alex
> 

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Re: [U-Boot] [PATCH 2/2] spi: kirkwood: Full dm conversion

[Stefan Roese]

Hi Chris,

On 27.04.2018 00:45, Chris Packham wrote:

On 26/04/18 18:00, Jagan Teki wrote:

On Thu, Mar 15, 2018 at 5:03 PM, Jagan Teki  wrote:

kirkwood now support dt along with platform data,
respective boards need to switch into dm for the same.


Added all board mainatiner, using this driver on their relevant
boards. So try to switch to DM_SPI(SPI_FLASH) before migration
deadline expires.

Jagan.


Hopefully I can get to db88f6820-amc next week.

Stefan, did you want me to send a patch for db88f6820-gp at the same
time since the amc board is derived from it?


Sure, that would be helpful.

But I'm a little bit puzzled about this DM conversion for MVEBU
platforms. As all MVEBU targets are already using DM and DM_SPI:

arch/arm/Kconfig:

...
config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
select OF_CONTROL
select OF_SEPARATE
select DM
select DM_ETH
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH

So there should be no need to change something here. Or is something
not working correctly on some of the MVEBU platforms?

What really is missing is the conversion of the older Marvell
platforms, like Kirkwood and Orion. Those are quite ancient and
have no DM / OF / DT support at all (AFAIR). So here is the real
work that needs to be done. Or all those boards might get dropped
soon.

Thanks,
Stefan
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Re: [U-Boot] [PATCH][v2] mtd: nand: fsl_ifc: Fix nand waitfunc return value

[York Sun]

> On Apr 26, 2018, at 19:58, Prabhakar Kushwaha  
> wrote:
>> 



> 
> Even though there are 2 bytes. 
> But NAND sub-system only consume 1 byte because all NAND flash has 1 byte 
> status register. 
> 

Then the commit message should describe the position of primary status field, 
instead of saying two bytes.

York

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Re: [U-Boot] [PATCH][v2] mtd: nand: fsl_ifc: Fix nand waitfunc return value

[Prabhakar Kushwaha]

Hi York,

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of York Sun
> Sent: Friday, April 27, 2018 2:31 AM
> To: Jagdish Gediya ; u-boot@lists.denx.de
> Cc: o...@buserror.net
> Subject: Re: [U-Boot] [PATCH][v2] mtd: nand: fsl_ifc: Fix nand waitfunc
> return value
> 
> On 03/20/2018 10:24 PM, Jagdish Gediya wrote:
> > As per the IFC hardware manual, Most significant 2 bytes in nand_fsr
> > register are the outcome of NAND READ STATUS command.
> >
> > So status value need to be shifted and aligned as per the nand
> > framework requirement.
> >
> > Signed-off-by: Jagdish Gediya 
> > Reviewed-by: Prabhakar Kushwaha 
> > ---
> > Changes for v2:
> > - Change the waitfunc return value according to semantic
> >   enforced by framework.
> >
> >  drivers/mtd/nand/fsl_ifc_nand.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/fsl_ifc_nand.c
> > b/drivers/mtd/nand/fsl_ifc_nand.c index 6eb44c3..7f487e7 100644
> > --- a/drivers/mtd/nand/fsl_ifc_nand.c
> > +++ b/drivers/mtd/nand/fsl_ifc_nand.c
> > @@ -701,6 +701,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct
> nand_chip *chip)
> > struct fsl_ifc_ctrl *ctrl = priv->ctrl;
> > struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
> > u32 nand_fsr;
> > +   int status;
> >
> > if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
> > return NAND_STATUS_FAIL;
> > @@ -721,10 +722,10 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct
> nand_chip *chip)
> > return NAND_STATUS_FAIL;
> >
> > nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
> > +   status = nand_fsr >> 24;
> >
> 
> You said most significant 2 bytes are the outcome, and you shift 24 bits. Did
> you intentionally use one byte?
> 

Even though there are 2 bytes. 
But NAND sub-system only consume 1 byte because all NAND flash has 1 byte 
status register. 

--pk  


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Re: [U-Boot] Hang while booting kernel via tftp/nfs on cubieboard2

[Ajay Garg]

Seems setting bootargs is not legal in bootz command, so segregated the two.
However, the end-result is same as in my original email.


tftp 0x4900 sun7i-a20-cubieboard2.dtb

tftp 0x4600 zImage-Cubieboard2

setenv bootargs console=ttyS0,115200 root=/dev/nfs
nfsroot=192.168.0.1:/srv/nfs/cubieboard2,nfsvers=3
ip=192.168.0.2:192.168.0.1::255.255.255.0:cubieboard2 ignore_loglevel
cma=128M

bootz 0x4600 - 0x4900

On Fri, Apr 27, 2018 at 7:39 AM, Ajay Garg  wrote:
> Hi All.
>
>
> a)
> As a pre-requisite, on the host-machine (serverip 192.168.0.1), the
> nfs-export is listed fine :
>
> ajay@latitude-3480:~showmount -e localhost
> Export list for localhost:
> /srv/nfs/cubieboard2 *
>
>
> b)
> The zImage and dtb files have been generated from 4.6 kernel, as per steps at
> https://github.com/maronai/cubieboard/wiki/3.1.-Compiling-mainline-kernel-for-CubieBoard2-and-CubieTruck
>
>
> Now, when trying to boot cubieboard2 via tftp/nfs, I get a hang, all
> details as below :
>
> ###
> U-Boot SPL 2017.01-2 (Jan 18 2017 - 21:30:38)
> DRAM: 1024 MiB
> CPU: 91200Hz, AXI/AHB/APB: 3/2/2
> Trying to boot from MMC1
>
> U-Boot 2017.01-2 (Jan 18 2017 - 21:30:38 -0700) Arch Linux ARM
>
> CPU:   Allwinner A20 (SUN7I)
> Model: Cubietech Cubieboard2
> I2C:   ready
> DRAM:  1 GiB
> MMC:   SUNXI SD/MMC: 0
> In:serial
> Out:   serial
> Err:   serial
> SCSI:  SATA link 0 timeout.
> AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
> flags: ncq stag pm led clo only pmp pio slum part ccc apst
> Net:   eth0: ethernet@01c5
> Hit any key to stop autoboot:  0
>
> => printenv
> autoboot=run loadkernel && run setargs && true && bootm 0x4800
> baudrate=115200
> boot_ram=saved_stdout=$stdout;setenv stdout nc;if iminfo 0x4100;
> then true; setenv stdout $saved_stdout; source 0x4100;else setenv
> stdi
> bootcmd=if run loadbootenv; then echo Loaded environment from
> ${bootenv};env import -t ${scriptaddr} ${filesize};fi;if test -n
> "${uenvcmd}"; t;
> bootdelay=3
> bootenv=uEnv.txt
> bootscr=boot.scr
> console=ttyS0,115200
> device=mmc
> ethact=ethernet@01c5
> ethaddr=12:34:56:78:90:ab
> fdtcontroladdr=7af2e820
> ipaddr=192.168.0.2
> kernel=uImage
> loadbootenv=fatload $device $partition $scriptaddr ${bootenv} ||
> ext2load $device $partition $scriptaddr boot/${bootenv} || ext2load
> $device $}
> loadbootscr=fatload $device $partition $scriptaddr ${bootscr} ||
> ext2load $device $partition $scriptaddr boot/${bootscr} ||ext2load
> $device $p}
> loadkernel=if bootpath=/boot/ && ext2load $device $partition
> 0x4300 ${bootpath}script.bin && ext2load $device $partition
> 0x4800 ${booti
> loglevel=8
> panicarg=panic=10
> partition=0:1
> scriptaddr=0x4400
> serial#=1651660f06c3457c
> serverip=192.168.0.1
> setargs=if test -z \\"$root\\"; then if test \\"$bootpath\\" =
> "/boot/"; then root="/dev/mmcblk0p1 rootwait"; else
> root="/dev/mmcblk0p2 rootwa}
> stderr=serial
> stdin=serial
> stdout=serial
>
> Environment size: 1979/131068 bytes
>
> => tftp 0x4900 sun7i-a20-cubieboard2.dtb
> Speed: 100, full duplex
> Using ethernet@01c5 device
> TFTP from server 192.168.0.1; our IP address is 192.168.0.2
> Filename 'sun7i-a20-cubieboard2.dtb'.
> Load address: 0x4900
> Loading: ###
>  4 MiB/s
> done
> Bytes transferred = 29537 (7361 hex)
>
> => tftp 0x4600 zImage-Cubieboard2
> Speed: 100, full duplex
> Using ethernet@01c5 device
> TFTP from server 192.168.0.1; our IP address is 192.168.0.2
> Filename 'zImage-Cubieboard2'.
> Load address: 0x4600
> Loading: #
>  #
>  #
>  
>  4.6 MiB/s
> done
> Bytes transferred = 3388416 (33b400 hex)
>
> => bootz 0x4600 - 0x4900 console=ttyS0,115200 root=/dev/nfs
> nfsroot=192.168.0.1:/srv/nfs/cubieboard2,nfsvers=3
> ip=192.168.0.2:192.168.0.1::255.255.255.0:cubieboard2 ignore_loglevel
> cma=128M
> ## Flattened Device Tree blob at 4900
>Booting using the fdt blob at 0x4900
>Loading Device Tree to 7af23000, end 7af2d360 ... OK
>
> Starting kernel ...
> ###
>
>
> What am I doing wrong? In general, how do I proceed to debug to get
> this working?
>
> Will be grateful for pointers.
>
>
> Thanks and Regards,
> Ajay



-- 
Regards,
Ajay
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Re: [U-Boot] [PATCH v1 12/16] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

[Ley Foon Tan]

On Thu, Apr 19, 2018 at 10:58 AM, Marek Vasut  wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>> Add SPL driver support for Stratix SoC
>>
>> Signed-off-by: Chin Liang See 
>> Signed-off-by: Ley Foon Tan 
>> ---
>>  arch/arm/mach-socfpga/Makefile|4 +
>>  arch/arm/mach-socfpga/include/mach/firewall_s10.h |   84 +
>>  arch/arm/mach-socfpga/spl_s10.c   |  205 
>> +
>>  3 files changed, 293 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h
>>  create mode 100644 arch/arm/mach-socfpga/spl_s10.c
>>
>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>> index b669d43..35b124a 100644
>> --- a/arch/arm/mach-socfpga/Makefile
>> +++ b/arch/arm/mach-socfpga/Makefile
>> @@ -40,6 +40,7 @@ obj-y   += system_manager_s10.o
>>  obj-y+= wrap_pinmux_config_s10.o
>>  obj-y+= wrap_pll_config_s10.o
>>  endif
>> +
>>  ifdef CONFIG_SPL_BUILD
>>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>  obj-y+= spl_gen5.o
>> @@ -51,6 +52,9 @@ endif
>>  ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
>>  obj-y+= spl_a10.o
>>  endif
>> +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>> +obj-y+= spl_s10.o
>> +endif
>>  endif
>>
>>  ifdef CONFIG_TARGET_SOCFPGA_GEN5
>> diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h 
>> b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
>> new file mode 100644
>> index 000..70aa9a6
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
>> @@ -0,0 +1,84 @@
>> +/* SPDX-License-Identifier: GPL-2.0
>> + *
>> + * Copyright (C) 2017-2018 Intel Corporation 
>> + *
>> + */
>> +
>> +#ifndef  _FIREWALL_S10_
>> +#define  _FIREWALL_S10_
>> +
>> +struct socfpga_firwall_l4_per {
>> + u32 nand;   /* 0x00 */
>> + u32 nand_data;
>> + u32 _pad_0x8;
>> + u32 usb0;
>> + u32 usb1;   /* 0x10 */
>> + u32 _pad_0x14;
>> + u32 _pad_0x18;
>> + u32 spim0;
>> + u32 spim1;  /* 0x20 */
>> + u32 spis0;
>> + u32 spis1;
>> + u32 emac0;
>> + u32 emac1;  /* 0x30 */
>> + u32 emac2;
>> + u32 _pad_0x38;
>> + u32 _pad_0x3c;
>> + u32 sdmmc;  /* 0x40 */
>> + u32 gpio0;
>> + u32 gpio1;
>> + u32 _pad_0x4c;
>> + u32 i2c0;   /* 0x50 */
>> + u32 i2c1;
>> + u32 i2c2;
>> + u32 i2c3;
>> + u32 i2c4;   /* 0x60 */
>> + u32 timer0;
>> + u32 timer1;
>> + u32 uart0;
>> + u32 uart1;  /* 0x70 */
>> +};
>> +
>> +struct socfpga_firwall_l4_sys {
>> + u32 _pad_0x00;  /* 0x00 */
>> + u32 _pad_0x04;
>> + u32 dma_ecc;
>> + u32 emac0rx_ecc;
>> + u32 emac0tx_ecc;/* 0x10 */
>> + u32 emac1rx_ecc;
>> + u32 emac1tx_ecc;
>> + u32 emac2rx_ecc;
>> + u32 emac2tx_ecc;/* 0x20 */
>> + u32 _pad_0x24;
>> + u32 _pad_0x28;
>> + u32 nand_ecc;
>> + u32 nand_read_ecc;  /* 0x30 */
>> + u32 nand_write_ecc;
>> + u32 ocram_ecc;
>> + u32 _pad_0x3c;
>> + u32 sdmmc_ecc;  /* 0x40 */
>> + u32 usb0_ecc;
>> + u32 usb1_ecc;
>> + u32 clock_manager;
>> + u32 _pad_0x50;  /* 0x50 */
>> + u32 io_manager;
>> + u32 reset_manager;
>> + u32 system_manager;
>> + u32 osc0_timer; /* 0x60 */
>> + u32 osc1_timer;
>> + u32 watchdog0;
>> + u32 watchdog1;
>> + u32 watchdog2;  /* 0x70 */
>> + u32 watchdog3;
>> +};
>> +
>> +#define FIREWALL_L4_DISABLE_ALL  (BIT(0) | BIT(24) | BIT(16))
>> +#define FIREWALL_BRIDGE_DISABLE_ALL  (~0)
>> +
>> +#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR   0xf7004688
>> +#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR0xf7018628
>> +
>> +#define CCU_ADMASK_P_MASK(BIT(0))
>> +#define CCU_ADMASK_NS_MASK   (BIT(1))
>
> Drop outer parenthesis
Noted.
>
>> +
>> +#endif /* _FIREWALL_S10_ */
>> diff --git a/arch/arm/mach-socfpga/spl_s10.c 
>> b/arch/arm/mach-socfpga/spl_s10.c
>> new file mode 100644
>> index 000..3b3833d
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/spl_s10.c
>> @@ -0,0 +1,205 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2016-2018 Intel Corporation 
>> + *
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static const struct socfpga_firwall_l4_per *firwall_l4_per_base =
>> + (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
>> +static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =

Re: [U-Boot] [PATCH v1 07/16] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

[Ley Foon Tan]

On Thu, Apr 19, 2018 at 10:49 AM, Marek Vasut  wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>> Add misc support such as EMAC and cpu info printout for Stratix SoC
>>
>> Signed-off-by: Chin Liang See 
>> Signed-off-by: Ley Foon Tan 
>> ---
>>  arch/arm/mach-socfpga/Makefile   |1 +
>>  arch/arm/mach-socfpga/misc_s10.c |  103 
>> ++
>>  2 files changed, 104 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
>>
>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>> index 910eb6f..b253914 100644
>> --- a/arch/arm/mach-socfpga/Makefile
>> +++ b/arch/arm/mach-socfpga/Makefile
>> @@ -32,6 +32,7 @@ endif
>>
>>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>  obj-y+= clock_manager_s10.o
>> +obj-y+= misc_s10.o
>>  obj-y+= reset_manager_s10.o
>>  obj-y+= system_manager_s10.o
>>  obj-y+= wrap_pinmux_config_s10.o
>> diff --git a/arch/arm/mach-socfpga/misc_s10.c 
>> b/arch/arm/mach-socfpga/misc_s10.c
>> new file mode 100644
>> index 000..b1cc6ca
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/misc_s10.c
>> @@ -0,0 +1,103 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2016-2018 Intel Corporation 
>> + *
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static struct socfpga_system_manager *sysmgr_regs =
>> + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>> +
>> +/*
>> + * DesignWare Ethernet initialization
>> + */
>> +#ifdef CONFIG_ETH_DESIGNWARE
>
> Use the reset framework ? Talk to Dinh if in doubt
Yes, will convert this to reset framework. Will send out separate
patches to convert device drivers to use reset framework.

>
>> +void dwmac_deassert_reset(const unsigned int of_reset_id,
>> +   const u32 phymode)
>> +{
>> + /* Put the emac we're using into reset.
>> +  * This is required before configuring the PHY interface
>> +  */
>> + socfpga_emac_manage_reset(of_reset_id, 1);
>> +
>> + clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
>> + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
>> + phymode);
>> +
>> + socfpga_emac_manage_reset(of_reset_id, 0);
>> +}
>> +#endif
>> +
>> +/*
>> + * Print CPU information
>> + */
>> +#if defined(CONFIG_DISPLAY_CPUINFO)
>> +int print_cpuinfo(void)
>> +{
>> + puts("CPU:   Intel FPGA SoCFPGA Platform\n");
>> + puts("FPGA:  Intel FPGA Stratix 10\n");
>
> This can well come from DT.

DT only contains the "model" and this is already display in
common/board_info.c:show_board_info().
So, will use simple puts here for the CPU info, unless we want add new
DT property.

Below is example output from console, model is retrieved from DT.

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK


>
>> + return 0;
>> +}
>> +#endif
>> +
>> +#ifdef CONFIG_ARCH_MISC_INIT
>> +int arch_misc_init(void)
>> +{
>> + char qspi_string[13];
>> +
>> + sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
>> + env_set("qspi_clock", qspi_string);
>> +
>> + return socfpga_eth_reset();
>> +}
>> +#endif
>> +
>> +int arch_early_init_r(void)
>> +{
>> + return 0;
>
> Needed ?
Will remove.
>
>> +}
>> +
>> +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>> +{
>> + if (argc != 2)
>> + return CMD_RET_USAGE;
>> +
>> + argv++;
>> +
>> + switch (*argv[0]) {
>> + case 'e':   /* Enable */
>> + socfpga_bridges_reset(1);
>> + break;
>> + case 'd':   /* Disable */
>> + socfpga_bridges_reset(0);
>> + break;
>
> Do you really need to duplicate this command ?
Will rework this part and merge with Gen5.
>
>> + default:
>> + return CMD_RET_USAGE;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +U_BOOT_CMD(bridge, 2, 1, do_bridge,
>> +"SoCFPGA HPS FPGA bridge control",
>> +"enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
>> +"bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA 
>> bridges\n"
>> +""
>> +);
>>

Thanks.

Regards
Ley Foon
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[U-Boot] Hang while booting kernel via tftp/nfs on cubieboard2

[Ajay Garg]

Hi All.


a)
As a pre-requisite, on the host-machine (serverip 192.168.0.1), the
nfs-export is listed fine :

ajay@latitude-3480:~showmount -e localhost
Export list for localhost:
/srv/nfs/cubieboard2 *


b)
The zImage and dtb files have been generated from 4.6 kernel, as per steps at
https://github.com/maronai/cubieboard/wiki/3.1.-Compiling-mainline-kernel-for-CubieBoard2-and-CubieTruck


Now, when trying to boot cubieboard2 via tftp/nfs, I get a hang, all
details as below :

###
U-Boot SPL 2017.01-2 (Jan 18 2017 - 21:30:38)
DRAM: 1024 MiB
CPU: 91200Hz, AXI/AHB/APB: 3/2/2
Trying to boot from MMC1

U-Boot 2017.01-2 (Jan 18 2017 - 21:30:38 -0700) Arch Linux ARM

CPU:   Allwinner A20 (SUN7I)
Model: Cubietech Cubieboard2
I2C:   ready
DRAM:  1 GiB
MMC:   SUNXI SD/MMC: 0
In:serial
Out:   serial
Err:   serial
SCSI:  SATA link 0 timeout.
AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
Net:   eth0: ethernet@01c5
Hit any key to stop autoboot:  0

=> printenv
autoboot=run loadkernel && run setargs && true && bootm 0x4800
baudrate=115200
boot_ram=saved_stdout=$stdout;setenv stdout nc;if iminfo 0x4100;
then true; setenv stdout $saved_stdout; source 0x4100;else setenv
stdi
bootcmd=if run loadbootenv; then echo Loaded environment from
${bootenv};env import -t ${scriptaddr} ${filesize};fi;if test -n
"${uenvcmd}"; t;
bootdelay=3
bootenv=uEnv.txt
bootscr=boot.scr
console=ttyS0,115200
device=mmc
ethact=ethernet@01c5
ethaddr=12:34:56:78:90:ab
fdtcontroladdr=7af2e820
ipaddr=192.168.0.2
kernel=uImage
loadbootenv=fatload $device $partition $scriptaddr ${bootenv} ||
ext2load $device $partition $scriptaddr boot/${bootenv} || ext2load
$device $}
loadbootscr=fatload $device $partition $scriptaddr ${bootscr} ||
ext2load $device $partition $scriptaddr boot/${bootscr} ||ext2load
$device $p}
loadkernel=if bootpath=/boot/ && ext2load $device $partition
0x4300 ${bootpath}script.bin && ext2load $device $partition
0x4800 ${booti
loglevel=8
panicarg=panic=10
partition=0:1
scriptaddr=0x4400
serial#=1651660f06c3457c
serverip=192.168.0.1
setargs=if test -z \\"$root\\"; then if test \\"$bootpath\\" =
"/boot/"; then root="/dev/mmcblk0p1 rootwait"; else
root="/dev/mmcblk0p2 rootwa}
stderr=serial
stdin=serial
stdout=serial

Environment size: 1979/131068 bytes

=> tftp 0x4900 sun7i-a20-cubieboard2.dtb
Speed: 100, full duplex
Using ethernet@01c5 device
TFTP from server 192.168.0.1; our IP address is 192.168.0.2
Filename 'sun7i-a20-cubieboard2.dtb'.
Load address: 0x4900
Loading: ###
 4 MiB/s
done
Bytes transferred = 29537 (7361 hex)

=> tftp 0x4600 zImage-Cubieboard2
Speed: 100, full duplex
Using ethernet@01c5 device
TFTP from server 192.168.0.1; our IP address is 192.168.0.2
Filename 'zImage-Cubieboard2'.
Load address: 0x4600
Loading: #
 #
 #
 
 4.6 MiB/s
done
Bytes transferred = 3388416 (33b400 hex)

=> bootz 0x4600 - 0x4900 console=ttyS0,115200 root=/dev/nfs
nfsroot=192.168.0.1:/srv/nfs/cubieboard2,nfsvers=3
ip=192.168.0.2:192.168.0.1::255.255.255.0:cubieboard2 ignore_loglevel
cma=128M
## Flattened Device Tree blob at 4900
   Booting using the fdt blob at 0x4900
   Loading Device Tree to 7af23000, end 7af2d360 ... OK

Starting kernel ...
###


What am I doing wrong? In general, how do I proceed to debug to get
this working?

Will be grateful for pointers.


Thanks and Regards,
Ajay
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[U-Boot] [PULL] u-boot-usb/master

[Marek Vasut]

The following changes since commit a61f9d1fbbca3c5e59b907ad3071db70ef174872:

  Merge git://git.denx.de/u-boot-spi (2018-04-25 20:50:28 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-usb.git master

for you to fetch changes up to d57ed4d9f2cb6abc9438104f321b4fe3bc829d57:

  usb: gadget: composite: fix NULL pointer when a non standard request
is received (2018-04-26 15:15:07 +0200)


Christophe Kerello (1):
  usb: gadget: composite: fix NULL pointer when a non standard
request is received

Neil Armstrong (1):
  usb: host: dwc3: fix phys init

 drivers/usb/gadget/composite.c |  5 -
 drivers/usb/host/xhci-dwc3.c   | 23 +--
 2 files changed, 17 insertions(+), 11 deletions(-)
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[U-Boot] [PULL] u-boot-socfpga/master

[Marek Vasut]

The following changes since commit d2a1f120cf638fd8a149bc8a46aec961c2fb9406:

  Merge git://git.denx.de/u-boot-rockchip (2018-04-26 07:21:41 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-socfpga.git master

for you to fetch changes up to 4ae87a83a64dbd71a14894114481dd92ffed4fdb:

  arm: socfpga: Fix with the correct polling on bit is set (2018-04-27
01:04:08 +0200)


Tien Fong Chee (1):
  arm: socfpga: Fix with the correct polling on bit is set

 drivers/fpga/socfpga_arria10.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)
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[U-Boot] [PULL] u-boot-sh/master

[Marek Vasut]

The following changes since commit a61f9d1fbbca3c5e59b907ad3071db70ef174872:

  Merge git://git.denx.de/u-boot-spi (2018-04-25 20:50:28 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-sh.git master

for you to fetch changes up to fe537802f1f0caa5c28f282bbb057ab2d9d684f8:

  ARM: rmobile: Fix PMIC address on E2 Silk (2018-04-26 13:56:57 +0200)


Marek Vasut (5):
  ARM: rmobile: Enable HS200 support on M3N Salvator-X
  ARM: rmobile: Update H2 Lager
  ARM: rmobile: Update M2-N Gose
  ARM: rmobile: Update E2 Alt
  ARM: rmobile: Fix PMIC address on E2 Silk

 arch/arm/dts/r8a7790-lager-u-boot.dts |   4 ++
 arch/arm/dts/r8a7793-gose-u-boot.dts  |   4 ++
 arch/arm/dts/r8a7794-alt-u-boot.dts   |   4 ++
 arch/arm/mach-rmobile/Kconfig.32  |   9 
 board/renesas/alt/Makefile|   6 ++-
 board/renesas/alt/alt.c   | 209
+---
 board/renesas/alt/alt_spl.c   | 411
+
 board/renesas/gose/Makefile   |   8 ++-
 board/renesas/gose/gose.c | 190
+
 board/renesas/gose/gose_spl.c | 408
+++
 board/renesas/lager/Makefile  |   6 ++-
 board/renesas/lager/lager.c   | 206
---
 board/renesas/lager/lager_spl.c   | 396
+++
 board/renesas/silk/silk.c |   2 +-
 configs/alt_defconfig |  49 --
 configs/gose_defconfig|  49 --
 configs/lager_defconfig   |  49 --
 configs/r8a77965_salvator-x_defconfig |   3 ++
 include/configs/alt.h |  71 --
 include/configs/gose.h|  64 
 include/configs/lager.h   |  65 +++-
 21 files changed, 1622 insertions(+), 591 deletions(-)
 create mode 100644 board/renesas/alt/alt_spl.c
 create mode 100644 board/renesas/gose/gose_spl.c
 create mode 100644 board/renesas/lager/lager_spl.c
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Re: [U-Boot] [PATCH 2/2] spi: kirkwood: Full dm conversion

[Chris Packham]

Hi Jagan,

On 26/04/18 18:00, Jagan Teki wrote:
> On Thu, Mar 15, 2018 at 5:03 PM, Jagan Teki  
> wrote:
>> kirkwood now support dt along with platform data,
>> respective boards need to switch into dm for the same.
> 
> Added all board mainatiner, using this driver on their relevant
> boards. So try to switch to DM_SPI(SPI_FLASH) before migration
> deadline expires.
> 
> Jagan.

Hopefully I can get to db88f6820-amc next week.

Stefan, did you want me to send a patch for db88f6820-gp at the same 
time since the amc board is derived from it?
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Re: [U-Boot] [PATCH 6/6] cmd: Add "boot_android" command.

[Stanislas BERTRAND]

Hi Sam,


> Can I ask you some questions about this code?
>  1. Do I understand correctly that this is just some old patch hanging
> in mailing list [1]?

Yes, it is from an old post to the mailing list.

>  2. What is the motivation of adding this command? We already have
> Android boot image support in bootm command, which we successfully use
> in TI just by loading needed images to RAM and then passing them to
> bootm, like this: [2].

I am working to get a Android A/B System implementation on my board.
I was looking to reuse existing implementation. Aiming to stay close to the 
mainline.

The command boot_android performs the different loading and checks required 
before calling bootm.

Like Alex mentioned [4], those patch series are not recent but it was good 
starting point of implementation.
I had to perform some customization to have a functional boot flow adapted to 
my system ( Android 7.1.1, Linux 4.4.45, U-Boot 2017.0 ).

I am not pushing to have this particular implementation mainline.
However having a mainline implementation for Android A/B system,
would be nice. I was giving feedback from my particular system usage.

>  3. Can you provide more information about how this code works? And
> probably show some relevant link from Android documentation where it
> says about boot flow implemented here?

>  [1] https://lists.denx.de/pipermail/u-boot/2017-April/285847.html
> [2] 
> http://git.denx.de/?p=u-boot.git;a=blob;f=include/environment/ti/boot.h;h=24b7783f88947db07480d814c798e51197c07ce2;hb=HEAD#l38

More information was posted by Alex in his original patch series [3].

Alex, I did add loading of the FDT in the boot_android command. How did you 
load your at 'fdt_addr' ?



Thanks,

[3] https://lists.denx.de/pipermail/u-boot/2017-April/285841.html
[4] https://lists.denx.de/pipermail/u-boot/2018-April/325674.html


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Re: [U-Boot] [PATCH v2] usb: f_mass_storage: Fix compile on x86

[Marek Vasut]

On 04/26/2018 10:47 PM, Bryan O'Donoghue wrote:
> Compiling the f_mass_storage driver for an x86 target results in a
> compilation error as set_bit and clear_bit are provided by bitops.h
> 
> The local version of set_bit and clear_bit are doing some IP-block specific
> bit-twiddling so we don't actually want to accidentally pick up the
> bitops.h version of set_bit and clear bit.
> 
> This patch renames to _set_bit() and _clear_bit() respectively to avoid the
> namespace collision.
> 
> Signed-off-by: Bryan O'Donoghue 
> Cc: Lukasz Majewski 
> Cc: Marek Vasut 
> ---
>  drivers/usb/gadget/f_mass_storage.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/usb/gadget/f_mass_storage.c 
> b/drivers/usb/gadget/f_mass_storage.c
> index 1ecb92ac6b..524c43419f 100644
> --- a/drivers/usb/gadget/f_mass_storage.c
> +++ b/drivers/usb/gadget/f_mass_storage.c
> @@ -283,7 +283,7 @@ static const char fsg_string_interface[] = "Mass Storage";
>  struct kref {int x; };
>  struct completion {int x; };
>  
> -inline void set_bit(int nr, volatile void *addr)
> +inline void _set_bit(int nr, volatile void *addr)

Do not name functions with _ prefix. Also, I think the suggestion from
Lukasz was better.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] fsl-ifc-nand : Corrected the programming of chip select

[York Sun]

On 04/17/2018 12:24 PM, Ronak Desai wrote:
> Corrected the chip selection in IFC_NAND_CSEL register. Due to this
> issue in multi-chip nand use-case, IFC was always pointing to the last
> probed chip even though user select another device through "nand device
> " command.
> 
> Also, updated the driver to remove usage of ifc_ctrl->cs_nand as it's
> the property of chip not the controller.
> 
> Signed-off-by: Ronak Desai 
> ---
>  drivers/mtd/nand/fsl_ifc_nand.c |   15 ++-
>  1 file changed, 6 insertions(+), 9 deletions(-)
> 
> --
> 1.7.9.5
> 
> diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
> index 495e3aa..2d0ca54 100644
> --- a/drivers/mtd/nand/fsl_ifc_nand.c
> +++ b/drivers/mtd/nand/fsl_ifc_nand.c
> @@ -48,7 +48,6 @@ struct fsl_ifc_ctrl {
>   /* device info */
>   struct fsl_ifc regs;
>   void __iomem *addr;  /* Address of assigned IFC buffer*/
> - unsigned int cs_nand;/* On which chipsel NAND is connected*/
>   unsigned int page;   /* Last page written to / read from  */
>   unsigned int read_bytes; /* Number of bytes read during command   */
>   unsigned int column; /* Saved column from SEQIN   */
> @@ -296,7 +295,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
>   int i;
> 
>   /* set the chip select for NAND Transaction */
> - ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
> + ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
> 

Can you check your code base? Commit 99145c488f78 has some of your
change already.

York
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Re: [U-Boot] [PATCH][v2] mtd: nand: fsl_ifc: Fix nand waitfunc return value

[York Sun]

On 03/20/2018 10:24 PM, Jagdish Gediya wrote:
> As per the IFC hardware manual, Most significant 2 bytes in
> nand_fsr register are the outcome of NAND READ STATUS command.
> 
> So status value need to be shifted and aligned as per the nand
> framework requirement.
> 
> Signed-off-by: Jagdish Gediya 
> Reviewed-by: Prabhakar Kushwaha 
> ---
> Changes for v2:
>   - Change the waitfunc return value according to semantic
> enforced by framework.
> 
>  drivers/mtd/nand/fsl_ifc_nand.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
> index 6eb44c3..7f487e7 100644
> --- a/drivers/mtd/nand/fsl_ifc_nand.c
> +++ b/drivers/mtd/nand/fsl_ifc_nand.c
> @@ -701,6 +701,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct 
> nand_chip *chip)
>   struct fsl_ifc_ctrl *ctrl = priv->ctrl;
>   struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
>   u32 nand_fsr;
> + int status;
>  
>   if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
>   return NAND_STATUS_FAIL;
> @@ -721,10 +722,10 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct 
> nand_chip *chip)
>   return NAND_STATUS_FAIL;
>  
>   nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
> + status = nand_fsr >> 24;
>  

You said most significant 2 bytes are the outcome, and you shift 24
bits. Did you intentionally use one byte?

York
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Re: [U-Boot] [RFC] Migrate to Linux Kernel style SPDX Tags for v2018.05

[Fabio Estevam]

Hi Tom,

On Thu, Apr 26, 2018 at 8:26 AM, Tom Rini  wrote:
> Hey all,
>
> This was already brought up by  Heinrich Schuchardt, but didn't get much
> traction.  So, I'm bringing it up again now.  The little feedback from
> that thread was we should move to Linux Kernel style tags.  I'm going to
> propose that we do just that, for v2018.05.  I'll play with coccinelle
> to get it done.  Comments?  Thanks!

Sounds good :-) Thanks
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Re: [U-Boot] [PATCH] usb: f_mass_storage: Fix compile on x86

[Lukasz Majewski]

Hi,

> On 04/26/2018 06:58 PM, Bryan O'Donoghue wrote:
> > On 26/04/18 16:14, Marek Vasut wrote:  
> >> On 04/26/2018 04:41 PM, Bryan O'Donoghue wrote:  
> >>> Compiling the f_mass_storage driver for an x86 target results in a
> >>> compilation error as set_bit and clear_bit are provided by
> >>> bitops.h
> >>>
> >>> Fix that now by only compiling up the local definition of set_bit
> >>> and clear_bit only if not already provided by the environment.
> >>>
> >>> Signed-off-by: Bryan O'Donoghue 
> >>> Cc: Lukasz Majewski 
> >>> Cc: Marek Vasut 
> >>> ---
> >>>   drivers/usb/gadget/f_mass_storage.c | 2 ++
> >>>   1 file changed, 2 insertions(+)
> >>>
> >>> diff --git a/drivers/usb/gadget/f_mass_storage.c
> >>> b/drivers/usb/gadget/f_mass_storage.c
> >>> index 1ecb92ac6b..2e856af6ed 100644
> >>> --- a/drivers/usb/gadget/f_mass_storage.c
> >>> +++ b/drivers/usb/gadget/f_mass_storage.c
> >>> @@ -283,6 +283,7 @@ static const char fsg_string_interface[] =
> >>> "Mass Storage";
> >>>   struct kref {int x; };
> >>>   struct completion {int x; };
> >>>   +#ifndef _I386_BITOPS_H
> >>>   inline void set_bit(int nr, volatile void *addr)
> >>>   {
> >>>   int    mask;
> >>> @@ -302,6 +303,7 @@ inline void clear_bit(int nr, volatile void
> >>> *addr) mask = 1 << (nr & 0x1f);
> >>>   *a &= ~mask;
> >>>   }
> >>> +#endif /* _I386_BITOPTS_H */  
> >>
> >> This doesn't look right, generic driver shouldn't contain
> >> arch-specific fixup or ifdef. Can this be somehow abstracted out?
> >>  
> > 
> > Hmm.
> > 
> > On a second look - the name of these functions should change not to
> > conflict with bitops.h - there's some funny bit-shifting going on
> > there..  
> 
> Better :)
> 

The best option would be to replace those inlines with functions
already provided in bitops.h - delete local instances and then re-use
ones from the generic header.


Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH] usb: f_mass_storage: Fix compile on x86

[Marek Vasut]

On 04/26/2018 06:58 PM, Bryan O'Donoghue wrote:
> On 26/04/18 16:14, Marek Vasut wrote:
>> On 04/26/2018 04:41 PM, Bryan O'Donoghue wrote:
>>> Compiling the f_mass_storage driver for an x86 target results in a
>>> compilation error as set_bit and clear_bit are provided by bitops.h
>>>
>>> Fix that now by only compiling up the local definition of set_bit and
>>> clear_bit only if not already provided by the environment.
>>>
>>> Signed-off-by: Bryan O'Donoghue 
>>> Cc: Lukasz Majewski 
>>> Cc: Marek Vasut 
>>> ---
>>>   drivers/usb/gadget/f_mass_storage.c | 2 ++
>>>   1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/usb/gadget/f_mass_storage.c
>>> b/drivers/usb/gadget/f_mass_storage.c
>>> index 1ecb92ac6b..2e856af6ed 100644
>>> --- a/drivers/usb/gadget/f_mass_storage.c
>>> +++ b/drivers/usb/gadget/f_mass_storage.c
>>> @@ -283,6 +283,7 @@ static const char fsg_string_interface[] = "Mass
>>> Storage";
>>>   struct kref {int x; };
>>>   struct completion {int x; };
>>>   +#ifndef _I386_BITOPS_H
>>>   inline void set_bit(int nr, volatile void *addr)
>>>   {
>>>   int    mask;
>>> @@ -302,6 +303,7 @@ inline void clear_bit(int nr, volatile void *addr)
>>>   mask = 1 << (nr & 0x1f);
>>>   *a &= ~mask;
>>>   }
>>> +#endif /* _I386_BITOPTS_H */
>>
>> This doesn't look right, generic driver shouldn't contain arch-specific
>> fixup or ifdef. Can this be somehow abstracted out?
>>
> 
> Hmm.
> 
> On a second look - the name of these functions should change not to
> conflict with bitops.h - there's some funny bit-shifting going on there..

Better :)

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Re: [U-Boot] [PATCH v3 1/2] arm: preserve lr correctly in arm926ejs startup code

[Marek Vasut]

On 04/26/2018 09:33 PM, Dr. Philipp Tomsich wrote:
> 
>> On 26 Apr 2018, at 20:18, Klaus Goger  
>> wrote:
>>
>> When building the mxs platform in thumb mode gcc generates code using
>> the intra procedure call scratch register (ip/r12) for the calling the
>> lowlevel_init function. This modifies the lr in flush_dcache which
>> causes u-boot proper to end in an endless loop.
>>
>> 40002334:   e1a0c00emov ip, lr
>> 40002338:   eb00df4cbl  4003a070
>> <__lowlevel_init_from_arm>
>> 4000233c:   e1a0e00cmov lr, ip
>> 40002340:   e1a0f00emov pc, lr
>> [...]
>> 4003a070 <__lowlevel_init_from_arm>:
>> 4003a070:   e59fc004ldr ip, [pc, #4]; 4003a07c
>> <__lowlevel_init_from_arm+0xc>
>> 4003a074:   e08fc00cadd ip, pc, ip
>> 4003a078:   e12fff1cbx  ip
>> 4003a07c:   fffc86cd.word   0xfffc86cd
>>
>> Instead of using the the ip/r12 register we use sl/r10 to preserve the
>> link register.
>>
>> According to "Procedure Call Standard for the ARM Architecture" by ARM
>> subroutines have to preserve the contents of register r4-r8, r10, r11
>> and SP. So using r12 to store the link register will fail if the called
>> function is using r12 and not preserving it as allowed.
> 
> Maybe you could rephrase this one, as the “not preserving it as allowed”
> made me read this twice until I realised that it is equivalent to “does not
> preserve (and is not required by the PCS to preserve)”?
> 
>> This can happen in ARM and thumb mode but will definitely be triggered
>> by building it in thumb.
>> Using r10 should be safe in any case as we are startup code and not
>> called by any C-function and no stack is set up.
>>
>> Signed-off-by: Klaus Goger 
>> Signed-off-by: Christoph Muellner 
> 
> Reviewed-by: Philipp Tomsich 

I'd prefer to see a review from someone not from the same company :)

>> ---
>>
>> Changes in v3:
>> - reword commit message as it isn't thumb specific
>> - use r10 instead of sl alias as we don't use it as stack limit pointer
>> - revert return to a pc mov as it is a unnecessary change for this patch
>>
>> Changes in v2:
>> - use bl instead of blx to call lowlevel_init
>> - remove mxs tag as it apply to all arm926ejs platforms
>>
>> arch/arm/cpu/arm926ejs/start.S | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
>> index 959d1ed86d..a625b39787 100644
>> --- a/arch/arm/cpu/arm926ejs/start.S
>> +++ b/arch/arm/cpu/arm926ejs/start.S
>> @@ -105,9 +105,9 @@ flush_dcache:
>>  /*
>>   * Go setup Memory and board specific bits prior to relocation.
>>   */
>> -mov ip, lr  /* perserve link reg across call */
>> +mov r10, lr /* perserve link reg across call */
>>  bl  lowlevel_init   /* go setup pll,mux,memory */
>> -mov lr, ip  /* restore link */
>> +mov lr, r10 /* restore link */
>> #endif
>>  mov pc, lr  /* back to my caller */
>> #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
>> --
>> 2.11.0
>>
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> 


-- 
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Marek Vasut
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Re: [U-Boot] [PATCH v3 1/2] arm: preserve lr correctly in arm926ejs startup code

[Dr. Philipp Tomsich]

> On 26 Apr 2018, at 20:18, Klaus Goger  
> wrote:
> 
> When building the mxs platform in thumb mode gcc generates code using
> the intra procedure call scratch register (ip/r12) for the calling the
> lowlevel_init function. This modifies the lr in flush_dcache which
> causes u-boot proper to end in an endless loop.
> 
> 40002334:   e1a0c00emov ip, lr
> 40002338:   eb00df4cbl  4003a070
> <__lowlevel_init_from_arm>
> 4000233c:   e1a0e00cmov lr, ip
> 40002340:   e1a0f00emov pc, lr
> [...]
> 4003a070 <__lowlevel_init_from_arm>:
> 4003a070:   e59fc004ldr ip, [pc, #4]; 4003a07c
> <__lowlevel_init_from_arm+0xc>
> 4003a074:   e08fc00cadd ip, pc, ip
> 4003a078:   e12fff1cbx  ip
> 4003a07c:   fffc86cd.word   0xfffc86cd
> 
> Instead of using the the ip/r12 register we use sl/r10 to preserve the
> link register.
> 
> According to "Procedure Call Standard for the ARM Architecture" by ARM
> subroutines have to preserve the contents of register r4-r8, r10, r11
> and SP. So using r12 to store the link register will fail if the called
> function is using r12 and not preserving it as allowed.

Maybe you could rephrase this one, as the “not preserving it as allowed”
made me read this twice until I realised that it is equivalent to “does not
preserve (and is not required by the PCS to preserve)”?

> This can happen in ARM and thumb mode but will definitely be triggered
> by building it in thumb.
> Using r10 should be safe in any case as we are startup code and not
> called by any C-function and no stack is set up.
> 
> Signed-off-by: Klaus Goger 
> Signed-off-by: Christoph Muellner 

Reviewed-by: Philipp Tomsich 

> 
> ---
> 
> Changes in v3:
> - reword commit message as it isn't thumb specific
> - use r10 instead of sl alias as we don't use it as stack limit pointer
> - revert return to a pc mov as it is a unnecessary change for this patch
> 
> Changes in v2:
> - use bl instead of blx to call lowlevel_init
> - remove mxs tag as it apply to all arm926ejs platforms
> 
> arch/arm/cpu/arm926ejs/start.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
> index 959d1ed86d..a625b39787 100644
> --- a/arch/arm/cpu/arm926ejs/start.S
> +++ b/arch/arm/cpu/arm926ejs/start.S
> @@ -105,9 +105,9 @@ flush_dcache:
>   /*
>* Go setup Memory and board specific bits prior to relocation.
>*/
> - mov ip, lr  /* perserve link reg across call */
> + mov r10, lr /* perserve link reg across call */
>   bl  lowlevel_init   /* go setup pll,mux,memory */
> - mov lr, ip  /* restore link */
> + mov lr, r10 /* restore link */
> #endif
>   mov pc, lr  /* back to my caller */
> #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
> --
> 2.11.0
> 
> ___
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Re: [U-Boot] [PATCH v2 7/7] arm: v7R: Add support for enabling caches

[Tom Rini]

On Thu, Apr 26, 2018 at 06:21:31PM +0530, Lokesh Vutla wrote:

> Cache maintenance procedure is same for v7A and v7R
> processors. So re-use cache-cp15.c file except for
> mmu parts.
> 
> Tested-by: Michal Simek 
> Signed-off-by: Lokesh Vutla 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH v2 6/7] arm: v7R: Add support for MPU

[Tom Rini]

On Thu, Apr 26, 2018 at 06:21:30PM +0530, Lokesh Vutla wrote:

> The Memory Protection Unit(MPU) allows to partition memory into regions
> and set individual protection attributes for each region. In absence
> of MPU a default map[1] will take effect. Add support for configuring
> MPU on Cortex-R, by reusing the existing support for Cortex-M processor.
> 
> [1] 
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I1002400.html
> 
> Tested-by: Michal Simek 
> Signed-off-by: Lokesh Vutla 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PULL] Please pull u-boot-rockchip

[Tom Rini]

On Thu, Apr 26, 2018 at 09:20:24AM +0200, Dr. Philipp Tomsich wrote:

> Tom,
> 
> I have a number of fixes, cleanups and config-changes for the upcoming release
> ready for you in u-boot-rockchip/master.  Please pull.
> 
> The Travis-CI report for this tree can be found at
>   https://travis-ci.org/ptomsich/u-boot-rockchip/builds/371249739
> 
> Thanks,
> Philipp.
> 
> 
> The following changes since commit 5512f5ccf1dc5cec068f8efa1d8ce81f51a988d3:
> 
>   Merge git://git.denx.de/u-boot-video (2018-04-24 20:27:43 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-rockchip.git master
> 
> for you to fetch changes up to eb3d707e99fcd2213d5f8f0fe4ae53ad416b377e:
> 
>   rockchip: defconfig: remove CONFIG_SYS_NS16550 (2018-04-25 22:20:07 +0200)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 6/6] cmd: Add "boot_android" command.

[Sam Protsenko]

On 19 April 2018 at 20:21, Stanislas BERTRAND  wrote:
> Hi Alex,
>
> I used work available in 
> https://android.googlesource.com/platform/external/u-boot/+/android-o-mr1-iot-preview-7.
> I selected the n-iot-preview-4 because it is U-Boot version 2017.01 which is 
> compatible with TI U-Boot work.
>
> One quick feedback about the boot_android :
>
>> The new "boot_android" command simply executes the Android Bootloader
>> flow. This receives the location (interface, dev, partition) of the
>> Android "misc" partition which is then used to lookup and infer the
>> kernel and system images that should be booted from the passed slot.
>>
>> Test: Booted a rpi3 build with Android Things.
>> Signed-off-by: Alex Deymo 

Hi Stanislas,

Can I ask you some questions about this code?
 1. Do I understand correctly that this is just some old patch hanging
in mailing list [1]?
 2. What is the motivation of adding this command? We already have
Android boot image support in bootm command, which we successfully use
in TI just by loading needed images to RAM and then passing them to
bootm, like this: [2].
 3. Can you provide more information about how this code works? And
probably show some relevant link from Android documentation where it
says about boot flow implemented here?

Thanks!

[1] https://lists.denx.de/pipermail/u-boot/2017-April/285847.html
[2] 
http://git.denx.de/?p=u-boot.git;a=blob;f=include/environment/ti/boot.h;h=24b7783f88947db07480d814c798e51197c07ce2;hb=HEAD#l38

>> ---
>>  README |   6 +++
>>  cmd/Kconfig|  10 +
>>  cmd/Makefile   |   1 +
>>  cmd/boot_android.c | 126 
>> +
>>  4 files changed, 143 insertions(+)
>>  create mode 100644 cmd/boot_android.c
>>
>> diff --git a/README b/README
>> index 384cc6aabb..5f62e14d94 100644
>> --- a/README
>> +++ b/README
>> @@ -1484,6 +1484,12 @@ The following options need to be configured:
>>   sending again an USB request to the device.
>>
>>  - Android Bootloader support:
>> + CONFIG_CMD_BOOT_ANDROID
>> + This enables the command "boot_android" which executes the
>> + Android Bootloader flow. Enabling CONFIG_CMD_FASTBOOT is
>> + recommended to support the Android Fastboot protocol as part
>> + of the bootloader.
>> +
>>   CONFIG_ANDROID_BOOTLOADER
>>   This enables support for the Android bootloader flow. Android
>>   devices can boot in normal mode, recovery mode or bootloader
>> diff --git a/cmd/Kconfig b/cmd/Kconfig
>> index 87a445d269..c4c22464b1 100644
>> --- a/cmd/Kconfig
>> +++ b/cmd/Kconfig
>> @@ -431,6 +431,16 @@ config CMD_LOAD_ANDROID
>> define the size and kernel address on the header, which are used by
>> this command.
>>
>> +config CMD_BOOT_ANDROID
>> + bool "boot_android"
>> + default n
>> + depends on ANDROID_BOOTLOADER
>> + help
>> +   Performs the Android Bootloader boot flow, loading the appropriate
>> +   Android image (normal kernel, recovery kernel or "bootloader" mode)
>> +   and booting it. The boot mode is determined by the contents of the
>> +   Android Bootloader Message.
>> +
>>  config CMD_FLASH
>>   bool "flinfo, erase, protect"
>>   default y
>> diff --git a/cmd/Makefile b/cmd/Makefile
>> index 2f75dab040..348cf75386 100644
>> --- a/cmd/Makefile
>> +++ b/cmd/Makefile
>> @@ -22,6 +22,7 @@ obj-$(CONFIG_CMD_BDI) += bdinfo.o
>>  obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
>>  obj-$(CONFIG_CMD_BLOCK_CACHE) += blkcache.o
>>  obj-$(CONFIG_CMD_BMP) += bmp.o
>> +obj-$(CONFIG_CMD_BOOT_ANDROID) += boot_android.o
>>  obj-$(CONFIG_CMD_BOOTEFI) += bootefi.o
>>  obj-$(CONFIG_CMD_BOOTMENU) += bootmenu.o
>>  obj-$(CONFIG_CMD_BOOTLDR) += bootldr.o
>> diff --git a/cmd/boot_android.c b/cmd/boot_android.c
>> new file mode 100644
>> index 00..067d9c7637
>> --- /dev/null
>> +++ b/cmd/boot_android.c
>> @@ -0,0 +1,126 @@
>> +/*
>> + * Copyright (C) 2016 The Android Open Source Project
>> + *
>> + * SPDX-License-Identifier: BSD-2-Clause
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/**
>> + * part_get_info_by_dev_and_name - Parse a device number and partition name
>> + * string in the form of "device_num;partition_name", for example "0;misc".
>> + * If the partition is found, sets dev_desc and part_info accordingly with 
>> the
>> + * information of the partition with the given partition_name.
>> + *
>> + * @dev_iface:   Device interface.
>> + * @dev_part_str:Input string argument, like "0;misc".
>> + * @dev_desc:Place to put the device description pointer.
>> + * @part_info:   Place to put the partition information.
>> + * @return 0 on success, or -1 on error
>> + */
>> +static int part_get_info_by_dev_and_name(const char *dev_iface,
>> +  const char *dev_part_str,
>> +  struct blk_desc **

Re: [U-Boot] [PATCH 0/8] Initial integration of AVB2.0

[Alex Deymo]

Hi Kever,
  libavb and libavb_ab are different things, and we split them for a
reason. Adding libavb is great, but you don't need to add libavb_ab as an
A/B implementation. The boot_android command referenced by Igor doesn't use
that as an A/B implementation, but uses the structs already defined in
the Boot Control Block (BCB) and the android bootloader flow. I would
recommend to include the libavb only.

Igor,
What changes did you need to do to libavb to import it to U-Boot? The idea
with libavb is that it should be easy to integrate into your bootloader
without changes; and therefore easy to update and integrate new patches
when we release new versions of libavb. We would like to avoid diverting
from it to reduce the maintenance cost.

Best regards,
Alex


Le jeu. 26 avr. 2018 à 05:05, Kever Yang  a
écrit :

> Hi Igor,
>
> It's great to see the patch set to support AVB2.0, the upstream
> libavb(from aosp) combine the AVB with A/B which I think should be
> two separate feature, are you going to split them?
>
> BTW, do you have plan to update boot_android cmd to support avb?
> the command is too weak for use now.
> And any plan to add opptee_client/smcc to talk to OPTEE/ATF?
>
> Thanks,
> - Kever
> On 04/25/2018 09:17 PM, Igor Opaniuk wrote:
> > This series of patches introduces support of Android Verified Boot 2.0,
> > which provides integrity checking of Android partitions on MMC.
> >
> > It integrates libavb/libavb_ab into the U-boot, provides implementation
> of
> > AvbOps, subset of `avb` commands to run verification chain (and for
> debugging
> > purposes), and it enables AVB2.0 verification on AM57xx HS SoC by
> default.
> >
> > Currently, there is still no support for verification of A/B boot slots
> > and no rollback protection (for storing rollback indexes
> > there are plans to use eMMC RPMB)
> >
> > Libavb/libavb_ab will be deviated from AOSP upstream in the future,
> > that's why minimal amount of changes were introduced into the lib
> sources,
> > so checkpatch may fail.
> >
> > For additional details check [1] AVB 2.0 README and doc/README.avb2,
> which
> > is a part of this patchset.
> >
> > [1]
> https://android.googlesource.com/platform/external/avb/+/master/README.md
> >
> > Igor Opaniuk (8):
> >   avb2.0: add Android Verified Boot 2.0 libraries
> >   avb2.0: integrate avb 2.0 into the build system
> >   avb2.0: implement AVB ops
> >   cmd: avb2.0: avb command for performing verification
> >   avb2.0: add boot states and dm-verity support
> >   am57xx_hs: avb2.0: add support of AVB 2.0
> >   test/py: avb2.0: add tests for avb commands
> >   doc: avb2.0: add README about AVB2.0 integration
> >
> >  cmd/Kconfig  |   15 +
> >  cmd/Makefile |3 +
> >  cmd/avb.c|  366 
> >  common/Makefile  |2 +
> >  common/avb_verify.c  |  748 
> >  configs/am57xx_hs_evm_defconfig  |3 +
> >  doc/README.avb2  |  100 +++
> >  include/avb/avb_ab_flow.h|  235 ++
> >  include/avb/avb_ab_ops.h |   61 ++
> >  include/avb/avb_chain_partition_descriptor.h |   54 ++
> >  include/avb/avb_crypto.h |  147 
> >  include/avb/avb_descriptor.h |  113 +++
> >  include/avb/avb_footer.h |   68 ++
> >  include/avb/avb_hash_descriptor.h|   55 ++
> >  include/avb/avb_hashtree_descriptor.h|   65 ++
> >  include/avb/avb_kernel_cmdline_descriptor.h  |   63 ++
> >  include/avb/avb_ops.h|  196 +
> >  include/avb/avb_property_descriptor.h|   89 ++
> >  include/avb/avb_rsa.h|   55 ++
> >  include/avb/avb_sha.h|   72 ++
> >  include/avb/avb_slot_verify.h|  239 ++
> >  include/avb/avb_sysdeps.h|   97 +++
> >  include/avb/avb_util.h   |  259 ++
> >  include/avb/avb_vbmeta_image.h   |  272 ++
> >  include/avb/avb_version.h|   45 +
> >  include/avb/libavb.h |   32 +
> >  include/avb/libavb_ab.h  |   22 +
> >  include/avb_verify.h |   97 +++
> >  include/configs/am57xx_evm.h |   11 +
> >  include/environment/ti/boot.h|   15 +
> >  lib/Kconfig  |   20 +
> >  lib/Makefile |2 +
> >  lib/libavb/Makefile  |   15 +
> >  lib/libavb/avb_chain_partition_descriptor.c  |   46 +
> >  lib/libavb/avb_crypto.c  |  355 
> >  lib/libavb/avb_descriptor.c  |  142 
> >  lib/libavb/avb_footer.c  |   36 +
> >  lib/libavb/avb_hash_descriptor.c |   43 +
> >  lib/libav

[U-Boot] [PATCH v3 2/2] arm: Make arch specific memcpy thumb-safe.

[Klaus Goger]

The current arch implementation of memcpy cannot be called
from thumb code, because it does not use bx instructions on return.
This patch addresses that. Note, that this patch does not touch
the hot loop of memcpy, so performance is not affected.

Tested on MXS (arm926ejs) with and without thumb-mode enabled.

Signed-off-by: Klaus Goger 
Signed-off-by: Christoph Muellner 

---

Changes in v3: None
Changes in v2:
- added memcpy patch to the series

 arch/arm/lib/memcpy.S | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index 588b3f8971..9e9a193c2a 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -62,7 +62,7 @@
 #endif
 ENTRY(memcpy)
cmp r0, r1
-   moveq   pc, lr
+   bxeqlr
 
enter   r4, lr
 
@@ -150,7 +150,8 @@ ENTRY(memcpy)
str1b   r0, r4, cs, abort=21f
str1b   r0, ip, cs, abort=21f
 
-   exitr4, pc
+   exitr4, lr
+   bx  lr
 
 9: rsb ip, ip, #4
cmp ip, #2
@@ -259,7 +260,8 @@ ENTRY(memcpy)
.endm
 
.macro  copy_abort_end
-   ldmfd   sp!, {r4, pc}
+   ldmfd   sp!, {r4, lr}
+   bx  lr
.endm
 
 ENDPROC(memcpy)
-- 
2.11.0

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[U-Boot] [PATCH v3 0/2] Fix thumb interwork in assembly code

[Klaus Goger]

While trying to compile u-boot in thumb due space constraints on a mxs
platform it was observed that there are some thumb-interwork issues
in the handwritten assembly files.

Since the first patch only applies to ARM926EJS and no board on that platform
has thumb enabled for now,it was probably never observed.
Strictly speaking it is not thumb specific as it can be triggered in ARM
mode too. But as it was discovered by enabling thumb and no mxs board is
currently using any relevant ARM code in lowlevel_init, we put the series
under the thumb subject.

The second one applies to the ARM specific assembly memcpy implementation
that is not enabled on any of the boards enabling thumb.

grep -l CONFIG_SYS_THUMB_BUILD=y configs/* | \
  xargs grep -c CONFIG_USE_ARCH_MEMCPY
configs/apalis_imx6_nospl_com_defconfig:0
configs/apalis_imx6_nospl_it_defconfig:0
configs/bk4r1_defconfig:0
configs/colibri_imx6_nospl_defconfig:0
configs/colibri_imx7_defconfig:0
configs/colibri_vf_defconfig:0
configs/highbank_defconfig:0
configs/openrd_base_defconfig:0
configs/openrd_client_defconfig:0
configs/openrd_ultimate_defconfig:0
configs/pcm052_defconfig:0
configs/tbs2910_defconfig:0
configs/x600_defconfig:0

With CONFIG_USE_ARCH_MEMCPY on our mxs platform the speedup for memcopy
was about 100%.

Changes in v3:
- reword commit message as it isn't thumb specific
- use r10 instead of sl alias as we don't use it as stack limit pointer
- revert return to a pc mov as it is a unnecessary change for this patch

Changes in v2:
- use bl instead of blx to call lowlevel_init
- remove mxs tag as it apply to all arm926ejs platforms
- added memcpy patch to the series

Klaus Goger (2):
  arm: preserve lr correctly in arm926ejs startup code
  arm: Make arch specific memcpy thumb-safe.

 arch/arm/cpu/arm926ejs/start.S | 4 ++--
 arch/arm/lib/memcpy.S  | 8 +---
 2 files changed, 7 insertions(+), 5 deletions(-)

-- 
2.11.0

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[U-Boot] [PATCH v3 1/2] arm: preserve lr correctly in arm926ejs startup code

[Klaus Goger]

When building the mxs platform in thumb mode gcc generates code using
the intra procedure call scratch register (ip/r12) for the calling the
lowlevel_init function. This modifies the lr in flush_dcache which
causes u-boot proper to end in an endless loop.

40002334:   e1a0c00emov ip, lr
40002338:   eb00df4cbl  4003a070
<__lowlevel_init_from_arm>
4000233c:   e1a0e00cmov lr, ip
40002340:   e1a0f00emov pc, lr
[...]
4003a070 <__lowlevel_init_from_arm>:
4003a070:   e59fc004ldr ip, [pc, #4]; 4003a07c
<__lowlevel_init_from_arm+0xc>
4003a074:   e08fc00cadd ip, pc, ip
4003a078:   e12fff1cbx  ip
4003a07c:   fffc86cd.word   0xfffc86cd

Instead of using the the ip/r12 register we use sl/r10 to preserve the
link register.

According to "Procedure Call Standard for the ARM Architecture" by ARM
subroutines have to preserve the contents of register r4-r8, r10, r11
and SP. So using r12 to store the link register will fail if the called
function is using r12 and not preserving it as allowed.
This can happen in ARM and thumb mode but will definitely be triggered
by building it in thumb.
Using r10 should be safe in any case as we are startup code and not
called by any C-function and no stack is set up.

Signed-off-by: Klaus Goger 
Signed-off-by: Christoph Muellner 

---

Changes in v3:
- reword commit message as it isn't thumb specific
- use r10 instead of sl alias as we don't use it as stack limit pointer
- revert return to a pc mov as it is a unnecessary change for this patch

Changes in v2:
- use bl instead of blx to call lowlevel_init
- remove mxs tag as it apply to all arm926ejs platforms

 arch/arm/cpu/arm926ejs/start.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 959d1ed86d..a625b39787 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -105,9 +105,9 @@ flush_dcache:
/*
 * Go setup Memory and board specific bits prior to relocation.
 */
-   mov ip, lr  /* perserve link reg across call */
+   mov r10, lr /* perserve link reg across call */
bl  lowlevel_init   /* go setup pll,mux,memory */
-   mov lr, ip  /* restore link */
+   mov lr, r10 /* restore link */
 #endif
mov pc, lr  /* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-- 
2.11.0

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Re: [U-Boot] [PATCH] usb: f_mass_storage: Fix compile on x86

[Bryan O'Donoghue]

On 26/04/18 16:14, Marek Vasut wrote:

On 04/26/2018 04:41 PM, Bryan O'Donoghue wrote:

Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h

Fix that now by only compiling up the local definition of set_bit and
clear_bit only if not already provided by the environment.

Signed-off-by: Bryan O'Donoghue 
Cc: Lukasz Majewski 
Cc: Marek Vasut 
---
  drivers/usb/gadget/f_mass_storage.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/usb/gadget/f_mass_storage.c 
b/drivers/usb/gadget/f_mass_storage.c
index 1ecb92ac6b..2e856af6ed 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -283,6 +283,7 @@ static const char fsg_string_interface[] = "Mass Storage";
  struct kref {int x; };
  struct completion {int x; };
  
+#ifndef _I386_BITOPS_H

  inline void set_bit(int nr, volatile void *addr)
  {
int mask;
@@ -302,6 +303,7 @@ inline void clear_bit(int nr, volatile void *addr)
mask = 1 << (nr & 0x1f);
*a &= ~mask;
  }
+#endif /* _I386_BITOPTS_H */


This doesn't look right, generic driver shouldn't contain arch-specific
fixup or ifdef. Can this be somehow abstracted out?



Hmm.

On a second look - the name of these functions should change not to 
conflict with bitops.h - there's some funny bit-shifting going on there..


---
bod
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[U-Boot] [PATCH v1 2/3] spi: sh_spi: DM conversion

[Akash Gajjar]

This patch adds support for DM to the sh_spi driver. legacy driver support is
removed.

Some TODOs are left over for later, These would be enhancements to the
original functionality, and can come later. The legacy functionality is
removed in this version.

This patch is not tested on board as well compile tested yet.

Signed-off-by: Akash Gajjar 
---
 drivers/spi/Kconfig   |  12 +--
 drivers/spi/sh_spi.c  | 214 +-
 drivers/spi/sh_spi.h  |   3 +-
 include/dm/platform_data/spi_sh.h |  20 
 4 files changed, 147 insertions(+), 102 deletions(-)
 create mode 100644 include/dm/platform_data/spi_sh.h

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ec92b84..be6ad22 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -155,6 +155,12 @@ config SANDBOX_SPI
};
  };
 
+config SH_SPI
+   bool "SuperH SPI driver"
+   help
+ Enable the SuperH SPI controller driver. This driver can be used
+ on various SuperH SoCs, such as SH7757.
+
 config STM32_QSPI
bool "STM32F7 QSPI driver"
depends on STM32F7
@@ -253,12 +259,6 @@ config DAVINCI_SPI
help
  Enable the Davinci SPI driver
 
-config SH_SPI
-   bool "SuperH SPI driver"
-   help
- Enable the SuperH SPI controller driver. This driver can be used
- on various SuperH SoCs, such as SH7757.
-
 config SH_QSPI
bool "Renesas Quad SPI driver"
help
diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
index fe394e3..b308ec8 100644
--- a/drivers/spi/sh_spi.c
+++ b/drivers/spi/sh_spi.c
@@ -1,6 +1,10 @@
 /*
  * SH SPI driver
  *
+ * Support for device model:
+ * Copyright (C) 2018  Akash Gajjar 
+ * Harshit Shah 
+ *
  * Copyright (C) 2011-2012 Renesas Solutions Corp.
  *
  * SPDX-License-Identifier:GPL-2.0
@@ -11,6 +15,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include "sh_spi.h"
 
 static void sh_spi_write(unsigned long data, unsigned long *reg)
@@ -41,15 +47,15 @@ static void sh_spi_clear_bit(unsigned long val, unsigned 
long *reg)
sh_spi_write(tmp, reg);
 }
 
-static void clear_fifo(struct sh_spi *ss)
+static void clear_fifo(struct sh_spi_regs *regs)
 {
-   sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
-   sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
+   sh_spi_set_bit(SH_SPI_RSTF, ®s->cr2);
+   sh_spi_clear_bit(SH_SPI_RSTF, ®s->cr2);
 }
 
-static int recvbuf_wait(struct sh_spi *ss)
+static int recvbuf_wait(struct sh_spi_regs *regs)
 {
-   while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
+   while (sh_spi_read(®s->cr1) & SH_SPI_RBE) {
if (ctrlc())
return 1;
udelay(10);
@@ -57,9 +63,9 @@ static int recvbuf_wait(struct sh_spi *ss)
return 0;
 }
 
-static int write_fifo_empty_wait(struct sh_spi *ss)
+static int write_fifo_empty_wait(struct sh_spi_regs *regs)
 {
-   while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
+   while (!(sh_spi_read(®s->cr1) & SH_SPI_TBE)) {
if (ctrlc())
return 1;
udelay(10);
@@ -67,11 +73,7 @@ static int write_fifo_empty_wait(struct sh_spi *ss)
return 0;
 }
 
-void spi_init(void)
-{
-}
-
-static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
+static void sh_spi_set_cs(struct sh_spi_regs *regs, unsigned int cs)
 {
unsigned long val = 0;
 
@@ -80,85 +82,53 @@ static void sh_spi_set_cs(struct sh_spi *ss, unsigned int 
cs)
if (cs & 0x02)
val |= SH_SPI_SSS1;
 
-   sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
-   sh_spi_set_bit(val, &ss->regs->cr4);
+   sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, ®s->cr4);
+   sh_spi_set_bit(val, ®s->cr4);
 }
 
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-   unsigned int max_hz, unsigned int mode)
+static void __spi_setup(struct sh_spi_regs *regs, uint cs)
 {
-   struct sh_spi *ss;
-
-   if (!spi_cs_is_valid(bus, cs))
-   return NULL;
-
-   ss = spi_alloc_slave(struct sh_spi, bus, cs);
-   if (!ss)
-   return NULL;
-
-   ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
-
+   /* initialize spi */
+   regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
/* SPI sycle stop */
-   sh_spi_write(0xfe, &ss->regs->cr1);
+   sh_spi_write(0xfe, ®s->cr1);
/* CR1 init */
-   sh_spi_write(0x00, &ss->regs->cr1);
+   sh_spi_write(0x00, ®s->cr1);
/* CR3 init */
-   sh_spi_write(0x00, &ss->regs->cr3);
-   sh_spi_set_cs(ss, cs);
+   sh_spi_write(0x00, ®s->cr3);
+   sh_spi_set_cs(regs, cs);
 
-   clear_fifo(ss);
+   clear_fifo(regs);
 
/* 1/8 clock */
-   sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
+   sh_spi_write(sh_spi_read(®s->cr2) | 0x07, ®s->cr2);
udelay

[U-Boot] [PATCH v1 3/3] spi: mxs_spi: DM conversion

[Akash Gajjar]

This patch adds support for DM to the mxs spi driver.

Some TODOs are left over for later, These would be enhancements to the
original functionality, and can come later.

The legacy functionality is present in this version, so old boards in the tree
is working with legacy SPI driver functionality.

Signed-off-by: Akash Gajjar 
---
 drivers/spi/Kconfig|  12 +-
 drivers/spi/mxs_spi.c  | 257 +++--
 include/dm/platform_data/spi_mxs.h |  18 +++
 3 files changed, 186 insertions(+), 101 deletions(-)
 create mode 100644 include/dm/platform_data/spi_mxs.h

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ec92b84..5d3e152 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -106,6 +106,12 @@ config MVEBU_A3700_SPI
  used to access the SPI NOR flash on platforms embedding this
  Marvell IP core.
 
+config MXS_SPI
+   bool "MXS SPI Driver"
+   help
+ Enable the MXS SPI controller driver. This driver can be used
+ on the i.MX23 and i.MX28 SoCs.
+
 config PIC32_SPI
bool "Microchip PIC32 SPI driver"
depends on MACH_PIC32
@@ -299,12 +305,6 @@ config MXC_SPI
  Enable the MXC SPI controller driver. This driver can be used
  on various i.MX SoCs such as i.MX31/35/51/6/7.
 
-config MXS_SPI
-   bool "MXS SPI Driver"
-   help
- Enable the MXS SPI controller driver. This driver can be used
- on the i.MX23 and i.MX28 SoCs.
-
 config OMAP3_SPI
bool "McSPI driver for OMAP"
help
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 790db78..b48ecbf 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -1,6 +1,9 @@
 /*
  * Freescale i.MX28 SPI driver
  *
+ * Support for device model:
+ * Copyright (C) 2018 Akash Gajjar 
+ *
  * Copyright (C) 2011 Marek Vasut 
  * on behalf of DENX Software Engineering GmbH
  *
@@ -20,6 +23,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #defineMXS_SPI_MAX_TIMEOUT 100
 #defineMXS_SPI_PORT_OFFSET 0x2000
@@ -28,93 +33,14 @@
 
 #define MXSSSP_SMALL_TRANSFER  512
 
-struct mxs_spi_slave {
-   struct spi_slaveslave;
-   uint32_tmax_khz;
-   uint32_tmode;
-   struct mxs_ssp_regs *regs;
+struct mxs_spi_priv {
+   struct mxs_ssp_regs *regs;
+   u32 max_khz;
+   u32 mode;
+   u32 bus;
+   u32 cs;
 };
 
-static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
-{
-   return container_of(slave, struct mxs_spi_slave, slave);
-}
-
-void spi_init(void)
-{
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-   /* MXS SPI: 4 ports and 3 chip selects maximum */
-   if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
-   return 0;
-   else
-   return 1;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
-   struct mxs_spi_slave *mxs_slave;
-
-   if (!spi_cs_is_valid(bus, cs)) {
-   printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
-   return NULL;
-   }
-
-   mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
-   if (!mxs_slave)
-   return NULL;
-
-   if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
-   goto err_init;
-
-   mxs_slave->max_khz = max_hz / 1000;
-   mxs_slave->mode = mode;
-   mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
-
-   return &mxs_slave->slave;
-
-err_init:
-   free(mxs_slave);
-   return NULL;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-   struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
-   free(mxs_slave);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-   struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
-   struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
-   uint32_t reg = 0;
-
-   mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
-
-   writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
-  SSP_CTRL0_BUS_WIDTH_ONE_BIT,
-  &ssp_regs->hw_ssp_ctrl0);
-
-   reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
-   reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
-   reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
-   writel(reg, &ssp_regs->hw_ssp_ctrl1);
-
-   writel(0, &ssp_regs->hw_ssp_cmd0);
-
-   mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
-
-   return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
 {
writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
@@ -127,10 +53,10 @@ static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
 }
 
-static int mxs_spi_xfe

[U-Boot] [PATCH v1 1/3] spi: sh_qspi: DM conversion

[Akash Gajjar]

This patch adds support for DM to the sh_qspi SPI driver.

The legacy functionality is removed in this version, so old boards in
the tree is not working with legacy SPI driver functionality.
Some TODOs are left over for later, These would be enhancements to the
original functionality, and can come later.

This patch is not tested on board as well compile tested yet.

Signed-off-by: Akash Gajjar 
---
 drivers/spi/sh_qspi.c  | 199 ++---
 include/dm/platform_data/qspi_sh.h |  20 
 2 files changed, 119 insertions(+), 100 deletions(-)
 create mode 100644 include/dm/platform_data/qspi_sh.h

diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
index 5075be3..5fdd52e 100644
--- a/drivers/spi/sh_qspi.c
+++ b/drivers/spi/sh_qspi.c
@@ -1,6 +1,10 @@
 /*
  * SH QSPI (Quad SPI) driver
  *
+ * Support for device model:
+ * Copyright (C) 2018 Akash Gajjar 
+ *   Harshit Shah 
+ *
  * Copyright (C) 2013 Renesas Electronics Corporation
  * Copyright (C) 2013 Nobuhiro Iwamatsu 
  *
@@ -14,6 +18,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /* SH QSPI register bit masks _ */
 #define SPCR_MSTR  0x08
@@ -67,151 +73,90 @@ struct sh_qspi_regs {
u32 spbmul3;
 };
 
-struct sh_qspi_slave {
-   struct spi_slaveslave;
-   struct sh_qspi_regs *regs;
+struct sh_qspi_priv {
+   struct sh_qspi_regs *regs;
 };
 
-static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
-{
-   return container_of(slave, struct sh_qspi_slave, slave);
-}
-
-static void sh_qspi_init(struct sh_qspi_slave *ss)
+static int __sh_qspi_setup(struct sh_qspi_priv *priv)
 {
/* QSPI initialize */
+   priv->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
+
/* Set master mode only */
-   writeb(SPCR_MSTR, &ss->regs->spcr);
+   writeb(SPCR_MSTR, &priv->regs->spcr);
 
/* Set SSL signal level */
-   writeb(0x00, &ss->regs->sslp);
+   writeb(0x00, &priv->regs->sslp);
 
/* Set MOSI signal value when transfer is in idle state */
-   writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
+   writeb(SPPCR_IO3FV | SPPCR_IO2FV, &priv->regs->sppcr);
 
/* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
-   writeb(0x01, &ss->regs->spbr);
+   writeb(0x01, &priv->regs->spbr);
 
/* Disable Dummy Data Transmission */
-   writeb(0x00, &ss->regs->spdcr);
+   writeb(0x00, &priv->regs->spdcr);
 
/* Set clock delay value */
-   writeb(0x00, &ss->regs->spckd);
+   writeb(0x00, &priv->regs->spckd);
 
/* Set SSL negation delay value */
-   writeb(0x00, &ss->regs->sslnd);
+   writeb(0x00, &priv->regs->sslnd);
 
/* Set next-access delay value */
-   writeb(0x00, &ss->regs->spnd);
+   writeb(0x00, &priv->regs->spnd);
 
/* Set equence command */
-   writew(SPCMD_INIT2, &ss->regs->spcmd0);
+   writew(SPCMD_INIT2, &priv->regs->spcmd0);
 
/* Reset transfer and receive Buffer */
-   setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
+   setbits_8(&priv->regs->spbfcr, SPBFCR_TXRST | SPBFCR_RXRST);
 
/* Clear transfer and receive Buffer control bit */
-   clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
+   clrbits_8(&priv->regs->spbfcr, SPBFCR_TXRST | SPBFCR_RXRST);
 
/* Set equence control method. Use equence0 only */
-   writeb(0x00, &ss->regs->spscr);
+   writeb(0x00, &priv->regs->spscr);
 
/* Enable SPI function */
-   setbits_8(&ss->regs->spcr, SPCR_SPE);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-   return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-   struct sh_qspi_slave *ss = to_sh_qspi(slave);
-
-   /* Set master mode only */
-   writeb(SPCR_MSTR, &ss->regs->spcr);
-
-   /* Set command */
-   writew(SPCMD_INIT1, &ss->regs->spcmd0);
-
-   /* Reset transfer and receive Buffer */
-   setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
-
-   /* Clear transfer and receive Buffer control bit */
-   clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
-
-   /* Set equence control method. Use equence0 only */
-   writeb(0x00, &ss->regs->spscr);
-
-   /* Enable SPI function */
-   setbits_8(&ss->regs->spcr, SPCR_SPE);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-   struct sh_qspi_slave *ss = to_sh_qspi(slave);
-
-   /* Disable SPI Function */
-   clrbits_8(&ss->regs->spcr, SPCR_SPE);
-}
-
-void spi_init(void)
-{
-   /* nothing to do */
+   setbits_8(&priv->regs->spcr, SPCR_SPE);
 }
 
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-   unsigned int max_hz, unsigned int mode)
+static int sh_qspi_set_speed(struct udevice *bus, uint hz)
 {
-   struct sh_qspi_slave *ss;
-
-   if (!spi_cs_is_valid(bus, cs))
-   return NULL;
-
-   ss = spi_alloc_s

[U-Boot] [PATCH] usb: f_mass_storage: Fix compile on x86

[Bryan O'Donoghue]

Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h

Fix that now by only compiling up the local definition of set_bit and
clear_bit only if not already provided by the environment.

Signed-off-by: Bryan O'Donoghue 
Cc: Lukasz Majewski 
Cc: Marek Vasut 
---
 drivers/usb/gadget/f_mass_storage.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/gadget/f_mass_storage.c 
b/drivers/usb/gadget/f_mass_storage.c
index 1ecb92ac6b..2e856af6ed 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -283,6 +283,7 @@ static const char fsg_string_interface[] = "Mass Storage";
 struct kref {int x; };
 struct completion {int x; };
 
+#ifndef _I386_BITOPS_H
 inline void set_bit(int nr, volatile void *addr)
 {
int mask;
@@ -302,6 +303,7 @@ inline void clear_bit(int nr, volatile void *addr)
mask = 1 << (nr & 0x1f);
*a &= ~mask;
 }
+#endif /* _I386_BITOPTS_H */
 
 struct fsg_dev;
 struct fsg_common;
-- 
2.17.0

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Re: [U-Boot] [PATCH 2/2] env: ti: android: boot with FIT Image

[Sam Protsenko]

On 26 April 2018 at 00:03, Praneeth Bajjuri  wrote:
> Boot android over emmc by default thru FIT image
>
> Signed-off-by: Praneeth Bajjuri 
> Suggested-by: Andrew F.Davis 
> ---

Reviewed-by: Sam Protsenko 

>  include/environment/ti/boot.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
> index 24b7783..a1767b4 100644
> --- a/include/environment/ti/boot.h
> +++ b/include/environment/ti/boot.h
> @@ -37,6 +37,7 @@
> "run mmcboot;\0" \
> "emmc_android_boot=" \
> "echo Trying to boot Android from eMMC ...; " \
> +   "run update_to_fit; " \
> "setenv eval_bootargs setenv bootargs $bootargs; " \
> "run eval_bootargs; " \
> "setenv mmcdev 1; " \
> @@ -49,7 +50,7 @@
> "part size mmc ${mmcdev} boot boot_size; " \
> "mmc read ${fdtaddr} ${fdt_start} ${fdt_size}; " \
> "mmc read ${loadaddr} ${boot_start} ${boot_size}; " \
> -   "bootm $loadaddr $loadaddr $fdtaddr;\0"
> +   "bootm ${loadaddr}#${fdtfile};\0 "
>
>  #ifdef CONFIG_OMAP54XX
>
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH 1/2] configs: TI: Enable FIT Library overlay support

[Sam Protsenko]

On 26 April 2018 at 00:03, Praneeth Bajjuri  wrote:
> Enable the FDT library overlay support for all TI SOC family.
>
> Without this option, when Loading fdt from FIT image, the
> following warning is seen.
>
> "config with overlays but CONFIG_OF_LIBFDT_OVERLAY not set".
>
> Signed-off-by: Praneeth Bajjuri 
> Suggested-by: Andrew F.Davis 

Reviewed-by: Sam Protsenko 

> ---
>  lib/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/lib/Kconfig b/lib/Kconfig
> index 436b90f..6d5306a 100644
> --- a/lib/Kconfig
> +++ b/lib/Kconfig
> @@ -252,6 +252,7 @@ config OF_LIBFDT
>
>  config OF_LIBFDT_OVERLAY
> bool "Enable the FDT library overlay support"
> +   default y if ARCH_OMAP2PLUS || ARCH_KEYSTONE
> help
>   This enables the FDT library (libfdt) overlay support.
>
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH] tools: zynqmpbif: Add support for load=after

[Alexander Graf]

On 04/26/2018 06:33 PM, Michal Simek wrote:

On 26.4.2018 13:37, Alexander Graf wrote:

Some times it's handy to have a partition loaded immediately after
the end of the previous blob. The most obvious example for this is
a U-Boot binary (coming from .elf) and a device tree file.

This patch adds that logic. With this, the following bif snippet
does what you would expect:

   [destination_cpu=a5x-0, exception_level=el-2] u-boot.elf
   [load=after] u-boot.dtb

converts to

   FSBL payload on CPU a5x-0 (PS):
 Offset : 0x00590500
 Size   : 577768 (0x8d0e8) bytes
 Load   : 0x0800
 Attributes : EL2
 Checksum   : 0xefca2cad
   FSBL payload on CPU none (PS):
 Offset : 0x0061d640
 Size   : 129760 (0x1fae0) bytes
 Load   : 0x0808d0e8 (entry=0x)
 Attributes : EL3
 Checksum   : 0xf7dd3d49

Signed-off-by: Alexander Graf 
---
  tools/zynqmpbif.c | 15 +++
  1 file changed, 15 insertions(+)

diff --git a/tools/zynqmpbif.c b/tools/zynqmpbif.c
index 6c8f66055d..47c233c15f 100644
--- a/tools/zynqmpbif.c
+++ b/tools/zynqmpbif.c
@@ -42,6 +42,7 @@ enum bif_flag {
BIF_FLAG_PUF_FILE,
BIF_FLAG_AARCH32,
BIF_FLAG_PART_OWNER_UBOOT,
+   BIF_FLAG_LOAD_AFTER,
  
  	/* Internal flags */

BIF_FLAG_BIT_FILE,
@@ -151,6 +152,11 @@ static char *parse_load(char *line, struct bif_entry *bf)
  {
char *endptr;
  
+	if (!strncmp(line, "after", strlen("after"))) {

+   bf->flags |= (1ULL << BIF_FLAG_LOAD_AFTER);
+   return line + strlen("after");
+   }
+
bf->load = strtoll(line, &endptr, 0);
  
  	return endptr;

@@ -336,6 +342,15 @@ static int bif_add_part(struct bif_entry *bf, const char 
*data, size_t len)
if (r)
return r;
  
+	if (bf->flags & (1ULL << BIF_FLAG_LOAD_AFTER) &&

+   bif_output.last_part) {
+   struct partition_header *p = bif_output.last_part;
+   uint64_t load = le64_to_cpu(p->load_address);
+
+   load += le32_to_cpu(p->len) * 4;
+   parthdr.load_address = cpu_to_le64(load);
+   }
+
parthdr.offset = cpu_to_le32(bf->offset / 4);
  
  	if (bf->flags & (1ULL << BIF_FLAG_BOOTLOADER)) {



As we have discussed over IRC this is out of current bif supported
options and load option with OF_SEPARATE/OF_BOARD should be used instead.
Some platforms are using CONFIG_SYS_FDT_BASE for that.
Generic solution for that would be good because right now is fdt_blob is
at &_end.


Yes, the &_end is what this patch enables to map in bif.


At least like this.

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 320ee1dc56b3..4262ac0677d3 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1292,8 +1292,12 @@ __weak void *board_fdt_blob_setup(void)
 else
 fdt_blob = (ulong *)&__bss_end;
  #else
+#ifndef CONFIG_SYS_FDT_BASE
 /* FDT is at end of image */
 fdt_blob = (ulong *)&_end;
+#else
+   fdt_blob = CONFIG_SYS_FDT_BASE;
+#endif


I agree that this is an alternative approach to this, but I like it much 
less :). It just feels wrong to hard code random addresses to load 
things from when everything is easy enough to pull out dynamically.


I'd much rather prefer to extend the official bif syntax with this. If 
we can't have that, I guess the next "best" option is to just create a 
combined .bin file and manually set the load/entry address from the elf 
header in my boot.bin generation script.



Alex

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Re: [U-Boot] [PATCH] tools: zynqmpbif: Add support for load=after

[Michal Simek]

On 26.4.2018 13:37, Alexander Graf wrote:
> Some times it's handy to have a partition loaded immediately after
> the end of the previous blob. The most obvious example for this is
> a U-Boot binary (coming from .elf) and a device tree file.
> 
> This patch adds that logic. With this, the following bif snippet
> does what you would expect:
> 
>   [destination_cpu=a5x-0, exception_level=el-2] u-boot.elf
>   [load=after] u-boot.dtb
> 
> converts to
> 
>   FSBL payload on CPU a5x-0 (PS):
> Offset : 0x00590500
> Size   : 577768 (0x8d0e8) bytes
> Load   : 0x0800
> Attributes : EL2
> Checksum   : 0xefca2cad
>   FSBL payload on CPU none (PS):
> Offset : 0x0061d640
> Size   : 129760 (0x1fae0) bytes
> Load   : 0x0808d0e8 (entry=0x)
> Attributes : EL3
> Checksum   : 0xf7dd3d49
> 
> Signed-off-by: Alexander Graf 
> ---
>  tools/zynqmpbif.c | 15 +++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/tools/zynqmpbif.c b/tools/zynqmpbif.c
> index 6c8f66055d..47c233c15f 100644
> --- a/tools/zynqmpbif.c
> +++ b/tools/zynqmpbif.c
> @@ -42,6 +42,7 @@ enum bif_flag {
>   BIF_FLAG_PUF_FILE,
>   BIF_FLAG_AARCH32,
>   BIF_FLAG_PART_OWNER_UBOOT,
> + BIF_FLAG_LOAD_AFTER,
>  
>   /* Internal flags */
>   BIF_FLAG_BIT_FILE,
> @@ -151,6 +152,11 @@ static char *parse_load(char *line, struct bif_entry *bf)
>  {
>   char *endptr;
>  
> + if (!strncmp(line, "after", strlen("after"))) {
> + bf->flags |= (1ULL << BIF_FLAG_LOAD_AFTER);
> + return line + strlen("after");
> + }
> +
>   bf->load = strtoll(line, &endptr, 0);
>  
>   return endptr;
> @@ -336,6 +342,15 @@ static int bif_add_part(struct bif_entry *bf, const char 
> *data, size_t len)
>   if (r)
>   return r;
>  
> + if (bf->flags & (1ULL << BIF_FLAG_LOAD_AFTER) &&
> + bif_output.last_part) {
> + struct partition_header *p = bif_output.last_part;
> + uint64_t load = le64_to_cpu(p->load_address);
> +
> + load += le32_to_cpu(p->len) * 4;
> + parthdr.load_address = cpu_to_le64(load);
> + }
> +
>   parthdr.offset = cpu_to_le32(bf->offset / 4);
>  
>   if (bf->flags & (1ULL << BIF_FLAG_BOOTLOADER)) {
> 

As we have discussed over IRC this is out of current bif supported
options and load option with OF_SEPARATE/OF_BOARD should be used instead.
Some platforms are using CONFIG_SYS_FDT_BASE for that.
Generic solution for that would be good because right now is fdt_blob is
at &_end.

At least like this.

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 320ee1dc56b3..4262ac0677d3 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1292,8 +1292,12 @@ __weak void *board_fdt_blob_setup(void)
else
fdt_blob = (ulong *)&__bss_end;
 #else
+#ifndef CONFIG_SYS_FDT_BASE
/* FDT is at end of image */
fdt_blob = (ulong *)&_end;
+#else
+   fdt_blob = CONFIG_SYS_FDT_BASE;
+#endif
 #endif
return fdt_blob;
 }

Thanks,
Michal
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Re: [U-Boot] [PATCH] arm64: zynqmp: Setup MMU map for DDR at run time

[Michal Simek]

On 26.4.2018 18:02, Alexander Graf wrote:
> On 04/26/2018 05:40 PM, Michal Simek wrote:
>> On 26.4.2018 17:21, Alexander Graf wrote:
>>> On 04/20/2018 09:46 AM, Michal Simek wrote:
 From: Nitin Jain 

 This patch used for filling the MMU map for DDR at run time based
 information read from Device Tree or automatically detected from static
 configuration.
>>> The sentence above is missing a word somewhere :).
>>>
>>> Also, the description doesn't actually tell me *why* this change is
>>> needed. What is the problem with the current static map? And what
>>> exactly changes really with this patch applied?
>> It is needed because for systems which has for example 1GB of memory but
>> you map 2GB there could be spurious accesses which we have seen in past
>> when mapping is not fitting with actual memory installed.
> 
> That makes sense. Can you please update the commit message?
> 

Sure.
M
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[U-Boot] [PATCH] test: dm: regmap: fix license header

[Masahiro Yamada]

Signed-off-by: Masahiro Yamada 
---

 test/dm/regmap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/test/dm/regmap.c b/test/dm/regmap.c
index 8125345..4b7dac1 100644
--- a/test/dm/regmap.c
+++ b/test/dm/regmap.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2015 Google, Inc
-2 *
+ *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-- 
2.7.4

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Re: [U-Boot] [PATCH v2 2/4] dm: ofnode: add ofnode_device_is_compatible() helper

[Masahiro Yamada]

Hi Simon,


2018-04-26 23:40 GMT+09:00 Simon Glass :
> Hi Masahiro,
>
> On 18 April 2018 at 21:14, Masahiro Yamada
>  wrote:
>> device_is_compatible() takes udevice, but there is no such a helper
>> that takes ofnode.
>>
>> Signed-off-by: Masahiro Yamada 
>> ---
>>
>> Changes in v2: None
>>
>>  drivers/core/device.c |  8 +---
>>  drivers/core/ofnode.c | 11 +++
>>  include/dm/ofnode.h   | 11 +++
>>  3 files changed, 23 insertions(+), 7 deletions(-)
>>
>
> Please can you add a simple test for this?

I wrote a simple test:

http://patchwork.ozlabs.org/patch/905181/

-- 
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[U-Boot] [PATCH] test: ofnode: test ofnode_device_is_compatible()

[Masahiro Yamada]

Test ofnode_device_is_compatible(), and also ofnode_path().

Requested-by: Simon Glass 
Signed-off-by: Masahiro Yamada 
---

 test/dm/Makefile |  1 +
 test/dm/ofnode.c | 19 +++
 2 files changed, 20 insertions(+)
 create mode 100644 test/dm/ofnode.c

diff --git a/test/dm/Makefile b/test/dm/Makefile
index 513c456..97c978a 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_DM_I2C) += i2c.o
 obj-$(CONFIG_LED) += led.o
 obj-$(CONFIG_DM_MAILBOX) += mailbox.o
 obj-$(CONFIG_DM_MMC) += mmc.o
+obj-y += ofnode.o
 obj-$(CONFIG_DM_PCI) += pci.o
 obj-$(CONFIG_PHY) += phy.o
 obj-$(CONFIG_POWER_DOMAIN) += power-domain.o
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
new file mode 100644
index 000..7dd6d88
--- /dev/null
+++ b/test/dm/ofnode.c
@@ -0,0 +1,19 @@
+/*
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static int dm_test_ofnode_compatible(struct unit_test_state *uts)
+{
+   ofnode root_node = ofnode_path("/");
+
+   ut_assert(ofnode_valid(root_node));
+   ut_assert(ofnode_device_is_compatible(root_node, "sandbox"));
+
+   return 0;
+}
+DM_TEST(dm_test_ofnode_compatible, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
-- 
2.7.4

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Re: [U-Boot] [PATCH] arm64: zynqmp: Setup MMU map for DDR at run time

[Alexander Graf]

On 04/26/2018 05:40 PM, Michal Simek wrote:

On 26.4.2018 17:21, Alexander Graf wrote:

On 04/20/2018 09:46 AM, Michal Simek wrote:

From: Nitin Jain 

This patch used for filling the MMU map for DDR at run time based
information read from Device Tree or automatically detected from static
configuration.

The sentence above is missing a word somewhere :).

Also, the description doesn't actually tell me *why* this change is
needed. What is the problem with the current static map? And what
exactly changes really with this patch applied?

It is needed because for systems which has for example 1GB of memory but
you map 2GB there could be spurious accesses which we have seen in past
when mapping is not fitting with actual memory installed.


That makes sense. Can you please update the commit message?


Thanks,

Alex

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Re: [U-Boot] [PATCH] arm64: zynqmp: Setup MMU map for DDR at run time

[Michal Simek]

On 26.4.2018 17:21, Alexander Graf wrote:
> On 04/20/2018 09:46 AM, Michal Simek wrote:
>> From: Nitin Jain 
>>
>> This patch used for filling the MMU map for DDR at run time based
>> information read from Device Tree or automatically detected from static
>> configuration.
> 
> The sentence above is missing a word somewhere :).
> 
> Also, the description doesn't actually tell me *why* this change is
> needed. What is the problem with the current static map? And what
> exactly changes really with this patch applied?

It is needed because for systems which has for example 1GB of memory but
you map 2GB there could be spurious accesses which we have seen in past
when mapping is not fitting with actual memory installed.

Thanks,
Michal

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Re: [U-Boot] [PATCH] regmap: add regmap_update_bits() helper

[Neil Armstrong]

Hi,

On 26/04/2018 16:40, Simon Glass wrote:
> Hi Neil,
> 
> On 23 April 2018 at 08:16, Neil Armstrong  wrote:
>> Add the regmap_update_bits() to simply the read/modify/write of registers
>> in a single command. The function is taken from Linux regmap
>> implementation.
>>
>> Signed-off-by: Neil Armstrong 
>> ---
>>  include/regmap.h | 23 +++
>>  1 file changed, 23 insertions(+)
>>
>> diff --git a/include/regmap.h b/include/regmap.h
>> index 493a5d8..3c463e9 100644
>> --- a/include/regmap.h
>> +++ b/include/regmap.h
>> @@ -47,6 +47,29 @@ int regmap_read(struct regmap *map, uint offset, uint 
>> *valp);
>> regmap_read(map, (uint32_t *)(ptr)->member - (uint32_t *)(ptr), valp)
>>
>>  /**
>> + * regmap_update_bits() - Perform a read/modify/write using a mask
>> + *
>> + * @map:   The map returned by regmap_init_mem*()
>> + * @offset:Offset of the memory
>> + * @mask:  Mask to apply to the read value
>> + * @val:   Value to apply to the value to write
>> + */
>> +static inline int regmap_update_bits(struct regmap *map, uint offset,
>> +uint mask, uint val)
> 
> Why is this inline? I think it would save code size to make it a
> normal function.

Seemed a good idea, but I'll move it to the uclass.

> 
> Also can you add a call to this function somewhere for sandbox, as a test?

I did not find any test for regmap_read/write for sandbox, or maybe I missed it.

> 
>> +{
>> +   uint reg;
>> +   int ret;
>> +
>> +   ret = regmap_read(map, offset, ®);
>> +   if (ret)
>> +   return ret;
>> +
>> +   reg &= ~mask;
>> +
>> +   return regmap_write(map, offset, reg | val);
>> +}
>> +
>> +/**
>>   * regmap_init_mem() - Set up a new register map that uses memory access
>>   *
>>   * Use regmap_uninit() to free it.
>> --
>> 2.7.4
>>
> 
> Regards,
> Simon
> 

Thanks,
Neil
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Re: [U-Boot] [PATCH] arm64: zynqmp: Setup MMU map for DDR at run time

[Alexander Graf]

On 04/20/2018 09:46 AM, Michal Simek wrote:

From: Nitin Jain 

This patch used for filling the MMU map for DDR at run time based
information read from Device Tree or automatically detected from static
configuration.


The sentence above is missing a word somewhere :).

Also, the description doesn't actually tell me *why* this change is 
needed. What is the problem with the current static map? And what 
exactly changes really with this patch applied?



Alex

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Re: [U-Boot] [RESEND][PATCH v1] phy: add support for STM32 usb phy controller

[Marek Vasut]

On 04/26/2018 04:23 PM, Patrice Chotard wrote:
> From: Christophe Kerello 
> 
> This patch adds phy tranceiver driver for STM32 USB PHY
> Controller (usbphyc) that provides dual port High-Speed
> phy for OTG (single port) and EHCI/OHCI host controller
> (two ports).
> One port of the phy is shared between the two USB controllers
> through a UTMI+ switch.
> 
> Signed-off-by: Christophe Kerello 
> Signed-off-by: Patrice Chotard 

[...]

> +struct pll_params {
> + u8 ndiv;
> + u16 frac;
> +};
> +
> +struct stm32_usbphyc {
> + fdt_addr_t base;
> + struct clk clk;
> + struct stm32_usbphyc_phy {
> + struct udevice *vdd;
> + struct udevice *vdda1v1;
> + struct udevice *vdda1v8;
> + int index;
> + bool init;
> + bool powered;
> + } phys[MAX_PHYS];

Shouldn't there be one driver instance per PHY ?

> +};
> +
> +void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params 
> *pll_params)
> +{
> + unsigned long long fvco, ndiv, frac;
> +
> + /*
> +  *| FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
> +  *| FVCO = 2880MHz
> +  *| NDIV = integer part of input bits to set the LDF
> +  *| FRACT = fractional part of input bits to set the LDF
> +  *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
> +  *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
> +  * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
> +  */
> + fvco = (unsigned long long)PLL_FVCO * 100; /* In Hz */
> +
> + ndiv = fvco;
> + do_div(ndiv, (clk_rate * 2));
> + pll_params->ndiv = (u8)ndiv;
> +
> + frac = fvco * (1 << 16);
> + do_div(frac, (clk_rate * 2));
> + frac = frac - (ndiv * (1 << 16));
> + pll_params->frac = (u16)frac;
> +}
> +
> +static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
> +{
> + struct pll_params pll_params;
> + u32 clk_rate = clk_get_rate(&usbphyc->clk);
> + u32 usbphyc_pll;
> +
> + if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
> + pr_debug("%s: input clk freq (%dHz) out of range\n",
> +  __func__, clk_rate);
> + return -EINVAL;
> + }
> +
> + stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
> +
> + usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
> + usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
> +
> + if (pll_params.frac) {
> + usbphyc_pll |= PLLFRACCTL;
> + usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
> +  & PLLFRACIN);
> + }
> +
> + writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
> +
> + pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,

dev_dbg

> +  clk_rate, pll_params.ndiv, pll_params.frac);
> +
> + return 0;
> +}
[...]

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2 0/7] arm: Introduce v7R support

[Alexander Graf]

On 04/26/2018 02:51 PM, Lokesh Vutla wrote:

The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded,
real-time systems. It implements the ARMv7-R architecture, and includes
Thumb-2 technology for optimum code density and processing throughput.

Except for MPU(Memory Protection Unit) and few CP15 registers, most of the
features are compatible with v7 architecture. This series adds minimal
support for v7-R architecture by reusing the v7 support. Also adding
support for MPU.

Travis-ci build report: 
https://travis-ci.org/lokeshvutla/u-boot/builds/371442638


Looks pretty clean to me :).

Reviewed-by: Alexander Graf 


Alex

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Re: [U-Boot] [PATCH] usb: f_mass_storage: Fix compile on x86

[Marek Vasut]

On 04/26/2018 04:41 PM, Bryan O'Donoghue wrote:
> Compiling the f_mass_storage driver for an x86 target results in a
> compilation error as set_bit and clear_bit are provided by bitops.h
> 
> Fix that now by only compiling up the local definition of set_bit and
> clear_bit only if not already provided by the environment.
> 
> Signed-off-by: Bryan O'Donoghue 
> Cc: Lukasz Majewski 
> Cc: Marek Vasut 
> ---
>  drivers/usb/gadget/f_mass_storage.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/usb/gadget/f_mass_storage.c 
> b/drivers/usb/gadget/f_mass_storage.c
> index 1ecb92ac6b..2e856af6ed 100644
> --- a/drivers/usb/gadget/f_mass_storage.c
> +++ b/drivers/usb/gadget/f_mass_storage.c
> @@ -283,6 +283,7 @@ static const char fsg_string_interface[] = "Mass Storage";
>  struct kref {int x; };
>  struct completion {int x; };
>  
> +#ifndef _I386_BITOPS_H
>  inline void set_bit(int nr, volatile void *addr)
>  {
>   int mask;
> @@ -302,6 +303,7 @@ inline void clear_bit(int nr, volatile void *addr)
>   mask = 1 << (nr & 0x1f);
>   *a &= ~mask;
>  }
> +#endif /* _I386_BITOPTS_H */

This doesn't look right, generic driver shouldn't contain arch-specific
fixup or ifdef. Can this be somehow abstracted out?

>  struct fsg_dev;
>  struct fsg_common;
> 


-- 
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[U-Boot] [RESEND][PATCH v1 1/4] power: regulator: stpmu1: Introduce stpmu1 driver

[Patrice Chotard]

From: Christophe Kerello 

Enable support for the regulator functions of the STPMU1X PMIC. The
driver implements get/set api for the various BUCKS and LDOs supported
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.

Signed-off-by: Christophe Kerello 
Signed-off-by: Patrick Delaunay 
Signed-off-by: Patrice Chotard 
---

 drivers/power/regulator/Kconfig  |   9 +
 drivers/power/regulator/Makefile |   1 +
 drivers/power/regulator/stpmu1.c | 670 +++
 3 files changed, 680 insertions(+)
 create mode 100644 drivers/power/regulator/stpmu1.c

diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 5b4ac10462b4..822cff6608b8 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -204,3 +204,12 @@ config DM_REGULATOR_TPS65910
The TPS65910 PMIC provides 4 SMPSs and 8 LDOs. This driver supports all
regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements
the get/set api for value and enable.
+
+config DM_REGULATOR_STPMU1
+   bool "Enable driver for STPMU1 regulators"
+   depends on DM_REGULATOR && PMIC_STPMU1
+   ---help---
+   Enable support for the regulator functions of the STPMU1 PMIC. The
+   driver implements get/set api for the various BUCKS and LDOs supported
+   by the PMIC device. This driver is controlled by a device tree node
+   which includes voltage limits.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index f7873ad27af1..d73a6e3577a9 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_PBIAS) += pbias_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
 obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMU1) += stpmu1.o
diff --git a/drivers/power/regulator/stpmu1.c b/drivers/power/regulator/stpmu1.c
new file mode 100644
index ..377958387b86
--- /dev/null
+++ b/drivers/power/regulator/stpmu1.c
@@ -0,0 +1,670 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author: Christophe Kerello 
+ *
+ * SPDX-License-Identifier:GPL-2.0+BSD-3-Clause
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct stpmu1_range {
+   int min_uv;
+   int min_sel;
+   int max_sel;
+   int step;
+};
+
+struct stpmu1_output_range {
+   const struct stpmu1_range *ranges;
+   int nbranges;
+};
+
+#define STPMU1_MODE(_id, _val, _name) { \
+   .id = _id,  \
+   .register_value = _val, \
+   .name = _name,  \
+}
+
+#define STPMU1_RANGE(_min_uv, _min_sel, _max_sel, _step) { \
+   .min_uv = _min_uv,  \
+   .min_sel = _min_sel,\
+   .max_sel = _max_sel,\
+   .step = _step,  \
+}
+
+#define STPMU1_OUTPUT_RANGE(_ranges, _nbranges) { \
+   .ranges = _ranges,  \
+   .nbranges = _nbranges,  \
+}
+
+static int stpmu1_output_find_uv(
+   int sel,
+   const struct stpmu1_output_range *output_range)
+{
+   const struct stpmu1_range *range;
+   int i;
+
+   for (i = 0, range = output_range->ranges;
+i < output_range->nbranges; i++, range++) {
+   if (sel >= range->min_sel && sel <= range->max_sel)
+   return range->min_uv +
+  (sel - range->min_sel) * range->step;
+   }
+
+   return -EINVAL;
+}
+
+static int stpmu1_output_find_sel(
+   int uv,
+   const struct stpmu1_output_range *output_range)
+{
+   const struct stpmu1_range *range;
+   int i;
+
+   for (i = 0, range = output_range->ranges;
+i < output_range->nbranges; i++, range++) {
+   if (uv == range->min_uv && !range->step)
+   return range->min_sel;
+
+   if (uv >= range->min_uv &&
+   uv <= range->min_uv +
+ (range->max_sel - range->min_sel) * range->step)
+   return range->min_sel +
+  (uv - range->min_uv) / range->step;
+   }
+
+   return -EINVAL;
+}
+
+/*
+ * BUCK regulators
+ */
+
+static const struct stpmu1_range buck1_ranges[] = {
+   STPMU1_RANGE(60, 0, 30, 25000),
+   STPMU1_RANGE(135, 31, 63, 0),
+};
+
+static const struct stpmu1_range buck2_ranges[] = {
+   STPMU1_RANGE(100, 0, 17, 0),
+   STPMU1_RANGE(105, 18, 19, 0),
+   STPMU1_RANGE(110, 20, 21, 0),
+   STPMU1_RANGE(115, 22, 23, 0),
+   STPMU1_RANGE(120, 24, 25, 0),
+   STPMU1_RANGE(125, 26, 27, 0),
+   STPMU1_RANGE(130, 28, 

[U-Boot] [RESEND][PATCH v1 0/4] Add STM32MP157 regulator driver

[Patrice Chotard]

This series :
  _ adds stpmu1 regulator driver
  _ enables regulator relative flags in stm32mp15_basic_defconfig
  _ updates pmic driver to bind regulator child nodes
  _ adds regulator nodes entry in DT


Christophe Kerello (1):
  power: regulator: stpmu1: Introduce stpmu1 driver

Patrice Chotard (3):
  power: pmic: stpmu1: Add regulator bindings
  ARM: dts: stm32mp157c-ed1: Add regulator node
  configs: stm32mp15_basic: Set regulator relative flags

 arch/arm/dts/stm32mp157c-ed1.dts| 272 +++
 configs/stm32mp15_basic_defconfig   |   5 +
 drivers/power/pmic/stpmu1.c |  34 ++
 drivers/power/regulator/Kconfig |   9 +
 drivers/power/regulator/Makefile|   1 +
 drivers/power/regulator/stpmu1.c| 670 
 include/dt-bindings/mfd/st,stpmu1.h |  60 
 7 files changed, 1051 insertions(+)
 create mode 100644 drivers/power/regulator/stpmu1.c
 create mode 100644 include/dt-bindings/mfd/st,stpmu1.h

-- 
1.9.1

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[U-Boot] [RESEND][PATCH v1 4/4] configs: stm32mp15_basic: Set regulator relative flags

[Patrice Chotard]

Enable DM_REGULATOR_STPMU1 flag to activate regulator
driver for STM32MP15 SoC and CMD_REGULATOR flag to be
able to set/get regulator state int U-boot command line.

Disable PMIC_CHILDREN as this flag is not needed in SPL
for STM32MP1.

Signed-off-by: Patrice Chotard 
---

 configs/stm32mp15_basic_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configs/stm32mp15_basic_defconfig 
b/configs/stm32mp15_basic_defconfig
index 4ab1d4c8b12c..b5a75563fc38 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -22,6 +22,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_ISO_PARTITION is not set
@@ -31,6 +32,10 @@ CONFIG_DM_MMC=y
 CONFIG_STM32_SDMMC2=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_STPMU1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STPMU1=y
 CONFIG_STM32_SERIAL=y
 # CONFIG_EFI_LOADER is not set
-- 
1.9.1

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[U-Boot] [RESEND][PATCH v1 3/4] ARM: dts: stm32mp157c-ed1: Add regulator node

[Patrice Chotard]

Add regulator nodes needed by stpmu1 regulator driver
Add vmmc-supply and vqmmc-supply regulator property for
sdmmc1 and sdmmc2.

Signed-off-by: Christophe Kerello 
Signed-off-by: Patrice Chotard 
---

 arch/arm/dts/stm32mp157c-ed1.dts| 272 
 include/dt-bindings/mfd/st,stpmu1.h |  60 
 2 files changed, 332 insertions(+)
 create mode 100644 include/dt-bindings/mfd/st,stpmu1.h

diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index 4b20fabb717a..76e384775252 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
model = "STMicroelectronics STM32MP157C pmic eval daughter";
@@ -23,6 +24,19 @@
memory {
reg = <0xC000 0x4000>;
};
+
+   sd_switch: regulator-sd_switch {
+   compatible = "regulator-gpio";
+   regulator-name = "sd_switch";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <290>;
+   regulator-type = "voltage";
+   regulator-always-on;
+
+   gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
+   gpios-states = <0>;
+   states = <180 0x1 290 0x0>;
+   };
 };
 
 &gpioa {
@@ -141,6 +155,262 @@
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
+
+   st,main_control_register = <0x04>;
+   st,vin_control_register = <0xc0>;
+   st,usb_control_register = <0x30>;
+
+   regulators {
+   compatible = "st,stpmu1-regulators";
+
+   ldo1-supply = <&v3v3>;
+   ldo2-supply = <&v3v3>;
+   ldo3-supply = <&vdd_ddr>;
+   ldo5-supply = <&v3v3>;
+   ldo6-supply = <&v3v3>;
+   pwr_sw1-supply = <&bst_out>;
+   pwr_sw2-supply = <&bst_out>;
+
+   vddcore: buck1 {
+   regulator-name = "vddcore";
+   regulator-min-microvolt = <80>;
+   regulator-max-microvolt = <135>;
+   regulator-always-on;
+   regulator-initial-mode = <2>;
+   regulator-over-current-protection;
+
+   regulator-state-standby {
+   regulator-on-in-suspend;
+   regulator-suspend-microvolt = <120>;
+   regulator-mode = <8>;
+   };
+   regulator-state-mem {
+   regulator-off-in-suspend;
+   };
+   regulator-state-disk {
+   regulator-off-in-suspend;
+   };
+   };
+
+   vdd_ddr: buck2 {
+   regulator-name = "vdd_ddr";
+   regulator-min-microvolt = <135>;
+   regulator-max-microvolt = <135>;
+   regulator-always-on;
+   regulator-initial-mode = <2>;
+   regulator-over-current-protection;
+
+   regulator-state-standby {
+   regulator-suspend-microvolt = <135>;
+   regulator-on-in-suspend;
+   regulator-mode = <8>;
+   };
+   regulator-state-mem {
+   regulator-suspend-microvolt = <135>;
+   regulator-on-in-suspend;
+   regulator-mode = <8>;
+   };
+   regulator-state-disk {
+   regulator-off-in-suspend;
+   };
+   };
+
+   vdd: buck3 {
+   regulator-name = "vdd";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   st,mask_reset;
+   regulator-initial-mode = <8>;
+   regulator-over-current-protection;
+
+   regulator-state-standby {
+   regulator-suspend-microvolt = <330>;
+   regulator-o

[U-Boot] [RESEND][PATCH v1 2/4] power: pmic: stpmu1: Add regulator bindings

[Patrice Chotard]

Add regulator bindings to get access to regulator managed
by drivers/power/regulator/stpmu1.c regulator driver.

Signed-off-by: Christophe Kerello 
Signed-off-by: Patrick Delaunay 
Signed-off-by: Patrice Chotard 
---

 drivers/power/pmic/stpmu1.c | 34 ++
 1 file changed, 34 insertions(+)

diff --git a/drivers/power/pmic/stpmu1.c b/drivers/power/pmic/stpmu1.c
index 4615365ea809..4a230ec163ae 100644
--- a/drivers/power/pmic/stpmu1.c
+++ b/drivers/power/pmic/stpmu1.c
@@ -13,6 +13,17 @@
 
 #define STMPU1_NUM_OF_REGS 0x100
 
+#ifndef CONFIG_SPL_BUILD
+static const struct pmic_child_info stpmu1_children_info[] = {
+   { .prefix = "ldo", .driver = "stpmu1_ldo" },
+   { .prefix = "buck", .driver = "stpmu1_buck" },
+   { .prefix = "vref_ddr", .driver = "stpmu1_vref_ddr" },
+   { .prefix = "pwr_sw", .driver = "stpmu1_pwr_sw" },
+   { .prefix = "boost", .driver = "stpmu1_boost" },
+   { },
+};
+#endif /* CONFIG_SPL_BUILD */
+
 static int stpmu1_reg_count(struct udevice *dev)
 {
return STMPU1_NUM_OF_REGS;
@@ -43,6 +54,28 @@ static int stpmu1_read(struct udevice *dev, uint reg, 
uint8_t *buff, int len)
return ret;
 }
 
+static int stpmu1_bind(struct udevice *dev)
+{
+#ifndef CONFIG_SPL_BUILD
+   ofnode regulators_node;
+   int children;
+
+   regulators_node = dev_read_subnode(dev, "regulators");
+   if (!ofnode_valid(regulators_node)) {
+   dev_dbg(dev, "regulators subnode not found!");
+   return -ENXIO;
+   }
+   dev_dbg(dev, "found regulators subnode\n");
+
+   children = pmic_bind_children(dev, regulators_node,
+ stpmu1_children_info);
+   if (!children)
+   dev_dbg(dev, "no child found\n");
+#endif /* CONFIG_SPL_BUILD */
+
+   return 0;
+}
+
 static struct dm_pmic_ops stpmu1_ops = {
.reg_count = stpmu1_reg_count,
.read = stpmu1_read,
@@ -58,5 +91,6 @@ U_BOOT_DRIVER(pmic_stpmu1) = {
.name = "stpmu1_pmic",
.id = UCLASS_PMIC,
.of_match = stpmu1_ids,
+   .bind = stpmu1_bind,
.ops = &stpmu1_ops,
 };
-- 
1.9.1

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Re: [U-Boot] [RESEND][PATCH v1 0/3] Add STM32MP157 regulator driver

[Patrice CHOTARD]

it misses one patch, sorry
i ressend it right now

Patrice

On 04/26/2018 04:42 PM, Patrice Chotard wrote:
> 
> This series :
>_ adds stpmu1 regulator driver
>_ enables regulator relative flags in stm32mp15_basic_defconfig
>_ updates pmic driver to bind regulator child nodes
>_ adds regulator nodes entry in DT
> 
> 
> Patrice Chotard (3):
>power: pmic: stpmu1: Add regulator bindings
>ARM: dts: stm32mp157c-ed1: Add regulator node
>configs: stm32mp15_basic: Set regulator relative flags
> 
>   arch/arm/dts/stm32mp157c-ed1.dts| 272 
> 
>   configs/stm32mp15_basic_defconfig   |   5 +
>   drivers/power/pmic/stpmu1.c |  34 +
>   include/dt-bindings/mfd/st,stpmu1.h |  60 
>   4 files changed, 371 insertions(+)
>   create mode 100644 include/dt-bindings/mfd/st,stpmu1.h
> 
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[U-Boot] [PATCH v1 10/11] ARM: dts: stm32: Add quadspi reset for stm32f746

[Patrice Chotard]

Add missing reset property in quadspi node.

Signed-off-by: Patrice Chotard 
---

 arch/arm/dts/stm32f746.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 8581df9a2778..4845279ccfca 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -92,6 +92,7 @@
interrupts = <92>;
spi-max-frequency = <10800>;
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
+   resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
status = "disabled";
};
usart1: serial@40011000 {
-- 
1.9.1

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[U-Boot] [PATCH v1 07/11] spi: stm32_qspi: Add chip select management

[Patrice Chotard]

From: Christophe Kerello 

Quad-SPI interface is able to manage 2 spi nor devices.
FSEL bit selects the flash memory to be addressed in single flash mode.

Signed-off-by: Christophe Kerello 
Signed-off-by: Patrice Chotard 
---

 drivers/spi/stm32_qspi.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 46915194f034..48b4dbce402b 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -160,6 +160,8 @@ enum STM32_QSPI_CCR_FMODE {
 #define STM32_CMD_READ_QUAD_OUTPUT_FAST0x6b
 #define STM32_CMD_QUAD_PP  0x32
 
+#define STM32_MAX_NORCHIP 2
+
 struct stm32_qspi_platdata {
u32 base;
u32 memory_map;
@@ -217,6 +219,12 @@ static void _stm32_qspi_set_flash_size(struct 
stm32_qspi_priv *priv, u32 size)
fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
 }
 
+static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
+{
+   clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
+   cs ? STM32_QSPI_CR_FSEL : 0);
+}
+
 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
 {
unsigned int ccr_reg = 0;
@@ -504,10 +512,17 @@ static int stm32_qspi_claim_bus(struct udevice *dev)
struct stm32_qspi_priv *priv;
struct udevice *bus;
struct spi_flash *flash;
+   struct dm_spi_slave_platdata *slave_plat;
 
bus = dev->parent;
priv = dev_get_priv(bus);
flash = dev_get_uclass_priv(dev);
+   slave_plat = dev_get_parent_platdata(dev);
+
+   if (slave_plat->cs >= STM32_MAX_NORCHIP)
+   return -ENODEV;
+
+   _stm32_qspi_set_cs(priv, slave_plat->cs);
 
_stm32_qspi_set_flash_size(priv, flash->size);
 
-- 
1.9.1

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[U-Boot] [PATCH v1 11/11] ARM: dts: stm32: Update qspi bindings for stm32f746

[Patrice Chotard]

Align qspi bindings following kernel dt-bindings
Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
from kernel v4.17-rc1.

Signed-off-by: Patrice Chotard 
---

 arch/arm/dts/stm32f746.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 4845279ccfca..afa7832f8936 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -88,7 +88,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0xA0001000 0x1000>, <0x9000 0x1000>;
-   reg-names = "QuadSPI", "QuadSPI-memory";
+   reg-names = "qspi", "qspi_mm";
interrupts = <92>;
spi-max-frequency = <10800>;
clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
-- 
1.9.1

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[U-Boot] [PATCH v1 09/11] spi: stm32_qspi: Add reset support

[Patrice Chotard]

In some situation, QSPI controller is already configured by an early
boot stage, adding reset support will insure that QSPI controller is
started from a pristine state.

Signed-off-by: Patrice Chotard 
---

 drivers/spi/stm32_qspi.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 897085f22a08..c4a65bcd6be6 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -464,6 +465,7 @@ static int stm32_qspi_probe(struct udevice *bus)
struct stm32_qspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
struct clk clk;
+   struct reset_ctl reset_ctl;
int ret;
 
dm_spi_bus = bus->uclass_priv;
@@ -491,6 +493,19 @@ static int stm32_qspi_probe(struct udevice *bus)
return priv->clock_rate;
}
 
+   ret = reset_get_by_index(bus, 0, &reset_ctl);
+   if (ret) {
+   if (ret != -ENOENT) {
+   dev_err(bus, "failed to get reset\n");
+   clk_disable(&clk);
+   return ret;
+   }
+   } else {
+   /* Reset QSPI controller */
+   reset_assert(&reset_ctl);
+   udelay(2);
+   reset_deassert(&reset_ctl);
+   }
 
setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 
-- 
1.9.1

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[U-Boot] [PATCH v1 04/11] spi: stm32_qspi: Align reg-names with kernel 4.12 RC1

[Patrice Chotard]

From: Christophe Kerello 

Align qspi bindings following kernel dt-bindings
Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
from kernel v4.12-rc1.

Signed-off-by: Christophe Kerello 
Signed-off-by: Patrice Chotard 
---

 drivers/spi/stm32_qspi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 7ce8afb91eb3..97026b33033e 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -421,13 +421,13 @@ static int stm32_qspi_ofdata_to_platdata(struct udevice 
*bus)
int ret;
 
ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-"QuadSPI", &res_regs);
+"qspi", &res_regs);
if (ret) {
debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
return -ENOMEM;
}
ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-"QuadSPI-memory", &res_mem);
+"qspi_mm", &res_mem);
if (ret) {
debug("Error: can't get mmap base address(ret = %d)!\n", ret);
return -ENOMEM;
-- 
1.9.1

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[U-Boot] [PATCH v1 08/11] spi: stm32_qspi: Use dev_read_xxx API

[Patrice Chotard]

Use dev_read_xxx() instead of old manner fdt_xxx() API

Signed-off-by: Patrice Chotard 
---

 drivers/spi/stm32_qspi.c | 17 ++---
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 48b4dbce402b..897085f22a08 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -17,8 +17,7 @@
 #include 
 #include 
 #include 
-
-DECLARE_GLOBAL_DATA_PTR;
+#include 
 
 struct stm32_qspi_regs {
u32 cr; /* 0x00 */
@@ -428,27 +427,23 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 
 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
 {
-   struct fdt_resource res_regs, res_mem;
+   struct resource res_regs, res_mem;
struct stm32_qspi_platdata *plat = bus->platdata;
-   const void *blob = gd->fdt_blob;
-   int node = dev_of_offset(bus);
int ret;
 
-   ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-"qspi", &res_regs);
+   ret = dev_read_resource_byname(bus, "qspi", &res_regs);
if (ret) {
debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
return -ENOMEM;
}
-   ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-"qspi_mm", &res_mem);
+   ret = dev_read_resource_byname(bus, "qspi_mm", &res_mem);
if (ret) {
debug("Error: can't get mmap base address(ret = %d)!\n", ret);
return -ENOMEM;
}
 
-   plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
-   STM32_QSPI_DEFAULT_SCK_FREQ);
+   plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency",
+   STM32_QSPI_DEFAULT_SCK_FREQ);
 
plat->base = res_regs.start;
plat->memory_map = res_mem.start;
-- 
1.9.1

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[U-Boot] [PATCH v1 03/11] spi: stm32_qspi: Sort include files alphabetically

[Patrice Chotard]

Sort include files by alphabetical order

Signed-off-by: Patrice Chotard 
---

 drivers/spi/stm32_qspi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 4977b89548d7..7ce8afb91eb3 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -9,14 +9,14 @@
  */
 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
-#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-- 
1.9.1

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[U-Boot] [PATCH v1 02/11] spi: stm32_qspi: Solve issue detected by checkpatch

[Patrice Chotard]

From: Patrick Delaunay 

Fix parameters function alingemnt
Fix variable declaration

Signed-off-by: Patrick Delaunay 
Signed-off-by: Patrice Chotard 
---

 drivers/spi/stm32_qspi.c | 31 ++-
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index b54b314a4921..4977b89548d7 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -207,6 +207,7 @@ static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv 
*priv)
 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
 {
u32 fsize = fls(size) - 1;
+
clrsetbits_le32(&priv->regs->dcr,
STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
@@ -256,13 +257,15 @@ static unsigned int _stm32_qspi_gen_ccr(struct 
stm32_qspi_priv *priv)
 }
 
 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
-   struct spi_flash *flash)
+   struct spi_flash *flash)
 {
+   unsigned int ccr_reg;
+
priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
| CMD_HAS_DUMMY;
priv->dummycycles = flash->dummy_byte * 8;
 
-   unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv);
+   ccr_reg = _stm32_qspi_gen_ccr(priv);
ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
 
_stm32_qspi_wait_for_not_busy(priv);
@@ -292,10 +295,12 @@ static void _stm32_qspi_start_xfer(struct stm32_qspi_priv 
*priv, u32 cr_reg)
 }
 
 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
-   struct spi_flash *flash, unsigned int bitlen,
-   const u8 *dout, u8 *din, unsigned long flags)
+   struct spi_flash *flash, unsigned int bitlen,
+   const u8 *dout, u8 *din, unsigned long flags)
 {
unsigned int words = bitlen / 8;
+   u32 ccr_reg;
+   int i;
 
if (flags & SPI_XFER_MMAP) {
_stm32_qspi_enable_mmap(priv, flash);
@@ -347,7 +352,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
}
 
if (flags & SPI_XFER_END) {
-   u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
+   ccr_reg = _stm32_qspi_gen_ccr(priv);
ccr_reg |= STM32_QSPI_CCR_IND_WRITE
<< STM32_QSPI_CCR_FMODE_SHIFT;
 
@@ -366,7 +371,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 
debug("%s: words:%d data:", __func__, words);
 
-   int i = 0;
+   i = 0;
while (words > i) {
writeb(dout[i], &priv->regs->dr);
debug("%02x ", dout[i]);
@@ -380,7 +385,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
}
}
} else if (din) {
-   u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
+   ccr_reg = _stm32_qspi_gen_ccr(priv);
ccr_reg |= STM32_QSPI_CCR_IND_READ
<< STM32_QSPI_CCR_FMODE_SHIFT;
 
@@ -395,7 +400,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 
debug("%s: data:", __func__);
 
-   int i = 0;
+   i = 0;
while (words > i) {
din[i] = readb(&priv->regs->dr);
debug("%02x ", din[i]);
@@ -519,7 +524,7 @@ static int stm32_qspi_release_bus(struct udevice *dev)
 }
 
 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
-   const void *dout, void *din, unsigned long flags)
+  const void *dout, void *din, unsigned long flags)
 {
struct stm32_qspi_priv *priv;
struct udevice *bus;
@@ -537,12 +542,13 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint 
speed)
 {
struct stm32_qspi_platdata *plat = bus->platdata;
struct stm32_qspi_priv *priv = dev_get_priv(bus);
+   u32 qspi_clk = priv->clock_rate;
+   u32 prescaler = 255;
+   u32 csht;
 
if (speed > plat->max_hz)
speed = plat->max_hz;
 
-   u32 qspi_clk = priv->clock_rate;
-   u32 prescaler = 255;
if (speed > 0) {
prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
if (prescaler > 255)
@@ -551,7 +557,7 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint 
speed)
prescaler = 0;
}
 
-   u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 1);
+   csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 1);
csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
 
_stm32_qspi_wait_for_not_busy(priv);
@@ -561,7 +567,6 @@ stat

[U-Boot] [PATCH v1 05/11] spi: stm32_qspi: Add st, stm32f469-qspi compatible string

[Patrice Chotard]

From: Christophe Kerello 

Add "st,stm32f469-qspi" compatible which is used on kernel side.
This will be necessary when DT will be synchronised from kernel.

Signed-off-by: Christophe Kerello 
Signed-off-by: Patrice Chotard 
---

 drivers/spi/stm32_qspi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 97026b33033e..6b7232905bc8 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -636,6 +636,7 @@ static const struct dm_spi_ops stm32_qspi_ops = {
 
 static const struct udevice_id stm32_qspi_ids[] = {
{ .compatible = "st,stm32-qspi" },
+   { .compatible = "st,stm32f469-qspi" },
{ }
 };
 
-- 
1.9.1

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[U-Boot] [PATCH v1 06/11] spi: stm32_qspi: Update mode management

[Patrice Chotard]

From: Christophe Kerello 

We face issue on Macronix/Spansion spi nors due to bad mode management.
We solve these issues using following mode configurations:
 - read_cmd = CMD_READ_QUAD_OUTPUT_FAST => 1-1-4
 - read_cmd = CMD_READ_DUAL_OUTPUT_FAST => 1-1-2
 - write_cmd = CMD_QUAD_PAGE_PROGRAM => 1-1-4
 - others commands => 1-1-1

Signed-off-by: Christophe Kerello 
Signed-off-by: Patrice Chotard 
---

 drivers/spi/stm32_qspi.c | 30 ++
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 6b7232905bc8..46915194f034 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -156,6 +156,10 @@ enum STM32_QSPI_CCR_FMODE {
 /* default SCK frequency, unit: HZ */
 #define STM32_QSPI_DEFAULT_SCK_FREQ 10800
 
+#define STM32_CMD_READ_DUAL_OUTPUT_FAST0x3b
+#define STM32_CMD_READ_QUAD_OUTPUT_FAST0x6b
+#define STM32_CMD_QUAD_PP  0x32
+
 struct stm32_qspi_platdata {
u32 base;
u32 memory_map;
@@ -217,26 +221,28 @@ static unsigned int _stm32_qspi_gen_ccr(struct 
stm32_qspi_priv *priv)
 {
unsigned int ccr_reg = 0;
u8 imode, admode, dmode;
-   u32 mode = priv->mode;
u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
 
imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
 
-   if (mode & SPI_RX_QUAD) {
+   /*
+* Based on mtd spi framework,
+* read_cmd = CMD_READ_QUAD_OUTPUT_FAST if (mode & SPI_RX_QUAD)
+* read_cmd = CMD_READ_DUAL_OUTPUT_FAST if (mode & SPI_RX_DUAL)
+* write_cmd = CMD_QUAD_PAGE_PROGRAM if (mode & SPI_TX_QUAD)
+*/
+   switch (cmd) {
+   case STM32_CMD_READ_QUAD_OUTPUT_FAST:
+   case STM32_CMD_QUAD_PP:
dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
-   if (mode & SPI_TX_QUAD) {
-   imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
-   admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
-   }
-   } else if (mode & SPI_RX_DUAL) {
+   break;
+   case STM32_CMD_READ_DUAL_OUTPUT_FAST:
dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
-   if (mode & SPI_TX_DUAL) {
-   imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
-   admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
-   }
-   } else {
+   break;
+   default:
dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
+   break;
}
 
if (priv->command & CMD_HAS_DATA)
-- 
1.9.1

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[U-Boot] [PATCH v1 01/11] spi: stm32_qspi: Remove CONFIG_CLK flag

[Patrice Chotard]

As all platforms which uses this driver have CONFIG_CLK flag
enable in their defconfig, we can remove it from driver code.

Signed-off-by: Patrice Chotard 
---

 drivers/spi/stm32_qspi.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 558708a4a7b0..b54b314a4921 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -449,6 +449,8 @@ static int stm32_qspi_probe(struct udevice *bus)
struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
struct stm32_qspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
+   struct clk clk;
+   int ret;
 
dm_spi_bus = bus->uclass_priv;
 
@@ -458,9 +460,6 @@ static int stm32_qspi_probe(struct udevice *bus)
 
priv->max_hz = plat->max_hz;
 
-#ifdef CONFIG_CLK
-   int ret;
-   struct clk clk;
ret = clk_get_by_index(bus, 0, &clk);
if (ret < 0)
return ret;
@@ -478,7 +477,6 @@ static int stm32_qspi_probe(struct udevice *bus)
return priv->clock_rate;
}
 
-#endif
 
setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 
-- 
1.9.1

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[U-Boot] [PATCH v1 00/11] Update STM32 QSPI driver

[Patrice Chotard]

This series :
  _ removes useless CONFIG_CLK flag
  _ fixes checkpatch warnings
  _ sorts include files in alphabetical order
  _ align DT bindings with kernel in DT and in driver code
  _ updates mode management
  _ add chip select management
  _ uses dev_read_xxx API
  _ add reset support



Christophe Kerello (4):
  spi: stm32_qspi: Align reg-names with kernel 4.12 RC1
  spi: stm32_qspi: Add st,stm32f469-qspi compatible string
  spi: stm32_qspi: Update mode management
  spi: stm32_qspi: Add chip select management

Patrice Chotard (6):
  spi: stm32_qspi: Remove CONFIG_CLK flag
  spi: stm32_qspi: Sort include files alphabetically
  spi: stm32_qspi: Use dev_read_xxx API
  spi: stm32_qspi: Add reset support
  ARM: dts: stm32: Add quadspi reset for stm32f746
  ARM: dts: stm32: Update qspi bindings for stm32f746

Patrick Delaunay (1):
  spi: stm32_qspi: Solve issue detected by checkpatch

 arch/arm/dts/stm32f746.dtsi |   3 +-
 drivers/spi/stm32_qspi.c| 121 
 2 files changed, 80 insertions(+), 44 deletions(-)

-- 
1.9.1

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[U-Boot] [RESEND][PATCH v1 1/4] power: regulator: Add support for stm32-vrefbuf

[Patrice Chotard]

From: Fabrice Gasnier 

Add regulator driver for STM32 voltage reference buffer which can be
used as voltage reference for ADCs, DACs and external components through
dedicated VREF+ pin.

Signed-off-by: Fabrice Gasnier 
Signed-off-by: Patrice Chotard 
---

 .../regulator/st,stm32-vrefbuf.txt |  23 +++
 drivers/power/regulator/Kconfig|   9 ++
 drivers/power/regulator/Makefile   |   1 +
 drivers/power/regulator/stm32-vrefbuf.c| 156 +
 4 files changed, 189 insertions(+)
 create mode 100644 doc/device-tree-bindings/regulator/st,stm32-vrefbuf.txt
 create mode 100644 drivers/power/regulator/stm32-vrefbuf.c

diff --git a/doc/device-tree-bindings/regulator/st,stm32-vrefbuf.txt 
b/doc/device-tree-bindings/regulator/st,stm32-vrefbuf.txt
new file mode 100644
index ..0f6b6feda33f
--- /dev/null
+++ b/doc/device-tree-bindings/regulator/st,stm32-vrefbuf.txt
@@ -0,0 +1,23 @@
+STM32 VREFBUF - Voltage reference buffer
+
+Some STM32 devices embed a voltage reference buffer which can be used as
+voltage reference for ADCs, DACs and also as voltage reference for external
+components through the dedicated VREF+ pin.
+
+Required properties:
+- compatible:  Must be "st,stm32-vrefbuf".
+- reg: Offset and length of VREFBUF register set.
+- clocks:  Must contain an entry for peripheral clock.
+
+Optional properties:
+- vdda-supply: Phandle to the parent vdda supply regulator node.
+
+Example:
+   vrefbuf: regulator@58003c00 {
+   compatible = "st,stm32-vrefbuf";
+   reg = <0x58003C00 0x8>;
+   clocks = <&rcc VREF_CK>;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <250>;
+   vdda-supply = <&vdda>;
+   };
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 822cff6608b8..414f4a53f786 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -197,6 +197,15 @@ config DM_REGULATOR_LP87565
be configured in multi phase modes. The driver implements
get/set api for value and enable.
 
+config DM_REGULATOR_STM32_VREFBUF
+   bool "Enable driver for STMicroelectronics STM32 VREFBUF"
+   depends on DM_REGULATOR && (STM32H7 || ARCH_STM32MP)
+   help
+   This driver supports STMicroelectronics STM32 VREFBUF (voltage
+   reference buffer) which can be used as voltage reference for
+   internal ADCs, DACs and also for external components through
+   dedicated Vref+ pin.
+
 config DM_REGULATOR_TPS65910
bool "Enable driver for TPS65910 PMIC regulators"
depends on DM_PMIC_TPS65910
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index d73a6e3577a9..16208af0694b 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -22,5 +22,6 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_PBIAS) += pbias_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o
 obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMU1) += stpmu1.o
diff --git a/drivers/power/regulator/stm32-vrefbuf.c 
b/drivers/power/regulator/stm32-vrefbuf.c
new file mode 100644
index ..eeb055cc6321
--- /dev/null
+++ b/drivers/power/regulator/stm32-vrefbuf.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author: Fabrice Gasnier 
+ *
+ * Originally based on the Linux kernel v4.16 drivers/regulator/stm32-vrefbuf.c
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* STM32 VREFBUF registers */
+#define STM32_VREFBUF_CSR  0x00
+
+/* STM32 VREFBUF CSR bitfields */
+#define STM32_VRS  GENMASK(6, 4)
+#define STM32_VRS_SHIFT4
+#define STM32_VRR  BIT(3)
+#define STM32_HIZ  BIT(1)
+#define STM32_ENVR BIT(0)
+
+struct stm32_vrefbuf {
+   void __iomem *base;
+   struct clk clk;
+   struct udevice *vdda_supply;
+};
+
+static const unsigned int stm32_vrefbuf_voltages[] = {
+   /* Matches resp. VRS = 000b, 001b, 010b, 011b */
+   250, 2048000, 180, 150,
+};
+
+static int stm32_vrefbuf_set_enable(struct udevice *dev, bool enable)
+{
+   struct stm32_vrefbuf *priv = dev_get_priv(dev);
+   u32 val;
+   int ret;
+
+   clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_HIZ | STM32_ENVR,
+   enable ? STM32_ENVR : STM32_HIZ);
+   if (!enable)
+   return 0;
+
+   /*
+* Vrefbuf startup time depends on externa

[U-Boot] [RESEND][PATCH v1 0/4] Add STM32 VREFBUF regulator driver

[Patrice Chotard]

This series :
  _ adds STM32 VREFBUF regulator driver
  _ adds VREFBUF clock gating
  _ enables STM32_VREFBUF flag in stm32mp15_basic_defconfig
  _ adds VREFBUF DT node


Fabrice Gasnier (3):
  power: regulator: Add support for stm32-vrefbuf
  clk: stm32mp1: Add VREF clock gating
  configs: stm32mp15: Enable STM32_VREFBUF flag

Patrice Chotard (1):
  ARM: dts: stm32mp157: Add vrefbuf DT node

 arch/arm/dts/stm32mp157.dtsi   |   9 ++
 configs/stm32mp15_basic_defconfig  |   1 +
 .../regulator/st,stm32-vrefbuf.txt |  23 +++
 drivers/clk/clk_stm32mp1.c |   3 +
 drivers/power/regulator/Kconfig|   9 ++
 drivers/power/regulator/Makefile   |   1 +
 drivers/power/regulator/stm32-vrefbuf.c| 156 +
 7 files changed, 202 insertions(+)
 create mode 100644 doc/device-tree-bindings/regulator/st,stm32-vrefbuf.txt
 create mode 100644 drivers/power/regulator/stm32-vrefbuf.c

-- 
1.9.1

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[U-Boot] [RESEND][PATCH v1 3/4] configs: stm32mp15: Enable STM32_VREFBUF flag

[Patrice Chotard]

From: Fabrice Gasnier 

Enable vrefbuf on stm32mp15, to be used by ADC.

Signed-off-by: Fabrice Gasnier 
Signed-off-by: Patrice Chotard 
---

 configs/stm32mp15_basic_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/stm32mp15_basic_defconfig 
b/configs/stm32mp15_basic_defconfig
index 195efa1ce06d..b1c3690c0094 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -36,6 +36,7 @@ CONFIG_DM_PMIC=y
 CONFIG_PMIC_STPMU1=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STM32_VREFBUF=y
 CONFIG_DM_REGULATOR_STPMU1=y
 CONFIG_STM32_SERIAL=y
 # CONFIG_EFI_LOADER is not set
-- 
1.9.1

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[U-Boot] [RESEND][PATCH v1 4/4] ARM: dts: stm32mp157: Add vrefbuf DT node

[Patrice Chotard]

Add vrefbuf device tree node. This allows to get
a voltage reference for ADCs.

Signed-off-by: Patrice Chotard 
---

 arch/arm/dts/stm32mp157.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
index b84899a1ea94..4b65d41f38cb 100644
--- a/arch/arm/dts/stm32mp157.dtsi
+++ b/arch/arm/dts/stm32mp157.dtsi
@@ -123,6 +123,15 @@
};
};
 
+   vrefbuf: vrefbuf@50025000 {
+   compatible = "st,stm32-vrefbuf";
+   reg = <0x50025000 0x8>;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <250>;
+   clocks = <&rcc_clk VREF>;
+   status = "disabled";
+   };
+
pinctrl: pin-controller {
compatible = "st,stm32mp157-pinctrl";
#address-cells = <1>;
-- 
1.9.1

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[U-Boot] [RESEND][PATCH v1 2/4] clk: stm32mp1: Add VREF clock gating

[Patrice Chotard]

From: Fabrice Gasnier 

Add VREF clock gating, that may be used by STM32 VREFBUF regulator.

Signed-off-by: Fabrice Gasnier 
Signed-off-by: Patrice Chotard 
---

 drivers/clk/clk_stm32mp1.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index c67aa444735a..97e9c12dd248 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -101,6 +101,7 @@
 #define RCC_USBCKSELR  0x91C
 #define RCC_MP_APB1ENSETR  0xA00
 #define RCC_MP_APB2ENSETR  0XA08
+#define RCC_MP_APB3ENSETR  0xA10
 #define RCC_MP_AHB2ENSETR  0xA18
 #define RCC_MP_AHB4ENSETR  0xA28
 
@@ -509,6 +510,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = 
{
 
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 
+   STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
+
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
-- 
1.9.1

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[U-Boot] [RESEND][PATCH v1 1/2] stm32mp: regulator: add SoC pwr regulator support

[Patrice Chotard]

From: Patrick Delaunay 

This driver binds and manages the following regulator of
SoC's PWR block :
  - reg11
  - reg18
  - usb33

Signed-off-by: Patrick Delaunay 
Signed-off-by: Patrice Chotard 
---

 arch/arm/mach-stm32mp/Makefile |   1 +
 arch/arm/mach-stm32mp/include/mach/stm32.h |   1 +
 arch/arm/mach-stm32mp/pwr_regulator.c  | 275 +
 arch/arm/mach-stm32mp/syscon.c |   2 +
 4 files changed, 279 insertions(+)
 create mode 100644 arch/arm/mach-stm32mp/pwr_regulator.c

diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index a495c53be8ca..83e8e64b7e5a 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -9,3 +9,4 @@ obj-y += dram_init.o
 obj-y += syscon.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h 
b/arch/arm/mach-stm32mp/include/mach/stm32.h
index c7a27894c451..91dc58d82df2 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -29,6 +29,7 @@
 enum {
STM32MP_SYSCON_UNKNOWN,
STM32MP_SYSCON_STGEN,
+   STM32MP_SYSCON_PWR,
 };
 
 /*
diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c 
b/arch/arm/mach-stm32mp/pwr_regulator.c
new file mode 100644
index ..187ffc092ce7
--- /dev/null
+++ b/arch/arm/mach-stm32mp/pwr_regulator.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:GPL-2.0+BSD-3-Clause
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define STM32MP_PWR_CR3 0xc
+#define STM32MP_PWR_CR3_USB33DEN BIT(24)
+#define STM32MP_PWR_CR3_USB33RDY BIT(26)
+#define STM32MP_PWR_CR3_REG18DEN BIT(28)
+#define STM32MP_PWR_CR3_REG18RDY BIT(29)
+#define STM32MP_PWR_CR3_REG11DEN BIT(30)
+#define STM32MP_PWR_CR3_REG11RDY BIT(31)
+
+struct stm32mp_pwr_reg_info {
+   u32 enable;
+   u32 ready;
+   char *name;
+};
+
+struct stm32mp_pwr_priv {
+   struct regmap *regmap;
+};
+
+static int stm32mp_pwr_write(struct udevice *dev, u8 reg,
+const u8 *buff, int len)
+{
+   struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
+   u32 val = *(u32 *)buff;
+
+   if (len != 4)
+   return -EINVAL;
+
+   return regmap_write(priv->regmap, STM32MP_PWR_CR3, val);
+}
+
+static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff,
+   int len)
+{
+   struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
+
+   if (len != 4)
+   return -EINVAL;
+
+   return regmap_read(priv->regmap, STM32MP_PWR_CR3, (u32 *)buff);
+}
+
+static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev)
+{
+   struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
+   struct regmap *regmap;
+
+   regmap = syscon_get_regmap_by_driver_data(STM32MP_SYSCON_PWR);
+   if (IS_ERR(regmap)) {
+   pr_err("%s: unable to find regmap (%ld)\n", __func__,
+  PTR_ERR(regmap));
+   return PTR_ERR(regmap);
+   }
+   priv->regmap = regmap;
+
+   return 0;
+}
+
+static const struct pmic_child_info pwr_children_info[] = {
+   { .prefix = "reg", .driver = "stm32mp_pwr_regulator"},
+   { .prefix = "usb", .driver = "stm32mp_pwr_regulator"},
+   { },
+};
+
+static int stm32mp_pwr_bind(struct udevice *dev)
+{
+   int children;
+
+   children = pmic_bind_children(dev, dev->node, pwr_children_info);
+   if (!children)
+   dev_dbg(dev, "no child found\n");
+
+   return 0;
+}
+
+static struct dm_pmic_ops stm32mp_pwr_ops = {
+   .read = stm32mp_pwr_read,
+   .write = stm32mp_pwr_write,
+};
+
+static const struct udevice_id stm32mp_pwr_ids[] = {
+   { .compatible = "st,stm32mp1,pwr-reg" },
+   { }
+};
+
+U_BOOT_DRIVER(stm32mp_pwr_pmic) = {
+   .name = "stm32mp_pwr_pmic",
+   .id = UCLASS_PMIC,
+   .of_match = stm32mp_pwr_ids,
+   .bind = stm32mp_pwr_bind,
+   .ops = &stm32mp_pwr_ops,
+   .ofdata_to_platdata = stm32mp_pwr_ofdata_to_platdata,
+   .priv_auto_alloc_size = sizeof(struct stm32mp_pwr_priv),
+};
+
+static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = {
+   .enable = STM32MP_PWR_CR3_REG11DEN,
+   .ready = STM32MP_PWR_CR3_REG11RDY,
+   .name = "reg11"
+};
+
+static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg18 = {
+   .enable = STM32MP_PWR_CR3_REG18DEN,
+   .ready = STM32MP_PWR_CR3_REG18RDY,
+   .name = "reg18"
+};
+
+static const struct stm32mp_pwr_reg_info stm32mp_pwr_usb33 = {
+   .enable = STM32MP_PWR_CR3_USB33DEN,
+   .ready = STM32MP_PWR_CR3_USB33RDY,
+   .name = "usb33"
+};
+
+static const struct stm32mp_pwr_reg_info *stm32mp_pwr_reg_infos[] = {
+   &stm32mp_pwr_reg11,
+   &stm32mp_pwr_reg18,
+   &stm32mp_pwr_usb33,
+   NULL
+};
+
+stat

[U-Boot] [RESEND][PATCH v1 2/2] ARM: dts: stm32mp157: Add SoC pwr regulator entry

[Patrice Chotard]

Add SoC power regulator entry for reg11, reg18 and usb33
regulator.

Signed-off-by: Patrice Chotard 
---

 arch/arm/dts/stm32mp157.dtsi | 33 +
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
index b84899a1ea94..a798144de2b7 100644
--- a/arch/arm/dts/stm32mp157.dtsi
+++ b/arch/arm/dts/stm32mp157.dtsi
@@ -123,6 +123,39 @@
};
};
 
+   pwr: pwr@50001000 {
+   compatible = "st,stm32mp1-pwr", "st,stm32-pwr", 
"syscon", "simple-mfd";
+   reg = <0x50001000 0x400>;
+   system-power-controller;
+   interrupts = ;
+   st,sysrcc = <&rcc>;
+   clocks = <&rcc_clk PLL2_R>;
+   clock-names = "phyclk";
+
+   pwr-regulators@c {
+   compatible = "st,stm32mp1,pwr-reg";
+   st,tzcr = <&rcc 0x0 0x1>;
+
+   reg11: reg11 {
+   regulator-name = "reg11";
+   regulator-min-microvolt = <110>;
+   regulator-max-microvolt = <110>;
+   };
+
+   reg18: reg18 {
+   regulator-name = "reg18";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   };
+
+   usb33: usb33 {
+   regulator-name = "usb33";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+   };
+   };
+
pinctrl: pin-controller {
compatible = "st,stm32mp157-pinctrl";
#address-cells = <1>;
-- 
1.9.1

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[U-Boot] [RESEND][PATCH v1 0/2] Add STM32MP157 SoC Power regulator

[Patrice Chotard]

This series :
   _ adds stmpu157 SoC power regulator driver
   _ populates DT with SoC power regulator entry


Patrice Chotard (1):
  ARM: dts: stm32mp157: Add SoC pwr regulator entry

Patrick Delaunay (1):
  stm32mp: regulator: add SoC pwr regulator support

 arch/arm/dts/stm32mp157.dtsi   |  33 
 arch/arm/mach-stm32mp/Makefile |   1 +
 arch/arm/mach-stm32mp/include/mach/stm32.h |   1 +
 arch/arm/mach-stm32mp/pwr_regulator.c  | 275 +
 arch/arm/mach-stm32mp/syscon.c |   2 +
 5 files changed, 312 insertions(+)
 create mode 100644 arch/arm/mach-stm32mp/pwr_regulator.c

-- 
1.9.1

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[U-Boot] [RESEND][PATCH v1 2/3] ARM: dts: stm32mp157c-ed1: Add regulator node

[Patrice Chotard]

Add regulator nodes needed by stpmu1 regulator driver
Add vmmc-supply and vqmmc-supply regulator property for
sdmmc1 and sdmmc2.

Signed-off-by: Christophe Kerello 
Signed-off-by: Patrice Chotard 
---

 arch/arm/dts/stm32mp157c-ed1.dts| 272 
 include/dt-bindings/mfd/st,stpmu1.h |  60 
 2 files changed, 332 insertions(+)
 create mode 100644 include/dt-bindings/mfd/st,stpmu1.h

diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index 4b20fabb717a..76e384775252 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
model = "STMicroelectronics STM32MP157C pmic eval daughter";
@@ -23,6 +24,19 @@
memory {
reg = <0xC000 0x4000>;
};
+
+   sd_switch: regulator-sd_switch {
+   compatible = "regulator-gpio";
+   regulator-name = "sd_switch";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <290>;
+   regulator-type = "voltage";
+   regulator-always-on;
+
+   gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
+   gpios-states = <0>;
+   states = <180 0x1 290 0x0>;
+   };
 };
 
 &gpioa {
@@ -141,6 +155,262 @@
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
+
+   st,main_control_register = <0x04>;
+   st,vin_control_register = <0xc0>;
+   st,usb_control_register = <0x30>;
+
+   regulators {
+   compatible = "st,stpmu1-regulators";
+
+   ldo1-supply = <&v3v3>;
+   ldo2-supply = <&v3v3>;
+   ldo3-supply = <&vdd_ddr>;
+   ldo5-supply = <&v3v3>;
+   ldo6-supply = <&v3v3>;
+   pwr_sw1-supply = <&bst_out>;
+   pwr_sw2-supply = <&bst_out>;
+
+   vddcore: buck1 {
+   regulator-name = "vddcore";
+   regulator-min-microvolt = <80>;
+   regulator-max-microvolt = <135>;
+   regulator-always-on;
+   regulator-initial-mode = <2>;
+   regulator-over-current-protection;
+
+   regulator-state-standby {
+   regulator-on-in-suspend;
+   regulator-suspend-microvolt = <120>;
+   regulator-mode = <8>;
+   };
+   regulator-state-mem {
+   regulator-off-in-suspend;
+   };
+   regulator-state-disk {
+   regulator-off-in-suspend;
+   };
+   };
+
+   vdd_ddr: buck2 {
+   regulator-name = "vdd_ddr";
+   regulator-min-microvolt = <135>;
+   regulator-max-microvolt = <135>;
+   regulator-always-on;
+   regulator-initial-mode = <2>;
+   regulator-over-current-protection;
+
+   regulator-state-standby {
+   regulator-suspend-microvolt = <135>;
+   regulator-on-in-suspend;
+   regulator-mode = <8>;
+   };
+   regulator-state-mem {
+   regulator-suspend-microvolt = <135>;
+   regulator-on-in-suspend;
+   regulator-mode = <8>;
+   };
+   regulator-state-disk {
+   regulator-off-in-suspend;
+   };
+   };
+
+   vdd: buck3 {
+   regulator-name = "vdd";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   st,mask_reset;
+   regulator-initial-mode = <8>;
+   regulator-over-current-protection;
+
+   regulator-state-standby {
+   regulator-suspend-microvolt = <330>;
+   regulator-o

[U-Boot] [RESEND][PATCH v1 1/3] power: pmic: stpmu1: Add regulator bindings

[Patrice Chotard]

Add regulator bindings to get access to regulator managed
by drivers/power/regulator/stpmu1.c regulator driver.

Signed-off-by: Christophe Kerello 
Signed-off-by: Patrick Delaunay 
Signed-off-by: Patrice Chotard 
---

 drivers/power/pmic/stpmu1.c | 34 ++
 1 file changed, 34 insertions(+)

diff --git a/drivers/power/pmic/stpmu1.c b/drivers/power/pmic/stpmu1.c
index 4615365ea809..4a230ec163ae 100644
--- a/drivers/power/pmic/stpmu1.c
+++ b/drivers/power/pmic/stpmu1.c
@@ -13,6 +13,17 @@
 
 #define STMPU1_NUM_OF_REGS 0x100
 
+#ifndef CONFIG_SPL_BUILD
+static const struct pmic_child_info stpmu1_children_info[] = {
+   { .prefix = "ldo", .driver = "stpmu1_ldo" },
+   { .prefix = "buck", .driver = "stpmu1_buck" },
+   { .prefix = "vref_ddr", .driver = "stpmu1_vref_ddr" },
+   { .prefix = "pwr_sw", .driver = "stpmu1_pwr_sw" },
+   { .prefix = "boost", .driver = "stpmu1_boost" },
+   { },
+};
+#endif /* CONFIG_SPL_BUILD */
+
 static int stpmu1_reg_count(struct udevice *dev)
 {
return STMPU1_NUM_OF_REGS;
@@ -43,6 +54,28 @@ static int stpmu1_read(struct udevice *dev, uint reg, 
uint8_t *buff, int len)
return ret;
 }
 
+static int stpmu1_bind(struct udevice *dev)
+{
+#ifndef CONFIG_SPL_BUILD
+   ofnode regulators_node;
+   int children;
+
+   regulators_node = dev_read_subnode(dev, "regulators");
+   if (!ofnode_valid(regulators_node)) {
+   dev_dbg(dev, "regulators subnode not found!");
+   return -ENXIO;
+   }
+   dev_dbg(dev, "found regulators subnode\n");
+
+   children = pmic_bind_children(dev, regulators_node,
+ stpmu1_children_info);
+   if (!children)
+   dev_dbg(dev, "no child found\n");
+#endif /* CONFIG_SPL_BUILD */
+
+   return 0;
+}
+
 static struct dm_pmic_ops stpmu1_ops = {
.reg_count = stpmu1_reg_count,
.read = stpmu1_read,
@@ -58,5 +91,6 @@ U_BOOT_DRIVER(pmic_stpmu1) = {
.name = "stpmu1_pmic",
.id = UCLASS_PMIC,
.of_match = stpmu1_ids,
+   .bind = stpmu1_bind,
.ops = &stpmu1_ops,
 };
-- 
1.9.1

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[U-Boot] [RESEND][PATCH v1 0/3] Add STM32MP157 regulator driver

[Patrice Chotard]

This series :
  _ adds stpmu1 regulator driver
  _ enables regulator relative flags in stm32mp15_basic_defconfig
  _ updates pmic driver to bind regulator child nodes
  _ adds regulator nodes entry in DT


Patrice Chotard (3):
  power: pmic: stpmu1: Add regulator bindings
  ARM: dts: stm32mp157c-ed1: Add regulator node
  configs: stm32mp15_basic: Set regulator relative flags

 arch/arm/dts/stm32mp157c-ed1.dts| 272 
 configs/stm32mp15_basic_defconfig   |   5 +
 drivers/power/pmic/stpmu1.c |  34 +
 include/dt-bindings/mfd/st,stpmu1.h |  60 
 4 files changed, 371 insertions(+)
 create mode 100644 include/dt-bindings/mfd/st,stpmu1.h

-- 
1.9.1

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Re: [U-Boot] [PATCH 6/8] cpu: Add cpu_print_info function

[Simon Glass]

Hi Mario,

On 26 April 2018 at 00:07, Mario Six  wrote:
> Hi Simon,
>
> On Tue, Apr 24, 2018 at 11:53 PM, Simon Glass  wrote:
>> Hi Mario,
>>
>> On 19 April 2018 at 01:50, Mario Six  wrote:
>>>
>>> Hi Simon,
>>>
>>> On Wed, Apr 18, 2018 at 5:45 PM, Simon Glass  wrote:
>>> > Hi Mario,
>>> >
>>> > On 18 April 2018 at 02:35, Mario Six  wrote:
>>> >> Hi Simon,
>>> >>
>>> >> On Thu, Apr 12, 2018 at 6:37 PM, Simon Glass  wrote:
>>> >>> Hi Mario,
>>> >>>
>>> >>> On 11 April 2018 at 00:39, Mario Six  wrote:
>>>  Hi Simon,
>>> 
>>>  On Fri, Mar 30, 2018 at 10:41 AM, Simon Glass  
>>>  wrote:
>>> > Hi,
>>> >
>>> > On 28 March 2018 at 20:38, Mario Six  wrote:
>>> >> Add a cpu_print_info function to the CPU uclass to emulate the 
>>> >> behavior
>>> >> of some current non-DM drivers (e.g. MPC83xx) to print CPU 
>>> >> information
>>> >> during startup.
>>> >>
>>> >> Signed-off-by: Mario Six 
>>> >> ---
>>> >>  drivers/cpu/cpu-uclass.c | 10 ++
>>> >>  include/cpu.h| 15 +++
>>> >>  2 files changed, 25 insertions(+)
>>> >>
>>> >
>>> > I really don't want drivers printing stuff. Can you use the existing
>>> > get_info() method?
>>> >
>>> 
>>>  I could, but I'm just emulating the behavior of the legacy code here, 
>>>  which
>>>  prints some information when the CPU is initialized. I think that's 
>>>  pretty
>>>  useful, and I can do that in our board file, but that would mean 
>>>  implementing
>>>  the same routine in every MPC83xx board to get the legacy behavior 
>>>  back.
>>> >>>
>>> >>> Yes, but I don't want the legacy code creeping into the eclass. Can
>>> >>> you convert the board to use the CPU eclass instead?
>>> >>>
>>> >>
>>> >> That's what I did, and I just discovered DISPLAY_CPUINFO, which does 
>>> >> exactly
>>> >> what is needed. I'll implement the print_cpuinfo function in the CPU 
>>> >> driver, so
>>> >> I can get rid of the print function in the uclass (and still retain the
>>> >> information printing at bootup).
>>> >
>>> > OK I see. Ideally we would have a function (perhaps in board_f) which
>>> > prints out the CPU info after obtaining it from the uclass. So could
>>> > you move your print_cpuinfo() function into board_f? Would it be
>>> > possible to use that if CONFIG_CPU is defined?
>>> >
>>> > At some point print_cpuinfo() could be removed from various board files.
>>> >
>>>
>>> The function prints the following (example for our device):
>>>
>>> --- >8 ---
>>>
>>> Reset Status: External/Internal Soft, External/Internal Hard
>>>
>>> CPU:   e300c3, MPC8308, Rev: 1.1 at 400 MHz, CSB: 133.333 MHz
>>>
>>> --- >8 ---
>>>
>>> So there are some values that are very specific to the platform, such as the
>>> CSB (Coherent System Bus) frequency, or the reset status. While it's 
>>> probably
>>> possible to put some of that into a generic info printing routine, lots of 
>>> it
>>> is so MPC83xx-specific that it doesn't make much sense for other CPUs.
>>
>> Well you get to provide a string from get_desc() so you can add
>> whatever you like!
>>
>
> OK, I thought I was supposed to decode the cpu_info and print that in the
> function. If i can use get_desc(), then it's fine. :-)
>
>>>
>>> Any idea how to tackle this? I don't really want to get rid of the Reset 
>>> Status
>>> printing especially, since it's pretty useful information for debugging 
>>> devices
>>> in the field.
>>
>> Re the reset status, shouldn't that come from the sysreset driver? I
>> wonder if we should add an API call for that? Or is it something
>> printed by the board?
>>
>
> No, that's indeed printed on every MPC83xx board (see prt_83xx_rsr in
> arch/powerpc/cpu/mpc83xx/cpu_init.c). A sysreset driver would probably be a
> good canonical candidate for printing such a message, true. But since there is
> no real system reset on MPC83xx to speak of, that would (for now at least) be
> the only thing a MPC83xx sysreset driver did. Also, we'd need another function
> in board_f.c, and I don't really know if reset cause printing is very
> wide-spread on other platforms to justify that.

Well I've certainly printed this info myself so I think it is useful,
particularly things like whether it was a watchdog reset or user
reset.

Regards,
Simon
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Re: [U-Boot] [PATCH] cmd: add ADC cli commands

[Simon Glass]

Hi Neil,

On 23 April 2018 at 08:18, Neil Armstrong  wrote:
> Add an 'adc' cli command to get adc devices informations and read single
> shots datas.
>
> Signed-off-by: Neil Armstrong 
> ---
>  cmd/Kconfig  |   7 
>  cmd/Makefile |   1 +
>  cmd/adc.c| 126 
> +++
>  3 files changed, 134 insertions(+)
>  create mode 100644 cmd/adc.c

Reviewed-by: Simon Glass 

Nits below

>
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index bc1d2f3..631daee 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -601,6 +601,13 @@ config CMD_ARMFLASH
> help
>   ARM Ltd reference designs flash partition access
>
> +config CMD_ADC
> +   bool "adc - Access ADC info and data"
> +   select ADC
> +   select DM_REGULATOR
> +   help
> + Shows ADC device info and get single shot data;

Please spell out ADC in the help. Also, what is single-shot data?

> +
>  config CMD_CLK
> bool "clk - Show clock frequencies"
> help
> diff --git a/cmd/Makefile b/cmd/Makefile
> index c4269ac..4c66353 100644
> --- a/cmd/Makefile
> +++ b/cmd/Makefile
> @@ -14,6 +14,7 @@ obj-y += version.o
>
>  # command
>  obj-$(CONFIG_CMD_AES) += aes.o
> +obj-$(CONFIG_CMD_ADC) += adc.o
>  obj-$(CONFIG_CMD_ARMFLASH) += armflash.o
>  obj-y += blk_common.o
>  obj-$(CONFIG_SOURCE) += source.o
> diff --git a/cmd/adc.c b/cmd/adc.c
> new file mode 100644
> index 000..f82305c
> --- /dev/null
> +++ b/cmd/adc.c
> @@ -0,0 +1,126 @@
> +/*
> + * Copyright (C) 2018 BayLibre, SAS
> + *  Author: Neil Armstrong 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +static int do_adc_list(cmd_tbl_t *cmdtp, int flag, int argc,
> +  char *const argv[])
> +{
> +   struct udevice *dev;
> +   int ret;
> +
> +   ret = uclass_first_device_err(UCLASS_ADC, &dev);

This will probe the device. Is that what you want?

> +   if (ret || !dev) {

You don't need to check dev, since ret will return -ENODEV if there is
no device. See the docs for uclass_first_device_err().

> +   printf("No available ADC device\n");

return?

> +   }
> +
> +   do {
> +   printf("- %s\n", dev->name);
> +
> +   ret = uclass_next_device(&dev);
> +   if (ret)
> +   return CMD_RET_FAILURE;
> +   } while (dev);
> +
> +   return CMD_RET_SUCCESS;
> +}
> +
> +static int do_adc_info(cmd_tbl_t *cmdtp, int flag, int argc,
> +  char *const argv[])
> +{
> +   struct udevice *dev;
> +   unsigned int data_mask;
> +   int ret, vss, vdd;
> +
> +   if (argc < 2)
> +   return CMD_RET_USAGE;
> +
> +   ret = uclass_get_device_by_name(UCLASS_ADC, argv[1], &dev);
> +   if (ret) {
> +   printf("Unknown ADC device %s\n", argv[1]);
> +   return CMD_RET_FAILURE;
> +   }
> +
> +   printf("ADC Device '%s' :\n", argv[1]);
> +
> +   ret = adc_data_mask(dev, &data_mask);
> +   if (ret)
> +   printf("data mask: Error %d\n", ret);
> +   else
> +   printf("data mask: %x\n", data_mask);

You could perhaps have a function to print the error or the value. I'm
not sure if it is worth it.

> +
> +   ret = adc_vdd_value(dev, &vdd);
> +   if (ret)
> +   printf("vdd: Error %d\n", ret);
> +   else
> +   printf("vdd: %duV\n", vdd);
> +
> +   ret = adc_vss_value(dev, &vss);
> +   if (ret)
> +   printf("vss: Error %d\n", ret);
> +   else
> +   printf("vss: %duV\n", vss);
> +
> +   return CMD_RET_SUCCESS;
> +}
> +

[..]

Regards,
Simon
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[U-Boot] [RESEND][PATCH v1 3/3] configs: stm32mp15_basic: Set regulator relative flags

[Patrice Chotard]

Enable DM_REGULATOR_STPMU1 flag to activate regulator
driver for STM32MP15 SoC and CMD_REGULATOR flag to be
able to set/get regulator state int U-boot command line.

Disable PMIC_CHILDREN as this flag is not needed in SPL
for STM32MP1.

Signed-off-by: Patrice Chotard 
---

 configs/stm32mp15_basic_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configs/stm32mp15_basic_defconfig 
b/configs/stm32mp15_basic_defconfig
index 4ab1d4c8b12c..b5a75563fc38 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -22,6 +22,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_ISO_PARTITION is not set
@@ -31,6 +32,10 @@ CONFIG_DM_MMC=y
 CONFIG_STM32_SDMMC2=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_STPMU1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STPMU1=y
 CONFIG_STM32_SERIAL=y
 # CONFIG_EFI_LOADER is not set
-- 
1.9.1

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Re: [U-Boot] [PATCH v2 2/4] dm: ofnode: add ofnode_device_is_compatible() helper

[Simon Glass]

Hi Masahiro,

On 18 April 2018 at 21:14, Masahiro Yamada
 wrote:
> device_is_compatible() takes udevice, but there is no such a helper
> that takes ofnode.
>
> Signed-off-by: Masahiro Yamada 
> ---
>
> Changes in v2: None
>
>  drivers/core/device.c |  8 +---
>  drivers/core/ofnode.c | 11 +++
>  include/dm/ofnode.h   | 11 +++
>  3 files changed, 23 insertions(+), 7 deletions(-)
>

Please can you add a simple test for this?

Regards,
Simon
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Re: [U-Boot] [PATCH] regmap: add regmap_update_bits() helper

[Simon Glass]

Hi Neil,

On 23 April 2018 at 08:16, Neil Armstrong  wrote:
> Add the regmap_update_bits() to simply the read/modify/write of registers
> in a single command. The function is taken from Linux regmap
> implementation.
>
> Signed-off-by: Neil Armstrong 
> ---
>  include/regmap.h | 23 +++
>  1 file changed, 23 insertions(+)
>
> diff --git a/include/regmap.h b/include/regmap.h
> index 493a5d8..3c463e9 100644
> --- a/include/regmap.h
> +++ b/include/regmap.h
> @@ -47,6 +47,29 @@ int regmap_read(struct regmap *map, uint offset, uint 
> *valp);
> regmap_read(map, (uint32_t *)(ptr)->member - (uint32_t *)(ptr), valp)
>
>  /**
> + * regmap_update_bits() - Perform a read/modify/write using a mask
> + *
> + * @map:   The map returned by regmap_init_mem*()
> + * @offset:Offset of the memory
> + * @mask:  Mask to apply to the read value
> + * @val:   Value to apply to the value to write
> + */
> +static inline int regmap_update_bits(struct regmap *map, uint offset,
> +uint mask, uint val)

Why is this inline? I think it would save code size to make it a
normal function.

Also can you add a call to this function somewhere for sandbox, as a test?

> +{
> +   uint reg;
> +   int ret;
> +
> +   ret = regmap_read(map, offset, ®);
> +   if (ret)
> +   return ret;
> +
> +   reg &= ~mask;
> +
> +   return regmap_write(map, offset, reg | val);
> +}
> +
> +/**
>   * regmap_init_mem() - Set up a new register map that uses memory access
>   *
>   * Use regmap_uninit() to free it.
> --
> 2.7.4
>

Regards,
Simon
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Re: [U-Boot] [PATCH v2 11/19] tpm: add TPM2_Clear command support

[Simon Glass]

Hi Miquel,

On 24 April 2018 at 07:17, Miquel Raynal  wrote:
> Hi Simon,
>
> On Fri, 30 Mar 2018 06:42:32 +0800, Simon Glass 
> wrote:
>
>> Hi Miquel,
>>
>> On 29 March 2018 at 15:43, Miquel Raynal  wrote:
>> > Add support for the TPM2_Clear command.
>> >
>> > Change the command file and the help accordingly.
>> >
>> > Signed-off-by: Miquel Raynal 
>> > ---
>> >  cmd/tpm.c  | 29 ++---
>> >  cmd/tpm_test.c |  6 +++---
>> >  include/tpm.h  | 21 +
>> >  lib/tpm.c  | 42 ++
>> >  4 files changed, 84 insertions(+), 14 deletions(-)
>> >
>> > diff --git a/cmd/tpm.c b/cmd/tpm.c
>> > index fc9ef9d4a3..32921e1a70 100644
>> > --- a/cmd/tpm.c
>> > +++ b/cmd/tpm.c
>> > @@ -454,6 +454,29 @@ static int do_tpm_init(cmd_tbl_t *cmdtp, int flag,
>> > return report_return_code(tpm_init());
>> >  }
>> >
>> > +static int do_tpm_force_clear(cmd_tbl_t *cmdtp, int flag,
>> > + int argc, char * const argv[])
>> > +{
>> > +   u32 handle = 0;
>> > +   const char *pw = (argc < 3) ? NULL : argv[2];
>> > +   const ssize_t pw_sz = pw ? strlen(pw) : 0;
>> > +
>> > +   if (argc < 2 || argc > 3)
>> > +   return CMD_RET_USAGE;
>> > +
>> > +   if (pw_sz > TPM2_DIGEST_LENGTH)
>> > +   return -EINVAL;
>> > +
>> > +   if (!strcasecmp("TPM2_RH_LOCKOUT", argv[1]))
>> > +   handle = TPM2_RH_LOCKOUT;
>> > +   else if (!strcasecmp("TPM2_RH_PLATFORM", argv[1]))
>> > +   handle = TPM2_RH_PLATFORM;
>> > +   else
>> > +   return CMD_RET_USAGE;
>> > +
>> > +   return report_return_code(tpm_force_clear(handle, pw, pw_sz));
>> > +}
>> > +
>> >  #define TPM_COMMAND_NO_ARG(cmd)\
>> >  static int do_##cmd(cmd_tbl_t *cmdtp, int flag,\
>> > int argc, char * const argv[])  \
>> > @@ -465,7 +488,6 @@ static int do_##cmd(cmd_tbl_t *cmdtp, int flag,
>> >  \
>> >
>> >  TPM_COMMAND_NO_ARG(tpm_self_test_full)
>> >  TPM_COMMAND_NO_ARG(tpm_continue_self_test)
>> > -TPM_COMMAND_NO_ARG(tpm_force_clear)
>> >  TPM_COMMAND_NO_ARG(tpm_physical_enable)
>> >  TPM_COMMAND_NO_ARG(tpm_physical_disable)
>> >
>> > @@ -951,8 +973,9 @@ U_BOOT_CMD(tpm, CONFIG_SYS_MAXARGS, 1, do_tpm,
>> >  "  physical_set_deactivated 0|1\n"
>> >  "- Set deactivated flag.\n"
>> >  "Admin Ownership Commands:\n"
>> > -"  force_clear\n"
>> > -"- Issue TPM_ForceClear command.\n"
>> > +"  force_clear []\n"
>> > +"- Issue TPM_[Force]Clear command, with  one of (TPMv2 only):\n"
>> > +"  * TPM2_RH_LOCKOUT, TPM2_RH_PLATFORM.\n"
>> >  "  tsc_physical_presence flags\n"
>> >  "- Set TPM device's Physical Presence flags to .\n"
>> >  "The Capability Commands:\n"
>> > diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c
>> > index 37ad2ff33d..da40dbc423 100644
>> > --- a/cmd/tpm_test.c
>> > +++ b/cmd/tpm_test.c
>> > @@ -176,7 +176,7 @@ static int test_fast_enable(void)
>> > TPM_CHECK(tpm_get_flags(&disable, &deactivated, NULL));
>> > printf("\tdisable is %d, deactivated is %d\n", disable, 
>> > deactivated);
>> > for (i = 0; i < 2; i++) {
>> > -   TPM_CHECK(tpm_force_clear());
>> > +   TPM_CHECK(tpm_force_clear(0, NULL, 0));
>> > TPM_CHECK(tpm_get_flags(&disable, &deactivated, NULL));
>> > printf("\tdisable is %d, deactivated is %d\n", disable,
>> >deactivated);
>> > @@ -458,7 +458,7 @@ static int test_write_limit(void)
>> > TPM_CHECK(TlclStartupIfNeeded());
>> > TPM_CHECK(tpm_self_test_full());
>> > TPM_CHECK(tpm_tsc_physical_presence(PRESENCE));
>> > -   TPM_CHECK(tpm_force_clear());
>> > +   TPM_CHECK(tpm_force_clear(0, NULL, 0));
>> > TPM_CHECK(tpm_physical_enable());
>> > TPM_CHECK(tpm_physical_set_deactivated(0));
>> >
>> > @@ -477,7 +477,7 @@ static int test_write_limit(void)
>> > }
>> >
>> > /* Reset write count */
>> > -   TPM_CHECK(tpm_force_clear());
>> > +   TPM_CHECK(tpm_force_clear(0, NULL, 0));
>> > TPM_CHECK(tpm_physical_enable());
>> > TPM_CHECK(tpm_physical_set_deactivated(0));
>> >
>> > diff --git a/include/tpm.h b/include/tpm.h
>> > index 38d7cb899d..2f1712 100644
>> > --- a/include/tpm.h
>> > +++ b/include/tpm.h
>> > @@ -43,13 +43,23 @@ enum tpm_startup_type {
>> >  };
>> >
>> >  enum tpm2_startup_types {
>> > -   TPM2_SU_CLEAR   = 0x,
>> > -   TPM2_SU_STATE   = 0x0001,
>> > +   TPM2_SU_CLEAR   = 0x,
>> > +   TPM2_SU_STATE   = 0x0001,
>> > +};
>> > +
>> > +enum tpm2_handles {
>>
>> Please add comment to enum
>
> Fine, I will document all of them. Just for you to know, these are
> values extracted from the (publicly available) specification, I did
> not change any of them.
>
>>
>> > +   TPM2_RH_OWNER   = 0x4001,
>> > +   TPM2_RS_PW

Re: [U-Boot] [PATCH v2 3/4] regmap: change regmap_init_mem() to take ofnode instead udevice

[Simon Glass]

On 18 April 2018 at 21:14, Masahiro Yamada
 wrote:
> Currently, regmap_init_mem() takes a udevice. This requires the node
> has already been associated with a device. It prevents syscon/regmap
> from behaving like those in Linux.
>
> Change the first argumenet to take a device node.
>
> Signed-off-by: Masahiro Yamada 
> Acked-by: Neil Armstrong 
> ---
>
> Changes in v2: None
>
>  arch/arm/mach-aspeed/ast2500/sdram_ast2500.c |  2 +-
>  drivers/core/regmap.c| 11 +--
>  drivers/core/syscon-uclass.c |  2 +-
>  drivers/phy/meson-gxl-usb2.c |  2 +-
>  drivers/phy/meson-gxl-usb3.c |  2 +-
>  drivers/ram/rockchip/dmc-rk3368.c|  2 +-
>  drivers/ram/rockchip/sdram_rk3188.c  |  2 +-
>  drivers/ram/rockchip/sdram_rk322x.c  |  2 +-
>  drivers/ram/rockchip/sdram_rk3288.c  |  2 +-
>  drivers/ram/rockchip/sdram_rk3399.c  |  2 +-
>  drivers/ram/stm32mp1/stm32mp1_ram.c  |  2 +-
>  drivers/reset/reset-meson.c  |  2 +-
>  include/regmap.h |  4 ++--
>  13 files changed, 18 insertions(+), 19 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v2 10/19] tpm: add TPM2_SelfTest command support

[Simon Glass]

Hi Miquel,

On 24 April 2018 at 06:53, Miquel Raynal  wrote:
> Hi Simon,
>
> I am back on that topic, let me answer some of your questions before
> addressing them in a next version.
>
> On Fri, 30 Mar 2018 06:42:25 +0800, Simon Glass
>  wrote:
>
>> Hi Miquel,
>>
>> On 29 March 2018 at 15:43, Miquel Raynal  wrote:
>> > Add support for the TPM2_Selftest command.
>> >
>> > Change the command file and the help accordingly.
>> >
>> > Signed-off-by: Miquel Raynal 
>> > ---
>> >  include/tpm.h |  9 +++--
>> >  lib/tpm.c | 36 
>> >  2 files changed, 35 insertions(+), 10 deletions(-)
>> >
>> > diff --git a/include/tpm.h b/include/tpm.h
>> > index ba71bac885..38d7cb899d 100644
>> > --- a/include/tpm.h
>> > +++ b/include/tpm.h
>> > @@ -31,6 +31,11 @@ enum tpm2_structures {
>> > TPM2_ST_SESSIONS= 0x8002,
>> >  };
>> >
>> > +enum tpm2_yes_no {
>> > +   TPMI_YES= 1,
>> > +   TPMI_NO = 0,
>> > +};
>> > +
>> >  enum tpm_startup_type {
>> > TPM_ST_CLEAR= 0x0001,
>> > TPM_ST_STATE= 0x0002,
>> > @@ -476,14 +481,14 @@ int tpm_startup(enum tpm_startup_type mode);
>> >   *
>> >   * @return return code of the operation
>> >   */
>> > -uint32_t tpm_self_test_full(void);
>> > +int tpm_self_test_full(void);
>> >
>> >  /**
>> >   * Issue a TPM_ContinueSelfTest command.
>> >   *
>> >   * @return return code of the operation
>> >   */
>> > -uint32_t tpm_continue_self_test(void);
>> > +int tpm_continue_self_test(void);
>> >
>> >  /**
>> >   * Issue a TPM_NV_DefineSpace command.  The implementation is limited
>> > diff --git a/lib/tpm.c b/lib/tpm.c
>> > index 0c57ef8dc7..3cc2888267 100644
>> > --- a/lib/tpm.c
>> > +++ b/lib/tpm.c
>> > @@ -341,20 +341,40 @@ int tpm_startup(enum tpm_startup_type mode)
>> > return 0;
>> >  }
>> >
>> > -uint32_t tpm_self_test_full(void)
>> > +int tpm_self_test_full(void)
>> >  {
>> > -   const uint8_t command[10] = {
>> > -   0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x50,
>> > +   const u8 command_v1[10] = {
>> > +   U16_TO_ARRAY(0xc1),
>>
>> Here I can see some benefit to your macros because the data is better
>> structured. But why not use the pack_byte_string() function?
>
> TPM buffers (1.0 and 2.0) are, most of the time, filled with data of
> known length (1, 2 or 4 bytes). You can see that most of the time,
> TPMv1 simple commands were just filling a buffer of bytes. I don't like
> very much the fact that the user should split the data in byte array so
> I introduced these macros that do it for me in a cleaner way. When you
> get an hexadecimal value (like it was the case before) it is easy to
> split a "0xabcd" in "0xab, 0xcd", but I prefer to use variables or
> simply defines sometimes and writing "TPM2_ST_NO_SESSIONS" as
> "TPM2_ST_NO_SESSIONS >> 8, TPM2_ST_NO_SESSIONS & 0xFF" is not readable
> at all.
>
> Now why did I not use the existing pack_byte_string() function. Well,
> at first I did and realized it was a pain to have a decent
> incrementation of the offsets, mostly when commands tend to be longer
> and longer. Having such lists of offset/variable/length while you could
> define them statically on the stack -which also saves some computing
> time- is quickly annoying and hard to review. From my point of view this
> function is a real asset when it comes to 'unknown'/'big' variable
> length (like a password, an hmac, an user input, etc) but should be
> avoided when not necessary: typically to fill a buffer with defined
> values.
>
> I am of course very open on the topic, this is my feeling but I don't
> have that much experience and would carefully listen to yours.

I don't think this is an unreasonable point of view. Either works.

But if you are changing the approach to use static data, should you
convert the existing code to the new scheme?

Regards,
Simon
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[U-Boot] [RESEND][PATCH v1] phy: add support for STM32 usb phy controller

[Patrice Chotard]

From: Christophe Kerello 

This patch adds phy tranceiver driver for STM32 USB PHY
Controller (usbphyc) that provides dual port High-Speed
phy for OTG (single port) and EHCI/OHCI host controller
(two ports).
One port of the phy is shared between the two USB controllers
through a UTMI+ switch.

Signed-off-by: Christophe Kerello 
Signed-off-by: Patrice Chotard 
---

 drivers/phy/Kconfig |  13 ++
 drivers/phy/Makefile|   1 +
 drivers/phy/phy-stm32-usbphyc.c | 403 
 3 files changed, 417 insertions(+)
 create mode 100644 drivers/phy/phy-stm32-usbphyc.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 4e9d09910c32..1de3f31bcdd1 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -110,4 +110,17 @@ config STI_USB_PHY
  used by USB2 and USB3 Host controllers available on
  STiH407 SoC families.
 
+config PHY_STM32_USBPHYC
+   tristate "STMicroelectronics STM32 SoC USB HS PHY driver"
+   depends on PHY && ARCH_STM32MP
+   help
+ Enable this to support the High-Speed USB transceiver that is part of
+ STMicroelectronics STM32 SoCs.
+
+ This driver controls the entire USB PHY block: the USB PHY controller
+ (USBPHYC) and the two 8-bit wide UTMI+ interface. First interface is
+ used by an HS USB Host controller, and the second one is shared
+ between an HS USB OTG controller and an HS USB Host controller,
+ selected by an USB switch.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 68087ae3b134..e93c3257230d 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o
 obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
 obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
 obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
+obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
new file mode 100644
index ..744a26c4cd3d
--- /dev/null
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier:GPL-2.0+BSD-3-Clause
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* USBPHYC registers */
+#define STM32_USBPHYC_PLL  0x0
+#define STM32_USBPHYC_MISC 0x8
+
+/* STM32_USBPHYC_PLL bit fields */
+#define PLLNDIVGENMASK(6, 0)
+#define PLLNDIV_SHIFT  0
+#define PLLFRACIN  GENMASK(25, 10)
+#define PLLFRACIN_SHIFT10
+#define PLLEN  BIT(26)
+#define PLLSTRBBIT(27)
+#define PLLSTRBYP  BIT(28)
+#define PLLFRACCTL BIT(29)
+#define PLLDITHEN0 BIT(30)
+#define PLLDITHEN1 BIT(31)
+
+/* STM32_USBPHYC_MISC bit fields */
+#define SWITHOST   BIT(0)
+
+#define MAX_PHYS   2
+
+#define PLL_LOCK_TIME_US   100
+#define PLL_PWR_DOWN_TIME_US   5
+#define PLL_FVCO   2880 /* in MHz */
+#define PLL_INFF_MIN_RATE  1920 /* in Hz */
+#define PLL_INFF_MAX_RATE  3840 /* in Hz */
+
+struct pll_params {
+   u8 ndiv;
+   u16 frac;
+};
+
+struct stm32_usbphyc {
+   fdt_addr_t base;
+   struct clk clk;
+   struct stm32_usbphyc_phy {
+   struct udevice *vdd;
+   struct udevice *vdda1v1;
+   struct udevice *vdda1v8;
+   int index;
+   bool init;
+   bool powered;
+   } phys[MAX_PHYS];
+};
+
+void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params)
+{
+   unsigned long long fvco, ndiv, frac;
+
+   /*
+*| FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
+*| FVCO = 2880MHz
+*| NDIV = integer part of input bits to set the LDF
+*| FRACT = fractional part of input bits to set the LDF
+*  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
+*  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
+* <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
+*/
+   fvco = (unsigned long long)PLL_FVCO * 100; /* In Hz */
+
+   ndiv = fvco;
+   do_div(ndiv, (clk_rate * 2));
+   pll_params->ndiv = (u8)ndiv;
+
+   frac = fvco * (1 << 16);
+   do_div(frac, (clk_rate * 2));
+   frac = frac - (ndiv * (1 << 16));
+   pll_params->frac = (u16)frac;
+}
+
+static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
+{
+   struct pll_params pll_params;
+   u32 clk_rate = clk_get_rate(&usbphyc->clk);
+   u32 usbphyc_pll;
+
+   if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
+   pr_debug("%s: input clk freq (%dHz) out of range\n",
+ 

[U-Boot] [PATCH v3 0/3] fix apalis_t30 optional pcie operation

[Marcel Ziswiler]

This series addresses a PCIe reliability issue as observed on Apalis T30
related to a PCIe reset timing violation.

This series is available at 
http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next

Changes in v3:
- Updated copyright period to 2014-2018.
- Added a blank line after declarations as warned by patman.
- Added Stephen's acked-by.
- Rebased and resend as series so far never got applied!

Changes in v2:
- Leave resp. enable all port 0 pins input drivers as a customer may
  optionally want to use some of those MXM3 pins as inputs as well.
- Stick to struct tegra_pcie_port as suggested by Stephen.
- Introduce proper CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT Kconfig option
  as suggested by Stephen.
- Improved the ifdef vs. if curly braces sequencing as suggested by
  Stephen.
- Keep PCIe port reset status in order to safeguard for future changes
  to the port reset order or even allow for re-initialisation should
  that ever be implemented in the higher levels of the driver model.

Marcel Ziswiler (3):
  apalis_t30: describe pcie ports
  apalis_t30: fix pcie port 0 and 1 pin muxing
  apalis_t30: fix optional pcie port reset for reliable pcie operation

 arch/arm/dts/tegra30-apalis.dts|  3 ++
 board/toradex/apalis_t30/Kconfig   |  9 
 board/toradex/apalis_t30/apalis_t30.c  | 57 +-
 .../toradex/apalis_t30/pinmux-config-apalis_t30.h  | 16 +++---
 4 files changed, 77 insertions(+), 8 deletions(-)

-- 
2.14.3

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[U-Boot] [PATCH v3 1/3] apalis_t30: describe pcie ports

[Marcel Ziswiler]

From: Marcel Ziswiler 

Add some more comments describing the various PCIe ports available.

Signed-off-by: Marcel Ziswiler 

---

Changes in v3: None
Changes in v2: None

 arch/arm/dts/tegra30-apalis.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 0b84dae215..0852d8dc53 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -43,16 +43,19 @@
vddio-pex-ctl-supply = <&sys_3v3_reg>;
hvdd-pex-supply = <&sys_3v3_reg>;
 
+   /* Apalis Type Specific 4 Lane PCIe */
pci@1,0 {
/* TS_DIFF1/2/3/4 left disabled */
nvidia,num-lanes = <4>;
};
 
+   /* Apalis PCIe */
pci@2,0 {
/* PCIE1_RX/TX left disabled */
nvidia,num-lanes = <1>;
};
 
+   /* I210 Gigabit Ethernet Controller (On-module) */
pci@3,0 {
status = "okay";
nvidia,num-lanes = <1>;
-- 
2.14.3

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[U-Boot] [PATCH v3 3/3] apalis_t30: fix optional pcie port reset for reliable pcie operation

[Marcel Ziswiler]

From: Marcel Ziswiler 

Allow optionally bringing up the Apalis type specific 4 lane PCIe port
as well as the PCIe switch as found on the Apalis Evaluation board. In
order to avoid violating the PCIe reset timing do this by overriding the
tegra_pcie_board_port_reset() function. Note however that both the
Apalis type specific 4 lane PCIe port as well as the regular Apalis PCIe
port are also left disabled in the device tree by default.

Signed-off-by: Marcel Ziswiler 
Acked-by: Stephen Warren 

---

Changes in v3:
- Updated copyright period to 2014-2018.
- Added a blank line after declarations as warned by patman.
- Added Stephen's acked-by.
- Rebased and resend as series so far never got applied!

Changes in v2:
- Stick to struct tegra_pcie_port as suggested by Stephen.
- Introduce proper CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT Kconfig option
  as suggested by Stephen.
- Improved the ifdef vs. if curly braces sequencing as suggested by
  Stephen.
- Keep PCIe port reset status in order to safeguard for future changes
  to the port reset order or even allow for re-initialisation should
  that ever be implemented in the higher levels of the driver model.

 board/toradex/apalis_t30/Kconfig  |  9 ++
 board/toradex/apalis_t30/apalis_t30.c | 57 ++-
 2 files changed, 65 insertions(+), 1 deletion(-)

diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig
index 16224daa12..9cd497091d 100644
--- a/board/toradex/apalis_t30/Kconfig
+++ b/board/toradex/apalis_t30/Kconfig
@@ -25,6 +25,15 @@ config TDX_CFG_BLOCK_PART
 config TDX_CFG_BLOCK_OFFSET
default "-512"
 
+config APALIS_T30_PCIE_EVALBOARD_INIT
+   bool "Apalis Evaluation Board PCIe Initialisation"
+   help
+ Bring up the Apalis type specific 4 lane PCIe port as well as the
+ Apalis PCIe port with the PCIe switch as found on the Apalis
+ Evaluation board. Note that by default both those ports are also left
+ disabled in the device tree which needs changing as well for this to
+ actually work.
+
 source "board/toradex/common/Kconfig"
 
 endif
diff --git a/board/toradex/apalis_t30/apalis_t30.c 
b/board/toradex/apalis_t30/apalis_t30.c
index 827eefd463..530ed145b5 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2014-2016
+ *  (C) Copyright 2014-2018
  *  Marcel Ziswiler 
  *
  * SPDX-License-Identifier:GPL-2.0+
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "../common/tdx-common.h"
 
 #include "pinmux-config-apalis_t30.h"
@@ -23,6 +24,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PMU_I2C_ADDRESS0x2D
 #define MAX_I2C_RETRY  3
 
+#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
+#define PEX_PERST_NTEGRA_GPIO(S, 7) /* Apalis GPIO7 */
+#define RESET_MOCI_CTRLTEGRA_GPIO(I, 4)
+
+static int pci_reset_status;
+#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
+
 int arch_misc_init(void)
 {
if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
@@ -107,6 +115,53 @@ int tegra_pcie_board_init(void)
return err;
}
 
+#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
+   gpio_request(PEX_PERST_N, "PEX_PERST_N");
+   gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
+#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
+
return 0;
 }
+
+void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
+{
+   int index = tegra_pcie_port_index_of_port(port);
+
+   if (index == 2) { /* I210 Gigabit Ethernet Controller (On-module) */
+   tegra_pcie_port_reset(port);
+   }
+#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
+   /*
+* Apalis PCIe aka port 1 and Apalis Type Specific 4 Lane PCIe aka port
+* 0 share the same RESET_MOCI therefore only assert it once for both
+* ports to avoid loosing the previously brought up port again.
+*/
+   else if ((index == 1) || (index == 0)) {
+   /* only do it once per init cycle */
+   if (pci_reset_status % 2 == 0) {
+   /*
+* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on
+* Apalis Evaluation Board
+*/
+   gpio_direction_output(PEX_PERST_N, 0);
+   gpio_direction_output(RESET_MOCI_CTRL, 0);
+
+   /*
+* Must be asserted for 100 ms after power and clocks
+* are stable
+*/
+   mdelay(100);
+
+   gpio_set_value(PEX_PERST_N, 1);
+   /*
+* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not
+* Guaranteed Until 900 us After PEX_PERST# De-assertion
+*/
+   mdelay(1);
+   gpio_set_value(RESE

[U-Boot] [PATCH v3 2/3] apalis_t30: fix pcie port 0 and 1 pin muxing

[Marcel Ziswiler]

From: Marcel Ziswiler 

Fix optional Apalis type specific 4 lane PCIe port 0 and Apalis PCIe
port 1 pin muxing.

Signed-off-by: Marcel Ziswiler 

---

Changes in v3: None
Changes in v2:
- Leave resp. enable all port 0 pins input drivers as a customer may
  optionally want to use some of those MXM3 pins as inputs as well.

 board/toradex/apalis_t30/pinmux-config-apalis_t30.h | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h 
b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
index e0b00ea841..a1e3bb64b6 100644
--- a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
+++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
@@ -285,17 +285,19 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = 
{
DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
 
-   DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
-   DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
-   DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
-   DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+   DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, INPUT),
+   DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, RSVD2, NORMAL, NORMAL, INPUT),
+   DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, INPUT),
+
+   DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, RSVD2, DOWN, TRISTATE, OUTPUT), /* 
NC */
+   DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC 
*/
+   DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT), /* 
NC */
 
-   DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, DOWN, TRISTATE, OUTPUT), /* 
NC */
-   DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, DOWN, TRISTATE, OUTPUT), /* NC 
*/
-   DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, DOWN, TRISTATE, OUTPUT), /* 
NC */
DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+   DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+
DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, NORMAL, INPUT),
 
-- 
2.14.3

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Re: [U-Boot] [PATCH] usb: gadget: composite: fix NULL pointer when a non standard request is received

[Lukasz Majewski]

Hi Patrice,

> Hi
> 
> It's a gentle reminder as this patch is present on mailing list since
> 5 weeks without any feedback.

Deepest apologizes for the delay.

I will test this patch - as some Samsung SoCs may use this feature and
let you know. 

> 
> Thanks
> 
> On 03/15/2018 09:34 AM, patrice.chot...@st.com wrote:
> > From: Christophe Kerello 
> > 
> > In case usb configuration is unknown (cdev->config == NULL), non
> > standard request should not be processed.
> > Remove also the cdev->config check below which will never happen.
> > 
> > This issue was seen using ums feature.
> > 
> > Signed-off-by: Christophe Kerello 
> > Signed-off-by: Patrice Chotard 
> > ---
> >   drivers/usb/gadget/composite.c | 5 -
> >   1 file changed, 4 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/usb/gadget/composite.c
> > b/drivers/usb/gadget/composite.c index d0ee7847b98d..a87639def974
> > 100644 --- a/drivers/usb/gadget/composite.c
> > +++ b/drivers/usb/gadget/composite.c
> > @@ -838,6 +838,9 @@ unknown:
> > ctrl->bRequestType, ctrl->bRequest,
> > w_value, w_index, w_length);
> >   
> > +   if (!cdev->config)
> > +   goto done;
> > +
> > /*
> >  * functions always handle their interfaces and
> > endpoints...
> >  * punt other recipients (other, WUSB, ...) to
> > the current @@ -882,7 +885,7 @@ unknown:
> > value = f->setup(f, ctrl);
> > else {
> > c = cdev->config;
> > -   if (c && c->setup)
> > +   if (c->setup)
> > value = c->setup(c, ctrl);
> > }
> >   
> >  




Best regards,

Lukasz Majewski

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de


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Re: [U-Boot] [U-Boot, BUG] snow: mmc: SD card access broken: unable to select a mode

[Guillaume Gardet]

Le 26/04/2018 à 12:31, Jaehoon Chung a écrit :

Hi,

On 04/09/2018 09:02 PM, Guillaume Gardet wrote:

Hi Jaehoon,

There are problems with SD card access on Samsung Chromebook (snow) with latest 
master (and also 2018.05-rc1 and 2018.03).

eMMC is ok, but SD card access leads to 'unable to select a mode' problem. If I 
disable HS mode, I can access the SD card without problem:



Once we try to select HS mode, all access to SD card result in failure, even 
when trying to setup a lower frequency mode, including SD legacy at 25 MHz.

Any idea what is going? Maybe you have fixes pending?

Sorry for late. Hmm. I will check your issue. Just disable MMC_MODE_HS, then 
it's working fine?
or HS_52MHz?


I tried to disable HS_52MHz only and it did not fix the problem. Then I tried 
to disable both HS and HS_52MHz and it fixed the problem.


Guillaume



Best Regards,
Jaehoon Chung



Guillaume

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 23f642980bf..28f4fa0f213 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -508,7 +508,8 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct 
dwmci_host *host,
       cfg->host_caps |= MMC_MODE_4BIT;
       cfg->host_caps &= ~MMC_MODE_8BIT;
   }
-    cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+    /* Temp workaround for Chromebook snow to avoid the 'unable to select a 
mode' error */
+//     cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;

   cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
   }





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Re: [U-Boot] [PATCH] usb: gadget: composite: fix NULL pointer when a non standard request is received

[Marek Vasut]

On 04/26/2018 03:13 PM, Patrice CHOTARD wrote:
> Hi
> 
> It's a gentle reminder as this patch is present on mailing list since 5 
> weeks without any feedback.

This should've been like a third non-gentle ping, seriously, two weeks
without feedback is already sucky. Time to buzz Lukasz, although he is
probably busy with personal stuff these days.

Applied

> Thanks
> 
> On 03/15/2018 09:34 AM, patrice.chot...@st.com wrote:
>> From: Christophe Kerello 
>>
>> In case usb configuration is unknown (cdev->config == NULL), non standard
>> request should not be processed.
>> Remove also the cdev->config check below which will never happen.
>>
>> This issue was seen using ums feature.
>>
>> Signed-off-by: Christophe Kerello 
>> Signed-off-by: Patrice Chotard 
>> ---
>>   drivers/usb/gadget/composite.c | 5 -
>>   1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
>> index d0ee7847b98d..a87639def974 100644
>> --- a/drivers/usb/gadget/composite.c
>> +++ b/drivers/usb/gadget/composite.c
>> @@ -838,6 +838,9 @@ unknown:
>>  ctrl->bRequestType, ctrl->bRequest,
>>  w_value, w_index, w_length);
>>   
>> +if (!cdev->config)
>> +goto done;
>> +
>>  /*
>>   * functions always handle their interfaces and endpoints...
>>   * punt other recipients (other, WUSB, ...) to the current
>> @@ -882,7 +885,7 @@ unknown:
>>  value = f->setup(f, ctrl);
>>  else {
>>  c = cdev->config;
>> -if (c && c->setup)
>> +if (c->setup)
>>  value = c->setup(c, ctrl);
>>  }
>>   


-- 
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Marek Vasut
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Re: [U-Boot] [PATCH] usb: gadget: composite: fix NULL pointer when a non standard request is received

[Patrice CHOTARD]

Hi

It's a gentle reminder as this patch is present on mailing list since 5 
weeks without any feedback.

Thanks

On 03/15/2018 09:34 AM, patrice.chot...@st.com wrote:
> From: Christophe Kerello 
> 
> In case usb configuration is unknown (cdev->config == NULL), non standard
> request should not be processed.
> Remove also the cdev->config check below which will never happen.
> 
> This issue was seen using ums feature.
> 
> Signed-off-by: Christophe Kerello 
> Signed-off-by: Patrice Chotard 
> ---
>   drivers/usb/gadget/composite.c | 5 -
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
> index d0ee7847b98d..a87639def974 100644
> --- a/drivers/usb/gadget/composite.c
> +++ b/drivers/usb/gadget/composite.c
> @@ -838,6 +838,9 @@ unknown:
>   ctrl->bRequestType, ctrl->bRequest,
>   w_value, w_index, w_length);
>   
> + if (!cdev->config)
> + goto done;
> +
>   /*
>* functions always handle their interfaces and endpoints...
>* punt other recipients (other, WUSB, ...) to the current
> @@ -882,7 +885,7 @@ unknown:
>   value = f->setup(f, ctrl);
>   else {
>   c = cdev->config;
> - if (c && c->setup)
> + if (c->setup)
>   value = c->setup(c, ctrl);
>   }
>   
> 
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[U-Boot] [PATCH] arm: imx53: Add support for imx53 boards from K+P

[Lukasz Majewski]

This commit adds support for DDC and HSC boards from
K+P in u-boot.

Console output:

U-Boot 2018.05-rc2-00090-g752b7ed6f9 (Apr 26 2018 - 14:24:24 +0200)

CPU:   Freescale i.MX53 rev2.1 at 800 MHz
Reset cause: WDOG
Model: K+P iMX53
DRAM:  512 MiB
MMC:   FSL_SDHC: 0
Loading Environment from MMC... OK
In:serial
Out:   serial
Err:   serial
Module EEPROM:
  ID: TQMa53-CB.0401
  SN: 63152762
  MAC: 00:0b:64:03:14:2a
BBoard:40x0 Rev:10
Net:   eth0: ethernet@63fec000
Hit any key to stop autoboot:  0

Signed-off-by: Lukasz Majewski 
---

 arch/arm/dts/imx53-kp.dts  | 135 ++
 arch/arm/mach-imx/mx5/Kconfig  |  12 +++
 board/k+p/kp_imx53/Kconfig |  15 +++
 board/k+p/kp_imx53/MAINTAINERS |   6 ++
 board/k+p/kp_imx53/Makefile|   8 ++
 board/k+p/kp_imx53/kp_id_rev.c | 121 +++
 board/k+p/kp_imx53/kp_id_rev.h |  28 ++
 board/k+p/kp_imx53/kp_imx53.c  | 212 +
 configs/kp_imx53_defconfig |  40 
 include/configs/kp_imx53.h | 113 ++
 10 files changed, 690 insertions(+)
 create mode 100644 arch/arm/dts/imx53-kp.dts
 create mode 100644 board/k+p/kp_imx53/Kconfig
 create mode 100644 board/k+p/kp_imx53/MAINTAINERS
 create mode 100644 board/k+p/kp_imx53/Makefile
 create mode 100644 board/k+p/kp_imx53/kp_id_rev.c
 create mode 100644 board/k+p/kp_imx53/kp_id_rev.h
 create mode 100644 board/k+p/kp_imx53/kp_imx53.c
 create mode 100644 configs/kp_imx53_defconfig
 create mode 100644 include/configs/kp_imx53.h

diff --git a/arch/arm/dts/imx53-kp.dts b/arch/arm/dts/imx53-kp.dts
new file mode 100644
index 00..fd64a9f2f6
--- /dev/null
+++ b/arch/arm/dts/imx53-kp.dts
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lu...@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include 
+#include "imx53.dtsi"
+#include "imx53-pinfunc.h"
+
+/ {
+   model = "K+P iMX53";
+   compatible = "kp,imx53-kp", "fsl,imx53";
+
+   chosen {
+   stdout-path = &uart2;
+   };
+};
+
+&fec {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_eth>;
+   phy-mode = "rmii";
+   phy-reset-gpios = <&gpio7 6 0>;
+   status = "okay";
+};
+
+&i2c2 {
+   pinctrl-names = "default", "gpio";
+   pinctrl-0 = <&pinctrl_i2c2>;
+   pinctrl-1 = <&pinctrl_i2c2_gpio>;
+   clock_frequency = <10>;
+
+   scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+   sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+
+   status = "okay";
+
+   pmic: mc34708@8 {
+   compatible = "fsl,mc34708";
+   reg = <0x8>;
+   };
+};
+
+&i2c3 {
+   pinctrl-names = "default", "gpio";
+   pinctrl-0 = <&pinctrl_i2c3>;
+   pinctrl-1 = <&pinctrl_i2c3_gpio>;
+   clock_frequency = <10>;
+
+   scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+   sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+
+   status = "okay";
+};
+
+&iomuxc {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_hog>;
+
+   imx53-kp {
+   pinctrl_eth: ethgrp {
+   fsl,pins = <
+   MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
+   MX53_PAD_FEC_MDC__FEC_MDC 0x4
+   MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
+   MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
+   MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
+   MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
+   MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
+   MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
+   /* The RX_ER pin needs to be pull down */
+   /* for this device */
+   MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1c0
+   MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
+   >;
+   };
+
+   pinctrl_hog: hoggrp {
+   fsl,pins = <
+   /* PHY RESET */
+   MX53_PAD_PATA_DA_0__GPIO7_6 0x182
+   /* VBUS_PWR_EN */
+   MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
+   /* BOOSTER_OFF */
+   MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
+   >;
+   };
+
+   pinctrl_i2c2: i2c2grp {
+   fsl,pins = <
+   MX53_PAD_KEY_ROW3__I2C2_SDA
+(0x1ee | IMX_PAD_SION)
+   MX53_PAD_KEY_COL3__I2C2_SCL
+(0x1ee | IMX_PAD_SION)
+   >;
+   };
+
+   pinctrl_i2c2_gpio: i2c2grpgpio {
+   fsl,pins = <
+

Re: [U-Boot] [PATCH 0/8] Initial integration of AVB2.0

[Igor Opaniuk]

On 26 April 2018 at 06:05, Kever Yang  wrote:
> Hi Igor,
>
> It's great to see the patch set to support AVB2.0, the upstream
> libavb(from aosp) combine the AVB with A/B which I think should be
> two separate feature, are you going to split them?

Hi Kever,

Right, support of verification of A/B slots is going to be in a
separate patch-set.

> BTW, do you have plan to update boot_android cmd to support avb?
> the command is too weak for use now.
> And any plan to add opptee_client/smcc to talk to OPTEE/ATF?

Did you mean boot_android cmd from this patch
https://lists.denx.de/pipermail/u-boot/2017-April/285867.html,
that was never up-streamed? I guess the main suggestion was to extend
existing bootm (by adding detection and parsing of Android boot images)
instead of introducing brand new command for booting Android.

As currently major amount of boards use sequence of mmc/bootm
commands for this purposes and bootm obviously is supposed to boot
something from RAM, I assumed that it would be wrong to invoke avb
verification from bootm itself. Because of this reason I've introduced
avb set of commands for explicitly triggering the verification process.
You can check the example how AVB2.0 is enabled on AM57xx HS
(check "am57xx_hs: avb2.0: add support of AVB 2.0" patch).

The only one prerequisite is that U-boot env itself should be also a part
of chain of trust  (so it can't be tampered and "avb verify" removed)

Best regards,
Igor

>
> Thanks,
> - Kever
> On 04/25/2018 09:17 PM, Igor Opaniuk wrote:
>> This series of patches introduces support of Android Verified Boot 2.0,
>> which provides integrity checking of Android partitions on MMC.
>>
>> It integrates libavb/libavb_ab into the U-boot, provides implementation of
>> AvbOps, subset of `avb` commands to run verification chain (and for debugging
>> purposes), and it enables AVB2.0 verification on AM57xx HS SoC by default.
>>
>> Currently, there is still no support for verification of A/B boot slots
>> and no rollback protection (for storing rollback indexes
>> there are plans to use eMMC RPMB)
>>
>> Libavb/libavb_ab will be deviated from AOSP upstream in the future,
>> that's why minimal amount of changes were introduced into the lib sources,
>> so checkpatch may fail.
>>
>> For additional details check [1] AVB 2.0 README and doc/README.avb2, which
>> is a part of this patchset.
>>
>> [1] https://android.googlesource.com/platform/external/avb/+/master/README.md
>>
>> Igor Opaniuk (8):
>>   avb2.0: add Android Verified Boot 2.0 libraries
>>   avb2.0: integrate avb 2.0 into the build system
>>   avb2.0: implement AVB ops
>>   cmd: avb2.0: avb command for performing verification
>>   avb2.0: add boot states and dm-verity support
>>   am57xx_hs: avb2.0: add support of AVB 2.0
>>   test/py: avb2.0: add tests for avb commands
>>   doc: avb2.0: add README about AVB2.0 integration
>>
>>  cmd/Kconfig  |   15 +
>>  cmd/Makefile |3 +
>>  cmd/avb.c|  366 
>>  common/Makefile  |2 +
>>  common/avb_verify.c  |  748 
>>  configs/am57xx_hs_evm_defconfig  |3 +
>>  doc/README.avb2  |  100 +++
>>  include/avb/avb_ab_flow.h|  235 ++
>>  include/avb/avb_ab_ops.h |   61 ++
>>  include/avb/avb_chain_partition_descriptor.h |   54 ++
>>  include/avb/avb_crypto.h |  147 
>>  include/avb/avb_descriptor.h |  113 +++
>>  include/avb/avb_footer.h |   68 ++
>>  include/avb/avb_hash_descriptor.h|   55 ++
>>  include/avb/avb_hashtree_descriptor.h|   65 ++
>>  include/avb/avb_kernel_cmdline_descriptor.h  |   63 ++
>>  include/avb/avb_ops.h|  196 +
>>  include/avb/avb_property_descriptor.h|   89 ++
>>  include/avb/avb_rsa.h|   55 ++
>>  include/avb/avb_sha.h|   72 ++
>>  include/avb/avb_slot_verify.h|  239 ++
>>  include/avb/avb_sysdeps.h|   97 +++
>>  include/avb/avb_util.h   |  259 ++
>>  include/avb/avb_vbmeta_image.h   |  272 ++
>>  include/avb/avb_version.h|   45 +
>>  include/avb/libavb.h |   32 +
>>  include/avb/libavb_ab.h  |   22 +
>>  include/avb_verify.h |   97 +++
>>  include/configs/am57xx_evm.h |   11 +
>>  include/environment/ti/boot.h|   15 +
>>  lib/Kconfig  |   20 +
>>  lib/Makefile |2 +
>>  lib/libavb/Makefile  |   15 +
>>  lib/libavb/avb_chain_partition_descriptor.c  |   46 +
>>  lib/libavb/avb_crypto.c  |  355 
>>  lib/liba