Re: [PATCH 13/13] cbfs: Don't require the CBFS size with cbfs_init_mem()

[Bin Meng]

On Wed, May 13, 2020 at 10:24 PM Simon Glass  wrote:
>
> The size is not actually used since it is present in the header. Drop this
> parameter. Also tidy up error handling while we are here.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/lib/fsp2/fsp_init.c | 3 +--
>  fs/cbfs/cbfs.c   | 9 +
>  include/cbfs.h   | 3 +--
>  3 files changed, 7 insertions(+), 8 deletions(-)
>

Reviewed-by: Bin Meng 

Re: [PATCH 12/13] cbfs: Allow reading a file from a CBFS given its base addr

[Bin Meng]

Hi Simon,

On Wed, May 13, 2020 at 10:24 PM Simon Glass  wrote:
>
> Currently we support reading a file from CBFS given the address of the end
> of the ROM. Sometimes we only know the start of the CBFS. Add a function
> to find a file given that.
>
> Signed-off-by: Simon Glass 
> ---
>
>  fs/cbfs/cbfs.c | 13 +
>  include/cbfs.h | 11 +++
>  2 files changed, 24 insertions(+)
>
> diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c
> index 76613fa871..1603409a8f 100644
> --- a/fs/cbfs/cbfs.c
> +++ b/fs/cbfs/cbfs.c
> @@ -413,6 +413,19 @@ int file_cbfs_find_uncached(ulong end_of_rom, const char 
> *name,
> return find_uncached(, name, start, node);
>  }
>
> +int file_cbfs_find_uncached_base(ulong base, const char *name,
> +struct cbfs_cachenode *node)
> +{
> +   struct cbfs_priv priv;
> +   int ret;
> +
> +   ret = cbfs_load_header_ptr(, base);
> +   if (ret)
> +   return ret;
> +
> +   return find_uncached(, name, (u8 *)base, node);

(void *)base

> +}
> +
>  const char *file_cbfs_name(const struct cbfs_cachenode *file)
>  {
> cbfs_s.result = CBFS_SUCCESS;
> diff --git a/include/cbfs.h b/include/cbfs.h
> index 4dd3c0795d..b1a8d2cad2 100644
> --- a/include/cbfs.h
> +++ b/include/cbfs.h
> @@ -173,6 +173,17 @@ int cbfs_init_mem(ulong base, ulong size, struct 
> cbfs_priv **privp);
>  int file_cbfs_find_uncached(ulong end_of_rom, const char *name,
> struct cbfs_cachenode *node);
>
> +/**
> + * file_cbfs_find_uncached() - Find a file in CBFS without using the heap

file_cbfs_find_uncached_base(), and the description is wrong

> + *
> + * @base: Points to the base of the CBFS
> + * @name: The name to search for
> + * @node: Returns the node if found
> + * @return 0 on success, -ENOENT if not found, -EFAULT on bad header
> + */
> +int file_cbfs_find_uncached_base(ulong base, const char *name,
> +struct cbfs_cachenode *node);
> +
>  /**
>   * file_cbfs_name() - Get the name of a file in CBFS.
>   *

Regards,
Bin

Re: [PATCH 11/13] cbfs: Change file_cbfs_find_uncached() to return an error

[Bin Meng]

Hi Simon,

On Wed, May 13, 2020 at 10:24 PM Simon Glass  wrote:
>
> This function currently returns a node pointer so there is no way to know
> the error code. Also it uses data in BSS which seems unnecessary since the
> caller might prefer to use a local variable.
>
> Update the function and split its body out into a separate function so we
> can use it later.
>
> Signed-off-by: Simon Glass 
> ---
>
>  fs/cbfs/cbfs.c | 48 +++-
>  include/cbfs.h | 16 +++-
>  2 files changed, 34 insertions(+), 30 deletions(-)
>
> diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c
> index 0db7cb9147..76613fa871 100644
> --- a/fs/cbfs/cbfs.c
> +++ b/fs/cbfs/cbfs.c
> @@ -371,40 +371,46 @@ const struct cbfs_cachenode *file_cbfs_find(const char 
> *name)
> return cbfs_find_file(_s, name);
>  }
>
> -const struct cbfs_cachenode *file_cbfs_find_uncached(ulong end_of_rom,
> -const char *name)
> +static int find_uncached(struct cbfs_priv *priv, const char *name, u8 *start,

This should be void *start

> +struct cbfs_cachenode *node)
>  {
> -   struct cbfs_priv *priv = _s;
> -   void *start;
> -   u32 size;
> -   u32 align;
> -   static struct cbfs_cachenode node;
> -
> -   if (file_cbfs_load_header(priv, end_of_rom))
> -   return NULL;
> -
> -   start = priv->start;
> -   size = priv->header.rom_size;
> -   align = priv->header.align;
> +   int size = priv->header.rom_size;
> +   int align = priv->header.align;
>
> while (size >= align) {
> -   int ret;
> int used;
> +   int ret;
>
> -   ret = file_cbfs_next_file(priv, start, size, align, ,
> +   ret = file_cbfs_next_file(priv, start, size, align, node,
>   );
> if (ret == -ENOENT)
> break;
> else if (ret)
> -   return NULL;
> -   if (!strcmp(name, node.name))
> -   return 
> +   return ret;
> +   if (!strcmp(name, node->name))
> +   return 0;
>
> size -= used;
> start += used;
> }
> -   cbfs_s.result = CBFS_FILE_NOT_FOUND;
> -   return NULL;
> +   priv->result = CBFS_FILE_NOT_FOUND;
> +
> +   return -ENOENT;
> +}
> +
> +int file_cbfs_find_uncached(ulong end_of_rom, const char *name,
> +   struct cbfs_cachenode *node)
> +{
> +   struct cbfs_priv priv;
> +   u8 *start;
> +   int ret;
> +
> +   ret = file_cbfs_load_header(, end_of_rom);
> +   if (ret)
> +   return ret;
> +   start = (u8 *)(end_of_rom + 1 - priv.header.rom_size);

This should be: start = priv->start;

> +
> +   return find_uncached(, name, start, node);
>  }
>
>  const char *file_cbfs_name(const struct cbfs_cachenode *file)
> diff --git a/include/cbfs.h b/include/cbfs.h
> index 5cc27d682d..4dd3c0795d 100644
> --- a/include/cbfs.h
> +++ b/include/cbfs.h
> @@ -163,17 +163,15 @@ int cbfs_init_mem(ulong base, ulong size, struct 
> cbfs_priv **privp);
>  /***/
>
>  /**
> - * file_cbfs_find_uncached() - Find a file with a particular name in CBFS
> - * without using the heap.
> + * file_cbfs_find_uncached() - Find a file in CBFS without using the heap
>   *
> - * @end_of_rom:Points to the end of the ROM the CBFS should 
> be read
> - *  from.
> - * @name:  The name to search for.
> - *
> - * @return A handle to the file, or NULL on error.
> + * @end_of_rom: Points to the end of the ROM the CBFS should be read from
> + * @name: The name to search for
> + * @node: Returns the node if found

This is misleading. Based on the comments it seems that we should
declare this to be:

struct cbfs_cachenode **node

> + * @return 0 on success, -ENOENT if not found, -EFAULT on bad header
>   */
> -const struct cbfs_cachenode *file_cbfs_find_uncached(ulong end_of_rom,
> -const char *name);
> +int file_cbfs_find_uncached(ulong end_of_rom, const char *name,
> +   struct cbfs_cachenode *node);
>
>  /**
>   * file_cbfs_name() - Get the name of a file in CBFS.
> --

Regards,
Bin

Re: [PATCH v12 21/21] riscv: Add Sipeed Maix support

[Rick Chen]

Hi Sean

>
> The Sipeed Maix series is a collection of boards built around the RISC-V
> Kendryte K210 processor. This processor contains several peripherals to
> accelerate neural network processing and other "ai" tasks. This includes a
> "KPU" neural network processor, an audio processor supporting beamforming
> reception, and a digital video port supporting capture and output at VGA
> resolution. Other peripherals include 8M of sram (accessible with and
> without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
> accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
> peripherals vary, but include spi flash; on-board usb-serial bridges; ports
> for cameras, displays, and sd cards; and ESP32 chips. Currently, only the
> Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly
> similar.
>
> Documentation for Maix boards is located at
> .  Documentation for the Kendryte K210 is
> located at . However, hardware details are
> rather lacking, so most technical reference has been taken from the
> standalone sdk located at
> .
>
> Signed-off-by: Sean Anderson 
> ---

This v12 series still have warnings and one error when compile

drivers/clk/kendryte/bypass.c:11: warning: "LOG_CATEGORY" redefined
   11 | #define LOG_CATEGORY UCLASS_CLK
  |
In file included from include/linux/compat.h:4,
 from include/linux/err.h:5,
 from include/clk.h:12,
 from include/kendryte/bypass.h:8,
 from drivers/clk/kendryte/bypass.c:6:
include/log.h:105: note: this is the location of the previous definition

drivers/reset/reset-syscon.c: In function 'syscon_reset_request':
drivers/reset/reset-syscon.c:25:6: warning: implicit declaration of function 'BI
   25 |  if (BIT(rst->id) & priv->mask)

Meanwhile v11 still fail in CI verification.
https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/689149050

If the difference between v11 and v12 is only removing the Sanity
check, then the v12 shall have the same result in CI verification.
Please check about that

Thanks,
Rick


>
> Changes in v9:
> - Update MAINTAINERS to reflect defconfig name change
>
> Changes in v8:
> - Remove unnecessary fdt fixup for sipeed maix
>
> Changes in v7:
> - Split docs off into their own patch
> - Enable ram clocks by name
>
> Changes in v6:
> - Remove trailing whitespace from documentation
> - Remove configuration for spi/pinmux/gpio features
> - Flesh out documentation some more
>
> Changes in v5:
> - Configure relocation location with CONFIG_SYS_SDRAM_*
> - Enable ram clocks
> - Add pinmux/gpio/led support
> - Remove (broken) MMC support
> - Store the environment in flash
> - Add partitions
> - Add bootcmd
> - Add docs for pinctrl and booting
>
> Changes in v4:
> - Rework documentation to be organized by board mfg not cpu mfg
> - Update docs to reflect working SPI support
> - Add proper spi support
> - Don't define unneecessary macros in config.h
> - Lower the default stack so it isn't clobbered on relocation
> - Update MAINTAINERS
> - Update copyright
>
> Changes in v3:
> - Reorder to be last in the patch series
> - Add documentation for the board
> - Generate defconfig with "make savedefconfig"
> - Update Kconfig to imply most features we need
> - Update MAINTAINERS
>
> Changes in v2:
> - Select CONFIG_SYS_RISCV_NOCOUNTER
> - Imply CONFIG_CLK_K210
> - Remove spurious references to CONFIG_ARCH_K210
> - Remove many configs from defconfig where the defaults were fine
> - Add a few "not set" lines to suppress unneeded defaults
> - Reduce pre-reloc malloc space, now that clocks initialization happens
>   later
>
>  arch/riscv/Kconfig |  4 +++
>  board/sipeed/maix/Kconfig  | 47 ++
>  board/sipeed/maix/MAINTAINERS  | 11 +++
>  board/sipeed/maix/Makefile |  5 
>  board/sipeed/maix/maix.c   | 41 ++
>  configs/sipeed_maix_bitm_defconfig |  8 +
>  include/configs/sipeed-maix.h  | 24 +++
>  7 files changed, 140 insertions(+)
>  create mode 100644 board/sipeed/maix/Kconfig
>  create mode 100644 board/sipeed/maix/MAINTAINERS
>  create mode 100644 board/sipeed/maix/Makefile
>  create mode 100644 board/sipeed/maix/maix.c
>  create mode 100644 configs/sipeed_maix_bitm_defconfig
>  create mode 100644 include/configs/sipeed-maix.h
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index a611f890a1..82d58ea370 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT
>  config TARGET_SIFIVE_FU540
> bool "Support SiFive FU540 Board"
>
> +config TARGET_SIPEED_MAIX
> +   bool "Support Sipeed Maix Board"
> +
>  endchoice
>
>  config SYS_ICACHE_OFF
> @@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
>  source "board/emulation/qemu-riscv/Kconfig"

Re: [PATCH 10/13] cbfs: Return the error code from file_cbfs_init()

[Bin Meng]

On Wed, May 13, 2020 at 10:24 PM Simon Glass  wrote:
>
> We may as well return the error code and use it directly in the command
> code. CBFS still uses its own error enum which we may be able to remove,
> but leave it for now.
>
> Signed-off-by: Simon Glass 
> ---
>
>  cmd/cbfs.c |  3 +--
>  fs/cbfs/cbfs.c | 23 +++
>  include/cbfs.h |  6 +++---
>  3 files changed, 19 insertions(+), 13 deletions(-)
>

Reviewed-by: Bin Meng 

Re: [PATCH 09/13] cbfs: Record the start address in cbfs_priv

[Bin Meng]

On Wed, May 13, 2020 at 10:24 PM Simon Glass  wrote:
>
> The start address of the CBFS is used when scanning for files. It makes
> sense to put this in our cbfs_priv struct and calculate it when we read
> the header.
>
> Update the code accordingly.
>
> Signed-off-by: Simon Glass 
> ---
>
>  fs/cbfs/cbfs.c | 44 +++-
>  1 file changed, 31 insertions(+), 13 deletions(-)
>

Reviewed-by: Bin Meng 

Re: [PATCH 08/13] cbfs: Use void * for the position pointers

[Bin Meng]

On Wed, May 13, 2020 at 10:24 PM Simon Glass  wrote:
>
> It doesn't make sense to use u8 * as the pointer type for accessing the
> CBFS since we do not access it as bytes, but via structures. Change it to
> void *, which allows us to avoid a cast.
>
> Signed-off-by: Simon Glass 
> ---
>
>  fs/cbfs/cbfs.c | 17 -
>  1 file changed, 8 insertions(+), 9 deletions(-)
>

Reviewed-by: Bin Meng 

Re: [PATCH 07/13] cbfs: Unify the two header loaders

[Bin Meng]

Hi Simon,

On Wed, May 13, 2020 at 10:24 PM Simon Glass  wrote:
>
> These two functions have mostly the same code. Pull this out into a common
> function.
>
> Also make this function zero the private data so that callers don't have
> to do it. Finally, update cbfs_load_header_ptr() to take the base of the
> ROM as its parameter, which makes more sense than passing the address of
> the header within the ROM.
>
> Signed-off-by: Simon Glass 
> ---
>
>  fs/cbfs/cbfs.c | 59 +++---
>  1 file changed, 37 insertions(+), 22 deletions(-)
>
> diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c
> index 05de58cf19..b4e6b959d1 100644
> --- a/fs/cbfs/cbfs.c
> +++ b/fs/cbfs/cbfs.c
> @@ -177,47 +177,63 @@ static int file_cbfs_fill_cache(struct cbfs_priv *priv, 
> u8 *start, u32 size,
> return 0;
>  }
>
> -/* Get the CBFS header out of the ROM and do endian conversion. */
> -static int file_cbfs_load_header(struct cbfs_priv *priv, ulong end_of_rom)
> +/**
> + * load_header() - Load the CBFS header
> + *
> + * Get the CBFS header out of the ROM and do endian conversion.
> + *
> + * @priv: Private data, which is inited by this function
> + * @addr: Address of CBFS header in memory-mapped SPI flash
> + * @return 0 if OK, -ENXIO if the header is bad
> + */
> +static int load_header(struct cbfs_priv *priv, ulong addr)
>  {
> struct cbfs_header *header = >header;
> struct cbfs_header *header_in_rom;
> -   int32_t offset = *(u32 *)(end_of_rom - 3);
>
> -   header_in_rom = (struct cbfs_header *)(end_of_rom + offset + 1);
> +   memset(priv, '\0', sizeof(*priv));
> +   header_in_rom = (struct cbfs_header *)addr;
> swap_header(header, header_in_rom);
>
> if (header->magic != good_magic || header->offset >
> header->rom_size - header->boot_block_size) {
> priv->result = CBFS_BAD_HEADER;
> -   return 1;
> +   return -ENXIO;
> }
> +
> return 0;
>  }
>
> -static int cbfs_load_header_ptr(struct cbfs_priv *priv, ulong base)
> +/**
> + * file_cbfs_load_header() - Get the CBFS header out of the ROM, given the 
> end
> + *
> + * @priv: Private data, which is inited by this function
> + * @addr: Address of the last byte of the ROM (typically 0x)

This should be end_of_rom

> + * @return 0 if OK, -ENXIO if the header is bad
> + */
> +static int file_cbfs_load_header(struct cbfs_priv *priv, ulong end_of_rom)
>  {
> -   struct cbfs_header *header = >header;
> -   struct cbfs_header *header_in_rom;
> -
> -   header_in_rom = (struct cbfs_header *)base;
> -   swap_header(header, header_in_rom);
> +   int offset = *(u32 *)(end_of_rom - 3);
>
> -   if (header->magic != good_magic || header->offset >
> -   header->rom_size - header->boot_block_size) {
> -   priv->result = CBFS_BAD_HEADER;
> -   return -EFAULT;
> -   }
> +   return load_header(priv, end_of_rom + offset + 1);
> +}
>
> -   return 0;
> +/**
> + * cbfs_load_header_ptr() - Get the CBFS header out of the ROM, given the 
> base
> + *
> + * @priv: Private data, which is inited by this function
> + * @addr: Address of the first byte of the ROM (e.g. 0xff00)

This should be base

> + * @return 0 if OK, -ENXIO if the header is bad
> + */
> +static int cbfs_load_header_ptr(struct cbfs_priv *priv, ulong base)
> +{
> +   return load_header(priv, base + MASTER_HDR_OFFSET);
>  }
>
>  static void cbfs_init(struct cbfs_priv *priv, ulong end_of_rom)
>  {
> u8 *start_of_rom;
>
> -   priv->initialised = false;
> -
> if (file_cbfs_load_header(priv, end_of_rom))
> return;
>
> @@ -241,10 +257,9 @@ int cbfs_init_mem(ulong base, ulong size, struct 
> cbfs_priv **privp)
>
> /*
>  * Use a local variable to start with until we know that the CBFS is
> -* valid. Assume that a master header appears at the start, at offset
> -* 0x38.
> +* valid.
>  */
> -   ret = cbfs_load_header_ptr(priv, base + MASTER_HDR_OFFSET);
> +   ret = cbfs_load_header_ptr(priv, base);
> if (ret)
> return ret;
>

Regards,
Bin

Re: [PATCH 2/2] fdtdec: Honor #address-cells and #size-cells in fdtdec_add_reserved_memory()

[Bin Meng]

Hi Simon,

On Wed, May 20, 2020 at 10:20 PM Simon Glass  wrote:
>
> Hi Bin,
>
> On Wed, 20 May 2020 at 00:38, Bin Meng  wrote:
> >
> > From: Bin Meng 
> >
> > At present fdtdec_add_reserved_memory() calls fdtdec_get_addr_size()
> > to get address and size for the subnodes of /reserved-memory node.
> >
> > We should honor #address-cells and #size-cells properties in the
> > parent node.
> >
> > Signed-off-by: Bin Meng 
> > ---
> >
> >  lib/fdtdec.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
>
> Reviewed-by: Simon Glass 
>
> Are there no tests for this?

There is currently no tests for this unforuatunately.

Regards,
Bin

Re: [RESEND PATCH] usb: dwc3: fix NULL pointer issue

[Chunfeng Yun]

Hi Marek,
On Wed, 2020-05-20 at 13:44 +0200, Marek Vasut wrote:
> On 5/20/20 9:53 AM, Chunfeng Yun wrote:
> > Hi Marek,
> > 
> > On Thu, 2020-05-14 at 13:55 +0800, Chunfeng Yun wrote:
> >> The phy_bulk pointer *usb_phys is used before allocated,
> >> fix it by using a phy_bulk variable instead in
> >> xhci_dwc3_platdata struct
> >>
> 
> I'm never receiving the emails to the denx address listed in the
> MAINTAINERS, any ideas why ?
I received the following email when I sent out this patch.
It seems the email is sent out, but rejected by server of denx



Delivery has failed to these recipients or groups:

ma...@denx.de
A problem occurred while delivering this message to this email address.
Try sending this message again. If the problem continues, please contact
your helpdesk.


The following organization rejected your message: mail-in.m-online.net
[212.114.242.10].


Diagnostic information for administrators:

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Message-ID: <1589961238.5899.11.camel@mhfsdcap03>
Subject: Re: [RESEND PATCH] usb: dwc3: fix NULL pointer issue
From: Chunfeng Yun 
To: Marek Vasut 
CC: GSS_MTK_Uboot_upstream , Ryder
Lee
, Weijie Gao ,

Date: Wed, 20 May 2020 15:53:58 +0800
In-Reply-To:
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> 
> Anyway, I'll pick this one, thanks.

Re: [PATCH 1/1] test: stabilize test_efi_secboot

[AKASHI Takahiro]

Heinrich,

On Mon, May 11, 2020 at 03:56:56PM +0900, AKASHI Takahiro wrote:
> Heinrich,
> 
> On Fri, May 08, 2020 at 08:10:28AM +0900, AKASHI Takahiro wrote:
> > On Thu, May 07, 2020 at 11:14:17PM +0200, Heinrich Schuchardt wrote:
> > > On 5/7/20 2:36 AM, AKASHI Takahiro wrote:
> > > > Heinrich,
> > > >
> > > > On Mon, May 04, 2020 at 12:33:26PM +0200, Heinrich Schuchardt wrote:
> > > >> When setting up the console via function efi_console_register() we call
> > > >> query_console_serial(). This functions sends an escape sequence to the
> > > >> terminal to query the display size. The response is another escape
> > > >> sequence.
> > > >>
> > > >> console.run_command_list() is looking for a regular expression '^==>'.
> > > >> If the escape sequence for the screen size precedes the prompt without 
> > > >> a
> > > >> line break, no match is found.
> > > >>
> > > >> When efi_disk_register() is called before efi_console_register() this 
> > > >> leads
> > > >> to a test failuere of the UEFI secure boot tests.
> > > >
> > > > Why does the order of those calls affect test results?
> > > 
> > > Please, have a look at function query_console_serial() and at
> > > run_command_list().
> > > 
> > > As described above:
> > > '\e7\e[r\e[999;999H\e[6n\e8==>' cannot be matched by regular expression
> > > '^==>'.
> > 
> > (Probably) right, but what I don't get here is why efi_disk_register()
> > have an impact on efi_console_register(). The former function has
> > nothing to do with any console behaviors.
> 
> You have merged your patch without replying to my comment.


Not yet


> > Moreover, I wonder
> > - why you want to move efi_console_register() after efi_disk_register().
> > - why python script can see such escape sequences.
> 
> I don't like your fix.
> With your fixes, my secure boot pytest now fails to run
> on sandbox locally.
> 
> Instead, I propose:
> 1. revert your commits
>commit 16ad946f41d3 ("efi_loader: change setup sequence")
>commit 5827c2545849 ("test: stabilize test_efi_secboot")
> 2. move efi_console_register() forward *before* efi_console_register()
> 
> 
> Then my secure boot test should work again without any modification.
> I believe that my solution is much better than your workaround.


Any comment?
Or do you want me to post a patch?


> -Takahiro Akashi
> 
> > > 
> > > >
> > > >> We can avoid the problem if the first UEFI command passed to
> > > >> u_boot_console.run_command_list() produces output. This patch achieves 
> > > >> this
> > > >> by appending '; echo' to the first UEFI related command of the 
> > > >> problematic
> > > >> tests.
> > > >
> > > > It looks to be a workaround.
> > > > We'd better have another approach to fix the problem.
> > > > Otherwise, similar issues will occur again.
> > > 
> > > I would not like to change the logic in Python to detect the U-Boot
> > > prompt for something UEFI specific. And we need a method to determine
> > > the size of a serial console.
> > > 
> > > The current approach allowed me to merge your patch series which
> > > otherwise might not have reached the v2020.07 release. Did the problem
> > > not show up in your Travis CI testing?
> > 
> > No. If your saying is correct, this can happen only if 
> > efi_console_register()
> > is moved after efi_disk_register(). Right?
> > 
> > > If you have a better solution, we can easily merge your patch.
> > 
> > First, I want to understand what's happening.
> > 
> > -Takahiro Akashi
> > 
> > > Best regards
> > > 
> > > Heinrich
> > > 
> > > >
> > > > Thanks,
> > > > -Takahiro Akashi
> > > >
> > > >> Signed-off-by: Heinrich Schuchardt 
> > > >> ---
> > > >>  test/py/tests/test_efi_secboot/test_authvar.py  | 8 
> > > >>  test/py/tests/test_efi_secboot/test_signed.py   | 4 ++--
> > > >>  test/py/tests/test_efi_secboot/test_unsigned.py | 6 +++---
> > > >>  3 files changed, 9 insertions(+), 9 deletions(-)
> > > >>
> > > >> diff --git a/test/py/tests/test_efi_secboot/test_authvar.py 
> > > >> b/test/py/tests/test_efi_secboot/test_authvar.py
> > > >> index 55dcaa95f1..9912694a3e 100644
> > > >> --- a/test/py/tests/test_efi_secboot/test_authvar.py
> > > >> +++ b/test/py/tests/test_efi_secboot/test_authvar.py
> > > >> @@ -133,7 +133,7 @@ class TestEfiAuthVar(object):
> > > >>  output = u_boot_console.run_command_list([
> > > >>  'host bind 0 %s' % disk_img,
> > > >>  'fatload host 0:1 400 PK.auth',
> > > >> -'setenv -e -nv -bs -rt -at -i 400,$filesize PK',
> > > >> +'setenv -e -nv -bs -rt -at -i 400,$filesize PK; 
> > > >> echo',
> > > >>  'fatload host 0:1 400 KEK.auth',
> > > >>  'setenv -e -nv -bs -rt -at -i 400,$filesize KEK',
> > > >>  'fatload host 0:1 400 db.auth',
> > > >> @@ -174,7 +174,7 @@ class TestEfiAuthVar(object):
> > > >>  output = u_boot_console.run_command_list([
> > > >>  'host bind 0 %s' % disk_img,
> > 

Re: [PATCH] efi_loader: Remove unnecessary debug

[AKASHI Takahiro]

On Tue, May 19, 2020 at 12:24:27PM +0200, Heinrich Schuchardt wrote:
> On 19.05.20 12:13, Pragnesh Patel wrote:
> > Remove unnecessary debug() from efi_set_variable_common().
> > native_name is NULL, so there is no meaning to print it.
> >
> > Signed-off-by: Pragnesh Patel 
> 
> Reviewed-by: Heinrich Schuchardt 

Nak

> >  lib/efi_loader/efi_variable.c | 2 --
> >  1 file changed, 2 deletions(-)
> >
> > diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
> > index 10892684d1..9698efbc5d 100644
> > --- a/lib/efi_loader/efi_variable.c
> > +++ b/lib/efi_loader/efi_variable.c
> > @@ -883,8 +883,6 @@ static efi_status_t efi_set_variable_common(u16 
> > *variable_name,
> > u32 attr;
> > efi_status_t ret = EFI_SUCCESS;
> >
> > -   debug("%s: set '%s'\n", __func__, native_name);

Instead,
debug("%s: set '%ls'\n", __func__, variable_name);

It would be helpful for tracing activities.
This function can be used outside of this file, particularly,
to handle READ_ONLY variables there.

-Takahiro Akashi

> > -
> > if (!variable_name || !*variable_name || !vendor ||
> > ((attributes & EFI_VARIABLE_RUNTIME_ACCESS) &&
> >  !(attributes & EFI_VARIABLE_BOOTSERVICE_ACCESS))) {
> >
> 

[PATCH 1/1] efi_loader: device path for SATA devices

[Heinrich Schuchardt]

Provide device path nodes for SATA devices.

This avoids creation of two handles with the same device path indicating
our root node.

This is what the device paths for a SATA drive with four partitions could
like:

/VenHw(..)/Sata(0x0,0x,0x0)
/VenHw(..)/Sata(0x0,0x,0x0)/HD(1,MBR,0x81ea591f,0x800,0x63ff830)
/VenHw(..)/Sata(0x0,0x,0x0)/HD(2,MBR,0x81ea591f,0x6400800,0x9ff830)
/VenHw(..)/Sata(0x0,0x,0x0)/HD(3,MBR,0x81ea591f,0x6e00800,0x16ef2ab0)
/VenHw(..)/Sata(0x0,0x,0x0)/HD(4,MBR,0x81ea591f,0x1dcf3800,0x1dcedab0)

Signed-off-by: Heinrich Schuchardt 
---
 include/efi_api.h|  8 
 lib/efi_loader/efi_device_path.c | 21 +
 lib/efi_loader/efi_device_path_to_text.c | 10 ++
 3 files changed, 39 insertions(+)

diff --git a/include/efi_api.h b/include/efi_api.h
index 77d6bf2660..759d911875 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -457,6 +457,7 @@ struct efi_device_path_acpi_path {
 #  define DEVICE_PATH_SUB_TYPE_MSG_USB 0x05
 #  define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR0x0b
 #  define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS   0x0f
+#  define DEVICE_PATH_SUB_TYPE_MSG_SATA0x12
 #  define DEVICE_PATH_SUB_TYPE_MSG_NVME0x17
 #  define DEVICE_PATH_SUB_TYPE_MSG_SD  0x1a
 #  define DEVICE_PATH_SUB_TYPE_MSG_MMC 0x1d
@@ -480,6 +481,13 @@ struct efi_device_path_usb {
u8 usb_interface;
 } __packed;

+struct efi_device_path_sata {
+   struct efi_device_path dp;
+   u16 hba_port;
+   u16 port_multiplier_port;
+   u16 logical_unit_number;
+} __packed;
+
 struct efi_device_path_mac_addr {
struct efi_device_path dp;
struct efi_mac_addr mac;
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 1606c830b8..ac248e0ce1 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -456,6 +456,11 @@ __maybe_unused static unsigned int dp_size(struct udevice 
*dev)
return dp_size(dev->parent) +
sizeof(struct efi_device_path_sd_mmc_path);
 #endif
+#if defined(CONFIG_AHCI) || defined(CONFIG_SATA)
+   case UCLASS_AHCI:
+   return dp_size(dev->parent) +
+   sizeof(struct efi_device_path_sata);
+#endif
 #if defined(CONFIG_NVME)
case UCLASS_NVME:
return dp_size(dev->parent) +
@@ -621,6 +626,22 @@ __maybe_unused static void *dp_fill(void *buf, struct 
udevice *dev)
return [1];
}
 #endif
+#if defined(CONFIG_AHCI) || defined(CONFIG_SATA)
+   case UCLASS_AHCI: {
+   struct efi_device_path_sata *dp =
+   dp_fill(buf, dev->parent);
+   struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+   dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+   dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_SATA;
+   dp->dp.length   = sizeof(*dp);
+   dp->hba_port = desc->devnum;
+   /* default 0x implies no port multiplier */
+   dp->port_multiplier_port = 0x;
+   dp->logical_unit_number = desc->lun;
+   return [1];
+   }
+#endif
 #if defined(CONFIG_NVME)
case UCLASS_NVME: {
struct efi_device_path_nvme *dp =
diff --git a/lib/efi_loader/efi_device_path_to_text.c 
b/lib/efi_loader/efi_device_path_to_text.c
index af1adbb71e..ef9d8a58ed 100644
--- a/lib/efi_loader/efi_device_path_to_text.c
+++ b/lib/efi_loader/efi_device_path_to_text.c
@@ -148,6 +148,16 @@ static char *dp_msging(char *s, struct efi_device_path *dp)

break;
}
+   case DEVICE_PATH_SUB_TYPE_MSG_SATA: {
+   struct efi_device_path_sata *sdp =
+   (struct efi_device_path_sata *) dp;
+
+   s += sprintf(s, "Sata(0x%x,0x%x,0x%x)",
+sdp->hba_port,
+sdp->port_multiplier_port,
+sdp->logical_unit_number);
+   break;
+   }
case DEVICE_PATH_SUB_TYPE_MSG_NVME: {
struct efi_device_path_nvme *ndp =
(struct efi_device_path_nvme *)dp;
--
2.26.2

[PATCH 1/1] efi_loader: device path for virtio block devices

[Heinrich Schuchardt]

The UEFI specification does not define a device sub-type for virtio.
Let's use a vendor hardware node here.

This avoids creation of two handles with the same device path indicating
our root node.

Reported-by: Ard Biesheuvel 
Signed-off-by: Heinrich Schuchardt 
---
 include/efi_loader.h |  4 
 lib/efi_loader/efi_device_path.c | 30 ++
 2 files changed, 34 insertions(+)

diff --git a/include/efi_loader.h b/include/efi_loader.h
index 75c20e4679..f902d8765a 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -41,6 +41,10 @@ static inline void *guidcpy(void *dst, const void *src)
 #define U_BOOT_HOST_DEV_GUID \
EFI_GUID(0xbbe4e671, 0x5773, 0x4ea1, \
 0x9a, 0xab, 0x3a, 0x7d, 0xbf, 0x40, 0xc4, 0x82)
+/* GUID used as root for virtio devices */
+#define U_BOOT_VIRTIO_DEV_GUID \
+   EFI_GUID(0x63293792, 0xadf5, 0x9325, \
+0xb9, 0x9f, 0x4e, 0x0e, 0x45, 0x5c, 0x1b, 0x1e)

 /* Use internal device tree when starting UEFI application */
 #define EFI_FDT_USE_INTERNAL NULL
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index f9349484a6..1606c830b8 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -20,6 +20,9 @@
 #ifdef CONFIG_SANDBOX
 const efi_guid_t efi_guid_host_dev = U_BOOT_HOST_DEV_GUID;
 #endif
+#ifdef CONFIG_VIRTIO_BLK
+const efi_guid_t efi_guid_virtio_dev = U_BOOT_VIRTIO_DEV_GUID;
+#endif

 /* template END node: */
 static const struct efi_device_path END = {
@@ -467,6 +470,16 @@ __maybe_unused static unsigned int dp_size(struct udevice 
*dev)
  */
return dp_size(dev->parent)
+ sizeof(struct efi_device_path_vendor) + 1;
+#endif
+#ifdef CONFIG_VIRTIO_BLK
+   case UCLASS_VIRTIO:
+/*
+ * Virtio devices will be represented as a vendor
+ * device node with an extra byte for the device
+ * number.
+ */
+   return dp_size(dev->parent)
+   + sizeof(struct efi_device_path_vendor) + 1;
 #endif
default:
return dp_size(dev->parent);
@@ -545,6 +558,23 @@ __maybe_unused static void *dp_fill(void *buf, struct 
udevice *dev)
return >vendor_data[1];
}
 #endif
+#ifdef CONFIG_VIRTIO_BLK
+   case UCLASS_VIRTIO: {
+   struct efi_device_path_vendor *dp;
+   struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+   dp_fill(buf, dev->parent);
+   dp = buf;
+   ++dp;
+   dp->dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
+   dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
+   dp->dp.length = sizeof(*dp) + 1;
+   memcpy(>guid, _guid_virtio_dev,
+  sizeof(efi_guid_t));
+   dp->vendor_data[0] = desc->devnum;
+   return >vendor_data[1];
+   }
+#endif
 #ifdef CONFIG_IDE
case UCLASS_IDE: {
struct efi_device_path_atapi *dp =
--
2.26.2

[PATCH 1/1] doc: driver-model: there is no UCLASS_SATA

[Heinrich Schuchardt]

%s/UCLASS_SATA/UCLASS_AHCI/g

Signed-off-by: Heinrich Schuchardt 
---
 doc/driver-model/design.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/doc/driver-model/design.rst b/doc/driver-model/design.rst
index 635effcef6..9e9272777d 100644
--- a/doc/driver-model/design.rst
+++ b/doc/driver-model/design.rst
@@ -613,7 +613,7 @@ be connected on a SATA bus or standalone with no bus::
xhci_usb (UCLASS_USB)
   flash (UCLASS_FLASH_STORAGE)  - parent data/methods defined by USB bus

-   sata (UCLASS_SATA)
+   sata (UCLASS_AHCI)
   flash (UCLASS_FLASH_STORAGE)  - parent data/methods defined by SATA bus

flash (UCLASS_FLASH_STORAGE)  - no parent data/methods (not on a bus)
--
2.26.2

[PATCH 1/1] MAINTAINERS: add doc/driver-model/ to DRIVER MODEL

[Heinrich Schuchardt]

The documentation should rest with the same maintainer as the code.

Signed-off-by: Heinrich Schuchardt 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8add9d4c2a..d1c4a28ce3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -607,6 +607,7 @@ DRIVER MODEL
 M: Simon Glass 
 S: Maintained
 T: git https://gitlab.denx.de/u-boot/custodians/u-boot-dm.git
+F: doc/driver-model/
 F: drivers/core/
 F: include/dm/
 F: test/dm/
--
2.26.2

Re: pull request of u-boot-fsl-qoriq for v2020.07

[Tom Rini]

On Wed, May 20, 2020 at 05:19:12AM +, Priyanka Jain wrote:

> Dear Tom,
> 
> Please find my pull-request for u-boot-fsl-qoriq/master
> https://travis-ci.org/github/p-priyanka-jain/u-boot/builds
> 
> 
> Summary
> Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds
> QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based 
> platforms
> Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
> 
> Priyanka

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature

[PATCH 1/1] efi_loader: initialize root node first

[Heinrich Schuchardt]

With commit 16ad946f41d3 ("efi_loader: change setup sequence") the
detection of block device was moved to the start of the initialization
sequence. In the case of virtio devices to two handles with the same device
path being created.

The root node handle should be created before anything else.

Reported-by: Ard Biesheuvel 
Fixes: 16ad946f41d3 ("efi_loader: change setup sequence")
Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_setup.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index 26a7423203..dd0c53fc23 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -135,6 +135,11 @@ efi_status_t efi_init_obj_list(void)
/* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */
switch_to_non_secure_mode();

+   /* Initialize root node */
+   ret = efi_root_node_register();
+   if (ret != EFI_SUCCESS)
+   goto out;
+
 #ifdef CONFIG_PARTITIONS
ret = efi_disk_register();
if (ret != EFI_SUCCESS)
@@ -175,11 +180,6 @@ efi_status_t efi_init_obj_list(void)
if (ret != EFI_SUCCESS)
goto out;

-   /* Initialize root node */
-   ret = efi_root_node_register();
-   if (ret != EFI_SUCCESS)
-   goto out;
-
/* Initialize EFI driver uclass */
ret = efi_driver_init();
if (ret != EFI_SUCCESS)
--
2.26.2

[PATCH v12 21/21] riscv: Add Sipeed Maix support

[Sean Anderson]

The Sipeed Maix series is a collection of boards built around the RISC-V
Kendryte K210 processor. This processor contains several peripherals to
accelerate neural network processing and other "ai" tasks. This includes a
"KPU" neural network processor, an audio processor supporting beamforming
reception, and a digital video port supporting capture and output at VGA
resolution. Other peripherals include 8M of sram (accessible with and
without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
peripherals vary, but include spi flash; on-board usb-serial bridges; ports
for cameras, displays, and sd cards; and ESP32 chips. Currently, only the
Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly
similar.

Documentation for Maix boards is located at
.  Documentation for the Kendryte K210 is
located at . However, hardware details are
rather lacking, so most technical reference has been taken from the
standalone sdk located at
.

Signed-off-by: Sean Anderson 
---

Changes in v9:
- Update MAINTAINERS to reflect defconfig name change

Changes in v8:
- Remove unnecessary fdt fixup for sipeed maix

Changes in v7:
- Split docs off into their own patch
- Enable ram clocks by name

Changes in v6:
- Remove trailing whitespace from documentation
- Remove configuration for spi/pinmux/gpio features
- Flesh out documentation some more

Changes in v5:
- Configure relocation location with CONFIG_SYS_SDRAM_*
- Enable ram clocks
- Add pinmux/gpio/led support
- Remove (broken) MMC support
- Store the environment in flash
- Add partitions
- Add bootcmd
- Add docs for pinctrl and booting

Changes in v4:
- Rework documentation to be organized by board mfg not cpu mfg
- Update docs to reflect working SPI support
- Add proper spi support
- Don't define unneecessary macros in config.h
- Lower the default stack so it isn't clobbered on relocation
- Update MAINTAINERS
- Update copyright

Changes in v3:
- Reorder to be last in the patch series
- Add documentation for the board
- Generate defconfig with "make savedefconfig"
- Update Kconfig to imply most features we need
- Update MAINTAINERS

Changes in v2:
- Select CONFIG_SYS_RISCV_NOCOUNTER
- Imply CONFIG_CLK_K210
- Remove spurious references to CONFIG_ARCH_K210
- Remove many configs from defconfig where the defaults were fine
- Add a few "not set" lines to suppress unneeded defaults
- Reduce pre-reloc malloc space, now that clocks initialization happens
  later

 arch/riscv/Kconfig |  4 +++
 board/sipeed/maix/Kconfig  | 47 ++
 board/sipeed/maix/MAINTAINERS  | 11 +++
 board/sipeed/maix/Makefile |  5 
 board/sipeed/maix/maix.c   | 41 ++
 configs/sipeed_maix_bitm_defconfig |  8 +
 include/configs/sipeed-maix.h  | 24 +++
 7 files changed, 140 insertions(+)
 create mode 100644 board/sipeed/maix/Kconfig
 create mode 100644 board/sipeed/maix/MAINTAINERS
 create mode 100644 board/sipeed/maix/Makefile
 create mode 100644 board/sipeed/maix/maix.c
 create mode 100644 configs/sipeed_maix_bitm_defconfig
 create mode 100644 include/configs/sipeed-maix.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a611f890a1..82d58ea370 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT
 config TARGET_SIFIVE_FU540
bool "Support SiFive FU540 Board"
 
+config TARGET_SIPEED_MAIX
+   bool "Support Sipeed Maix Board"
+
 endchoice
 
 config SYS_ICACHE_OFF
@@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/fu540/Kconfig"
+source "board/sipeed/maix/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
new file mode 100644
index 00..0cdcd32adc
--- /dev/null
+++ b/board/sipeed/maix/Kconfig
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2019-20 Sean Anderson 
+
+if TARGET_SIPEED_MAIX
+
+config SYS_BOARD
+   default "maix"
+
+config SYS_VENDOR
+   default "sipeed"
+
+config SYS_CPU
+   default "generic"
+
+config SYS_CONFIG_NAME
+   default "sipeed-maix"
+
+config SYS_TEXT_BASE
+   default 0x8000
+
+config DEFAULT_DEVICE_TREE
+   default "k210-maix-bit"
+
+config NR_CPUS
+   default 2
+
+config NR_DRAM_BANKS
+   default 3
+
+config BOARD_SPECIFIC_OPTIONS
+   def_bool y
+   select GENERIC_RISCV
+   select RISCV_PRIV_1_9
+   imply SMP
+   imply DM_SERIAL
+   imply SIFIVE_SERIAL
+   imply SIFIVE_CLINT
+   imply POWER_DOMAIN
+   imply SIMPLE_PM_BUS
+   imply CLK_CCF
+   imply CLK_COMPOSITE_CCF

[PATCH v12 15/21] riscv: Add option to support RISC-V privileged spec 1.9

[Sean Anderson]

Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs.  Using the new CSR on an old processor causes an illegal
instruction exception.  This patch adds an option to use the old CSRs
instead of the new one.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v6:
- Reformat so chechpatch errors less

Changes in v5:
- Rename to 1.9 to reflect the spec as implemented by the k210

Changes in v4:
- Fixed CSRs not being defined properly (thanks bmeng)
- Added ifdefs for all changed CSRs (e.g. for VM)
- Also properly disable VM on boot

Changes in v3:
- Renamed from "riscv: Add option to disable writes to mcounteren"
- Added original functionality back for older priv specs.

Changes in v2:
- Moved forward in the patch series

 arch/riscv/Kconfig   | 10 +
 arch/riscv/cpu/cpu.c |  9 
 arch/riscv/include/asm/csr.h | 40 
 3 files changed, 59 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fb5fe5afff..a611f890a1 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -268,6 +268,16 @@ config XIP
 config SHOW_REGS
bool "Show registers on unhandled exception"
 
+config RISCV_PRIV_1_9
+   bool "Use version 1.9 of the RISC-V priviledged specification"
+   help
+ Older versions of the RISC-V priviledged specification had
+ separate counter enable CSRs for each privilege mode. Writing
+ to the unified mcounteren CSR on a processor implementing the
+ old specification will result in an illegal instruction
+ exception. In addition to counter CSR changes, the way virtual
+ memory is configured was also changed.
+
 config STACK_SIZE_SHIFT
int
default 14
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index d75a3f045a..bbd6c15352 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -91,11 +91,20 @@ int arch_cpu_init_dm(void)
 * Enable perf counters for cycle, time,
 * and instret counters only
 */
+#ifdef CONFIG_RISCV_PRIV_1_9
+   csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
+   csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
+#else
csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
+#endif
 
/* Disable paging */
if (supports_extension('s'))
+#ifdef CONFIG_RISCV_PRIV_1_9
+   csr_read_clear(CSR_MSTATUS, SR_VM);
+#else
csr_write(CSR_SATP, 0);
+#endif
}
 
 #ifdef CONFIG_SMP
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index d1520743a2..1a15089cae 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -15,7 +15,11 @@
 #define SR_SIE _AC(0x0002, UL) /* Supervisor Interrupt Enable */
 #define SR_SPIE_AC(0x0020, UL) /* Previous Supervisor IE */
 #define SR_SPP _AC(0x0100, UL) /* Previously Supervisor */
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define SR_PUM _AC(0x0004, UL) /* Protect User Memory Access */
+#else
 #define SR_SUM _AC(0x0004, UL) /* Supervisor User Memory Access */
+#endif
 
 #define SR_FS  _AC(0x6000, UL) /* Floating-point Status */
 #define SR_FS_OFF  _AC(0x, UL)
@@ -29,6 +33,22 @@
 #define SR_XS_CLEAN_AC(0x0001, UL)
 #define SR_XS_DIRTY_AC(0x00018000, UL)
 
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define SR_VM  _AC(0x1F00, UL) /* Virtualization Management */
+#define SR_VM_MODE_BARE_AC(0x, UL) /* No translation or 
protection */
+#define SR_VM_MODE_BB  _AC(0x0100, UL) /* Single base-and-bound */
+/* Separate instruction and data base-and-bound */
+#define SR_VM_MODE_BBID_AC(0x0200, UL)
+#ifndef CONFIG_64BIT
+#define SR_VM_MODE_32  _AC(0x0800, UL)
+#define SR_VM_MODE SR_VM_MODE_32
+#else
+#define SR_VM_MODE_39  _AC(0x0900, UL)
+#define SR_VM_MODE_48  _AC(0x0A00, UL)
+#define SR_VM_MODE SR_VM_MODE_39
+#endif
+#endif
+
 #ifndef CONFIG_64BIT
 #define SR_SD  _AC(0x8000, UL) /* FS/XS dirty */
 #else
@@ -36,6 +56,7 @@
 #endif
 
 /* SATP flags */
+#ifndef CONFIG_RISCV_PRIV_1_9
 #ifndef CONFIG_64BIT
 #define SATP_PPN   _AC(0x003F, UL)
 #define SATP_MODE_32   _AC(0x8000, UL)
@@ -45,6 +66,7 @@
 #define SATP_MODE_39   _AC(0x8000, UL)
 #define SATP_MODE  SATP_MODE_39
 #endif
+#endif
 
 /* SCAUSE */
 #define SCAUSE_IRQ_FLAG(_AC(1, UL) << (__riscv_xlen - 1))
@@ -88,17 +110,35 @@
 #define CSR_SCAUSE 0x142
 #define CSR_STVAL  0x143
 #define CSR_SIP0x144
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define CSR_SPTBR  0x180
+#else
 #define CSR_SATP   0x180
+#endif
 #define CSR_MSTATUS 

[PATCH v12 19/21] riscv: Add device tree for K210 and Sipeed Maix BitM

[Sean Anderson]

Where possible, I have tried to find compatible drivers based on the layout
of registers. However, many devices remain untested. All untested devices
have been left disabled, but some tentative properties (such as compatible
strings, and clocks, interrupts, and resets properties) have been added.

Signed-off-by: Sean Anderson 
---

Changes in v7:
- Move clocks node to be just before soc node, matching linux's tree
- Merge memory nodes into one node with different registers
- Add aliases for uclasses which use them
- Fix size of clint

Changes in v6:
- Remove spi, gpio, pinmux, wdt, and led bindings
- Use consistent capitalization for hex digits

Changes in v5:
- Add more compatible strings
- Add cache line size
- Document CPUs as rocket cores
- Flesh out the gpio devices
- Add ports for audio and video devices
- Add fpioa pinctrl support
- Configure pins for MMC on SPI1
- Enable MMC
- Fix a couple uart properties (Thanks laanwj)
- Reorder ram now that relocation is handled with CONFIG_SYS defines
- Enable WDT
- Add pinctrl properties
- Add gpio support
- Add led support
- Add assorted AV bindings
- Add compatible strings for ram
- Use GPIO-based CS for MMC
- Limit SPI flash to 50 MHz

Changes in v4:
- Set regs sizes to full address range
- Remove clock-frequency property from cpus
- Add spi-max-frequency to spi devices from documentation
- Add more compatible strings for each device
- Add AI ram as a separate memory bank. Its clock is disabled on boot, and
  it cannot be accessed
- Reorder memory banks so u-boot relocates higher, leaving more room to
  load boot images
- Add designware ssi CTRL0 field shifts to spi devices
- Don't enable the MMC slot
- Update copyright
- Lint

Changes in v3:
- Move this patch to the end of the series
- Add a max frequency for spi3
- Remov unused compatible strings from spi-flash@0
- Add s and u to isa string
- Fix mmu-type
- Remove cache-line size since it is unused (in u-boot) and undocumented
  (upstream)
- Add timer interrupts to clint0
- Round up various registers
- Add riscv,max-priority to plic
- Add apb* busses, since they have clocks which need to be enabled to
  access their devices
- Change uart compatible strings to "snps,dw-apb-uart", since that appears
  to match their registers
- Add compatible string for wdt*
- Add system reset device under sysctl
- Add reset device under sysctl

Changes in v2:
- Model changed to "Sipeed Maix Bit" to match file name
- Value of stdout-path fixed
- SD card slot compatible changed to "mmc-spi-slot"
- "jedec,spi-nor" added to spi flash compatible list
- Aliases for spi busses added
- timebase-frequency divided by 50 to match timer speed
- cpu-frequency renamed to clock-frequency
- CPUX_intc restyled to cpuX_intc
- "kendryte,k210-soc" added to soc compatible list for future-proofing
- PLIC handle renamed to plic0 from pic0
- K210_RST_SOC removed from sysrst, due to not being located in the reset
  register
- K210_RST_* numbers changed to match their bit offset within the reset
  register
- gpio_controller restyled to gpio-controller
- Added a second clock to the dma binding to match what the driver expects
- Changed "snps,designware-spi" compatible string to "snps,dw-apb-ssi" to
  match the correct driver
- Added a name to the spi clocks
- Added reg-io-width property to spi bindings
- Assigned a default parent to K210_CLK_SPI3
- Removed assigned clocks for ACLK and PLLs
- Removed u-boot,dm-pre-reloc bindings

 arch/riscv/dts/Makefile |   1 +
 arch/riscv/dts/k210-maix-bit.dts|  47 ++
 arch/riscv/dts/k210.dtsi| 594 
 include/dt-bindings/reset/k210-sysctl.h |  38 ++
 4 files changed, 680 insertions(+)
 create mode 100644 arch/riscv/dts/k210-maix-bit.dts
 create mode 100644 arch/riscv/dts/k210.dtsi
 create mode 100644 include/dt-bindings/reset/k210-sysctl.h

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 4f30e6936f..3a6f96c67d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
 
 dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
new file mode 100644
index 00..5b32c5fd5f
--- /dev/null
+++ b/arch/riscv/dts/k210-maix-bit.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson 
+ */
+
+/dts-v1/;
+
+#include "k210.dtsi"
+
+#include 
+
+/ {
+   model = "Sipeed Maix Bit 2.0";
+   compatible = "sipeed,maix-bitm", "sipeed,maix-bit", "kendryte,k210";
+
+   chosen {
+   stdout-path = "serial0:115200";
+   };
+
+   sound {
+   compatible = "simple-audio-card";
+   simple-audio-card,format = "i2s";
+   status = "disabled";
+
+   simple-audio-card,cpu {
+  

[PATCH v12 17/21] riscv: Try to get cpu frequency from a "clocks" node if it exists

[Sean Anderson]

Instead of always using the "clock-frequency" property to determine cpu
frequency, try using a clock in "clocks" if it exists. This patch also
fixes a bug where there could be spurious higher frequencies if sizeof(u32)
!= sizeof(ulong).

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---
This patch was previously sumbitted on its own as
https://patchwork.ozlabs.org/patch/1232420/

This patch is the combination of the patches
https://patchwork.ozlabs.org/patch/1223933/
https://patchwork.ozlabs.org/patch/1224957/
"riscv: Fix incorrect cpu frequency on RV64"
"riscv: Try to get cpu frequency from device tree"

Changes in v5:
- Include linux/err.h explicitly
- Reword commit message

Changes in v4:
- New

 drivers/cpu/riscv_cpu.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index cb04f5638d..2d44d1c17b 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2018, Bin Meng 
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -11,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -29,9 +31,24 @@ static int riscv_cpu_get_desc(struct udevice *dev, char 
*buf, int size)
 
 static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
 {
+   int ret;
+   struct clk clk;
const char *mmu;
 
-   dev_read_u32(dev, "clock-frequency", (u32 *)>cpu_freq);
+   /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */
+   info->cpu_freq = 0;
+
+   /* First try getting the frequency from the assigned clock */
+   ret = clk_get_by_index(dev, 0, );
+   if (!ret) {
+   ret = clk_get_rate();
+   if (!IS_ERR_VALUE(ret))
+   info->cpu_freq = ret;
+   clk_free();
+   }
+
+   if (!info->cpu_freq)
+   dev_read_u32(dev, "clock-frequency", (u32 *)>cpu_freq);
 
mmu = dev_read_string(dev, "mmu-type");
if (!mmu)
-- 
2.26.2

[PATCH v12 18/21] riscv: Enable cpu clock if it is present

[Sean Anderson]

The cpu clock is probably already enabled if we are executing code (though
we could be executing from a different core). This patch prevents the cpu
clock or its parents from being disabled.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---
This patch was previously submitted on its own as
https://patchwork.ozlabs.org/patch/1232420/

Changes in v4:
- New

 drivers/cpu/riscv_cpu.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 2d44d1c17b..76b0489d2a 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2018, Bin Meng 
+ * Copyright (C) 2020, Sean Anderson 
  */
 
 #include 
@@ -119,6 +120,24 @@ static int riscv_cpu_bind(struct udevice *dev)
return 0;
 }
 
+static int riscv_cpu_probe(struct udevice *dev)
+{
+   int ret = 0;
+   struct clk clk;
+
+   /* Get a clock if it exists */
+   ret = clk_get_by_index(dev, 0, );
+   if (ret)
+   return 0;
+
+   ret = clk_enable();
+   clk_free();
+   if (ret == -ENOSYS || ret == -ENOTSUPP)
+   return 0;
+   else
+   return ret;
+}
+
 static const struct cpu_ops riscv_cpu_ops = {
.get_desc   = riscv_cpu_get_desc,
.get_info   = riscv_cpu_get_info,
@@ -135,6 +154,7 @@ U_BOOT_DRIVER(riscv_cpu) = {
.id = UCLASS_CPU,
.of_match = riscv_cpu_ids,
.bind = riscv_cpu_bind,
+   .probe = riscv_cpu_probe,
.ops = _cpu_ops,
.flags = DM_FLAG_PRE_RELOC,
 };
-- 
2.26.2

[PATCH v12 20/21] doc: riscv: Add documentation for Sipeed Maix Bit

[Sean Anderson]

This patch adds documentation for the Sipeed Maix bit, and more generally
for the Kendryte K210 processor.

Signed-off-by: Sean Anderson 
---

Changes in v9:
- Mark dts code block as "none" explicitly
Changes in v7:
- Split off into its own patch
- Fix size of clint

 doc/board/index.rst|   1 +
 doc/board/sipeed/index.rst |   9 ++
 doc/board/sipeed/maix.rst  | 298 +
 3 files changed, 308 insertions(+)
 create mode 100644 doc/board/sipeed/index.rst
 create mode 100644 doc/board/sipeed/maix.rst

diff --git a/doc/board/index.rst b/doc/board/index.rst
index 01b233f737..126dcc2438 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -17,6 +17,7 @@ Board-specific doc
renesas/index
rockchip/index
sifive/index
+   sipeed/index
st/index
toradex/index
xilinx/index
diff --git a/doc/board/sipeed/index.rst b/doc/board/sipeed/index.rst
new file mode 100644
index 00..3518e2d8f4
--- /dev/null
+++ b/doc/board/sipeed/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sipeed
+==
+
+.. toctree::
+   :maxdepth: 2
+
+   maix
diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst
new file mode 100644
index 00..06e0008b9f
--- /dev/null
+++ b/doc/board/sipeed/maix.rst
@@ -0,0 +1,298 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020 Sean Anderson 
+
+Maix Bit
+
+
+Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor,
+a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate
+neural network processing and other "ai" tasks. This includes a "KPU" neural
+network processor, an audio processor supporting beamforming reception, and a
+digital video port supporting capture and output at VGA resolution. Other
+peripherals include 8M of SRAM (accessible with and without caching); 
remappable
+pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller;
+and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi 
flash;
+on-board usb-serial bridges; ports for cameras, displays, and sd cards; and
+ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but
+the boards are fairly similar.
+
+Documentation for Maix boards is available from
+`Sipeed's website `_.
+Documentation for the Kendryte K210 is available from
+`Kendryte's website `_. However, hardware
+details are rather lacking, so most technical reference has been taken from the
+`standalone sdk `_.
+
+Build and boot steps
+
+
+To build u-boot, run
+
+.. code-block:: none
+
+make sipeed_maix_bitm_defconfig
+make CROSS_COMPILE=
+
+To flash u-boot to a maix bit, run
+
+.. code-block:: none
+
+kflash -tp /dev/ -B bit_mic u-boot-dtb.bin
+
+Boot output should look like the following:
+
+.. code-block:: none
+
+U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
+
+DRAM:  8 MiB
+In:serial@3800
+Out:   serial@3800
+Err:   serial@3800
+=>
+
+Loading Images
+^^
+
+To load a kernel, transfer it over serial.
+
+.. code-block:: none
+
+=> loady 8000 150
+## Switch baudrate to 150 bps and press ENTER ...
+
+*** baud: 150
+
+*** baud: 150 ***
+## Ready for binary (ymodem) download to 0x8000 at 150 bps...
+C
+*** file: loader.bin
+$ sz -vv loader.bin
+Sending: loader.bin
+Bytes Sent:2478208   BPS:72937
+Sending:
+Ymodem sectors/kbytes sent:   0/ 0k
+Transfer complete
+
+*** exit status: 0 ***
+## Total Size  = 0x0025d052 = 2478162 Bytes
+## Switch baudrate to 115200 bps and press ESC ...
+
+*** baud: 115200
+
+*** baud: 115200 ***
+=>
+
+Running Programs
+
+
+Binaries
+
+
+To run a bare binary, use the ``go`` command:
+
+.. code-block:: none
+
+=> loady
+## Ready for binary (ymodem) download to 0x8000 at 115200 bps...
+C
+*** file: ./examples/standalone/hello_world.bin
+$ sz -vv ./examples/standalone/hello_world.bin
+Sending: hello_world.bin
+Bytes Sent:   4864   BPS:649
+Sending:
+Ymodem sectors/kbytes sent:   0/ 0k
+Transfer complete
+
+*** exit status: 0 ***
+(CAN) packets, 5 retries
+## Total Size  = 0x12f8 = 4856 Bytes
+=> go 8000
+## Starting application at 0x8000 ...
+Example expects ABI version 9
+Actual U-Boot ABI version 9
+Hello World
+argc = 1
+argv[0] = "8000"
+argv[1] = ""
+Hit any key to exit ...
+
+Legacy Images
+"
+
+To run legacy images, use the ``bootm`` command:
+
+.. code-block:: none
+
+$ tools/mkimage -A riscv -O u-boot -T standalone -C none -a 8000 -e 
8000 -d examples/standalone/hello_world.bin hello_world.img
+Image Name:
+Created:  Thu 

[PATCH v12 16/21] riscv: Allow use of reset drivers

[Sean Anderson]

Currently, one cannot use a reset driver on RISC-V. Follow the MIPS
example, and disable the default reset handler when the sysreset driver is
enabled.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v3:
- New

 arch/riscv/lib/reset.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
index 8779c619cc..6008bbe78e 100644
--- a/arch/riscv/lib/reset.c
+++ b/arch/riscv/lib/reset.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 
+#ifndef CONFIG_SYSRESET
 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
printf("resetting ...\n");
@@ -16,3 +17,4 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char 
*const argv[])
 
return 0;
 }
+#endif
-- 
2.26.2

[PATCH v12 14/21] riscv: Clean up IPI initialization code

[Sean Anderson]

The previous IPI code initialized the device whenever the first call was
made to a riscv_*_ipi function. This made it difficult to determine when
the IPI device was initialized. This patch introduces a new function
riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is
called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions
should be called.

Signed-off-by: Sean Anderson 
Reviewed-by: Rick Chen 
---

Changes in v12:
- Remove sanity check as requested

Changes in v11:
- Initialize IPI when used by SPL
Changes in v9:
- Fix type of ret variable in riscv_ipi_init
Changes in v7:
- Split IPI clearing off into its own patch

Changes in v6:
- Fix some formatting
- Clear IPIs before enabling interrupts instead of using a ipi_ready flag
- Only print messages on error in smp code

Changes in v5:
- New

 arch/riscv/cpu/cpu.c  |  6 +
 arch/riscv/include/asm/smp.h  | 43 ++
 arch/riscv/lib/andes_plic.c   | 34 +---
 arch/riscv/lib/sbi_ipi.c  |  5 
 arch/riscv/lib/sifive_clint.c | 33 ---
 arch/riscv/lib/smp.c  | 50 +--
 common/spl/spl_opensbi.c  |  5 
 7 files changed, 89 insertions(+), 87 deletions(-)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 5804aa8e73..d75a3f045a 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -98,6 +98,12 @@ int arch_cpu_init_dm(void)
csr_write(CSR_SATP, 0);
}
 
+#ifdef CONFIG_SMP
+   ret = riscv_init_ipi();
+   if (ret)
+   return ret;
+#endif
+
return 0;
 }
 
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 74de92ed13..1b428856b2 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -51,4 +51,47 @@ void handle_ipi(ulong hart);
  */
 int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
 
+/**
+ * riscv_init_ipi() - Initialize inter-process interrupt (IPI) driver
+ *
+ * Platform code must provide this function. This function is called once after
+ * the cpu driver is initialized. No other riscv_*_ipi() calls will be made
+ * before this function is called.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int riscv_init_ipi(void);
+
+/**
+ * riscv_send_ipi() - Send inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of receiving hart
+ * @return 0 if OK, -ve on error
+ */
+int riscv_send_ipi(int hart);
+
+/**
+ * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be cleared
+ * @return 0 if OK, -ve on error
+ */
+int riscv_clear_ipi(int hart);
+
+/**
+ * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be checked
+ * @pending: Pointer to variable with result of the check,
+ *   1 if IPI is pending, 0 otherwise
+ * @return 0 if OK, -ve on error
+ */
+int riscv_get_ipi(int hart, int *pending);
+
 #endif
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 20529ab3eb..5cf29df670 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -30,20 +30,6 @@
 #define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))
 
 DECLARE_GLOBAL_DATA_PTR;
-static int init_plic(void);
-
-#define PLIC_BASE_GET(void)\
-   do {\
-   long *ret;  \
-   \
-   if (!gd->arch.plic) {   \
-   ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
-   if (IS_ERR(ret))\
-   return PTR_ERR(ret);\
-   gd->arch.plic = ret;\
-   init_plic();\
-   }   \
-   } while (0)
 
 static int enable_ipi(int hart)
 {
@@ -93,13 +79,21 @@ static int init_plic(void)
return -ENODEV;
 }
 
+int riscv_init_ipi(void)
+{
+   long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
+
+   if (IS_ERR(ret))
+   return PTR_ERR(ret);
+   gd->arch.plic = ret;
+
+   return init_plic();
+}
+
 int riscv_send_ipi(int hart)
 {
-   unsigned int ipi;
+   unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
 
-   PLIC_BASE_GET();
-
-   ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
 
@@ -110,8 +104,6 @@ int 

[PATCH v12 10/21] reset: Add generic reset driver

[Sean Anderson]

This patch adds a generic reset driver. It is designed to be useful when
one has a register in a regmap which contains bits that reset other
devices. I thought this seemed like a very generic use, so here is a
generic driver. The overall structure has been modeled on the syscon-reboot
driver.

Signed-off-by: Sean Anderson 
Reviewed-by: Simon Glass 
---

Changes in v5:
- Reorder includes
- Include linux/err.h explicitly

Changes in v4:
- Added basic test
- Fix incorrect usage of regmap_update_bits

Changes in v3:
- New

 arch/sandbox/dts/test.dts | 15 
 configs/sandbox_defconfig |  2 +
 .../reset/syscon-reset.txt| 36 +
 drivers/reset/Kconfig |  5 ++
 drivers/reset/Makefile|  1 +
 drivers/reset/reset-syscon.c  | 80 +++
 test/dm/Makefile  |  1 +
 test/dm/syscon-reset.c| 58 ++
 8 files changed, 198 insertions(+)
 create mode 100644 doc/device-tree-bindings/reset/syscon-reset.txt
 create mode 100644 drivers/reset/reset-syscon.c
 create mode 100644 test/dm/syscon-reset.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index d08396aff6..f5b685f7fe 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1035,6 +1035,21 @@
clocks = <_sandbox 4>;
power-domains = < 1>;
};
+
+   resetc2: syscon-reset {
+   compatible = "syscon-reset";
+   #reset-cells = <1>;
+   regmap = <>;
+   offset = <1>;
+   mask = <0x27FF>;
+   assert-high = <0>;
+   };
+
+   syscon-reset-test {
+   compatible = "sandbox,misc_sandbox";
+   resets = < 15>, < 30>, < 60>;
+   reset-names = "valid", "no_mask", "out_of_range";
+   };
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 722459a2a5..30401834ad 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -196,6 +196,8 @@ CONFIG_REMOTEPROC_SANDBOX=y
 CONFIG_DM_RESET=y
 CONFIG_SANDBOX_RESET=y
 CONFIG_DM_RNG=y
+CONFIG_RNG_SANDBOX=y
+CONFIG_RESET_SYSCON=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_RV8803=y
 CONFIG_DEBUG_UART_SANDBOX=y
diff --git a/doc/device-tree-bindings/reset/syscon-reset.txt 
b/doc/device-tree-bindings/reset/syscon-reset.txt
new file mode 100644
index 00..f136b3d225
--- /dev/null
+++ b/doc/device-tree-bindings/reset/syscon-reset.txt
@@ -0,0 +1,36 @@
+Generic SYSCON mapped register reset driver
+
+This is a generic reset driver using syscon to map the reset register.
+The reset is generally performed with a write to the reset register
+defined by the register map pointed by syscon reference plus the offset and
+shifted by the reset specifier/
+
+To assert a reset on some device, the equivalent of the following operation is
+performed, where reset_id is the reset specifier from the device's resets
+property.
+
+   if (BIT(reset_id) & mask)
+   regmap[offset][reset_id] = assert-high;
+
+Required properties:
+- compatible: should contain "syscon-reset"
+- #reset-cells: must be 1
+- regmap: this is phandle to the register map node
+- offset: offset in the register map for the reboot register (in bytes)
+
+Optional properties:
+- mask: accept only the reset specifiers defined by the mask (32 bit)
+- assert-high: Bit to write when asserting a reset. Defaults to 1.
+
+Default will be little endian mode, 32 bit access only.
+
+Example:
+
+   reset-controller {
+   compatible = "syscon-reset";
+   #reset-cells = <1>;
+   regmap = <>;
+   offset = <0x20>;
+   mask = <0x27FF>;
+   assert-high = <0>;
+   };
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 88d3be1593..58ba0c686e 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -148,4 +148,9 @@ config RESET_IMX7
help
  Support for reset controller on i.MX7/8 SoCs.
 
+config RESET_SYSCON
+   bool "Enable generic syscon reset driver support"
+   depends on DM_RESET
+   help
+ Support generic syscon mapped register reset devices.
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 0a044d5d8c..433f1eca54 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
diff --git a/drivers/reset/reset-syscon.c b/drivers/reset/reset-syscon.c
new file mode 100644
index 00..34dfe0bab6
--- /dev/null
+++ b/drivers/reset/reset-syscon.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Sean Anderson

[PATCH v12 12/21] riscv: Add headers for asm/global_data.h

[Sean Anderson]

This header depended on bd_t and ulong, but did not include the appropriate
headers.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v4:
- Include compiler.h not linux/compiler.h

 arch/riscv/include/asm/global_data.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index 6c50149218..2eb14815bc 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -11,6 +11,8 @@
 #define __ASM_GBL_DATA_H
 
 #include 
+#include 
+#include 
 
 /* Architecture-specific global data */
 struct arch_global_data {
-- 
2.26.2

[PATCH v12 13/21] riscv: Clear pending interrupts before enabling IPIs

[Sean Anderson]

On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.

Signed-off-by: Sean Anderson 
Reviewed-by: Rick Chen 
---

Changes in v7:
- Split of into its own patch

 arch/riscv/cpu/start.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 5f1c220e0c..f408e41ab9 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -65,6 +65,8 @@ _start:
 #else
li  t0, SIE_SSIE
 #endif
+   /* Clear any pending IPIs */
+   csrcMODE_PREFIX(ip), t0
csrsMODE_PREFIX(ie), t0
 #endif
 
-- 
2.26.2

[PATCH v12 11/21] lib: Always set errno in hcreate_r

[Sean Anderson]

This could give a confusing error message if it failed and didn't set
errno.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
---

Changes in v5:
- New

 lib/hashtable.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/lib/hashtable.c b/lib/hashtable.c
index b96dbe19be..7b6781bc35 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -110,8 +110,10 @@ int hcreate_r(size_t nel, struct hsearch_data *htab)
}
 
/* There is still another table active. Return with error. */
-   if (htab->table != NULL)
+   if (htab->table != NULL) {
+   __set_errno(EINVAL);
return 0;
+   }
 
/* Change nel to the first prime number not smaller as nel. */
nel |= 1;   /* make odd */
@@ -124,8 +126,10 @@ int hcreate_r(size_t nel, struct hsearch_data *htab)
/* allocate memory and zero out */
htab->table = (struct env_entry_node *)calloc(htab->size + 1,
sizeof(struct env_entry_node));
-   if (htab->table == NULL)
+   if (htab->table == NULL) {
+   __set_errno(ENOMEM);
return 0;
+   }
 
/* everything went alright */
return 1;
-- 
2.26.2

[PATCH v12 08/21] dm: Add support for simple-pm-bus

[Sean Anderson]

This type of bus is used in Linux to designate buses which have power
domains and/or clocks which need to be enabled before their child devices
can be used. Because power domains are automatically enabled before probing
in U-Boot, we just need to enable any clocks present.

Signed-off-by: Sean Anderson 
Reviewed-by: Simon Glass 
---

Changes in v10:
- Remove const qualifiers from simple_pm_bus_* functions
Changes in v5:
- Reorder includes (simple pm)

Changes in v4:
- Split the bus off into its own driver
- Add test
- Fix line spacing in Kconfig
- Lint

Changes in v3:
- New

 arch/sandbox/dts/test.dts |  6 ++
 arch/sandbox/include/asm/clk.h|  1 +
 configs/sandbox_defconfig |  1 +
 .../bus/simple-pm-bus.txt | 44 +++
 drivers/core/Kconfig  |  7 +++
 drivers/core/Makefile |  1 +
 drivers/core/simple-pm-bus.c  | 56 +++
 test/dm/Makefile  |  1 +
 test/dm/simple-pm-bus.c   | 45 +++
 9 files changed, 162 insertions(+)
 create mode 100644 doc/device-tree-bindings/bus/simple-pm-bus.txt
 create mode 100644 drivers/core/simple-pm-bus.c
 create mode 100644 test/dm/simple-pm-bus.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 5ce5e28476..d08396aff6 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1029,6 +1029,12 @@
mdio: mdio-test {
compatible = "sandbox,mdio";
};
+
+   pm-bus-test {
+   compatible = "simple-pm-bus";
+   clocks = <_sandbox 4>;
+   power-domains = < 1>;
+   };
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
index 1573e4a134..c184c4bffc 100644
--- a/arch/sandbox/include/asm/clk.h
+++ b/arch/sandbox/include/asm/clk.h
@@ -21,6 +21,7 @@ enum sandbox_clk_id {
SANDBOX_CLK_ID_I2C,
SANDBOX_CLK_ID_UART1,
SANDBOX_CLK_ID_UART2,
+   SANDBOX_CLK_ID_BUS,
 
SANDBOX_CLK_ID_COUNT,
 };
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 9445d78118..722459a2a5 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -96,6 +96,7 @@ CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
+CONFIG_SIMPLE_PM_BUS=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
 CONFIG_AXI=y
diff --git a/doc/device-tree-bindings/bus/simple-pm-bus.txt 
b/doc/device-tree-bindings/bus/simple-pm-bus.txt
new file mode 100644
index 00..6f15037131
--- /dev/null
+++ b/doc/device-tree-bindings/bus/simple-pm-bus.txt
@@ -0,0 +1,44 @@
+Simple Power-Managed Bus
+
+
+A Simple Power-Managed Bus is a transparent bus that doesn't need a real
+driver, as it's typically initialized by the boot loader.
+
+However, its bus controller is part of a PM domain, or under the control of a
+functional clock.  Hence, the bus controller's PM domain and/or clock must be
+enabled for child devices connected to the bus (either on-SoC or externally)
+to function.
+
+While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
+in the Devicetree Specification, it is not an extension of "simple-bus".
+
+
+Required properties:
+  - compatible: Must contain at least "simple-pm-bus".
+   Must not contain "simple-bus".
+   It's recommended to let this be preceded by one or more
+   vendor-specific compatible values.
+  - #address-cells, #size-cells, ranges: Must describe the mapping between
+   parent address and child address spaces.
+
+Optional platform-specific properties for clock or PM domain control (at least
+one of them is required):
+  - clocks: Must contain a reference to the functional clock(s),
+  - power-domains: Must contain a reference to the PM domain.
+Please refer to the binding documentation for the clock and/or PM domain
+providers for more details.
+
+
+Example:
+
+   bsc: bus@fec1 {
+   compatible = "renesas,bsc-sh73a0", "renesas,bsc",
+"simple-pm-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0 0x2000>;
+   reg = <0xfec1 0x400>;
+   interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <_clk>;
+   power-domains = <_a4s>;
+   };
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index a3b0399342..a594899f37 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -195,6 +195,13 @@ config SPL_SIMPLE_BUS
  Supports the 'simple-bus' driver, which is used on some systems
  in SPL.
 
+config SIMPLE_PM_BUS
+   bool "Support simple-pm-bus driver"
+   depends on DM && OF_CONTROL && CLK && POWER_DOMAIN
+   help
+ Supports the 'simple-pm-bus' driver, which is used for 

[PATCH v12 05/21] clk: Add K210 pll support

[Sean Anderson]

This pll code is primarily based on the code from the kendryte standalone
sdk in lib/drivers/sysctl.c. k210_pll_calc_config is roughly analogous to
the algorithm used to set the pll frequency, but it has been completely
rewritten to be fixed-point based.

Signed-off-by: Sean Anderson 
CC: Lukasz Majewski 
---

Changes in v8:
- Rename k210_pll_params to k210_pll_config to avoid a name conflict with the
  rest of the clock code
Changes in v6:
- Reformat code to reduce checkpatch errors

Changes in v5:
- Add function to register from a struct

Changes in v4:
- Rename the reference clock to "divider clock", and input clock to "reference
  clock" to match the upstream documentation.
- Add a test for calc_params. This currently resides in test/dm, but perhaps it
  should be moved to its own directory.
- Update MAINTAINERS
- Update copyright
- Lint

Changes in v3:
- Add an option to not include support for setting the pll rate. This saves
  around 1K in the final executable.
- Remove udelays to suppress warnings
- Bypass PLL after enabling, instead of before
- Check if the PLL is enabled already before doing a reset
- Fix bug with locked mask

Changes in v2:
- Rename driver to "k210_clk_pll"
- Add additional in-line documentation on algorithm and PLLs
- Restrict the range of internal VCO and reference frequencies
- Don't load driver before relocation
- Remove spurious references to mach-k210

 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   1 +
 drivers/clk/kendryte/Kconfig  |  12 +
 drivers/clk/kendryte/Makefile |   1 +
 drivers/clk/kendryte/pll.c| 601 ++
 include/kendryte/pll.h|  57 
 include/test/export.h |  16 +
 test/dm/Makefile  |   1 +
 test/dm/k210_pll.c|  96 ++
 9 files changed, 786 insertions(+)
 create mode 100644 drivers/clk/kendryte/Kconfig
 create mode 100644 drivers/clk/kendryte/Makefile
 create mode 100644 drivers/clk/kendryte/pll.c
 create mode 100644 include/kendryte/pll.h
 create mode 100644 include/test/export.h
 create mode 100644 test/dm/k210_pll.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 8b8b71..82cb1874e1 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -156,6 +156,7 @@ source "drivers/clk/analogbits/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/exynos/Kconfig"
 source "drivers/clk/imx/Kconfig"
+source "drivers/clk/kendryte/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/owl/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e01783391d..d911954581 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
 obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
+obj-$(CONFIG_CLK_K210) += kendryte/
 obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
 obj-$(CONFIG_CLK_OWL) += owl/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig
new file mode 100644
index 00..7b69c8afaf
--- /dev/null
+++ b/drivers/clk/kendryte/Kconfig
@@ -0,0 +1,12 @@
+config CLK_K210
+   bool "Clock support for Kendryte K210"
+   depends on CLK && CLK_CCF
+   help
+ This enables support clock driver for Kendryte K210 platforms.
+
+config CLK_K210_SET_RATE
+   bool "Enable setting the Kendryte K210 PLL rate"
+   depends on CLK_K210
+   help
+ Add functionality to calculate new rates for K210 PLLs. Enabling this
+ feature adds around 1K to U-Boot's final size.
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
new file mode 100644
index 00..c56d93ea1c
--- /dev/null
+++ b/drivers/clk/kendryte/Makefile
@@ -0,0 +1 @@
+obj-y += pll.o
diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
new file mode 100644
index 00..2c5d5b8857
--- /dev/null
+++ b/drivers/clk/kendryte/pll.c
@@ -0,0 +1,601 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson 
+ */
+#include 
+
+#define LOG_CATEGORY UCLASS_CLK
+#include 
+/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLK_K210_PLL "k210_clk_pll"
+
+#ifdef CONFIG_CLK_K210_SET_RATE
+static int k210_pll_enable(struct clk *clk);
+static int k210_pll_disable(struct clk *clk);
+
+/*
+ * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
+ * General-Purpose PLL. The logical layout of the PLL with internal feedback is
+ * approximately the following:
+ *
+ *  +---+
+ *  |reference clock|
+ *  +---+
+ *  |
+ *  v
+ *+--+
+ *|/r|
+ *+--+
+ *  |
+ *  v
+ *   +-+
+ *   |divided clock|
+ *   +-+
+ *  |
+ *

[PATCH v12 07/21] clk: Add K210 clock support

[Sean Anderson]

Due to the large number of clocks, I decided to use the CCF. The overall
structure is modeled after the imx code. Clocks parameters are stored in
several arrays, and are then instantiated at run-time. There are some
translation macros (FOOIFY()) which allow for more dense packing.

Signed-off-by: Sean Anderson 
CC: Lukasz Majewski 
---

Changes in v8:
- Rework code to not need a new CCF api
- Add some documentation

Changes in v7:
- Add numbering to some sysctl registers

Changes in v6:
- Reformat code so checkpatch generates fewer warnings
- Give "fictional" clocks their own ids
- Rename sysctl CLK_FREQ register to UART_BAUD to better reflect its
  semantics

Changes in v5:
- Don't unmap priv->reg
- Remove comment on APB clocks since it has been clarified by Kendryte
- Add i2s mclks
- Reorder clock ids to be continuous
- Rewrite to statically allocate all clocks. This has helped find several
  bugs (since it is easy to see when a clock has the wrong register).
- Fix ACLK sometimes having the wrong parent
- Fix SPI3 having the wrong divider
- Prevent being probed multiple times on failure

Changes in v4:
- Reparent aclk before configuring pll0
- Update copyright
- Lint

Changes in v3:
- Removed sysctl struct, replacing it with defines. This is to have the
  same interface to sysctl from C as from the device tree.
- Fixed clocks having the same id
- Fixed clocks not using the correct register/bits
- Aligned the defines in headers

Changes in v2:
- Add clk.o to obj-y
- Don't probe before relocation

 MAINTAINERS   |   7 +
 .../mfd/kendryte,k210-sysctl.txt  |  33 +
 drivers/clk/kendryte/Kconfig  |   2 +-
 drivers/clk/kendryte/Makefile |   2 +-
 drivers/clk/kendryte/clk.c| 663 ++
 include/dt-bindings/clock/k210-sysctl.h   |  59 ++
 include/dt-bindings/mfd/k210-sysctl.h |  38 +
 include/kendryte/clk.h|  35 +
 8 files changed, 837 insertions(+), 2 deletions(-)
 create mode 100644 doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
 create mode 100644 drivers/clk/kendryte/clk.c
 create mode 100644 include/dt-bindings/clock/k210-sysctl.h
 create mode 100644 include/dt-bindings/mfd/k210-sysctl.h
 create mode 100644 include/kendryte/clk.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 8add9d4c2a..d221f83535 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -867,6 +867,13 @@ F: arch/riscv/
 F: cmd/riscv/
 F: tools/prelink-riscv.c
 
+RISC-V KENDRYTE
+M: Sean Anderson 
+S: Maintained
+F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
+F: drivers/clk/kendryte/
+F: include/kendryte/
+
 RNG
 M: Sughosh Ganu 
 R: Heinrich Schuchardt 
diff --git a/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt 
b/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
new file mode 100644
index 00..5b24abcb62
--- /dev/null
+++ b/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
@@ -0,0 +1,33 @@
+Kendryte K210 Sysctl
+
+This binding describes the K210 sysctl device, which contains many 
miscellaneous
+registers controlling system functionality. This node is a register map and can
+be reference by other bindings which need a phandle to the K210 sysctl regmap.
+
+Required properties:
+- compatible: should be
+   "kendryte,k210-sysctl", "syscon", "simple-mfd"
+- reg: address and length of the sysctl registers
+- reg-io-width: must be <4>
+
+Clock sub-node
+
+This node is a binding for the clock tree driver
+
+Required properties:
+- compatible: should be "kendryte,k210-clk"
+- clocks: phandle to the "in0" external oscillator
+- #clock-cells: must be <1>
+
+Example:
+sysctl: syscon@5044 {
+   compatible = "kendryte,k210-sysctl", "syscon", "simple-mfd";
+   reg = <0x5044 0x100>;
+   reg-io-width = <4>;
+
+   sysclk: clock-controller {
+   compatible = "kendryte,k210-clk";
+   clocks = <>;
+   #clock-cells = <1>;
+   };
+};
diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig
index 7b69c8afaf..073fca0781 100644
--- a/drivers/clk/kendryte/Kconfig
+++ b/drivers/clk/kendryte/Kconfig
@@ -1,6 +1,6 @@
 config CLK_K210
bool "Clock support for Kendryte K210"
-   depends on CLK && CLK_CCF
+   depends on CLK && CLK_CCF && CLK_COMPOSITE_CCF
help
  This enables support clock driver for Kendryte K210 platforms.
 
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index 47f682fce3..6fb68253ae 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += bypass.o pll.o
+obj-y += bypass.o clk.o pll.o
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
new file mode 100644
index 00..981b3b7699
--- /dev/null
+++ b/drivers/clk/kendryte/clk.c
@@ -0,0 +1,663 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson 
+ */
+#include 
+

[PATCH v12 09/21] dm: Fix error handling for dev_read_addr_ptr

[Sean Anderson]

dev_read_addr_ptr had different semantics depending on whether OF_LIVE was
enabled. This patch converts both implementations to return NULL on error,
and converts all call sites which check for FDT_ADDR_T_NONE to check for
NULL instead. This patch also removes the call to map_physmem, since we
have dev_remap_addr* for those semantics.

Signed-off-by: Sean Anderson 
Reviewed-by: Bin Meng 
Reviewed-by: Simon Glass 
---

Changes in v10:
- Explicitly cast fdt_addr_t to uintptr_t before casting to void *
Changes in v5:
- New

 drivers/clk/imx/clk-imx8mp.c  | 2 +-
 drivers/core/read.c   | 2 +-
 drivers/pinctrl/broadcom/pinctrl-bcm283x.c| 2 +-
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 2 +-
 include/dm/read.h | 4 +++-
 5 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 3d7aebb8e5..124138cf51 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -282,7 +282,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", 
"sys_pll2_out", 1, 1));
 
base = dev_read_addr_ptr(dev);
-   if (base == (void *)FDT_ADDR_T_NONE)
+   if (!base)
return -EINVAL;
 
clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 
24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 3d421f7a69..24f324eac2 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -167,7 +167,7 @@ void *dev_read_addr_ptr(const struct udevice *dev)
 {
fdt_addr_t addr = dev_read_addr(dev);
 
-   return (addr == FDT_ADDR_T_NONE) ? NULL : map_sysmem(addr, 0);
+   return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
 }
 
 void *dev_remap_addr(const struct udevice *dev)
diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c 
b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
index f44af6cf9a..c22d534da9 100644
--- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
+++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
@@ -117,7 +117,7 @@ int bcm283x_pinctl_probe(struct udevice *dev)
}
 
priv->base_reg = dev_read_addr_ptr(dev);
-   if (priv->base_reg == (void *)FDT_ADDR_T_NONE) {
+   if (!priv->base_reg) {
debug("%s: Failed to get base address\n", __func__);
return -EINVAL;
}
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c 
b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 5fdc150295..e8187a3780 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -631,7 +631,7 @@ int mtk_pinctrl_common_probe(struct udevice *dev,
int ret;
 
priv->base = dev_read_addr_ptr(dev);
-   if (priv->base == (void *)FDT_ADDR_T_NONE)
+   if (!priv->base)
return -EINVAL;
 
priv->soc = soc;
diff --git a/include/dm/read.h b/include/dm/read.h
index b952551d55..555c73248c 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -799,7 +799,9 @@ static inline fdt_addr_t dev_read_addr(const struct udevice 
*dev)
 
 static inline void *dev_read_addr_ptr(const struct udevice *dev)
 {
-   return devfdt_get_addr_ptr(dev);
+   void *addr = devfdt_get_addr_ptr(dev);
+
+   return ((fdt_addr_t)(uintptr_t)addr == FDT_ADDR_T_NONE) ? NULL : addr;
 }
 
 static inline fdt_addr_t dev_read_addr_pci(const struct udevice *dev)
-- 
2.26.2

[PATCH v12 06/21] clk: Add a bypass clock for K210

[Sean Anderson]

This is a small driver to do a software bypass of a clock if hardware
bypass is not working. I have tried to write this in a generic fashion, so
that it could be potentially broken out of the kendryte code at some future
date. For the K210, it is used to have aclk bypass pll0 and use in0 instead
so that the CPU keeps on working.

Signed-off-by: Sean Anderson 
CC: Lukasz Majewski 
---

Changes in v5:
- Add function to register from a struct bypass

Changes in v4:
- New

 drivers/clk/kendryte/Makefile |   2 +-
 drivers/clk/kendryte/bypass.c | 270 ++
 include/kendryte/bypass.h |  31 
 3 files changed, 302 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/kendryte/bypass.c
 create mode 100644 include/kendryte/bypass.h

diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index c56d93ea1c..47f682fce3 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += pll.o
+obj-y += bypass.o pll.o
diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c
new file mode 100644
index 00..eb3e27d055
--- /dev/null
+++ b/drivers/clk/kendryte/bypass.c
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson 
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#define LOG_CATEGORY UCLASS_CLK
+#include 
+
+#define CLK_K210_BYPASS "k210_clk_bypass"
+
+/*
+ * This is a small driver to do a software bypass of a clock if hardware bypass
+ * is not working. I have tried to write this in a generic fashion, so that it
+ * could be potentially broken out of the kendryte code at some future date.
+ *
+ * Say you have the following clock configuration
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ * ^
+ */|
+ *   / |
+ *  /  |
+ * /   |
+ */|
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * But the pll does not have a bypass, so when you configure the pll, the
+ * configuration needs to change to look like
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ *   ^
+ *   |\
+ *   | \
+ *   |  \
+ *   |   \
+ *   |\
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * To set this up, create a bypass clock with bypassee=pll and alt=osc. When
+ * creating the child clocks, set their parent to the bypass clock. After
+ * creating all the children, call k210_bypass_setchildren().
+ */
+
+static int k210_bypass_dobypass(struct k210_bypass *bypass)
+{
+   int ret, i;
+
+   /*
+* If we already have saved parents, then the children are already
+* bypassed
+*/
+   if (bypass->child_count && bypass->saved_parents[0])
+   return 0;
+
+   for (i = 0; i < bypass->child_count; i++) {
+   struct clk *child = bypass->children[i];
+   struct clk *parent = clk_get_parent(child);
+
+   if (IS_ERR(parent)) {
+   for (; i; i--)
+   bypass->saved_parents[i] = NULL;
+   return PTR_ERR(parent);
+   }
+   bypass->saved_parents[i] = parent;
+   }
+
+   for (i = 0; i < bypass->child_count; i++) {
+   struct clk *child = bypass->children[i];
+
+   ret = clk_set_parent(child, bypass->alt);
+   if (ret) {
+   for (; i; i--)
+   clk_set_parent(bypass->children[i],
+  bypass->saved_parents[i]);
+   for (i = 0; i < bypass->child_count; i++)
+   bypass->saved_parents[i] = NULL;
+   return ret;
+   }
+   }
+
+   return 0;
+}
+
+static int k210_bypass_unbypass(struct k210_bypass *bypass)
+{
+   int err, ret, i;
+
+   if (!bypass->child_count && !bypass->saved_parents[0]) {
+   log_warning("Cannot unbypass children; dobypass not called 
first\n");
+   return 0;
+   }
+
+   ret = 0;
+   for (i = 0; i < bypass->child_count; i++) {
+   err = clk_set_parent(bypass->children[i],
+bypass->saved_parents[i]);
+   if (err)
+   ret = err;
+   bypass->saved_parents[i] = NULL;
+   }
+   return ret;
+}
+
+static ulong k210_bypass_get_rate(struct clk *clk)
+{
+   struct k210_bypass *bypass = to_k210_bypass(clk);
+   const struct clk_ops *ops = bypass->bypassee_ops;
+
+   if (ops->get_rate)
+   return ops->get_rate(bypass->bypassee);
+   else
+   return clk_get_parent_rate(bypass->bypassee);
+}
+
+static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate)
+{
+   int ret;
+   struct k210_bypass *bypass = to_k210_bypass(clk);
+   const struct clk_ops *ops = bypass->bypassee_ops;
+
+   /* Don't bother bypassing if we aren't going to set the rate */
+ 

[PATCH v12 01/21] clk: Always use the supplied struct clk

[Sean Anderson]

CCF clocks should always use the struct clock passed to their methods for
extracting the driver-specific clock information struct. Previously, many
functions would use the clk->dev->priv if the device was bound. This could
cause problems with composite clocks. The individual clocks in a composite
clock did not have the ->dev field filled in. This was fine, because the
device-specific clock information would be used. However, since there was
no ->dev, there was no way to get the parent clock. This caused the
recalc_rate method of the CCF divider clock to fail. One option would be to
use the clk->priv field to get the composite clock and from there get the
appropriate parent device. However, this would tie the implementation to
the composite clock. In general, different devices should not rely on the
contents of ->priv from another device.

The simple solution to this problem is to just always use the supplied
struct clock. The composite clock now fills in the ->dev pointer of its
child clocks.  This allows child clocks to make calls like clk_get_parent()
without issue.

imx avoided the above problem by using a custom get_rate function with
composite clocks.

Signed-off-by: Sean Anderson 
Acked-by: Lukasz Majewski 
---

Changes in v4:
- Lint

Changes in v3:
- Documented new assumptions in the CCF
- Wrapped docs to 80 columns

 doc/imx/clk/ccf.txt| 63 +-
 drivers/clk/clk-composite.c|  7 
 drivers/clk/clk-divider.c  |  6 ++--
 drivers/clk/clk-fixed-factor.c |  3 +-
 drivers/clk/clk-gate.c |  6 ++--
 drivers/clk/clk-mux.c  | 12 +++
 drivers/clk/imx/clk-gate2.c|  4 +--
 7 files changed, 50 insertions(+), 51 deletions(-)

diff --git a/doc/imx/clk/ccf.txt b/doc/imx/clk/ccf.txt
index 36b60dc438..e40ac360e8 100644
--- a/doc/imx/clk/ccf.txt
+++ b/doc/imx/clk/ccf.txt
@@ -1,42 +1,37 @@
 Introduction:
 =
 
-This documentation entry describes the Common Clock Framework [CCF]
-port from Linux kernel (v5.1.12) to U-Boot.
+This documentation entry describes the Common Clock Framework [CCF] port from
+Linux kernel (v5.1.12) to U-Boot.
 
-This code is supposed to bring CCF to IMX based devices (imx6q, imx7
-imx8). Moreover, it also provides some common clock code, which would
-allow easy porting of CCF Linux code to other platforms.
+This code is supposed to bring CCF to IMX based devices (imx6q, imx7 imx8).
+Moreover, it also provides some common clock code, which would allow easy
+porting of CCF Linux code to other platforms.
 
 Design decisions:
 =
 
-* U-Boot's driver model [DM] for clk differs from Linux CCF. The most
-  notably difference is the lack of support for hierarchical clocks and
-  "clock as a manager driver" (single clock DTS node acts as a starting
-  point for all other clocks).
+* U-Boot's driver model [DM] for clk differs from Linux CCF. The most notably
+  difference is the lack of support for hierarchical clocks and "clock as a
+  manager driver" (single clock DTS node acts as a starting point for all other
+  clocks).
 
-* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE
-  is not set (no need for recursive access).
+* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE is
+  not set (no need for recursive access).
 
-* On purpose the "manager" clk driver (clk-imx6q.c) is not using large
-  table to store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = 
-  Instead we use udevice's linked list for the same class (UCLASS_CLK).
+* On purpose the "manager" clk driver (clk-imx6q.c) is not using large table to
+  store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] =  Instead we
+  use udevice's linked list for the same class (UCLASS_CLK).
 
   Rationale:
   --
-When porting the code as is from Linux, one would need ~1KiB of RAM to
-store it. This is way too much if we do plan to use this driver in SPL.
+When porting the code as is from Linux, one would need ~1KiB of RAM to 
store
+it. This is way too much if we do plan to use this driver in SPL.
 
 * The "central" structure of this patch series is struct udevice and its
   uclass_priv field contains the struct clk pointer (to the originally created
   one).
 
-* Up till now U-Boot's driver model (DM) CLK operates on udevice (main
-  access to clock is by udevice ops)
-  In the CCF the access to struct clk (embodying pointer to *dev) is
-  possible via dev_get_clk_ptr() (it is a wrapper on dev_get_uclass_priv()).
-
 * To keep things simple the struct udevice's uclass_priv pointer is used to
   store back pointer to corresponding struct clk. However, it is possible to
   modify clk-uclass.c file and add there struct uc_clk_priv, which would have
@@ -45,13 +40,17 @@ Design decisions:
   setting .per_device_auto_alloc_size = sizeof(struct uc_clk_priv)) the
   uclass_priv stores the pointer to struct clk.
 
+* Non-CCF clocks do not have a pointer to a clock in 

[PATCH v12 04/21] clk: Fix clk_get_by_* handling of index

[Sean Anderson]

clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean
predicate instead of the index. Other clk_get_by_* functions got the clock
correctly, but passed a predicate instead of the index to clk_get_by_tail.
This could lead to confusing error messages.

Signed-off-by: Sean Anderson 
CC: Lukasz Majewski 
---

Changes in v7:
- New

 drivers/clk/clk-uclass.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 774d6ccdf8..ac725abfdf 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -123,7 +123,7 @@ static int clk_get_by_indexed_prop(struct udevice *dev, 
const char *prop_name,
 
 
return clk_get_by_index_tail(ret, dev_ofnode(dev), , "clocks",
-index > 0, clk);
+index, clk);
 }
 
 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
@@ -135,7 +135,7 @@ int clk_get_by_index(struct udevice *dev, int index, struct 
clk *clk)
 index, );
 
return clk_get_by_index_tail(ret, dev_ofnode(dev), , "clocks",
-index > 0, clk);
+index, clk);
 }
 
 int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
@@ -144,10 +144,10 @@ int clk_get_by_index_nodev(ofnode node, int index, struct 
clk *clk)
int ret;
 
ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
-index > 0, );
+index, );
 
return clk_get_by_index_tail(ret, node, , "clocks",
-index > 0, clk);
+index, clk);
 }
 
 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
-- 
2.26.2

[PATCH v12 00/21] riscv: Add Sipeed Maix support

[Sean Anderson]

This patch series adds support for Sipeed Maix boards and the Kendryte
K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other
models are similar.

Known Bugs/Limitations:
- Accessing the AI ram hangs, limiting available ram to 6M
- Trying to boot an image with bootm fails with
  ERROR: Failed to allocate 0x7d60 bytes below 0x8000.

To flash u-boot to a maix bit, run
kflash -tp /dev/ -B bit_mic u-boot-dtb.bin

Boot output should look like the following:

U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)

DRAM:  8 MiB
In:serial@3800
Out:   serial@3800
Err:   serial@3800
=>

Changes for v12:
- Remove sanity check in IPI code as requested

Changes for v11:
- Fix hang in SPL because the IPI was not initialized

Changes for v10:
- Fix warnings when casting fdt_addr_t
- Fix warnings about const functions

Changes for v9:
- Fix error in Andes PLIC
- Update MAINTAINERS
- Mark dts blocks in documentation as "none" highlighting

Changes for v8:
- Removed dependency on the patch "clk: Add functions to register CCF clock
  structs". Hopefully this will make reviewing easier.

Changes for v7:
- Split documentation from other board support
- Split IPI clear from other IPI cleanup
- Rebased onto a clean upstream. Hopefully this fixes any patching
  problems.

Changes for v6:
- Remove spi, pinmux, gpio, led, and wdt support --- to be added in separate
  patches
- Rebase onto master
- Clear IPIs before enabling them
- Reorganize code so checkpatch errors less

Changes for v5:
- Rebase onto master
- Add pinconf support
- Add gpio support
- Store environment in spi flash
- Group patches by prefix
- Add additional documentation
- Add SMP support
- Add WDT support

Changes for v4:
- Linted several patches
- Updated the copyright year for several files
- Added tests for syscon-reset, simple-pm-bus, and the pll calc_rate function
- Added/updated documentation
- Fixed SPI for the nor flash
- Fixed PLLs not enabling/setting rate properly
- RISCV_PRIV_1_9_1 now (un)defines all diferring CSRs, and also disables VM
- More devicetree changes

Changes for v3:
- Remove patch to set RV64I as default
- Remove patch for a separate sysctl driver
- Split off cpu frequency patch into its own series
- Reorder support/devicetree patches to come last
- Add patch for reset driver
- Add simple-pm-bus for busses with their own clocks
- Add additional documentation
- Reword mcounteren patch to refer to the RISC-V priv spec 1.9.1
- Many devicetree changes
- Switch to "make savedefconfig" to generate the config

Changes for v2:
- Many bugfixes for the device tree
- Modify the config to build without errors
- Add support for keeping internal PLL frequencies in-range
- Fix several rebase-induced artifacts

Sean Anderson (21):
  clk: Always use the supplied struct clk
  clk: Check that ops of composite clock components exist before calling
  clk: Unconditionally recursively en-/dis-able clocks
  clk: Fix clk_get_by_* handling of index
  clk: Add K210 pll support
  clk: Add a bypass clock for K210
  clk: Add K210 clock support
  dm: Add support for simple-pm-bus
  dm: Fix error handling for dev_read_addr_ptr
  reset: Add generic reset driver
  lib: Always set errno in hcreate_r
  riscv: Add headers for asm/global_data.h
  riscv: Clear pending interrupts before enabling IPIs
  riscv: Clean up IPI initialization code
  riscv: Add option to support RISC-V privileged spec 1.9
  riscv: Allow use of reset drivers
  riscv: Try to get cpu frequency from a "clocks" node if it exists
  riscv: Enable cpu clock if it is present
  riscv: Add device tree for K210 and Sipeed Maix BitM
  doc: riscv: Add documentation for Sipeed Maix Bit
  riscv: Add Sipeed Maix support

 MAINTAINERS   |   7 +
 arch/riscv/Kconfig|  14 +
 arch/riscv/cpu/cpu.c  |  15 +
 arch/riscv/cpu/start.S|   2 +
 arch/riscv/dts/Makefile   |   1 +
 arch/riscv/dts/k210-maix-bit.dts  |  47 ++
 arch/riscv/dts/k210.dtsi  | 594 
 arch/riscv/include/asm/csr.h  |  40 ++
 arch/riscv/include/asm/global_data.h  |   2 +
 arch/riscv/include/asm/smp.h  |  43 ++
 arch/riscv/lib/andes_plic.c   |  34 +-
 arch/riscv/lib/reset.c|   2 +
 arch/riscv/lib/sbi_ipi.c  |   5 +
 arch/riscv/lib/sifive_clint.c |  33 +-
 arch/riscv/lib/smp.c  |  50 +-
 arch/sandbox/dts/test.dts |  21 +
 arch/sandbox/include/asm/clk.h|   1 +
 board/sipeed/maix/Kconfig |  47 ++
 board/sipeed/maix/MAINTAINERS |  11 +
 board/sipeed/maix/Makefile|   5 +
 board/sipeed/maix/maix.c  |  41 ++
 common/spl/spl_opensbi.c  |   5 +
 configs/sandbox_defconfig   

[PATCH v12 02/21] clk: Check that ops of composite clock components exist before calling

[Sean Anderson]

clk_composite_ops was shared between all devices in the composite clock
driver.  If one clock had a feature (such as supporting set_parent) which
another clock did not, it could call a null pointer dereference.

This patch does three things
1. It adds null-pointer checks to all composite clock functions.
2. It makes clk_composite_ops const and sets its functions at compile-time.
3. It adds some basic sanity checks to num_parents.

The combined effect of these changes is that any of mux, rate, or gate can
be NULL, and composite clocks will still function normally. Previously, at
least mux had to exist, since clk_composite_get_parent was used to
determine the parent for clk_register.

Signed-off-by: Sean Anderson 
Acked-by: Lukasz Majewski 
---

Changes in v4:
- Return ENOTSUPP not ENOSYS with no set_parent

Changes in v3:
- Don't return an error code where a no-op would be fine

 drivers/clk/clk-composite.c | 57 +++--
 1 file changed, 35 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 2ff1d6b47f..819bfca2fc 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -24,7 +24,10 @@ static u8 clk_composite_get_parent(struct clk *clk)
(struct clk *)dev_get_clk_ptr(clk->dev) : clk);
struct clk *mux = composite->mux;
 
-   return clk_mux_get_parent(mux);
+   if (mux)
+   return clk_mux_get_parent(mux);
+   else
+   return 0;
 }
 
 static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
@@ -34,7 +37,10 @@ static int clk_composite_set_parent(struct clk *clk, struct 
clk *parent)
const struct clk_ops *mux_ops = composite->mux_ops;
struct clk *mux = composite->mux;
 
-   return mux_ops->set_parent(mux, parent);
+   if (mux && mux_ops)
+   return mux_ops->set_parent(mux, parent);
+   else
+   return -ENOTSUPP;
 }
 
 static unsigned long clk_composite_recalc_rate(struct clk *clk)
@@ -44,7 +50,10 @@ static unsigned long clk_composite_recalc_rate(struct clk 
*clk)
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk *rate = composite->rate;
 
-   return rate_ops->get_rate(rate);
+   if (rate && rate_ops)
+   return rate_ops->get_rate(rate);
+   else
+   return clk_get_parent_rate(clk);
 }
 
 static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
@@ -54,7 +63,10 @@ static ulong clk_composite_set_rate(struct clk *clk, 
unsigned long rate)
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk *clk_rate = composite->rate;
 
-   return rate_ops->set_rate(clk_rate, rate);
+   if (rate && rate_ops)
+   return rate_ops->set_rate(clk_rate, rate);
+   else
+   return clk_get_rate(clk);
 }
 
 static int clk_composite_enable(struct clk *clk)
@@ -64,7 +76,10 @@ static int clk_composite_enable(struct clk *clk)
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk *gate = composite->gate;
 
-   return gate_ops->enable(gate);
+   if (gate && gate_ops)
+   return gate_ops->enable(gate);
+   else
+   return 0;
 }
 
 static int clk_composite_disable(struct clk *clk)
@@ -74,15 +89,12 @@ static int clk_composite_disable(struct clk *clk)
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk *gate = composite->gate;
 
-   gate_ops->disable(gate);
-
-   return 0;
+   if (gate && gate_ops)
+   return gate_ops->disable(gate);
+   else
+   return 0;
 }
 
-struct clk_ops clk_composite_ops = {
-   /* This will be set according to clk_register_composite */
-};
-
 struct clk *clk_register_composite(struct device *dev, const char *name,
   const char * const *parent_names,
   int num_parents, struct clk *mux,
@@ -96,7 +108,9 @@ struct clk *clk_register_composite(struct device *dev, const 
char *name,
struct clk *clk;
struct clk_composite *composite;
int ret;
-   struct clk_ops *composite_ops = _composite_ops;
+
+   if (!num_parents || (num_parents != 1 && !mux))
+   return ERR_PTR(-EINVAL);
 
composite = kzalloc(sizeof(*composite), GFP_KERNEL);
if (!composite)
@@ -105,8 +119,6 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
if (mux && mux_ops) {
composite->mux = mux;
composite->mux_ops = mux_ops;
-   if (mux_ops->set_parent)
-   composite_ops->set_parent = clk_composite_set_parent;
mux->data = (ulong)composite;
}
 
@@ -115,11 +127,6 @@ struct clk *clk_register_composite(struct device *dev, 
const char *name,
clk = ERR_PTR(-EINVAL);
goto err;

[PATCH v12 03/21] clk: Unconditionally recursively en-/dis-able clocks

[Sean Anderson]

For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
just enable them as normal. The enable count is local to the struct clk,
but this will never result in the actual en-/dis-able op being called
(unless the same struct clk is enabled twice).

For clocks in the CCF, we always traverse up the tree when enabling.
Previously, CCF clocks without id set would be skipped, stopping the
traversal too early.

Signed-off-by: Sean Anderson 
CC: Lukasz Majewski 
---

Changes in v6:
- Fix disable incorrectly recursing into non-clock devices

Changes in v5:
- Clear enable_count on request

Changes in v4:
- Lint

Changes in v3:
- New

 drivers/clk/clk-uclass.c | 60 ++--
 1 file changed, 27 insertions(+), 33 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 9ffc2243cb..774d6ccdf8 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -412,6 +412,7 @@ int clk_request(struct udevice *dev, struct clk *clk)
ops = clk_dev_ops(dev);
 
clk->dev = dev;
+   clk->enable_count = 0;
 
if (!ops->request)
return 0;
@@ -523,7 +524,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 int clk_enable(struct clk *clk)
 {
const struct clk_ops *ops;
-   struct clk *clkp = NULL;
int ret;
 
debug("%s(clk=%p)\n", __func__, clk);
@@ -532,32 +532,29 @@ int clk_enable(struct clk *clk)
ops = clk_dev_ops(clk->dev);
 
if (CONFIG_IS_ENABLED(CLK_CCF)) {
-   /* Take id 0 as a non-valid clk, such as dummy */
-   if (clk->id && !clk_get_by_id(clk->id, )) {
-   if (clkp->enable_count) {
-   clkp->enable_count++;
-   return 0;
-   }
-   if (clkp->dev->parent &&
-   device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
-   ret = 
clk_enable(dev_get_clk_ptr(clkp->dev->parent));
-   if (ret) {
-   printf("Enable %s failed\n",
-  clkp->dev->parent->name);
-   return ret;
-   }
+   if (clk->enable_count) {
+   clk->enable_count++;
+   return 0;
+   }
+   if (clk->dev->parent &&
+   device_get_uclass_id(clk->dev->parent) == UCLASS_CLK) {
+   ret = clk_enable(dev_get_clk_ptr(clk->dev->parent));
+   if (ret) {
+   printf("Enable %s failed\n",
+  clk->dev->parent->name);
+   return ret;
}
}
 
if (ops->enable) {
ret = ops->enable(clk);
if (ret) {
-   printf("Enable %s failed\n", clk->dev->name);
+   printf("Enable %s failed (error %d)\n",
+  clk->dev->name, ret);
return ret;
}
}
-   if (clkp)
-   clkp->enable_count++;
+   clk->enable_count++;
} else {
if (!ops->enable)
return -ENOSYS;
@@ -583,7 +580,6 @@ int clk_enable_bulk(struct clk_bulk *bulk)
 int clk_disable(struct clk *clk)
 {
const struct clk_ops *ops;
-   struct clk *clkp = NULL;
int ret;
 
debug("%s(clk=%p)\n", __func__, clk);
@@ -592,29 +588,27 @@ int clk_disable(struct clk *clk)
ops = clk_dev_ops(clk->dev);
 
if (CONFIG_IS_ENABLED(CLK_CCF)) {
-   if (clk->id && !clk_get_by_id(clk->id, )) {
-   if (clkp->enable_count == 0) {
-   printf("clk %s already disabled\n",
-  clkp->dev->name);
-   return 0;
-   }
-
-   if (--clkp->enable_count > 0)
-   return 0;
+   if (clk->enable_count == 0) {
+   printf("clk %s already disabled\n",
+  clk->dev->name);
+   return 0;
}
 
+   if (--clk->enable_count > 0)
+   return 0;
+
if (ops->disable) {
ret = ops->disable(clk);
if (ret)
return ret;
}
 
-   if (clkp && clkp->dev->parent &&
-   device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
-   ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
+   if (clk->dev->parent &&
+  

Re: [PATCH] rockchip: rk3328: rock64 - fix gen3 SPL hang

[Matwey V. Kornilov]

ср, 20 мая 2020 г. в 20:41, Kurt Miller :
>
> On Wed, 2020-05-20 at 16:30 +0800, Chen-Yu Tsai wrote:
> > On Wed, May 20, 2020 at 4:05 PM Matwey V. Kornilov
> >  wrote:
> > >
> > >
> > > вт, 19 мая 2020 г. в 17:30, Kurt Miller :
> > > >
> > > >
> > > > On Tue, 2020-05-19 at 12:48 +0300, Matwey V. Kornilov wrote:
> > > > >
> > > > > вт, 19 мая 2020 г. в 01:06, Kurt Miller :
> > > > > >
> > > > > >
> > > > > >
> > > > > > On Wed, 2020-05-13 at 16:10 -0400, Kurt Miller wrote:
> > > > > > >
> > > > > > >
> > > > > > > On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > Thanks. Have you already checked it on gen2? I think I have 
> > > > > > > > gen2 board to test.
> > > > > > > Yes, I have both gen3 and gen2 boards. gen2 continues to work
> > > > > > > with this patch as well.
> > > > > > Hi Matwey,
> > > > > Hi Kurt,
> > > > >
> > > > > Sorry for the late reply. I've just managed to apply you patch on top
> > > > > of ed9a3aa645 and it didn't work for me on 2GB v2.0 rock64 board.
> > > > >
> > > > > U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 
> > > > > 12:44:16)
> > > > > LPDDR3, 800MHz
> > > > > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
> > > > > Trying to boot from BOOTROM
> > > > > Returning to boot ROM...
> > > > >
> > > > > U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 
> > > > > 12:44:16 +0300)
> > > > > Trying to boot from MMC1
> > > > > [and nothing else happens here]
> > > > >
> > > > > What do you think may be the reason?
> > > > Hi Matwey,
> > > >
> > > Hi Kurt,
> > >
> > > >
> > > > Thank you for testing the patch. Hmm, are you building with ATF 2.3?
> > > You are right here, I was testing with ATF 2.1, while ATF 2.3 works 
> > > correctly.
> > > First working commit in ATF is 0aad563c ("rockchip: Update BL31_BASE
> > > to 0x4").
>
> Great! I did some more gen2 testing as well. Booting with just eMMC
> works and with both eMMC and uSD also works for me.
>
> > > I suppose, it is worth to mention in the commit message for this
> > > patch. What do you think?
> > This was already mentioned in commits such as
> >
> > c0a474b9d9a1 rockchip: evb-rk3328: Enable support ATF in SPL
> > 4690ef8907e9 rockchip: rk3288-evb: update SPL_STACK/MALLOC_LEN config
> > with rk3399
> > 6024467bcc0e rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs
> > 006ab58d4636 rockchip: rk3399: update SPL_STACK_R_ADDR
> >
> > ChenYu
> >
>
> Yes this changed back in the 2020.01 release time-frame. If the
> commit message needs improvement, please suggest what you want
> and I can resubmit the patch.

Well, I think it is fine anyway.

>
> Thanks,
> -Kurt
>
> > >
> > >
> > > >
> > > >
> > > > I’m booting from the uSD without an eMMC installed. Are you booting
> > > > from the eMMC or have one installed?
> > > I'm booting from uSD without eMMC installed also.
> > >
> > >
> > > >
> > > >
> > > > Here are some background emails related to the gen3 freeze. I also
> > > > included the output for when gen3 fails below and the output for
> > > > my gen2 2gb and gen3 4gb with the patch.
> > > >
> > > > https://marc.info/?l=u-boot=158550521101881=2
> > > > https://marc.info/?l=u-boot=156427088018689=2
> > > >
> > > > Gen2 2GB with patch:
> > > >
> > > > U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15)
> > > > LPDDR3, 800MHz
> > > > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
> > > > Trying to boot from BOOTROM
> > > > Returning to boot ROM...
> > > >
> > > > U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 
> > > > -0400)
> > > > Trying to boot from MMC1
> > > > NOTICE:  BL31: v2.3():2.3
> > > > NOTICE:  BL31: Built : 11:30:57, May 15 2020
> > > > NOTICE:  BL31:Rockchip release version: v1.2
> > > > INFO:ARM GICv2 driver initialized
> > > > INFO:plat_rockchip_pmu_init: pd status 0xe
> > > > INFO:BL31: Initializing runtime services
> > > > INFO:BL31: cortex_a53: CPU workaround for 855873 was applied
> > > > INFO:BL31: Preparing for EL3 exit to normal world
> > > > INFO:Entry point address = 0x20
> > > > INFO:SPSR = 0x3c9
> > > >
> > > >
> > > > U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 
> > > > -0400)
> > > >
> > > > Model: Pine64 Rock64
> > > > DRAM:  2 GiB
> > > > PMIC:  RK8050 (on=0x40, off=0x01)
> > > > MMC:   mmc@ff50: 1, mmc@ff52: 0
> > > > Loading Environment from MMC... *** Warning - bad CRC, using default 
> > > > environment
> > > >
> > > > In:serial@ff13
> > > > Out:   serial@ff13
> > > > Err:   serial@ff13
> > > > Model: Pine64 Rock64
> > > > Net:   eth0: ethernet@ff54
> > > > Hit any key to stop autoboot:  0
> > > > Card did not respond to voltage select!
> > > > switch to partitions #0, OK
> > > > mmc1 is current device
> > > > Scanning mmc 1:1...
> > > > Found EFI removable media binary efi/boot/bootaa64.efi
> > > > libfdt 

Re: [PATCH] rockchip: rk3328: rock64 - fix gen3 SPL hang

[Matwey V. Kornilov]

ср, 13 мая 2020 г. в 22:55, Kurt Miller :
>
> Use the same approach as ROC-RK3328-CC which enables SPL GPIO,
> pinctl and regulator support. This allows the gen3 board to
> boot through SPL and does not break gen2 in the process.
>
> Signed-off-by: Kurt Miller 

Acked-by: Matwey V. Kornilov 

> ---
>
>  arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +
>  configs/rock64-rk3328_defconfig|  7 ++-
>  2 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi 
> b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
> index 8318bf4e60..f076075076 100644
> --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
> +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
> @@ -11,6 +11,22 @@
> };
>  };
>
> + {
> +   u-boot,dm-spl;
> +};
> +
> + {
> +   u-boot,dm-spl;
> +};
> +
> +_gpio {
> +   u-boot,dm-spl;
> +};
> +
> +_pull_up_4ma {
> +   u-boot,dm-spl;
> +};
> +
>  _host0_xhci {
> vbus-supply = <_host_5v>;
> status = "okay";
> @@ -25,3 +41,8 @@
> /delete-property/ regulator-always-on;
> /delete-property/ regulator-boot-on;
>  };
> +
> +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
> +_sd {
> +   u-boot,dm-spl;
> +};
> diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
> index 7d096d38c6..0bc2198f5c 100644
> --- a/configs/rock64-rk3328_defconfig
> +++ b/configs/rock64-rk3328_defconfig
> @@ -1,6 +1,7 @@
>  CONFIG_ARM=y
>  CONFIG_ARCH_ROCKCHIP=y
>  CONFIG_SYS_TEXT_BASE=0x0020
> +CONFIG_SPL_GPIO_SUPPORT=y
>  CONFIG_ENV_OFFSET=0x3F8000
>  CONFIG_ROCKCHIP_RK3328=y
>  CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
> @@ -25,6 +26,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
>  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>  CONFIG_TPL_SYS_MALLOC_SIMPLE=y
>  CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_SPL_POWER_SUPPORT=y
>  CONFIG_SPL_ATF=y
>  CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
>  CONFIG_CMD_BOOTZ=y
> @@ -36,7 +39,7 @@ CONFIG_CMD_TIME=y
>  CONFIG_SPL_OF_CONTROL=y
>  CONFIG_TPL_OF_CONTROL=y
>  CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
> -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
> interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
> assigned-clock-rates assigned-clock-parents"
>  CONFIG_TPL_OF_PLATDATA=y
>  CONFIG_ENV_IS_IN_MMC=y
>  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> @@ -64,7 +67,9 @@ CONFIG_PINCTRL=y
>  CONFIG_SPL_PINCTRL=y
>  CONFIG_DM_PMIC=y
>  CONFIG_PMIC_RK8XX=y
> +CONFIG_SPL_DM_REGULATOR=y
>  CONFIG_REGULATOR_PWM=y
> +CONFIG_SPL_DM_REGULATOR_FIXED=y
>  CONFIG_DM_REGULATOR_FIXED=y
>  CONFIG_REGULATOR_RK8XX=y
>  CONFIG_PWM_ROCKCHIP=y
> --
> 2.26.0
>


-- 
With best regards,
Matwey V. Kornilov

Re: [PATCH] rockchip: rk3328: rock64 - fix gen3 SPL hang

[Kurt Miller]

On Wed, 2020-05-20 at 16:30 +0800, Chen-Yu Tsai wrote:
> On Wed, May 20, 2020 at 4:05 PM Matwey V. Kornilov
>  wrote:
> > 
> > 
> > вт, 19 мая 2020 г. в 17:30, Kurt Miller :
> > > 
> > > 
> > > On Tue, 2020-05-19 at 12:48 +0300, Matwey V. Kornilov wrote:
> > > > 
> > > > вт, 19 мая 2020 г. в 01:06, Kurt Miller :
> > > > > 
> > > > > 
> > > > > 
> > > > > On Wed, 2020-05-13 at 16:10 -0400, Kurt Miller wrote:
> > > > > > 
> > > > > > 
> > > > > > On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > Thanks. Have you already checked it on gen2? I think I have gen2 
> > > > > > > board to test.
> > > > > > Yes, I have both gen3 and gen2 boards. gen2 continues to work
> > > > > > with this patch as well.
> > > > > Hi Matwey,
> > > > Hi Kurt,
> > > > 
> > > > Sorry for the late reply. I've just managed to apply you patch on top
> > > > of ed9a3aa645 and it didn't work for me on 2GB v2.0 rock64 board.
> > > > 
> > > > U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16)
> > > > LPDDR3, 800MHz
> > > > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
> > > > Trying to boot from BOOTROM
> > > > Returning to boot ROM...
> > > > 
> > > > U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16 
> > > > +0300)
> > > > Trying to boot from MMC1
> > > > [and nothing else happens here]
> > > > 
> > > > What do you think may be the reason?
> > > Hi Matwey,
> > > 
> > Hi Kurt,
> > 
> > > 
> > > Thank you for testing the patch. Hmm, are you building with ATF 2.3?
> > You are right here, I was testing with ATF 2.1, while ATF 2.3 works 
> > correctly.
> > First working commit in ATF is 0aad563c ("rockchip: Update BL31_BASE
> > to 0x4").

Great! I did some more gen2 testing as well. Booting with just eMMC
works and with both eMMC and uSD also works for me.

> > I suppose, it is worth to mention in the commit message for this
> > patch. What do you think?
> This was already mentioned in commits such as
> 
> c0a474b9d9a1 rockchip: evb-rk3328: Enable support ATF in SPL
> 4690ef8907e9 rockchip: rk3288-evb: update SPL_STACK/MALLOC_LEN config
> with rk3399
> 6024467bcc0e rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs
> 006ab58d4636 rockchip: rk3399: update SPL_STACK_R_ADDR
> 
> ChenYu
> 

Yes this changed back in the 2020.01 release time-frame. If the
commit message needs improvement, please suggest what you want
and I can resubmit the patch.

Thanks,
-Kurt

> > 
> > 
> > > 
> > > 
> > > I’m booting from the uSD without an eMMC installed. Are you booting
> > > from the eMMC or have one installed?
> > I'm booting from uSD without eMMC installed also.
> > 
> > 
> > > 
> > > 
> > > Here are some background emails related to the gen3 freeze. I also
> > > included the output for when gen3 fails below and the output for
> > > my gen2 2gb and gen3 4gb with the patch.
> > > 
> > > https://marc.info/?l=u-boot=158550521101881=2
> > > https://marc.info/?l=u-boot=156427088018689=2
> > > 
> > > Gen2 2GB with patch:
> > > 
> > > U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15)
> > > LPDDR3, 800MHz
> > > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
> > > Trying to boot from BOOTROM
> > > Returning to boot ROM...
> > > 
> > > U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 
> > > -0400)
> > > Trying to boot from MMC1
> > > NOTICE:  BL31: v2.3():2.3
> > > NOTICE:  BL31: Built : 11:30:57, May 15 2020
> > > NOTICE:  BL31:Rockchip release version: v1.2
> > > INFO:ARM GICv2 driver initialized
> > > INFO:plat_rockchip_pmu_init: pd status 0xe
> > > INFO:BL31: Initializing runtime services
> > > INFO:BL31: cortex_a53: CPU workaround for 855873 was applied
> > > INFO:BL31: Preparing for EL3 exit to normal world
> > > INFO:Entry point address = 0x20
> > > INFO:SPSR = 0x3c9
> > > 
> > > 
> > > U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
> > > 
> > > Model: Pine64 Rock64
> > > DRAM:  2 GiB
> > > PMIC:  RK8050 (on=0x40, off=0x01)
> > > MMC:   mmc@ff50: 1, mmc@ff52: 0
> > > Loading Environment from MMC... *** Warning - bad CRC, using default 
> > > environment
> > > 
> > > In:serial@ff13
> > > Out:   serial@ff13
> > > Err:   serial@ff13
> > > Model: Pine64 Rock64
> > > Net:   eth0: ethernet@ff54
> > > Hit any key to stop autoboot:  0
> > > Card did not respond to voltage select!
> > > switch to partitions #0, OK
> > > mmc1 is current device
> > > Scanning mmc 1:1...
> > > Found EFI removable media binary efi/boot/bootaa64.efi
> > > libfdt fdt_check_header(): FDT_ERR_BADMAGIC
> > > Scanning disk m...@ff50.blk...
> > > ** Unrecognized filesystem type **
> > > Card did not respond to voltage select!
> > > Scanning disk m...@ff52.blk...
> > > Disk m...@ff52.blk not ready
> > > Found 3 disks
> > > BootOrder not defined
> > > EFI boot manager: Cannot load any image
> > > 

Re: [PATCH v2 2/3] spl: fit: fail fit loading in case of FDT appending error

[Michael Nazzareno Trimarchi]

Hi Dario

On Mon, May 11, 2020 at 8:43 AM Dario Binacchi  wrote:
>
> If uboot does not embed its device tree and the FIT loading function
> returns error in case of failure in the FDT append, the redundant itb
> image could be loaded.
>
> cc: Michael Trimarchi 
> Signed-off-by: Dario Binacchi 
>
> ---
>
> Changes in v2:
>  - Replace CONFIG_IS_ENABLED(OF_EMBED) with IS_ENABLED(CONFIG_OF_EMBED))
>
>  common/spl/spl_fit.c | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index c51e4beb1c..42c354c908 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -617,9 +617,12 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
>  * Booting a next-stage U-Boot may require us to append the FDT.
>  * We allow this to fail, as the U-Boot image might embed its FDT.
>  */
> -   if (spl_image->os == IH_OS_U_BOOT)
> -   spl_fit_append_fdt(spl_image, info, sector, fit,
> -  images, base_offset);
> +   if (spl_image->os == IH_OS_U_BOOT) {
> +   ret = spl_fit_append_fdt(spl_image, info, sector, fit,
> +images, base_offset);
> +   if (!IS_ENABLED(CONFIG_OF_EMBED) && ret < 0)
> +   return ret;
> +   }
>

Reviewed-by: Michael Trimarchi 

> firmware_node = node;
> /* Now check if there are more images for us to load */
> --
> 2.17.1
>


-- 
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO  -  Founder  Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
|  [`as] http://www.amarulasolutions.com   |

[PATCH] phy: Fix possible NULL pointer deference

[Vignesh Raghavendra]

It is possible that users of generic_phy_*() APIs may pass a valid
struct phy pointer but phy->dev can be NULL, leading to NULL pointer
deference in phy_dev_ops().

So call generic_phy_valid() to verify that phy and phy->dev are both
valid.

Signed-off-by: Vignesh Raghavendra 
---
 drivers/phy/phy-uclass.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c
index 1fded5ebf42f..89510c5772e0 100644
--- a/drivers/phy/phy-uclass.c
+++ b/drivers/phy/phy-uclass.c
@@ -117,7 +117,7 @@ int generic_phy_init(struct phy *phy)
 {
struct phy_ops const *ops;
 
-   if (!phy)
+   if (!generic_phy_valid(phy))
return 0;
ops = phy_dev_ops(phy->dev);
 
@@ -128,7 +128,7 @@ int generic_phy_reset(struct phy *phy)
 {
struct phy_ops const *ops;
 
-   if (!phy)
+   if (!generic_phy_valid(phy))
return 0;
ops = phy_dev_ops(phy->dev);
 
@@ -139,7 +139,7 @@ int generic_phy_exit(struct phy *phy)
 {
struct phy_ops const *ops;
 
-   if (!phy)
+   if (!generic_phy_valid(phy))
return 0;
ops = phy_dev_ops(phy->dev);
 
@@ -150,7 +150,7 @@ int generic_phy_power_on(struct phy *phy)
 {
struct phy_ops const *ops;
 
-   if (!phy)
+   if (!generic_phy_valid(phy))
return 0;
ops = phy_dev_ops(phy->dev);
 
@@ -161,7 +161,7 @@ int generic_phy_power_off(struct phy *phy)
 {
struct phy_ops const *ops;
 
-   if (!phy)
+   if (!generic_phy_valid(phy))
return 0;
ops = phy_dev_ops(phy->dev);
 
-- 
2.26.2

Re: [PATCH v4] dm: uclass: don't assign aliased seq numbers

[Michael Walle]

Hi Simon,

Am 2020-05-19 18:47, schrieb Simon Glass:

Hi Michael,

On Tue, 19 May 2020 at 06:17, Michael Walle  wrote:


Hi Simon,

Am 2020-04-24 16:17, schrieb Michael Walle:
> Hi Simon,
>
> Am 2020-04-20 01:38, schrieb Simon Glass:
>
> [..snip..]
>
>>> > uclass 31: eth
>>> > 0   * smsc95xx_eth @ 3db69ac0, seq 0, (req -1)
>>>
>>> Shouldn't this be "req 0" if the ethernet alias is actually matched.
>>> Does u-boot actually supports matching usb nodes to devices? If not,
>>> shouldn't the alias be removed then?
>>>
>>> That being said, it is still strange why the bootloader doesn't find
>>> ethernet-1 then. I've tried with my board, no native ethernet support
>>> and an usb network dongle which works as expected (well the dongle
>>> seems to have some issues to actually transfer frames).
>>
>> It is a bit strange. Removing the alias does not fix it though.
>
> Are you sure you removed the alias in the correct file? There are two,
> could you please double check if is not contained in the resulting
> device tree?
>
> dtc -I dtb -O dts dts/dt.dtb
>
> I just tested it on a rpi3b. and it works if i remove the alias.
>
>> So far as I know U-Boot doesn't work with the alias, since there is no
>> driver for the "usb424,2514" compatible string.
>
> So it is actually correct behaviour of my patch. ethernet1 doesn't work
> because there is no eth1addr. So I see three solutions:
>
> (1) make the matching work
> (2) remove the alias
> (3) set eth1addr instead of ethaddr

Any news on this? Can I help somewhere? I'd go with (2).


What is involved in (1)?


I've given it a try in the new v5 version.

-michael

[PATCH v5 1/2] usb: provide a device tree node to USB devices

[Michael Walle]

It is possible to specify a device tree node for an USB device. This is
useful if you have a static USB setup and want to use aliases which
point to these nodes, like on the Raspberry Pi.
The nodes are matched against their hub port number, the compatible
strings are not matched for now.

Signed-off-by: Michael Walle 
---
This is a new patch in v5:
  Fixes the ethernet0 alias on Raspberry Pis. This has never been
  working, but wasn't a problem until recently. Patch 2/2 changes
  the allocation of the numbers and reserves possible aliases.

 drivers/usb/host/usb-uclass.c | 41 ++-
 1 file changed, 36 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index cb79dfbbd5..f42c0625cb 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -494,6 +494,35 @@ static int usb_match_one_id(struct usb_device_descriptor 
*desc,
return usb_match_one_id_intf(desc, int_desc, id);
 }
 
+static ofnode usb_get_ofnode(struct udevice *hub, int port)
+{
+   ofnode node;
+   u32 reg;
+
+   if (!dev_has_of_node(hub))
+   return ofnode_null();
+
+   /*
+* The USB controller and its USB hub are two different udevices,
+* but the device tree has only one node for both. Thus we are
+* assigning this node to both udevices.
+* If port is zero, the controller scans its root hub, thus we
+* are using the same ofnode as the controller here.
+*/
+   if (!port)
+   return dev_ofnode(hub);
+
+   ofnode_for_each_subnode(node, dev_ofnode(hub)) {
+   if (ofnode_read_u32(node, "reg", ))
+   continue;
+
+   if (reg == port)
+   return node;
+   }
+
+   return ofnode_null();
+}
+
 /**
  * usb_find_and_bind_driver() - Find and bind the right USB driver
  *
@@ -502,13 +531,14 @@ static int usb_match_one_id(struct usb_device_descriptor 
*desc,
 static int usb_find_and_bind_driver(struct udevice *parent,
struct usb_device_descriptor *desc,
struct usb_interface_descriptor *iface,
-   int bus_seq, int devnum,
+   int bus_seq, int devnum, int port,
struct udevice **devp)
 {
struct usb_driver_entry *start, *entry;
int n_ents;
int ret;
char name[30], *str;
+   ofnode node = usb_get_ofnode(parent, port);
 
*devp = NULL;
debug("%s: Searching for driver\n", __func__);
@@ -533,8 +563,8 @@ static int usb_find_and_bind_driver(struct udevice *parent,
 * find another driver. For now this doesn't seem
 * necesssary, so just bind the first match.
 */
-   ret = device_bind(parent, drv, drv->name, NULL, -1,
- );
+   ret = device_bind_ofnode(parent, drv, drv->name, NULL,
+node, );
if (ret)
goto error;
debug("%s: Match found: %s\n", __func__, drv->name);
@@ -651,9 +681,10 @@ int usb_scan_device(struct udevice *parent, int port,
if (ret) {
if (ret != -ENOENT)
return ret;
-   ret = usb_find_and_bind_driver(parent, >descriptor, iface,
+   ret = usb_find_and_bind_driver(parent, >descriptor,
+  iface,
   udev->controller_dev->seq,
-  udev->devnum, );
+  udev->devnum, port, );
if (ret)
return ret;
created = true;
-- 
2.20.1

[PATCH v5 2/2] dm: uclass: don't assign aliased seq numbers

[Michael Walle]

If there are aliases for an uclass, set the base for the "dynamically"
allocated numbers next to the highest alias.

Please note, that this might lead to holes in the sequences, depending
on the device tree. For example if there is only an alias "ethernet1",
the next device seq number would be 2.

In particular this fixes a problem with boards which are using ethernet
aliases but also might have network add-in cards like the E1000. If the
board is started with the add-in card and depending on the order of the
drivers, the E1000 might occupy the first ethernet device and mess up
all the hardware addresses, because the devices are now shifted by one.

Also adapt the test cases to the new handling and add test cases
checking the holes in the seq numbers.

Signed-off-by: Michael Walle 
Reviewed-by: Alex Marginean 
Tested-by: Alex Marginean 
Acked-by: Vladimir Oltean 
Reviewed-by: Simon Glass 
Tested-by: Michal Simek  [on zcu102-revA]
---
 arch/sandbox/dts/test.dts |  4 ++--
 drivers/core/uclass.c | 21 +++--
 include/configs/sandbox.h |  6 +++---
 test/dm/eth.c | 14 +++---
 test/dm/test-fdt.c| 22 +-
 5 files changed, 44 insertions(+), 23 deletions(-)

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 5ce5e28476..37dbd86017 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -23,8 +23,8 @@
pci0 = 
pci1 = 
pci2 = 
-   remoteproc1 = _1;
-   remoteproc2 = _2;
+   remoteproc0 = _1;
+   remoteproc1 = _2;
rtc0 = _0;
rtc1 = _1;
spi0 = "/spi@0";
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 2ab419cfe4..c3f1b73cd6 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -689,13 +689,14 @@ int uclass_unbind_device(struct udevice *dev)
 
 int uclass_resolve_seq(struct udevice *dev)
 {
+   struct uclass *uc = dev->uclass;
+   struct uclass_driver *uc_drv = uc->uc_drv;
struct udevice *dup;
-   int seq;
+   int seq = 0;
int ret;
 
assert(dev->seq == -1);
-   ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, dev->req_seq,
-   false, );
+   ret = uclass_find_device_by_seq(uc_drv->id, dev->req_seq, false, );
if (!ret) {
dm_warn("Device '%s': seq %d is in use by '%s'\n",
dev->name, dev->req_seq, dup->name);
@@ -707,9 +708,17 @@ int uclass_resolve_seq(struct udevice *dev)
return ret;
}
 
-   for (seq = 0; seq < DM_MAX_SEQ; seq++) {
-   ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, seq,
-   false, );
+   if (CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_SEQ_ALIAS) &&
+   (uc_drv->flags & DM_UC_FLAG_SEQ_ALIAS)) {
+   /*
+* dev_read_alias_highest_id() will return -1 if there no
+* alias. Thus we can always add one.
+*/
+   seq = dev_read_alias_highest_id(uc_drv->name) + 1;
+   }
+
+   for (; seq < DM_MAX_SEQ; seq++) {
+   ret = uclass_find_device_by_seq(uc_drv->id, seq, false, );
if (ret == -ENODEV)
break;
if (ret)
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 7fda63f71a..4549c81169 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -95,9 +95,9 @@
 #endif
 
 #define SANDBOX_ETH_SETTINGS   "ethaddr=00:00:11:22:33:44\0" \
-   "eth1addr=00:00:11:22:33:45\0" \
-   "eth3addr=00:00:11:22:33:46\0" \
-   "eth5addr=00:00:11:22:33:47\0" \
+   "eth3addr=00:00:11:22:33:45\0" \
+   "eth5addr=00:00:11:22:33:46\0" \
+   "eth6addr=00:00:11:22:33:47\0" \
"ipaddr=1.2.3.4\0"
 
 #define MEM_LAYOUT_ENV_SETTINGS \
diff --git a/test/dm/eth.c b/test/dm/eth.c
index 1fddcaabb0..b58c9640a2 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -48,7 +48,7 @@ static int dm_test_eth_alias(struct unit_test_state *uts)
ut_assertok(net_loop(PING));
ut_asserteq_str("eth@10002000", env_get("ethact"));
 
-   env_set("ethact", "eth1");
+   env_set("ethact", "eth6");
ut_assertok(net_loop(PING));
ut_asserteq_str("eth@10004000", env_get("ethact"));
 
@@ -105,7 +105,7 @@ static int dm_test_eth_act(struct unit_test_state *uts)
const char *ethname[DM_TEST_ETH_NUM] = {"eth@10002000", "eth@10003000",
"sbe5", "eth@10004000"};
const char *addrname[DM_TEST_ETH_NUM] = {"ethaddr", "eth5addr",
- 

Re: patman: ImportError

[Stefan Bosch]

Hi Simon,

Am 20.05.20 um 02:52 schrieb Simon Glass:

Hi Stefan,

On Sun, 17 May 2020 at 07:54, Stefan Bosch  wrote:


Hi Simon,

Am 17.05.20 um 01:03 schrieb Simon Glass:

Hi Stefan,

On Sat, 16 May 2020 at 05:27, Stefan Bosch  wrote:


Hello,

recently, I updated my local repository (U-Boot master). Last commit is
c693f212c5b0433b3a49a89d87cbff28bf78eb87 now. Previously it has been
4df3578119b043d76b86b50077b06898fc2a4f62 (Date:   Wed Dec 18 18:25:42
2019 +0100).

Now I get an "ImportError" if I call patman:

u-boot_master$ ./tools/patman/patman --help
Traceback (most recent call last):
 File "./tools/patman/patman", line 21, in 
   from patman import checkpatch
 File
"/home/stefan/u-boot_master/tools/patman/../patman/checkpatch.py", line
10, in 
   from patman import command
 File "/home/stefan/u-boot_master/tools/patman/../patman/command.py",
line 8, in 
   from patman import tools
 File "/home/stefan/u-boot_master/tools/patman/../patman/tools.py",
line 13, in 
   from patman import command
ImportError: cannot import name 'command'

Cause of this 'ImportError' is probably that "from patman import
command" has already been done before in checkpatch.py (circular
dependency). I think the error has to do with your your commit
bf776679a73f3b9eae37aabd2be5754483039cb2 (patman: Move to absolute imports).

My Python version is 3.4.3.


The circular dependency has been there for some time, but perhaps in
Python 2, not Python 3. My Python is 3.6.9 or 3.7.7.

I sent a patch to break the circular dependency. Can you please try it
and see if it helps?

Regards,
Simon



Thanks for your quick reply. I tried your patch, the good news is that
the ImportError for 'command' has been gone. The bad news is that the
same occurs for 'checkpatch' now:

$ ./tools/patman/patman --help
Traceback (most recent call last):
File "./tools/patman/patman", line 21, in 
  from patman import checkpatch
File
"/home/stefan/u-boot_master/tools/patman/../patman/checkpatch.py", line
11, in 
  from patman import gitutil
File "/home/stefan/u-boot_master/tools/patman/../patman/gitutil.py",
line 10, in 
  from patman import checkpatch
ImportError: cannot import name 'checkpatch'


OK I will try a new patch.

Which distribution are you using?

Regards,
Simon



I am using Ubuntu 14.04 (Kernel "3.13.0-170-generic").

Thanks for the new patch. Unfortunately I get the following ImportError now:

$ ./tools/patman/patman --help
Traceback (most recent call last):
  File "./tools/patman/patman", line 21, in 
from patman import checkpatch
  File 
"/home/stefan/u-boot_master/tools/patman/../patman/checkpatch.py", line 
11, in 

from patman import gitutil
  File "/home/stefan/u-boot_master/tools/patman/../patman/gitutil.py", 
line 12, in 

from patman import series
  File "/home/stefan/u-boot_master/tools/patman/../patman/series.py", 
line 8, in 

from patman import get_maintainer
  File 
"/home/stefan/u-boot_master/tools/patman/../patman/get_maintainer.py", 
line 8, in 

from patman import gitutil
ImportError: cannot import name 'gitutil'

Regards
Stefan

Re: Regression when building with DEVICE_TREE parameter

[Masahiro Yamada]

On Wed, May 20, 2020 at 10:50 PM Patrice CHOTARD  wrote:
>
> Hi Masahiro
>
> As indicated into doc/README.fdt-control, it's possible build U-boot with 
> specifying dts-file-name using
> $ make DEVICE_TREE=


I think this doc might be misleading.

The intended usage is like this.


If you see arch/arm/dts/Makefile,
each platform typically has multiple DTBs.


dtb-$(CONFIG_ARCH_FOO) +=  \
   foo-board1.dtb \
   foo-board2.dtb \
   foo-board3.dtb


When you build for CONFIG_ARCH_FOO,
all of the three are compiled,
but U-Boot needs to pick one to bind.

If you have
CONFIG_DEFAULT_DEVICE_TREE=foo-board1.dtb
in the configuration, foo-board1.dtb is
appended to the final u-boot binary.


If you want to choose a different DTB,
you can also do  "make DEVICE_TREE=foo-board2.dtb"
from the command line, but it must be chosen
from the DTBs added to dtb-y.


DEVICE_TREE=foo-board4.dtb just fails because
there is no dtb-y entry for that.




> But since your commit a3444bd09af9 ("Revert "Ensure device tree DTS is 
> compiled") it's no more possible:

Right.
Before a3444bd09af9, you was able to build whichever
device tree without having the correct entry to Makefile.

As 89c2b5c02049aea pointed out, people really did not care
(or even notice) whether arch/arm/dts/Makefile is correct or not.


That was why DEVICE_TREE=trial was previously working.



> make ARCH=arm CROSS_COMPILE=$CROSS_COMPILE -j 16 DEVICE_TREE="trial"
>
> Device Tree Source is not correctly specified.
> Please define 'CONFIG_DEFAULT_DEVICE_TREE'
> or build with 'DEVICE_TREE=' argument
>
> dts/Makefile:28: recipe for target 'arch/arm/dts/trial.dtb' failed
> make[1]: *** [arch/arm/dts/trial.dtb] Error 1
> Makefile:1087: recipe for target 'dts/dt.dtb' failed


This is because there is no entry for trial.dtb
in arch/arm/dts/Makefile.


You need to add "dtb-y += trial.dtb"
to arch/arm/dts/Makefile.




Please let me know what you want to do.

Your device tree is not upstreamed.
You want to drop it in the tree,
and build it without modifying the source tree.
Is this correct?

The current U-Boot cannot do that.

Each device tree needs to be wired up
to arch//dts/Makefile.


I know a counter approach was proposed in the past.

See this patch:
http://patchwork.ozlabs.org/project/uboot/patch/1451223875-20914-3-git-send-email-tho...@wytron.com.tw/

It stops maintaining arch//dts/Makefile,
then people can set CONFIG_DEFAULT_DEVICE_TREE
to compile whatever device tree.
I think it was one idea, but not adopted.



If you want to separate your DT from
upstream code, EXT_DTB might be used
to append externally built DTB.

See these commits:

63b4b5bae52e48528876e13e858ef934ac2e4a3b
d18926af30d111362c6262c356feb768d7a367a3






> make: *** [dts/dt.dtb] Error 2
>
> By reverting the above patch, it's restoring the attended behavior. But In 
> your commit you indicated several issues.
>
> Unfortunately, i am not a Makefile "expert", can anybody have a look at it ?
>
> Thanks
>
> Patrice










-- 
Best Regards
Masahiro Yamada

Re: [PATCH v1 2/3] board: ns3: add FIT image its file

[Pramod Kumar]

Hi Thomas,

This is generic and used for development. Specific keys will be used by
Customer/Specific applications.

Regards,
Pramod

On Wed, May 20, 2020 at 7:25 AM Thomas Fitzsimmons 
wrote:

> Hi Rayagonda and Pramod,
>
> Rayagonda Kokatanur  writes:
>
> > From: Pramod Kumar 
> >
> > Add FIT image its file.
>
> The .its file and dev keys seem generic.  Are you intending to add to
> the .its file subsequently, e.g., to demonstrate FIT usage unique to the
> NS3?
>
> Thomas
>

Re: [PATCH 3/6] ARM: uniphier: drop #include again from umc-pxs2.c

[Simon Glass]

On Tue, 19 May 2020 at 21:32, Masahiro Yamada
 wrote:
>
> I do not understand the change made to this file by
> commit 691d719db718 ("common: Drop init.h from common header").
>
>   git show 691d719db718 -- arch/arm/mach-uniphier/dram/umc-pxs2.c
>
> This file does not call or define any functions declared in 
>
> Simply revert the change made to this file.
>
> Signed-off-by: Masahiro Yamada 
> ---
>
>  arch/arm/mach-uniphier/dram/umc-pxs2.c | 1 -
>  1 file changed, 1 deletion(-)
>

Reviewed-by: Simon Glass 

RE: [PATCH v11 15/18] sifive: fu540: Add sample SD gpt partition layout

[Pragnesh Patel]

Hi Bin/Jagan,

>-Original Message-
>From: Bin Meng 
>Sent: 20 May 2020 19:30
>To: Pragnesh Patel 
>Cc: U-Boot Mailing List ; Atish Patra
>; Palmer Dabbelt ; Paul
>Walmsley ; Jagan Teki
>; Anup Patel ; Sagar
>Kadam ; Rick Chen ; Palmer
>Dabbelt 
>Subject: Re: [PATCH v11 15/18] sifive: fu540: Add sample SD gpt partition
>layout
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh,
>
>On Tue, May 19, 2020 at 3:05 PM Pragnesh Patel
> wrote:
>>
>> From: Jagan Teki 
>>
>> This is a sample GPT partition layout for SD card, right now three
>> important partitions are added to make the system bootable.
>>
>> partition layout:
>>
>> PartStart LBA   End LBA Name
>> Attributes
>> Type GUID
>> Partition GUID
>>   1 0x0022  0x0821  "loader1"
>> attrs:  0x
>> type:   5b193300-fc78-40cd-8002-e86c45580b47
>> guid:   cbcbef44-e627-42bc-b134-93b6f3784b8c
>>   2 0x0822  0x2821  "loader2"
>> attrs:  0x
>> type:   2e54b353-1271-4842-806f-e436d6af6985
>> guid:   f54eba28-d8de-4852-978d-1a673777e2ae
>>   3 0x2822  0x00020821  "rootfs"
>> attrs:  0x0004
>> type:   0fc63daf-8483-4772-8e79-3d69d8477de4
>> type:   linux
>> guid:   9561df46-8d55-4799-a83b-cfee9ef6ff93
>>
>> Note:
>> - loader1 would be fsbl or spl
>> - loader2 would be U-Boot or U-Boot proper
>>
>> Signed-off-by: Jagan Teki 
>> Reviewed-by: Bin Meng 
>> Reviewed-by: Pragnesh Patel 
>> ---
>>  board/sifive/fu540/Kconfig |  2 ++
>>  include/configs/sifive-fu540.h | 13 +
>>  2 files changed, 15 insertions(+)
>>
>
>I see Jagan posted patches for SPI flash booting, and the layout is different
>from MMC.
>
>Can we use the same layout here, ie: by reserving spaces for the U-Boot
>environment on MMC?
>
>See
>http://patchwork.ozlabs.org/project/uboot/patch/20200519192340.16624-7-
>ja...@amarulasolutions.com/
>
>0 - 34 : reserved for GPT header
>   35 - 39 : unused
>   40 - 2087 : loader1 (SPL, FSBL)
> 2088 - 10279 : loader2 (U-Boot proper, U-Boot)
>10280 - 10535 : environment
>10536 - 65494 : rootfs
>65528 - 65536 : distro script

I am okay with this. @Jagan Teki do you have any comment on this ?

>
>
>REgards,
>Bin

Re: [PATCH 5/6] ARM: uniphier: delete or replace includes

[Simon Glass]

On Tue, 19 May 2020 at 21:32, Masahiro Yamada
 wrote:
>
>  pulls in a lot of bloat.  is unneeded in most of
> places.
>
> Signed-off-by: Masahiro Yamada 
> ---
>
>  arch/arm/mach-uniphier/arm32/cache-uniphier.c | 1 -
>  arch/arm/mach-uniphier/arm32/psci.c   | 1 -
>  arch/arm/mach-uniphier/arm32/timer.c  | 2 +-
>  arch/arm/mach-uniphier/arm64/mem_map.c| 1 -
>  arch/arm/mach-uniphier/base-address.c | 2 +-
>  arch/arm/mach-uniphier/board_late_init.c  | 1 -
>  arch/arm/mach-uniphier/boards.c   | 2 +-
>  arch/arm/mach-uniphier/boot-device/boot-device-ld11.c | 1 -
>  arch/arm/mach-uniphier/boot-device/boot-device-ld4.c  | 1 -
>  arch/arm/mach-uniphier/boot-device/boot-device-pro5.c | 1 -
>  arch/arm/mach-uniphier/boot-device/boot-device-pxs2.c | 1 -
>  arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c | 1 -
>  arch/arm/mach-uniphier/boot-device/boot-device.c  | 2 +-
>  arch/arm/mach-uniphier/clk/clk-dram-ld4.c | 1 -
>  arch/arm/mach-uniphier/clk/clk-dram-pxs2.c| 1 -
>  arch/arm/mach-uniphier/clk/clk-early-ld4.c| 1 -
>  arch/arm/mach-uniphier/clk/clk-ld11.c | 1 -
>  arch/arm/mach-uniphier/clk/dpll-ld4.c | 1 -
>  arch/arm/mach-uniphier/clk/dpll-pro4.c| 1 -
>  arch/arm/mach-uniphier/debug-uart/debug-uart.c| 1 -
>  arch/arm/mach-uniphier/dram/cmd_ddrmphy.c | 1 -
>  arch/arm/mach-uniphier/dram/cmd_ddrphy.c  | 1 -
>  arch/arm/mach-uniphier/dram/umc-ld4.c | 1 -
>  arch/arm/mach-uniphier/dram/umc-pro4.c| 1 -
>  arch/arm/mach-uniphier/dram/umc-sld8.c| 1 -
>  arch/arm/mach-uniphier/dram_init.c| 2 +-
>  arch/arm/mach-uniphier/fdt-fixup.c| 2 +-
>  arch/arm/mach-uniphier/memconf.c  | 1 -
>  arch/arm/mach-uniphier/micro-support-card.c   | 3 ++-
>  arch/arm/mach-uniphier/mmc-boot-mode.c| 1 -
>  arch/arm/mach-uniphier/mmc-first-dev.c| 1 -
>  arch/arm/mach-uniphier/pinctrl-glue.c | 1 -
>  arch/arm/mach-uniphier/reset.c| 1 -
>  arch/arm/mach-uniphier/sbc/sbc-ld11.c | 1 -
>  arch/arm/mach-uniphier/sbc/sbc.c  | 1 -
>  arch/arm/mach-uniphier/spl_board_init.c   | 1 -
>  36 files changed, 8 insertions(+), 36 deletions(-)
>

Reviewed-by: Simon Glass 

Actually common.h is a lot better than it was.

Three years ago it was just over 1000 lines. lz4_wapper.c produced
5630 of pre-processed C. Now it is about 4000 and the list of
dependencies is 72 lines instead of 91.

Yes common.h is still a problem, but I think we need to look at other
headers also. For example, global_data.h includes fdtdec.h for one
type, which includes lots of things. There are quite a few other
headers that pull in too much stuff.

Do you know of a good way to measure this stuff automatically?

Regards,
Simon

Re: [PATCH 4/6] ARM: uniphier: drop #include again

[Simon Glass]

Hi Masahiro,

On Tue, 19 May 2020 at 21:32, Masahiro Yamada
 wrote:
>
> I do not understand the changes made to these files by
> commit f7ae49fc4f36 ("common: Drop log.h from common header").
>
>   git show f7ae49fc4f36 -- arch/arm/mach-uniphier/
>
> None of them uses the log function feature.
>
> Simply revert the changes made to these files.
>
> Signed-off-by: Masahiro Yamada 
> ---
>
>  arch/arm/mach-uniphier/board_init.c   | 1 -
>  arch/arm/mach-uniphier/dram/ddrphy-training.c | 1 -
>  arch/arm/mach-uniphier/dram/umc-pxs2.c| 1 -
>  arch/arm/mach-uniphier/micro-support-card.c   | 1 -
>  arch/arm/mach-uniphier/nand-reset.c   | 1 -
>  5 files changed, 5 deletions(-)
>

Reviewed-by: Simon Glass 

Uniphier is very unusual in that it doesn't include common.h in quite
a few files. I hope by the next time we get to RC2 common.h will be
empty apart from config.h.

Regards,
Simon

Re: [PATCH 2/2] fdtdec: Honor #address-cells and #size-cells in fdtdec_add_reserved_memory()

[Simon Glass]

Hi Bin,

On Wed, 20 May 2020 at 00:38, Bin Meng  wrote:
>
> From: Bin Meng 
>
> At present fdtdec_add_reserved_memory() calls fdtdec_get_addr_size()
> to get address and size for the subnodes of /reserved-memory node.
>
> We should honor #address-cells and #size-cells properties in the
> parent node.
>
> Signed-off-by: Bin Meng 
> ---
>
>  lib/fdtdec.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Simon Glass 

Are there no tests for this?

Re: [PATCH 1/6] ARM: uniphier: include instead of from psci.c

[Simon Glass]

Hi Masahiro,

On Tue, 19 May 2020 at 21:32, Masahiro Yamada
 wrote:
>
> I do not understand the change made to this file by
> commit 90526e9fbac4 ("common: Drop net.h from common header").
>
>   git show 90526e9fbac4 -- arch/arm/mach-uniphier/arm32/psci.c
>
> It added  while this file does not call the standard cache
> functions at all.
>
> All the uniphier-specific cache functions, uniphier_cache_*() are
> declared in cache-uniphier.h, which is already included from this file.
>
> Including  is sensible to fix the -Wmissing-prototypes
> warnings because this file defines psci_cpu_on and psci_system_reset().
>
> Signed-off-by: Masahiro Yamada 
> ---
>
>  arch/arm/mach-uniphier/arm32/psci.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

I suspect it is a limitation of my scripting, which is not perfect. It
should rely more on ctags, etc. than grep/

Reviewed-by: Simon Glass 

Regards,
Simon

Re: [PATCH v1 00/15] add basic driver support for broadcom NS3 soc

[Simon Glass]

Hi Rayagonda,

On Tue, 19 May 2020 at 23:19, Rayagonda Kokatanur
 wrote:
>
> Hi Thomas,
>
> On Wed, May 20, 2020 at 7:34 AM Thomas Fitzsimmons  
> wrote:
> >
> > Rayagonda Kokatanur  writes:
> >
> > > On Tue, May 19, 2020 at 11:01 PM Tom Rini  wrote:
> > >>
> > >> On Tue, May 19, 2020 at 10:39:49PM +0530, Rayagonda Kokatanur wrote:
> > >> > Hi Tom,
> > >> >
> > >> >
> > >> > On Tue, May 19, 2020 at 12:46 AM Tom Rini  wrote:
> > >> > >
> > >> > > On Sun, May 17, 2020 at 01:49:30PM +0530, Rayagonda Kokatanur wrote:
> > >> > >
> > >> > > > This is the second patch set series prepared on top of the
> > >> > > > first patch set ("add initial support for broadcom NS3 soc").
> > >> > > >
> > >> > > > This patch set will add following,
> > >> > > > -dt nodes and defconfig options for basic device like pinctrl,
> > >> > > >  gpio, mmc, qspi, wdt, i2c and pcie.
> > >> > > > -start wdt service
> > >> > > > -Enable GPT commands
> > >> > > > -Enable EXT4 and FAT fs support
> > >> > >
> > >> > > All of the dts changes not in a -u-boot.dtsi file either come from
> > >> > > mainline Linux or at least linux-next and have had some level 
> > >> > > upstream
> > >> > > review, right?  Thanks!
> > >> >
> > >> > Yes. All the DTS changes are merged in the Linux and are available at
> > >> > arch/arm64/boot/dts/broadcom/stingray/
> > >>
> > >> Great.  Please reference the release you're taking these from as that
> > >> will make future resyncs easier.  Thanks!
> > >
> > > It's Linux v5.6.
> >
> > What's the relationship between e.g., bcm958742t.dts and ns3.dts?  I
> > looked at the mainline Linux device trees and I couldn't easily see the
> > correspondence.  Will the renaming complicate synchronization?
>
> Do we need to maintain the same dt file between linux and uboot ?
> Also in uboot we don't enable all devices,  how do we handle this ?

If there is no U-Boot driver for a particular node then it will be
ignored. It is easier to keep them in sync if they are the same in
U-Boot and Linux.

> Please let me know.

That is implied by your question above :-)

Regards,
SImon

Re: [PATCH 1/2] fdtdec: Fix the types of addr and size in fdtdec_add_reserved_memory()

[Simon Glass]

On Wed, 20 May 2020 at 00:38, Bin Meng  wrote:
>
> From: Bin Meng 
>
> fdtdec_get_addr_size() expects size is of type 'fdt_size_t', and
> return value is of type 'fdt_addr_t'. Adjust their types accordingly.
>
> Signed-off-by: Bin Meng 
> ---
>
>  lib/fdtdec.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Simon Glass 

Re: Warnings on Edison

[Andy Shevchenko]

On Wed, May 20, 2020 at 09:35:34AM -0400, Tom Rini wrote:

...

> as Edison still works.

I believe no-one who is building it from sources for Edison uses that old
ACPICA tools.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v2 1/9] spl: Try to get SPL boot device via board_get_int

[Tom Rini]

On Wed, May 20, 2020 at 06:46:55PM +0530, Jagan Teki wrote:
> On Wed, May 20, 2020 at 6:32 PM Tom Rini  wrote:
> >
> > On Wed, May 20, 2020 at 12:53:32AM +0530, Jagan Teki wrote:
> >
> > > Usually, the associated board would supply spl boot device
> > > using spl_boot_device() but some boards have board driver
> > > that are possible to supply boot device via board_get_int
> > > with BOARD_SPL_BOOT_DEVICE id.
> > >
> > > This patch add support for those.
> > >
> > > Cc: Mario Six 
> > > Cc: Tom Rini 
> > > Cc: Simon Glass 
> > > Cc: Jean-Jacques Hiblot 
> > > Signed-off-by: Jagan Teki 
> > > ---
> > > Changes for v2:
> > > - new patch
> > >
> > >  common/spl/spl.c | 14 +-
> > >  include/board.h  |  9 +
> > >  2 files changed, 22 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/common/spl/spl.c b/common/spl/spl.c
> > > index fc5cbbbeba..a07b71b3c1 100644
> > > --- a/common/spl/spl.c
> > > +++ b/common/spl/spl.c
> > > @@ -9,6 +9,7 @@
> > >  #include 
> > >  #include 
> > >  #include 
> > > +#include 
> > >  #include 
> > >  #include 
> > >  #include 
> > > @@ -483,9 +484,20 @@ int spl_init(void)
> > >  #define BOOT_DEVICE_NONE 0xdeadbeef
> > >  #endif
> > >
> > > +__weak u32 spl_boot_device(void)
> > > +{
> > > + return 0;
> > > +}
> > > +
> > >  __weak void board_boot_order(u32 *spl_boot_list)
> > >  {
> > > - spl_boot_list[0] = spl_boot_device();
> > > + struct udevice *board;
> > > +
> > > + if (!board_get())
> > > + board_get_int(board, BOARD_SPL_BOOT_DEVICE,
> > > +   (int *)_boot_list[0]);
> > > + else
> > > + spl_boot_list[0] = spl_boot_device();
> > >  }
> > >
> > >  static struct spl_image_loader *spl_ll_find_loader(uint boot_device)
> > > diff --git a/include/board.h b/include/board.h
> > > index 678b652b0a..ce4eaba38d 100644
> > > --- a/include/board.h
> > > +++ b/include/board.h
> > > @@ -211,3 +211,12 @@ static inline int board_get_fit_loadable(struct 
> > > udevice *dev, int index,
> > >  }
> > >
> > >  #endif
> > > +
> > > +/**
> > > + * Common board unique identifier
> > > + *
> > > + * @BOARD_SPL_BOOT_DEVICE:   id to get SPL boot device.
> > > + */
> > > +enum common_ids {
> > > + BOARD_SPL_BOOT_DEVICE,
> > > +};
> >
> > I don't understand why we need this abstraction.  The intention of what
> > we have today is that the generic SPL framework calls out to something
> > to ask "what are we booted from?".  Why can the board driver not just
> > supply that information?  Thanks!
> 
> Yes, we can update boot-device on respective areas by probing board
> driver and assign spl_boot_list[0] by explicitly define
> spl_boot_device function, but this change bypass all these codes. Just
> like how we did on SPL fit to load the concerned image via board
> driver.

I still don't get it, sorry.  Why is spl_boot_device() not provided by
the "board" driver to say what to boot in this case?

-- 
Tom


signature.asc
Description: PGP signature

Re: [PATCH v11 15/18] sifive: fu540: Add sample SD gpt partition layout

[Bin Meng]

Hi Pragnesh,

On Tue, May 19, 2020 at 3:05 PM Pragnesh Patel
 wrote:
>
> From: Jagan Teki 
>
> This is a sample GPT partition layout for SD card,
> right now three important partitions are added to
> make the system bootable.
>
> partition layout:
>
> PartStart LBA   End LBA Name
> Attributes
> Type GUID
> Partition GUID
>   1 0x0022  0x0821  "loader1"
> attrs:  0x
> type:   5b193300-fc78-40cd-8002-e86c45580b47
> guid:   cbcbef44-e627-42bc-b134-93b6f3784b8c
>   2 0x0822  0x2821  "loader2"
> attrs:  0x
> type:   2e54b353-1271-4842-806f-e436d6af6985
> guid:   f54eba28-d8de-4852-978d-1a673777e2ae
>   3 0x2822  0x00020821  "rootfs"
> attrs:  0x0004
> type:   0fc63daf-8483-4772-8e79-3d69d8477de4
> type:   linux
> guid:   9561df46-8d55-4799-a83b-cfee9ef6ff93
>
> Note:
> - loader1 would be fsbl or spl
> - loader2 would be U-Boot or U-Boot proper
>
> Signed-off-by: Jagan Teki 
> Reviewed-by: Bin Meng 
> Reviewed-by: Pragnesh Patel 
> ---
>  board/sifive/fu540/Kconfig |  2 ++
>  include/configs/sifive-fu540.h | 13 +
>  2 files changed, 15 insertions(+)
>

I see Jagan posted patches for SPI flash booting, and the layout is
different from MMC.

Can we use the same layout here, ie: by reserving spaces for the
U-Boot environment on MMC?

See 
http://patchwork.ozlabs.org/project/uboot/patch/20200519192340.16624-7-ja...@amarulasolutions.com/

0 - 34 : reserved for GPT header
   35 - 39 : unused
   40 - 2087 : loader1 (SPL, FSBL)
 2088 - 10279 : loader2 (U-Boot proper, U-Boot)
10280 - 10535 : environment
10536 - 65494 : rootfs
65528 - 65536 : distro script


REgards,
Bin

RE: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL

[Pragnesh Patel]

Hi Bin,

>-Original Message-
>From: Bin Meng 
>Sent: 20 May 2020 19:15
>To: Pragnesh Patel 
>Cc: Rick Chen ; Jagan Teki
>; Sean Anderson ; U-
>Boot Mailing List ; rick ; Alan
>Kao 
>Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh,
>
>On Wed, May 20, 2020 at 7:52 PM Pragnesh Patel
> wrote:
>>
>> Hi Bin,
>>
>> >-Original Message-
>> >From: Bin Meng 
>> >Sent: 20 May 2020 15:54
>> >To: Pragnesh Patel 
>> >Cc: Rick Chen ; Jagan Teki
>> >; Sean Anderson ;
>U-
>> >Boot Mailing List ; rick ;
>> >Alan Kao 
>> >Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >Hi Pragnesh,
>> >
>> >On Wed, May 20, 2020 at 3:41 PM Pragnesh Patel
>> > wrote:
>> >>
>> >> Hi Bin,
>> >>
>> >> >-Original Message-
>> >> >From: Bin Meng 
>> >> >Sent: 20 May 2020 13:07
>> >> >To: Pragnesh Patel 
>> >> >Cc: Rick Chen ; Jagan Teki
>> >> >; Sean Anderson
>;
>> >U-
>> >> >Boot Mailing List ; rick
>> >> >; Alan Kao 
>> >> >Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
>> >> >
>> >> >[External Email] Do not click links or attachments unless you
>> >> >recognize the sender and know the content is safe
>> >> >
>> >> >"Hi Pragnesh,
>> >> >
>> >> >On Wed, May 20, 2020 at 3:29 PM Pragnesh Patel
>> >> > wrote:
>> >> >>
>> >> >>
>> >> >>
>> >> >> >-Original Message-
>> >> >> >From: Rick Chen 
>> >> >> >Sent: 20 May 2020 08:38
>> >> >> >To: Bin Meng ; Pragnesh Patel
>> >> >> >; Jagan Teki
>> >> >> >; Sean Anderson
>> >
>> >> >> >Cc: U-Boot Mailing List ; rick
>> >> >> >; Alan Kao 
>> >> >> >Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
>> >> >> >
>> >> >> >[External Email] Do not click links or attachments unless you
>> >> >> >recognize the sender and know the content is safe
>> >> >> >
>> >> >> >Hi Bin
>> >> >> >
>> >> >> >> -Original Message-
>> >> >> >> From: Bin Meng [mailto:bmeng...@gmail.com]
>> >> >> >> Sent: Tuesday, May 19, 2020 4:44 PM
>> >> >> >> To: Pragnesh Patel; Rick Jian-Zhi Chen(陳建志)
>> >> >> >> Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support
>> >> >> >> SPL
>> >> >> >>
>> >> >> >> Hi Rick,
>> >> >> >>
>> >> >> >> On Tue, May 19, 2020 at 3:04 PM Pragnesh Patel
>> >> >> > wrote:
>> >> >> >> >
>> >> >> >> > This series add support for SPL to FU540. U-Boot SPL can
>> >> >> >> > boot from
>> >> >> >> > L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC
>> >firmware)
>> >> >and
>> >> >> >> > U-Boot proper from MMC devices.
>> >> >> >> >
>> >> >> >> > This series depends on:
>> >> >> >> > [1] https://patchwork.ozlabs.org/patch/1281853
>> >> >> >> > [2] https://patchwork.ozlabs.org/patch/1281852
>> >> >> >> >
>> >> >> >> > All these together is available for testing here [3] [3]
>> >> >> >> > https://github.com/pragnesh26992/u-boot/tree/spl
>> >> >> >> >
>> >> >> >> > How to test this patch:
>> >> >> >> > 1) Go to OpenSBI-dir : make PLATFORM=generic
>FW_DYNAMIC=y
>> >> >> >> > 2) export
>> >> >> >> >
>> >> >>
>> >>
>>
OPENSBI=i
>> >c.
>> >> >> >> > bi
>> >> >> >> > n>
>> >> >> >> > 3) Change to u-boot-dir
>> >> >> >> > 4) make sifive_fu540_defconfig
>> >> >> >> > 5) make all
>> >> >> >> > 6) Format the SD card (make sure the disk has GPT,
>> >> >> >> > otherwise use gdisk to switch)
>> >> >> >> >
>> >> >> >> > # sudo sgdisk --clear \
>> >> >> >> > > --set-alignment=2 \
>> >> >> >> > > --new=1:34:2081 --change-name=1:loader1
>> >> >> >> > --typecode=1:5B193300-
>> >> >> >FC78-40CD-8002-E86C45580B47 \
>> >> >> >> > > --new=2:2082:10273 --change-name=2:loader2 --
>> >> >> >typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
>> >> >> >> > > --new=3:10274: --change-name=3:rootfs
>> >> >> >> > --typecode=3:0FC63DAF-
>> >> >> >8483-4772-8E79-3D69D8477DE4 \
>> >> >> >> > > /dev/sda
>> >> >> >> >
>> >> >> >> > 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
>> >> >> >> > 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082
>> >> >> >> >
>> >> >> >> > Changes in v11:
>> >> >> >> > - Remove TPL related code and OF_PLATDATA from FU540
>> >> >> >> >   DDR driver (drivers/ram/sifive/fu540_ddr.c)
>> >> >> >> > - Update FU540 doc (doc/board/sifive/fu540.rst)
>> >> >> >> >   Remove unnecessary print
>> >> >> >>
>> >> >> >> Could we get this v11 applied as soon as possible for v2020.07?
>> >> >> >
>> >> >> >No problem, if everything is OK, I will applied ASAP.
>> >> >> >But Jagan seem have some responses, please check about it.
>> >> >> >
>> >> >> >>
>> >> >> >> > This series depends on:
>> >> >> >> > [1] https://patchwork.ozlabs.org/patch/1281853
>> >> >> >> > [2] https://patchwork.ozlabs.org/patch/1281852
>> >> >>
>> >> >> With " assigned-clocks" and " assigned-clock-rates" for cpus,
>> >> >> this
>> >> >> FU540 SPL series is no more 

RE: [PATCH v10 17/18] configs: fu540: Add config options for U-Boot SPL

[Pragnesh Patel]

Hi Bin,

>-Original Message-
>From: Bin Meng 
>Sent: 20 May 2020 19:14
>To: Pragnesh Patel 
>Cc: Jagan Teki ; U-Boot-Denx b...@lists.denx.de>; Atish Patra ; Palmer Dabbelt
>; Paul Walmsley ;
>Anup Patel ; Sagar Kadam
>; Rick Chen ; Palmer
>Dabbelt 
>Subject: Re: [PATCH v10 17/18] configs: fu540: Add config options for U-Boot
>SPL
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh,
>
>On Wed, May 20, 2020 at 9:33 PM Pragnesh Patel
> wrote:
>>
>> Hi Jagan,
>>
>> >-Original Message-
>> >From: U-Boot  On Behalf Of Pragnesh
>> >Patel
>> >Sent: 20 May 2020 12:55
>> >To: Bin Meng ; Jagan Teki
>> >
>> >Cc: U-Boot-Denx ; Atish Patra
>> >; Palmer Dabbelt ;
>> >Paul Walmsley ; Anup Patel
>> >; Sagar Kadam ; Rick
>Chen
>> >; Palmer Dabbelt 
>> >Subject: RE: [PATCH v10 17/18] configs: fu540: Add config options for
>> >U-Boot SPL
>> >
>> >Hi Jagan,
>> >
>> >>-Original Message-
>> >>From: Bin Meng 
>> >>Sent: 20 May 2020 10:07
>> >>To: Jagan Teki 
>> >>Cc: Pragnesh Patel ; U-Boot-Denx > >>b...@lists.denx.de>; Atish Patra ; Palmer
>> >>Dabbelt ; Paul Walmsley
>> >;
>> >>Anup Patel ; Sagar Kadam
>> >;
>> >>Rick Chen ; Palmer Dabbelt
>
>> >>Subject: Re: [PATCH v10 17/18] configs: fu540: Add config options
>> >>for U-Boot SPL
>> >>
>> >>[External Email] Do not click links or attachments unless you
>> >>recognize the sender and know the content is safe
>> >>
>> >>Hi Jagan,
>> >>
>> >>On Wed, May 20, 2020 at 12:11 AM Jagan Teki
>> >>
>> >>wrote:
>> >>>
>> >>> On Sat, May 16, 2020 at 11:42 AM Pragnesh Patel
>> >>>  wrote:
>> >>> >
>> >>> > Hi Jagan,
>> >>> >
>> >>> > >-Original Message-
>> >>> > >From: Jagan Teki 
>> >>> > >Sent: 15 May 2020 23:05
>> >>> > >To: Pragnesh Patel 
>> >>> > >Cc: U-Boot-Denx ; Atish Patra
>> >>> > >; Palmer Dabbelt
>> >>;
>> >>> > >Bin Meng ; Paul Walmsley
>> >>> > >; Anup Patel ;
>> >Sagar
>> >>> > >Kadam ; Rick Chen
>;
>> >>> > >Palmer Dabbelt 
>> >>> > >Subject: Re: [PATCH v10 17/18] configs: fu540: Add config
>> >>> > >options for U-Boot SPL
>> >>> > >
>> >>> > >[External Email] Do not click links or attachments unless you
>> >>> > >recognize the sender and know the content is safe
>> >>> > >
>> >>> > >On Thu, May 14, 2020 at 5:24 PM Pragnesh Patel
>> >>> > > wrote:
>> >>> > >>
>> >>> > >> With sifive_fu540_defconfig:
>> >>> > >>
>> >>> > >> User can use FSBL or u-boot-spl.bin anyone at a time.
>> >>> > >>
>> >>> > >> For FSBL,
>> >>> > >> fsbl->fw_payload.bin (opensbi + U-Boot)
>> >>> > >>
>> >>> > >> For u-boot-spl.bin,
>> >>> > >> u-boot-spl.bin->FIT image (opensbi + U-Boot proper + dtb)
>> >>> > >>
>> >>> > >> U-Boot SPL will be loaded by ZSBL from SD card (replace
>> >>> > >> fsbl.bin with
>> >>> > >> u-boot-spl.bin) and runs in L2 LIM in machine mode and then
>> >>> > >> load FIT image u-boot.itb from SD card into RAM.
>> >>> > >>
>> >>> > >> U-Boot SPL expects u-boot.itb FIT image at the starting of SD
>> >>> > >> card sector number (0x822) of GUID type
>> >>> > >> "2E54B353-1271-4842-806F-
>> >>> > >E436D6AF6985"
>> >>> > >>
>> >>> > >> Signed-off-by: Pragnesh Patel 
>> >>> > >> Signed-off-by: Jagan Teki 
>> >>> > >> Reviewed-by: Jagan Teki 
>> >>> > >> ---
>> >>> > >>  configs/sifive_fu540_defconfig |   8 ++
>> >>> > >>  doc/board/sifive/fu540.rst | 134
>> >>+
>> >>> > >>  2 files changed, 142 insertions(+)
>> >>> > >>
>> >>> > >> diff --git a/configs/sifive_fu540_defconfig
>> >>> > >> b/configs/sifive_fu540_defconfig index f805aacc7a..8d412f8d6a
>> >>> > >> 100644
>> >>> > >> --- a/configs/sifive_fu540_defconfig
>> >>> > >> +++ b/configs/sifive_fu540_defconfig
>> >>> > >> @@ -1,6 +1,11 @@
>> >>> > >>  CONFIG_RISCV=y
>> >>> > >> +CONFIG_SPL_GPIO_SUPPORT=y
>> >>> > >> +CONFIG_SYS_MALLOC_F_LEN=0x3000
>> >>> > >>  CONFIG_ENV_SIZE=0x2
>> >>> > >> +CONFIG_SPL_MMC_SUPPORT=y
>> >>> > >>  CONFIG_NR_DRAM_BANKS=1
>> >>> > >> +CONFIG_SPL=y
>> >>> > >> +CONFIG_SPL_SPI_SUPPORT=y
>> >>> > >>  CONFIG_TARGET_SIFIVE_FU540=y  CONFIG_ARCH_RV64I=y
>> >>> > >> CONFIG_RISCV_SMODE=y @@ -9,7 +14,10 @@ CONFIG_FIT=y
>> >>> > >> CONFIG_MISC_INIT_R=y  CONFIG_DISPLAY_CPUINFO=y
>> >>> > >> CONFIG_DISPLAY_BOARDINFO=y
>> >>> > >> +CONFIG_SPL_SEPARATE_BSS=y
>> >>> > >> +CONFIG_SPL_YMODEM_SUPPORT=y
>> >>> > >>  CONFIG_OF_BOARD_FIXUP=y
>> >>> > >>  CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
>> >>> > >>  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>> >>> > >> +CONFIG_SPL_CLK=y
>> >>> > >>  CONFIG_DM_MTD=y
>> >>> > >> diff --git a/doc/board/sifive/fu540.rst
>> >>> > >> b/doc/board/sifive/fu540.rst index 610ba87074..89e8d66c56
>> >>> > >> 100644
>> >>> > >> --- a/doc/board/sifive/fu540.rst
>> >>> > >> +++ b/doc/board/sifive/fu540.rst
>> >>> > >> @@ -31,6 +31,9 @@ TODO:
>> >>> > >>  stdout-path = "/soc/serial@1001:115200";
>> >>> > >> };
>> >>> > >>
>> >>> > >> +Booting from MMC using FSBL
>> >>> > >> +---
>> >>> > >> +
>> >>> > >>  Building

Regression when building with DEVICE_TREE parameter

[Patrice CHOTARD]

Hi Masahiro

As indicated into doc/README.fdt-control, it's possible build U-boot with 
specifying dts-file-name using
$ make DEVICE_TREE=
But since your commit a3444bd09af9 ("Revert "Ensure device tree DTS is 
compiled") it's no more possible:

make ARCH=arm CROSS_COMPILE=$CROSS_COMPILE -j 16 DEVICE_TREE="trial"

Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=' argument

dts/Makefile:28: recipe for target 'arch/arm/dts/trial.dtb' failed
make[1]: *** [arch/arm/dts/trial.dtb] Error 1
Makefile:1087: recipe for target 'dts/dt.dtb' failed
make: *** [dts/dt.dtb] Error 2

By reverting the above patch, it's restoring the attended behavior. But In your 
commit you indicated several issues.

Unfortunately, i am not a Makefile "expert", can anybody have a look at it ?

Thanks

Patrice

Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL

[Bin Meng]

Hi Pragnesh,

On Wed, May 20, 2020 at 7:52 PM Pragnesh Patel
 wrote:
>
> Hi Bin,
>
> >-Original Message-
> >From: Bin Meng 
> >Sent: 20 May 2020 15:54
> >To: Pragnesh Patel 
> >Cc: Rick Chen ; Jagan Teki
> >; Sean Anderson ; U-
> >Boot Mailing List ; rick ; Alan
> >Kao 
> >Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
> >
> >[External Email] Do not click links or attachments unless you recognize the
> >sender and know the content is safe
> >
> >Hi Pragnesh,
> >
> >On Wed, May 20, 2020 at 3:41 PM Pragnesh Patel
> > wrote:
> >>
> >> Hi Bin,
> >>
> >> >-Original Message-
> >> >From: Bin Meng 
> >> >Sent: 20 May 2020 13:07
> >> >To: Pragnesh Patel 
> >> >Cc: Rick Chen ; Jagan Teki
> >> >; Sean Anderson ;
> >U-
> >> >Boot Mailing List ; rick ;
> >> >Alan Kao 
> >> >Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
> >> >
> >> >[External Email] Do not click links or attachments unless you
> >> >recognize the sender and know the content is safe
> >> >
> >> >"Hi Pragnesh,
> >> >
> >> >On Wed, May 20, 2020 at 3:29 PM Pragnesh Patel
> >> > wrote:
> >> >>
> >> >>
> >> >>
> >> >> >-Original Message-
> >> >> >From: Rick Chen 
> >> >> >Sent: 20 May 2020 08:38
> >> >> >To: Bin Meng ; Pragnesh Patel
> >> >> >; Jagan Teki
> >> >> >; Sean Anderson
> >
> >> >> >Cc: U-Boot Mailing List ; rick
> >> >> >; Alan Kao 
> >> >> >Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
> >> >> >
> >> >> >[External Email] Do not click links or attachments unless you
> >> >> >recognize the sender and know the content is safe
> >> >> >
> >> >> >Hi Bin
> >> >> >
> >> >> >> -Original Message-
> >> >> >> From: Bin Meng [mailto:bmeng...@gmail.com]
> >> >> >> Sent: Tuesday, May 19, 2020 4:44 PM
> >> >> >> To: Pragnesh Patel; Rick Jian-Zhi Chen(陳建志)
> >> >> >> Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
> >> >> >>
> >> >> >> Hi Rick,
> >> >> >>
> >> >> >> On Tue, May 19, 2020 at 3:04 PM Pragnesh Patel
> >> >> > wrote:
> >> >> >> >
> >> >> >> > This series add support for SPL to FU540. U-Boot SPL can boot
> >> >> >> > from
> >> >> >> > L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC
> >firmware)
> >> >and
> >> >> >> > U-Boot proper from MMC devices.
> >> >> >> >
> >> >> >> > This series depends on:
> >> >> >> > [1] https://patchwork.ozlabs.org/patch/1281853
> >> >> >> > [2] https://patchwork.ozlabs.org/patch/1281852
> >> >> >> >
> >> >> >> > All these together is available for testing here [3] [3]
> >> >> >> > https://github.com/pragnesh26992/u-boot/tree/spl
> >> >> >> >
> >> >> >> > How to test this patch:
> >> >> >> > 1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y
> >> >> >> > 2) export
> >> >> >> >
> >> >>
> >>
> >>>OPENSBI= >c.
> >> >> >> > bi
> >> >> >> > n>
> >> >> >> > 3) Change to u-boot-dir
> >> >> >> > 4) make sifive_fu540_defconfig
> >> >> >> > 5) make all
> >> >> >> > 6) Format the SD card (make sure the disk has GPT, otherwise
> >> >> >> > use gdisk to switch)
> >> >> >> >
> >> >> >> > # sudo sgdisk --clear \
> >> >> >> > > --set-alignment=2 \
> >> >> >> > > --new=1:34:2081 --change-name=1:loader1
> >> >> >> > --typecode=1:5B193300-
> >> >> >FC78-40CD-8002-E86C45580B47 \
> >> >> >> > > --new=2:2082:10273 --change-name=2:loader2 --
> >> >> >typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
> >> >> >> > > --new=3:10274: --change-name=3:rootfs
> >> >> >> > --typecode=3:0FC63DAF-
> >> >> >8483-4772-8E79-3D69D8477DE4 \
> >> >> >> > > /dev/sda
> >> >> >> >
> >> >> >> > 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
> >> >> >> > 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082
> >> >> >> >
> >> >> >> > Changes in v11:
> >> >> >> > - Remove TPL related code and OF_PLATDATA from FU540
> >> >> >> >   DDR driver (drivers/ram/sifive/fu540_ddr.c)
> >> >> >> > - Update FU540 doc (doc/board/sifive/fu540.rst)
> >> >> >> >   Remove unnecessary print
> >> >> >>
> >> >> >> Could we get this v11 applied as soon as possible for v2020.07?
> >> >> >
> >> >> >No problem, if everything is OK, I will applied ASAP.
> >> >> >But Jagan seem have some responses, please check about it.
> >> >> >
> >> >> >>
> >> >> >> > This series depends on:
> >> >> >> > [1] https://patchwork.ozlabs.org/patch/1281853
> >> >> >> > [2] https://patchwork.ozlabs.org/patch/1281852
> >> >>
> >> >> With " assigned-clocks" and " assigned-clock-rates" for cpus, this
> >> >> FU540 SPL series is no more depend on the above patches.
> >> >>
> >> >> cpus {
> >> >> assigned-clocks = < PRCI_CLK_COREPLL>;
> >> >> assigned-clock-rates = <10>; .
> >> >> }
> >> >>
> >> >> I will update the series dependency in v12. Thanks to @Sean
> >> >> Anderson for
> >> >the suggestion.
> >> >>
> >> >
> >> >Are these "assigned-clocks" and "assigned-clock-rates" bindings the
> >> >suggested ones by the Linux kernel upstream?
> >>
> >> https://patchwork.ozlabs.org/project/uboot/patch/20200502100628.24809-
> >> 

Re: [PATCH v10 17/18] configs: fu540: Add config options for U-Boot SPL

[Bin Meng]

Hi Pragnesh,

On Wed, May 20, 2020 at 9:33 PM Pragnesh Patel
 wrote:
>
> Hi Jagan,
>
> >-Original Message-
> >From: U-Boot  On Behalf Of Pragnesh Patel
> >Sent: 20 May 2020 12:55
> >To: Bin Meng ; Jagan Teki
> >
> >Cc: U-Boot-Denx ; Atish Patra
> >; Palmer Dabbelt ; Paul
> >Walmsley ; Anup Patel ;
> >Sagar Kadam ; Rick Chen ;
> >Palmer Dabbelt 
> >Subject: RE: [PATCH v10 17/18] configs: fu540: Add config options for U-Boot
> >SPL
> >
> >Hi Jagan,
> >
> >>-Original Message-
> >>From: Bin Meng 
> >>Sent: 20 May 2020 10:07
> >>To: Jagan Teki 
> >>Cc: Pragnesh Patel ; U-Boot-Denx  >>b...@lists.denx.de>; Atish Patra ; Palmer Dabbelt
> >>; Paul Walmsley
> >;
> >>Anup Patel ; Sagar Kadam
> >;
> >>Rick Chen ; Palmer Dabbelt 
> >>Subject: Re: [PATCH v10 17/18] configs: fu540: Add config options for
> >>U-Boot SPL
> >>
> >>[External Email] Do not click links or attachments unless you recognize
> >>the sender and know the content is safe
> >>
> >>Hi Jagan,
> >>
> >>On Wed, May 20, 2020 at 12:11 AM Jagan Teki
> >>
> >>wrote:
> >>>
> >>> On Sat, May 16, 2020 at 11:42 AM Pragnesh Patel
> >>>  wrote:
> >>> >
> >>> > Hi Jagan,
> >>> >
> >>> > >-Original Message-
> >>> > >From: Jagan Teki 
> >>> > >Sent: 15 May 2020 23:05
> >>> > >To: Pragnesh Patel 
> >>> > >Cc: U-Boot-Denx ; Atish Patra
> >>> > >; Palmer Dabbelt
> >>;
> >>> > >Bin Meng ; Paul Walmsley
> >>> > >; Anup Patel ;
> >Sagar
> >>> > >Kadam ; Rick Chen ;
> >>> > >Palmer Dabbelt 
> >>> > >Subject: Re: [PATCH v10 17/18] configs: fu540: Add config options
> >>> > >for U-Boot SPL
> >>> > >
> >>> > >[External Email] Do not click links or attachments unless you
> >>> > >recognize the sender and know the content is safe
> >>> > >
> >>> > >On Thu, May 14, 2020 at 5:24 PM Pragnesh Patel
> >>> > > wrote:
> >>> > >>
> >>> > >> With sifive_fu540_defconfig:
> >>> > >>
> >>> > >> User can use FSBL or u-boot-spl.bin anyone at a time.
> >>> > >>
> >>> > >> For FSBL,
> >>> > >> fsbl->fw_payload.bin (opensbi + U-Boot)
> >>> > >>
> >>> > >> For u-boot-spl.bin,
> >>> > >> u-boot-spl.bin->FIT image (opensbi + U-Boot proper + dtb)
> >>> > >>
> >>> > >> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin
> >>> > >> with
> >>> > >> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load
> >>> > >> FIT image u-boot.itb from SD card into RAM.
> >>> > >>
> >>> > >> U-Boot SPL expects u-boot.itb FIT image at the starting of SD
> >>> > >> card sector number (0x822) of GUID type
> >>> > >> "2E54B353-1271-4842-806F-
> >>> > >E436D6AF6985"
> >>> > >>
> >>> > >> Signed-off-by: Pragnesh Patel 
> >>> > >> Signed-off-by: Jagan Teki 
> >>> > >> Reviewed-by: Jagan Teki 
> >>> > >> ---
> >>> > >>  configs/sifive_fu540_defconfig |   8 ++
> >>> > >>  doc/board/sifive/fu540.rst | 134
> >>+
> >>> > >>  2 files changed, 142 insertions(+)
> >>> > >>
> >>> > >> diff --git a/configs/sifive_fu540_defconfig
> >>> > >> b/configs/sifive_fu540_defconfig index f805aacc7a..8d412f8d6a
> >>> > >> 100644
> >>> > >> --- a/configs/sifive_fu540_defconfig
> >>> > >> +++ b/configs/sifive_fu540_defconfig
> >>> > >> @@ -1,6 +1,11 @@
> >>> > >>  CONFIG_RISCV=y
> >>> > >> +CONFIG_SPL_GPIO_SUPPORT=y
> >>> > >> +CONFIG_SYS_MALLOC_F_LEN=0x3000
> >>> > >>  CONFIG_ENV_SIZE=0x2
> >>> > >> +CONFIG_SPL_MMC_SUPPORT=y
> >>> > >>  CONFIG_NR_DRAM_BANKS=1
> >>> > >> +CONFIG_SPL=y
> >>> > >> +CONFIG_SPL_SPI_SUPPORT=y
> >>> > >>  CONFIG_TARGET_SIFIVE_FU540=y
> >>> > >>  CONFIG_ARCH_RV64I=y
> >>> > >>  CONFIG_RISCV_SMODE=y
> >>> > >> @@ -9,7 +14,10 @@ CONFIG_FIT=y
> >>> > >>  CONFIG_MISC_INIT_R=y
> >>> > >>  CONFIG_DISPLAY_CPUINFO=y
> >>> > >>  CONFIG_DISPLAY_BOARDINFO=y
> >>> > >> +CONFIG_SPL_SEPARATE_BSS=y
> >>> > >> +CONFIG_SPL_YMODEM_SUPPORT=y
> >>> > >>  CONFIG_OF_BOARD_FIXUP=y
> >>> > >>  CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
> >>> > >>  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> >>> > >> +CONFIG_SPL_CLK=y
> >>> > >>  CONFIG_DM_MTD=y
> >>> > >> diff --git a/doc/board/sifive/fu540.rst
> >>> > >> b/doc/board/sifive/fu540.rst index 610ba87074..89e8d66c56 100644
> >>> > >> --- a/doc/board/sifive/fu540.rst
> >>> > >> +++ b/doc/board/sifive/fu540.rst
> >>> > >> @@ -31,6 +31,9 @@ TODO:
> >>> > >>  stdout-path = "/soc/serial@1001:115200";
> >>> > >> };
> >>> > >>
> >>> > >> +Booting from MMC using FSBL
> >>> > >> +---
> >>> > >> +
> >>> > >>  Building
> >>> > >>  
> >>> > >>
> >>> > >> @@ -421,3 +424,134 @@ as well.
> >>> > >>
> >>> > >> Please press Enter to activate this console.
> >>> > >> / #
> >>> > >> +
> >>> > >> +Booting from MMC using U-Boot SPL
> >>> > >> +-
> >>> > >> +
> >>> > >> +Building
> >>> > >> +
> >>> > >> +
> >>> > >> +Before building U-Boot SPL, OpenSBI must be built first.
> >>> > >> +OpenSBI can be cloned and built for FU540 as below:
> >>> > >> +
> >>> > >> +.. code-block:: console
> >>> > >> +
> >>> > >> +   git clone 

Re: Warnings on Edison

[Tom Rini]

On Wed, May 20, 2020 at 07:22:26AM -0600, Simon Glass wrote:
> Hi Tom,
> 
> On Wed, 20 May 2020 at 07:06, Tom Rini  wrote:
> >
> > On Wed, May 20, 2020 at 11:17:17AM +0300, Andy Shevchenko wrote:
> > > On Tue, May 19, 2020 at 10:47:27AM -0600, Simon Glass wrote:
> > > > Hi Andy,
> > > >
> > > > When I build edison on master I recently started seeing this warning:
> > > >
> > > > +board/intel/edison/dsdt.asl.tmp210: Name (SSCN, Package ()
> > > > +Warning  4089 -Object is not referenced ^
> > > > +
> > > > +board/intel/edison/dsdt.asl.tmp214: Name (FMCN, Package ()
> > > > +board/intel/edison/dsdt.asl.tmp218: Name (HSCN, Package ()
> > > > +board/intel/edison/dsdt.asl.tmp239: Name (SSCN, Package ()
> > > > +board/intel/edison/dsdt.asl.tmp243: Name (FMCN, Package ()
> > > > +board/intel/edison/dsdt.asl.tmp247: Name (HSCN, Package ()
> > > > +board/intel/edison/dsdt.asl.tmp291: Method (GPLD, 1,
> > > > Serialized) {
> > > > +Warning  4089 -  Object is not referenced ^
> > >
> > > Can't reproduce.
> > > ASL+ Optimizing Compiler/Disassembler version 20190509
> >
> > Ah, that explains it then I bet.  Ubuntu/bionic is:
> > ASL+ Optimizing Compiler/Disassembler version 20180105
> 
> I must have installed something newer, 20180810. I have not upgraded
> to 2020.04 yet. A bit nervous about what will change.

To be clear, I see the warning on bionic too.  If we can easily install
just a new iasl in CI (and locally as needed) via deb, that would be
good, otherwise if it's just a warning maybe we live with it, so long as
Edison still works.

-- 
Tom


signature.asc
Description: PGP signature

RE: [PATCH v10 17/18] configs: fu540: Add config options for U-Boot SPL

[Pragnesh Patel]

Hi Jagan,

>-Original Message-
>From: U-Boot  On Behalf Of Pragnesh Patel
>Sent: 20 May 2020 12:55
>To: Bin Meng ; Jagan Teki
>
>Cc: U-Boot-Denx ; Atish Patra
>; Palmer Dabbelt ; Paul
>Walmsley ; Anup Patel ;
>Sagar Kadam ; Rick Chen ;
>Palmer Dabbelt 
>Subject: RE: [PATCH v10 17/18] configs: fu540: Add config options for U-Boot
>SPL
>
>Hi Jagan,
>
>>-Original Message-
>>From: Bin Meng 
>>Sent: 20 May 2020 10:07
>>To: Jagan Teki 
>>Cc: Pragnesh Patel ; U-Boot-Denx >b...@lists.denx.de>; Atish Patra ; Palmer Dabbelt
>>; Paul Walmsley
>;
>>Anup Patel ; Sagar Kadam
>;
>>Rick Chen ; Palmer Dabbelt 
>>Subject: Re: [PATCH v10 17/18] configs: fu540: Add config options for
>>U-Boot SPL
>>
>>[External Email] Do not click links or attachments unless you recognize
>>the sender and know the content is safe
>>
>>Hi Jagan,
>>
>>On Wed, May 20, 2020 at 12:11 AM Jagan Teki
>>
>>wrote:
>>>
>>> On Sat, May 16, 2020 at 11:42 AM Pragnesh Patel
>>>  wrote:
>>> >
>>> > Hi Jagan,
>>> >
>>> > >-Original Message-
>>> > >From: Jagan Teki 
>>> > >Sent: 15 May 2020 23:05
>>> > >To: Pragnesh Patel 
>>> > >Cc: U-Boot-Denx ; Atish Patra
>>> > >; Palmer Dabbelt
>>;
>>> > >Bin Meng ; Paul Walmsley
>>> > >; Anup Patel ;
>Sagar
>>> > >Kadam ; Rick Chen ;
>>> > >Palmer Dabbelt 
>>> > >Subject: Re: [PATCH v10 17/18] configs: fu540: Add config options
>>> > >for U-Boot SPL
>>> > >
>>> > >[External Email] Do not click links or attachments unless you
>>> > >recognize the sender and know the content is safe
>>> > >
>>> > >On Thu, May 14, 2020 at 5:24 PM Pragnesh Patel
>>> > > wrote:
>>> > >>
>>> > >> With sifive_fu540_defconfig:
>>> > >>
>>> > >> User can use FSBL or u-boot-spl.bin anyone at a time.
>>> > >>
>>> > >> For FSBL,
>>> > >> fsbl->fw_payload.bin (opensbi + U-Boot)
>>> > >>
>>> > >> For u-boot-spl.bin,
>>> > >> u-boot-spl.bin->FIT image (opensbi + U-Boot proper + dtb)
>>> > >>
>>> > >> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin
>>> > >> with
>>> > >> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load
>>> > >> FIT image u-boot.itb from SD card into RAM.
>>> > >>
>>> > >> U-Boot SPL expects u-boot.itb FIT image at the starting of SD
>>> > >> card sector number (0x822) of GUID type
>>> > >> "2E54B353-1271-4842-806F-
>>> > >E436D6AF6985"
>>> > >>
>>> > >> Signed-off-by: Pragnesh Patel 
>>> > >> Signed-off-by: Jagan Teki 
>>> > >> Reviewed-by: Jagan Teki 
>>> > >> ---
>>> > >>  configs/sifive_fu540_defconfig |   8 ++
>>> > >>  doc/board/sifive/fu540.rst | 134
>>+
>>> > >>  2 files changed, 142 insertions(+)
>>> > >>
>>> > >> diff --git a/configs/sifive_fu540_defconfig
>>> > >> b/configs/sifive_fu540_defconfig index f805aacc7a..8d412f8d6a
>>> > >> 100644
>>> > >> --- a/configs/sifive_fu540_defconfig
>>> > >> +++ b/configs/sifive_fu540_defconfig
>>> > >> @@ -1,6 +1,11 @@
>>> > >>  CONFIG_RISCV=y
>>> > >> +CONFIG_SPL_GPIO_SUPPORT=y
>>> > >> +CONFIG_SYS_MALLOC_F_LEN=0x3000
>>> > >>  CONFIG_ENV_SIZE=0x2
>>> > >> +CONFIG_SPL_MMC_SUPPORT=y
>>> > >>  CONFIG_NR_DRAM_BANKS=1
>>> > >> +CONFIG_SPL=y
>>> > >> +CONFIG_SPL_SPI_SUPPORT=y
>>> > >>  CONFIG_TARGET_SIFIVE_FU540=y
>>> > >>  CONFIG_ARCH_RV64I=y
>>> > >>  CONFIG_RISCV_SMODE=y
>>> > >> @@ -9,7 +14,10 @@ CONFIG_FIT=y
>>> > >>  CONFIG_MISC_INIT_R=y
>>> > >>  CONFIG_DISPLAY_CPUINFO=y
>>> > >>  CONFIG_DISPLAY_BOARDINFO=y
>>> > >> +CONFIG_SPL_SEPARATE_BSS=y
>>> > >> +CONFIG_SPL_YMODEM_SUPPORT=y
>>> > >>  CONFIG_OF_BOARD_FIXUP=y
>>> > >>  CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
>>> > >>  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>>> > >> +CONFIG_SPL_CLK=y
>>> > >>  CONFIG_DM_MTD=y
>>> > >> diff --git a/doc/board/sifive/fu540.rst
>>> > >> b/doc/board/sifive/fu540.rst index 610ba87074..89e8d66c56 100644
>>> > >> --- a/doc/board/sifive/fu540.rst
>>> > >> +++ b/doc/board/sifive/fu540.rst
>>> > >> @@ -31,6 +31,9 @@ TODO:
>>> > >>  stdout-path = "/soc/serial@1001:115200";
>>> > >> };
>>> > >>
>>> > >> +Booting from MMC using FSBL
>>> > >> +---
>>> > >> +
>>> > >>  Building
>>> > >>  
>>> > >>
>>> > >> @@ -421,3 +424,134 @@ as well.
>>> > >>
>>> > >> Please press Enter to activate this console.
>>> > >> / #
>>> > >> +
>>> > >> +Booting from MMC using U-Boot SPL
>>> > >> +-
>>> > >> +
>>> > >> +Building
>>> > >> +
>>> > >> +
>>> > >> +Before building U-Boot SPL, OpenSBI must be built first.
>>> > >> +OpenSBI can be cloned and built for FU540 as below:
>>> > >> +
>>> > >> +.. code-block:: console
>>> > >> +
>>> > >> +   git clone https://github.com/riscv/opensbi.git
>>> > >> +   cd opensbi
>>> > >> +   make PLATFORM=generic FW_DYNAMIC=y
>>> > >> +
>>> > >> +Copy OpenSBI FW_DYNAMIC image
>>> > >> +(build/platform/generic/firmware/fw_dynamic.bin) into U-Boot
>>> > >> +root directory
>>> > >> +
>>> > >> +.. code-block:: console
>>> > >> +
>>> > >> +   cp build/platform/generic/firmware/fw_dynamic.bin
>>> > >> 

[PATCH v2] imx: imx8qm_rom7720_a1: update README

[Oliver Graute]

Update README to extract firmware from scripts

Signed-off-by: Oliver Graute 
---
 board/advantech/imx8qm_rom7720_a1/README | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/board/advantech/imx8qm_rom7720_a1/README 
b/board/advantech/imx8qm_rom7720_a1/README
index bff5712589..d3e3cec063 100644
--- a/board/advantech/imx8qm_rom7720_a1/README
+++ b/board/advantech/imx8qm_rom7720_a1/README
@@ -29,6 +29,17 @@ $ wget 
https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
 $ chmod +x firmware-imx-8.0.bin
 $ ./firmware-imx-8.0.bin
 
+Or use this to avoid running random scripts from the internet,
+but note that you must agree to the license the script displays:
+
+$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1
+$ tar -xf imx-sc-firmware-1.1.tar.bz2
+$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir)
+
+$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1
+$ tar -xf firmware-imx-8.0.tar.bz2
+$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir)
+
 Build U-Boot
 
 
-- 
2.17.1

Re: [PATCH] imx: imx8qm_rom7720_a1: update README

[Oliver Graute]

On 15/05/20, Oliver Graute wrote:
> Update README to extract firmware from scripts
> 
> Signed-off-by: Oliver Graute 
> ---
>  board/advantech/imx8qm_rom7720_a1/README | 11 +++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/board/advantech/imx8qm_rom7720_a1/README 
> b/board/advantech/imx8qm_rom7720_a1/README
> index bff5712589..d3e3cec063 100644
> --- a/board/advantech/imx8qm_rom7720_a1/README
> +++ b/board/advantech/imx8qm_rom7720_a1/README
> @@ -29,6 +29,17 @@ $ wget 
> https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
>  $ chmod +x firmware-imx-8.0.bin
>  $ ./firmware-imx-8.0.bin
>  
> +Or use this to avoid running random scripts from the internet,
> +but note that you must agree to the license the script displays:
> +
> +$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 
> skip=1
> +$ tar -xf imx-sc-firmware-1.1.tar.bz2
> +$ cp imx-sc-firmware-1.1/mx8qx-val-scfw-tcm.bin $(builddir)

typo it should be mx8qm-val-scfw-tcm.bin

Best Regards,

Oliver

Re: [PATCH v2 1/9] spl: Try to get SPL boot device via board_get_int

[Jagan Teki]

On Wed, May 20, 2020 at 6:32 PM Tom Rini  wrote:
>
> On Wed, May 20, 2020 at 12:53:32AM +0530, Jagan Teki wrote:
>
> > Usually, the associated board would supply spl boot device
> > using spl_boot_device() but some boards have board driver
> > that are possible to supply boot device via board_get_int
> > with BOARD_SPL_BOOT_DEVICE id.
> >
> > This patch add support for those.
> >
> > Cc: Mario Six 
> > Cc: Tom Rini 
> > Cc: Simon Glass 
> > Cc: Jean-Jacques Hiblot 
> > Signed-off-by: Jagan Teki 
> > ---
> > Changes for v2:
> > - new patch
> >
> >  common/spl/spl.c | 14 +-
> >  include/board.h  |  9 +
> >  2 files changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/common/spl/spl.c b/common/spl/spl.c
> > index fc5cbbbeba..a07b71b3c1 100644
> > --- a/common/spl/spl.c
> > +++ b/common/spl/spl.c
> > @@ -9,6 +9,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -483,9 +484,20 @@ int spl_init(void)
> >  #define BOOT_DEVICE_NONE 0xdeadbeef
> >  #endif
> >
> > +__weak u32 spl_boot_device(void)
> > +{
> > + return 0;
> > +}
> > +
> >  __weak void board_boot_order(u32 *spl_boot_list)
> >  {
> > - spl_boot_list[0] = spl_boot_device();
> > + struct udevice *board;
> > +
> > + if (!board_get())
> > + board_get_int(board, BOARD_SPL_BOOT_DEVICE,
> > +   (int *)_boot_list[0]);
> > + else
> > + spl_boot_list[0] = spl_boot_device();
> >  }
> >
> >  static struct spl_image_loader *spl_ll_find_loader(uint boot_device)
> > diff --git a/include/board.h b/include/board.h
> > index 678b652b0a..ce4eaba38d 100644
> > --- a/include/board.h
> > +++ b/include/board.h
> > @@ -211,3 +211,12 @@ static inline int board_get_fit_loadable(struct 
> > udevice *dev, int index,
> >  }
> >
> >  #endif
> > +
> > +/**
> > + * Common board unique identifier
> > + *
> > + * @BOARD_SPL_BOOT_DEVICE:   id to get SPL boot device.
> > + */
> > +enum common_ids {
> > + BOARD_SPL_BOOT_DEVICE,
> > +};
>
> I don't understand why we need this abstraction.  The intention of what
> we have today is that the generic SPL framework calls out to something
> to ask "what are we booted from?".  Why can the board driver not just
> supply that information?  Thanks!

Yes, we can update boot-device on respective areas by probing board
driver and assign spl_boot_list[0] by explicitly define
spl_boot_device function, but this change bypass all these codes. Just
like how we did on SPL fit to load the concerned image via board
driver.

152781d4641e0e4c37b3a32f699cf99aeec877c8
"spl: fit: Allow the board to tell if more images must be loaded from FIT"

Jagan.

Re: [PATCH v2 2/9] dt-bindings: board: Document sifive, fu540-modeselect

[Bin Meng]

Hi Jagan,

On Wed, May 20, 2020 at 3:24 AM Jagan Teki  wrote:
>
> Add dt-bindings documentation for sifive,fu540-modeselect board
> driver, which usually get runtime boot mode of fu540 boards.
>
> Cc: Simon Glass 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v2:
> - new patch
>
>  .../board/sifive,fu540-modeselect.txt | 15 +++
>  1 file changed, 15 insertions(+)
>  create mode 100644 doc/device-tree-bindings/board/sifive,fu540-modeselect.txt
>
> diff --git a/doc/device-tree-bindings/board/sifive,fu540-modeselect.txt 
> b/doc/device-tree-bindings/board/sifive,fu540-modeselect.txt
> new file mode 100644
> index 00..801c068390
> --- /dev/null
> +++ b/doc/device-tree-bindings/board/sifive,fu540-modeselect.txt
> @@ -0,0 +1,15 @@
> +fu540 board driver
> +
> +This driver provides capabilities to get the current boot device for
> +fu540 associated board.

This is not a board specific setting, but a SoC specific setting. The
MSEL is common for all FU540 based board.

> +
> +Required properties:
> +- compatible:  should be "sifive,fu540-modeselect"
> +- reg: physical base address and size of fu540 modeselct
> +
> +Example:
> +
> +board: mode@1000 {
> +   compatible = "sifive,fu540-modeselect";
> +   reg = <0x0 0x1000 0x0 0x1FFF>;

We should only map 4 bytes for mode select.

> +};
> --

Regards,
Bin

Re: Warnings on Edison

[Tom Rini]

On Wed, May 20, 2020 at 11:17:17AM +0300, Andy Shevchenko wrote:
> On Tue, May 19, 2020 at 10:47:27AM -0600, Simon Glass wrote:
> > Hi Andy,
> > 
> > When I build edison on master I recently started seeing this warning:
> > 
> > +board/intel/edison/dsdt.asl.tmp210: Name (SSCN, Package ()
> > +Warning  4089 -Object is not referenced ^
> > +
> > +board/intel/edison/dsdt.asl.tmp214: Name (FMCN, Package ()
> > +board/intel/edison/dsdt.asl.tmp218: Name (HSCN, Package ()
> > +board/intel/edison/dsdt.asl.tmp239: Name (SSCN, Package ()
> > +board/intel/edison/dsdt.asl.tmp243: Name (FMCN, Package ()
> > +board/intel/edison/dsdt.asl.tmp247: Name (HSCN, Package ()
> > +board/intel/edison/dsdt.asl.tmp291: Method (GPLD, 1,
> > Serialized) {
> > +Warning  4089 -  Object is not referenced ^
> 
> Can't reproduce.
> ASL+ Optimizing Compiler/Disassembler version 20190509

Ah, that explains it then I bet.  Ubuntu/bionic is:
ASL+ Optimizing Compiler/Disassembler version 20180105

-- 
Tom


signature.asc
Description: PGP signature

Re: [PATCH 1/7] amlogic: Remove ARCH= references from documentation

[Neil Armstrong]

Hi,

Le 19/05/2020 à 16:51, Tom Rini a écrit :
> When building U-Boot we select the architecture via Kconfig and not ARCH
> being passed in via the environment or make cmdline.
> 
> Cc: Beniamino Galvani 
> Cc: Neil Armstrong 
> Cc: u-boot-amlo...@groups.io
> Signed-off-by: Tom Rini 
> ---
> As an aside, these files should be converted rST and moved to doc/board/
> and the MAINTAINERS file updated to include the new documentation file
> too.  Thanks!

Adding this to my TODO list !

Thanks,
Neil

> ---
>  board/amlogic/p200/README.nanopi-k2| 1 -
>  board/amlogic/p200/README.odroid-c2| 1 -
>  board/amlogic/p200/README.p200 | 1 -
>  board/amlogic/p201/README.p201 | 1 -
>  board/amlogic/p212/README.khadas-vim   | 1 -
>  board/amlogic/p212/README.libretech-ac | 1 -
>  board/amlogic/p212/README.libretech-cc | 1 -
>  board/amlogic/p212/README.p212 | 1 -
>  board/amlogic/q200/README.khadas-vim2  | 1 -
>  board/amlogic/q200/README.q200 | 1 -
>  board/amlogic/s400/README  | 1 -
>  board/amlogic/sei510/README| 1 -
>  board/amlogic/sei610/README| 1 -
>  board/amlogic/u200/README  | 1 -
>  board/amlogic/w400/README.khadas-vim3  | 1 -
>  board/amlogic/w400/README.khadas-vim3l | 1 -
>  board/amlogic/w400/README.odroid-n2| 1 -
>  board/amlogic/w400/README.w400 | 1 -
>  18 files changed, 18 deletions(-)
> 
> diff --git a/board/amlogic/p200/README.nanopi-k2 
> b/board/amlogic/p200/README.nanopi-k2
> index d450d3c2b2af..c8dec3569b4d 100644
> --- a/board/amlogic/p200/README.nanopi-k2
> +++ b/board/amlogic/p200/README.nanopi-k2
> @@ -24,7 +24,6 @@ Currently the u-boot port supports the following devices:
>  u-boot compilation
>  ==
>  
> - > export ARCH=arm
>   > export CROSS_COMPILE=aarch64-none-elf-
>   > make nanopi-k2_defconfig
>   > make
> diff --git a/board/amlogic/p200/README.odroid-c2 
> b/board/amlogic/p200/README.odroid-c2
> index bed48c5728ba..3b9f80df29d8 100644
> --- a/board/amlogic/p200/README.odroid-c2
> +++ b/board/amlogic/p200/README.odroid-c2
> @@ -29,7 +29,6 @@ Currently the u-boot port supports the following devices:
>  u-boot compilation
>  ==
>  
> - > export ARCH=arm
>   > export CROSS_COMPILE=aarch64-none-elf-
>   > make odroid-c2_defconfig
>   > make
> diff --git a/board/amlogic/p200/README.p200 b/board/amlogic/p200/README.p200
> index 01d82d1e79e3..84d5ca535691 100644
> --- a/board/amlogic/p200/README.p200
> +++ b/board/amlogic/p200/README.p200
> @@ -31,7 +31,6 @@ Currently the u-boot port supports the following devices:
>  u-boot compilation
>  ==
>  
> - > export ARCH=arm
>   > export CROSS_COMPILE=aarch64-none-elf-
>   > make p200_defconfig
>   > make
> diff --git a/board/amlogic/p201/README.p201 b/board/amlogic/p201/README.p201
> index c251096ce142..4bb5e9590532 100644
> --- a/board/amlogic/p201/README.p201
> +++ b/board/amlogic/p201/README.p201
> @@ -31,7 +31,6 @@ Currently the u-boot port supports the following devices:
>  u-boot compilation
>  ==
>  
> - > export ARCH=arm
>   > export CROSS_COMPILE=aarch64-none-elf-
>   > make p201_defconfig
>   > make
> diff --git a/board/amlogic/p212/README.khadas-vim 
> b/board/amlogic/p212/README.khadas-vim
> index a2c7606454f8..ccf933861b79 100644
> --- a/board/amlogic/p212/README.khadas-vim
> +++ b/board/amlogic/p212/README.khadas-vim
> @@ -30,7 +30,6 @@ Currently the u-boot port supports the following devices:
>  U-Boot compilation
>  ==
>  
> - > export ARCH=arm
>   > export CROSS_COMPILE=aarch64-none-elf-
>   > make khadas-vim_defconfig
>   > make
> diff --git a/board/amlogic/p212/README.libretech-ac 
> b/board/amlogic/p212/README.libretech-ac
> index 538604261b84..3f713ec32634 100644
> --- a/board/amlogic/p212/README.libretech-ac
> +++ b/board/amlogic/p212/README.libretech-ac
> @@ -25,7 +25,6 @@ Currently the U-Boot port supports the following devices:
>  U-Boot compilation
>  ==
>  
> - > export ARCH=arm
>   > export CROSS_COMPILE=aarch64-none-elf-
>   > make libretech-ac_defconfig
>   > make
> diff --git a/board/amlogic/p212/README.libretech-cc 
> b/board/amlogic/p212/README.libretech-cc
> index 6af7de3cfa79..74434d4435ec 100644
> --- a/board/amlogic/p212/README.libretech-cc
> +++ b/board/amlogic/p212/README.libretech-cc
> @@ -30,7 +30,6 @@ Currently the U-Boot port supports the following devices:
>  U-Boot compilation
>  ==
>  
> - > export ARCH=arm
>   > export CROSS_COMPILE=aarch64-none-elf-
>   > make libretech-cc_defconfig
>   > make
> diff --git a/board/amlogic/p212/README.p212 b/board/amlogic/p212/README.p212
> index ef5370c763c4..3776f2449391 100644
> --- a/board/amlogic/p212/README.p212
> +++ b/board/amlogic/p212/README.p212
> @@ -31,7 +31,6 @@ Currently the u-boot port supports the following devices:
>  u-boot compilation
>  ==
>  
> - > export ARCH=arm
>   > export CROSS_COMPILE=aarch64-none-elf-
>   > make 

Re: [PATCH v2 1/9] spl: Try to get SPL boot device via board_get_int

[Tom Rini]

On Wed, May 20, 2020 at 12:53:32AM +0530, Jagan Teki wrote:

> Usually, the associated board would supply spl boot device
> using spl_boot_device() but some boards have board driver
> that are possible to supply boot device via board_get_int
> with BOARD_SPL_BOOT_DEVICE id.
> 
> This patch add support for those.
> 
> Cc: Mario Six 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Cc: Jean-Jacques Hiblot 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v2:
> - new patch
> 
>  common/spl/spl.c | 14 +-
>  include/board.h  |  9 +
>  2 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/common/spl/spl.c b/common/spl/spl.c
> index fc5cbbbeba..a07b71b3c1 100644
> --- a/common/spl/spl.c
> +++ b/common/spl/spl.c
> @@ -9,6 +9,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -483,9 +484,20 @@ int spl_init(void)
>  #define BOOT_DEVICE_NONE 0xdeadbeef
>  #endif
>  
> +__weak u32 spl_boot_device(void)
> +{
> + return 0;
> +}
> +
>  __weak void board_boot_order(u32 *spl_boot_list)
>  {
> - spl_boot_list[0] = spl_boot_device();
> + struct udevice *board;
> +
> + if (!board_get())
> + board_get_int(board, BOARD_SPL_BOOT_DEVICE,
> +   (int *)_boot_list[0]);
> + else
> + spl_boot_list[0] = spl_boot_device();
>  }
>  
>  static struct spl_image_loader *spl_ll_find_loader(uint boot_device)
> diff --git a/include/board.h b/include/board.h
> index 678b652b0a..ce4eaba38d 100644
> --- a/include/board.h
> +++ b/include/board.h
> @@ -211,3 +211,12 @@ static inline int board_get_fit_loadable(struct udevice 
> *dev, int index,
>  }
>  
>  #endif
> +
> +/**
> + * Common board unique identifier
> + *
> + * @BOARD_SPL_BOOT_DEVICE:   id to get SPL boot device.
> + */
> +enum common_ids {
> + BOARD_SPL_BOOT_DEVICE,
> +};

I don't understand why we need this abstraction.  The intention of what
we have today is that the generic SPL framework calls out to something
to ask "what are we booted from?".  Why can the board driver not just
supply that information?  Thanks!

-- 
Tom


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Re: [PATCH] image: Add support for ZSTD decompression

[Tom Rini]

On Wed, May 20, 2020 at 01:38:01PM +0200, Robert Marko wrote:

> Tom,
> I have tried various things but CONFIG_IS_ENABLED won't work inside of
> switch case.
> It works fine outside of if though.

OK, thanks, I'll poke things more to make sure what I'm worried about
doesn't happen.

-- 
Tom


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Description: PGP signature

Re: [PATCH] armv8: cache_v8: fix mmu_set_region_dcache_behaviour

[Tom Rini]

On Wed, May 20, 2020 at 12:10:23PM +, Peng Fan wrote:
> > Subject: [PATCH] armv8: cache_v8: fix mmu_set_region_dcache_behaviour
> 
> Any comments?

I'll put it on my list, thanks.

-- 
Tom


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Re: [PATCH v2] cmd: avb: free partition buffer upon verify completion

[Tom Rini]

On Mon, May 11, 2020 at 12:11:53PM +0200, Gary Bisson wrote:

> Doing the same as the unittests for libavb [1].
> 
> Allows to run 'avb verify' multiple times which can be useful after a
> failure to be able to re-flash the partition and try again.
> 
> [1]
> https://android.googlesource.com/platform/external/avb/+/refs/tags/android-9.0.0_r37/test/avb_slot_verify_unittest.cc#156
> 
> Signed-off-by: Gary Bisson 
> Reviewed-by: Igor Opaniuk 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v2] drivers: crypto: mod_exp_sw: Re-add DM_FLAG_PRE_RELOC

[Tom Rini]

On Thu, May 07, 2020 at 08:36:03PM +0200, Jan Kiszka wrote:

> From: Jan Kiszka 
> 
> This driver is safe to use in SPL without relocation. Denying
> DM_FLAG_PRE_RELOC prevents its usability for verifying the main U-Boot
> or other artifacts from the SPL unless needless enabling the full driver
> set (SPL_OF_PLATDATA).
> 
> Fixes: 17e117408571 ("drivers: crypto: rsa_mod_exp: avoid DM_FLAG_PRE_RELOC")
> CC: Heinrich Schuchardt 
> CC: Marek Vasut 
> Signed-off-by: Jan Kiszka 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v2] test: Use ut_asserteq_mem() where possible

[Tom Rini]

On Sun, May 10, 2020 at 12:52:45PM -0600, Simon Glass wrote:

> Quite a few tests still use ut_assertok(memcmp(...)) and variants. Modify
> them to use the macro designed for this purpose.
> 
> Suggested-by: Wolfgang Wallner 
> 
> Signed-off-by: Simon Glass 
> Reviewed-by: Wolfgang Wallner 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] mpc83xx: remove redundant MPC83xx_RESET #define

[Tom Rini]

On Tue, May 05, 2020 at 12:21:18AM +0200, Rasmus Villemoes wrote:

> This macro is only used (tested for existence) in mpc83xx.c, which
> unconditionally includes mpc83xx.h where it is unconditionally
> defined. Removing it makes the remaining code easier to read.
> 
> Signed-off-by: Rasmus Villemoes 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] mpc83xx, abb: remove suvd3 board

[Tom Rini]

On Tue, Feb 18, 2020 at 06:03:51PM +0100, Heiko Schocher wrote:

> the mpc83xxx suvd3 variant is not longer used, so
> remove it.
> 
> Signed-off-by: Holger Brunck 
> Signed-off-by: Heiko Schocher 
> Reviewed-by: Simon Glass 
> Reviewed-by: Priyanka Jain 

Applied to u-boot/master, thanks!

-- 
Tom


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Description: PGP signature

RE: [PATCH] armv8: cache_v8: fix mmu_set_region_dcache_behaviour

[Peng Fan]

> Subject: [PATCH] armv8: cache_v8: fix mmu_set_region_dcache_behaviour

Any comments?

Thanks,
Peng.

> 
> enum dcache_option already shift left 2 bits, PMD_ATTRINDX(option), will
> wrongly shift left the attr 4bits, which is wrong. And make the region user 
> set
> not has expected attribute and might affect the splitted block region.
> 
> Reviewed-by: Ye Li 
> Signed-off-by: Peng Fan 
> ---
>  arch/arm/cpu/armv8/cache_v8.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv8/cache_v8.c
> b/arch/arm/cpu/armv8/cache_v8.c index 6a5518f9de..35ee5572e9 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -555,7 +555,7 @@ static u64 set_one_region(u64 start, u64 size, u64
> attrs, bool flag, int level)  void
> mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
>enum dcache_option option)
>  {
> - u64 attrs = PMD_ATTRINDX(option);
> + u64 attrs = PMD_ATTRINDX(option >> 2);
>   u64 real_start = start;
>   u64 real_size = size;
> 
> --
> 2.16.4

rk3399: SPI boot: Return from ROM unsuccessful (with TPL)

[Jagan Teki]

It seems like SPI boot on rk3399 with TPL based is unable to return
from ROM or switching to from TPL to SPL is unsuccessful.

I have verified board_init_f on spl.c and the control is not even
reached here. On the other hand the SPL-alone boot flow works fine
from SPI.

SPI boot log:

U-Boot TPL 2020.07-rc2-00047-gd2ebbbd0e6,`irty (May 20 2020 - 17:22:25)
Channel 0: LPDDR4, 50MHz
BW=30 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Shze=2048LB
Channel 1: LPDR4,50MHz
BW=32 CoL=10 Bk=8 CR0 Row=15 CS1 Row=15 CS=2 Die BW=16 Cize=2048LB
256B stride
256B spride
lpddr4_set_rate: change freq to 4 mhz 0, 1
lpddr4_set_rate8 changE freq to 8 mhz 0, 0
Trying to bont from BOOTROM
Returning to boot ROM...

Any inputs?

Jagan.

RE: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL

[Pragnesh Patel]

Hi Bin,

>-Original Message-
>From: Bin Meng 
>Sent: 20 May 2020 15:54
>To: Pragnesh Patel 
>Cc: Rick Chen ; Jagan Teki
>; Sean Anderson ; U-
>Boot Mailing List ; rick ; Alan
>Kao 
>Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh,
>
>On Wed, May 20, 2020 at 3:41 PM Pragnesh Patel
> wrote:
>>
>> Hi Bin,
>>
>> >-Original Message-
>> >From: Bin Meng 
>> >Sent: 20 May 2020 13:07
>> >To: Pragnesh Patel 
>> >Cc: Rick Chen ; Jagan Teki
>> >; Sean Anderson ;
>U-
>> >Boot Mailing List ; rick ;
>> >Alan Kao 
>> >Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >"Hi Pragnesh,
>> >
>> >On Wed, May 20, 2020 at 3:29 PM Pragnesh Patel
>> > wrote:
>> >>
>> >>
>> >>
>> >> >-Original Message-
>> >> >From: Rick Chen 
>> >> >Sent: 20 May 2020 08:38
>> >> >To: Bin Meng ; Pragnesh Patel
>> >> >; Jagan Teki
>> >> >; Sean Anderson
>
>> >> >Cc: U-Boot Mailing List ; rick
>> >> >; Alan Kao 
>> >> >Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
>> >> >
>> >> >[External Email] Do not click links or attachments unless you
>> >> >recognize the sender and know the content is safe
>> >> >
>> >> >Hi Bin
>> >> >
>> >> >> -Original Message-
>> >> >> From: Bin Meng [mailto:bmeng...@gmail.com]
>> >> >> Sent: Tuesday, May 19, 2020 4:44 PM
>> >> >> To: Pragnesh Patel; Rick Jian-Zhi Chen(陳建志)
>> >> >> Subject: Re: [PATCH v11 00/18] RISC-V SiFive FU540 support SPL
>> >> >>
>> >> >> Hi Rick,
>> >> >>
>> >> >> On Tue, May 19, 2020 at 3:04 PM Pragnesh Patel
>> >> > wrote:
>> >> >> >
>> >> >> > This series add support for SPL to FU540. U-Boot SPL can boot
>> >> >> > from
>> >> >> > L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC
>firmware)
>> >and
>> >> >> > U-Boot proper from MMC devices.
>> >> >> >
>> >> >> > This series depends on:
>> >> >> > [1] https://patchwork.ozlabs.org/patch/1281853
>> >> >> > [2] https://patchwork.ozlabs.org/patch/1281852
>> >> >> >
>> >> >> > All these together is available for testing here [3] [3]
>> >> >> > https://github.com/pragnesh26992/u-boot/tree/spl
>> >> >> >
>> >> >> > How to test this patch:
>> >> >> > 1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y
>> >> >> > 2) export
>> >> >> >
>> >>
>>
>>>OPENSBI=c.
>> >> >> > bi
>> >> >> > n>
>> >> >> > 3) Change to u-boot-dir
>> >> >> > 4) make sifive_fu540_defconfig
>> >> >> > 5) make all
>> >> >> > 6) Format the SD card (make sure the disk has GPT, otherwise
>> >> >> > use gdisk to switch)
>> >> >> >
>> >> >> > # sudo sgdisk --clear \
>> >> >> > > --set-alignment=2 \
>> >> >> > > --new=1:34:2081 --change-name=1:loader1
>> >> >> > --typecode=1:5B193300-
>> >> >FC78-40CD-8002-E86C45580B47 \
>> >> >> > > --new=2:2082:10273 --change-name=2:loader2 --
>> >> >typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
>> >> >> > > --new=3:10274: --change-name=3:rootfs
>> >> >> > --typecode=3:0FC63DAF-
>> >> >8483-4772-8E79-3D69D8477DE4 \
>> >> >> > > /dev/sda
>> >> >> >
>> >> >> > 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
>> >> >> > 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082
>> >> >> >
>> >> >> > Changes in v11:
>> >> >> > - Remove TPL related code and OF_PLATDATA from FU540
>> >> >> >   DDR driver (drivers/ram/sifive/fu540_ddr.c)
>> >> >> > - Update FU540 doc (doc/board/sifive/fu540.rst)
>> >> >> >   Remove unnecessary print
>> >> >>
>> >> >> Could we get this v11 applied as soon as possible for v2020.07?
>> >> >
>> >> >No problem, if everything is OK, I will applied ASAP.
>> >> >But Jagan seem have some responses, please check about it.
>> >> >
>> >> >>
>> >> >> > This series depends on:
>> >> >> > [1] https://patchwork.ozlabs.org/patch/1281853
>> >> >> > [2] https://patchwork.ozlabs.org/patch/1281852
>> >>
>> >> With " assigned-clocks" and " assigned-clock-rates" for cpus, this
>> >> FU540 SPL series is no more depend on the above patches.
>> >>
>> >> cpus {
>> >> assigned-clocks = < PRCI_CLK_COREPLL>;
>> >> assigned-clock-rates = <10>; .
>> >> }
>> >>
>> >> I will update the series dependency in v12. Thanks to @Sean
>> >> Anderson for
>> >the suggestion.
>> >>
>> >
>> >Are these "assigned-clocks" and "assigned-clock-rates" bindings the
>> >suggested ones by the Linux kernel upstream?
>>
>> https://patchwork.ozlabs.org/project/uboot/patch/20200502100628.24809-
>> 17-pragnesh.pa...@sifive.com/
>
>I see. "assigned-clocks" is only needed for U-Boot.
>
>Do we still need "clocks" in each cpu node?

Right now, "cpu detail" shows wrong frequency in U-Boot for FU540.
This 
https://patchwork.ozlabs.org/project/uboot/patch/20200503024637.327733-18-sean...@gmail.com/
 patch solves that problem.

For this patch, we need "clocks" in each cpu 

Re: [RESEND PATCH] usb: dwc3: fix NULL pointer issue

[Marek Vasut]

On 5/20/20 9:53 AM, Chunfeng Yun wrote:
> Hi Marek,
> 
> On Thu, 2020-05-14 at 13:55 +0800, Chunfeng Yun wrote:
>> The phy_bulk pointer *usb_phys is used before allocated,
>> fix it by using a phy_bulk variable instead in
>> xhci_dwc3_platdata struct
>>

I'm never receiving the emails to the denx address listed in the
MAINTAINERS, any ideas why ?

Anyway, I'll pick this one, thanks.

Re: [PATCH] image: Add support for ZSTD decompression

[Robert Marko]

Tom,
I have tried various things but CONFIG_IS_ENABLED won't work inside of
switch case.
It works fine outside of if though.


On Tue, May 5, 2020 at 11:19 PM Robert Marko  wrote:
>
>
>
> On Mon, May 4, 2020 at 3:04 PM Tom Rini  wrote:
>>
>> On Sun, May 03, 2020 at 12:24:14PM +0200, Robert Marko wrote:
>> > Hi,
>> >
>> > I checked and SPL_ZSTD symbol already exists.
>> > But trying to use #if CONFIG_IS_ENABLED(ZSTD) inside
>> > of the switch case will fail with the preprocessor error:
>> > In file included from tools/common/image.c:1:
>>
>> Ah right, oops.
>>
>> > > ./tools/../common/image.c: In function ‘image_decomp’:
>> > > ./tools/../common/image.c:510:22: error: missing binary operator before
>> > > token "("
>> > >   510 | #if CONFIG_IS_ENABLED(ZSTD)
>> >
>> >
>> > Outside of the switch_case it works fine
>>
>> Sounds like  needs an explicit #include then.
>
> Unfortunately, it does not help.
> Preprocessor throws the same error
>>
>>
>> >
>> >
>> > On Fri, May 1, 2020 at 6:42 PM Tom Rini  wrote:
>> >
>> > > On Fri, May 01, 2020 at 05:15:41PM +0200, Robert Marko wrote:
>> > > > On Fri, May 1, 2020 at 4:56 PM Tom Rini  wrote:
>> > > > >
>> > > > > On Sat, Apr 25, 2020 at 07:37:21PM +0200, Robert Marko wrote:
>> > > > >
>> > > > > > This patch adds support for ZSTD decompression of FIT images.
>> > > > > >
>> > > > > > Signed-off-by: Robert Marko 
>> > > > > > Cc: Luka Perkov 
>> > > > > > ---
>> > > > > >  common/image.c  | 52
>> > > +
>> > > > > >  include/image.h |  1 +
>> > > > > >  2 files changed, 53 insertions(+)
>> > > > > >
>> > > > > > diff --git a/common/image.c b/common/image.c
>> > > > > > index 94873cb6ed..70ba0f4328 100644
>> > > > > > --- a/common/image.c
>> > > > > > +++ b/common/image.c
>> > > > > > @@ -42,6 +42,7 @@
>> > > > > >  #include 
>> > > > > >  #include 
>> > > > > >  #include 
>> > > > > > +#include 
>> > > > > >
>> > > > > >  #ifdef CONFIG_CMD_BDI
>> > > > > >  extern int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *
>> > > const argv[]);
>> > > > > > @@ -193,6 +194,7 @@ static const table_entry_t uimage_comp[] = {
>> > > > > >   {   IH_COMP_LZMA,   "lzma", "lzma compressed",
>> > >   },
>> > > > > >   {   IH_COMP_LZO,"lzo",  "lzo compressed",
>> > >  },
>> > > > > >   {   IH_COMP_LZ4,"lz4",  "lz4 compressed",
>> > >  },
>> > > > > > + {   IH_COMP_ZSTD,   "zstd", "zstd compressed",
>> > >   },
>> > > > > >   {   -1, "", "",
>> > >  },
>> > > > > >  };
>> > > > > >
>> > > > > > @@ -480,6 +482,56 @@ int image_decomp(int comp, ulong load, ulong
>> > > image_start, int type,
>> > > > > >   break;
>> > > > > >   }
>> > > > > >  #endif /* CONFIG_LZ4 */
>> > > > > > +#ifdef CONFIG_ZSTD
>> > > > >
>> > > > > We need to add SPL_ZSTD as a symbol to lib/Kconfig and then use
>> > > > > CONFIG_IS_ENABLED() tests here to avoid growth in SPL.  Thanks!
>> > > > Hi,
>> > > > is that something that I need to do or?
>> > >
>> > > Yes.  You need to add the symbol, and then the code you're adding needs
>> > > to make use of '#if CONFIG_IS_ENABLED(ZSTD)' rather than '#ifdef
>> > > CONFIG_ZSTD'.  Sorry for not being clear enough.
>> > >
>> > > --
>> > > Tom
>> > >
>>
>> --
>> Tom

[PATCH 3/3] gpio: mpc8xxx: support fsl-layerscape platform.

[Hui Song]

From: "hui.song" 

Make the MPC8XXX gpio driver to support the fsl-layerscape.

Signed-off-by: hui.song 
---
 drivers/gpio/mpc8xxx_gpio.c | 108 +---
 1 file changed, 87 insertions(+), 21 deletions(-)

diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
index 1dfd22522c..41bd2f8374 100644
--- a/drivers/gpio/mpc8xxx_gpio.c
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -6,12 +6,15 @@
  * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
  *
  * Copyright 2010 eXMeritus, A Boeing Company
+ * Copyright 2020 NXP
  */
 
 #include 
 #include 
 #include 
 #include 
+#include 
+#include 
 
 struct ccsr_gpio {
u32 gpdir;
@@ -20,6 +23,7 @@ struct ccsr_gpio {
u32 gpier;
u32 gpimr;
u32 gpicr;
+   u32 gpibe;
 };
 
 struct mpc8xxx_gpio_data {
@@ -35,6 +39,7 @@ struct mpc8xxx_gpio_data {
 */
u32 dat_shadow;
ulong type;
+   bool  little_endian;
 };
 
 enum {
@@ -47,33 +52,56 @@ inline u32 gpio_mask(uint gpio)
return (1U << (31 - (gpio)));
 }
 
-static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
+static inline u32 mpc8xxx_gpio_get_val(struct udevice *dev, u32 mask)
 {
-   return in_be32(>gpdat) & mask;
+   struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+   if (data->little_endian)
+   return in_le32(>base->gpdat) & mask;
+   else
+   return in_be32(>base->gpdat) & mask;
 }
 
-static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
+static inline u32 mpc8xxx_gpio_get_dir(struct udevice *dev, u32 mask)
 {
-   return in_be32(>gpdir) & mask;
+   struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+   if (data->little_endian)
+   return in_le32(>base->gpdir) & mask;
+   else
+   return in_be32(>base->gpdir) & mask;
 }
 
-static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
+static inline int mpc8xxx_gpio_open_drain_val(struct udevice *dev, u32 mask)
 {
-   return in_be32(>gpodr) & mask;
+   struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+   if (data->little_endian)
+   return in_le32(>base->gpodr) & mask;
+   else
+   return in_be32(>base->gpodr) & mask;
 }
 
-static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
+static inline void mpc8xxx_gpio_open_drain_on(struct udevice *dev, u32
  gpios)
 {
+   struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
/* GPODR register 1 -> open drain on */
-   setbits_be32(>gpodr, gpios);
+   if (data->little_endian)
+   setbits_le32(>base->gpodr, gpios);
+   else
+   setbits_be32(>base->gpodr, gpios);
 }
 
-static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
+static inline void mpc8xxx_gpio_open_drain_off(struct udevice *dev,
   u32 gpios)
 {
+   struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
/* GPODR register 0 -> open drain off (actively driven) */
-   clrbits_be32(>gpodr, gpios);
+   if (data->little_endian)
+   clrbits_le32(>base->gpodr, gpios);
+   else
+   clrbits_be32(>base->gpodr, gpios);
 }
 
 static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
@@ -82,7 +110,10 @@ static int mpc8xxx_gpio_direction_input(struct udevice 
*dev, uint gpio)
u32 mask = gpio_mask(gpio);
 
/* GPDIR register 0 -> input */
-   clrbits_be32(>base->gpdir, mask);
+   if (data->little_endian)
+   clrbits_le32(>base->gpdir, mask);
+   else
+   clrbits_be32(>base->gpdir, mask);
 
return 0;
 }
@@ -100,10 +131,20 @@ static int mpc8xxx_gpio_set_value(struct udevice *dev, 
uint gpio, int value)
data->dat_shadow &= ~mask;
}
 
-   gpdir = in_be32(>gpdir);
+   if (data->little_endian)
+   gpdir = in_le32(>gpdir);
+   else
+   gpdir = in_be32(>gpdir);
+
gpdir |= gpio_mask(gpio);
-   out_be32(>gpdat, gpdir & data->dat_shadow);
-   out_be32(>gpdir, gpdir);
+
+   if (data->little_endian) {
+   out_le32(>gpdat, gpdir & data->dat_shadow);
+   out_le32(>gpdir, gpdir);
+   } else {
+   out_be32(>gpdat, gpdir & data->dat_shadow);
+   out_be32(>gpdir, gpdir);
+   }
 
return 0;
 }
@@ -124,21 +165,20 @@ static int mpc8xxx_gpio_get_value(struct udevice *dev, 
uint gpio)
 {
struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 
-   if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) {
+   if (!!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio))) {
/* Output -> use shadowed value */
return !!(data->dat_shadow & gpio_mask(gpio));
}
 
/* Input -> read value from GPDAT register */
-   return 

Re: [PATCH] rockchip: rk3328: rock64 - fix gen3 SPL hang

[Chen-Yu Tsai]

On Wed, May 20, 2020 at 4:05 PM Matwey V. Kornilov
 wrote:
>
> вт, 19 мая 2020 г. в 17:30, Kurt Miller :
> >
> > On Tue, 2020-05-19 at 12:48 +0300, Matwey V. Kornilov wrote:
> > > вт, 19 мая 2020 г. в 01:06, Kurt Miller :
> > > >
> > > >
> > > > On Wed, 2020-05-13 at 16:10 -0400, Kurt Miller wrote:
> > > > >
> > > > > On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote:
> > > > > >
> > > > > >
> > > > > > Thanks. Have you already checked it on gen2? I think I have gen2 
> > > > > > board to test.
> > > > > Yes, I have both gen3 and gen2 boards. gen2 continues to work
> > > > > with this patch as well.
> > > > Hi Matwey,
> > > Hi Kurt,
> > >
> > > Sorry for the late reply. I've just managed to apply you patch on top
> > > of ed9a3aa645 and it didn't work for me on 2GB v2.0 rock64 board.
> > >
> > > U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16)
> > > LPDDR3, 800MHz
> > > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
> > > Trying to boot from BOOTROM
> > > Returning to boot ROM...
> > >
> > > U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 12:44:16 
> > > +0300)
> > > Trying to boot from MMC1
> > > [and nothing else happens here]
> > >
> > > What do you think may be the reason?
> >
> > Hi Matwey,
> >
>
> Hi Kurt,
>
> > Thank you for testing the patch. Hmm, are you building with ATF 2.3?
>
> You are right here, I was testing with ATF 2.1, while ATF 2.3 works correctly.
> First working commit in ATF is 0aad563c ("rockchip: Update BL31_BASE
> to 0x4").
> I suppose, it is worth to mention in the commit message for this
> patch. What do you think?

This was already mentioned in commits such as

c0a474b9d9a1 rockchip: evb-rk3328: Enable support ATF in SPL
4690ef8907e9 rockchip: rk3288-evb: update SPL_STACK/MALLOC_LEN config
with rk3399
6024467bcc0e rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs
006ab58d4636 rockchip: rk3399: update SPL_STACK_R_ADDR

ChenYu

>
> >
> > I’m booting from the uSD without an eMMC installed. Are you booting
> > from the eMMC or have one installed?
>
> I'm booting from uSD without eMMC installed also.
>
>
> >
> > Here are some background emails related to the gen3 freeze. I also
> > included the output for when gen3 fails below and the output for
> > my gen2 2gb and gen3 4gb with the patch.
> >
> > https://marc.info/?l=u-boot=158550521101881=2
> > https://marc.info/?l=u-boot=156427088018689=2
> >
> > Gen2 2GB with patch:
> >
> > U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15)
> > LPDDR3, 800MHz
> > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
> > Trying to boot from BOOTROM
> > Returning to boot ROM...
> >
> > U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 
> > -0400)
> > Trying to boot from MMC1
> > NOTICE:  BL31: v2.3():2.3
> > NOTICE:  BL31: Built : 11:30:57, May 15 2020
> > NOTICE:  BL31:Rockchip release version: v1.2
> > INFO:ARM GICv2 driver initialized
> > INFO:plat_rockchip_pmu_init: pd status 0xe
> > INFO:BL31: Initializing runtime services
> > INFO:BL31: cortex_a53: CPU workaround for 855873 was applied
> > INFO:BL31: Preparing for EL3 exit to normal world
> > INFO:Entry point address = 0x20
> > INFO:SPSR = 0x3c9
> >
> >
> > U-Boot 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 -0400)
> >
> > Model: Pine64 Rock64
> > DRAM:  2 GiB
> > PMIC:  RK8050 (on=0x40, off=0x01)
> > MMC:   mmc@ff50: 1, mmc@ff52: 0
> > Loading Environment from MMC... *** Warning - bad CRC, using default 
> > environment
> >
> > In:serial@ff13
> > Out:   serial@ff13
> > Err:   serial@ff13
> > Model: Pine64 Rock64
> > Net:   eth0: ethernet@ff54
> > Hit any key to stop autoboot:  0
> > Card did not respond to voltage select!
> > switch to partitions #0, OK
> > mmc1 is current device
> > Scanning mmc 1:1...
> > Found EFI removable media binary efi/boot/bootaa64.efi
> > libfdt fdt_check_header(): FDT_ERR_BADMAGIC
> > Scanning disk m...@ff50.blk...
> > ** Unrecognized filesystem type **
> > Card did not respond to voltage select!
> > Scanning disk m...@ff52.blk...
> > Disk m...@ff52.blk not ready
> > Found 3 disks
> > BootOrder not defined
> > EFI boot manager: Cannot load any image
> > 169176 bytes read in 15 ms (10.8 MiB/s)
> > libfdt fdt_check_header(): FDT_ERR_BADMAGIC
> > disks: sd0*
> >
> > Gen3 4GB with patch:
> >
> > U-Boot TPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15)
> > LPDDR3, 800MHz
> > BW=32 Col=11 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=4096MB
> > Trying to boot from BOOTROM
> > Returning to boot ROM...
> >
> > U-Boot SPL 2020.07-rc2-00133-ged9a3aa645-dirty (May 19 2020 - 09:52:15 
> > -0400)
> > Trying to boot from MMC1
> > NOTICE:  BL31: v2.3():2.3
> > NOTICE:  BL31: Built : 11:30:57, May 15 2020
> > NOTICE:  BL31:Rockchip release version: v1.2
> > INFO:ARM GICv2 driver initialized
> > INFO:plat_rockchip_pmu_init: pd status 0xe

[PATCH 2/3] dm: armv8: gpio: include for fsl-layerscape

[Hui Song]

From: "hui.song" 

Enable the gpio feature on fsl-layerscape platform.

Signed-off-by: hui.song 
---
 arch/arm/include/asm/gpio.h | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 333e407b66..7715a01706 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,12 +1,8 @@
 #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \
!defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \
-   !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \
-   !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \
-   !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \
-   !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \
-   !defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \
-   !defined(CONFIG_CORTINA_PLATFORM)
+   !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \
+   !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM)
 #include 
 #endif
 #include 
-- 
2.17.1

[PATCH 1/3] armv8: gpio: add gpio feature

[Hui Song]

From: "hui.song" 

add one struct mpc8xxx_gpio_plat to enable gpio feature.

Signed-off-by: hui.song 
---
 .../include/asm/arch-fsl-layerscape/gpio.h| 22 +++
 1 file changed, 22 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/gpio.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/gpio.h 
b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h
new file mode 100644
index 00..7ae5eee8b6
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes  via , so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_MX85XX_GPIO_H
+#define __ASM_ARCH_MX85XX_GPIO_H
+
+struct mpc8xxx_gpio_plat {
+   ulong addr;
+   ulong size;
+   uint ngpios;
+};
+
+#endif
-- 
2.17.1

[PATCH] serial: Corrected riscv_sbi console flag to ensure it loads at first time

[Kongou Hikari]

Signed-off-by: Kongou Hikari 
---
 arch/riscv/dts/nuclei-hbird.dts   | 1 -
 drivers/serial/serial_riscv_sbi.c | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/nuclei-hbird.dts b/arch/riscv/dts/nuclei-hbird.dts
index 39d76b63ba..aea6719b24 100644
--- a/arch/riscv/dts/nuclei-hbird.dts
+++ b/arch/riscv/dts/nuclei-hbird.dts
@@ -57,7 +57,6 @@
};
 
   console {
-   u-boot,dm-pre-reloc;
compatible = "sbi,console";
   };
 
diff --git a/drivers/serial/serial_riscv_sbi.c 
b/drivers/serial/serial_riscv_sbi.c
index add11be04e..5551b6fd44 100644
--- a/drivers/serial/serial_riscv_sbi.c
+++ b/drivers/serial/serial_riscv_sbi.c
@@ -101,4 +101,5 @@ U_BOOT_DRIVER(serial_riscv_sbi) = {
.id = UCLASS_SERIAL,
.of_match = serial_riscv_sbi_ids,
.ops= _riscv_sbi_ops,
+   .flags  = DM_FLAG_PRE_RELOC,
 };
-- 
2.17.1

[PATCH] serial: Add riscv_sbi console support

[光]

From: Kongou Hikari 

  - This patch supports debug serial and console from SBI syscall.

Signed-off-by: Kongou Hikari 
---
 drivers/serial/Kconfig|  17 +
 drivers/serial/Makefile   |   1 +
 drivers/serial/serial_riscv_sbi.c | 104 ++
 3 files changed, 122 insertions(+)
 create mode 100644 drivers/serial/serial_riscv_sbi.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 90e3983170..60dcf9bc9a 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -388,12 +388,20 @@ config DEBUG_UART_MTK
driver will be available until the real driver model serial is
running.

+
+config DEBUG_UART_RISCV_SBI
+bool "RISC-V SBI CONSOLE"
+depends on RISCV_SBI_CONSOLE
+help
+  Select this to enable a debug UART using RISC-V SBI console driver.
+
 endchoice

 config DEBUG_UART_BASE
  hex "Base address of UART"
  depends on DEBUG_UART
  default 0 if DEBUG_UART_SANDBOX
+ default 0 if DEBUG_UART_RISCV_SBI
  help
This is the base address of your UART for memory-mapped UARTs.

@@ -404,6 +412,7 @@ config DEBUG_UART_CLOCK
  int "UART input clock"
  depends on DEBUG_UART
  default 0 if DEBUG_UART_SANDBOX
+ default 0 if DEBUG_UART_RISCV_SBI
  help
The UART input clock determines the speed of the internal UART
circuitry. The baud rate is derived from this by dividing the input
@@ -481,6 +490,14 @@ config ALTERA_JTAG_UART_BYPASS
output will wait forever until a JTAG terminal is connected. If you
not are sure, say Y.

+config RISCV_SBI_CONSOLE
+ bool "RISC-V SBI console support"
+ depends on RISCV
+ help
+   This enables support for console via RISC-V SBI calls.
+
+   If you don't know what do to here, say Y.
+
 config ALTERA_UART
  bool "Altera UART support"
  depends on DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index e4a927..15b2a3ea6f 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_MXC_UART) += serial_mxc.o
 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
 obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
 obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
+obj-$(CONFIG_RISCV_SBI_CONSOLE) += serial_riscv_sbi.o
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
 endif
diff --git a/drivers/serial/serial_riscv_sbi.c 
b/drivers/serial/serial_riscv_sbi.c
new file mode 100644
index 00..add11be04e
--- /dev/null
+++ b/drivers/serial/serial_riscv_sbi.c
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2008 David Gibson, IBM Corporation
+ * Copyright (C) 2012 Regents of the University of California
+ * Copyright (C) 2020 Nuclei System Technologies
+ * Copyright (C) 2020 Ruigang Wan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+
+#ifdef CONFIG_DEBUG_UART_RISCV_SBI
+
+#include 
+
+
+static inline void _debug_uart_init(void)
+{
+ //Nothing
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ sbi_console_putchar(ch);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
+
+static int sbi_tty_pending_char = -1;
+
+static int sbi_tty_put(struct udevice *dev, const char ch)
+{
+
+ sbi_console_putchar(ch);
+
+ return 0;
+}
+
+static int sbi_tty_get(struct udevice *dev)
+{
+ int c;
+ if (sbi_tty_pending_char != -1)
+ {
+  c = sbi_tty_pending_char;
+  sbi_tty_pending_char = -1;
+ }
+ else
+ {
+  c = sbi_console_getchar();
+  if (c < 0)
+   return -EAGAIN;
+ }
+
+ return c;
+}
+
+static int sbi_tty_setbrg(struct udevice *dev, int baudrate)
+{
+ return 0;
+}
+
+static int sbi_tty_pending(struct udevice *dev, bool input)
+{
+ int c;
+ if (input)
+ {
+  if (sbi_tty_pending_char != -1)
+   return 1;
+
+  c = sbi_console_getchar();
+  if(c < 0)
+   return 0;
+  sbi_tty_pending_char = c;
+  return 1;
+ }
+ return 0;
+}
+
+static const struct udevice_id serial_riscv_sbi_ids[] = {
+ { .compatible = "sbi,console" },
+ { }
+};
+
+const struct dm_serial_ops serial_riscv_sbi_ops = {
+ .putc = sbi_tty_put,
+ .pending = sbi_tty_pending,
+ .getc = sbi_tty_get,
+ .setbrg = sbi_tty_setbrg,
+};
+
+U_BOOT_DRIVER(serial_riscv_sbi) = {
+ .name = "serial_riscv_sbi",
+ .id = UCLASS_SERIAL,
+ .of_match = serial_riscv_sbi_ids,
+ .ops = _riscv_sbi_ops,
+};
-- 
2.17.1

[PATCH] riscv: Add Nuclei Hummingbird (UX600) platform support

[光]

From: Kongou Hikari 

---
 arch/riscv/Kconfig  |   4 +
 arch/riscv/dts/Makefile |   1 +
 arch/riscv/dts/nuclei-hbird.dts | 132 
 board/nuclei/hbird/Kconfig  |  53 +
 board/nuclei/hbird/MAINTAINERS  |   6 ++
 board/nuclei/hbird/Makefile |   5 ++
 board/nuclei/hbird/hbird.c  |  27 +++
 configs/nuclei_hbird_defconfig  |  20 +
 include/configs/nuclei-hbird.h  |  46 +++
 9 files changed, 294 insertions(+)
 create mode 100644 arch/riscv/dts/nuclei-hbird.dts
 create mode 100644 board/nuclei/hbird/Kconfig
 create mode 100644 board/nuclei/hbird/MAINTAINERS
 create mode 100644 board/nuclei/hbird/Makefile
 create mode 100644 board/nuclei/hbird/hbird.c
 create mode 100644 configs/nuclei_hbird_defconfig
 create mode 100644 include/configs/nuclei-hbird.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fb5fe5afff..b2807c33d7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -11,6 +11,9 @@ choice
 config TARGET_AX25_AE350
  bool "Support ax25-ae350"

+config TARGET_NUCLEI_HBIRD
+ bool "Support Nuclei HBird"
+
 config TARGET_MICROCHIP_ICICLE
  bool "Support Microchip PolarFire-SoC Icicle Board"

@@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/fu540/Kconfig"
+source "board/nuclei/hbird/Kconfig"

 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 4f30e6936f..da86846f11 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@

 dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_NUCLEI_HBIRD) += nuclei-hbird.dtb

 targets += $(dtb-y)

diff --git a/arch/riscv/dts/nuclei-hbird.dts b/arch/riscv/dts/nuclei-hbird.dts
new file mode 100644
index 00..39d76b63ba
--- /dev/null
+++ b/arch/riscv/dts/nuclei-hbird.dts
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 22020 Nuclei System Technologies */
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ 32768
+
+/dts-v1/;
+
+/ {
+  #address-cells = <2>;
+  #size-cells = <2>;
+  compatible = "nuclei,ux600";
+  model = "nuclei,ux600";
+
+  chosen {
+ bootargs = "earlycon=sbi";
+ stdout-path = "serial0";
+  };
+
+  cpus {
+#address-cells = <1>;
+#size-cells = <0>;
+timebase-frequency = ;
+cpu0: cpu@0 {
+  device_type = "cpu";
+  reg = <0>;
+  status = "okay";
+  compatible = "riscv";
+  riscv,isa = "rv64imac";
+  mmu-type = "riscv,sv39";
+  clock-frequency = <800>;
+  cpu0_intc: interrupt-controller {
+#interrupt-cells = <1>;
+interrupt-controller;
+compatible = "riscv,cpu-intc";
+  };
+};
+  };
+
+  memory@A000 {
+device_type = "memory";
+reg = <0x0 0xA000 0x0 0x1000>;
+  };
+
+  soc {
+#address-cells = <2>;
+#size-cells = <2>;
+compatible = "nuclei,ux600", "simple-bus";
+ranges;
+  };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <800>;
+ clock-output-names = "hfclk";
+ };
+
+  console {
+ u-boot,dm-pre-reloc;
+ compatible = "sbi,console";
+  };
+
+  plic0: interrupt-controller@800 {
+ #interrupt-cells = <1>;
+ compatible = "riscv,plic0";
+ interrupt-controller;
+riscv,ndev = <53>;
+ interrupts-extended =
+ <_intc 11 _intc 9>;
+ reg = <0x0 0x800 0x0 0x400>;
+ };
+
+ uart0: serial@10013000 {
+compatible = "sifive,uart0";
+reg = <0x0 0x10013000 0x0 0x1000>;
+interrupt-parent = <>;
+interrupts = <4>;
+status = "disabled";
+ };
+
+ uart1: serial@10023000 {
+compatible = "sifive,uart0";
+reg = <0x0 0x10023000 0x0 0x1000>;
+interrupt-parent = <>;
+interrupts = <5>;
+status = "okay";
+ };
+
+ qspi0: spi@10014000 {
+ compatible = "sifive,spi0";
+ reg = <0x0 0x10014000 0x0 0x1000>;
+ #interrupt-parent = <>;
+ #interrupts = <51>;
+ clocks = <>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "gd25q32", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100>;
+ // m25p,fast-read;
+ #spi-tx-bus-width = <1>;
+ #spi-rx-bus-width = <1>;
+ };
+ };
+
+ qspi2: spi@10034000 {
+ compatible = "sifive,spi0";
+ reg = <0x0 0x10034000 0x0 0x1000>;
+ #interrupt-parent = <>;
+ #interrupts = <6>;
+ clocks = <>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ mmc@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <800>;
+ voltage-ranges = <3300 3300>;
+ disable-wp;
+ };
+ };
+
+
+};
diff --git a/board/nuclei/hbird/Kconfig b/board/nuclei/hbird/Kconfig
new file mode 100644
index 00..697182ba02
--- 

[PATCH 1/2] serial: Add riscv_sbi console support

[Kongou Hikari]

  - This patch supports debug serial and console from SBI syscall.

Signed-off-by: Kongou Hikari 
---
 drivers/serial/Kconfig|  17 +
 drivers/serial/Makefile   |   1 +
 drivers/serial/serial_riscv_sbi.c | 104 ++
 3 files changed, 122 insertions(+)
 create mode 100644 drivers/serial/serial_riscv_sbi.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 90e3983170..60dcf9bc9a 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -388,12 +388,20 @@ config DEBUG_UART_MTK
  driver will be available until the real driver model serial is
  running.
 
+
+config DEBUG_UART_RISCV_SBI
+bool "RISC-V SBI CONSOLE"
+depends on RISCV_SBI_CONSOLE
+help
+  Select this to enable a debug UART using RISC-V SBI console driver.
+
 endchoice
 
 config DEBUG_UART_BASE
hex "Base address of UART"
depends on DEBUG_UART
default 0 if DEBUG_UART_SANDBOX
+   default 0 if DEBUG_UART_RISCV_SBI
help
  This is the base address of your UART for memory-mapped UARTs.
 
@@ -404,6 +412,7 @@ config DEBUG_UART_CLOCK
int "UART input clock"
depends on DEBUG_UART
default 0 if DEBUG_UART_SANDBOX
+   default 0 if DEBUG_UART_RISCV_SBI
help
  The UART input clock determines the speed of the internal UART
  circuitry. The baud rate is derived from this by dividing the input
@@ -481,6 +490,14 @@ config ALTERA_JTAG_UART_BYPASS
  output will wait forever until a JTAG terminal is connected. If you
  not are sure, say Y.
 
+config RISCV_SBI_CONSOLE
+   bool "RISC-V SBI console support"
+   depends on RISCV
+   help
+ This enables support for console via RISC-V SBI calls.
+
+ If you don't know what do to here, say Y.
+
 config ALTERA_UART
bool "Altera UART support"
depends on DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index e4a927..15b2a3ea6f 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_MXC_UART) += serial_mxc.o
 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
 obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
 obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
+obj-$(CONFIG_RISCV_SBI_CONSOLE) += serial_riscv_sbi.o
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
 endif
diff --git a/drivers/serial/serial_riscv_sbi.c 
b/drivers/serial/serial_riscv_sbi.c
new file mode 100644
index 00..add11be04e
--- /dev/null
+++ b/drivers/serial/serial_riscv_sbi.c
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2008 David Gibson, IBM Corporation
+ * Copyright (C) 2012 Regents of the University of California
+ * Copyright (C) 2020 Nuclei System Technologies
+ * Copyright (C) 2020 Ruigang Wan 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+
+#ifdef CONFIG_DEBUG_UART_RISCV_SBI
+
+#include 
+
+
+static inline void _debug_uart_init(void)
+{
+   //Nothing
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+   sbi_console_putchar(ch);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
+
+static int sbi_tty_pending_char = -1;
+
+static int sbi_tty_put(struct udevice *dev, const char ch)
+{
+
+   sbi_console_putchar(ch);
+
+   return 0;
+}
+
+static int sbi_tty_get(struct udevice *dev)
+{
+   int c;
+   if (sbi_tty_pending_char != -1)
+   {
+   c = sbi_tty_pending_char;
+   sbi_tty_pending_char = -1;
+   }
+   else
+   {
+   c = sbi_console_getchar();
+   if (c < 0)
+   return -EAGAIN;
+   }
+
+   return c;
+}
+
+static int sbi_tty_setbrg(struct udevice *dev, int baudrate)
+{
+   return 0;
+}
+
+static int sbi_tty_pending(struct udevice *dev, bool input)
+{
+   int c;
+   if (input)
+   {
+   if (sbi_tty_pending_char != -1)
+   return 1;
+
+   c = sbi_console_getchar();
+   if(c < 0)
+   return 0;
+   sbi_tty_pending_char = c;
+   return 1;
+   }
+   return 0;
+}
+
+static const struct udevice_id serial_riscv_sbi_ids[] = {
+   { .compatible = "sbi,console" },
+   { }
+};
+
+const struct dm_serial_ops serial_riscv_sbi_ops = {
+   .putc = sbi_tty_put,
+   .pending = sbi_tty_pending,
+   .getc = sbi_tty_get,
+   .setbrg = sbi_tty_setbrg,
+};
+
+U_BOOT_DRIVER(serial_riscv_sbi) = {
+   .name   = "serial_riscv_sbi",
+   .id = UCLASS_SERIAL,
+   .of_match = serial_riscv_sbi_ids,
+   .ops= _riscv_sbi_ops,
+};
-- 
2.17.1

[PATCH 2/2] riscv: Add Nuclei Hummingbird (UX600) platform support

[Kongou Hikari]

---
 arch/riscv/Kconfig  |   4 +
 arch/riscv/dts/Makefile |   1 +
 arch/riscv/dts/nuclei-hbird.dts | 132 
 board/nuclei/hbird/Kconfig  |  53 +
 board/nuclei/hbird/MAINTAINERS  |   6 ++
 board/nuclei/hbird/Makefile |   5 ++
 board/nuclei/hbird/hbird.c  |  27 +++
 configs/nuclei_hbird_defconfig  |  20 +
 include/configs/nuclei-hbird.h  |  46 +++
 9 files changed, 294 insertions(+)
 create mode 100644 arch/riscv/dts/nuclei-hbird.dts
 create mode 100644 board/nuclei/hbird/Kconfig
 create mode 100644 board/nuclei/hbird/MAINTAINERS
 create mode 100644 board/nuclei/hbird/Makefile
 create mode 100644 board/nuclei/hbird/hbird.c
 create mode 100644 configs/nuclei_hbird_defconfig
 create mode 100644 include/configs/nuclei-hbird.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fb5fe5afff..b2807c33d7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -11,6 +11,9 @@ choice
 config TARGET_AX25_AE350
bool "Support ax25-ae350"
 
+config TARGET_NUCLEI_HBIRD
+   bool "Support Nuclei HBird"
+
 config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
 
@@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/fu540/Kconfig"
+source "board/nuclei/hbird/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 4f30e6936f..da86846f11 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
 
 dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_NUCLEI_HBIRD) += nuclei-hbird.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/riscv/dts/nuclei-hbird.dts b/arch/riscv/dts/nuclei-hbird.dts
new file mode 100644
index 00..39d76b63ba
--- /dev/null
+++ b/arch/riscv/dts/nuclei-hbird.dts
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 22020 Nuclei System Technologies */
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ32768
+
+/dts-v1/;
+
+/ {
+  #address-cells = <2>;
+  #size-cells = <2>;
+  compatible = "nuclei,ux600";
+  model = "nuclei,ux600";
+
+  chosen {
+ bootargs = "earlycon=sbi";
+ stdout-path = "serial0";
+  };
+
+  cpus {
+#address-cells = <1>;
+#size-cells = <0>;
+timebase-frequency = ;
+cpu0: cpu@0 {
+  device_type = "cpu";
+  reg = <0>;
+  status = "okay";
+  compatible = "riscv";
+  riscv,isa = "rv64imac";
+  mmu-type = "riscv,sv39";
+  clock-frequency = <800>;
+  cpu0_intc: interrupt-controller {
+#interrupt-cells = <1>;
+interrupt-controller;
+compatible = "riscv,cpu-intc";
+  };
+};
+  };
+
+  memory@A000 {
+device_type = "memory";
+reg = <0x0 0xA000 0x0 0x1000>;
+  };
+
+  soc {
+#address-cells = <2>;
+#size-cells = <2>;
+compatible = "nuclei,ux600", "simple-bus";
+ranges;
+  };
+
+   hfclk: hfclk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <800>;
+   clock-output-names = "hfclk";
+   };
+
+  console {
+   u-boot,dm-pre-reloc;
+   compatible = "sbi,console";
+  };
+
+  plic0: interrupt-controller@800 {
+   #interrupt-cells = <1>;
+   compatible = "riscv,plic0";
+   interrupt-controller;
+riscv,ndev = <53>;
+   interrupts-extended =
+   <_intc 11 _intc 9>;
+   reg = <0x0 0x800 0x0 0x400>;
+   };
+
+   uart0: serial@10013000 {
+compatible = "sifive,uart0";
+reg = <0x0 0x10013000 0x0 0x1000>;
+interrupt-parent = <>;
+interrupts = <4>;
+status = "disabled";
+   };
+
+   uart1: serial@10023000 {
+compatible = "sifive,uart0";
+reg = <0x0 0x10023000 0x0 0x1000>;
+interrupt-parent = <>;
+interrupts = <5>;
+status = "okay";
+   };
+
+   qspi0: spi@10014000 {
+   compatible = "sifive,spi0";
+   reg = <0x0 0x10014000 0x0 0x1000>;
+   #interrupt-parent = <>;
+   #interrupts = <51>;
+   clocks = <>;
+   num-cs = <1>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   flash@0 {
+   compatible = "gd25q32", "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <100>;
+   //  m25p,fast-read;

RE: [PATCH v2 1/6] arm: dts: lx2160a: add noted for dpmacs 1, 2, 5-6

[Priyanka Jain (OSS)]

>-Original Message-
>From: U-Boot  On Behalf Of Ioana Ciornei
>Sent: Monday, April 27, 2020 5:51 PM
>To: Priyanka Jain ; u-boot@lists.denx.de
>Cc: Alexandru Marginean ; Madalin Bucur
>; Florin Laurentiu Chiculita
>; Razvan Ionut Cirjan
>; Ioana Ciornei 
>Subject: [PATCH v2 1/6] arm: dts: lx2160a: add noted for dpmacs 1, 2, 5-6
>
>Add nodes for DPMACs 1, 2 and 5-6 which were missing from the description.
>These will be later used on the LX2160AQDS specific DTS.
>
>Signed-off-by: Ioana Ciornei 
>---
Series applied to u-boot-fsl-qoriq. Awaiting upstream.

Thanks
Priyanka

RE: [PATCH] board_r: Detect ifc-nor flash at run-time

[Priyanka Jain (OSS)]

>-Original Message-
>From: U-Boot  On Behalf Of Rajesh Bhagat
>Sent: Thursday, April 30, 2020 3:54 PM
>To: u-boot@lists.denx.de
>Cc: Priyanka Jain ; Pankit Garg
>
>Subject: [PATCH] board_r: Detect ifc-nor flash at run-time
>
>From: Pankit Garg 
>
>CONFIG_MTD_NOR_FLASH flag needs to be enable for all boot sources,as all
>flash drivers need to compile in TFA Boot.Probe ifc nor flash only when there
>is nor flash available on board.So needs to detect ifc-nor flash at run-time 
>for
>probing.
>
>Signed-off-by: Pankit Garg 
>---
Applied to u-boot-fsl-qoriq. Awaiting upstream.

Thanks
Priyanka

RE: [PATCH] net: fsl-mc: fixup DPC: add /board/ports node if missing

[Priyanka Jain (OSS)]

>-Original Message-
>From: U-Boot  On Behalf Of Razvan Ionut
>Cirjan
>Sent: Tuesday, April 28, 2020 6:40 PM
>To: Priyanka Jain ; joe.hershber...@ni.com; u-
>b...@lists.denx.de
>Cc: Ioana Ciornei ; Florin Laurentiu Chiculita
>; Cristi Sovaiala
>; Razvan Ionut Cirjan
>
>Subject: [PATCH] net: fsl-mc: fixup DPC: add /board/ports node if missing
>
>The DPC fixup for MAC address and enet_if is not made if /board/ports node
>is missing in DPC file.
>Add /board/ports or /ports nodes if them are missing.
>
>Signed-off-by: Razvan Ionut Cirjan 
>---
Applied to u-boot-fsl-qoriq. Awaiting upstream.

Thanks
Priyanka