Re: [PATCH 3/6] cmd: mem: Drop #ifdef for MEM_SUPPORT_64BIT_DATA
On 03.06.20 03:26, Simon Glass wrote:
This is defined only when __lp64__ is defined. That means that ulong is
64 bits long. Therefore we don't need to use a separate u64 type on those
architectures.
Fix up the code to take advantage of that, removing the preprocessor
conditions.
Signed-off-by: Simon Glass
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
cmd/mem.c | 117 ++
1 file changed, 38 insertions(+), 79 deletions(-)
diff --git a/cmd/mem.c b/cmd/mem.c
index da02bbce95..9ab6b1dd08 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -34,9 +34,11 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
/* Create a compile-time value */
-#if MEM_SUPPORT_64BIT_DATA
+#ifdef MEM_SUPPORT_64BIT_DATA
+#define SUPPORT_64BIT_DATA 1
#define HELP_Q ", .q"
#else
+#define SUPPORT_64BIT_DATA 0
#define HELP_Q ""
#endif
@@ -123,11 +125,7 @@ static int do_mem_nm(struct cmd_tbl *cmdtp, int flag, int argc,
static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
-#if MEM_SUPPORT_64BIT_DATA
- u64 writeval;
-#else
- ulong writeval;
-#endif
+ ulong writeval; /* 64-bit if SUPPORT_64BIT_DATA */
ulong addr, count;
int size;
void *buf, *start;
@@ -148,11 +146,10 @@ static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int
argc,
/* Get the value to write.
*/
-#if MEM_SUPPORT_64BIT_DATA
- writeval = simple_strtoull(argv[2], NULL, 16);
-#else
- writeval = simple_strtoul(argv[2], NULL, 16);
-#endif
+ if (SUPPORT_64BIT_DATA)
+ writeval = simple_strtoull(argv[2], NULL, 16);
+ else
+ writeval = simple_strtoul(argv[2], NULL, 16);
/* Count ? */
if (argc == 4) {
@@ -167,10 +164,8 @@ static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int
argc,
while (count-- > 0) {
if (size == 4)
*((u32 *)buf) = (u32)writeval;
-#if MEM_SUPPORT_64BIT_DATA
- else if (size == 8)
- *((u64 *)buf) = (u64)writeval;
-#endif
+ else if (SUPPORT_64BIT_DATA && size == 8)
+ *((ulong *)buf) = writeval;
else if (size == 2)
*((u16 *)buf) = (u16)writeval;
else
@@ -247,11 +242,7 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
int rcode = 0;
const char *type;
const void *buf1, *buf2, *base;
-#if MEM_SUPPORT_64BIT_DATA
- u64 word1, word2;
-#else
- ulong word1, word2;
-#endif
+ ulong word1, word2; /* 64-bit if SUPPORT_64BIT_DATA */
if (argc != 4)
return CMD_RET_USAGE;
@@ -279,11 +270,9 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
if (size == 4) {
word1 = *(u32 *)buf1;
word2 = *(u32 *)buf2;
-#if MEM_SUPPORT_64BIT_DATA
- } else if (size == 8) {
- word1 = *(u64 *)buf1;
- word2 = *(u64 *)buf2;
-#endif
+ } else if (SUPPORT_64BIT_DATA && size == 8) {
+ word1 = *(ulong *)buf1;
+ word2 = *(ulong *)buf2;
} else if (size == 2) {
word1 = *(u16 *)buf1;
word2 = *(u16 *)buf2;
@@ -293,15 +282,9 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
}
if (word1 != word2) {
ulong offset = buf1 - base;
-#if MEM_SUPPORT_64BIT_DATA
- printf("%s at 0x%p (%#0*llx) != %s at 0x%p (%#0*llx)\n",
- type, (void *)(addr1 + offset), size, word1,
- type, (void *)(addr2 + offset), size, word2);
-#else
printf("%s at 0x%08lx (%#0*lx) != %s at 0x%08lx
(%#0*lx)\n",
type, (ulong)(addr1 + offset), size, word1,
type, (ulong)(addr2 + offset), size, word2);
-#endif
rcode = 1;
break;
}
@@ -398,9 +381,7 @@ static int do_mem_loop(struct cmd_tbl *cmdtp, int flag, int
argc,
{
ulong addr, length, i, bytes;
int size;
-#if MEM_SUPPORT_64BIT_DATA
- volatile u64 *llp;
-#endif
+ volatile ulong *llp; /* 64-bit if SUPPORT_64BIT_DATA */
volatile u32 *longp;
volatile u16 *shortp;
volatile u8 *cp;
@@ -431,13 +412,11 @@ static int do_mem_loop(struct cmd_tbl *cmdtp, int flag,
int argc,
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
-#if MEM_SUPPORT_64BIT_DATA
- if (size == 8) {
- llp = (u64 *)buf;
+ if (SUPPORT_64BIT_DATA && size == 8) {
+ llp = (ulong *)buf;
for
Re: [PATCH 2/6] cmd: mem: Use a macro to avoid #ifdef in help
On 03.06.20 03:26, Simon Glass wrote:
It is a bit painful to have #ifdefs in the middle of the help for each
command. Add a macro to avoid this.
Signed-off-by: Simon Glass
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
cmd/mem.c | 68 ++-
1 file changed, 17 insertions(+), 51 deletions(-)
diff --git a/cmd/mem.c b/cmd/mem.c
index fe43427d3c..da02bbce95 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -33,6 +33,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define CONFIG_SYS_MEMTEST_SCRATCH 0
#endif
+/* Create a compile-time value */
+#if MEM_SUPPORT_64BIT_DATA
+#define HELP_Q ", .q"
+#else
+#define HELP_Q ""
+#endif
+
static int mod_mem(struct cmd_tbl *, int, int, int, char * const []);
/* Display values from last command.
@@ -1016,7 +1023,6 @@ static int do_mem_mtest(struct cmd_tbl *cmdtp, int flag,
int argc,
*
* Syntax:
*mm{.b, .w, .l, .q} {addr}
- * nm{.b, .w, .l, .q} {addr}
*/
static int
mod_mem(struct cmd_tbl *cmdtp, int incrflag, int flag, int argc,
@@ -1196,63 +1202,39 @@ static int do_random(struct cmd_tbl *cmdtp, int flag,
int argc,
U_BOOT_CMD(
md, 3, 1, do_mem_md,
"memory display",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address [# of objects]"
-#else
- "[.b, .w, .l] address [# of objects]"
-#endif
+ "[.b, .w, .l" HELP_Q "] address [# of objects]"
);
U_BOOT_CMD(
mm, 2, 1, do_mem_mm,
"memory modify (auto-incrementing address)",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address"
-#else
- "[.b, .w, .l] address"
-#endif
+ "[.b, .w, .l" HELP_Q "] address"
);
U_BOOT_CMD(
nm, 2, 1, do_mem_nm,
"memory modify (constant address)",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address"
-#else
- "[.b, .w, .l] address"
-#endif
+ "[.b, .w, .l" HELP_Q "] address"
);
U_BOOT_CMD(
mw, 4, 1, do_mem_mw,
"memory write (fill)",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address value [count]"
-#else
- "[.b, .w, .l] address value [count]"
-#endif
+ "[.b, .w, .l" HELP_Q "] address value [count]"
);
U_BOOT_CMD(
cp, 4, 1, do_mem_cp,
"memory copy",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] source target count"
-#else
- "[.b, .w, .l] source target count"
-#endif
+ "[.b, .w, .l" HELP_Q "] source target count"
);
U_BOOT_CMD(
cmp,4, 1, do_mem_cmp,
"memory compare",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] addr1 addr2 count"
-#else
- "[.b, .w, .l] addr1 addr2 count"
-#endif
+ "[.b, .w, .l" HELP_Q "] addr1 addr2 count"
);
#ifdef CONFIG_CMD_CRC32
@@ -1299,22 +1281,14 @@ U_BOOT_CMD(
U_BOOT_CMD(
loop, 3, 1, do_mem_loop,
"infinite loop on address range",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address number_of_objects"
-#else
- "[.b, .w, .l] address number_of_objects"
-#endif
+ "[.b, .w, .l" HELP_Q "] address number_of_objects"
);
#ifdef CONFIG_LOOPW
U_BOOT_CMD(
loopw, 4, 1, do_mem_loopw,
"infinite write loop on address range",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address number_of_objects data_to_write"
-#else
- "[.b, .w, .l] address number_of_objects data_to_write"
-#endif
+ "[.b, .w, .l" HELP_Q "] address number_of_objects data_to_write"
);
#endif /* CONFIG_LOOPW */
@@ -1330,21 +1304,13 @@ U_BOOT_CMD(
U_BOOT_CMD(
mdc,4, 1, do_mem_mdc,
"memory display cyclic",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address count delay(ms)"
-#else
- "[.b, .w, .l] address count delay(ms)"
-#endif
+ "[.b, .w, .l" HELP_Q "] address count delay(ms)"
);
U_BOOT_CMD(
mwc,4, 1, do_mem_mwc,
"memory write cyclic",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address value delay(ms)"
-#else
- "[.b, .w, .l] address value delay(ms)"
-#endif
+ "[.b, .w, .l" HELP_Q "] address value delay(ms)"
);
#endif /* CONFIG_CMD_MX_CYCLIC */
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 1/6] Update MEM_SUPPORT_64BIT_DATA to be always defined
On 03.06.20 03:26, Simon Glass wrote:
Define this macro always so we don't need the preprocessor to check it.
Convert the users to #if instead of #ifdef.
Note that '#if MEM_SUPPORT_64BIT_DATA' does not give an error if the
macro is not define. It just assumes zero.
Signed-off-by: Simon Glass
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
cmd/mem.c | 54 +--
common/command.c | 2 +-
include/compiler.h| 4 +++-
lib/display_options.c | 6 ++---
4 files changed, 34 insertions(+), 32 deletions(-)
diff --git a/cmd/mem.c b/cmd/mem.c
index 9b97f7bf69..fe43427d3c 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -116,7 +116,7 @@ static int do_mem_nm(struct cmd_tbl *cmdtp, int flag, int
argc,
static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
u64 writeval;
#else
ulong writeval;
@@ -141,7 +141,7 @@ static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int
argc,
/* Get the value to write.
*/
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
writeval = simple_strtoull(argv[2], NULL, 16);
#else
writeval = simple_strtoul(argv[2], NULL, 16);
@@ -160,7 +160,7 @@ static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int
argc,
while (count-- > 0) {
if (size == 4)
*((u32 *)buf) = (u32)writeval;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
else if (size == 8)
*((u64 *)buf) = (u64)writeval;
#endif
@@ -240,7 +240,7 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
int rcode = 0;
const char *type;
const void *buf1, *buf2, *base;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
u64 word1, word2;
#else
ulong word1, word2;
@@ -272,7 +272,7 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
if (size == 4) {
word1 = *(u32 *)buf1;
word2 = *(u32 *)buf2;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
} else if (size == 8) {
word1 = *(u64 *)buf1;
word2 = *(u64 *)buf2;
@@ -286,7 +286,7 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
}
if (word1 != word2) {
ulong offset = buf1 - base;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
printf("%s at 0x%p (%#0*llx) != %s at 0x%p (%#0*llx)\n",
type, (void *)(addr1 + offset), size, word1,
type, (void *)(addr2 + offset), size, word2);
@@ -391,7 +391,7 @@ static int do_mem_loop(struct cmd_tbl *cmdtp, int flag, int
argc,
{
ulong addr, length, i, bytes;
int size;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
volatile u64 *llp;
#endif
volatile u32 *longp;
@@ -424,7 +424,7 @@ static int do_mem_loop(struct cmd_tbl *cmdtp, int flag, int
argc,
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
if (size == 8) {
llp = (u64 *)buf;
for (;;)
@@ -446,7 +446,7 @@ static int do_mem_loop(struct cmd_tbl *cmdtp, int flag, int
argc,
i = *cp;
}
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
if (size == 8) {
for (;;) {
llp = (u64 *)buf;
@@ -489,7 +489,7 @@ static int do_mem_loopw(struct cmd_tbl *cmdtp, int flag,
int argc,
{
ulong addr, length, i, bytes;
int size;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
volatile u64 *llp;
u64 data;
#else
@@ -519,7 +519,7 @@ static int do_mem_loopw(struct cmd_tbl *cmdtp, int flag,
int argc,
length = simple_strtoul(argv[2], NULL, 16);
/* data to write */
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
data = simple_strtoull(argv[3], NULL, 16);
#else
data = simple_strtoul(argv[3], NULL, 16);
@@ -532,7 +532,7 @@ static int do_mem_loopw(struct cmd_tbl *cmdtp, int flag,
int argc,
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
if (size == 8) {
llp = (u64 *)buf;
for (;;)
@@ -554,7 +554,7 @@ static int do_mem_loopw(struct cmd_tbl *cmdtp, int flag,
int argc,
*cp = data;
}
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
if (size == 8) {
for (;;) {
Re: [PATCH v2] i2c: octeon_i2c: Add I2C controller driver for Octeon
On Tue, May 26, 2020 at 5:43 PM Stefan Roese wrote:
>
> From: Suneel Garapati
>
> Add support for I2C controllers found on Octeon II/III and Octeon TX
> TX2 SoC platforms.
>
> Signed-off-by: Aaron Williams
> Signed-off-by: Suneel Garapati
> Signed-off-by: Stefan Roese
> Cc: Heiko Schocher
> Cc: Simon Glass
> Cc: Daniel Schwierzeck
> Cc: Aaron Williams
> Cc: Chandrakala Chavva
> ---
> v2 (Stefan):
> - Added clk framework support and dropped ad-hoc clock code
> - Removed #ifdef's for Octeon vs OcteonTX/TX2 completely
> The differentiation is now made via driver data / compatible
> string
> - Added device-tree bindings documentation
> - Removed unused macro
>
> RFC -> v1 (Stefan):
> - Separated this patch from the OcteonTX/TX2 RFC patch series into a
> single patch. This is useful, as the upcoming MIPS Octeon support will
> use this I2C driver.
> - Added MIPS Octeon II/III support (big endian). Rename driver and its
> function names from "octeontx" to "octeon" to better match all Octeon
> platforms.
> - Moved from union to defines / bitmasks as suggested by Simon. This makes
> the driver usage on little- and big-endian platforms much easier.
> - Enhanced Kconfig text
> - Removed all clock macros (use values from DT)
> - Removed long driver debug strings. This is only available when a debug
> version of this driver is built. The user / developer can lookup the
> descriptive error messages in the driver in this case anyway.
> - Removed static "last_id"
> - Dropped misc blank lines. Misc reformatting.
> - Dropped "!= 0"
> - Added missing function comments
> - Added missing strut comments
> - Changed comment style
> - Renames "result" to "ret"
> - Hex numbers uppercase
> - Minor other changes
> - Reword commit text and subject
>
> doc/device-tree-bindings/i2c/octeon-i2c.txt | 24 +
> drivers/i2c/Kconfig | 10 +
> drivers/i2c/Makefile| 1 +
> drivers/i2c/octeon_i2c.c| 847
> 4 files changed, 882 insertions(+)
> create mode 100644 doc/device-tree-bindings/i2c/octeon-i2c.txt
> create mode 100644 drivers/i2c/octeon_i2c.c
Reviewed-by: Rayagonda Kokatanur
>
> diff --git a/doc/device-tree-bindings/i2c/octeon-i2c.txt
> b/doc/device-tree-bindings/i2c/octeon-i2c.txt
> new file mode 100644
> index 00..9c1908ec2c
> --- /dev/null
> +++ b/doc/device-tree-bindings/i2c/octeon-i2c.txt
> @@ -0,0 +1,24 @@
> +* I2C controller embedded in Marvell Octeon platforms
> +
> +Required properties :
> +- compatible : Must be "cavium,octeon-7890-twsi" or a compatible string
> +- reg : Offset and length of the register set for the device
> +- clocks: Must contain the input clock of the I2C instance
> +- #address-cells = <1>;
> +- #size-cells = <0>;
> +
> +Optional properties :
> +- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
> + the default 100 kHz frequency will be used. As only Normal, Fast and Fast+
> + modes are implemented, possible values are 10, 40 and 100.
> +
> +Example :
> +
> + i2c0: i2c@118001000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "cavium,octeon-7890-twsi";
> + reg = <0x11800 0x1000 0x0 0x200>;
> + clock-frequency = <10>;
> + clocks = <>;
> + };
> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
> index f8b18de8f3..363b899e9c 100644
> --- a/drivers/i2c/Kconfig
> +++ b/drivers/i2c/Kconfig
> @@ -374,6 +374,16 @@ config SYS_I2C_SANDBOX
> bus. Devices can be attached to the bus using the device tree
> which specifies the driver to use. See sandbox.dts as an example.
>
> +config SYS_I2C_OCTEON
> + bool "Octeon II/III/TX/TX2 I2C driver"
> + depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
> + default y
> + help
> + Add support for the Marvell Octeon I2C driver. This is used with
> + various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
> + chips have several I2C ports and all are provided, controlled by
> + the device tree.
> +
> config SYS_I2C_S3C24X0
> bool "Samsung I2C driver"
> depends on ARCH_EXYNOS4 && DM_I2C
> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
> index 62935b7ebc..2b58aae892 100644
> --- a/drivers/i2c/Makefile
> +++ b/drivers/i2c/Makefile
> @@ -27,6 +27,7 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
> obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
> obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
> obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
> +obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
> obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
> obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
> obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
> diff --git a/drivers/i2c/octeon_i2c.c b/drivers/i2c/octeon_i2c.c
> new file mode 100644
> index 00..c11d6ff93d
> --- /dev/null
>
Re: [PATCH v1] i2c: octeon_i2c: Add I2C controller driver for Octeon
On 03.06.20 07:37, Rayagonda Kokatanur wrote: On Wed, Jun 3, 2020 at 10:50 AM Stefan Roese wrote: Hi Rayagonda, v1 is superseeded. Please review the latest version, v2: https://patchwork.ozlabs.org/project/uboot/patch/20200526121307.2735-1...@denx.de/ Thank you, I missed that v2. Anyway please ignore my comments, all of them are fixed in v2. Good. Could you please send a Reviewed-by tag then? Thanks, Stefan Thanks, Rayagonda Thanks, Stefan On 03.06.20 07:15, Rayagonda Kokatanur wrote: Hi Stefan, Few minor comments, On Thu, May 14, 2020 at 12:53 PM Stefan Roese wrote: From: Suneel Garapati Add support for I2C controllers found on Octeon II/III and Octeon TX TX2 SoC platforms. Signed-off-by: Aaron Williams Signed-off-by: Suneel Garapati Signed-off-by: Stefan Roese Cc: Heiko Schocher Cc: Simon Glass Cc: Daniel Schwierzeck Cc: Aaron Williams Cc: Chandrakala Chavva --- RFC -> v1 (Stefan): - Separated this patch from the OcteonTX/TX2 RFC patch series into a single patch. This is useful, as the upcoming MIPS Octeon support will use this I2C driver. - Added MIPS Octeon II/III support (big endian). Rename driver and its function names from "octeontx" to "octeon" to better match all Octeon platforms. - Moved from union to defines / bitmasks as suggested by Simon. This makes the driver usage on little- and big-endian platforms much easier. - Enhanced Kconfig text - Removed all clock macros (use values from DT) - Removed long driver debug strings. This is only available when a debug version of this driver is built. The user / developer can lookup the descriptive error messages in the driver in this case anyway. - Removed static "last_id" - Dropped misc blank lines. Misc reformatting. - Dropped "!= 0" - Added missing function comments - Added missing strut comments - Changed comment style - Renames "result" to "ret" - Hex numbers uppercase - Minor other changes - Reword commit text and subject drivers/i2c/Kconfig | 10 + drivers/i2c/Makefile | 1 + drivers/i2c/octeon_i2c.c | 803 +++ 3 files changed, 814 insertions(+) create mode 100644 drivers/i2c/octeon_i2c.c diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index e42b6516bf..1330b36698 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -374,6 +374,16 @@ config SYS_I2C_SANDBOX bus. Devices can be attached to the bus using the device tree which specifies the driver to use. See sandbox.dts as an example. +config SYS_I2C_OCTEON + bool "Octeon II/III/TX/TX2 I2C driver" + depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C + default y + help + Add support for the Marvell Octeon I2C driver. This is used with + various Octeon parts such as Octeon II/III and OcteonTX/TX2. All + chips have several I2C ports and all are provided, controlled by + the device tree. + config SYS_I2C_S3C24X0 bool "Samsung I2C driver" depends on ARCH_EXYNOS4 && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 62935b7ebc..2b58aae892 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o +obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o diff --git a/drivers/i2c/octeon_i2c.c b/drivers/i2c/octeon_i2c.c new file mode 100644 index 00..210f98655e --- /dev/null +++ b/drivers/i2c/octeon_i2c.c @@ -0,0 +1,803 @@ +// SPDX-License-Identifier:GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. Should it be 2020 ? + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * Octeon II/III (MIPS) have different register offsets than the ARM based + * Octeon TX/TX2 SoCs + */ +#if defined(CONFIG_ARCH_OCTEON) +#define REG_OFFS 0x +#else +#define REG_OFFS 0x1000 +#endif How about getting this offset from dt ? + +#define TWSI_SW_TWSI (REG_OFFS + 0x00) +#define TWSI_TWSI_SW (REG_OFFS + 0x08) +#define TWSI_INT (REG_OFFS + 0x10) +#define TWSI_SW_TWSI_EXT (REG_OFFS + 0x18) + +#define TWSI_SW_DATA_MASK GENMASK_ULL(31, 0) +#define TWSI_SW_EOP_IA_MASKGENMASK_ULL(34, 32) +#define TWSI_SW_IA_MASKGENMASK_ULL(39, 35) +#define TWSI_SW_ADDR_MASK GENMASK_ULL(49, 40) +#define TWSI_SW_SCR_MASK GENMASK_ULL(51, 50) +#define TWSI_SW_SIZE_MASK GENMASK_ULL(54, 52) +#define TWSI_SW_SOVR BIT_ULL(55) +#define TWSI_SW_R BIT_ULL(56) +#define TWSI_SW_OP_MASKGENMASK_ULL(60, 57) +#define TWSI_SW_EIA
Re: [PATCH v1] i2c: octeon_i2c: Add I2C controller driver for Octeon
On Wed, Jun 3, 2020 at 10:50 AM Stefan Roese wrote: > > Hi Rayagonda, > > v1 is superseeded. Please review the latest version, v2: > > https://patchwork.ozlabs.org/project/uboot/patch/20200526121307.2735-1...@denx.de/ Thank you, I missed that v2. Anyway please ignore my comments, all of them are fixed in v2. Thanks, Rayagonda > > Thanks, > Stefan > > On 03.06.20 07:15, Rayagonda Kokatanur wrote: > > Hi Stefan, > > > > Few minor comments, > > > > On Thu, May 14, 2020 at 12:53 PM Stefan Roese wrote: > >> > >> From: Suneel Garapati > >> > >> Add support for I2C controllers found on Octeon II/III and Octeon TX > >> TX2 SoC platforms. > >> > >> Signed-off-by: Aaron Williams > >> Signed-off-by: Suneel Garapati > >> Signed-off-by: Stefan Roese > >> Cc: Heiko Schocher > >> Cc: Simon Glass > >> Cc: Daniel Schwierzeck > >> Cc: Aaron Williams > >> Cc: Chandrakala Chavva > >> --- > >> RFC -> v1 (Stefan): > >> - Separated this patch from the OcteonTX/TX2 RFC patch series into a > >>single patch. This is useful, as the upcoming MIPS Octeon support will > >>use this I2C driver. > >> - Added MIPS Octeon II/III support (big endian). Rename driver and its > >>function names from "octeontx" to "octeon" to better match all Octeon > >>platforms. > >> - Moved from union to defines / bitmasks as suggested by Simon. This makes > >>the driver usage on little- and big-endian platforms much easier. > >> - Enhanced Kconfig text > >> - Removed all clock macros (use values from DT) > >> - Removed long driver debug strings. This is only available when a debug > >>version of this driver is built. The user / developer can lookup the > >>descriptive error messages in the driver in this case anyway. > >> - Removed static "last_id" > >> - Dropped misc blank lines. Misc reformatting. > >> - Dropped "!= 0" > >> - Added missing function comments > >> - Added missing strut comments > >> - Changed comment style > >> - Renames "result" to "ret" > >> - Hex numbers uppercase > >> - Minor other changes > >> - Reword commit text and subject > >> > >> drivers/i2c/Kconfig | 10 + > >> drivers/i2c/Makefile | 1 + > >> drivers/i2c/octeon_i2c.c | 803 +++ > >> 3 files changed, 814 insertions(+) > >> create mode 100644 drivers/i2c/octeon_i2c.c > >> > >> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig > >> index e42b6516bf..1330b36698 100644 > >> --- a/drivers/i2c/Kconfig > >> +++ b/drivers/i2c/Kconfig > >> @@ -374,6 +374,16 @@ config SYS_I2C_SANDBOX > >>bus. Devices can be attached to the bus using the device tree > >>which specifies the driver to use. See sandbox.dts as an > >> example. > >> > >> +config SYS_I2C_OCTEON > >> + bool "Octeon II/III/TX/TX2 I2C driver" > >> + depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && > >> DM_I2C > >> + default y > >> + help > >> + Add support for the Marvell Octeon I2C driver. This is used with > >> + various Octeon parts such as Octeon II/III and OcteonTX/TX2. All > >> + chips have several I2C ports and all are provided, controlled by > >> + the device tree. > >> + > >> config SYS_I2C_S3C24X0 > >> bool "Samsung I2C driver" > >> depends on ARCH_EXYNOS4 && DM_I2C > >> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile > >> index 62935b7ebc..2b58aae892 100644 > >> --- a/drivers/i2c/Makefile > >> +++ b/drivers/i2c/Makefile > >> @@ -27,6 +27,7 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o > >> obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o > >> obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o > >> obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o > >> +obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o > >> obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o > >> obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o > >> obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o > >> diff --git a/drivers/i2c/octeon_i2c.c b/drivers/i2c/octeon_i2c.c > >> new file mode 100644 > >> index 00..210f98655e > >> --- /dev/null > >> +++ b/drivers/i2c/octeon_i2c.c > >> @@ -0,0 +1,803 @@ > >> +// SPDX-License-Identifier:GPL-2.0 > >> +/* > >> + * Copyright (C) 2018 Marvell International Ltd. > > > > Should it be 2020 ? > >> + */ > >> + > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> + > >> +/* > >> + * Octeon II/III (MIPS) have different register offsets than the ARM based > >> + * Octeon TX/TX2 SoCs > >> + */ > >> +#if defined(CONFIG_ARCH_OCTEON) > >> +#define REG_OFFS 0x > >> +#else > >> +#define REG_OFFS 0x1000 > >> +#endif > > > > How about getting this offset from dt ? > >> + > >> +#define TWSI_SW_TWSI (REG_OFFS + 0x00) > >> +#define TWSI_TWSI_SW (REG_OFFS + 0x08) > >> +#define TWSI_INT (REG_OFFS + 0x10) > >> +#define TWSI_SW_TWSI_EXT (REG_OFFS + 0x18) > >> + > >> +#define TWSI_SW_DATA_MASK
Re: [PATCH v1] i2c: octeon_i2c: Add I2C controller driver for Octeon
Hi Rayagonda,
v1 is superseeded. Please review the latest version, v2:
https://patchwork.ozlabs.org/project/uboot/patch/20200526121307.2735-1...@denx.de/
Thanks,
Stefan
On 03.06.20 07:15, Rayagonda Kokatanur wrote:
Hi Stefan,
Few minor comments,
On Thu, May 14, 2020 at 12:53 PM Stefan Roese wrote:
From: Suneel Garapati
Add support for I2C controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
Signed-off-by: Stefan Roese
Cc: Heiko Schocher
Cc: Simon Glass
Cc: Daniel Schwierzeck
Cc: Aaron Williams
Cc: Chandrakala Chavva
---
RFC -> v1 (Stefan):
- Separated this patch from the OcteonTX/TX2 RFC patch series into a
single patch. This is useful, as the upcoming MIPS Octeon support will
use this I2C driver.
- Added MIPS Octeon II/III support (big endian). Rename driver and its
function names from "octeontx" to "octeon" to better match all Octeon
platforms.
- Moved from union to defines / bitmasks as suggested by Simon. This makes
the driver usage on little- and big-endian platforms much easier.
- Enhanced Kconfig text
- Removed all clock macros (use values from DT)
- Removed long driver debug strings. This is only available when a debug
version of this driver is built. The user / developer can lookup the
descriptive error messages in the driver in this case anyway.
- Removed static "last_id"
- Dropped misc blank lines. Misc reformatting.
- Dropped "!= 0"
- Added missing function comments
- Added missing strut comments
- Changed comment style
- Renames "result" to "ret"
- Hex numbers uppercase
- Minor other changes
- Reword commit text and subject
drivers/i2c/Kconfig | 10 +
drivers/i2c/Makefile | 1 +
drivers/i2c/octeon_i2c.c | 803 +++
3 files changed, 814 insertions(+)
create mode 100644 drivers/i2c/octeon_i2c.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index e42b6516bf..1330b36698 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -374,6 +374,16 @@ config SYS_I2C_SANDBOX
bus. Devices can be attached to the bus using the device tree
which specifies the driver to use. See sandbox.dts as an example.
+config SYS_I2C_OCTEON
+ bool "Octeon II/III/TX/TX2 I2C driver"
+ depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
+ default y
+ help
+ Add support for the Marvell Octeon I2C driver. This is used with
+ various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
+ chips have several I2C ports and all are provided, controlled by
+ the device tree.
+
config SYS_I2C_S3C24X0
bool "Samsung I2C driver"
depends on ARCH_EXYNOS4 && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 62935b7ebc..2b58aae892 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
diff --git a/drivers/i2c/octeon_i2c.c b/drivers/i2c/octeon_i2c.c
new file mode 100644
index 00..210f98655e
--- /dev/null
+++ b/drivers/i2c/octeon_i2c.c
@@ -0,0 +1,803 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
Should it be 2020 ?
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * Octeon II/III (MIPS) have different register offsets than the ARM based
+ * Octeon TX/TX2 SoCs
+ */
+#if defined(CONFIG_ARCH_OCTEON)
+#define REG_OFFS 0x
+#else
+#define REG_OFFS 0x1000
+#endif
How about getting this offset from dt ?
+
+#define TWSI_SW_TWSI (REG_OFFS + 0x00)
+#define TWSI_TWSI_SW (REG_OFFS + 0x08)
+#define TWSI_INT (REG_OFFS + 0x10)
+#define TWSI_SW_TWSI_EXT (REG_OFFS + 0x18)
+
+#define TWSI_SW_DATA_MASK GENMASK_ULL(31, 0)
+#define TWSI_SW_EOP_IA_MASKGENMASK_ULL(34, 32)
+#define TWSI_SW_IA_MASKGENMASK_ULL(39, 35)
+#define TWSI_SW_ADDR_MASK GENMASK_ULL(49, 40)
+#define TWSI_SW_SCR_MASK GENMASK_ULL(51, 50)
+#define TWSI_SW_SIZE_MASK GENMASK_ULL(54, 52)
+#define TWSI_SW_SOVR BIT_ULL(55)
+#define TWSI_SW_R BIT_ULL(56)
+#define TWSI_SW_OP_MASKGENMASK_ULL(60, 57)
+#define TWSI_SW_EIAGENMASK_ULL(61)
+#define TWSI_SW_SLONLY BIT_ULL(62)
+#define TWSI_SW_V BIT_ULL(63)
+
+#define TWSI_INT_SDA_OVR BIT_ULL(8)
+#define TWSI_INT_SCL_OVR BIT_ULL(9)
+#define TWSI_INT_SDA BIT_ULL(10)
+#define TWSI_INT_SCL BIT_ULL(11)
+
+enum {
+ TWSI_OP_WRITE = 0,
Re: [PATCH v1] i2c: octeon_i2c: Add I2C controller driver for Octeon
Hi Stefan,
Few minor comments,
On Thu, May 14, 2020 at 12:53 PM Stefan Roese wrote:
>
> From: Suneel Garapati
>
> Add support for I2C controllers found on Octeon II/III and Octeon TX
> TX2 SoC platforms.
>
> Signed-off-by: Aaron Williams
> Signed-off-by: Suneel Garapati
> Signed-off-by: Stefan Roese
> Cc: Heiko Schocher
> Cc: Simon Glass
> Cc: Daniel Schwierzeck
> Cc: Aaron Williams
> Cc: Chandrakala Chavva
> ---
> RFC -> v1 (Stefan):
> - Separated this patch from the OcteonTX/TX2 RFC patch series into a
> single patch. This is useful, as the upcoming MIPS Octeon support will
> use this I2C driver.
> - Added MIPS Octeon II/III support (big endian). Rename driver and its
> function names from "octeontx" to "octeon" to better match all Octeon
> platforms.
> - Moved from union to defines / bitmasks as suggested by Simon. This makes
> the driver usage on little- and big-endian platforms much easier.
> - Enhanced Kconfig text
> - Removed all clock macros (use values from DT)
> - Removed long driver debug strings. This is only available when a debug
> version of this driver is built. The user / developer can lookup the
> descriptive error messages in the driver in this case anyway.
> - Removed static "last_id"
> - Dropped misc blank lines. Misc reformatting.
> - Dropped "!= 0"
> - Added missing function comments
> - Added missing strut comments
> - Changed comment style
> - Renames "result" to "ret"
> - Hex numbers uppercase
> - Minor other changes
> - Reword commit text and subject
>
> drivers/i2c/Kconfig | 10 +
> drivers/i2c/Makefile | 1 +
> drivers/i2c/octeon_i2c.c | 803 +++
> 3 files changed, 814 insertions(+)
> create mode 100644 drivers/i2c/octeon_i2c.c
>
> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
> index e42b6516bf..1330b36698 100644
> --- a/drivers/i2c/Kconfig
> +++ b/drivers/i2c/Kconfig
> @@ -374,6 +374,16 @@ config SYS_I2C_SANDBOX
> bus. Devices can be attached to the bus using the device tree
> which specifies the driver to use. See sandbox.dts as an example.
>
> +config SYS_I2C_OCTEON
> + bool "Octeon II/III/TX/TX2 I2C driver"
> + depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
> + default y
> + help
> + Add support for the Marvell Octeon I2C driver. This is used with
> + various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
> + chips have several I2C ports and all are provided, controlled by
> + the device tree.
> +
> config SYS_I2C_S3C24X0
> bool "Samsung I2C driver"
> depends on ARCH_EXYNOS4 && DM_I2C
> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
> index 62935b7ebc..2b58aae892 100644
> --- a/drivers/i2c/Makefile
> +++ b/drivers/i2c/Makefile
> @@ -27,6 +27,7 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
> obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
> obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
> obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
> +obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
> obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
> obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
> obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
> diff --git a/drivers/i2c/octeon_i2c.c b/drivers/i2c/octeon_i2c.c
> new file mode 100644
> index 00..210f98655e
> --- /dev/null
> +++ b/drivers/i2c/octeon_i2c.c
> @@ -0,0 +1,803 @@
> +// SPDX-License-Identifier:GPL-2.0
> +/*
> + * Copyright (C) 2018 Marvell International Ltd.
Should it be 2020 ?
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/*
> + * Octeon II/III (MIPS) have different register offsets than the ARM based
> + * Octeon TX/TX2 SoCs
> + */
> +#if defined(CONFIG_ARCH_OCTEON)
> +#define REG_OFFS 0x
> +#else
> +#define REG_OFFS 0x1000
> +#endif
How about getting this offset from dt ?
> +
> +#define TWSI_SW_TWSI (REG_OFFS + 0x00)
> +#define TWSI_TWSI_SW (REG_OFFS + 0x08)
> +#define TWSI_INT (REG_OFFS + 0x10)
> +#define TWSI_SW_TWSI_EXT (REG_OFFS + 0x18)
> +
> +#define TWSI_SW_DATA_MASK GENMASK_ULL(31, 0)
> +#define TWSI_SW_EOP_IA_MASKGENMASK_ULL(34, 32)
> +#define TWSI_SW_IA_MASKGENMASK_ULL(39, 35)
> +#define TWSI_SW_ADDR_MASK GENMASK_ULL(49, 40)
> +#define TWSI_SW_SCR_MASK GENMASK_ULL(51, 50)
> +#define TWSI_SW_SIZE_MASK GENMASK_ULL(54, 52)
> +#define TWSI_SW_SOVR BIT_ULL(55)
> +#define TWSI_SW_R BIT_ULL(56)
> +#define TWSI_SW_OP_MASKGENMASK_ULL(60, 57)
> +#define TWSI_SW_EIAGENMASK_ULL(61)
> +#define TWSI_SW_SLONLY BIT_ULL(62)
> +#define TWSI_SW_V BIT_ULL(63)
> +
> +#define TWSI_INT_SDA_OVR BIT_ULL(8)
> +#define TWSI_INT_SCL_OVR BIT_ULL(9)
> +#define TWSI_INT_SDA BIT_ULL(10)
> +#define TWSI_INT_SCL BIT_ULL(11)
> +
> +enum {
> +
Re: [PATCH v3 10/10] test: dm: rtc: add tests of rtc shell command
Hello Rasmus, Am 02.06.2020 um 21:14 schrieb Rasmus Villemoes: Add tests of the "list", "read" and "write" subcommands of the rtc shell command. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- test/dm/rtc.c | 58 +++ 1 file changed, 58 insertions(+) Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v3 09/10] test: dm: rtc: add test of dm_rtc_read, dm_rtc_write
Hello Rasmus, Am 02.06.2020 um 21:14 schrieb Rasmus Villemoes: Define a few aux registers and check that they can be read/written individually. Also check that one can access the time-keeping registers directly and get the expected results. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- arch/sandbox/include/asm/rtc.h | 5 test/dm/rtc.c | 45 ++ 2 files changed, 50 insertions(+) Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v3 08/10] rtc: i2c_rtc_emul: catch any write to the "reset" register
Hello Rasmus, Am 02.06.2020 um 21:14 schrieb Rasmus Villemoes: It's more natural that any write that happens to touch the reset register should cause a reset, rather than just a write that starts at that offset. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- drivers/rtc/i2c_rtc_emul.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v3 06/10] rtc: add rtc command
Hello Rasmus, Am 02.06.2020 um 21:13 schrieb Rasmus Villemoes: Mostly as an aid for debugging RTC drivers, provide a command that can be used to read/write arbitrary registers (assuming the driver provides the read/write methods or their single-register-at-a-time variants). Signed-off-by: Rasmus Villemoes --- cmd/Kconfig | 6 ++ cmd/Makefile | 1 + cmd/rtc.c| 167 +++ 3 files changed, 174 insertions(+) create mode 100644 cmd/rtc.c Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v3 07/10] rtc: sandbox-rtc: fix set method
Hello Rasmu, Am 02.06.2020 um 21:14 schrieb Rasmus Villemoes: The current set method is broken; a simple test case is to first set the date to something in April, then change the date to 31st May: => date 040412122020.34 Date: 2020-04-04 (Saturday)Time: 12:12:34 => date 053112122020.34 Date: 2020-05-01 (Friday)Time: 12:12:34 or via the amending of the existing rtc_set_get test case similarly: $ ./u-boot -T -v => ut dm rtc_set_get Test: dm_test_rtc_set_get: rtc.c expected: 31/08/2004 18:18:00 actual: 01/08/2004 18:18:00 The problem is that after each register write, sandbox_i2c_rtc_complete_write() gets called and sets the internal time from the current set of registers. However, when we get to writing 31 to mday, the registers are in an inconsistent state (mon is still 4), so the mktime machinery ends up translating April 31st to May 1st. Upon the next register write, the registers are populated by sandbox_i2c_rtc_prepare_read(), so the 31 we just wrote to mday gets overwritten by a 1. Fix it by writing all registers at once, and for consistency, update the get method to retrieve them all with one "i2c transfer". Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- drivers/rtc/sandbox_rtc.c | 65 +++ test/dm/rtc.c | 15 - 2 files changed, 38 insertions(+), 42 deletions(-) Good catch! Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v3 05/10] rtc: pcf2127: provide ->write method
Hello Rasmus, Am 02.06.2020 um 21:13 schrieb Rasmus Villemoes: Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- drivers/rtc/pcf2127.c | 7 +++ 1 file changed, 7 insertions(+) Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v3 03/10] rtc: fall back to ->{read,write} if ->{read,write}8 are not provided
Hello Rasmus,
Am 02.06.2020 um 21:13 schrieb Rasmus Villemoes:
Similar to how the dm_rtc_{read,write} functions fall back to using
the {read,write}8 methods, do the opposite in the rtc_{read,write}8
functions.
This way, each driver only needs to provide either ->read8 or ->read
to make both rtc_read8() and dm_rtc_read() work - without this, a
driver that provides ->read() would most likely just duplicate the
logic here for implementing a ->read8() method in term of its ->read()
method. The same remarks of course apply to the write case.
Reviewed-by: Simon Glass
Signed-off-by: Rasmus Villemoes
---
drivers/rtc/rtc-uclass.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
Reviewed-by: Heiko Schocher
bye,
Heiko
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v3 04/10] rtc: pcf2127: provide ->read method
Hello Rasmus, Am 02.06.2020 um 21:13 schrieb Rasmus Villemoes: This simply consists of renaming the existing pcf2127_read_reg() helper to follow the naming of the other methods (i.e. pcf2127_rtc_) and changing the type of its "len" parameter. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- drivers/rtc/pcf2127.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v3 02/10] rtc: add dm_rtc_write() helper
Hello Rasmus, Am 02.06.2020 um 21:13 schrieb Rasmus Villemoes: Similar to dm_rtc_read(), introduce a helper that allows the caller to write multiple consecutive 8-bit registers with one call. If the driver provides the ->write method, use that, otherwise loop using ->write8. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- drivers/rtc/rtc-uclass.c | 18 ++ include/rtc.h| 24 2 files changed, 42 insertions(+) Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v3 01/10] rtc: add dm_rtc_read helper and ->read method
Hello Rasmus, Am 02.06.2020 um 21:13 schrieb Rasmus Villemoes: Some users may want to read multiple consecutive 8-bit registers. Instead of each caller having to implement the loop, provide a dm_rtc_read() helper. Also, allow a driver to provide a ->read method, which can be more efficient than reading one register at a time. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- drivers/rtc/rtc-uclass.c | 18 ++ include/rtc.h| 23 +++ 2 files changed, 41 insertions(+) Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v2] i2c: octeon_i2c: Add I2C controller driver for Octeon
Hello Stefan, Am 26.05.2020 um 14:13 schrieb Stefan Roese: From: Suneel Garapati Add support for I2C controllers found on Octeon II/III and Octeon TX TX2 SoC platforms. Signed-off-by: Aaron Williams Signed-off-by: Suneel Garapati Signed-off-by: Stefan Roese Cc: Heiko Schocher Cc: Simon Glass Cc: Daniel Schwierzeck Cc: Aaron Williams Cc: Chandrakala Chavva --- v2 (Stefan): - Added clk framework support and dropped ad-hoc clock code - Removed #ifdef's for Octeon vs OcteonTX/TX2 completely The differentiation is now made via driver data / compatible string - Added device-tree bindings documentation - Removed unused macro RFC -> v1 (Stefan): - Separated this patch from the OcteonTX/TX2 RFC patch series into a single patch. This is useful, as the upcoming MIPS Octeon support will use this I2C driver. - Added MIPS Octeon II/III support (big endian). Rename driver and its function names from "octeontx" to "octeon" to better match all Octeon platforms. - Moved from union to defines / bitmasks as suggested by Simon. This makes the driver usage on little- and big-endian platforms much easier. - Enhanced Kconfig text - Removed all clock macros (use values from DT) - Removed long driver debug strings. This is only available when a debug version of this driver is built. The user / developer can lookup the descriptive error messages in the driver in this case anyway. - Removed static "last_id" - Dropped misc blank lines. Misc reformatting. - Dropped "!= 0" - Added missing function comments - Added missing strut comments - Changed comment style - Renames "result" to "ret" - Hex numbers uppercase - Minor other changes - Reword commit text and subject doc/device-tree-bindings/i2c/octeon-i2c.txt | 24 + drivers/i2c/Kconfig | 10 + drivers/i2c/Makefile| 1 + drivers/i2c/octeon_i2c.c| 847 4 files changed, 882 insertions(+) create mode 100644 doc/device-tree-bindings/i2c/octeon-i2c.txt create mode 100644 drivers/i2c/octeon_i2c.c Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v13 00/19] RISC-V SiFive FU540 support SPL
Hi Jagan > From: Jagan Teki [mailto:ja...@amarulasolutions.com] > Sent: Wednesday, June 03, 2020 2:57 AM > To: Rick Jian-Zhi Chen(陳建志) > Cc: U-Boot-Denx; Atish Patra; Palmer Dabbelt; Bin Meng; Paul Walmsley; Anup > Patel; Sagar Kadam; Pragnesh Patel > Subject: Re: [PATCH v13 00/19] RISC-V SiFive FU540 support SPL > > Hi Rick, > > On Fri, May 29, 2020 at 11:34 AM Pragnesh Patel > wrote: > > > > This series add support for SPL to FU540. U-Boot SPL can boot from > > L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and > > U-Boot proper from MMC devices. > > > > This series is also available here [1] for testing [1] > > https://github.com/pragnesh26992/u-boot/tree/spl > > > > How to test this patch: > > 1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y > > 2) export OPENSBI= > opensbi/build/platform/generic/firmware/fw_dynamic.bin> > > 3) Change to u-boot-dir > > 4) make sifive_fu540_defconfig > > 5) make all > > 6) Format the SD card (make sure the disk has GPT, otherwise use gdisk > > to switch) > > > > # sudo sgdisk --clear \ > > > --set-alignment=2 \ > > > --new=1:34:2081 --change-name=1:loader1 > > --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \ > > > --new=2:2082:10273 --change-name=2:loader2 > > --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \ > > > --new=3:10274: --change-name=3:rootfs > > --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \ > > > /dev/sda > > > > 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34 > > 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082 > > > > Changes in v13: > > - Add a new patch to set the ethernet clock rate > > (riscv: sifive: dts: fu540: set ethernet clock rate) > > > > Changes in v12: > > - Rebase on mainline U-Boot > > Added necessary include files which are not part of common header now > > Remove unnecessary include files > > > > drivers/misc/sifive-otp.c > > +#include > > +#include > > > > board/sifive/fu540/fu540.c > > -#include > > +#include > > > > board/sifive/fu540/spl.c > > +#include > > +#include > > +#include > > > > drivers/ram/sifive/fu540_ddr.c > > +#include > > > > arch/riscv/cpu/fu540/cpu.c > > -#include > > +#include > > > > arch/riscv/cpu/fu540/spl.c > > -#include > > +#include > > > > board/sifive/fu540/spl.c > > -#include > > +#include > > +#include > > +#include > > > > - Update commit description for Release ethernet clock reset > > - Update OpenSBI building section in "doc/board/sifive/fu540.rst" > > > > Changes in v11: > > - Remove TPL related code and OF_PLATDATA from FU540 > > DDR driver (drivers/ram/sifive/fu540_ddr.c) > > - Update FU540 doc (doc/board/sifive/fu540.rst) > > Remove unnecessary print > > > > Changes in v10: > > - Update commit description for ethernet clock reset > > (https://patchwork.ozlabs.org/patch/1289003) > > - Update commit description for ddr clock initialization > > (https://patchwork.ozlabs.org/patch/1289000) > > > > Changes in v9: > > - Remove cache related patches from this series > > sifive: dts: fu540: Enable L2 Cache in U-Boot > > (https://patchwork.ozlabs.org/patch/1286705) > > riscv: sifive: fu540: enable all cache ways from U-Boot proper > > (https://patchwork.ozlabs.org/patch/1286706) > > - Rename SiFive DDR driver from sdram_fu540.c to fu540_ddr.c > > and also do some typo correction in driver > > - Remove CONFIG_SPL_BUILD for __prci_ddr_release_reset() > > - Release ethernet clock reset instead of ethernet clock > > initialization > > (https://patchwork.ozlabs.org/patch/1286697) > > - Squash fu540 cpu patches > > (https://patchwork.ozlabs.org/patch/1286699) > > (https://patchwork.ozlabs.org/patch/1286700) > > - Use spl_boot_device() instead of board_boot_order() > > > > Changes in v8: > > - Remove SPL_CRC7_SUPPORT Kconfig option and compile > > crc7.o when CONFIG_MMC_SPI selected > > - Add "TODO" in drivers/ram/sifive/sdram_fu540.c > > - Remove unnecessary TODO from drivers/clk/sifive/fu540-prci.c > > - Make fu540-hifive-unleashed-a00-sdram-ddr4.dtsi file dual-licensed > > - Add 2 new patches > > sifive: fu540: Add sample SD gpt partition layout > > (https://patchwork.ozlabs.org/patch/1092) > > sifive: fu540: Add U-Boot proper sector start > > (https://patchwork.ozlabs.org/patch/1093) > > - Remove patch > > riscv: Enable cpu clock if it is present > > (https://patchwork.ozlabs.org/patch/1281573) > > - Update doc/board/sifive/fu540.rst for PLATFORM=generic > > > > Changes in v7: > > - Standardize SD gpt partition layout > > - Add delay for SiFive OTP driver > > - Use DM way for corepll and ddrpll > > - Add new cpu fu540 (arch/riscv/cpu/fu540) > > - Update document for FU540 (doc/board/sifive/fu540.rst) > > > > Changes in v6: > > - Typo Correction > > - Make fu540-c000-u-boot.dtsi and hifive-unleashed-a00-u-boot.dtsi > >
RE: [PATCH v3 1/2] mtd: rawnand: ca_nand: add Cortina Access Parallel NAND controller support
Hi Miquel/Tom, >> Hi Alex, >> >> Alex Nemirovsky wrote on Mon, 1 >> Jun 2020 14:26:49 -0700: >> >> > From: Jason Li >> > >> > Supports all CA SoCs which support a parallel nand controller. >> > It should be noted that some CA Soc also support an separate >> > SPI serial NAND controller. >> > >> > This driver only supports the parallel NAND controller. A different >> > driver supports the SPI NAND interface controller. >> > >> > Signed-off-by: Jason Li >> > Signed-off-by: Alex Nemirovsky >> > >> > CC: Miquel Raynal >> > CC: Simon Glass >> > CC: Tom Rini >> > --- >> > >> > Changes in v3: >> > - Include udelay.h to avoid implicit declaration of udelay() >> > >> > Changes in v2: >> > - Cleanup code style to pass checkpatch.pl >> > >> > MAINTAINERS|2 + >> > drivers/mtd/nand/raw/Kconfig | 31 + >> > drivers/mtd/nand/raw/Makefile |1 + >> > drivers/mtd/nand/raw/ca_nand.c | 4943 >> > >> > drivers/mtd/nand/raw/ca_nand.h | 3899 +++ >> >> This is insanely big ! >> >> > 5 files changed, 8876 insertions(+) >> > create mode 100644 drivers/mtd/nand/raw/ca_nand.c >> > create mode 100644 drivers/mtd/nand/raw/ca_nand.h >> > >> > diff --git a/MAINTAINERS b/MAINTAINERS >> > index 8add9d4..6da2ad8 100644 >> > --- a/MAINTAINERS >> > +++ b/MAINTAINERS >> > @@ -181,6 +181,8 @@ F: drivers/gpio/cortina_gpio.c >> > F:drivers/watchdog/cortina_wdt.c >> > F:drivers/serial/serial_cortina.c >> > F:drivers/mmc/ca_dw_mmc.c >> > +F:drivers/mtd/nand/raw/ca_nand.c >> > +F:drivers/mtd/nand/raw/ca_nand.h >> > >> > ARM/CZ.NIC TURRIS MOX SUPPORT >> > M:Marek Behun >> > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig >> > index c4d9d31..b3cbfcc 100644 >> > --- a/drivers/mtd/nand/raw/Kconfig >> > +++ b/drivers/mtd/nand/raw/Kconfig >> > @@ -102,6 +102,37 @@ config NAND_BRCMNAND_63158 >> > help >> > Enable support for broadcom nand driver on bcm63158. >> > >> > +config NAND_CORTINA >> > +tristate "Support Cortina-Access Parallel NAND cntlr." >> > + select SYS_NAND_SELF_INIT >> >> Alignment looks wrong >> >> > +help >> > + This enables the parallel RAW NAND driver for the >> > +Cortina-Access CA Family of SoCs. >> > + >> > +config NAND_CORTINA_ECC_LEVEL >> > +int "Cortina-Access Parallel Nand driver HW ECC algorithm" >> > +default 3 >> > +range 0 5 >> > +depends on NAND_CORTINA >> > +help >> > + NAND Flash ECC algorithm. Value range from 0 to 5. >> > + The default value is 3. >> > + >> > + 0: Hamming algorithm. Correct 3 bad bits in 256 btyes. >> > + 1: Hamming algorithm. Correct 3 bad bits in 512 btyes. >> > + 2: BCH algorithm. Correct 8 bad bits in 1K btyes. >> > + 3: BCH algorithm. Correct 16 bad bits in 1K btyes. >> > + 4: BCH algorithm. Correct 24 bad bits in 1K btyes. >> > + 5: BCH algorithm. Correct 40 bad bits in 1K btyes. >> >> Not sure how u-boot guys want to handle this but the current way to >> request for a specif correction is to pass nand-ecc-strength and >> nand-ecc-size DT properties. If the driver does not support the >> requested properties, there is a function (at least in Linux) which >> finds the closest correction called nand_ecc_choose_conf(), provided >> that you implemented a few specific hooks in your driver. > >We have drivers making use of those properties too, so this one should >as well. Thanks! > >-- >Tom Since DTB is separate image from u-boot. If we put these information in DTB. What ECC algorithm should be applied when read DTB from flash? Could you guide more detail. Thanks, Jason
[tools] FIT tools rework
Hello I would like to introduce a change in the FIT host tools, and thus I'm looking for advice and opinion. The change would only take place on the host FIT reading tools, namely fit_info, fit_check, and their libraries. The main idea here is, I think this tool is quite handy and complete for development and debug, but my need is a production ready tool set, usable on the target booted by u-boot. The use case being a target fully booted wanting to check and retrieve information from its own FIT images. In my opinion (and I may very well have misunderstood it and be wrong), this tool (or any other one) may not answer this need, not even with small fixes. That's why I'd like to refactor it as a whole, changing its architecture (that's a big word for a single toolset and a couple of functions in libraries, with respect to actual implementation). I tend to prefer removing current front-end implementation, as a new toolset would actually make it redundant. I would however understand the idea of breaking compatibility with external tests could rule this out (fishing for advice here). Here are the main points I would like to find in a renewed toolset, usable in the linux environment booted from u-boot. Take this as the way of a program doing one thing only, but doing it well and clearly. - a separate program for each feature - perform separate checks on FIT images: I should be able to only check signature, or only integrity - check signatures out of crt, pem, ... files: DTB stored public keys are pretty uncommon on userspace, and that goes against usual pubkey formats - use various device types as FIT image input (MTD, UBI volume, ...): I'm not sure about this one. I think that could (and should) be handled out of the tool, and the caller should provide a readable file. Fishing for opinion nontheless - retrieve FIT properties: indeed fit_info provides properties, but I think a more friendly way would improve readability and ease of use. Among other things, that includes the ability to return only the property value (for scripting indeed), for a few data types. In my opinion, reading FIT metadata is a must have for a userspace application, and while dtc (and others) provides a way to do it, such an utility could be included in the fit tools. It should be able to return several properties at once, that would be nice and better for processing time. - check authenticity when retrieving properties: while chances of external corruption between a signature check and properties value check are low, the ability to check FIT metadata while retrieving some of them could come in handy. Those are only my ideas of what such a tool should have and you are indeed more than welcome to add ideas, challenge them, or simply tell me there already are usable ways of doing all this and no such change is required. Thanks
Re: [PATCH v4] net: tftp: Add client support for RFC 7440
Ramon Fried-4 wrote
> + if (strcmp((char *)pkt + i, "windowsize") == 0) {
> For servers that doesnt support windowsize option the above check could
> result in accessing memory outside of valid range. Please check if (i+11)
> < len before comparing the strings.
>
>
> +
> + if (ntohs(*(__be16 *)pkt) != (ushort)(tftp_cur_block + 1)) {
> + debug("Received unexpected block: %d, expected: %d\n",
> + ntohs(*(__be16 *)pkt),
> + (ushort)(tftp_cur_block + 1));
> + /*
> + * If one packet is dropped most likely
> + * all other buffers in the window
> + * that will arrive will cause a sending NACK.
> + * This just overwellms the server, let's just send one.
> + */
> + if (tftp_last_nack != tftp_cur_block) {
> + tftp_send();
> + tftp_last_nack = tftp_cur_block;
> + tftp_next_ack = (ushort)(tftp_cur_block +
> + tftp_windowsize);
> + }
> + break;
> + }
> +
> + tftp_cur_block++;
>
> Monotonically increasing the tftp_cur_block will cause error for cases
> where sequence number wraps around as tftp_cur_block is ulong, thus during
> wraparound the check ntohs(*(__be16 *)pkt) != (ushort)(tftp_cur_block + 1)
> will fail and incorrectly generate ACK, and the connection will eventually
> be terminated once the retry is exhausted. Please modulo the increment
> with TFTP_SEQUENCE_SIZE.
> --
> 2.26.2
Quoted from:
http://u-boot.10912.n7.nabble.com/PATCH-v4-net-tftp-Add-client-support-for-RFC-7440-tp412754.html
--
Sent from: http://u-boot.10912.n7.nabble.com/
Re: [PATCH 1/2] riscv: sbi: Remove sbi_spec_version
Hi Bin
Bin Meng 於 2020年6月2日 週二 下午5:39寫道：
>
> Hi Rick,
>
> On Tue, Jun 2, 2020 at 5:13 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > Bin Meng 於 2020年6月1日 週一 下午5:06寫道：
> > >
> > > Hi Rick,
> > >
> > > On Mon, Jun 1, 2020 at 4:14 PM Rick Chen wrote:
> > > >
> > > > Hi Bin
> > > >
> > > > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > > > Sent: Wednesday, May 27, 2020 5:05 PM
> > > > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> > > > > Cc: Atish Patra; Bin Meng
> > > > > Subject: [PATCH 1/2] riscv: sbi: Remove sbi_spec_version
> > > > >
> > > > > From: Bin Meng
> > > > >
> > > > > U-Boot defaults to use SBI v0.2. Howerver there is a global variable
> > > > > sbi_spec_version that stills refers to v0.1. Since it is not used
> > > > > anywhere, let's remove it.
> > > > >
> > > > > Signed-off-by: Bin Meng
> > > > > ---
> > > > >
> > > > > arch/riscv/include/asm/sbi.h | 2 --
> > > > > arch/riscv/lib/sbi.c | 3 ---
> > > > > 2 files changed, 5 deletions(-)
> > > > >
> > > > > diff --git a/arch/riscv/include/asm/sbi.h
> > > > > b/arch/riscv/include/asm/sbi.h index 453cb5c..08e1ac0 100644
> > > > > --- a/arch/riscv/include/asm/sbi.h
> > > > > +++ b/arch/riscv/include/asm/sbi.h
> > > > > @@ -77,7 +77,6 @@ enum sbi_ext_rfence_fid {
> > > > > #define SBI_FID_REMOTE_SFENCE_VMA_ASID
> > > > > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID
> > > > > #endif
> > > > >
> > > > > -#define SBI_SPEC_VERSION_DEFAULT 0x1
> > > > > #define SBI_SPEC_VERSION_MAJOR_SHIFT 24
> > > > > #define SBI_SPEC_VERSION_MAJOR_MASK0x7f
> > > > > #define SBI_SPEC_VERSION_MINOR_MASK0xff
> > > > > @@ -90,7 +89,6 @@ enum sbi_ext_rfence_fid {
> > > > > #define SBI_ERR_DENIED -4
> > > > > #define SBI_ERR_INVALID_ADDRESS-5
> > > > >
> > > > > -extern unsigned long sbi_spec_version;
> > > > > struct sbiret {
> > > > > long error;
> > > > > long value;
> > > > > diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index
> > > > > 993597e..f298846 100644
> > > > > --- a/arch/riscv/lib/sbi.c
> > > > > +++ b/arch/riscv/lib/sbi.c
> > > > > @@ -11,9 +11,6 @@
> > > > > #include
> > > > > #include
> > > > >
> > > > > -/* default SBI version is 0.1 */
> > > > > -unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
> > > >
> > > > Why not keep this variable and get version of openSbi automatically,
> > > > then register v01 or v02 callback function just like sbi_init() of
> > > > Atish' patch.
> > >
> > > I feel this is not needed anyway, because we are using Kconfig option
> > > to pass the same information.
> >
> > U-Boot proper has been configured as SBI_V02 by default currently.
> > About backward compatible issue, it is not so friendly for users.
> > They shall select SBI_VERSION configurations correctly in U-Boot
> > proper and re-compile between different versions of openSbi.
> > If U-Boot proper can probe openSbi and switch V01 or V02 mode
> > automatically, users can run smoothly without awareness of SBI
> > versions.
> >
>
> OpenSBI v0.7 is not backward compatible with previous version
> regarding the multicore boot. Dynamically detecting SBI and the SBI
> implementation version will make U-Boot codes very complicated. In
> addition to SBI v0.1 vs. v0.2, we need detect whether SBI HSM
> extension is available and if that's not available, U-Boot has to do
> the lottery multi-core boot in every stage (SPL and proper). RISC-V is
> a new architecture and without a lot of legacy burden to carry on, I
> hope we can do the clean room implementation from the beginning.
>
OK.
Thanks for explanation.
Reviewed-by: Rick Chen
> Regards,
> Bin
Re: [PATCH 1/1] efi_loader: validate load option
Heinrich,
On Sun, May 31, 2020 at 10:52:16PM +0200, Heinrich Schuchardt wrote:
> For passing the optional data of the load option to the loaded imaged
> protocol we need its size.
>
> efi_deserialize_load_option() is changed to return the size of the optional
> data.
>
> As a by-product we get a partial validation of the load option.
> Checking the length of the device path remains to be implemented.
>
> Signed-off-by: Heinrich Schuchardt
Please add "Reported-by: Coverity (CID xxx)" for tracing
as you requested me before.
(even if it doesn't fully address the issue.)
Reported-by: Coverity (CID 303760)
Reported-by: Coverity (CID 303768)
Reported-by: Coverity (CID 303776)
-Takahiro Akashi
> ---
> cmd/efidebug.c | 21 +++-
> include/efi_loader.h | 3 ++-
> lib/efi_loader/efi_bootmgr.c | 48 +---
> 3 files changed, 56 insertions(+), 16 deletions(-)
>
> diff --git a/cmd/efidebug.c b/cmd/efidebug.c
> index 32430e62f0..58018f700c 100644
> --- a/cmd/efidebug.c
> +++ b/cmd/efidebug.c
> @@ -694,14 +694,19 @@ static int do_efi_boot_rm(struct cmd_tbl *cmdtp, int
> flag,
> *
> * Decode the value of UEFI load option variable and print information.
> */
> -static void show_efi_boot_opt_data(u16 *varname16, void *data, size_t size)
> +static void show_efi_boot_opt_data(u16 *varname16, void *data, size_t *size)
> {
> struct efi_load_option lo;
> char *label, *p;
> size_t label_len16, label_len;
> u16 *dp_str;
> + efi_status_t ret;
>
> - efi_deserialize_load_option(, data);
> + ret = efi_deserialize_load_option(, data, size);
> + if (ret != EFI_SUCCESS) {
> + printf("%ls: invalid load option\n", varname16);
> + return;
> + }
>
> label_len16 = u16_strlen(lo.label);
> label_len = utf16_utf8_strnlen(lo.label, label_len16);
> @@ -728,8 +733,7 @@ static void show_efi_boot_opt_data(u16 *varname16, void
> *data, size_t size)
>
> printf(" data:\n");
> print_hex_dump("", DUMP_PREFIX_OFFSET, 16, 1,
> -lo.optional_data, size + (u8 *)data -
> -(u8 *)lo.optional_data, true);
> +lo.optional_data, *size, true);
> free(label);
> }
>
> @@ -759,7 +763,7 @@ static void show_efi_boot_opt(u16 *varname16)
> _global_variable_guid,
> NULL, , data));
> if (ret == EFI_SUCCESS)
> - show_efi_boot_opt_data(varname16, data, size);
> + show_efi_boot_opt_data(varname16, data, );
> free(data);
> }
> }
> @@ -920,7 +924,12 @@ static int show_efi_boot_order(void)
> goto out;
> }
>
> - efi_deserialize_load_option(, data);
> + ret = efi_deserialize_load_option(, data, );
> + if (ret != EFI_SUCCESS) {
> + printf("%ls: invalid load option\n", var_name16);
> + ret = CMD_RET_FAILURE;
> + goto out;
> + }
>
> label_len16 = u16_strlen(lo.label);
> label_len = utf16_utf8_strnlen(lo.label, label_len16);
> diff --git a/include/efi_loader.h b/include/efi_loader.h
> index 9533df26dc..c2cae814b6 100644
> --- a/include/efi_loader.h
> +++ b/include/efi_loader.h
> @@ -708,7 +708,8 @@ struct efi_load_option {
> const u8 *optional_data;
> };
>
> -void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data);
> +efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8
> *data,
> + efi_uintn_t *size);
> unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8
> **data);
> efi_status_t efi_bootmgr_load(efi_handle_t *handle);
>
> diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
> index fa65445c12..e268e9c4b8 100644
> --- a/lib/efi_loader/efi_bootmgr.c
> +++ b/lib/efi_loader/efi_bootmgr.c
> @@ -38,24 +38,50 @@ static const struct efi_runtime_services *rs;
> *
> * @lo: pointer to target
> * @data:serialized data
> + * @size:size of the load option, on return size of the optional data
> + * Return: status code
> */
> -void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data)
> +efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8
> *data,
> + efi_uintn_t *size)
> {
> + efi_uintn_t len;
> +
> + len = sizeof(u32);
> + if (*size < len + 2 * sizeof(u16))
> + return EFI_INVALID_PARAMETER;
> lo->attributes = get_unaligned_le32(data);
> - data += sizeof(u32);
> + data += len;
> + *size -= len;
>
> + len = sizeof(u16);
> lo->file_path_length = get_unaligned_le16(data);
> - data += sizeof(u16);
> + data += len;
> + *size -= len;
>
>
RE: [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model
Hi Jagan,
Thanks a lot for your comments!
> -Original Message-
> From: Jagan Teki
> Sent: 2020年6月3日 3:29
> To: Z.q. Hou
> Cc: U-Boot-Denx ; Priyanka Jain
> ; Shengzhou Liu ; Simon
> Glass ; Biwen Li ; Bin Meng
> ; Jiafei Pan ; Chuanhua Han
> ; Xiaowei Bao
> Subject: Re: [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver
> model
>
> On Tue, Jun 2, 2020 at 7:10 PM Zhiqiang Hou
> wrote:
> >
> > From: Chuanhua Han
> >
> > Modify the Freescale ESPI driver to support the driver model.
> > Also resolved the following problems:
> >
> > = WARNING == This
> board does
> > not use CONFIG_DM_SPI. Please update the board before v2019.04 for no
> > dm conversion and v2019.07 for partially dm converted drivers.
> > Failure to update can lead to driver/board removal See
> > doc/driver-model/MIGRATION.txt for more info.
> >
> > = WARNING == This
> board does
> > not use CONFIG_DM_SPI_FLASH. Please update the board to use
> > CONFIG_SPI_FLASH before the v2019.07 release.
> > Failure to update by the deadline may result in board removal.
> > See doc/driver-model/MIGRATION.txt for more info.
> >
> >
> > Signed-off-by: Chuanhua Han
> > Signed-off-by: Xiaowei Bao
> > Signed-off-by: Hou Zhiqiang
> > ---
> > V2:
> > - Rebase the patch, no change intended.
> >
> > drivers/spi/fsl_espi.c | 444
>
> > include/dm/platform_data/fsl_espi.h | 16 +
> > 2 files changed, 337 insertions(+), 123 deletions(-) create mode
> > 100644 include/dm/platform_data/fsl_espi.h
> >
> > diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index
> > 50d194f614..5c76fd962e 100644
> > --- a/drivers/spi/fsl_espi.c
> > +++ b/drivers/spi/fsl_espi.c
> > @@ -3,7 +3,9 @@
> > * eSPI controller driver.
> > *
> > * Copyright 2010-2011 Freescale Semiconductor, Inc.
> > + * Copyright 2020 NXP
> > * Author: Mingkai Hu (mingkai...@freescale.com)
> > + *Chuanhua Han (chuanhua@nxp.com)
> > */
> >
> > #include
> > @@ -14,10 +16,16 @@
> > #include
> > #include
> > #include
> > +#include
> > +#include
> > +#include
> > +#include
> >
> > struct fsl_spi_slave {
> > struct spi_slave slave;
> > ccsr_espi_t *espi;
> > + u32 speed_hz;
> > + unsigned intcs;
> > unsigned intdiv16;
> > unsigned intpm;
> > int tx_timeout;
> > @@ -31,6 +39,9 @@ struct fsl_spi_slave { #define to_fsl_spi_slave(s)
> > container_of(s, struct fsl_spi_slave, slave)
> > #define US_PER_SECOND 100UL
> >
> > +/* default SCK frequency, unit: HZ */
> > +#define FSL_ESPI_DEFAULT_SCK_FREQ 1000
> > +
> > #define ESPI_MAX_CS_NUM4
> > #define ESPI_FIFO_WIDTH_BIT32
> >
> > @@ -65,116 +76,27 @@ struct fsl_spi_slave {
> >
> > #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
> >
> > -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> > - unsigned int max_hz, unsigned int mode)
> > -{
> > - struct fsl_spi_slave *fsl;
> > - sys_info_t sysinfo;
> > - unsigned long spibrg = 0;
> > - unsigned long spi_freq = 0;
> > - unsigned char pm = 0;
> > -
> > - if (!spi_cs_is_valid(bus, cs))
> > - return NULL;
> > -
> > - fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
> > - if (!fsl)
> > - return NULL;
> > -
> > - fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
> > - fsl->mode = mode;
> > - fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> > -
> > - /* Set eSPI BRG clock source */
> > - get_sys_info();
> > - spibrg = sysinfo.freq_systembus / 2;
> > - fsl->div16 = 0;
> > - if ((spibrg / max_hz) > 32) {
> > - fsl->div16 = ESPI_CSMODE_DIV16;
> > - pm = spibrg / (max_hz * 16 * 2);
> > - if (pm > 16) {
> > - pm = 16;
> > - debug("Requested speed is too low: %d
> Hz, %ld Hz "
> > - "is used.\n", max_hz, spibrg / (32 *
> 16));
> > - }
> > - } else
> > - pm = spibrg / (max_hz * 2);
> > - if (pm)
> > - pm--;
> > - fsl->pm = pm;
> > -
> > - if (fsl->div16)
> > - spi_freq = spibrg / ((pm + 1) * 2 * 16);
> > - else
> > - spi_freq = spibrg / ((pm + 1) * 2);
> > -
> > - /* set tx_timeout to 10 times of one espi FIFO entry go out */
> > - fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND *
> ESPI_FIFO_WIDTH_BIT
> > - * 10), spi_freq);
> > -
> > - return >slave;
> > -}
> > -
> > -void spi_free_slave(struct spi_slave *slave) -{
> > - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> > -
RE: [PATCHv4 3/3] spi: Convert CONFIG_DM_SPI* to CONFIG_$(SPL_TPL_)DM_SPI*
Hi Tom and Jagan,
Thanks a lot for your comments!
> -Original Message-
> From: Tom Rini
> Sent: 2020年6月3日 3:02
> To: Jagan Teki ; Z.q. Hou
>
> Cc: U-Boot-Denx ; Lokesh Vutla
> ; Andrew F Davis ; Heiko Schocher
> ; Simon Glass ; Feng Li
> ; Alison Wang ; Sumit Garg
> ; Eugen Hristev ;
> Patrick Delaunay ; Vignesh R ;
> Joe Hershberger ; Stefan Roese ;
> Wolfgang Denk ; Lukasz Majewski ; Miquel
> Raynal ; Marek Vasut ; Bin
> Meng ; Simon Goldschmidt
> ; Markus Klotzbuecher
> ; Baruch Siach ;
> Harald Seiler ; Joel Johnson ; Anatolij
> Gustschin ; Priyanka Jain ;
> Madalin Bucur (OSS) ; Gervais, Francois
> ; Udit Agarwal
> Subject: Re: [PATCHv4 3/3] spi: Convert CONFIG_DM_SPI* to
> CONFIG_$(SPL_TPL_)DM_SPI*
>
> On Wed, Jun 03, 2020 at 12:10:30AM +0530, Jagan Teki wrote:
> > On Tue, Jun 2, 2020 at 11:57 PM Tom Rini wrote:
> > >
> > > On Tue, Jun 02, 2020 at 06:59:21PM +0530, Jagan Teki wrote:
> > > > On Tue, Jun 2, 2020 at 6:47 PM Zhiqiang Hou
> wrote:
> > > > >
> > > > > From: Lukasz Majewski
> > > > >
> > > > > This change allows more fine tuning of driver model based SPI
> > > > > support in SPL and TPL. It is now possible to explicitly
> > > > > enable/disable the DM_SPI support in SPL and TPL via Kconfig option.
> > > > >
> > > > > Before this change it was necessary to use:
> > > > > /* SPI Flash Configs */
> > > > > #if defined(CONFIG_SPL_BUILD)
> > > > > #undef CONFIG_DM_SPI
> > > > > #undef CONFIG_DM_SPI_FLASH
> > > > > #undef CONFIG_SPI_FLASH_MTD
> > > > > #endif
> > > > >
> > > > > in the ./include/configs/.h, which is error prone and
> > > > > shall be avoided when we strive to switch to Kconfig.
> > > > >
> > > > > The goal of this patch:
> > > > >
> > > > > Provide distinction for DM_SPI support in both U-Boot proper and SPL
> (TPL).
> > > > > Valid use case is when U-Boot proper wants to use DM_SPI, but
> > > > > SPL must still support non DM driver.
> > > > >
> > > > > Another use case is the conversion of non DM/DTS SPI driver to
> > > > > support DM/DTS. When such driver needs to work in both SPL and
> > > > > U-Boot proper, the distinction is needed in Kconfig (also if SPL
> > > > > version of the driver supports OF_PLATDATA).
> > > > >
> > > > > In the end of the day one would have to support following use
> > > > > cases (in single driver file - e.g. mxs_spi.c):
> > > > >
> > > > > - U-Boot proper driver supporting DT/DTS
> > > > > - U-Boot proper driver without DT/DTS support (deprecated)
> > > > > - SPL driver without DT/DTS support
> > > > > - SPL (and TPL) driver with DT/DTS (when the SoC has enough
> resources to
> > > > > run full blown DT/DTS)
> > > > > - SPL driver with DT/DTS and SPL_OF_PLATDATA (when one have
> constrained
> > > > > environment with no fitImage and OF_LIBFDT support).
> > > > >
> > > > > Some boards do require SPI support (with DM) in SPL (TPL) and
> > > > > some only have DM_SPI{_FLASH} defined to allow compiling SPL.
> > > > >
> > > > > This patch converts #ifdef CONFIG_DM_SPI* to #if
> > > > > CONFIG_IS_ENABLED(DM_SPI) and provides corresponding defines in
> Kconfig.
> > > > >
> > > > > Signed-off-by: Lukasz Majewski
> > > > > Tested-by: Adam Ford #da850-evm
> > > > > Signed-off-by: Hou Zhiqiang
> > > > > ---
> > > > > V4:
> > > > > - Rebase the patch and remove SPL_DM_SPI from target ls1046
> boards.
> > > > >
> > > > > arch/arm/Kconfig| 11
> +++
> > > > > board/l+g/vinco/vinco.c | 4 ++--
> > > > > cmd/sf.c| 4 ++--
> > > > > cmd/spi.c | 6 +++---
> > > > > common/spl/Kconfig | 20
>
> > > > > configs/am57xx_evm_defconfig| 2 ++
> > > > > configs/am57xx_hs_evm_defconfig | 2 ++
> > > > > configs/am57xx_hs_evm_usb_defconfig | 2 ++
> > > > > configs/axm_defconfig | 2 ++
> > > > > configs/chromebook_link64_defconfig | 2 ++
> > > > > configs/chromebook_samus_tpl_defconfig | 4
> > > > > configs/dra7xx_evm_defconfig| 2 ++
> > > > > configs/dra7xx_hs_evm_defconfig | 2 ++
> > > > > configs/dra7xx_hs_evm_usb_defconfig | 2 ++
> > > > > configs/j721e_evm_a72_defconfig | 2 ++
> > > > > configs/j721e_evm_r5_defconfig | 2 ++
> > > > > configs/ls1021aiot_qspi_defconfig | 2 ++
> > > > > configs/ls1021aiot_sdcard_defconfig | 2 ++
> > > > > configs/ls1021aqds_qspi_defconfig | 1 +
> > > > > configs/ls1021aqds_sdcard_qspi_defconfig| 1 +
> > > > > configs/ls1021atwr_qspi_defconfig | 1 +
> > > > > configs/sama5d2_xplained_spiflash_defconfig | 2 ++
> > > > > configs/sama5d3xek_spiflash_defconfig | 7 ---
> > > > > configs/sama5d4_xplained_spiflash_defconfig | 2 ++
> > > > > configs/sama5d4ek_spiflash_defconfig| 2 ++
> > > > >
Re: [PATCH v1 1/2] net: cortina_ni: Addd eth support for Cortina Access CAxxxx SoCs
Abbie/Aaron, please remove legacy mode code so that we only support DM mode per Tom’s request. Thanks -AN > On Jun 2, 2020, at 5:38 PM, Tom Rini wrote: > > On Wed, Jun 03, 2020 at 12:18:18AM +, Alex Nemirovsky wrote: >> Hi Tom, >> >>> On Jun 2, 2020, at 6:02 AM, Tom Rini wrote: >>> >>> On Mon, Jun 01, 2020 at 07:44:25PM -0700, Alex Nemirovsky wrote: >>> From: Aaron Tseng Add Cortina Access Ethernet device driver for CA SoCs. This driver supports both legacy and DM_ETH network models. Signed-off-by: Aaron Tseng Signed-off-by: Alex Nemirovsky CC: Joe Hershberger CC: Abbie Chang CC: Tom Rini >>> [snip] +#define HEADER_A_SIZE 8 +#define CORTINA_NI_DBG 1 +/*define CORTINA_NI_DBG if individual rx,tx,init needs to be called */ >>> >>> We have pr_debug, etc, please use those and not a custom debug defiine. >>> +#ifdef CONFIG_DM_ETH +#if CORTINA_NI_DBG +static struct udevice *dbg_dev; +#endif +static struct udevice *curr_dev; +#else >>> >>> The deadline for drivers to convert to DM for ethernet is v2020.07. >>> Please rework to not introduce any legacy mode support. Thanks! >> >> For clarity, we are providing BOTH DM and Legacy mode support in our driver. >> Is the request to REMOVE Legacy mode support, even though DM support is >> already provided to meet the 2020.07 requirement? > > Yes, remove the legacy code as there's no non-legacy users in upstream > to support. Thanks! > > -- > Tom
[PATCH 6/6] cmd: Add a memory-search command
It is useful to be able to find hex values and strings in a memory range.
Add a command to support this.
cmd: Fix 'md' and add a memory-search command
At present 'md.q' is broken. This series provides a fix for this. It also
implements a new memory-search command called 'ms'. It allows searching
memory for hex and string data.
END
Signed-off-by: Simon Glass
---
README| 10 ++
cmd/Kconfig | 14 +++
cmd/mem.c | 151 +++
test/Makefile | 1 +
test/cmd/Makefile | 5 +
test/cmd/mem_search.c | 275 ++
6 files changed, 456 insertions(+)
create mode 100644 test/cmd/Makefile
create mode 100644 test/cmd/mem_search.c
diff --git a/README b/README
index 17dc0ee33b..8abcff0783 100644
--- a/README
+++ b/README
@@ -3283,6 +3283,7 @@ md- memory display
mm - memory modify (auto-incrementing)
nm - memory modify (constant address)
mw - memory write (fill)
+ms - memory search
cp - memory copy
cmp- memory compare
crc32 - checksum calculation
@@ -3528,6 +3529,15 @@ List of environment variables (most likely not complete):
CONFIG_NET_RETRY_COUNT, if defined. This value has
precedence over the valu based on CONFIG_NET_RETRY_COUNT.
+ memmatches - Number of matches found by the last 'ms' command, in hex
+
+ memaddr - Address of the last match found by the 'ms' command, in hex,
+ or 0 if none
+
+ mempos - Index position of the last match found by the 'ms' command,
+ in units of the size (.b, .w, .l) of the search
+
+
The following image location variables contain the location of images
used in booting. The "Image" column gives the role of the image and is
not an environment variable name. The other columns are environment
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 153864c587..a02a376d49 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -717,6 +717,20 @@ config CMD_MEMORY
base - print or set address offset
loop - initialize loop on address range
+config MEM_SEARCH
+ bool "ms - Memory search"
+ help
+ Memory-search command
+
+ This allows searching through a region of memory looking for hex
+ data (byte, 16-bit word, 32-bit long, also 64-bit on machines that
+ support it). It is also possible to search for a string. The
+ command accepts a memory range and a list of values to search for.
+ The values need to appear in memory in the same order they are given
+ in the command. At most 10 matches can be returned at a time, but
+ pressing return will show the next 10 matches. Environment variables
+ are set for use with scripting (memmatches, memaddr, mempos).
+
config CMD_MX_CYCLIC
bool "Enable cyclic md/mw commands"
depends on CMD_MEMORY
diff --git a/cmd/mem.c b/cmd/mem.c
index 9ab6b1dd08..575893c18d 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -52,6 +53,10 @@ static ulong dp_last_length = 0x40;
static ulong mm_last_addr, mm_last_size;
static ulong base_address = 0;
+#ifdef CONFIG_MEM_SEARCH
+static u8 search_buf[64];
+static uint search_len;
+#endif
/* Memory Display
*
@@ -362,6 +367,142 @@ static int do_mem_cp(struct cmd_tbl *cmdtp, int flag, int
argc,
return 0;
}
+#ifdef CONFIG_MEM_SEARCH
+static int do_mem_search(struct cmd_tbl *cmdtp, int flag, int argc,
+char *const argv[])
+{
+ ulong addr, length, bytes, offset;
+ u8 *ptr, *end, *buf;
+ bool quiet = false;
+ ulong last_pos; /* Offset of last match in 'size' units*/
+ ulong last_addr;/* Address of last displayed line */
+ int limit = 10;
+ int count;
+ int size;
+ int i;
+
+ /* We use the last specified parameters, unless new ones are entered */
+ addr = dp_last_addr;
+ size = dp_last_size;
+ length = dp_last_length;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ if ((!flag & CMD_FLAG_REPEAT)) {
+ /*
+* Check for a size specification.
+* Defaults to long if no or incorrect specification.
+*/
+ size = cmd_get_data_size(argv[0], 4);
+ if (size < 0 && size != -2 /* string */)
+ return 1;
+
+ argc--; argv++;
+ while (argc && *argv[0] == '-') {
+ int ch = argv[0][1];
+
+ if (ch == 'q')
+ quiet = true;
+ else if (ch == 'l' && isxdigit(argv[0][2]))
+ limit = simple_strtoul(argv[0] + 2, NULL, 16);
+ else
+ return CMD_RET_USAGE;
+
[PATCH 5/6] command: Drop #ifdef for MEM_SUPPORT_64BIT_DATA
This is defined only when __lp64__ is defined. That means that ulong is 64 bits long. Therefore we don't need to use a separate u64 type on those architectures. Fix up the code to take advantage of that, removing the preprocessor conditions. Also include the header file that defines MEM_SUPPORT_64BIT_DATA. It is included by env.h in this file, but that might not last forever. Signed-off-by: Simon Glass --- common/command.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/common/command.c b/common/command.c index fc37ed4d7c..2c491e20a7 100644 --- a/common/command.c +++ b/common/command.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -473,12 +474,12 @@ int cmd_get_data_size(char* arg, int default_size) return 2; case 'l': return 4; -#if MEM_SUPPORT_64BIT_DATA - case 'q': - return 8; -#endif case 's': return -2; + case 'q': + if (MEM_SUPPORT_64BIT_DATA) + return 8; + /* no break */ default: return -1; } -- 2.27.0.rc2.251.g90737beb825-goog
[PATCH 3/6] cmd: mem: Drop #ifdef for MEM_SUPPORT_64BIT_DATA
This is defined only when __lp64__ is defined. That means that ulong is
64 bits long. Therefore we don't need to use a separate u64 type on those
architectures.
Fix up the code to take advantage of that, removing the preprocessor
conditions.
Signed-off-by: Simon Glass
---
cmd/mem.c | 117 ++
1 file changed, 38 insertions(+), 79 deletions(-)
diff --git a/cmd/mem.c b/cmd/mem.c
index da02bbce95..9ab6b1dd08 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -34,9 +34,11 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
/* Create a compile-time value */
-#if MEM_SUPPORT_64BIT_DATA
+#ifdef MEM_SUPPORT_64BIT_DATA
+#define SUPPORT_64BIT_DATA 1
#define HELP_Q ", .q"
#else
+#define SUPPORT_64BIT_DATA 0
#define HELP_Q ""
#endif
@@ -123,11 +125,7 @@ static int do_mem_nm(struct cmd_tbl *cmdtp, int flag, int
argc,
static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
-#if MEM_SUPPORT_64BIT_DATA
- u64 writeval;
-#else
- ulong writeval;
-#endif
+ ulong writeval; /* 64-bit if SUPPORT_64BIT_DATA */
ulong addr, count;
int size;
void *buf, *start;
@@ -148,11 +146,10 @@ static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int
argc,
/* Get the value to write.
*/
-#if MEM_SUPPORT_64BIT_DATA
- writeval = simple_strtoull(argv[2], NULL, 16);
-#else
- writeval = simple_strtoul(argv[2], NULL, 16);
-#endif
+ if (SUPPORT_64BIT_DATA)
+ writeval = simple_strtoull(argv[2], NULL, 16);
+ else
+ writeval = simple_strtoul(argv[2], NULL, 16);
/* Count ? */
if (argc == 4) {
@@ -167,10 +164,8 @@ static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int
argc,
while (count-- > 0) {
if (size == 4)
*((u32 *)buf) = (u32)writeval;
-#if MEM_SUPPORT_64BIT_DATA
- else if (size == 8)
- *((u64 *)buf) = (u64)writeval;
-#endif
+ else if (SUPPORT_64BIT_DATA && size == 8)
+ *((ulong *)buf) = writeval;
else if (size == 2)
*((u16 *)buf) = (u16)writeval;
else
@@ -247,11 +242,7 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
int rcode = 0;
const char *type;
const void *buf1, *buf2, *base;
-#if MEM_SUPPORT_64BIT_DATA
- u64 word1, word2;
-#else
- ulong word1, word2;
-#endif
+ ulong word1, word2; /* 64-bit if SUPPORT_64BIT_DATA */
if (argc != 4)
return CMD_RET_USAGE;
@@ -279,11 +270,9 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
if (size == 4) {
word1 = *(u32 *)buf1;
word2 = *(u32 *)buf2;
-#if MEM_SUPPORT_64BIT_DATA
- } else if (size == 8) {
- word1 = *(u64 *)buf1;
- word2 = *(u64 *)buf2;
-#endif
+ } else if (SUPPORT_64BIT_DATA && size == 8) {
+ word1 = *(ulong *)buf1;
+ word2 = *(ulong *)buf2;
} else if (size == 2) {
word1 = *(u16 *)buf1;
word2 = *(u16 *)buf2;
@@ -293,15 +282,9 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
}
if (word1 != word2) {
ulong offset = buf1 - base;
-#if MEM_SUPPORT_64BIT_DATA
- printf("%s at 0x%p (%#0*llx) != %s at 0x%p (%#0*llx)\n",
- type, (void *)(addr1 + offset), size, word1,
- type, (void *)(addr2 + offset), size, word2);
-#else
printf("%s at 0x%08lx (%#0*lx) != %s at 0x%08lx
(%#0*lx)\n",
type, (ulong)(addr1 + offset), size, word1,
type, (ulong)(addr2 + offset), size, word2);
-#endif
rcode = 1;
break;
}
@@ -398,9 +381,7 @@ static int do_mem_loop(struct cmd_tbl *cmdtp, int flag, int
argc,
{
ulong addr, length, i, bytes;
int size;
-#if MEM_SUPPORT_64BIT_DATA
- volatile u64 *llp;
-#endif
+ volatile ulong *llp; /* 64-bit if SUPPORT_64BIT_DATA */
volatile u32 *longp;
volatile u16 *shortp;
volatile u8 *cp;
@@ -431,13 +412,11 @@ static int do_mem_loop(struct cmd_tbl *cmdtp, int flag,
int argc,
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
-#if MEM_SUPPORT_64BIT_DATA
- if (size == 8) {
- llp = (u64 *)buf;
+ if (SUPPORT_64BIT_DATA && size == 8) {
+ llp = (ulong *)buf;
for (;;)
i = *llp;
}
-#endif
if
[PATCH 2/6] cmd: mem: Use a macro to avoid #ifdef in help
It is a bit painful to have #ifdefs in the middle of the help for each
command. Add a macro to avoid this.
Signed-off-by: Simon Glass
---
cmd/mem.c | 68 ++-
1 file changed, 17 insertions(+), 51 deletions(-)
diff --git a/cmd/mem.c b/cmd/mem.c
index fe43427d3c..da02bbce95 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -33,6 +33,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define CONFIG_SYS_MEMTEST_SCRATCH 0
#endif
+/* Create a compile-time value */
+#if MEM_SUPPORT_64BIT_DATA
+#define HELP_Q ", .q"
+#else
+#define HELP_Q ""
+#endif
+
static int mod_mem(struct cmd_tbl *, int, int, int, char * const []);
/* Display values from last command.
@@ -1016,7 +1023,6 @@ static int do_mem_mtest(struct cmd_tbl *cmdtp, int flag,
int argc,
*
* Syntax:
* mm{.b, .w, .l, .q} {addr}
- * nm{.b, .w, .l, .q} {addr}
*/
static int
mod_mem(struct cmd_tbl *cmdtp, int incrflag, int flag, int argc,
@@ -1196,63 +1202,39 @@ static int do_random(struct cmd_tbl *cmdtp, int flag,
int argc,
U_BOOT_CMD(
md, 3, 1, do_mem_md,
"memory display",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address [# of objects]"
-#else
- "[.b, .w, .l] address [# of objects]"
-#endif
+ "[.b, .w, .l" HELP_Q "] address [# of objects]"
);
U_BOOT_CMD(
mm, 2, 1, do_mem_mm,
"memory modify (auto-incrementing address)",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address"
-#else
- "[.b, .w, .l] address"
-#endif
+ "[.b, .w, .l" HELP_Q "] address"
);
U_BOOT_CMD(
nm, 2, 1, do_mem_nm,
"memory modify (constant address)",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address"
-#else
- "[.b, .w, .l] address"
-#endif
+ "[.b, .w, .l" HELP_Q "] address"
);
U_BOOT_CMD(
mw, 4, 1, do_mem_mw,
"memory write (fill)",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address value [count]"
-#else
- "[.b, .w, .l] address value [count]"
-#endif
+ "[.b, .w, .l" HELP_Q "] address value [count]"
);
U_BOOT_CMD(
cp, 4, 1, do_mem_cp,
"memory copy",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] source target count"
-#else
- "[.b, .w, .l] source target count"
-#endif
+ "[.b, .w, .l" HELP_Q "] source target count"
);
U_BOOT_CMD(
cmp,4, 1, do_mem_cmp,
"memory compare",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] addr1 addr2 count"
-#else
- "[.b, .w, .l] addr1 addr2 count"
-#endif
+ "[.b, .w, .l" HELP_Q "] addr1 addr2 count"
);
#ifdef CONFIG_CMD_CRC32
@@ -1299,22 +1281,14 @@ U_BOOT_CMD(
U_BOOT_CMD(
loop, 3, 1, do_mem_loop,
"infinite loop on address range",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address number_of_objects"
-#else
- "[.b, .w, .l] address number_of_objects"
-#endif
+ "[.b, .w, .l" HELP_Q "] address number_of_objects"
);
#ifdef CONFIG_LOOPW
U_BOOT_CMD(
loopw, 4, 1, do_mem_loopw,
"infinite write loop on address range",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address number_of_objects data_to_write"
-#else
- "[.b, .w, .l] address number_of_objects data_to_write"
-#endif
+ "[.b, .w, .l" HELP_Q "] address number_of_objects data_to_write"
);
#endif /* CONFIG_LOOPW */
@@ -1330,21 +1304,13 @@ U_BOOT_CMD(
U_BOOT_CMD(
mdc,4, 1, do_mem_mdc,
"memory display cyclic",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address count delay(ms)"
-#else
- "[.b, .w, .l] address count delay(ms)"
-#endif
+ "[.b, .w, .l" HELP_Q "] address count delay(ms)"
);
U_BOOT_CMD(
mwc,4, 1, do_mem_mwc,
"memory write cyclic",
-#if MEM_SUPPORT_64BIT_DATA
- "[.b, .w, .l, .q] address value delay(ms)"
-#else
- "[.b, .w, .l] address value delay(ms)"
-#endif
+ "[.b, .w, .l" HELP_Q "] address value delay(ms)"
);
#endif /* CONFIG_CMD_MX_CYCLIC */
--
2.27.0.rc2.251.g90737beb825-goog
[PATCH 4/6] display_options: Drop #ifdef for MEM_SUPPORT_64BIT_DATA
This is defined only when __lp64__ is defined. That means that ulong is
64 bits long. Therefore we don't need to use a separate u64 type on those
architectures.
Fix up the code to take advantage of that, removing the preprocessor
conditions.
Also include the missing header file that defines MEM_SUPPORT_64BIT_DATA
Fixes: 09140113108 ("command: Remove the cmd_tbl_t typedef")
Signed-off-by: Simon Glass
---
lib/display_options.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/lib/display_options.c b/lib/display_options.c
index dadfc60560..ea9977cc18 100644
--- a/lib/display_options.c
+++ b/lib/display_options.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -137,19 +138,13 @@ int print_buffer(ulong addr, const void *data, uint
width, uint count,
{
/* linebuf as a union causes proper alignment */
union linebuf {
-#if MEM_SUPPORT_64BIT_DATA
uint64_t uq[MAX_LINE_LENGTH_BYTES/sizeof(uint64_t) + 1];
-#endif
uint32_t ui[MAX_LINE_LENGTH_BYTES/sizeof(uint32_t) + 1];
uint16_t us[MAX_LINE_LENGTH_BYTES/sizeof(uint16_t) + 1];
uint8_t uc[MAX_LINE_LENGTH_BYTES/sizeof(uint8_t) + 1];
} lb;
int i;
-#if MEM_SUPPORT_64BIT_DATA
- uint64_t __maybe_unused x;
-#else
- uint32_t __maybe_unused x;
-#endif
+ ulong x;
if (linelen*width > MAX_LINE_LENGTH_BYTES)
linelen = MAX_LINE_LENGTH_BYTES / width;
@@ -168,20 +163,16 @@ int print_buffer(ulong addr, const void *data, uint
width, uint count,
for (i = 0; i < thislinelen; i++) {
if (width == 4)
x = lb.ui[i] = *(volatile uint32_t *)data;
-#if MEM_SUPPORT_64BIT_DATA
- else if (width == 8)
- x = lb.uq[i] = *(volatile uint64_t *)data;
-#endif
+ else if (MEM_SUPPORT_64BIT_DATA && width == 8)
+ x = lb.uq[i] = *(volatile ulong *)data;
else if (width == 2)
x = lb.us[i] = *(volatile uint16_t *)data;
else
x = lb.uc[i] = *(volatile uint8_t *)data;
#if defined(CONFIG_SPL_BUILD)
printf(" %x", (uint)x);
-#elif defined(MEM_SUPPORT_64BIT_DATA)
- printf(" %0*llx", width * 2, (long long)x);
#else
- printf(" %0*x", width * 2, x);
+ printf(" %0*lx", width * 2, x);
#endif
data += width;
}
--
2.27.0.rc2.251.g90737beb825-goog
[PATCH 1/6] Update MEM_SUPPORT_64BIT_DATA to be always defined
Define this macro always so we don't need the preprocessor to check it.
Convert the users to #if instead of #ifdef.
Note that '#if MEM_SUPPORT_64BIT_DATA' does not give an error if the
macro is not define. It just assumes zero.
Signed-off-by: Simon Glass
---
cmd/mem.c | 54 +--
common/command.c | 2 +-
include/compiler.h| 4 +++-
lib/display_options.c | 6 ++---
4 files changed, 34 insertions(+), 32 deletions(-)
diff --git a/cmd/mem.c b/cmd/mem.c
index 9b97f7bf69..fe43427d3c 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -116,7 +116,7 @@ static int do_mem_nm(struct cmd_tbl *cmdtp, int flag, int
argc,
static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
u64 writeval;
#else
ulong writeval;
@@ -141,7 +141,7 @@ static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int
argc,
/* Get the value to write.
*/
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
writeval = simple_strtoull(argv[2], NULL, 16);
#else
writeval = simple_strtoul(argv[2], NULL, 16);
@@ -160,7 +160,7 @@ static int do_mem_mw(struct cmd_tbl *cmdtp, int flag, int
argc,
while (count-- > 0) {
if (size == 4)
*((u32 *)buf) = (u32)writeval;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
else if (size == 8)
*((u64 *)buf) = (u64)writeval;
#endif
@@ -240,7 +240,7 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
int rcode = 0;
const char *type;
const void *buf1, *buf2, *base;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
u64 word1, word2;
#else
ulong word1, word2;
@@ -272,7 +272,7 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
if (size == 4) {
word1 = *(u32 *)buf1;
word2 = *(u32 *)buf2;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
} else if (size == 8) {
word1 = *(u64 *)buf1;
word2 = *(u64 *)buf2;
@@ -286,7 +286,7 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int
argc,
}
if (word1 != word2) {
ulong offset = buf1 - base;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
printf("%s at 0x%p (%#0*llx) != %s at 0x%p (%#0*llx)\n",
type, (void *)(addr1 + offset), size, word1,
type, (void *)(addr2 + offset), size, word2);
@@ -391,7 +391,7 @@ static int do_mem_loop(struct cmd_tbl *cmdtp, int flag, int
argc,
{
ulong addr, length, i, bytes;
int size;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
volatile u64 *llp;
#endif
volatile u32 *longp;
@@ -424,7 +424,7 @@ static int do_mem_loop(struct cmd_tbl *cmdtp, int flag, int
argc,
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
if (size == 8) {
llp = (u64 *)buf;
for (;;)
@@ -446,7 +446,7 @@ static int do_mem_loop(struct cmd_tbl *cmdtp, int flag, int
argc,
i = *cp;
}
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
if (size == 8) {
for (;;) {
llp = (u64 *)buf;
@@ -489,7 +489,7 @@ static int do_mem_loopw(struct cmd_tbl *cmdtp, int flag,
int argc,
{
ulong addr, length, i, bytes;
int size;
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
volatile u64 *llp;
u64 data;
#else
@@ -519,7 +519,7 @@ static int do_mem_loopw(struct cmd_tbl *cmdtp, int flag,
int argc,
length = simple_strtoul(argv[2], NULL, 16);
/* data to write */
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
data = simple_strtoull(argv[3], NULL, 16);
#else
data = simple_strtoul(argv[3], NULL, 16);
@@ -532,7 +532,7 @@ static int do_mem_loopw(struct cmd_tbl *cmdtp, int flag,
int argc,
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
if (size == 8) {
llp = (u64 *)buf;
for (;;)
@@ -554,7 +554,7 @@ static int do_mem_loopw(struct cmd_tbl *cmdtp, int flag,
int argc,
*cp = data;
}
-#ifdef MEM_SUPPORT_64BIT_DATA
+#if MEM_SUPPORT_64BIT_DATA
if (size == 8) {
for (;;) {
llp = (u64 *)buf;
@@ -1023,7 +1023,7 @@ mod_mem(struct cmd_tbl *cmdtp, int incrflag, int flag,
int
Re: [PATCH 2/2] riscv: sbi: Move sbi_probe_extension() out of CONFIG_SBI_V01
Hi Atish
Atish Patra 於 2020年6月3日 週三 上午2:32寫道：
>
> On Mon, Jun 1, 2020 at 2:09 AM Bin Meng wrote:
> >
> > Hi Rick,
> >
> > On Mon, Jun 1, 2020 at 5:08 PM Rick Chen wrote:
> > >
> > > Hi Bin
> > >
> > > > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > > > Sent: Wednesday, May 27, 2020 5:05 PM
> > > > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> > > > > Cc: Atish Patra; Bin Meng
> > > > > Subject: [PATCH 2/2] riscv: sbi: Move sbi_probe_extension() out of
> > > > > CONFIG_SBI_V01
> > > > >
> > > > > From: Bin Meng
> > > > >
> > > > > sbi_probe_extension() is an API defined in SBI v0.2, not v0.1.
> > > > >
> > > > > Fixes 7e249bc13aaf: ("riscv: Move all SMP related SBI calls to
> > > > > SBI_v01")
> > > > > Signed-off-by: Bin Meng
> > > > > ---
> > > >
> > > > Reviewed-by: Rick Chen
> > > >
> > >
> > > BTW, it seem look like sbi_remote_fence_i, sbi_remote_sfence_vma and
> > > sbi_remote_sfence_vma_asid
> > > are all can be used no mater in SBI_V01 or SBI_V02. Because you have
> > > distinguished them in sbi.h
> >
> > No these calls are different and not compatible between SBI_V01 and SBI_V02.
> >
>
> In addition to that, U-Boot proper enables SMP only for SBI_V01
> because U-Boot doesn't need
> boot all the cores if the supervisor OS & SBI provider supports SBI
> v0.2 with HSM.
>
> Starting with OpenSBI v0.7 & Linux kernel 5.7 supports both. Thus,
> there is no advantage in adding
> redundant code in a generic path that is never going to be used.
>
> Any SBI provider that only supports SBI v0.1, the user can fall back
> to SBI_V01 config.
Thanks for your explanation.
Regards,
Rick
> > See commit 7e249bc13aaf: ("riscv: Move all SMP related SBI calls to
> > SBI_v01")
> >
> > Regards,
> > Bin
>
>
>
> --
> Regards,
> Atish
Re: [PATCH 2/2] riscv: Enable CONFIG_OF_BOARD_FIXUP by default
Hi Atish Atish Patra 於 2020年6月3日 週三 上午2:22寫道： > > On Mon, Jun 1, 2020 at 11:51 PM Rick Chen wrote: > > > > Hi Bin > > > > Bin Meng 於 2020年6月2日 週二 下午2:33寫道： > > > > > > Hi Rick, > > > > > > On Tue, Jun 2, 2020 at 2:16 PM Rick Chen wrote: > > > > > > > > Hi Bin > > > > > > > > Bin Meng 於 2020年6月2日 週二 下午2:13寫道： > > > > > > > > > > Hi Rick, > > > > > > > > > > On Tue, Jun 2, 2020 at 2:04 PM Rick Chen wrote: > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > On Mon, Jun 1, 2020 at 3:36 PM Rick Chen > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > On Thu, May 28, 2020 at 4:17 PM Rick Chen > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > From: Bin Meng [mailto:bmeng...@gmail.com] > > > > > > > > > > > Sent: Wednesday, May 20, 2020 3:40 PM > > > > > > > > > > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List > > > > > > > > > > > Cc: Bin Meng > > > > > > > > > > > Subject: [PATCH 2/2] riscv: Enable CONFIG_OF_BOARD_FIXUP > > > > > > > > > > > by default > > > > > > > > > > > > > > > > > > > > > > From: Bin Meng > > > > > > > > > > > > > > > > > > > > > > Starting from OpenSBI v0.7, the SBI firmware > > > > > > > > > > > inserts/fixes up the reserved memory node for PMP > > > > > > > > > > > protected memory regions. All RISC-V boards needs to copy > > > > > > > > > > > the reserved memory node from the device tree provided by > > > > > > > > > > > the firmware to the device tree used by U-Boot. > > > > > > > > > > > > > > > > > > > > > > Turn on CONFIG_OF_BOARD_FIXUP by default. > > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Bin Meng > > > > > > > > > > > --- > > > > > > > > > > > > > > > > > > > > > > arch/riscv/Kconfig | 3 +++ > > > > > > > > > > > configs/sifive_fu540_defconfig | 1 - > > > > > > > > > > > 2 files changed, 3 insertions(+), 1 deletion(-) > > > > > > > > > > > > > > > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > > > > > > > > > > index fb5fe5a..5176b35 100644 > > > > > > > > > > > --- a/arch/riscv/Kconfig > > > > > > > > > > > +++ b/arch/riscv/Kconfig > > > > > > > > > > > @@ -272,4 +272,7 @@ config STACK_SIZE_SHIFT > > > > > > > > > > > int > > > > > > > > > > > default 14 > > > > > > > > > > > > > > > > > > > > > > +config OF_BOARD_FIXUP > > > > > > > > > > > + default y > > > > > > > > > > > > > > > > > > > > I think it shall invoke by individual board, just like the > > > > > > > > > > description > > > > > > > > > > of riscv_fdt_copy_resv_mem_node function. > > > > > > > > > > > > > > > > > > I believe we should turn on this feature by default for every > > > > > > > > > RISC-V > > > > > > > > > board, because SBI firmware used memory must be marked as > > > > > > > > > reserved > > > > > > > > > otherwise OS might use it and get crashed. For boards which > > > > > > > > > don't want > > > > > > > > > to enable this, they can unset the option in their board > > > > > > > > > defconfig > > > > > > > > > files. This is to reduce some maintenance effort. > > > > > > > > > > > > > > > > But not all RISC-V boards need this configuration. > > > > > > > > If we enable it by default, non spl configuration will run this > > > > > > > > fdt > > > > > > > > fix flow, but it is unnecessary. > > > > > > > > > > > > > > > > > > > > > > Non SPL configuration also needs this, because U-Boot has to > > > > > > > patch the > > > > > > > final DTB that is passed to the kernel. It's a RISC-V architecture > > > > > > > thing. > > > > > > > > > > > > But non SPL configuration will not run openSbi, why it will need > > > > > > this flow ? > > > > > > > > > > > > > > > > Which configuration is this? > > > > > > > > e.q: ae350_rv[32|64]_defconfig > > > > > > > > > > It looks these 2 configs are for U-Boot M-mode. How are they supposed > > > to work, if they do not work with OpenSBI? > > > > They work with BBL(riscv-pk). > > > > Thanks, > > Rick > > > > > > > > Regards, > > > Bin > > How about enabling only if OF_SEPARATE is enabled ? > We don't need a board fixup for prior stage case. > It is a good suggestion. Thanks, Rick > > -- > Regards, > Atish
Re: [PATCH v1 1/2] net: cortina_ni: Addd eth support for Cortina Access CAxxxx SoCs
On Wed, Jun 03, 2020 at 12:18:18AM +, Alex Nemirovsky wrote: > Hi Tom, > > > On Jun 2, 2020, at 6:02 AM, Tom Rini wrote: > > > > On Mon, Jun 01, 2020 at 07:44:25PM -0700, Alex Nemirovsky wrote: > > > >> From: Aaron Tseng > >> > >> Add Cortina Access Ethernet device driver for CA SoCs. > >> This driver supports both legacy and DM_ETH network models. > >> > >> Signed-off-by: Aaron Tseng > >> Signed-off-by: Alex Nemirovsky > >> > >> CC: Joe Hershberger > >> CC: Abbie Chang > >> CC: Tom Rini > > [snip] > >> +#define HEADER_A_SIZE 8 > >> +#define CORTINA_NI_DBG 1 > >> +/*define CORTINA_NI_DBG if individual rx,tx,init needs to be called */ > > > > We have pr_debug, etc, please use those and not a custom debug defiine. > > > >> +#ifdef CONFIG_DM_ETH > >> +#if CORTINA_NI_DBG > >> +static struct udevice *dbg_dev; > >> +#endif > >> +static struct udevice *curr_dev; > >> +#else > > > > The deadline for drivers to convert to DM for ethernet is v2020.07. > > Please rework to not introduce any legacy mode support. Thanks! > > For clarity, we are providing BOTH DM and Legacy mode support in our driver. > Is the request to REMOVE Legacy mode support, even though DM support is > already provided to meet the 2020.07 requirement? Yes, remove the legacy code as there's no non-legacy users in upstream to support. Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 1/2] mtd: rawnand: ca_nand: add Cortina Access Parallel NAND controller support
> On Jun 2, 2020, at 12:20 AM, Miquel Raynal wrote: > > Hi Alex, > > Alex Nemirovsky wrote on Mon, 1 > Jun 2020 14:26:49 -0700: > >> From: Jason Li >> >> Supports all CA SoCs which support a parallel nand controller. >> It should be noted that some CA Soc also support an separate >> SPI serial NAND controller. >> >> This driver only supports the parallel NAND controller. A different >> driver supports the SPI NAND interface controller. >> >> Signed-off-by: Jason Li >> Signed-off-by: Alex Nemirovsky >> >> CC: Miquel Raynal >> CC: Simon Glass >> CC: Tom Rini >> --- >> >> Changes in v3: >> - Include udelay.h to avoid implicit declaration of udelay() >> >> Changes in v2: >> - Cleanup code style to pass checkpatch.pl >> >> MAINTAINERS|2 + >> drivers/mtd/nand/raw/Kconfig | 31 + >> drivers/mtd/nand/raw/Makefile |1 + >> drivers/mtd/nand/raw/ca_nand.c | 4943 >> >> drivers/mtd/nand/raw/ca_nand.h | 3899 +++ > > This is insanely big ! Hi Miquel, could you clarify? Is there a change request? > >> 5 files changed, 8876 insertions(+) >> create mode 100644 drivers/mtd/nand/raw/ca_nand.c >> create mode 100644 drivers/mtd/nand/raw/ca_nand.h >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 8add9d4..6da2ad8 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -181,6 +181,8 @@ F: drivers/gpio/cortina_gpio.c >> F: drivers/watchdog/cortina_wdt.c >> F: drivers/serial/serial_cortina.c >> F: drivers/mmc/ca_dw_mmc.c >> +F: drivers/mtd/nand/raw/ca_nand.c >> +F: drivers/mtd/nand/raw/ca_nand.h >> >> ARM/CZ.NIC TURRIS MOX SUPPORT >> M: Marek Behun >> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig >> index c4d9d31..b3cbfcc 100644 >> --- a/drivers/mtd/nand/raw/Kconfig >> +++ b/drivers/mtd/nand/raw/Kconfig >> @@ -102,6 +102,37 @@ config NAND_BRCMNAND_63158 >>help >> Enable support for broadcom nand driver on bcm63158. >> >> +config NAND_CORTINA >> +tristate "Support Cortina-Access Parallel NAND cntlr." >> +select SYS_NAND_SELF_INIT > > Alignment looks wrong > >> +help >> + This enables the parallel RAW NAND driver for the >> + Cortina-Access CA Family of SoCs. >> + >> +config NAND_CORTINA_ECC_LEVEL >> +int "Cortina-Access Parallel Nand driver HW ECC algorithm" >> +default 3 >> +range 0 5 >> +depends on NAND_CORTINA >> +help >> + NAND Flash ECC algorithm. Value range from 0 to 5. >> + The default value is 3. >> + >> + 0: Hamming algorithm. Correct 3 bad bits in 256 btyes. >> + 1: Hamming algorithm. Correct 3 bad bits in 512 btyes. >> + 2: BCH algorithm. Correct 8 bad bits in 1K btyes. >> + 3: BCH algorithm. Correct 16 bad bits in 1K btyes. >> + 4: BCH algorithm. Correct 24 bad bits in 1K btyes. >> + 5: BCH algorithm. Correct 40 bad bits in 1K btyes. > > Not sure how u-boot guys want to handle this but the current way to > request for a specif correction is to pass nand-ecc-strength and > nand-ecc-size DT properties. If the driver does not support the > requested properties, there is a function (at least in Linux) which > finds the closest correction called nand_ecc_choose_conf(), provided > that you implemented a few specific hooks in your driver. > > But basically, this should be the core's input, not the user, unless > you have a strong reason to do so. > >> + >> +config NAND_CORTINA_ECC_HW_BCH >> + bool >> + default y >> + depends on NAND_CORTINA_ECC_LEVEL=2 \ >> + || NAND_CORTINA_ECC_LEVEL=3 \ >> + || NAND_CORTINA_ECC_LEVEL=4 \ >> + || NAND_CORTINA_ECC_LEVEL=5 >> + >> config NAND_DAVINCI >> bool "Support TI Davinci NAND controller" >>
Re: [PATCH v1 1/2] net: cortina_ni: Addd eth support for Cortina Access CAxxxx SoCs
Hi Tom, > On Jun 2, 2020, at 6:02 AM, Tom Rini wrote: > > On Mon, Jun 01, 2020 at 07:44:25PM -0700, Alex Nemirovsky wrote: > >> From: Aaron Tseng >> >> Add Cortina Access Ethernet device driver for CA SoCs. >> This driver supports both legacy and DM_ETH network models. >> >> Signed-off-by: Aaron Tseng >> Signed-off-by: Alex Nemirovsky >> >> CC: Joe Hershberger >> CC: Abbie Chang >> CC: Tom Rini > [snip] >> +#define HEADER_A_SIZE 8 >> +#define CORTINA_NI_DBG 1 >> +/*define CORTINA_NI_DBG if individual rx,tx,init needs to be called */ > > We have pr_debug, etc, please use those and not a custom debug defiine. > >> +#ifdef CONFIG_DM_ETH >> +#if CORTINA_NI_DBG >> +static struct udevice *dbg_dev; >> +#endif >> +static struct udevice *curr_dev; >> +#else > > The deadline for drivers to convert to DM for ethernet is v2020.07. > Please rework to not introduce any legacy mode support. Thanks! For clarity, we are providing BOTH DM and Legacy mode support in our driver. Is the request to REMOVE Legacy mode support, even though DM support is already provided to meet the 2020.07 requirement? > > -- > Tom
[PATCH 3/6] env: Fix invalid env handling in env_init()
In case the env storage driver marks environment as ENV_INVALID, we must
reset the $ret return value to -ENOENT to let the env init code reset the
environment to the default one a bit further down.
Signed-off-by: Marek Vasut
---
env/env.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/env/env.c b/env/env.c
index dcc25c030b..024d36fdbe 100644
--- a/env/env.c
+++ b/env/env.c
@@ -300,6 +300,9 @@ int env_init(void)
debug("%s: Environment %s init done (ret=%d)\n", __func__,
drv->name, ret);
+
+ if (gd->env_valid == ENV_INVALID)
+ ret = -ENOENT;
}
if (!prio)
--
2.25.1
[PATCH 2/6] env: Add H_DEFAULT flag
Add another internal environment flag which indicates that the operation
is resetting the environment to the default one. This allows the env code
to discern between import of external environment and reset to default.
Signed-off-by: Marek Vasut
---
env/common.c | 3 ++-
include/search.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/env/common.c b/env/common.c
index 088b2aebb4..0db56e610a 100644
--- a/env/common.c
+++ b/env/common.c
@@ -81,6 +81,7 @@ void env_set_default(const char *s, int flags)
debug("Using default environment\n");
}
+ flags |= H_DEFAULT;
if (himport_r(_htab, (char *)default_environment,
sizeof(default_environment), '\0', flags, 0,
0, NULL) == 0)
@@ -99,7 +100,7 @@ int env_set_default_vars(int nvars, char * const vars[], int
flags)
* Special use-case: import from default environment
* (and use \0 as a separator)
*/
- flags |= H_NOCLEAR;
+ flags |= H_NOCLEAR | H_DEFAULT;
return himport_r(_htab, (const char *)default_environment,
sizeof(default_environment), '\0',
flags, 0, nvars, vars);
diff --git a/include/search.h b/include/search.h
index bca36d3abc..c4b50c9630 100644
--- a/include/search.h
+++ b/include/search.h
@@ -112,5 +112,6 @@ int hwalk_r(struct hsearch_data *htab,
#define H_MATCH_METHOD (H_MATCH_IDENT | H_MATCH_SUBSTR | H_MATCH_REGEX)
#define H_PROGRAMMATIC (1 << 9) /* indicate that an import is from env_set() */
#define H_ORIGIN_FLAGS (H_INTERACTIVE | H_PROGRAMMATIC)
+#define H_DEFAULT (1 << 10) /* indicate that an import is default env */
#endif /* _SEARCH_H_ */
--
2.25.1
[PATCH 6/6] env: Add support for explicit write access list
This option marks any U-Boot variable which does not have explicit 'w'
writeable flag set as read-only. This way the environment can be locked
down and only variables explicitly configured to be writeable can ever
be changed by either 'env import', 'env set' or loading user environment
from environment storage.
Signed-off-by: Marek Vasut
---
env/Kconfig | 8
env/flags.c | 92 +++--
include/env_flags.h | 6 ++-
lib/hashtable.c | 5 ++-
4 files changed, 98 insertions(+), 13 deletions(-)
diff --git a/env/Kconfig b/env/Kconfig
index 8166e5df91..f53a1457fb 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -613,6 +613,14 @@ config ENV_APPEND
with newly imported data. This may be used in combination with static
flags to e.g. to protect variables which must not be modified.
+config ENV_WRITEABLE_LIST
+ bool "Permit write access only to listed variables"
+ default n
+ help
+ If defined, only environment variables which explicitly set the 'w'
+ writeable flag can be written and modified at runtime. No variables
+ can be otherwise created, written or imported into the environment.
+
config ENV_ACCESS_IGNORE_FORCE
bool "Block forced environment operations"
default n
diff --git a/env/flags.c b/env/flags.c
index f7a53775c4..a2f6c1a3ec 100644
--- a/env/flags.c
+++ b/env/flags.c
@@ -28,8 +28,15 @@
#define ENV_FLAGS_NET_VARTYPE_REPS ""
#endif
+#if CONFIG_IS_ENABLED(ENV_WRITEABLE_LIST)
+#define ENV_FLAGS_WRITEABLE_VARACCESS_REPS "w"
+#else
+#define ENV_FLAGS_WRITEABLE_VARACCESS_REPS ""
+#endif
+
static const char env_flags_vartype_rep[] = "sdxb" ENV_FLAGS_NET_VARTYPE_REPS;
-static const char env_flags_varaccess_rep[] = "aroc";
+static const char env_flags_varaccess_rep[] =
+ "aroc" ENV_FLAGS_WRITEABLE_VARACCESS_REPS;
static const int env_flags_varaccess_mask[] = {
0,
ENV_FLAGS_VARACCESS_PREVENT_DELETE |
@@ -38,7 +45,11 @@ static const int env_flags_varaccess_mask[] = {
ENV_FLAGS_VARACCESS_PREVENT_DELETE |
ENV_FLAGS_VARACCESS_PREVENT_OVERWR,
ENV_FLAGS_VARACCESS_PREVENT_DELETE |
- ENV_FLAGS_VARACCESS_PREVENT_NONDEF_OVERWR};
+ ENV_FLAGS_VARACCESS_PREVENT_NONDEF_OVERWR,
+#if CONFIG_IS_ENABLED(ENV_WRITEABLE_LIST)
+ ENV_FLAGS_VARACCESS_WRITEABLE,
+#endif
+ };
#ifdef CONFIG_CMD_ENV_FLAGS
static const char * const env_flags_vartype_names[] = {
@@ -56,6 +67,9 @@ static const char * const env_flags_varaccess_names[] = {
"read-only",
"write-once",
"change-default",
+#if CONFIG_IS_ENABLED(ENV_WRITEABLE_LIST)
+ "writeable",
+#endif
};
/*
@@ -130,21 +144,33 @@ enum env_flags_vartype env_flags_parse_vartype(const char
*flags)
*/
enum env_flags_varaccess env_flags_parse_varaccess(const char *flags)
{
+#if CONFIG_IS_ENABLED(ENV_WRITEABLE_LIST)
+ enum env_flags_varaccess va_default = env_flags_varaccess_readonly;
+#else
+ enum env_flags_varaccess va_default = env_flags_varaccess_any;
+#endif
+ enum env_flags_varaccess va;
char *access;
if (strlen(flags) <= ENV_FLAGS_VARACCESS_LOC)
- return env_flags_varaccess_any;
+ return va_default;
access = strchr(env_flags_varaccess_rep,
flags[ENV_FLAGS_VARACCESS_LOC]);
- if (access != NULL)
- return (enum env_flags_varaccess)
+ if (access != NULL) {
+ va = (enum env_flags_varaccess)
(access - _flags_varaccess_rep[0]);
+#if CONFIG_IS_ENABLED(ENV_WRITEABLE_LIST)
+ if (va != env_flags_varaccess_writeable)
+ return env_flags_varaccess_readonly;
+#endif
+ return va;
+ }
printf("## Warning: Unknown environment variable access method '%c'\n",
flags[ENV_FLAGS_VARACCESS_LOC]);
- return env_flags_varaccess_any;
+ return va_default;
}
/*
@@ -152,17 +178,29 @@ enum env_flags_varaccess env_flags_parse_varaccess(const
char *flags)
*/
enum env_flags_varaccess env_flags_parse_varaccess_from_binflags(int binflags)
{
+#if CONFIG_IS_ENABLED(ENV_WRITEABLE_LIST)
+ enum env_flags_varaccess va_default = env_flags_varaccess_readonly;
+#else
+ enum env_flags_varaccess va_default = env_flags_varaccess_any;
+#endif
+ enum env_flags_varaccess va;
int i;
for (i = 0; i < ARRAY_SIZE(env_flags_varaccess_mask); i++)
if (env_flags_varaccess_mask[i] ==
- (binflags & ENV_FLAGS_VARACCESS_BIN_MASK))
- return (enum env_flags_varaccess)i;
+ (binflags & ENV_FLAGS_VARACCESS_BIN_MASK)) {
+ va = (enum env_flags_varaccess)i;
+#if CONFIG_IS_ENABLED(ENV_WRITEABLE_LIST)
+ if (va != env_flags_varaccess_writeable)
+ return
[PATCH 5/6] env: Add option to only ever append environment
Add configuration option which prevents the environment hash table to be
ever cleared and reloaded with different content. This is useful in case
the first environment loaded into the hash table contains e.g. sensitive
content which must not be dropped or reloaded.
Signed-off-by: Marek Vasut
---
env/Kconfig | 9 +
env/env.c | 2 ++
lib/hashtable.c | 4
3 files changed, 15 insertions(+)
diff --git a/env/Kconfig b/env/Kconfig
index ca7fef682b..8166e5df91 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -604,6 +604,15 @@ config DELAY_ENVIRONMENT
later by U-Boot code. With CONFIG_OF_CONTROL this is instead
controlled by the value of /config/load-environment.
+config ENV_APPEND
+ bool "Always append the environment with new data"
+ default n
+ help
+ If defined, the environment hash table is only ever appended with new
+ data, but the existing hash table can never be dropped and reloaded
+ with newly imported data. This may be used in combination with static
+ flags to e.g. to protect variables which must not be modified.
+
config ENV_ACCESS_IGNORE_FORCE
bool "Block forced environment operations"
default n
diff --git a/env/env.c b/env/env.c
index 024d36fdbe..d85f925bcb 100644
--- a/env/env.c
+++ b/env/env.c
@@ -204,7 +204,9 @@ int env_load(void)
ret = drv->load();
if (!ret) {
printf("OK\n");
+#ifdef CONFIG_ENV_APPEND
return 0;
+#endif
} else if (ret == -ENOMSG) {
/* Handle "bad CRC" case */
if (best_prio == -1)
diff --git a/lib/hashtable.c b/lib/hashtable.c
index b96dbe19be..24aef5a085 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -822,6 +822,10 @@ int himport_r(struct hsearch_data *htab,
if (nvars)
memcpy(localvars, vars, sizeof(vars[0]) * nvars);
+#ifdef CONFIG_ENV_APPEND
+ flag |= H_NOCLEAR;
+#endif
+
if ((flag & H_NOCLEAR) == 0 && !nvars) {
/* Destroy old hash table if one exists */
debug("Destroy Hash Table: %p table = %p\n", htab,
--
2.25.1
[PATCH 4/6] env: nowhere: Implement .load callback
Add .load callback for the 'nowhere' environment driver. This is useful
for when the 'nowhere' driver is used in combination with other drivers
and should be used to load the default environment.
Signed-off-by: Marek Vasut
---
env/nowhere.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/env/nowhere.c b/env/nowhere.c
index f5b0a17652..417a636f83 100644
--- a/env/nowhere.c
+++ b/env/nowhere.c
@@ -15,6 +15,12 @@
DECLARE_GLOBAL_DATA_PTR;
+static int env_nowhere_load(void)
+{
+ env_set_default(NULL, 0);
+
+ return 0;
+}
/*
* Because we only ever have the default environment available we must mark
* it as invalid.
@@ -30,5 +36,6 @@ static int env_nowhere_init(void)
U_BOOT_ENV_LOCATION(nowhere) = {
.location = ENVL_NOWHERE,
.init = env_nowhere_init,
+ .load = env_nowhere_load,
ENV_NAME("nowhere")
};
--
2.25.1
[PATCH 1/6] env: Warn on force access if ENV_ACCESS_IGNORE_FORCE set
If the ENV_ACCESS_IGNORE_FORCE is set, inform user that the variable
cannot be force-set if such attempt happens.
Signed-off-by: Marek Vasut
---
env/flags.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/env/flags.c b/env/flags.c
index b88fe7ba9c..f7a53775c4 100644
--- a/env/flags.c
+++ b/env/flags.c
@@ -524,8 +524,10 @@ int env_flags_validate(const struct env_entry *item, const
char *newval,
/* check for access permission */
#ifndef CONFIG_ENV_ACCESS_IGNORE_FORCE
- if (flag & H_FORCE)
+ if (flag & H_FORCE) {
+ printf("## Error: Can't force access to \"%s\"\n", name);
return 0;
+ }
#endif
switch (op) {
case env_op_delete:
--
2.25.1
Re: [PATCH 1/1] sunxi: CONFIG_INIT_SP_RELATIVE=y for Pine64 LTS
On 02/06/2020 20:55, Tom Rini wrote: Hi, > On Tue, Jun 02, 2020 at 09:45:25PM +0200, Heinrich Schuchardt wrote: >> On 6/2/20 5:51 PM, Tom Rini wrote: >>> On Sun, May 31, 2020 at 10:43:00AM +, Heinrich Schuchardt wrote: >>> Booting pine64-lts_defconfig with either of CONFIG_RSA=y or CONFIG_LOG=y fails if CONFIG_INIT_SP_RELATIVE is not set. Signed-off-by: Heinrich Schuchardt --- configs/pine64-lts_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index ef108a1a31..b03bef01b1 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -1,5 +1,8 @@ CONFIG_ARM=y +CONFIG_INIT_SP_RELATIVE=y CONFIG_ARCH_SUNXI=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y >>> >>> Look at the option however. This is something that all sunxi should be >>> selecting. >> >> What indicates that all sunxi should select CONFIG_INIT_SP_RELATIVE? > > config INIT_SP_RELATIVE > bool "Specify the early stack pointer relative to the .bss section" > help > U-Boot typically uses a hard-coded value for the stack pointer > before relocation. Enable this option to instead calculate the > initial SP at run-time. This is useful to avoid hard-coding > addresses > into U-Boot, so that it can be loaded and executed at arbitrary > addresses and thus avoid using arbitrary addresses at runtime. > > If this option is enabled, the early stack pointer is set to > &_bss_start with a offset value added. The offset is specified by > SYS_INIT_SP_BSS_OFFSET. > > And that in turn tells me this is something that's done at the SoC > level, especially for sunxi where things have been abstracted such that > everyone (very roughly) shares the same board file, linker file, etc, > and it's just defconfig+dts* files that change from board to board. I agree on that, this particular defconfig change is generic to all sunxi boards and we should fix this properly for the whole platform. > So, to put it another way, what about the pine64-lts config is unique > and causing this to be needed, but another arm64 sunxi platform would > not? I think were Heinrich came from is selecting CONFIG_RSA for his particular build. I guess this requires a bigger malloc area. Now this somehow collides which how we calculate the stack pointer, but it is too late here to really track this down ;-) Heinrich, can you please give an explanation what problem CONFIG_INIT_SP_RELATIVE fixed and why? It seems like to cause some side effect, but does not sound like the proper solution (because this is more mean for the position independent build option). Cheers, Andre
Re: [PATCH] env: Add option to only ever append environment
On 6/3/20 1:32 AM, Tom Rini wrote: > On Tue, Jun 02, 2020 at 09:06:42PM +0200, Marek Vasut wrote: >> On 6/2/20 7:36 PM, Tom Rini wrote: >> [...] One will append the environment, the other will override it (if you have multiple envs enabled). >>> >>> So it sounds like it wouldn't be valid to have this option differ >>> between SPL and main U-Boot? >> >> Consider the case where you have default env in SPL, and multiple envs >> in U-Boot proper. > > Yes, today you can end up with cases where you build something that > doesn't > work as intended (likely something around falcon boot and/or boot count > limit in env). Which is what I'm getting at here. Is there some > cases where it would make any sense to enable this option in full U-Boot > but disable it in SPL? Yes, like my current use case, where I want to configure the SPL differently than U-Boot itself. SPL doesn't even have environment support enabled, but it might be needed later. >>> >>> Sorry I wasn't clear enough. Does it make sense (when? how?) to have >>> environment in SPL but mismatch this feature? >> >> If you have only one env source in SPL and multiple in U-Boot for >> example. But this is besides the point, > > Yes, so lets set that aside. > >> I want to be able to configure >> my env handling whichever I need it to without working around problems >> like the ones below. > > You're instead adding two others kinds of problems. You're adding code > that would make use of a symbol that doesn't exist. You're also adding > what seems like a non-functional runtime (we set the variable in full > U-Boot and can't read it in SPL). So can you confirm that having this > enabled in full U-Boot but disabled in SPL does not result in the case > of a mismatch in the environment, in the case of having access to more > than just the default compiled environment? I have the env completely disabled in SPL, so it does not. And also, I don't want to end up in the same problem we currently have e.g. with USB gadget, where I have to manually #ifdef CONFIG_SPL_BUILD #undef CONFIG_ options in the board config file. >>> >>> Yes, don't do that, I've had to fix a few of those of late in catching >>> converted but still in config header options. >> >> This is the result of not having a dedicated SPL/TPL config options though. > > Then we should fix that. But not every option is/should be listed in > triplicate. OK, then I can re-do this patch without the CONFIG_IS_ENABLED() and then add another #undef into the board config.
Re: [PATCH] env: Add option to only ever append environment
On Tue, Jun 02, 2020 at 09:06:42PM +0200, Marek Vasut wrote: > On 6/2/20 7:36 PM, Tom Rini wrote: > [...] > >> One will append the environment, the other will override it (if you > >> have > >> multiple envs enabled). > > > > So it sounds like it wouldn't be valid to have this option differ > > between SPL and main U-Boot? > > Consider the case where you have default env in SPL, and multiple envs > in U-Boot proper. > >>> > >>> Yes, today you can end up with cases where you build something that > >>> doesn't > >>> work as intended (likely something around falcon boot and/or boot count > >>> limit in env). Which is what I'm getting at here. Is there some > >>> cases where it would make any sense to enable this option in full U-Boot > >>> but disable it in SPL? > >> > >> Yes, like my current use case, where I want to configure the SPL > >> differently than U-Boot itself. SPL doesn't even have environment > >> support enabled, but it might be needed later. > > > > Sorry I wasn't clear enough. Does it make sense (when? how?) to have > > environment in SPL but mismatch this feature? > > If you have only one env source in SPL and multiple in U-Boot for > example. But this is besides the point, Yes, so lets set that aside. > I want to be able to configure > my env handling whichever I need it to without working around problems > like the ones below. You're instead adding two others kinds of problems. You're adding code that would make use of a symbol that doesn't exist. You're also adding what seems like a non-functional runtime (we set the variable in full U-Boot and can't read it in SPL). So can you confirm that having this enabled in full U-Boot but disabled in SPL does not result in the case of a mismatch in the environment, in the case of having access to more than just the default compiled environment? > >> And also, I don't want to end up in the same problem we currently have > >> e.g. with USB gadget, where I have to manually #ifdef CONFIG_SPL_BUILD > >> #undef CONFIG_ options in the board config file. > > > > Yes, don't do that, I've had to fix a few of those of late in catching > > converted but still in config header options. > > This is the result of not having a dedicated SPL/TPL config options though. Then we should fix that. But not every option is/should be listed in triplicate. -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/8] mx6memcal: Finish migration to defconfig options
Reviewed by: Eric Nelson On 5/26/20 12:06 PM, Tom Rini wrote: The config header for this platform uses '#undef' in a number of cases. All of the MMC related ones were already handled correctly in the defconfig file. In the case of CONFIG_CMD_FUSE, the command was being built and enabled via defconfig. Disable it in the defconfig, cleanup the header. Cc: Eric Nelson Signed-off-by: Tom Rini --- configs/mx6memcal_defconfig | 1 + include/configs/mx6memcal.h | 5 - 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index 8b5e0ff9b134..ed24b7996b6b 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_MEMTEST_START=0x1000 CONFIG_SYS_MEMTEST_END=0x2000 +# CONFIG_CMD_FUSE is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_CACHE=y diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index 3d79a7e43765..b774b167f648 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -13,11 +13,6 @@ #include "mx6_common.h" #include "imx6_spl.h" -#undef CONFIG_MMC -#undef CONFIG_SPL_MMC_SUPPORT -#undef CONFIG_GENERIC_MMC -#undef CONFIG_CMD_FUSE - #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #define CONFIG_MXC_UART
[PATCH 0/4] crypto/fsl: add RNG support
First, improve the compatibility on newer Era CAAMs. These introduced new version registers. Secondly, add RNG support for the CAAM. This way we get random number generator support for EFI for free and KASLR will work with ARM64 kernels booted with bootefi. Michael Walle (4): crypto/fsl: make SEC%u status line consistent crypto/fsl: export caam_get_era() crypto/fsl: support newer SEC modules crypto/fsl: add RNG support drivers/crypto/fsl/Kconfig | 11 + drivers/crypto/fsl/Makefile | 1 + drivers/crypto/fsl/jobdesc.c | 9 drivers/crypto/fsl/jobdesc.h | 3 ++ drivers/crypto/fsl/jr.c | 23 -- drivers/crypto/fsl/rng.c | 87 drivers/crypto/fsl/sec.c | 2 +- include/fsl_sec.h| 57 +++ 8 files changed, 180 insertions(+), 13 deletions(-) create mode 100644 drivers/crypto/fsl/rng.c -- 2.20.1
[PATCH 3/4] crypto/fsl: support newer SEC modules
Since Era 10, the version registers changed. Add the version registers
and use them on newer modules.
Signed-off-by: Michael Walle
---
drivers/crypto/fsl/jr.c | 12 --
include/fsl_sec.h | 51 +++--
2 files changed, 54 insertions(+), 9 deletions(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 612e86818b..9f3da9c474 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -498,9 +498,17 @@ static int instantiate_rng(uint8_t sec_idx)
static u8 get_rng_vid(uint8_t sec_idx)
{
ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
- u32 cha_vid = sec_in32(>chavid_ls);
+ u8 vid;
- return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
+ if (caam_get_era() < 10) {
+ vid = (sec_in32(>chavid_ls) & SEC_CHAVID_RNG_LS_MASK)
+ >> SEC_CHAVID_LS_RNG_SHIFT;
+ } else {
+ vid = (sec_in32(>vreg.rng) & CHA_VER_VID_MASK)
+ >> CHA_VER_VID_SHIFT;
+ }
+
+ return vid;
}
/*
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 2ebb75c9b2..8dce0bbb1b 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -73,6 +73,41 @@ struct rng4tst {
u32 rsvd2[15];
};
+/* Version registers (Era 10+) */
+struct version_regs {
+ u32 crca; /* CRCA_VERSION */
+ u32 afha; /* AFHA_VERSION */
+ u32 kfha; /* KFHA_VERSION */
+ u32 pkha; /* PKHA_VERSION */
+ u32 aesa; /* AESA_VERSION */
+ u32 mdha; /* MDHA_VERSION */
+ u32 desa; /* DESA_VERSION */
+ u32 snw8a; /* SNW8A_VERSION */
+ u32 snw9a; /* SNW9A_VERSION */
+ u32 zuce; /* ZUCE_VERSION */
+ u32 zuca; /* ZUCA_VERSION */
+ u32 ccha; /* CCHA_VERSION */
+ u32 ptha; /* PTHA_VERSION */
+ u32 rng;/* RNG_VERSION */
+ u32 trng; /* TRNG_VERSION */
+ u32 aaha; /* AAHA_VERSION */
+ u32 rsvd[10];
+ u32 sr; /* SR_VERSION */
+ u32 dma;/* DMA_VERSION */
+ u32 ai; /* AI_VERSION */
+ u32 qi; /* QI_VERSION */
+ u32 jr; /* JR_VERSION */
+ u32 deco; /* DECO_VERSION */
+};
+
+#define CHA_VER_NUM_MASK 0x00ff
+#define CHA_VER_MISC_SHIFT 8
+#define CHA_VER_MISC_MASK 0xff00
+#define CHA_VER_REV_SHIFT 16
+#define CHA_VER_REV_MASK 0x00ff
+#define CHA_VER_VID_SHIFT 24
+#define CHA_VER_VID_MASK 0xff00
+
typedef struct ccsr_sec {
u32 res0;
u32 mcfgr; /* Master CFG Register */
@@ -98,17 +133,19 @@ typedef struct ccsr_sec {
u32 drr;/* DECO Reset Register */
u8 res5[0x4d8];
struct rng4tst rng; /* RNG Registers */
- u8 res6[0x8a0];
+ u8 res6[0x780];
+ struct version_regs vreg; /* version registers since era 10 */
+ u8 res7[0xa0];
u32 crnr_ms;/* CHA Revision Number Register, MS */
u32 crnr_ls;/* CHA Revision Number Register, LS */
u32 ctpr_ms;/* Compile Time Parameters Register, MS */
u32 ctpr_ls;/* Compile Time Parameters Register, LS */
- u8 res7[0x10];
+ u8 res8[0x10];
u32 far_ms; /* Fault Address Register, MS */
u32 far_ls; /* Fault Address Register, LS */
u32 falr; /* Fault Address LIODN Register */
u32 fadr; /* Fault Address Detail Register */
- u8 res8[0x4];
+ u8 res9[0x4];
u32 csta; /* CAAM Status Register */
u32 smpart; /* Secure Memory Partition Parameters */
u32 smvid; /* Secure Memory Version ID */
@@ -121,16 +158,16 @@ typedef struct ccsr_sec {
u32 secvid_ms; /* SEC Version ID Register, MS */
u32 secvid_ls; /* SEC Version ID Register, LS */
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
- u8 res9[0x6f020];
+ u8 res10[0x6f020];
#else
- u8 res9[0x6020];
+ u8 res10[0x6020];
#endif
u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
- u8 res10[0x8ffd8];
+ u8 res11[0x8ffd8];
#else
- u8 res10[0x8fd8];
+ u8 res11[0x8fd8];
#endif
} ccsr_sec_t;
--
2.20.1
[PATCH 1/4] crypto/fsl: make SEC%u status line consistent
Align the status line with all the other output in U-Boot.
Before the change:
DDR3.9 GiB (DDR3, 32-bit, CL=11, ECC on)
SEC0: RNG instantiated
WDT: Started with servicing (60s timeout)
After the change:
DDR3.9 GiB (DDR3, 32-bit, CL=11, ECC on)
SEC0: RNG instantiated
WDT: Started with servicing (60s timeout)
Signed-off-by: Michael Walle
---
drivers/crypto/fsl/jr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index e2d9216cfc..612e86818b 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -657,7 +657,7 @@ int sec_init_idx(uint8_t sec_idx)
printf("SEC%u: RNG instantiation failed\n", sec_idx);
return -1;
}
- printf("SEC%u: RNG instantiated\n", sec_idx);
+ printf("SEC%u: RNG instantiated\n", sec_idx);
}
#endif
return ret;
--
2.20.1
[PATCH 2/4] crypto/fsl: export caam_get_era()
We need the era in other modules, too. For example, to get the RNG
version.
Signed-off-by: Michael Walle
---
drivers/crypto/fsl/sec.c | 2 +-
include/fsl_sec.h| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c
index a2c0bfaf44..a2fe5b1cc9 100644
--- a/drivers/crypto/fsl/sec.c
+++ b/drivers/crypto/fsl/sec.c
@@ -98,7 +98,7 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
fdt_strerror(err));
}
#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */
-static u8 caam_get_era(void)
+u8 caam_get_era(void)
{
static const struct {
u16 ip_id;
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index c0d2c7e866..2ebb75c9b2 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -316,6 +316,8 @@ int blob_dek(const u8 *src, u8 *dst, u8 len);
int sec_init_idx(uint8_t);
#endif
int sec_init(void);
+
+u8 caam_get_era(void);
#endif
#endif /* __FSL_SEC_H */
--
2.20.1
[PATCH 4/4] crypto/fsl: add RNG support
Register the random number generator with the rng subsystem in u-boot.
This way it can be used by EFI as well as for the 'rng' command.
Signed-off-by: Michael Walle
---
drivers/crypto/fsl/Kconfig | 11 +
drivers/crypto/fsl/Makefile | 1 +
drivers/crypto/fsl/jobdesc.c | 9
drivers/crypto/fsl/jobdesc.h | 3 ++
drivers/crypto/fsl/jr.c | 9
drivers/crypto/fsl/rng.c | 84
6 files changed, 117 insertions(+)
create mode 100644 drivers/crypto/fsl/rng.c
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 181a1e5e99..5936b77494 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -45,3 +45,14 @@ config SYS_FSL_SEC_COMPAT
config SYS_FSL_SEC_LE
bool "Little-endian access to Freescale Secure Boot"
+
+if FSL_CAAM
+
+config FSL_CAAM_RNG
+ bool "Enable Random Number Generator support"
+ depends on DM_RNG
+ default y
+ help
+ Enable support for the random number generator module of the CAAM.
+
+endif
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index cfb36f3bb9..a5e8d38e38 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
obj-$(CONFIG_CMD_BLOB) += fsl_blob.o
obj-$(CONFIG_CMD_DEKBLOB) += fsl_blob.o
obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
+obj-$(CONFIG_FSL_CAAM_RNG) += rng.o
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c
index 2f35e0c90b..5602a3d93c 100644
--- a/drivers/crypto/fsl/jobdesc.c
+++ b/drivers/crypto/fsl/jobdesc.c
@@ -286,6 +286,15 @@ void inline_cnstr_jobdesc_rng_instantiation(uint32_t
*desc, int handle)
}
}
+void inline_cnstr_jobdesc_rng(u32 *desc, void *data_out, u32 size)
+{
+ dma_addr_t dma_data_out = virt_to_phys(data_out);
+
+ init_job_desc(desc, 0);
+ append_operation(desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG);
+ append_fifo_store(desc, dma_data_out, size, FIFOST_TYPE_RNGSTORE);
+}
+
/* Change key size to bytes form bits in calling function*/
void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
struct pk_in_params *pkin, uint8_t *out,
diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h
index d782c46b9d..35075ff434 100644
--- a/drivers/crypto/fsl/jobdesc.h
+++ b/drivers/crypto/fsl/jobdesc.h
@@ -41,7 +41,10 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t
*key_idnfr,
void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle);
+void inline_cnstr_jobdesc_rng(u32 *desc, void *data_out, u32 size);
+
void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
struct pk_in_params *pkin, uint8_t *out,
uint32_t out_siz);
+
#endif
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 9f3da9c474..8ecc0f05b0 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -19,6 +19,7 @@
#include
#include
#endif
+#include
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
@@ -665,6 +666,14 @@ int sec_init_idx(uint8_t sec_idx)
printf("SEC%u: RNG instantiation failed\n", sec_idx);
return -1;
}
+#ifdef CONFIG_DM_RNG
+ if (IS_ENABLED(CONFIG_DM_RNG)) {
+ ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
+NULL);
+ if (ret)
+ printf("Couldn't bind rng driver (%d)\n", ret);
+ }
+#endif
printf("SEC%u: RNG instantiated\n", sec_idx);
}
#endif
diff --git a/drivers/crypto/fsl/rng.c b/drivers/crypto/fsl/rng.c
new file mode 100644
index 00..3da318d767
--- /dev/null
+++ b/drivers/crypto/fsl/rng.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 Michael Walle
+ *
+ * Driver for Freescale Cryptographic Accelerator and Assurance
+ * Module (CAAM) hardware random number generator.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "desc_constr.h"
+#include "jobdesc.h"
+#include "jr.h"
+
+#define CAAM_RNG_MAX_FIFO_STORE_SIZE 16
+#define CAAM_RNG_DESC_LEN (3 * CAAM_CMD_SZ + CAAM_PTR_SZ)
+
+struct caam_rng_platdata {
+ u32 desc[CAAM_RNG_DESC_LEN / 4];
+ u8 data[CAAM_RNG_MAX_FIFO_STORE_SIZE] __aligned(ARCH_DMA_MINALIGN);
+};
+
+static int caam_rng_read_one(struct caam_rng_platdata *pdata)
+{
+ int size = CAAM_RNG_MAX_FIFO_STORE_SIZE;
+ int ret;
+
+ ret = run_descriptor_jr(pdata->desc);
+ if (ret < 0)
+ return -EIO;
+
+ invalidate_dcache_range((unsigned long)pdata->data,
+ (unsigned long)pdata->data +
[PATCH] serial: Convert ARM_DCC to Kconfig
The symbol "CONFIG_ARM_DCC" is used to control building drivers/serial/arm_dcc.c. Provide a simple Kconfig entry for this. Cc: Luca Ceresoli Cc: Michal Simek Cc: Tom McLeod Cc: Mike Looijmans Signed-off-by: Tom Rini --- Note that this is a pre-req for http://patchwork.ozlabs.org/project/uboot/patch/4fbd0373ed4b10dda62371137c7d3a1c59fb0c7c.1590660308.git.michal.si...@xilinx.com/ --- .../avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 1 + configs/bitmain_antminer_s9_defconfig | 1 + configs/syzygy_hub_defconfig| 1 + configs/topic_miami_defconfig | 1 + configs/topic_miamilite_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + configs/xilinx_versal_mini_defconfig| 1 + configs/xilinx_versal_mini_emmc0_defconfig | 1 + configs/xilinx_versal_mini_emmc1_defconfig | 1 + configs/xilinx_versal_virt_defconfig| 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xilinx_zynqmp_mini_defconfig| 1 + configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 + configs/xilinx_zynqmp_mini_nand_defconfig | 1 + configs/xilinx_zynqmp_mini_nand_single_defconfig| 1 + configs/xilinx_zynqmp_mini_qspi_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig| 1 + configs/zynq_cse_nand_defconfig | 1 + configs/zynq_cse_nor_defconfig | 1 + configs/zynq_cse_qspi_defconfig | 1 + drivers/serial/Kconfig | 6 ++ include/configs/xilinx_versal.h | 1 - include/configs/xilinx_zynqmp.h | 1 - include/configs/zynq-common.h | 2 -- scripts/config_whitelist.txt| 1 - 26 files changed, 27 insertions(+), 5 deletions(-) diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index 785283fbea8f..030d28a5dfc7 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -55,6 +55,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y CONFIG_SPI=y CONFIG_ZYNQMP_GQSPI=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index 9f8802383689..ef5f5676157c 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -66,6 +66,7 @@ CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y # CONFIG_WATCHDOG is not set CONFIG_WDT=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index db6077c11bd1..242ebf89e149 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -48,6 +48,7 @@ CONFIG_PHY_XILINX=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index f50d12d154e2..26b6a8e034f1 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -49,6 +49,7 @@ CONFIG_SF_DEFAULT_SPEED=10800 CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y CONFIG_ZYNQ_QSPI=y CONFIG_USB=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index d2fe64ed9ee4..fb967e90f851 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -49,6 +49,7 @@ CONFIG_SF_DEFAULT_SPEED=10800 CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y CONFIG_ZYNQ_QSPI=y CONFIG_USB=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 9afd7f6bcada..23ad93f423ac 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -49,6 +49,7 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set # CONFIG_NETDEVICES is not set CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y CONFIG_ZYNQ_QSPI=y CONFIG_USB=y diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index a3b71ccc3e1b..3186c9843e42 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -54,4 +54,5 @@
Re: [PATCH v2 00/10] new rtc methods, rtc command, and tests
Hi Rasmus, On Tue, 2 Jun 2020 at 13:44, Rasmus Villemoes wrote: > > On 02/06/2020 21.29, Simon Glass wrote: > > Hi Rasmus, > > > > On Tue, 2 Jun 2020 at 12:40, Rasmus Villemoes > > wrote: > >> > >> Urgh. The name rtc_read() is already used for a local helper by a number > >> of rtc drivers (also rtc_write, for somewhat fewer drivers). So I can > >> still call the methods ->read and ->write, but the functions will need > >> another name. Probably dm_rtc_read/dm_rtc_write, since this is only for > >> DM-enabled drivers anyway, and matches the existing dm_rtc_get/dm_rtc_set. > > > > The conflict is OK, since at some point those drivers will be updated > > to DM or removed. I'd rather avoid the dm_ prefix if not necessary. > > There are some DM-enabled drivers that still use those names as local > helpers, e.g. rx8025.c and pt7c4338.c. OK then they probably need a prefix of the driver name on those functions. Regards, Simon
[PATCH 2/2] omap5: uevm: convert to device model
Convert omap5 uevm board to device model.
Signed-off-by: Tero Kristo
---
arch/arm/dts/omap5-u-boot.dtsi | 42 ++
board/ti/omap5_uevm/evm.c | 78 +-
configs/omap5_uevm_defconfig | 9
3 files changed, 61 insertions(+), 68 deletions(-)
diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi
index 39071e223d..5a1c7bc9fe 100644
--- a/arch/arm/dts/omap5-u-boot.dtsi
+++ b/arch/arm/dts/omap5-u-boot.dtsi
@@ -7,6 +7,7 @@
* Based on "dra7.dtsi"
*/
+#ifdef CONFIG_DRA7XX
/{
chosen {
tick-timer =
@@ -105,3 +106,44 @@
{
u-boot,dm-spl;
};
+
+#else /* OMAP54XX */
+_cfg {
+ segment@0 {
+ /* SCM Core */
+ target-module@2000 {
+ compatible = "simple-bus";
+ };
+
+ /* USB HS */
+ target-module@64000 {
+ compatible = "simple-bus";
+ };
+ };
+};
+
+_per {
+ segment@0 {
+ /* UART3 */
+ target-module@2 {
+ compatible = "simple-bus";
+ };
+
+ /* I2C1 */
+ target-module@7 {
+ compatible = "simple-bus";
+ };
+
+ /* MMC1 */
+ target-module@9c000 {
+ compatible = "simple-bus";
+ };
+
+ /* MMC2 */
+ target-module@b4000 {
+ compatible = "simple-bus";
+ };
+ };
+};
+
+#endif
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index e35f319b46..319bb6aa64 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -149,39 +150,21 @@ int board_init(void)
return 0;
}
-int board_eth_init(bd_t *bis)
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
return 0;
}
+#endif /* CONFIG_SPL_OS_BOOT */
-#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
-static void enable_host_clocks(void)
+int board_eth_init(bd_t *bis)
{
- int auxclk;
- int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
- OPTFCLKEN_HSIC480M_P3_CLK |
- OPTFCLKEN_HSIC60M_P2_CLK |
- OPTFCLKEN_HSIC480M_P2_CLK |
- OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
-
- /* Enable port 2 and 3 clocks*/
- setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
-
- /* Enable port 2 and 3 usb host ports tll clocks*/
- setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
- (OPTFCLKEN_USB_CH1_CLK_ENABLE |
OPTFCLKEN_USB_CH2_CLK_ENABLE));
-#ifdef CONFIG_USB_XHCI_OMAP
- /* Enable the USB OTG Super speed clocks */
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
- (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
-#endif
-
- auxclk = readl((*prcm)->scrm_auxclk1);
- /* Request auxilary clock */
- auxclk |= AUXCLK_ENABLE_MASK;
- writel(auxclk, (*prcm)->scrm_auxclk1);
+ return 0;
}
-#endif
/**
* @brief misc_init_r - Configure EVM board specific configurations
@@ -223,45 +206,6 @@ int board_mmc_init(bd_t *bis)
}
#endif
-#ifdef CONFIG_USB_EHCI_HCD
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
- .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- int ret;
-
- enable_host_clocks();
-
- ret = omap_ehci_hcd_init(index, _bdata, hccr, hcor);
- if (ret < 0) {
- puts("Failed to initialize ehci\n");
- return ret;
- }
-
- return 0;
-}
-
-int ehci_hcd_stop(void)
-{
- return omap_ehci_hcd_stop();
-}
-
-void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
-{
- /* The LAN9730 needs to be reset after the port power has been set. */
- if (port == 3) {
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
- udelay(10);
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
- }
-}
-#endif
-
#ifdef CONFIG_USB_XHCI_OMAP
/**
* @brief board_usb_init - Configure EVM board specific configurations
@@ -276,8 +220,6 @@ int board_usb_init(int index, enum usb_init_type init)
ret = palmas_enable_ss_ldo();
#endif
- enable_host_clocks();
-
return 0;
}
#endif
diff --git a/configs/omap5_uevm_defconfig
[PATCH 0/2] omap5 uevm: convert to device model
Hi, Following the omap4 panda conversion series, this converts the omap5-uevm board to device model. Some semi nasty hacks were needed in the omap5-u-boot.dtsi files as this is common to both dra7xx and omap5, due to overloading of dra7xx architecture on top of omap5. Fixing that requires some more patching, so I just did a simple #ifdef within the u-boot specific dtsi file for now. -Tero -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Re: [PATCH v2 12/13] armv8: layerscape: relocate spin table if EFI_LOADER is enabled
Am 2020-06-02 22:00, schrieb Heinrich Schuchardt:
On 6/1/20 9:53 PM, Michael Walle wrote:
On ARM64, a 64kb region is reserved for the runtime services code.
Unfortunately, this code overlaps with the spin table code, which also
needs to be reserved. Thus now that the code is relocatable, allocate
a
new page from EFI, copy the spin table code into it, update any
pointers
to the old region and the start the secondary CPUs.
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/fsl-layerscape/mp.c | 36
++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index d50c5a437b..bd85351705 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -79,6 +79,10 @@ int fsl_layerscape_wake_seconday_cores(void)
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
u64 *table;
+#ifdef CONFIG_EFI_LOADER
+ u64 reloc_addr = U32_MAX;
+ efi_status_t ret;
+#endif
#ifdef COUNTER_FREQUENCY_REAL
/* update for secondary cores */
@@ -87,6 +91,38 @@ int fsl_layerscape_wake_seconday_cores(void)
(unsigned long)&__real_cntfrq + 8);
#endif
+#ifdef CONFIG_EFI_LOADER
+ /*
+ * EFI will reserve 64kb for its runtime services. This will
probably
+ * overlap with our spin table code, which is why we have to
relocate
+* it.
+* Keep this after the __real_cntfrq update, so we have it when we
+* copy the complete section here.
+*/
+ ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
+EFI_RESERVED_MEMORY_TYPE,
+efi_size_in_pages(secondary_boot_code_size),
+_addr);
+ if (ret == EFI_SUCCESS) {
+ debug("Relocating spin table from %llx to %llx (size %lx)\n",
+ (u64)secondary_boot_code_start, reloc_addr,
+ secondary_boot_code_size);
+ memcpy((void *)reloc_addr, secondary_boot_code_start,
+ secondary_boot_code_size);
+ flush_dcache_range(reloc_addr,
+ reloc_addr + secondary_boot_code_size);
dcache flush is done here. but icache is missing, correct.
+
+ /* set new entry point for secondary cores */
+ secondary_boot_addr += (void *)reloc_addr -
+ secondary_boot_code_start;
+ flush_dcache_range((unsigned long)_boot_addr,
+ (unsigned long)_boot_addr + 8);
Wouldn't you want to flush the complete target range of memcpy() and
afterwards call invalidate_icache_all(). At least this is what we do in
other cases after copying instructions. Cf. efi_runtime_relocate().
see above.
-michael
+
+ /* this will be used to reserve the memory */
+ secondary_boot_code_start = (void *)reloc_addr;
+ }
+#endif
+
cores = cpu_mask();
/* Clear spin table so that secondary processors
* observe the correct value after waking up from wfe.
Re: [PATCH 1/1] config: remove CONFIG_ARMV8_SWITCH_TO_EL1 from whitelist.txt
On Tue, Jun 02, 2020 at 09:45:56PM +0200, Heinrich Schuchardt wrote:
> Since commit 208bdaf2ae5f ("vexpress/aemv8a: drop
> CONFIG_ARMV8_SWITCH_TO_EL1") no board uses CONFIG_ARMV8_SWITCH_TO_EL1. So
> we should remove this setting from whitelist.txt. If anybody should ever
> need it again, he should add a Kconfig option.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> scripts/config_whitelist.txt | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index fe9a1971cc..15b77c981e 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -49,7 +49,6 @@ CONFIG_ARMV7_PSCI_1_0
> CONFIG_ARMV7_SECURE_BASE
> CONFIG_ARMV7_SECURE_MAX_SIZE
> CONFIG_ARMV7_SECURE_RESERVE_SIZE
> -CONFIG_ARMV8_SWITCH_TO_EL1
> CONFIG_ARM_ARCH_CP15_ERRATA
> CONFIG_ARM_DCC
> CONFIG_ARM_FREQ
Nak, the file is auto-generated. That said, scripts/build-whitelist.sh
might be able to note that up top without breaking the logic used to
break builds that add new symbols.
The next problem however is that the code around
CONFIG_ARMV8_SWITCH_TO_EL1 hasn't been removed, and needs to be
otherwise the symbol will be listed again when I run the generator next.
Thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH v2 12/13] armv8: layerscape: relocate spin table if EFI_LOADER is enabled
On 6/1/20 9:53 PM, Michael Walle wrote:
> On ARM64, a 64kb region is reserved for the runtime services code.
> Unfortunately, this code overlaps with the spin table code, which also
> needs to be reserved. Thus now that the code is relocatable, allocate a
> new page from EFI, copy the spin table code into it, update any pointers
> to the old region and the start the secondary CPUs.
>
> Signed-off-by: Michael Walle
> ---
> arch/arm/cpu/armv8/fsl-layerscape/mp.c | 36 ++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> index d50c5a437b..bd85351705 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> @@ -79,6 +79,10 @@ int fsl_layerscape_wake_seconday_cores(void)
> u32 cores, cpu_up_mask = 1;
> int i, timeout = 10;
> u64 *table;
> +#ifdef CONFIG_EFI_LOADER
> + u64 reloc_addr = U32_MAX;
> + efi_status_t ret;
> +#endif
>
> #ifdef COUNTER_FREQUENCY_REAL
> /* update for secondary cores */
> @@ -87,6 +91,38 @@ int fsl_layerscape_wake_seconday_cores(void)
> (unsigned long)&__real_cntfrq + 8);
> #endif
>
> +#ifdef CONFIG_EFI_LOADER
> + /*
> + * EFI will reserve 64kb for its runtime services. This will probably
> + * overlap with our spin table code, which is why we have to relocate
> + * it.
> + * Keep this after the __real_cntfrq update, so we have it when we
> + * copy the complete section here.
> + */
> + ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
> + EFI_RESERVED_MEMORY_TYPE,
> + efi_size_in_pages(secondary_boot_code_size),
> + _addr);
> + if (ret == EFI_SUCCESS) {
> + debug("Relocating spin table from %llx to %llx (size %lx)\n",
> + (u64)secondary_boot_code_start, reloc_addr,
> + secondary_boot_code_size);
> + memcpy((void *)reloc_addr, secondary_boot_code_start,
> +secondary_boot_code_size);
> + flush_dcache_range(reloc_addr,
> +reloc_addr + secondary_boot_code_size);
> +
> + /* set new entry point for secondary cores */
> + secondary_boot_addr += (void *)reloc_addr -
> +secondary_boot_code_start;
> + flush_dcache_range((unsigned long)_boot_addr,
> +(unsigned long)_boot_addr + 8);
Wouldn't you want to flush the complete target range of memcpy() and
afterwards call invalidate_icache_all(). At least this is what we do in
other cases after copying instructions. Cf. efi_runtime_relocate().
Best regards
Heinrich
> +
> + /* this will be used to reserve the memory */
> + secondary_boot_code_start = (void *)reloc_addr;
> + }
> +#endif
> +
> cores = cpu_mask();
> /* Clear spin table so that secondary processors
>* observe the correct value after waking up from wfe.
>
Re: [PATCH 1/1] sunxi: CONFIG_INIT_SP_RELATIVE=y for Pine64 LTS
On Tue, Jun 02, 2020 at 09:45:25PM +0200, Heinrich Schuchardt wrote: > On 6/2/20 5:51 PM, Tom Rini wrote: > > On Sun, May 31, 2020 at 10:43:00AM +, Heinrich Schuchardt wrote: > > > >> Booting pine64-lts_defconfig with either of CONFIG_RSA=y or CONFIG_LOG=y > >> fails if CONFIG_INIT_SP_RELATIVE is not set. > >> > >> Signed-off-by: Heinrich Schuchardt > >> --- > >> configs/pine64-lts_defconfig | 3 +++ > >> 1 file changed, 3 insertions(+) > >> > >> diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig > >> index ef108a1a31..b03bef01b1 100644 > >> --- a/configs/pine64-lts_defconfig > >> +++ b/configs/pine64-lts_defconfig > >> @@ -1,5 +1,8 @@ > >> CONFIG_ARM=y > >> +CONFIG_INIT_SP_RELATIVE=y > >> CONFIG_ARCH_SUNXI=y > >> +CONFIG_SYS_MALLOC_F_LEN=0x8000 > >> +CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 > >> CONFIG_SPL=y > >> CONFIG_MACH_SUN50I=y > >> CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y > > > > Look at the option however. This is something that all sunxi should be > > selecting. > > What indicates that all sunxi should select CONFIG_INIT_SP_RELATIVE? config INIT_SP_RELATIVE bool "Specify the early stack pointer relative to the .bss section" help U-Boot typically uses a hard-coded value for the stack pointer before relocation. Enable this option to instead calculate the initial SP at run-time. This is useful to avoid hard-coding addresses into U-Boot, so that it can be loaded and executed at arbitrary addresses and thus avoid using arbitrary addresses at runtime. If this option is enabled, the early stack pointer is set to &_bss_start with a offset value added. The offset is specified by SYS_INIT_SP_BSS_OFFSET. And that in turn tells me this is something that's done at the SoC level, especially for sunxi where things have been abstracted such that everyone (very roughly) shares the same board file, linker file, etc, and it's just defconfig+dts* files that change from board to board. So, to put it another way, what about the pine64-lts config is unique and causing this to be needed, but another arm64 sunxi platform would not? Thanks! -- Tom signature.asc Description: PGP signature
[PATCH 1/1] config: remove CONFIG_ARMV8_SWITCH_TO_EL1 from whitelist.txt
Since commit 208bdaf2ae5f ("vexpress/aemv8a: drop
CONFIG_ARMV8_SWITCH_TO_EL1") no board uses CONFIG_ARMV8_SWITCH_TO_EL1. So
we should remove this setting from whitelist.txt. If anybody should ever
need it again, he should add a Kconfig option.
Signed-off-by: Heinrich Schuchardt
---
scripts/config_whitelist.txt | 1 -
1 file changed, 1 deletion(-)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index fe9a1971cc..15b77c981e 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -49,7 +49,6 @@ CONFIG_ARMV7_PSCI_1_0
CONFIG_ARMV7_SECURE_BASE
CONFIG_ARMV7_SECURE_MAX_SIZE
CONFIG_ARMV7_SECURE_RESERVE_SIZE
-CONFIG_ARMV8_SWITCH_TO_EL1
CONFIG_ARM_ARCH_CP15_ERRATA
CONFIG_ARM_DCC
CONFIG_ARM_FREQ
--
2.26.2
Re: [PATCH 1/1] sunxi: CONFIG_INIT_SP_RELATIVE=y for Pine64 LTS
On 6/2/20 5:51 PM, Tom Rini wrote: > On Sun, May 31, 2020 at 10:43:00AM +, Heinrich Schuchardt wrote: > >> Booting pine64-lts_defconfig with either of CONFIG_RSA=y or CONFIG_LOG=y >> fails if CONFIG_INIT_SP_RELATIVE is not set. >> >> Signed-off-by: Heinrich Schuchardt >> --- >> configs/pine64-lts_defconfig | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig >> index ef108a1a31..b03bef01b1 100644 >> --- a/configs/pine64-lts_defconfig >> +++ b/configs/pine64-lts_defconfig >> @@ -1,5 +1,8 @@ >> CONFIG_ARM=y >> +CONFIG_INIT_SP_RELATIVE=y >> CONFIG_ARCH_SUNXI=y >> +CONFIG_SYS_MALLOC_F_LEN=0x8000 >> +CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 >> CONFIG_SPL=y >> CONFIG_MACH_SUN50I=y >> CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y > > Look at the option however. This is something that all sunxi should be > selecting. What indicates that all sunxi should select CONFIG_INIT_SP_RELATIVE? > And if this is intentional as part of the design, an audit > of the other ARM64 SoCs would be in order to see who else didn't know > they needed to select this. Thanks! >
Re: [PATCH v2 00/10] new rtc methods, rtc command, and tests
On 02/06/2020 21.29, Simon Glass wrote: > Hi Rasmus, > > On Tue, 2 Jun 2020 at 12:40, Rasmus Villemoes > wrote: >> >> Urgh. The name rtc_read() is already used for a local helper by a number >> of rtc drivers (also rtc_write, for somewhat fewer drivers). So I can >> still call the methods ->read and ->write, but the functions will need >> another name. Probably dm_rtc_read/dm_rtc_write, since this is only for >> DM-enabled drivers anyway, and matches the existing dm_rtc_get/dm_rtc_set. > > The conflict is OK, since at some point those drivers will be updated > to DM or removed. I'd rather avoid the dm_ prefix if not necessary. There are some DM-enabled drivers that still use those names as local helpers, e.g. rx8025.c and pt7c4338.c. Rasmus
Re: [PATCH v2 06/10] rtc: add rtc command
Hi Rasmus,
On Tue, 2 Jun 2020 at 08:36, Rasmus Villemoes
wrote:
>
> On 02/06/2020 15.22, Simon Glass wrote:
> > Hi Rasmus,
> >
> > On Tue, 2 Jun 2020 at 03:13, Rasmus Villemoes
> > wrote:
> >>
> >> On 31/05/2020 16.07, Simon Glass wrote:
> >>> Hi Rasmus,
> >>>
> >>> On Tue, 19 May 2020 at 16:01, Rasmus Villemoes
> >>> wrote:
>
> >
> > [..]
> >
> +int do_rtc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> + static int curr_rtc = 0;
> + struct udevice *dev;
> + int ret, idx;
> +
> + if (argc < 2)
> + return CMD_RET_USAGE;
> +
> + argc--;
> + argv++;
> +
> + if (!strcmp(argv[0], "list")) {
> >>>
> >>> It is comment in U-Boot to just check the letters that are needed. So
> >>> here you could do (*argv[0] == 'l')
> >>
> >> Yes, and I consider that an anti-pattern. It makes it impossible to
> >> later introduce another (sub)command which starts with a
> >> previously-unique prefix. Now, if that "just type a unique prefix"
> >> wasn't official, so scripts were always supposed to use the full names,
> >> it wouldn't be that big a problem (scripts written for later versions of
> >> U-Boot, or U-Boots configured with more (sub)commands, could still fail
> >> silently if used on an earlier U-Boot or one with fewer (sub)commands
> >> instead of producing a "usage" error message), but
> >> https://www.denx.de/wiki/view/DULG/UBootCommandLineInterface explicitly
> >> mentions that as a feature (and says h can be used for help, which it
> >> can't when the hash command is built in, perfectly exemplifying what I'm
> >> talking about).
> >
> > Hah funny. Using an abbreviation is only possible if no other command
> > starts with the same leters.
> >
> > It is certainly very risky to use abbreviations in scripts. I would
> > not recommend it. Abbreviations are for interactive use. If you have
> > auto-completion on you can use tab.
>
> Exactly, so the ability to use the abbreviated form doesn't really buy
> anything - it's risky in scripts, and interactively, it merely saves a
> tab keystroke (and that's all lost in the cognitive overhead of having
> to remember just what abbrev is enough).
Not quite:
- tab is an extra, unnecessary keystroke
- many comments don't implement auto-complete (e.g. try 'gpio i'
- auto-complete adds to code size
- fully checking the string adds to code size
>
> > But here we are talking about a sub-command, which is a bit more
> > controlled, in that it doesn't depend on what other commands the user
> > enables.
>
> True, but the same point applies; if I allowed "rtc w", one couldn't
> easily later add an "rtc wobble" subcommand (ok, my imagination is
> lacking, but you get the idea).
>
> > Anyway, it's up to you what you want to do here.
>
> In that case I'll keep checking for the full name of subcommands.
OK.
Regards,
Simon
Re: [PATCH v2 00/10] new rtc methods, rtc command, and tests
Hi Rasmus, On Tue, 2 Jun 2020 at 12:40, Rasmus Villemoes wrote: > > On 20/05/2020 00.01, Rasmus Villemoes wrote: > > I need access to registers other than just the timekeeping ones of the > > pcf2127, so I wanted to implement ->read8 and ->write8. But for > > testing these it appeared there was no convenient way to invoke those > > from the shell, so I also ended up adding such a command. > > > > Also, it seemed more natural to provide array variants that can read > > or write several registers at once, so rtc_ops is expanded a bit. > > > > Changes in v2: > > > > - Use simply "read" and "write" instead of "read8_array", > > "write8_array", both for functions and methods, as suggested by > > Simon. > > Urgh. The name rtc_read() is already used for a local helper by a number > of rtc drivers (also rtc_write, for somewhat fewer drivers). So I can > still call the methods ->read and ->write, but the functions will need > another name. Probably dm_rtc_read/dm_rtc_write, since this is only for > DM-enabled drivers anyway, and matches the existing dm_rtc_get/dm_rtc_set. The conflict is OK, since at some point those drivers will be updated to DM or removed. I'd rather avoid the dm_ prefix if not necessary. Regards, Simon
Re: [PATCHv2 01/36] dm: spi: Convert Freescale ESPI driver to driver model
On Tue, Jun 2, 2020 at 7:10 PM Zhiqiang Hou wrote:
>
> From: Chuanhua Han
>
> Modify the Freescale ESPI driver to support the driver model.
> Also resolved the following problems:
>
> = WARNING ==
> This board does not use CONFIG_DM_SPI. Please update
> the board before v2019.04 for no dm conversion
> and v2019.07 for partially dm converted drivers.
> Failure to update can lead to driver/board removal
> See doc/driver-model/MIGRATION.txt for more info.
>
> = WARNING ==
> This board does not use CONFIG_DM_SPI_FLASH. Please update
> the board to use CONFIG_SPI_FLASH before the v2019.07 release.
> Failure to update by the deadline may result in board removal.
> See doc/driver-model/MIGRATION.txt for more info.
>
>
> Signed-off-by: Chuanhua Han
> Signed-off-by: Xiaowei Bao
> Signed-off-by: Hou Zhiqiang
> ---
> V2:
> - Rebase the patch, no change intended.
>
> drivers/spi/fsl_espi.c | 444
> include/dm/platform_data/fsl_espi.h | 16 +
> 2 files changed, 337 insertions(+), 123 deletions(-)
> create mode 100644 include/dm/platform_data/fsl_espi.h
>
> diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
> index 50d194f614..5c76fd962e 100644
> --- a/drivers/spi/fsl_espi.c
> +++ b/drivers/spi/fsl_espi.c
> @@ -3,7 +3,9 @@
> * eSPI controller driver.
> *
> * Copyright 2010-2011 Freescale Semiconductor, Inc.
> + * Copyright 2020 NXP
> * Author: Mingkai Hu (mingkai...@freescale.com)
> + *Chuanhua Han (chuanhua@nxp.com)
> */
>
> #include
> @@ -14,10 +16,16 @@
> #include
> #include
> #include
> +#include
> +#include
> +#include
> +#include
>
> struct fsl_spi_slave {
> struct spi_slave slave;
> ccsr_espi_t *espi;
> + u32 speed_hz;
> + unsigned intcs;
> unsigned intdiv16;
> unsigned intpm;
> int tx_timeout;
> @@ -31,6 +39,9 @@ struct fsl_spi_slave {
> #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
> #define US_PER_SECOND 100UL
>
> +/* default SCK frequency, unit: HZ */
> +#define FSL_ESPI_DEFAULT_SCK_FREQ 1000
> +
> #define ESPI_MAX_CS_NUM4
> #define ESPI_FIFO_WIDTH_BIT32
>
> @@ -65,116 +76,27 @@ struct fsl_spi_slave {
>
> #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
>
> -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> - unsigned int max_hz, unsigned int mode)
> -{
> - struct fsl_spi_slave *fsl;
> - sys_info_t sysinfo;
> - unsigned long spibrg = 0;
> - unsigned long spi_freq = 0;
> - unsigned char pm = 0;
> -
> - if (!spi_cs_is_valid(bus, cs))
> - return NULL;
> -
> - fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
> - if (!fsl)
> - return NULL;
> -
> - fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
> - fsl->mode = mode;
> - fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
> -
> - /* Set eSPI BRG clock source */
> - get_sys_info();
> - spibrg = sysinfo.freq_systembus / 2;
> - fsl->div16 = 0;
> - if ((spibrg / max_hz) > 32) {
> - fsl->div16 = ESPI_CSMODE_DIV16;
> - pm = spibrg / (max_hz * 16 * 2);
> - if (pm > 16) {
> - pm = 16;
> - debug("Requested speed is too low: %d Hz, %ld Hz "
> - "is used.\n", max_hz, spibrg / (32 * 16));
> - }
> - } else
> - pm = spibrg / (max_hz * 2);
> - if (pm)
> - pm--;
> - fsl->pm = pm;
> -
> - if (fsl->div16)
> - spi_freq = spibrg / ((pm + 1) * 2 * 16);
> - else
> - spi_freq = spibrg / ((pm + 1) * 2);
> -
> - /* set tx_timeout to 10 times of one espi FIFO entry go out */
> - fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
> - * 10), spi_freq);
> -
> - return >slave;
> -}
> -
> -void spi_free_slave(struct spi_slave *slave)
> -{
> - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> - free(fsl);
> -}
> -
> -int spi_claim_bus(struct spi_slave *slave)
> +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs)
> {
> struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
> ccsr_espi_t *espi = fsl->espi;
> - unsigned char pm = fsl->pm;
> - unsigned int cs = slave->cs;
> - unsigned int mode = fsl->mode;
> - unsigned int div16 = fsl->div16;
> - int i;
> -
> - debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs);
> -
> - /* Enable eSPI interface */
> - out_be32(>mode, ESPI_MODE_RXTHR(3)
> - | ESPI_MODE_TXTHR(4) |
Re: [PATCH]: cmd: part: add part block command
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
hm...
It seems that the changes never reached upstream:
git://github.com/01org/edison-u-boot.git branch edison-v2014.04
this branch was implementing 'part info' sub-command which was useful to
retrieve partition info.
the new repo:
git://github.com/edison-fw/u-boot.git branch acpi-v2020.04 does implement
'part number' but does not implement neither 'info' or 'block'.
I do not insist for you to take this patch, but I think it is useful (it is
the simplest version which supports all needed functionality).
If you think the same, let me know. I can change name of the sub-command or
implement this in a different way, if needed.
Thank you,
Razvan
On 2020-06-02 at 18:51, tr...@konsulko.com wrote:
> On Tue, Jun 02, 2020 at 11:36:48AM -0700, razvan becheriu wrote:
> > -BEGIN PGP SIGNED MESSAGE-
> > Hash: SHA256
> >
> > here is the implementation of the functions:
> >
> > # function ota_conv_sizes
> > # Convert a bytes size to a block size
> > # input bytesize : size in bytes to convert
> > # input blksize : size of a block in bytes
> > # output num_blk : converted size in blocks
> > setenv ota_conv_sizes 'setexpr num_blk $bytesize / $blksize ; setexpr
> > mod_blk $bytesize % $blksize ; if itest $mod_blk > 0 ; then setexpr
num_blk
> > $num_blk + 1; fi;'
> >
> > # function ota_mmc_write
> > # Write a memory buffer to mmc drive
> > # input floadaddr: address of buffer to write
> > # input u_part_start : block start in mmc
> > # input num_blk : number of block to write
> > setenv ota_mmc_write 'if itest $ota_verbose == 1 ; then echo "mmc write
> > ${floadaddr} ${u_part_start} ${num_blk};"; fi; mmc write $floadaddr
> > $u_part_start $num_blk; ret=$?; if itest $ret != 0 ; then setenv
> > ota_abort_reason "mmc write ${floadaddr} ${u_part_start} ${num_blk}
> > failed"; setenv ota_abort 1; fi;'
> >
> > the old u-boot version supported 'part info mmc 0:${u_part_num}
> > u_part_start u_part_sz u_part_blksz;' to get the block size.
>
> Old upstream U-Boot?
>
> --
> Tom
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[PATCH v3 10/10] test: dm: rtc: add tests of rtc shell command
Add tests of the "list", "read" and "write" subcommands of the rtc
shell command.
Reviewed-by: Simon Glass
Signed-off-by: Rasmus Villemoes
---
test/dm/rtc.c | 58 +++
1 file changed, 58 insertions(+)
diff --git a/test/dm/rtc.c b/test/dm/rtc.c
index ff1bc7b7f6..dd037a6e17 100644
--- a/test/dm/rtc.c
+++ b/test/dm/rtc.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -175,6 +176,63 @@ static int dm_test_rtc_read_write(struct unit_test_state
*uts)
}
DM_TEST(dm_test_rtc_read_write, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+/* Test 'rtc list' command */
+static int dm_test_rtc_cmd_list(struct unit_test_state *uts)
+{
+ console_record_reset();
+
+ run_command("rtc list", 0);
+ ut_assert_nextline("RTC #0 - rtc@43");
+ ut_assert_nextline("RTC #1 - rtc@61");
+ ut_assert_console_end();
+
+ return 0;
+}
+DM_TEST(dm_test_rtc_cmd_list, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test 'rtc read' and 'rtc write' commands */
+static int dm_test_rtc_cmd_rw(struct unit_test_state *uts)
+{
+ console_record_reset();
+
+ run_command("rtc dev 0", 0);
+ ut_assert_nextline("RTC #0 - rtc@43");
+ ut_assert_console_end();
+
+ run_command("rtc write 0x30 aabb", 0);
+ ut_assert_console_end();
+
+ run_command("rtc read 0x30 2", 0);
+ ut_assert_nextline("0030: aa bb
..");
+ ut_assert_console_end();
+
+ run_command("rtc dev 1", 0);
+ ut_assert_nextline("RTC #1 - rtc@61");
+ ut_assert_console_end();
+
+ run_command("rtc write 0x30 ccdd", 0);
+ ut_assert_console_end();
+
+ run_command("rtc read 0x30 2", 0);
+ ut_assert_nextline("0030: cc dd
..");
+ ut_assert_console_end();
+
+ /*
+* Switch back to device #0, check that its aux registers
+* still have the same values.
+*/
+ run_command("rtc dev 0", 0);
+ ut_assert_nextline("RTC #0 - rtc@43");
+ ut_assert_console_end();
+
+ run_command("rtc read 0x30 2", 0);
+ ut_assert_nextline("0030: aa bb
..");
+ ut_assert_console_end();
+
+ return 0;
+}
+DM_TEST(dm_test_rtc_cmd_rw, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
/* Reset the time */
static int dm_test_rtc_reset(struct unit_test_state *uts)
{
--
2.23.0
[PATCH v3 09/10] test: dm: rtc: add test of dm_rtc_read, dm_rtc_write
Define a few aux registers and check that they can be read/written
individually. Also check that one can access the time-keeping
registers directly and get the expected results.
Reviewed-by: Simon Glass
Signed-off-by: Rasmus Villemoes
---
arch/sandbox/include/asm/rtc.h | 5
test/dm/rtc.c | 45 ++
2 files changed, 50 insertions(+)
diff --git a/arch/sandbox/include/asm/rtc.h b/arch/sandbox/include/asm/rtc.h
index 1fbfea7999..5bb032f59f 100644
--- a/arch/sandbox/include/asm/rtc.h
+++ b/arch/sandbox/include/asm/rtc.h
@@ -21,6 +21,11 @@ enum {
REG_RESET = 0x20,
+ REG_AUX0= 0x30,
+ REG_AUX1,
+ REG_AUX2,
+ REG_AUX3,
+
REG_COUNT = 0x80,
};
diff --git a/test/dm/rtc.c b/test/dm/rtc.c
index e072fd618b..ff1bc7b7f6 100644
--- a/test/dm/rtc.c
+++ b/test/dm/rtc.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -130,6 +131,50 @@ static int dm_test_rtc_set_get(struct unit_test_state *uts)
}
DM_TEST(dm_test_rtc_set_get, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+static int dm_test_rtc_read_write(struct unit_test_state *uts)
+{
+ struct rtc_time time;
+ struct udevice *dev, *emul;
+ long old_offset;
+ u8 buf[4], reg;
+
+ ut_assertok(uclass_get_device(UCLASS_RTC, 0, ));
+
+ memcpy(buf, "car", 4);
+ ut_assertok(dm_rtc_write(dev, REG_AUX0, buf, 4));
+ memset(buf, '\0', sizeof(buf));
+ ut_assertok(dm_rtc_read(dev, REG_AUX0, buf, 4));
+ ut_asserteq(memcmp(buf, "car", 4), 0);
+
+ reg = 'b';
+ ut_assertok(dm_rtc_write(dev, REG_AUX0, , 1));
+ memset(buf, '\0', sizeof(buf));
+ ut_assertok(dm_rtc_read(dev, REG_AUX0, buf, 4));
+ ut_asserteq(memcmp(buf, "bar", 4), 0);
+
+ reg = 't';
+ ut_assertok(dm_rtc_write(dev, REG_AUX2, , 1));
+ memset(buf, '\0', sizeof(buf));
+ ut_assertok(dm_rtc_read(dev, REG_AUX1, buf, 3));
+ ut_asserteq(memcmp(buf, "at", 3), 0);
+
+ ut_assertok(i2c_emul_find(dev, ));
+ ut_assert(emul != NULL);
+
+ old_offset = sandbox_i2c_rtc_set_offset(emul, false, 0);
+ ut_assertok(dm_rtc_get(dev, ));
+
+ ut_assertok(dm_rtc_read(dev, REG_SEC, , 1));
+ ut_asserteq(time.tm_sec, reg);
+ ut_assertok(dm_rtc_read(dev, REG_MDAY, , 1));
+ ut_asserteq(time.tm_mday, reg);
+
+ sandbox_i2c_rtc_set_offset(emul, true, old_offset);
+
+ return 0;
+}
+DM_TEST(dm_test_rtc_read_write, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
/* Reset the time */
static int dm_test_rtc_reset(struct unit_test_state *uts)
{
--
2.23.0
[PATCH v3 07/10] rtc: sandbox-rtc: fix set method
The current set method is broken; a simple test case is to first set
the date to something in April, then change the date to 31st May:
=> date 040412122020.34
Date: 2020-04-04 (Saturday)Time: 12:12:34
=> date 053112122020.34
Date: 2020-05-01 (Friday)Time: 12:12:34
or via the amending of the existing rtc_set_get test case similarly:
$ ./u-boot -T -v
=> ut dm rtc_set_get
Test: dm_test_rtc_set_get: rtc.c
expected: 31/08/2004 18:18:00
actual: 01/08/2004 18:18:00
The problem is that after each register write,
sandbox_i2c_rtc_complete_write() gets called and sets the internal
time from the current set of registers. However, when we get to
writing 31 to mday, the registers are in an inconsistent state (mon is
still 4), so the mktime machinery ends up translating April 31st to
May 1st. Upon the next register write, the registers are populated by
sandbox_i2c_rtc_prepare_read(), so the 31 we just wrote to mday gets
overwritten by a 1.
Fix it by writing all registers at once, and for consistency, update
the get method to retrieve them all with one "i2c transfer".
Reviewed-by: Simon Glass
Signed-off-by: Rasmus Villemoes
---
drivers/rtc/sandbox_rtc.c | 65 +++
test/dm/rtc.c | 15 -
2 files changed, 38 insertions(+), 42 deletions(-)
diff --git a/drivers/rtc/sandbox_rtc.c b/drivers/rtc/sandbox_rtc.c
index b08d758a74..77065e49c7 100644
--- a/drivers/rtc/sandbox_rtc.c
+++ b/drivers/rtc/sandbox_rtc.c
@@ -14,55 +14,38 @@
static int sandbox_rtc_get(struct udevice *dev, struct rtc_time *time)
{
- time->tm_sec = dm_i2c_reg_read(dev, REG_SEC);
- if (time->tm_sec < 0)
- return time->tm_sec;
- time->tm_min = dm_i2c_reg_read(dev, REG_MIN);
- if (time->tm_min < 0)
- return time->tm_min;
- time->tm_hour = dm_i2c_reg_read(dev, REG_HOUR);
- if (time->tm_hour < 0)
- return time->tm_hour;
- time->tm_mday = dm_i2c_reg_read(dev, REG_MDAY);
- if (time->tm_mday < 0)
- return time->tm_mday;
- time->tm_mon = dm_i2c_reg_read(dev, REG_MON);
- if (time->tm_mon < 0)
- return time->tm_mon;
- time->tm_year = dm_i2c_reg_read(dev, REG_YEAR);
- if (time->tm_year < 0)
- return time->tm_year;
- time->tm_year += 1900;
- time->tm_wday = dm_i2c_reg_read(dev, REG_WDAY);
- if (time->tm_wday < 0)
- return time->tm_wday;
+ u8 buf[7];
+ int ret;
+
+ ret = dm_i2c_read(dev, REG_SEC, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ time->tm_sec = buf[REG_SEC - REG_SEC];
+ time->tm_min = buf[REG_MIN - REG_SEC];
+ time->tm_hour = buf[REG_HOUR - REG_SEC];
+ time->tm_mday = buf[REG_MDAY - REG_SEC];
+ time->tm_mon = buf[REG_MON - REG_SEC];
+ time->tm_year = buf[REG_YEAR - REG_SEC] + 1900;
+ time->tm_wday = buf[REG_WDAY - REG_SEC];
return 0;
}
static int sandbox_rtc_set(struct udevice *dev, const struct rtc_time *time)
{
+ u8 buf[7];
int ret;
- ret = dm_i2c_reg_write(dev, REG_SEC, time->tm_sec);
- if (ret < 0)
- return ret;
- ret = dm_i2c_reg_write(dev, REG_MIN, time->tm_min);
- if (ret < 0)
- return ret;
- ret = dm_i2c_reg_write(dev, REG_HOUR, time->tm_hour);
- if (ret < 0)
- return ret;
- ret = dm_i2c_reg_write(dev, REG_MDAY, time->tm_mday);
- if (ret < 0)
- return ret;
- ret = dm_i2c_reg_write(dev, REG_MON, time->tm_mon);
- if (ret < 0)
- return ret;
- ret = dm_i2c_reg_write(dev, REG_YEAR, time->tm_year - 1900);
- if (ret < 0)
- return ret;
- ret = dm_i2c_reg_write(dev, REG_WDAY, time->tm_wday);
+ buf[REG_SEC - REG_SEC] = time->tm_sec;
+ buf[REG_MIN - REG_SEC] = time->tm_min;
+ buf[REG_HOUR - REG_SEC] = time->tm_hour;
+ buf[REG_MDAY - REG_SEC] = time->tm_mday;
+ buf[REG_MON - REG_SEC] = time->tm_mon;
+ buf[REG_YEAR - REG_SEC] = time->tm_year - 1900;
+ buf[REG_WDAY - REG_SEC] = time->tm_wday;
+
+ ret = dm_i2c_write(dev, REG_SEC, buf, sizeof(buf));
if (ret < 0)
return ret;
diff --git a/test/dm/rtc.c b/test/dm/rtc.c
index 88f86581cc..e072fd618b 100644
--- a/test/dm/rtc.c
+++ b/test/dm/rtc.c
@@ -70,7 +70,20 @@ static int dm_test_rtc_set_get(struct unit_test_state *uts)
old_base_time = sandbox_i2c_rtc_get_set_base_time(emul, -1);
memset(, '\0', sizeof(time));
- time.tm_mday = 25;
+ time.tm_mday = 3;
+ time.tm_mon = 6;
+ time.tm_year = 2004;
+ time.tm_sec = 0;
+ time.tm_min = 18;
+ time.tm_hour = 18;
+ ut_assertok(dm_rtc_set(dev, ));
+
+ memset(, '\0', sizeof(cmp));
+ ut_assertok(dm_rtc_get(dev, ));
+ ut_assertok(cmp_times(, , true));
+
+ memset(, '\0', sizeof(time));
+
[PATCH v3 04/10] rtc: pcf2127: provide ->read method
This simply consists of renaming the existing pcf2127_read_reg()
helper to follow the naming of the other
methods (i.e. pcf2127_rtc_) and changing the type of its
"len" parameter.
Reviewed-by: Simon Glass
Signed-off-by: Rasmus Villemoes
---
drivers/rtc/pcf2127.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c
index c423960b34..eea72ad522 100644
--- a/drivers/rtc/pcf2127.c
+++ b/drivers/rtc/pcf2127.c
@@ -23,8 +23,7 @@
#define PCF2127_REG_MO 0x08
#define PCF2127_REG_YR 0x09
-static int pcf2127_read_reg(struct udevice *dev, uint offset,
- u8 *buffer, int len)
+static int pcf2127_rtc_read(struct udevice *dev, uint offset, u8 *buffer, uint
len)
{
struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
struct i2c_msg msg;
@@ -73,7 +72,7 @@ static int pcf2127_rtc_get(struct udevice *dev, struct
rtc_time *tm)
int ret = 0;
uchar buf[10] = { PCF2127_REG_CTRL1 };
- ret = pcf2127_read_reg(dev, PCF2127_REG_CTRL1, buf, sizeof(buf));
+ ret = pcf2127_rtc_read(dev, PCF2127_REG_CTRL1, buf, sizeof(buf));
if (ret < 0)
return ret;
@@ -110,6 +109,7 @@ static const struct rtc_ops pcf2127_rtc_ops = {
.get = pcf2127_rtc_get,
.set = pcf2127_rtc_set,
.reset = pcf2127_rtc_reset,
+ .read = pcf2127_rtc_read,
};
static const struct udevice_id pcf2127_rtc_ids[] = {
--
2.23.0
[PATCH v3 05/10] rtc: pcf2127: provide ->write method
Reviewed-by: Simon Glass
Signed-off-by: Rasmus Villemoes
---
drivers/rtc/pcf2127.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c
index eea72ad522..88ff8c52c3 100644
--- a/drivers/rtc/pcf2127.c
+++ b/drivers/rtc/pcf2127.c
@@ -43,6 +43,12 @@ static int pcf2127_rtc_read(struct udevice *dev, uint
offset, u8 *buffer, uint l
return dm_i2c_xfer(dev, , 1);
}
+static int pcf2127_rtc_write(struct udevice *dev, uint offset,
+const u8 *buffer, uint len)
+{
+ return dm_i2c_write(dev, offset, buffer, len);
+}
+
static int pcf2127_rtc_set(struct udevice *dev, const struct rtc_time *tm)
{
uchar buf[7] = {0};
@@ -110,6 +116,7 @@ static const struct rtc_ops pcf2127_rtc_ops = {
.set = pcf2127_rtc_set,
.reset = pcf2127_rtc_reset,
.read = pcf2127_rtc_read,
+ .write = pcf2127_rtc_write,
};
static const struct udevice_id pcf2127_rtc_ids[] = {
--
2.23.0
[PATCH v3 02/10] rtc: add dm_rtc_write() helper
Similar to dm_rtc_read(), introduce a helper that allows the caller to
write multiple consecutive 8-bit registers with one call. If the
driver provides the ->write method, use that, otherwise loop using
->write8.
Reviewed-by: Simon Glass
Signed-off-by: Rasmus Villemoes
---
drivers/rtc/rtc-uclass.c | 18 ++
include/rtc.h| 24
2 files changed, 42 insertions(+)
diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c
index 92cc8c5664..a8714156c6 100644
--- a/drivers/rtc/rtc-uclass.c
+++ b/drivers/rtc/rtc-uclass.c
@@ -58,6 +58,24 @@ int dm_rtc_read(struct udevice *dev, unsigned int reg, u8
*buf, unsigned int len
return 0;
}
+int dm_rtc_write(struct udevice *dev, unsigned int reg,
+const u8 *buf, unsigned int len)
+{
+ struct rtc_ops *ops = rtc_get_ops(dev);
+
+ assert(ops);
+ if (ops->write)
+ return ops->write(dev, reg, buf, len);
+ if (!ops->write8)
+ return -ENOSYS;
+ while (len--) {
+ int ret = ops->write8(dev, reg++, *buf++);
+ if (ret < 0)
+ return ret;
+ }
+ return 0;
+}
+
int rtc_read8(struct udevice *dev, unsigned int reg)
{
struct rtc_ops *ops = rtc_get_ops(dev);
diff --git a/include/rtc.h b/include/rtc.h
index 6887fe4d42..9538e54b74 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -67,6 +67,18 @@ struct rtc_ops {
int (*read)(struct udevice *dev, unsigned int reg,
u8 *buf, unsigned int len);
+ /**
+* write() - Write multiple 8-bit registers
+*
+* @dev:Device to write to
+* @reg:First register to write
+* @buf:Input buffer
+* @len:Number of registers to write
+* @return 0 if OK, -ve on error
+*/
+ int (*write)(struct udevice *dev, unsigned int reg,
+const u8 *buf, unsigned int len);
+
/**
* read8() - Read an 8-bit register
*
@@ -132,6 +144,18 @@ int dm_rtc_reset(struct udevice *dev);
*/
int dm_rtc_read(struct udevice *dev, unsigned int reg, u8 *buf, unsigned int
len);
+/**
+ * dm_rtc_write() - Write multiple 8-bit registers
+ *
+ * @dev: Device to write to
+ * @reg: First register to write
+ * @buf: Input buffer
+ * @len: Number of registers to write
+ * @return 0 if OK, -ve on error
+ */
+int dm_rtc_write(struct udevice *dev, unsigned int reg,
+const u8 *buf, unsigned int len);
+
/**
* rtc_read8() - Read an 8-bit register
*
--
2.23.0
[PATCH v3 08/10] rtc: i2c_rtc_emul: catch any write to the "reset" register
It's more natural that any write that happens to touch the reset register should cause a reset, rather than just a write that starts at that offset. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- drivers/rtc/i2c_rtc_emul.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/i2c_rtc_emul.c b/drivers/rtc/i2c_rtc_emul.c index a010af411b..7f78ff83cb 100644 --- a/drivers/rtc/i2c_rtc_emul.c +++ b/drivers/rtc/i2c_rtc_emul.c @@ -197,7 +197,8 @@ static int sandbox_i2c_rtc_xfer(struct udevice *emul, struct i2c_msg *msg, /* Write the register */ memcpy(plat->reg + offset, ptr, len); - if (offset == REG_RESET) + /* If the reset register was written to, do reset. */ + if (offset <= REG_RESET && REG_RESET < offset + len) reset_time(emul); } } -- 2.23.0
[PATCH v3 06/10] rtc: add rtc command
Mostly as an aid for debugging RTC drivers, provide a command that can
be used to read/write arbitrary registers (assuming the driver
provides the read/write methods or their single-register-at-a-time
variants).
Signed-off-by: Rasmus Villemoes
---
cmd/Kconfig | 6 ++
cmd/Makefile | 1 +
cmd/rtc.c| 167 +++
3 files changed, 174 insertions(+)
create mode 100644 cmd/rtc.c
diff --git a/cmd/Kconfig b/cmd/Kconfig
index f9be1988f6..7eea25facd 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1715,6 +1715,12 @@ config CMD_DATE
Enable the 'date' command for getting/setting the time/date in RTC
devices.
+config CMD_RTC
+ bool "rtc"
+ depends on DM_RTC
+ help
+ Enable the 'rtc' command for low-level access to RTC devices.
+
config CMD_TIME
bool "time"
help
diff --git a/cmd/Makefile b/cmd/Makefile
index 974ad48b0a..c7992113e4 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -120,6 +120,7 @@ obj-$(CONFIG_CMD_REISER) += reiser.o
obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
obj-$(CONFIG_CMD_RNG) += rng.o
obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o
+obj-$(CONFIG_CMD_RTC) += rtc.o
obj-$(CONFIG_SANDBOX) += host.o
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_CMD_NVME) += nvme.o
diff --git a/cmd/rtc.c b/cmd/rtc.c
new file mode 100644
index 00..36b01735f0
--- /dev/null
+++ b/cmd/rtc.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MAX_RTC_BYTES 32
+
+static int do_rtc_read(struct udevice *dev, int argc, char * const argv[])
+{
+ u8 buf[MAX_RTC_BYTES];
+ int reg, len, ret, r;
+
+ if (argc < 2 || argc > 3)
+ return CMD_RET_USAGE;
+
+ reg = simple_strtoul(argv[0], NULL, 16);
+ len = simple_strtoul(argv[1], NULL, 16);
+
+ if (argc == 3) {
+ u8 *addr;
+
+ addr = map_sysmem(simple_strtoul(argv[2], NULL, 16), len);
+ ret = dm_rtc_read(dev, reg, addr, len);
+ unmap_sysmem(addr);
+ if (ret) {
+ printf("dm_rtc_read() failed: %d\n", ret);
+ return CMD_RET_FAILURE;
+ }
+ return CMD_RET_SUCCESS;
+ }
+
+ while (len) {
+ r = min_t(int, len, sizeof(buf));
+ ret = dm_rtc_read(dev, reg, buf, r);
+ if (ret) {
+ printf("dm_rtc_read() failed: %d\n", ret);
+ return CMD_RET_FAILURE;
+ }
+ print_buffer(reg, buf, 1, r, 0);
+ len -= r;
+ reg += r;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_rtc_write(struct udevice *dev, int argc, char * const argv[])
+{
+ u8 buf[MAX_RTC_BYTES];
+ int reg, len, ret;
+ const char *s;
+ int slen;
+
+ if (argc < 2 || argc > 3)
+ return CMD_RET_USAGE;
+
+ reg = simple_strtoul(argv[0], NULL, 16);
+
+ if (argc == 3) {
+ u8 *addr;
+
+ len = simple_strtoul(argv[1], NULL, 16);
+ addr = map_sysmem(simple_strtoul(argv[2], NULL, 16), len);
+ ret = dm_rtc_write(dev, reg, addr, len);
+ unmap_sysmem(addr);
+ if (ret) {
+ printf("dm_rtc_write() failed: %d\n", ret);
+ return CMD_RET_FAILURE;
+ }
+ return CMD_RET_SUCCESS;
+ }
+
+ s = argv[1];
+ slen = strlen(s);
+
+ if (slen % 2) {
+ printf("invalid hex string\n");
+ return CMD_RET_FAILURE;
+ }
+
+ while (slen) {
+ len = min_t(int, slen / 2, sizeof(buf));
+ if (hex2bin(buf, s, len)) {
+ printf("invalid hex string\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = dm_rtc_write(dev, reg, buf, len);
+ if (ret) {
+ printf("dm_rtc_write() failed: %d\n", ret);
+ return CMD_RET_FAILURE;
+ }
+ s += 2 * len;
+ slen -= 2 * len;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+int do_rtc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ static int curr_rtc = 0;
+ struct udevice *dev;
+ int ret, idx;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ argc--;
+ argv++;
+
+ if (!strcmp(argv[0], "list")) {
+ struct uclass *uc;
+ idx = 0;
+
+ uclass_id_foreach_dev(UCLASS_RTC, dev, uc) {
+ printf("RTC #%d - %s\n", idx++, dev->name);
+ }
+ if (!idx) {
+ printf("*** no RTC devices available ***\n");
+ return CMD_RET_FAILURE;
+ }
+
[PATCH v3 03/10] rtc: fall back to ->{read, write} if ->{read, write}8 are not provided
Similar to how the dm_rtc_{read,write} functions fall back to using
the {read,write}8 methods, do the opposite in the rtc_{read,write}8
functions.
This way, each driver only needs to provide either ->read8 or ->read
to make both rtc_read8() and dm_rtc_read() work - without this, a
driver that provides ->read() would most likely just duplicate the
logic here for implementing a ->read8() method in term of its ->read()
method. The same remarks of course apply to the write case.
Reviewed-by: Simon Glass
Signed-off-by: Rasmus Villemoes
---
drivers/rtc/rtc-uclass.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c
index a8714156c6..2a4c2331cc 100644
--- a/drivers/rtc/rtc-uclass.c
+++ b/drivers/rtc/rtc-uclass.c
@@ -81,9 +81,17 @@ int rtc_read8(struct udevice *dev, unsigned int reg)
struct rtc_ops *ops = rtc_get_ops(dev);
assert(ops);
- if (!ops->read8)
- return -ENOSYS;
- return ops->read8(dev, reg);
+ if (ops->read8)
+ return ops->read8(dev, reg);
+ if (ops->read) {
+ u8 buf[1];
+ int ret = ops->read(dev, reg, buf, 1);
+
+ if (ret < 0)
+ return ret;
+ return buf[0];
+ }
+ return -ENOSYS;
}
int rtc_write8(struct udevice *dev, unsigned int reg, int val)
@@ -91,9 +99,13 @@ int rtc_write8(struct udevice *dev, unsigned int reg, int
val)
struct rtc_ops *ops = rtc_get_ops(dev);
assert(ops);
- if (!ops->write8)
- return -ENOSYS;
- return ops->write8(dev, reg, val);
+ if (ops->write8)
+ return ops->write8(dev, reg, val);
+ if (ops->write) {
+ u8 buf[1] = { val };
+ return ops->write(dev, reg, buf, 1);
+ }
+ return -ENOSYS;
}
int rtc_read16(struct udevice *dev, unsigned int reg, u16 *valuep)
--
2.23.0
[PATCH v3 01/10] rtc: add dm_rtc_read helper and ->read method
Some users may want to read multiple consecutive 8-bit
registers. Instead of each caller having to implement the loop,
provide a dm_rtc_read() helper. Also, allow a driver to provide a
->read method, which can be more efficient than reading one register
at a time.
Reviewed-by: Simon Glass
Signed-off-by: Rasmus Villemoes
---
drivers/rtc/rtc-uclass.c | 18 ++
include/rtc.h| 23 +++
2 files changed, 41 insertions(+)
diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c
index 926cca234e..92cc8c5664 100644
--- a/drivers/rtc/rtc-uclass.c
+++ b/drivers/rtc/rtc-uclass.c
@@ -40,6 +40,24 @@ int dm_rtc_reset(struct udevice *dev)
return ops->reset(dev);
}
+int dm_rtc_read(struct udevice *dev, unsigned int reg, u8 *buf, unsigned int
len)
+{
+ struct rtc_ops *ops = rtc_get_ops(dev);
+
+ assert(ops);
+ if (ops->read)
+ return ops->read(dev, reg, buf, len);
+ if (!ops->read8)
+ return -ENOSYS;
+ while (len--) {
+ int ret = ops->read8(dev, reg++);
+ if (ret < 0)
+ return ret;
+ *buf++ = ret;
+ }
+ return 0;
+}
+
int rtc_read8(struct udevice *dev, unsigned int reg)
{
struct rtc_ops *ops = rtc_get_ops(dev);
diff --git a/include/rtc.h b/include/rtc.h
index 8aabfc1162..6887fe4d42 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -55,6 +55,18 @@ struct rtc_ops {
*/
int (*reset)(struct udevice *dev);
+ /**
+* read() - Read multiple 8-bit registers
+*
+* @dev:Device to read from
+* @reg:First register to read
+* @buf:Output buffer
+* @len:Number of registers to read
+* @return 0 if OK, -ve on error
+*/
+ int (*read)(struct udevice *dev, unsigned int reg,
+ u8 *buf, unsigned int len);
+
/**
* read8() - Read an 8-bit register
*
@@ -109,6 +121,17 @@ int dm_rtc_set(struct udevice *dev, struct rtc_time *time);
*/
int dm_rtc_reset(struct udevice *dev);
+/**
+ * dm_rtc_read() - Read multiple 8-bit registers
+ *
+ * @dev: Device to read from
+ * @reg: First register to read
+ * @buf: Output buffer
+ * @len: Number of registers to read
+ * @return 0 if OK, -ve on error
+ */
+int dm_rtc_read(struct udevice *dev, unsigned int reg, u8 *buf, unsigned int
len);
+
/**
* rtc_read8() - Read an 8-bit register
*
--
2.23.0
[PATCH v3 00/10] new rtc methods, rtc command, and tests
I need access to registers other than just the timekeeping ones of the
pcf2127, so I wanted to implement ->read8 and ->write8. But for
testing these it appeared there was no convenient way to invoke those
from the shell, so I also ended up adding such a command.
Also, it seemed more natural to provide array variants that can read
or write several registers at once, so rtc_ops is expanded a bit.
Simon, I've taken the liberty of keeping your R-Bs despite the first
bullet below, yell if that's inappropriate.
Changes in v3:
- Call the functions dm_rtc_read/dm_rtc_write rather than just
rtc_read/rtc_write, since the latter names are used for local
helpers by a number of drivers. That also matches the existing
dm_rtc_set/dm_rtc_get (though then not the existing
rtc_read{8,16,32}).
- Update the rtc command (patch 6) as per Simon's feedback (parse
input as hex, avoid overlong lines, use print_buffer()).
- Update the tests (patches 9 and 10) according to these changes.
Changes in v2:
- Use simply "read" and "write" instead of "read8_array",
"write8_array", both for functions and methods, as suggested by
Simon.
- The rtc command's interface has been simplified a bit (no separate
read/readm; the number of arguments determines whether the user
wants the result on the console or to a memory address)
- Add tests, both of rtc_{read,write}() and of the shell command,
fixing a few things I stumbled on.
Rasmus Villemoes (10):
rtc: add dm_rtc_read helper and ->read method
rtc: add dm_rtc_write() helper
rtc: fall back to ->{read,write} if ->{read,write}8 are not provided
rtc: pcf2127: provide ->read method
rtc: pcf2127: provide ->write method
rtc: add rtc command
rtc: sandbox-rtc: fix set method
rtc: i2c_rtc_emul: catch any write to the "reset" register
test: dm: rtc: add test of dm_rtc_read, dm_rtc_write
test: dm: rtc: add tests of rtc shell command
arch/sandbox/include/asm/rtc.h | 5 +
cmd/Kconfig| 6 ++
cmd/Makefile | 1 +
cmd/rtc.c | 167 +
drivers/rtc/i2c_rtc_emul.c | 3 +-
drivers/rtc/pcf2127.c | 13 ++-
drivers/rtc/rtc-uclass.c | 56 ++-
drivers/rtc/sandbox_rtc.c | 65 +
include/rtc.h | 47 ++
test/dm/rtc.c | 118 ++-
10 files changed, 431 insertions(+), 50 deletions(-)
create mode 100644 cmd/rtc.c
--
2.23.0
Re: [PATCHv4 3/3] spi: Convert CONFIG_DM_SPI* to CONFIG_$(SPL_TPL_)DM_SPI*
On Wed, Jun 3, 2020 at 12:31 AM Tom Rini wrote:
>
> On Wed, Jun 03, 2020 at 12:10:30AM +0530, Jagan Teki wrote:
> > On Tue, Jun 2, 2020 at 11:57 PM Tom Rini wrote:
> > >
> > > On Tue, Jun 02, 2020 at 06:59:21PM +0530, Jagan Teki wrote:
> > > > On Tue, Jun 2, 2020 at 6:47 PM Zhiqiang Hou
> > > > wrote:
> > > > >
> > > > > From: Lukasz Majewski
> > > > >
> > > > > This change allows more fine tuning of driver model based SPI support
> > > > > in
> > > > > SPL and TPL. It is now possible to explicitly enable/disable the
> > > > > DM_SPI
> > > > > support in SPL and TPL via Kconfig option.
> > > > >
> > > > > Before this change it was necessary to use:
> > > > > /* SPI Flash Configs */
> > > > > #if defined(CONFIG_SPL_BUILD)
> > > > > #undef CONFIG_DM_SPI
> > > > > #undef CONFIG_DM_SPI_FLASH
> > > > > #undef CONFIG_SPI_FLASH_MTD
> > > > > #endif
> > > > >
> > > > > in the ./include/configs/.h, which is error prone and shall be
> > > > > avoided when we strive to switch to Kconfig.
> > > > >
> > > > > The goal of this patch:
> > > > >
> > > > > Provide distinction for DM_SPI support in both U-Boot proper and SPL
> > > > > (TPL).
> > > > > Valid use case is when U-Boot proper wants to use DM_SPI, but SPL must
> > > > > still support non DM driver.
> > > > >
> > > > > Another use case is the conversion of non DM/DTS SPI driver to support
> > > > > DM/DTS. When such driver needs to work in both SPL and U-Boot proper,
> > > > > the
> > > > > distinction is needed in Kconfig (also if SPL version of the driver
> > > > > supports OF_PLATDATA).
> > > > >
> > > > > In the end of the day one would have to support following use cases
> > > > > (in
> > > > > single driver file - e.g. mxs_spi.c):
> > > > >
> > > > > - U-Boot proper driver supporting DT/DTS
> > > > > - U-Boot proper driver without DT/DTS support (deprecated)
> > > > > - SPL driver without DT/DTS support
> > > > > - SPL (and TPL) driver with DT/DTS (when the SoC has enough resources
> > > > > to
> > > > > run full blown DT/DTS)
> > > > > - SPL driver with DT/DTS and SPL_OF_PLATDATA (when one have
> > > > > constrained
> > > > > environment with no fitImage and OF_LIBFDT support).
> > > > >
> > > > > Some boards do require SPI support (with DM) in SPL (TPL) and some
> > > > > only
> > > > > have DM_SPI{_FLASH} defined to allow compiling SPL.
> > > > >
> > > > > This patch converts #ifdef CONFIG_DM_SPI* to #if
> > > > > CONFIG_IS_ENABLED(DM_SPI)
> > > > > and provides corresponding defines in Kconfig.
> > > > >
> > > > > Signed-off-by: Lukasz Majewski
> > > > > Tested-by: Adam Ford #da850-evm
> > > > > Signed-off-by: Hou Zhiqiang
> > > > > ---
> > > > > V4:
> > > > > - Rebase the patch and remove SPL_DM_SPI from target ls1046 boards.
> > > > >
> > > > > arch/arm/Kconfig| 11 +++
> > > > > board/l+g/vinco/vinco.c | 4 ++--
> > > > > cmd/sf.c| 4 ++--
> > > > > cmd/spi.c | 6 +++---
> > > > > common/spl/Kconfig | 20
> > > > > configs/am57xx_evm_defconfig| 2 ++
> > > > > configs/am57xx_hs_evm_defconfig | 2 ++
> > > > > configs/am57xx_hs_evm_usb_defconfig | 2 ++
> > > > > configs/axm_defconfig | 2 ++
> > > > > configs/chromebook_link64_defconfig | 2 ++
> > > > > configs/chromebook_samus_tpl_defconfig | 4
> > > > > configs/dra7xx_evm_defconfig| 2 ++
> > > > > configs/dra7xx_hs_evm_defconfig | 2 ++
> > > > > configs/dra7xx_hs_evm_usb_defconfig | 2 ++
> > > > > configs/j721e_evm_a72_defconfig | 2 ++
> > > > > configs/j721e_evm_r5_defconfig | 2 ++
> > > > > configs/ls1021aiot_qspi_defconfig | 2 ++
> > > > > configs/ls1021aiot_sdcard_defconfig | 2 ++
> > > > > configs/ls1021aqds_qspi_defconfig | 1 +
> > > > > configs/ls1021aqds_sdcard_qspi_defconfig| 1 +
> > > > > configs/ls1021atwr_qspi_defconfig | 1 +
> > > > > configs/sama5d2_xplained_spiflash_defconfig | 2 ++
> > > > > configs/sama5d3xek_spiflash_defconfig | 7 ---
> > > > > configs/sama5d4_xplained_spiflash_defconfig | 2 ++
> > > > > configs/sama5d4ek_spiflash_defconfig| 2 ++
> > > > > configs/stm32mp15_basic_defconfig | 2 ++
> > > > > configs/taurus_defconfig| 2 ++
> > > > > drivers/mtd/spi/Makefile| 4 ++--
> > > > > drivers/mtd/spi/sf_probe.c | 2 +-
> > > > > drivers/net/fm/fm.c | 4 ++--
> > > > > drivers/spi/Makefile| 2 +-
> > > > > drivers/spi/atmel_spi.c | 4 ++--
> > > > > drivers/spi/davinci_spi.c | 6 +++---
> > > > > drivers/spi/fsl_dspi.c | 5 +++--
> > > > >
Re: [PATCH] env: Add option to only ever append environment
On 6/2/20 7:36 PM, Tom Rini wrote: [...] >> One will append the environment, the other will override it (if you have >> multiple envs enabled). > > So it sounds like it wouldn't be valid to have this option differ > between SPL and main U-Boot? Consider the case where you have default env in SPL, and multiple envs in U-Boot proper. >>> >>> Yes, today you can end up with cases where you build something that doesn't >>> work as intended (likely something around falcon boot and/or boot count >>> limit in env). Which is what I'm getting at here. Is there some >>> cases where it would make any sense to enable this option in full U-Boot >>> but disable it in SPL? >> >> Yes, like my current use case, where I want to configure the SPL >> differently than U-Boot itself. SPL doesn't even have environment >> support enabled, but it might be needed later. > > Sorry I wasn't clear enough. Does it make sense (when? how?) to have > environment in SPL but mismatch this feature? If you have only one env source in SPL and multiple in U-Boot for example. But this is besides the point, I want to be able to configure my env handling whichever I need it to without working around problems like the ones below. >> And also, I don't want to end up in the same problem we currently have >> e.g. with USB gadget, where I have to manually #ifdef CONFIG_SPL_BUILD >> #undef CONFIG_ options in the board config file. > > Yes, don't do that, I've had to fix a few of those of late in catching > converted but still in config header options. This is the result of not having a dedicated SPL/TPL config options though.
Re: [PATCHv4 3/3] spi: Convert CONFIG_DM_SPI* to CONFIG_$(SPL_TPL_)DM_SPI*
On Wed, Jun 03, 2020 at 12:10:30AM +0530, Jagan Teki wrote:
> On Tue, Jun 2, 2020 at 11:57 PM Tom Rini wrote:
> >
> > On Tue, Jun 02, 2020 at 06:59:21PM +0530, Jagan Teki wrote:
> > > On Tue, Jun 2, 2020 at 6:47 PM Zhiqiang Hou wrote:
> > > >
> > > > From: Lukasz Majewski
> > > >
> > > > This change allows more fine tuning of driver model based SPI support in
> > > > SPL and TPL. It is now possible to explicitly enable/disable the DM_SPI
> > > > support in SPL and TPL via Kconfig option.
> > > >
> > > > Before this change it was necessary to use:
> > > > /* SPI Flash Configs */
> > > > #if defined(CONFIG_SPL_BUILD)
> > > > #undef CONFIG_DM_SPI
> > > > #undef CONFIG_DM_SPI_FLASH
> > > > #undef CONFIG_SPI_FLASH_MTD
> > > > #endif
> > > >
> > > > in the ./include/configs/.h, which is error prone and shall be
> > > > avoided when we strive to switch to Kconfig.
> > > >
> > > > The goal of this patch:
> > > >
> > > > Provide distinction for DM_SPI support in both U-Boot proper and SPL
> > > > (TPL).
> > > > Valid use case is when U-Boot proper wants to use DM_SPI, but SPL must
> > > > still support non DM driver.
> > > >
> > > > Another use case is the conversion of non DM/DTS SPI driver to support
> > > > DM/DTS. When such driver needs to work in both SPL and U-Boot proper,
> > > > the
> > > > distinction is needed in Kconfig (also if SPL version of the driver
> > > > supports OF_PLATDATA).
> > > >
> > > > In the end of the day one would have to support following use cases (in
> > > > single driver file - e.g. mxs_spi.c):
> > > >
> > > > - U-Boot proper driver supporting DT/DTS
> > > > - U-Boot proper driver without DT/DTS support (deprecated)
> > > > - SPL driver without DT/DTS support
> > > > - SPL (and TPL) driver with DT/DTS (when the SoC has enough resources to
> > > > run full blown DT/DTS)
> > > > - SPL driver with DT/DTS and SPL_OF_PLATDATA (when one have constrained
> > > > environment with no fitImage and OF_LIBFDT support).
> > > >
> > > > Some boards do require SPI support (with DM) in SPL (TPL) and some only
> > > > have DM_SPI{_FLASH} defined to allow compiling SPL.
> > > >
> > > > This patch converts #ifdef CONFIG_DM_SPI* to #if
> > > > CONFIG_IS_ENABLED(DM_SPI)
> > > > and provides corresponding defines in Kconfig.
> > > >
> > > > Signed-off-by: Lukasz Majewski
> > > > Tested-by: Adam Ford #da850-evm
> > > > Signed-off-by: Hou Zhiqiang
> > > > ---
> > > > V4:
> > > > - Rebase the patch and remove SPL_DM_SPI from target ls1046 boards.
> > > >
> > > > arch/arm/Kconfig| 11 +++
> > > > board/l+g/vinco/vinco.c | 4 ++--
> > > > cmd/sf.c| 4 ++--
> > > > cmd/spi.c | 6 +++---
> > > > common/spl/Kconfig | 20
> > > > configs/am57xx_evm_defconfig| 2 ++
> > > > configs/am57xx_hs_evm_defconfig | 2 ++
> > > > configs/am57xx_hs_evm_usb_defconfig | 2 ++
> > > > configs/axm_defconfig | 2 ++
> > > > configs/chromebook_link64_defconfig | 2 ++
> > > > configs/chromebook_samus_tpl_defconfig | 4
> > > > configs/dra7xx_evm_defconfig| 2 ++
> > > > configs/dra7xx_hs_evm_defconfig | 2 ++
> > > > configs/dra7xx_hs_evm_usb_defconfig | 2 ++
> > > > configs/j721e_evm_a72_defconfig | 2 ++
> > > > configs/j721e_evm_r5_defconfig | 2 ++
> > > > configs/ls1021aiot_qspi_defconfig | 2 ++
> > > > configs/ls1021aiot_sdcard_defconfig | 2 ++
> > > > configs/ls1021aqds_qspi_defconfig | 1 +
> > > > configs/ls1021aqds_sdcard_qspi_defconfig| 1 +
> > > > configs/ls1021atwr_qspi_defconfig | 1 +
> > > > configs/sama5d2_xplained_spiflash_defconfig | 2 ++
> > > > configs/sama5d3xek_spiflash_defconfig | 7 ---
> > > > configs/sama5d4_xplained_spiflash_defconfig | 2 ++
> > > > configs/sama5d4ek_spiflash_defconfig| 2 ++
> > > > configs/stm32mp15_basic_defconfig | 2 ++
> > > > configs/taurus_defconfig| 2 ++
> > > > drivers/mtd/spi/Makefile| 4 ++--
> > > > drivers/mtd/spi/sf_probe.c | 2 +-
> > > > drivers/net/fm/fm.c | 4 ++--
> > > > drivers/spi/Makefile| 2 +-
> > > > drivers/spi/atmel_spi.c | 4 ++--
> > > > drivers/spi/davinci_spi.c | 6 +++---
> > > > drivers/spi/fsl_dspi.c | 5 +++--
> > > > drivers/spi/kirkwood_spi.c | 2 +-
> > > > drivers/spi/mxc_spi.c | 6 +++---
> > > > drivers/spi/omap3_spi.c | 4 ++--
> > >
> > > nondm code on most of the driver will remove in the next version, So I
> > > didn't see any usecase of this conversion here.
> >
> > I
Re: [PATCH v13 00/19] RISC-V SiFive FU540 support SPL
Hi Rick, On Fri, May 29, 2020 at 11:34 AM Pragnesh Patel wrote: > > This series add support for SPL to FU540. U-Boot SPL can boot from > L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and > U-Boot proper from MMC devices. > > This series is also available here [1] for testing > [1] https://github.com/pragnesh26992/u-boot/tree/spl > > How to test this patch: > 1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y > 2) export OPENSBI= opensbi/build/platform/generic/firmware/fw_dynamic.bin> > 3) Change to u-boot-dir > 4) make sifive_fu540_defconfig > 5) make all > 6) Format the SD card (make sure the disk has GPT, otherwise use gdisk to > switch) > > # sudo sgdisk --clear \ > > --set-alignment=2 \ > > --new=1:34:2081 --change-name=1:loader1 > --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \ > > --new=2:2082:10273 --change-name=2:loader2 > --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \ > > --new=3:10274: --change-name=3:rootfs > --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \ > > /dev/sda > > 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34 > 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082 > > Changes in v13: > - Add a new patch to set the ethernet clock rate > (riscv: sifive: dts: fu540: set ethernet clock rate) > > Changes in v12: > - Rebase on mainline U-Boot > Added necessary include files which are not part of common header now > Remove unnecessary include files > > drivers/misc/sifive-otp.c > +#include > +#include > > board/sifive/fu540/fu540.c > -#include > +#include > > board/sifive/fu540/spl.c > +#include > +#include > +#include > > drivers/ram/sifive/fu540_ddr.c > +#include > > arch/riscv/cpu/fu540/cpu.c > -#include > +#include > > arch/riscv/cpu/fu540/spl.c > -#include > +#include > > board/sifive/fu540/spl.c > -#include > +#include > +#include > +#include > > - Update commit description for Release ethernet clock reset > - Update OpenSBI building section in "doc/board/sifive/fu540.rst" > > Changes in v11: > - Remove TPL related code and OF_PLATDATA from FU540 > DDR driver (drivers/ram/sifive/fu540_ddr.c) > - Update FU540 doc (doc/board/sifive/fu540.rst) > Remove unnecessary print > > Changes in v10: > - Update commit description for ethernet clock reset > (https://patchwork.ozlabs.org/patch/1289003) > - Update commit description for ddr clock initialization > (https://patchwork.ozlabs.org/patch/1289000) > > Changes in v9: > - Remove cache related patches from this series > sifive: dts: fu540: Enable L2 Cache in U-Boot > (https://patchwork.ozlabs.org/patch/1286705) > riscv: sifive: fu540: enable all cache ways from U-Boot proper > (https://patchwork.ozlabs.org/patch/1286706) > - Rename SiFive DDR driver from sdram_fu540.c to fu540_ddr.c > and also do some typo correction in driver > - Remove CONFIG_SPL_BUILD for __prci_ddr_release_reset() > - Release ethernet clock reset instead of ethernet clock > initialization > (https://patchwork.ozlabs.org/patch/1286697) > - Squash fu540 cpu patches > (https://patchwork.ozlabs.org/patch/1286699) > (https://patchwork.ozlabs.org/patch/1286700) > - Use spl_boot_device() instead of board_boot_order() > > Changes in v8: > - Remove SPL_CRC7_SUPPORT Kconfig option and compile > crc7.o when CONFIG_MMC_SPI selected > - Add "TODO" in drivers/ram/sifive/sdram_fu540.c > - Remove unnecessary TODO from drivers/clk/sifive/fu540-prci.c > - Make fu540-hifive-unleashed-a00-sdram-ddr4.dtsi file dual-licensed > - Add 2 new patches > sifive: fu540: Add sample SD gpt partition layout > (https://patchwork.ozlabs.org/patch/1092) > sifive: fu540: Add U-Boot proper sector start > (https://patchwork.ozlabs.org/patch/1093) > - Remove patch > riscv: Enable cpu clock if it is present > (https://patchwork.ozlabs.org/patch/1281573) > - Update doc/board/sifive/fu540.rst for PLATFORM=generic > > Changes in v7: > - Standardize SD gpt partition layout > - Add delay for SiFive OTP driver > - Use DM way for corepll and ddrpll > - Add new cpu fu540 (arch/riscv/cpu/fu540) > - Update document for FU540 (doc/board/sifive/fu540.rst) > > Changes in v6: > - Typo Correction > - Make fu540-c000-u-boot.dtsi and hifive-unleashed-a00-u-boot.dtsi > Dual Licensed > - Sync Hifive unleashed dts from Linux > - Add arch/riscv/fu540 for FU540 specific code > > Changes in v5: > - Return read/write bytes for sifive_otp_read and sifive_otp_write > - Correct Palmer's email address > > Changes in v4: > - Split misc DM driver patch into multiple patches > - Added new SPL_CRC7_SUPPORT Kconfig option > - Added DM driver for DDR > - Added clk_enable and clk_disable ops in SiFive PRCI driver > - Added early clock initialization for SPL in SiFive PRCI driver > - Added early clock initialization for SPL in SiFive PRCI driver > - Added SPL
Pull request: u-boot-spi/master
Hi Tom, Please pull this PR. Summay: - Toshiba spinand (Yoshio) - SPI/SPI Flash cleanup (Jagan) - Remove SH SPI (Jagan) Travis-CI: https://travis-ci.org/github/openedev/u-boot-amarula/builds/693428912 The following changes since commit ab80137cc436e977ef91a154372ae5aeae3f4fb0: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell (2020-05-27 10:56:25 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-spi master for you to fetch changes up to db2e6d0ad7860653fcec63ded4211d74b83c2e09: doc: driver-model: Update SPI migration status (2020-06-01 19:10:37 +0530) Jagan Teki (11): spi Drop spi_init() spi: Kconfig: Drop redundant CF_SPI definition spi: Kconfig: Move MSCC_BB_SPI, FSL_QSPI into DM_SPI spi: Zap sh_spi driver mtd: spi: Use CONFIG_IS_ENABLED to prevent ifdef sf: Drop spl_flash_get_sw_write_prot mtd: spi: Call sst_write in _write ops cmd: sf Drop reassignment of new into flash env: sf: Free the old env_flash mtd: sf: Drop plat from sf_probe doc: driver-model: Update SPI migration status Yoshio Furuyama (2): mtd: spinand: toshiba: Rename function name to change suffix and prefix (8Gbit) mtd: spinand: toshiba: Support for new Kioxia Serial NAND cmd/sf.c | 3 - doc/driver-model/migration.rst | 2 - drivers/mtd/nand/spi/toshiba.c | 167 --- drivers/mtd/spi/sf-uclass.c| 9 -- drivers/mtd/spi/sf_internal.h | 14 ++- drivers/mtd/spi/sf_probe.c | 27 ++--- drivers/mtd/spi/spi-nor-core.c | 24 ++-- drivers/mtd/spi/spi-nor-tiny.c | 6 - drivers/spi/Kconfig| 43 +++ drivers/spi/Makefile | 1 - drivers/spi/cf_spi.c | 4 - drivers/spi/kirkwood_spi.c | 4 - drivers/spi/sh_spi.c | 250 - drivers/spi/sh_spi.h | 67 --- env/sf.c | 13 +-- include/spi_flash.h| 27 - test/dm/sf.c | 10 +- 17 files changed, 174 insertions(+), 497 deletions(-) delete mode 100644 drivers/spi/sh_spi.c delete mode 100644 drivers/spi/sh_spi.h
Re: [PATCH]: cmd: part: add part block command
On Tue, Jun 02, 2020 at 11:36:48AM -0700, razvan becheriu wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA256
>
> here is the implementation of the functions:
>
> # function ota_conv_sizes
> # Convert a bytes size to a block size
> # input bytesize : size in bytes to convert
> # input blksize : size of a block in bytes
> # output num_blk : converted size in blocks
> setenv ota_conv_sizes 'setexpr num_blk $bytesize / $blksize ; setexpr
> mod_blk $bytesize % $blksize ; if itest $mod_blk > 0 ; then setexpr num_blk
> $num_blk + 1; fi;'
>
> # function ota_mmc_write
> # Write a memory buffer to mmc drive
> # input floadaddr: address of buffer to write
> # input u_part_start : block start in mmc
> # input num_blk : number of block to write
> setenv ota_mmc_write 'if itest $ota_verbose == 1 ; then echo "mmc write
> ${floadaddr} ${u_part_start} ${num_blk};"; fi; mmc write $floadaddr
> $u_part_start $num_blk; ret=$?; if itest $ret != 0 ; then setenv
> ota_abort_reason "mmc write ${floadaddr} ${u_part_start} ${num_blk}
> failed"; setenv ota_abort 1; fi;'
>
> the old u-boot version supported 'part info mmc 0:${u_part_num}
> u_part_start u_part_sz u_part_blksz;' to get the block size.
Old upstream U-Boot?
--
Tom
signature.asc
Description: PGP signature
Pull request: u-boot-sunxi/master
Hi Tom, Please pull this PR. Summary: - H6 emac support - USB PHY H6 logic alignment Travis-CI: https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi The following changes since commit d09b832cd8ccb7e37e2b188394df5a73d7074c3b: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh (2020-05-30 20:11:38 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi master for you to fetch changes up to 1e7d00ae262e124eaf97d9e3ce4fb25739e4f5d6: sunxi: H6: Enable Ethernet on the Pine H64 (2020-06-01 22:38:53 +0530) Roman Stratiienko (1): phy: sun4i-usb: Align H6 initialization logic with the kernel Samuel Holland (4): sunxi: Silence warning about non-static inline function net: sun8i_emac: Use consistent clock bitfield definitions net: sun8i_emac: Add support for the H6 variant sunxi: H6: Enable Ethernet on the Pine H64 arch/arm/mach-sunxi/dram_sunxi_dw.c | 18 +- configs/pine_h64_defconfig| 1 + drivers/net/sun8i_emac.c | 20 +--- drivers/phy/allwinner/phy-sun4i-usb.c | 6 -- 4 files changed, 27 insertions(+), 18 deletions(-)
Re: [PATCHv4 3/3] spi: Convert CONFIG_DM_SPI* to CONFIG_$(SPL_TPL_)DM_SPI*
On Tue, Jun 2, 2020 at 11:57 PM Tom Rini wrote:
>
> On Tue, Jun 02, 2020 at 06:59:21PM +0530, Jagan Teki wrote:
> > On Tue, Jun 2, 2020 at 6:47 PM Zhiqiang Hou wrote:
> > >
> > > From: Lukasz Majewski
> > >
> > > This change allows more fine tuning of driver model based SPI support in
> > > SPL and TPL. It is now possible to explicitly enable/disable the DM_SPI
> > > support in SPL and TPL via Kconfig option.
> > >
> > > Before this change it was necessary to use:
> > > /* SPI Flash Configs */
> > > #if defined(CONFIG_SPL_BUILD)
> > > #undef CONFIG_DM_SPI
> > > #undef CONFIG_DM_SPI_FLASH
> > > #undef CONFIG_SPI_FLASH_MTD
> > > #endif
> > >
> > > in the ./include/configs/.h, which is error prone and shall be
> > > avoided when we strive to switch to Kconfig.
> > >
> > > The goal of this patch:
> > >
> > > Provide distinction for DM_SPI support in both U-Boot proper and SPL
> > > (TPL).
> > > Valid use case is when U-Boot proper wants to use DM_SPI, but SPL must
> > > still support non DM driver.
> > >
> > > Another use case is the conversion of non DM/DTS SPI driver to support
> > > DM/DTS. When such driver needs to work in both SPL and U-Boot proper, the
> > > distinction is needed in Kconfig (also if SPL version of the driver
> > > supports OF_PLATDATA).
> > >
> > > In the end of the day one would have to support following use cases (in
> > > single driver file - e.g. mxs_spi.c):
> > >
> > > - U-Boot proper driver supporting DT/DTS
> > > - U-Boot proper driver without DT/DTS support (deprecated)
> > > - SPL driver without DT/DTS support
> > > - SPL (and TPL) driver with DT/DTS (when the SoC has enough resources to
> > > run full blown DT/DTS)
> > > - SPL driver with DT/DTS and SPL_OF_PLATDATA (when one have constrained
> > > environment with no fitImage and OF_LIBFDT support).
> > >
> > > Some boards do require SPI support (with DM) in SPL (TPL) and some only
> > > have DM_SPI{_FLASH} defined to allow compiling SPL.
> > >
> > > This patch converts #ifdef CONFIG_DM_SPI* to #if CONFIG_IS_ENABLED(DM_SPI)
> > > and provides corresponding defines in Kconfig.
> > >
> > > Signed-off-by: Lukasz Majewski
> > > Tested-by: Adam Ford #da850-evm
> > > Signed-off-by: Hou Zhiqiang
> > > ---
> > > V4:
> > > - Rebase the patch and remove SPL_DM_SPI from target ls1046 boards.
> > >
> > > arch/arm/Kconfig| 11 +++
> > > board/l+g/vinco/vinco.c | 4 ++--
> > > cmd/sf.c| 4 ++--
> > > cmd/spi.c | 6 +++---
> > > common/spl/Kconfig | 20
> > > configs/am57xx_evm_defconfig| 2 ++
> > > configs/am57xx_hs_evm_defconfig | 2 ++
> > > configs/am57xx_hs_evm_usb_defconfig | 2 ++
> > > configs/axm_defconfig | 2 ++
> > > configs/chromebook_link64_defconfig | 2 ++
> > > configs/chromebook_samus_tpl_defconfig | 4
> > > configs/dra7xx_evm_defconfig| 2 ++
> > > configs/dra7xx_hs_evm_defconfig | 2 ++
> > > configs/dra7xx_hs_evm_usb_defconfig | 2 ++
> > > configs/j721e_evm_a72_defconfig | 2 ++
> > > configs/j721e_evm_r5_defconfig | 2 ++
> > > configs/ls1021aiot_qspi_defconfig | 2 ++
> > > configs/ls1021aiot_sdcard_defconfig | 2 ++
> > > configs/ls1021aqds_qspi_defconfig | 1 +
> > > configs/ls1021aqds_sdcard_qspi_defconfig| 1 +
> > > configs/ls1021atwr_qspi_defconfig | 1 +
> > > configs/sama5d2_xplained_spiflash_defconfig | 2 ++
> > > configs/sama5d3xek_spiflash_defconfig | 7 ---
> > > configs/sama5d4_xplained_spiflash_defconfig | 2 ++
> > > configs/sama5d4ek_spiflash_defconfig| 2 ++
> > > configs/stm32mp15_basic_defconfig | 2 ++
> > > configs/taurus_defconfig| 2 ++
> > > drivers/mtd/spi/Makefile| 4 ++--
> > > drivers/mtd/spi/sf_probe.c | 2 +-
> > > drivers/net/fm/fm.c | 4 ++--
> > > drivers/spi/Makefile| 2 +-
> > > drivers/spi/atmel_spi.c | 4 ++--
> > > drivers/spi/davinci_spi.c | 6 +++---
> > > drivers/spi/fsl_dspi.c | 5 +++--
> > > drivers/spi/kirkwood_spi.c | 2 +-
> > > drivers/spi/mxc_spi.c | 6 +++---
> > > drivers/spi/omap3_spi.c | 4 ++--
> >
> > nondm code on most of the driver will remove in the next version, So I
> > didn't see any usecase of this conversion here.
>
> I think this is still the right direction to go in. non-DM for SPL is
> allowed and this is part of the logical steps needed for moving forward
> with "now pull non-DM driver into own file for SPL" until the efforts to
> make DM smaller still are ready. So this series is on my
Re: [PATCH v2 00/10] new rtc methods, rtc command, and tests
On 20/05/2020 00.01, Rasmus Villemoes wrote: > I need access to registers other than just the timekeeping ones of the > pcf2127, so I wanted to implement ->read8 and ->write8. But for > testing these it appeared there was no convenient way to invoke those > from the shell, so I also ended up adding such a command. > > Also, it seemed more natural to provide array variants that can read > or write several registers at once, so rtc_ops is expanded a bit. > > Changes in v2: > > - Use simply "read" and "write" instead of "read8_array", > "write8_array", both for functions and methods, as suggested by > Simon. Urgh. The name rtc_read() is already used for a local helper by a number of rtc drivers (also rtc_write, for somewhat fewer drivers). So I can still call the methods ->read and ->write, but the functions will need another name. Probably dm_rtc_read/dm_rtc_write, since this is only for DM-enabled drivers anyway, and matches the existing dm_rtc_get/dm_rtc_set. Rasmus
Re: [PATCH]: cmd: part: add part block command
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
here is the implementation of the functions:
# function ota_conv_sizes
# Convert a bytes size to a block size
# input bytesize : size in bytes to convert
# input blksize : size of a block in bytes
# output num_blk : converted size in blocks
setenv ota_conv_sizes 'setexpr num_blk $bytesize / $blksize ; setexpr
mod_blk $bytesize % $blksize ; if itest $mod_blk > 0 ; then setexpr num_blk
$num_blk + 1; fi;'
# function ota_mmc_write
# Write a memory buffer to mmc drive
# input floadaddr: address of buffer to write
# input u_part_start : block start in mmc
# input num_blk : number of block to write
setenv ota_mmc_write 'if itest $ota_verbose == 1 ; then echo "mmc write
${floadaddr} ${u_part_start} ${num_blk};"; fi; mmc write $floadaddr
$u_part_start $num_blk; ret=$?; if itest $ret != 0 ; then setenv
ota_abort_reason "mmc write ${floadaddr} ${u_part_start} ${num_blk}
failed"; setenv ota_abort 1; fi;'
the old u-boot version supported 'part info mmc 0:${u_part_num}
u_part_start u_part_sz u_part_blksz;' to get the block size.
# function ota_get_partition_attributes
# Retrieve partition attribute
# input u_part_num : partition number
# output u_part_start : partition start block number
# output u_part_sz: partition size in blocks
# output u_part_blksz : partition block size in bytes
setenv ota_get_partition_attributes 'if itest $ota_verbose == 1 ; then echo
"part info mmc 0:${u_part_num} u_part_start u_part_sz u_part_blksz;"; fi;
part info mmc 0:${u_part_num} u_part_start u_part_sz u_part_blksz;ret=$?;
if itest $ret != 0 ; then setenv ota_abort_reason "part info mmc
0:${u_part_num} u_part_start u_part_sz u_part_blksz failed: ${ret}"; setenv
ota_abort 1; fi;'
the new u-boot does not, so we need an explicit command 'part block mmc 0
${u_part_lbl} u_part_blksz;'
# function ota_get_partition_attributes_alternative
# Retrieve partition attribute
# input u_part_lbl : partition label
# output u_part_start : partition start block number
# output u_part_sz: partition size in blocks
# output u_part_blksz : partition block size in bytes
setenv ota_get_partition_attributes_alternative 'if itest $ota_verbose == 1
; then echo "part start mmc 0 ${u_part_lbl} u_part_start; part size mmc 0
${u_part_lbl} u_part_sz; part block mmc 0 ${u_part_lbl} u_part_blksz;"; fi;
part start mmc 0 ${u_part_lbl} u_part_start;ret=$?; if itest $ret != 0 ;
then setenv ota_abort_reason "part start mmc 0 ${u_part_lbl} u_part_start
failed: ${ret}"; setenv ota_abort 1; fi; part size mmc 0 ${u_part_lbl}
u_part_sz;ret=$?; if itest $ret != 0 ; then setenv ota_abort_reason "part
size mmc 0 ${u_part_lbl} u_part_sz failed: ${ret}"; setenv ota_abort 1; fi;
part block mmc 0 ${u_part_lbl} u_part_blksz;ret=$?; if itest $ret != 0 ;
then setenv ota_abort_reason "part block mmc 0 ${u_part_lbl} u_part_blksz
failed: ${ret}"; setenv ota_abort 1; fi;'
On 2020-06-02 at 18:08, razvan.beche...@gmail.com wrote:
> setexpr can compute the divide/multiply part, but we still need to get
the
> partition block size somehow.
>
> I know that this is 0x200 by default, but we can not hardcode that in the
> scripts. we should read that from the partition info.
>
> On 2020-06-02 at 17:55, tr...@konsulko.com wrote:
> > On Mon, Jun 01, 2020 at 01:20:25PM +0300, razvan.beche...@gmail.com
> wrote:
> > >
> > > The Intel Edison OTA process requires a conversion of data size
> > > from bytes to number of blocks. The following functions are used:
> > >
> > > # function ota_conv_sizes
> > > # Convert a bytes size to a block size
> > > # input bytesize : size in bytes to convert
> > > # input blksize : size of a block in bytes
> > > # output num_blk : converted size in blocks
> > >
> > > # function ota_mmc_write
> > > # Write a memory buffer to mmc drive
> > > # input floadaddr: address of buffer to write
> > > # input u_part_start : block start in mmc
> > > # input num_blk : number of block to write
> > >
> > > This patch adds the cmd part sub-command 'block' which returns
> > > the partition block size in bytes.
> >
> > This is usually done with the setexpr command today, thanks!
> >
> > --
> > Tom
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Re: [PATCH 2/2] riscv: sbi: Move sbi_probe_extension() out of CONFIG_SBI_V01
On Mon, Jun 1, 2020 at 2:09 AM Bin Meng wrote:
>
> Hi Rick,
>
> On Mon, Jun 1, 2020 at 5:08 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > > > From: Bin Meng [mailto:bmeng...@gmail.com]
> > > > Sent: Wednesday, May 27, 2020 5:05 PM
> > > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> > > > Cc: Atish Patra; Bin Meng
> > > > Subject: [PATCH 2/2] riscv: sbi: Move sbi_probe_extension() out of
> > > > CONFIG_SBI_V01
> > > >
> > > > From: Bin Meng
> > > >
> > > > sbi_probe_extension() is an API defined in SBI v0.2, not v0.1.
> > > >
> > > > Fixes 7e249bc13aaf: ("riscv: Move all SMP related SBI calls to SBI_v01")
> > > > Signed-off-by: Bin Meng
> > > > ---
> > >
> > > Reviewed-by: Rick Chen
> > >
> >
> > BTW, it seem look like sbi_remote_fence_i, sbi_remote_sfence_vma and
> > sbi_remote_sfence_vma_asid
> > are all can be used no mater in SBI_V01 or SBI_V02. Because you have
> > distinguished them in sbi.h
>
> No these calls are different and not compatible between SBI_V01 and SBI_V02.
>
In addition to that, U-Boot proper enables SMP only for SBI_V01
because U-Boot doesn't need
boot all the cores if the supervisor OS & SBI provider supports SBI
v0.2 with HSM.
Starting with OpenSBI v0.7 & Linux kernel 5.7 supports both. Thus,
there is no advantage in adding
redundant code in a generic path that is never going to be used.
Any SBI provider that only supports SBI v0.1, the user can fall back
to SBI_V01 config.
> See commit 7e249bc13aaf: ("riscv: Move all SMP related SBI calls to SBI_v01")
>
> Regards,
> Bin
--
Regards,
Atish
Re: [PATCH]: cmd: part: add part block command
On Tue, Jun 02, 2020 at 11:08:19AM -0700, razvan becheriu wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA256 > > setexpr can compute the divide/multiply part, but we still need to get the > partition block size somehow. > > I know that this is 0x200 by default, but we can not hardcode that in the > scripts. we should read that from the partition info. So there's plenty of examples today of hard-coding that value. Are you worried about a potential future change or an exists today problem you can't otherwise determine the hardware revision of at run-time? Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCHv4 3/3] spi: Convert CONFIG_DM_SPI* to CONFIG_$(SPL_TPL_)DM_SPI*
On Tue, Jun 02, 2020 at 06:59:21PM +0530, Jagan Teki wrote:
> On Tue, Jun 2, 2020 at 6:47 PM Zhiqiang Hou wrote:
> >
> > From: Lukasz Majewski
> >
> > This change allows more fine tuning of driver model based SPI support in
> > SPL and TPL. It is now possible to explicitly enable/disable the DM_SPI
> > support in SPL and TPL via Kconfig option.
> >
> > Before this change it was necessary to use:
> > /* SPI Flash Configs */
> > #if defined(CONFIG_SPL_BUILD)
> > #undef CONFIG_DM_SPI
> > #undef CONFIG_DM_SPI_FLASH
> > #undef CONFIG_SPI_FLASH_MTD
> > #endif
> >
> > in the ./include/configs/.h, which is error prone and shall be
> > avoided when we strive to switch to Kconfig.
> >
> > The goal of this patch:
> >
> > Provide distinction for DM_SPI support in both U-Boot proper and SPL (TPL).
> > Valid use case is when U-Boot proper wants to use DM_SPI, but SPL must
> > still support non DM driver.
> >
> > Another use case is the conversion of non DM/DTS SPI driver to support
> > DM/DTS. When such driver needs to work in both SPL and U-Boot proper, the
> > distinction is needed in Kconfig (also if SPL version of the driver
> > supports OF_PLATDATA).
> >
> > In the end of the day one would have to support following use cases (in
> > single driver file - e.g. mxs_spi.c):
> >
> > - U-Boot proper driver supporting DT/DTS
> > - U-Boot proper driver without DT/DTS support (deprecated)
> > - SPL driver without DT/DTS support
> > - SPL (and TPL) driver with DT/DTS (when the SoC has enough resources to
> > run full blown DT/DTS)
> > - SPL driver with DT/DTS and SPL_OF_PLATDATA (when one have constrained
> > environment with no fitImage and OF_LIBFDT support).
> >
> > Some boards do require SPI support (with DM) in SPL (TPL) and some only
> > have DM_SPI{_FLASH} defined to allow compiling SPL.
> >
> > This patch converts #ifdef CONFIG_DM_SPI* to #if CONFIG_IS_ENABLED(DM_SPI)
> > and provides corresponding defines in Kconfig.
> >
> > Signed-off-by: Lukasz Majewski
> > Tested-by: Adam Ford #da850-evm
> > Signed-off-by: Hou Zhiqiang
> > ---
> > V4:
> > - Rebase the patch and remove SPL_DM_SPI from target ls1046 boards.
> >
> > arch/arm/Kconfig| 11 +++
> > board/l+g/vinco/vinco.c | 4 ++--
> > cmd/sf.c| 4 ++--
> > cmd/spi.c | 6 +++---
> > common/spl/Kconfig | 20
> > configs/am57xx_evm_defconfig| 2 ++
> > configs/am57xx_hs_evm_defconfig | 2 ++
> > configs/am57xx_hs_evm_usb_defconfig | 2 ++
> > configs/axm_defconfig | 2 ++
> > configs/chromebook_link64_defconfig | 2 ++
> > configs/chromebook_samus_tpl_defconfig | 4
> > configs/dra7xx_evm_defconfig| 2 ++
> > configs/dra7xx_hs_evm_defconfig | 2 ++
> > configs/dra7xx_hs_evm_usb_defconfig | 2 ++
> > configs/j721e_evm_a72_defconfig | 2 ++
> > configs/j721e_evm_r5_defconfig | 2 ++
> > configs/ls1021aiot_qspi_defconfig | 2 ++
> > configs/ls1021aiot_sdcard_defconfig | 2 ++
> > configs/ls1021aqds_qspi_defconfig | 1 +
> > configs/ls1021aqds_sdcard_qspi_defconfig| 1 +
> > configs/ls1021atwr_qspi_defconfig | 1 +
> > configs/sama5d2_xplained_spiflash_defconfig | 2 ++
> > configs/sama5d3xek_spiflash_defconfig | 7 ---
> > configs/sama5d4_xplained_spiflash_defconfig | 2 ++
> > configs/sama5d4ek_spiflash_defconfig| 2 ++
> > configs/stm32mp15_basic_defconfig | 2 ++
> > configs/taurus_defconfig| 2 ++
> > drivers/mtd/spi/Makefile| 4 ++--
> > drivers/mtd/spi/sf_probe.c | 2 +-
> > drivers/net/fm/fm.c | 4 ++--
> > drivers/spi/Makefile| 2 +-
> > drivers/spi/atmel_spi.c | 4 ++--
> > drivers/spi/davinci_spi.c | 6 +++---
> > drivers/spi/fsl_dspi.c | 5 +++--
> > drivers/spi/kirkwood_spi.c | 2 +-
> > drivers/spi/mxc_spi.c | 6 +++---
> > drivers/spi/omap3_spi.c | 4 ++--
>
> nondm code on most of the driver will remove in the next version, So I
> didn't see any usecase of this conversion here.
I think this is still the right direction to go in. non-DM for SPL is
allowed and this is part of the logical steps needed for moving forward
with "now pull non-DM driver into own file for SPL" until the efforts to
make DM smaller still are ready. So this series is on my list to test
and confirm doesn't change binary size on.
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH 2/2] riscv: Enable CONFIG_OF_BOARD_FIXUP by default
On Mon, Jun 1, 2020 at 11:51 PM Rick Chen wrote: > > Hi Bin > > Bin Meng 於 2020年6月2日 週二 下午2:33寫道： > > > > Hi Rick, > > > > On Tue, Jun 2, 2020 at 2:16 PM Rick Chen wrote: > > > > > > Hi Bin > > > > > > Bin Meng 於 2020年6月2日 週二 下午2:13寫道： > > > > > > > > Hi Rick, > > > > > > > > On Tue, Jun 2, 2020 at 2:04 PM Rick Chen wrote: > > > > > > > > > > Hi Bin > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > On Mon, Jun 1, 2020 at 3:36 PM Rick Chen > > > > > > wrote: > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > On Thu, May 28, 2020 at 4:17 PM Rick Chen > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > From: Bin Meng [mailto:bmeng...@gmail.com] > > > > > > > > > > Sent: Wednesday, May 20, 2020 3:40 PM > > > > > > > > > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List > > > > > > > > > > Cc: Bin Meng > > > > > > > > > > Subject: [PATCH 2/2] riscv: Enable CONFIG_OF_BOARD_FIXUP by > > > > > > > > > > default > > > > > > > > > > > > > > > > > > > > From: Bin Meng > > > > > > > > > > > > > > > > > > > > Starting from OpenSBI v0.7, the SBI firmware inserts/fixes > > > > > > > > > > up the reserved memory node for PMP protected memory > > > > > > > > > > regions. All RISC-V boards needs to copy the reserved > > > > > > > > > > memory node from the device tree provided by the firmware > > > > > > > > > > to the device tree used by U-Boot. > > > > > > > > > > > > > > > > > > > > Turn on CONFIG_OF_BOARD_FIXUP by default. > > > > > > > > > > > > > > > > > > > > Signed-off-by: Bin Meng > > > > > > > > > > --- > > > > > > > > > > > > > > > > > > > > arch/riscv/Kconfig | 3 +++ > > > > > > > > > > configs/sifive_fu540_defconfig | 1 - > > > > > > > > > > 2 files changed, 3 insertions(+), 1 deletion(-) > > > > > > > > > > > > > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index > > > > > > > > > > fb5fe5a..5176b35 100644 > > > > > > > > > > --- a/arch/riscv/Kconfig > > > > > > > > > > +++ b/arch/riscv/Kconfig > > > > > > > > > > @@ -272,4 +272,7 @@ config STACK_SIZE_SHIFT > > > > > > > > > > int > > > > > > > > > > default 14 > > > > > > > > > > > > > > > > > > > > +config OF_BOARD_FIXUP > > > > > > > > > > + default y > > > > > > > > > > > > > > > > > > I think it shall invoke by individual board, just like the > > > > > > > > > description > > > > > > > > > of riscv_fdt_copy_resv_mem_node function. > > > > > > > > > > > > > > > > I believe we should turn on this feature by default for every > > > > > > > > RISC-V > > > > > > > > board, because SBI firmware used memory must be marked as > > > > > > > > reserved > > > > > > > > otherwise OS might use it and get crashed. For boards which > > > > > > > > don't want > > > > > > > > to enable this, they can unset the option in their board > > > > > > > > defconfig > > > > > > > > files. This is to reduce some maintenance effort. > > > > > > > > > > > > > > But not all RISC-V boards need this configuration. > > > > > > > If we enable it by default, non spl configuration will run this > > > > > > > fdt > > > > > > > fix flow, but it is unnecessary. > > > > > > > > > > > > > > > > > > > Non SPL configuration also needs this, because U-Boot has to patch > > > > > > the > > > > > > final DTB that is passed to the kernel. It's a RISC-V architecture > > > > > > thing. > > > > > > > > > > But non SPL configuration will not run openSbi, why it will need this > > > > > flow ? > > > > > > > > > > > > > Which configuration is this? > > > > > > e.q: ae350_rv[32|64]_defconfig > > > > > > > It looks these 2 configs are for U-Boot M-mode. How are they supposed > > to work, if they do not work with OpenSBI? > > They work with BBL(riscv-pk). > Does BBL support /reserved-memory node add support ? If not, riscv_fdt_copy_resv_mem_node should have returned in the first check unless you added it manually for verification. > Thanks, > Rick > > > > > Regards, > > Bin -- Regards, Atish
Re: [PATCH v2 2/3] riscv: Expand the DT size before copy reserved memory node
On Thu, May 28, 2020 at 1:47 AM Bin Meng wrote:
>
> From: Bin Meng
>
> The FDT blob might not have sufficient space to hold a copy of
> reserved memory node. Expand it before the copy.
>
> Reported-by: Rick Chen
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/lib/fdt_fixup.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
> index 5f523f0..1290a64 100644
> --- a/arch/riscv/lib/fdt_fixup.c
> +++ b/arch/riscv/lib/fdt_fixup.c
> @@ -41,6 +41,12 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void
> *dst)
> return 0;
> }
>
> + err = fdt_open_into(dst, dst, fdt_totalsize(dst) + 32);
The size may be bigger than 32 bytes in future given that we may have
multiple reserved pmp regions.
How about calculating the size from the source and using that instead
of a fixed size ?
> + if (err < 0) {
> + printf("Device Tree can't be expanded to accommodate new
> node");
> + return err;
> + }
> +
> fdt_for_each_subnode(node, src, offset) {
> name = fdt_get_name(src, node, NULL);
>
> --
> 2.7.4
>
--
Regards,
Atish
Re: [PATCH 2/2] riscv: Enable CONFIG_OF_BOARD_FIXUP by default
On Mon, Jun 1, 2020 at 11:51 PM Rick Chen wrote: > > Hi Bin > > Bin Meng 於 2020年6月2日 週二 下午2:33寫道： > > > > Hi Rick, > > > > On Tue, Jun 2, 2020 at 2:16 PM Rick Chen wrote: > > > > > > Hi Bin > > > > > > Bin Meng 於 2020年6月2日 週二 下午2:13寫道： > > > > > > > > Hi Rick, > > > > > > > > On Tue, Jun 2, 2020 at 2:04 PM Rick Chen wrote: > > > > > > > > > > Hi Bin > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > On Mon, Jun 1, 2020 at 3:36 PM Rick Chen > > > > > > wrote: > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > On Thu, May 28, 2020 at 4:17 PM Rick Chen > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > From: Bin Meng [mailto:bmeng...@gmail.com] > > > > > > > > > > Sent: Wednesday, May 20, 2020 3:40 PM > > > > > > > > > > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List > > > > > > > > > > Cc: Bin Meng > > > > > > > > > > Subject: [PATCH 2/2] riscv: Enable CONFIG_OF_BOARD_FIXUP by > > > > > > > > > > default > > > > > > > > > > > > > > > > > > > > From: Bin Meng > > > > > > > > > > > > > > > > > > > > Starting from OpenSBI v0.7, the SBI firmware inserts/fixes > > > > > > > > > > up the reserved memory node for PMP protected memory > > > > > > > > > > regions. All RISC-V boards needs to copy the reserved > > > > > > > > > > memory node from the device tree provided by the firmware > > > > > > > > > > to the device tree used by U-Boot. > > > > > > > > > > > > > > > > > > > > Turn on CONFIG_OF_BOARD_FIXUP by default. > > > > > > > > > > > > > > > > > > > > Signed-off-by: Bin Meng > > > > > > > > > > --- > > > > > > > > > > > > > > > > > > > > arch/riscv/Kconfig | 3 +++ > > > > > > > > > > configs/sifive_fu540_defconfig | 1 - > > > > > > > > > > 2 files changed, 3 insertions(+), 1 deletion(-) > > > > > > > > > > > > > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index > > > > > > > > > > fb5fe5a..5176b35 100644 > > > > > > > > > > --- a/arch/riscv/Kconfig > > > > > > > > > > +++ b/arch/riscv/Kconfig > > > > > > > > > > @@ -272,4 +272,7 @@ config STACK_SIZE_SHIFT > > > > > > > > > > int > > > > > > > > > > default 14 > > > > > > > > > > > > > > > > > > > > +config OF_BOARD_FIXUP > > > > > > > > > > + default y > > > > > > > > > > > > > > > > > > I think it shall invoke by individual board, just like the > > > > > > > > > description > > > > > > > > > of riscv_fdt_copy_resv_mem_node function. > > > > > > > > > > > > > > > > I believe we should turn on this feature by default for every > > > > > > > > RISC-V > > > > > > > > board, because SBI firmware used memory must be marked as > > > > > > > > reserved > > > > > > > > otherwise OS might use it and get crashed. For boards which > > > > > > > > don't want > > > > > > > > to enable this, they can unset the option in their board > > > > > > > > defconfig > > > > > > > > files. This is to reduce some maintenance effort. > > > > > > > > > > > > > > But not all RISC-V boards need this configuration. > > > > > > > If we enable it by default, non spl configuration will run this > > > > > > > fdt > > > > > > > fix flow, but it is unnecessary. > > > > > > > > > > > > > > > > > > > Non SPL configuration also needs this, because U-Boot has to patch > > > > > > the > > > > > > final DTB that is passed to the kernel. It's a RISC-V architecture > > > > > > thing. > > > > > > > > > > But non SPL configuration will not run openSbi, why it will need this > > > > > flow ? > > > > > > > > > > > > > Which configuration is this? > > > > > > e.q: ae350_rv[32|64]_defconfig > > > > > > > It looks these 2 configs are for U-Boot M-mode. How are they supposed > > to work, if they do not work with OpenSBI? > > They work with BBL(riscv-pk). > > Thanks, > Rick > > > > > Regards, > > Bin How about enabling only if OF_SEPARATE is enabled ? We don't need a board fixup for prior stage case. -- Regards, Atish
Re: [PATCH]: cmd: part: add part block command
-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 setexpr can compute the divide/multiply part, but we still need to get the partition block size somehow. I know that this is 0x200 by default, but we can not hardcode that in the scripts. we should read that from the partition info. On 2020-06-02 at 17:55, tr...@konsulko.com wrote: > On Mon, Jun 01, 2020 at 01:20:25PM +0300, razvan.beche...@gmail.com wrote: > > > > The Intel Edison OTA process requires a conversion of data size > > from bytes to number of blocks. The following functions are used: > > > > # function ota_conv_sizes > > # Convert a bytes size to a block size > > # input bytesize : size in bytes to convert > > # input blksize : size of a block in bytes > > # output num_blk : converted size in blocks > > > > # function ota_mmc_write > > # Write a memory buffer to mmc drive > > # input floadaddr: address of buffer to write > > # input u_part_start : block start in mmc > > # input num_blk : number of block to write > > > > This patch adds the cmd part sub-command 'block' which returns > > the partition block size in bytes. > > This is usually done with the setexpr command today, thanks! > > -- > Tom -BEGIN PGP SIGNATURE- Version: FlowCrypt 7.7.7 Gmail Encryption Comment: Seamlessly send and receive encrypted email wsFcBAEBCAAGBQJe1pWTAAoJECfW4OyT2xPzMlgQAJVisTh8t9wGyC0vGmt0 B3vdRqbo2KyHILomQffFSvPxw2s3KiXSCYzL7rXe+rnSQhVAylnCoM2NQSxi 66alVw6yQzxdLSmOddQmemuH5AEpVV3XFRfG4t78upRarfDffQn2xAy0OFs4 /1jrAktvxcXvaZetwu3Idi/lzoFynqT44Nbv1xpjRJgGyTseZh9xXCB5f6rr sxQTAq5H7Ez+v2XkXtQLoJJnO51N4lBjjoXv+nbWYYBwBOLgOlQMXDNVpY4W mY4Dc71GEl2YH7tF7mpzKNZuOKUUpLlMh5FOm17QsL3XjuORIUhwUjKYKzIR kWRi/Inr4MoYH7eIlK/CCzXEMkrLSAkforcrN2kuolY229vGVuDiSUsrFawV xfsqGTLGKJmYnYXiBDNSrqOQGSk4UDLydP/EAGxyvwq4m2pVLRQlVxttfejU aD0eh1x6QLBTC2B55VlASyg8KFnobpUMJEWiMJMa3lcytbGLahqSbEax9ZF3 5rdsxWXuW6rv4zJvKzAnSt6dz3qI6vDJy3/5RoE0Zoxp9O5p7uSsTMPxpu2b bDYoJY4+Th5MNXQYb7F2WAj1G42a1J6QNM3RsTFbDULYCSLPxqa5dOhLJI+U Fv9ezGedKkAAhmeKhfFVqCX1O5UGIPrYfV5NRDRFVpmNXd4GjhRfSs0Ozfdw D0ty =Nf5n -END PGP SIGNATURE- 0x27D6E0EC93DB13F3.asc Description: application/pgp-keys
Re: [PATCH] cmd: part: Add 'block' sub-command
On Mon, Jun 01, 2020 at 01:20:26PM +0300, razvan.beche...@gmail.com wrote:
> From: Razvan Becheriu
>
> Add part block sub-command which returns block size.
>
> e.g.:
> part block mmc $mmcdev system_a system_a_index
>
> Signed-off-by: Razvan Becheriu
> ---
> cmd/part.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/cmd/part.c b/cmd/part.c
> index 5e4e45ca6d..d78d914e7a 100644
> --- a/cmd/part.c
> +++ b/cmd/part.c
> @@ -25,6 +25,7 @@
> enum cmd_part_info {
> CMD_PART_INFO_START = 0,
> CMD_PART_INFO_SIZE,
> + CMD_PART_INFO_BLOCK,
> CMD_PART_INFO_NUMBER
> };
>
> @@ -151,6 +152,9 @@ static int do_part_info(int argc, char * const argv[],
> enum cmd_part_info param)
> case CMD_PART_INFO_SIZE:
> snprintf(buf, sizeof(buf), LBAF, info.size);
> break;
> + case CMD_PART_INFO_BLOCK:
> + snprintf(buf, sizeof(buf), LBAF, info.blksz);
> + break;
> case CMD_PART_INFO_NUMBER:
> snprintf(buf, sizeof(buf), "0x%x", part);
> break;
> @@ -177,6 +181,11 @@ static int do_part_size(int argc, char * const argv[])
> return do_part_info(argc, argv, CMD_PART_INFO_SIZE);
> }
>
> +static int do_part_block(int argc, char * const argv[])
> +{
> + return do_part_info(argc, argv, CMD_PART_INFO_BLOCK);
> +}
> +
> static int do_part_number(int argc, char * const argv[])
> {
> return do_part_info(argc, argv, CMD_PART_INFO_NUMBER);
> @@ -195,6 +204,8 @@ static int do_part(cmd_tbl_t *cmdtp, int flag, int argc,
> char * const argv[])
> return do_part_start(argc - 2, argv + 2);
> else if (!strcmp(argv[1], "size"))
> return do_part_size(argc - 2, argv + 2);
> + else if (!strcmp(argv[1], "block"))
> + return do_part_block(argc - 2, argv + 2);
> else if (!strcmp(argv[1], "number"))
> return do_part_number(argc - 2, argv + 2);
>
> @@ -219,6 +230,9 @@ U_BOOT_CMD(
> "part size\n"
> "- set environment variable to the size of the partition (in
> blocks)\n"
> " part can be either partition number or partition name\n"
> + "part block\n"
> + "- set environment variable to the size of the partition block\n"
> + " part can be either partition number or partition name\n"
> "part number\n"
> "- set environment variable to the partition number using the
> partition name\n"
> " part must be specified as partition name"
I believe you can solve the problems mentioned in the cover letter with
setexpr to do the conversion so nak on this patch, thanks.
--
Tom
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Re: [PATCH]: cmd: part: add part block command
On Mon, Jun 01, 2020 at 01:20:25PM +0300, razvan.beche...@gmail.com wrote: > > The Intel Edison OTA process requires a conversion of data size > from bytes to number of blocks. The following functions are used: > > # function ota_conv_sizes > # Convert a bytes size to a block size > # input bytesize : size in bytes to convert > # input blksize : size of a block in bytes > # output num_blk : converted size in blocks > > # function ota_mmc_write > # Write a memory buffer to mmc drive > # input floadaddr: address of buffer to write > # input u_part_start : block start in mmc > # input num_blk : number of block to write > > This patch adds the cmd part sub-command 'block' which returns > the partition block size in bytes. This is usually done with the setexpr command today, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] env: Add option to only ever append environment
On Tue, Jun 02, 2020 at 06:06:17PM +0200, Marek Vasut wrote:
> On 6/2/20 6:00 PM, Tom Rini wrote:
> > On Tue, Jun 02, 2020 at 05:55:25PM +0200, Marek Vasut wrote:
> >> On 6/2/20 4:38 PM, Tom Rini wrote:
> >>> On Tue, Jun 02, 2020 at 02:47:12PM +0200, Marek Vasut wrote:
> On 6/2/20 2:44 PM, Tom Rini wrote:
> > On Tue, Jun 02, 2020 at 02:05:39PM +0200, Rasmus Villemoes wrote:
> >> On 02/06/2020 13.04, Marek Vasut wrote:
> >>> On 6/2/20 8:42 AM, Rasmus Villemoes wrote:
> On 29/05/2020 19.54, Marek Vasut wrote:
> > +config ENV_APPEND
> > + bool "Always append the environment with new data"
> > + default n
> > + help
> > + If defined, the environment hash table is only ever appended
> > with new
> > + data, but the existing hash table can never be dropped and
> > reloaded
> > + with newly imported data. This may be used in combination
> > with static
> > + flags to e.g. to protect variables which must not be modified.
> > +
> > config ENV_ACCESS_IGNORE_FORCE
> > bool "Block forced environment operations"
> > default n
> > diff --git a/env/env.c b/env/env.c
> > index 024d36fdbe..967a9d36d7 100644
> > --- a/env/env.c
> > +++ b/env/env.c
> > @@ -204,7 +204,9 @@ int env_load(void)
> > ret = drv->load();
> > if (!ret) {
> > printf("OK\n");
> > +#if !CONFIG_IS_ENABLED(ENV_APPEND)
> > return 0;
> > +#endif
>
> Don't use CONFIG_IS_ENABLED() unless you actually introduce both
> CONFIG_FOO and CONFIG_SPL_FOO. Otherwise the above
> CONFIG_IS_ENABLED(ENV_APPEND) is guaranteed to evaluate to false in
> SPL.
> Of course that only matters if environment support is enabled in SPL,
> but some actually use that.
> >>>
> >>> We actually want to use CONFIG_IS_ENABLED() as much as possible to
> >>> make
> >>> these options future-proof, so that others won't have to chase down
> >>> all
> >>> kinds of #ifdef CONFIG stuff and fix it later on for SPL/TPL/etc.
> >>>
> >>
> >> That makes no sense. You're introducing something whose help text
> >> doesn't spell out that the option only applies to U-Boot proper, and is
> >> completely ignored in SPL (since CONFIG_SPL_ENV_APPEND never exists).
> >> The reason it's ignored in SPL is that you use the SPL-or-not-SPL-aware
> >> CONFIG_IS_ENABLED() helper, and you say that's so that somebody in the
> >> future can implement CONFIG_SPL_ENV_APPEND?
> >>
> >> If you intend for ENV_APPEND to be something that's either set or not
> >> set for a given board, then the code needs to use the SPL-agnostic
> >> IS_ENABLED(CONFIG_ENV_APPEND). If you intend it to be something that
> >> can
> >> be set independently for the env support in SPL vs U-Boot proper, you
> >> need to add both config options and, as you do, use CONFIG_IS_ENABLED.
> >
> > How will this code behave if there is a mismatch between SPL and full
> > U-Boot (disabled SPL, enabled full, as the patch stands today) ?
>
> One will append the environment, the other will override it (if you have
> multiple envs enabled).
> >>>
> >>> So it sounds like it wouldn't be valid to have this option differ
> >>> between SPL and main U-Boot?
> >>
> >> Consider the case where you have default env in SPL, and multiple envs
> >> in U-Boot proper.
> >
> > Yes, today you can end up with cases where you build something that doesn't
> > work as intended (likely something around falcon boot and/or boot count
> > limit in env). Which is what I'm getting at here. Is there some
> > cases where it would make any sense to enable this option in full U-Boot
> > but disable it in SPL?
>
> Yes, like my current use case, where I want to configure the SPL
> differently than U-Boot itself. SPL doesn't even have environment
> support enabled, but it might be needed later.
Sorry I wasn't clear enough. Does it make sense (when? how?) to have
environment in SPL but mismatch this feature?
> And also, I don't want to end up in the same problem we currently have
> e.g. with USB gadget, where I have to manually #ifdef CONFIG_SPL_BUILD
> #undef CONFIG_ options in the board config file.
Yes, don't do that, I've had to fix a few of those of late in catching
converted but still in config header options.
--
Tom
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