[PATCH] doc: devicetree: dt_qemu.rst: Fix the typo and space

[Yu Chien Peter Lin]

Fix typo and whitespace in the document.

Signed-off-by: Yu Chien Peter Lin 
---
 doc/develop/devicetree/dt_qemu.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/doc/develop/devicetree/dt_qemu.rst 
b/doc/develop/devicetree/dt_qemu.rst
index c25c4fb053..8ba2b22559 100644
--- a/doc/develop/devicetree/dt_qemu.rst
+++ b/doc/develop/devicetree/dt_qemu.rst
@@ -13,7 +13,7 @@ When `CONFIG_OF_BOARD` is enabled
 Obtaining the QEMU devicetree
 -
 
-Where QEMU generates its own devicetree to pass to U-Boot tou can use
+Where QEMU generates its own devicetree to pass to U-Boot you can use
 `-dtb u-boot.dtb` to force QEMU to use U-Boot's in-tree version.
 
 To obtain the devicetree that qemu generates, add `-machine dumpdtb=qemu.dtb`,
@@ -38,7 +38,7 @@ to produce a text file. It drops the duplicate header on the 
qemu one. Then it
 joins them up and runs them through dtc to compile the output::
 
 qemu-system-arm -machine virt -machine dumpdtb=qemu.dtb
-cat  <(dtc -I dtb qemu.dtb) <(dtc -I dtb  u-boot.dtb |grep -v /dts-v1/) 
|dtc - -o merged.dtb
+cat  <(dtc -I dtb qemu.dtb) <(dtc -I dtb u-boot.dtb | grep -v /dts-v1/) | 
dtc - -o merged.dtb
 
 You can then run qemu with the merged devicetree, e.g.::
 
-- 
2.34.1

[RFC PATCH] doc: arch: Add document for RISC-V architecture

[Yu Chien Peter Lin]

This patch adds a brief introduction to the RISC-V architecture and
the typical boot process used on a variety of RISC-V platforms.

Signed-off-by: Yu Chien Peter Lin 
---
Hi RISC-V community,

Please leave a comment if there is anything I've missed that should
be mentioned in the document. Thanks.
---
 doc/arch/index.rst |  1 +
 doc/arch/riscv.rst | 43 +++
 2 files changed, 44 insertions(+)
 create mode 100644 doc/arch/riscv.rst

diff --git a/doc/arch/index.rst b/doc/arch/index.rst
index b3e85f9bf3..b8da4b8c8e 100644
--- a/doc/arch/index.rst
+++ b/doc/arch/index.rst
@@ -11,6 +11,7 @@ Architecture-specific doc
m68k
mips
nios2
+   riscv
sandbox/index
sh
x86
diff --git a/doc/arch/riscv.rst b/doc/arch/riscv.rst
new file mode 100644
index 00..243e7e7e2e
--- /dev/null
+++ b/doc/arch/riscv.rst
@@ -0,0 +1,43 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2023, Yu Chien Peter Lin 
+
+RISC-V
+==
+
+Overview
+
+
+This document outlines the U-Boot boot process for the RISC-V architecture.
+RISC-V is an open-source instruction set architecture (ISA) based on the
+principles of reduced instruction set computing (RISC). It has been designed
+to be flexible and customizable, allowing it to be adapted to different use
+cases, from embedded systems to high performance servers.
+
+Typical Boot Process
+
+
+RISC-V production boot images typically include a U-Boot SPL for 
platform-specific
+initialization. The U-Boot SPL then loads a FIT image (u-boot.itb), which 
contains
+an SBI (Supervisor Binary Interface) firmware such as `OpenSBI 
`_, as well as a regular
+U-Boot (or U-Boot proper) running in S-mode. Finally, the S-mode Operating 
System
+is loaded.
+
+In between the boot stages, the hartid is passed through the a0 register, and 
the
+start address of the devicetree is passed through the a1 register.
+
+The following diagram illustrates the boot process::
+
+   <--( M-mode )><---( S-mode )-->
+   ++   +-+++   ++
+   | U-Boot SPL |-->|   SBI   |--->| U-Boot |-->|   OS   |
+   ++   +-+++   ++
+
+To examine the boot process with the QEMU virt machine, you can follow the 
steps
+in the following document:
+:doc:`../board/emulation/qemu-riscv.rst`
+
+Toolchain
+-
+
+You can build the `RISC-V GNU toolchain 
`_ from scratch, or 
download a
+pre-built toolchain from the `releases page 
`_.
-- 
2.34.1

Re: [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64

[Andrew Abbott]

On Sun, Jan 8, 2023, at 08:57, Simon Glass wrote:
> This board is useful for benchmarking overall U-Boot performance. Enable
> the bootstage feature so we get a report.
> 
> Since this returns to the boot rom before finishing executing
> board_init_r() in SPL, add a few bootstage calls so that we can collect
> timing from TPL.
> 
> For the stash region, use a portion of SRAM, 64KB below the stack top.
> This allows the TPL image to be up to nearly 120KB (it is typically about
> 64KB). SPL normally runs from SDRAM at 0, so can use the same stash
> region.
> 
> Signed-off-by: Simon Glass 

> diff --git a/configs/rockpro64-rk3399_defconfig 
> b/configs/rockpro64-rk3399_defconfig
> index 5b8d678f6bb..2f1ae156bd4 100644
> --- a/configs/rockpro64-rk3399_defconfig
> +++ b/configs/rockpro64-rk3399_defconfig
> @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x3F8000
> CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
> CONFIG_ROCKCHIP_RK3399=y
> CONFIG_TARGET_ROCKPRO64_RK3399=y
> +CONFIG_BOOTSTAGE_STASH_ADDR=0xff8e
> CONFIG_DEBUG_UART_BASE=0xFF1A
> CONFIG_DEBUG_UART_CLOCK=2400
> CONFIG_SPL_SPI_FLASH_SUPPORT=y
> @@ -17,6 +18,12 @@ CONFIG_SYS_LOAD_ADDR=0x800800
> CONFIG_DEBUG_UART=y
> CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30
> +CONFIG_BOOTSTAGE=y

Building from master commit a1e6b529e57c622e862e93fa6da03d9504565089 and 
copying u-boot-rockchip.bin to an SD card and booting from that on a RockPRO64 
v2.1, I don't get past this:
(dirty because building on NixOS applies some patches)

>U-Boot TPL 2023.04-rc1-00483-ga1e6b529e5-dirty (Jan 01 1980 - 00:00:00)
>Channel 0: LPDDR4, 50MHz
>BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
>Channel 1: LPDDR4, 50MHz
>BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
>256B stride
>lpddr4_set_rate: change freq to 800MHz 1, 0
>Trying to boot from BOOTROM
>Returning to boot ROM...
>
>U-Boot SPL 2023.04-rc1-00483-ga1e6b529e5-dirty (Jan 01 1980 - 00:00:00 +)
>Trying to boot from MMC2

I bisected down to this patch. If I disable CONFIG_BOOTSTATE, I can boot. Is 
there something I need to do to successfully boot with bootstate enabled?

[PATCH v2 4/4] arm64: dts: imx8mp: Do not delete PHY nodes on i.MX8MP DHCOM PDK2

[Marek Vasut]

The PHY nodes may be activated via DTO in case another SoM variant
is populated into the development kit. Do not delete the nodes.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: u-boot@lists.denx.de
---
V2: No change
---
 arch/arm/dts/imx8mp-dhcom-pdk2.dts | 12 
 1 file changed, 12 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts 
b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
index ac104cd3e62..8f4eff37c40 100644
--- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
@@ -104,18 +104,6 @@
};
 };
 
-/*
- * PDK2 carrier board uses SoM with KSZ9131 populated and connected to
- * SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node.
- */
-/delete-node/ 
-
-/*
- * PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC
- * ethernet RGMII interface. The SoM is not populated with second FEC PHY.
- */
-/delete-node/ 
-
  { /* Second ethernet */
pinctrl-0 = <_fec_rgmii>;
phy-handle = <>;
-- 
2.39.1

[PATCH v2 3/4] arm64: dts: imx8mp: Add FEC RMII pin mux on i.MX8MP DHCOM

[Marek Vasut]

The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for both options, so that DT overlay can override these
settings on SoM variant with the LAN8740Ai PHY.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: u-boot@lists.denx.de
---
V2: No change
---
 arch/arm/dts/imx8mp-dhcom-pdk2.dts |  2 ++
 arch/arm/dts/imx8mp-dhcom-som.dtsi | 22 +++---
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts 
b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
index 382fbedaf6b..ac104cd3e62 100644
--- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
@@ -117,7 +117,9 @@
 /delete-node/ 
 
  { /* Second ethernet */
+   pinctrl-0 = <_fec_rgmii>;
phy-handle = <>;
+   phy-mode = "rgmii";
 
mdio {
ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi 
b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index b56607dfb39..9fd8bce8065 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -129,9 +129,9 @@
 
  { /* Second ethernet */
pinctrl-names = "default";
-   pinctrl-0 = <_fec>;
+   pinctrl-0 = <_fec_rmii>;
phy-handle = <>;
-   phy-mode = "rgmii";
+   phy-mode = "rmii";
fsl,magic-packet;
status = "okay";
 
@@ -723,7 +723,7 @@
>;
};
 
-   pinctrl_fec: dhcom-fec-grp {
+   pinctrl_fec_rgmii: dhcom-fec-rgmii-grp {/* RGMII */
fsl,pins = <
MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK0x1f
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC   0x3
@@ -744,6 +744,22 @@
>;
};
 
+   pinctrl_fec_rmii: dhcom-fec-rmii-grp {  /* RMII */
+   fsl,pins = <
+   MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC   0x3
+   MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO  0x3
+   MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
+   MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
+   MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL  0x91
+   MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x91
+   MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
+   MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
+   MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL  0x1f
+   /* Clock */
+   MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK
0x401f
+   >;
+   };
+
pinctrl_flexcan1: dhcom-flexcan1-grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX  0x154
-- 
2.39.1

[PATCH v2 2/4] arm64: dts: imx8mp: Add EQoS RMII pin mux on i.MX8MP DHCOM

[Marek Vasut]

The i.MX8MP DHCOM SoM may come with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY on the SoM attached to EQoS MAC. Add pin
mux settings for both options, so that DT overlay can override
these settings on SoM variant with the LAN8740Ai PHY.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: u-boot@lists.denx.de
---
V2: No change
---
 arch/arm/dts/imx8mp-dhcom-som.dtsi | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi 
b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index 304c94557ed..b56607dfb39 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -83,7 +83,7 @@
 
  {/* First ethernet */
pinctrl-names = "default";
-   pinctrl-0 = <_eqos>;
+   pinctrl-0 = <_eqos_rgmii>;
phy-handle = <>;
phy-mode = "rgmii-id";
status = "okay";
@@ -664,7 +664,7 @@
>;
};
 
-   pinctrl_eqos: dhcom-eqos-grp {  /* RGMII */
+   pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp {  /* RGMII */
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO   0x3
@@ -683,6 +683,22 @@
>;
};
 
+   pinctrl_eqos_rmii: dhcom-eqos-rmii-grp {/* RMII */
+   fsl,pins = <
+   MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+   MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO   0x3
+   MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+   MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0   0x1f
+   MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1   0x1f
+   MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER   0x1f
+   MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+   MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0   0x91
+   MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1   0x91
+   /* Clock */
+   
MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK  0x401f
+   >;
+   };
+
pinctrl_enet_vio: dhcom-enet-vio-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO100x22
-- 
2.39.1

[PATCH v2 1/4] arm64: dts: imx8mp: Adjust EQoS PHY address on i.MX8MP DHCOM

[Marek Vasut]

The current variant of the SoM has LAN8740Ai PHY connected to EQoS
strapped to MDIO address 0 , adjust the MDIO address to match the
hardware.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: u-boot@lists.denx.de
---
V2: This is EQoS PHY address, not FEC, update commit message
---
 arch/arm/dts/imx8mp-dhcom-som.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi 
b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index 0f13ee36277..304c94557ed 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -94,14 +94,14 @@
#size-cells = <0>;
 
/* Up to one of these two PHYs may be populated. */
-   ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
+   ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
compatible = "ethernet-phy-id0007.c110",
 "ethernet-phy-ieee802.3-c22";
interrupt-parent = <>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <_ethphy0>;
pinctrl-names = "default";
-   reg = <1>;
+   reg = <0>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = < 20 GPIO_ACTIVE_LOW>;
-- 
2.39.1

[PATCH] arm64: imx8mp: Auto-detect PHY on i.MX8MP DHCOM

[Marek Vasut]

The i.MX8MP DHCOM SoM may be populated with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY attached to EQoS MAC, and either external RGMII PHY
or LAN8740Ai RMII PHY attached to FEC MAC. The SoM configuration can be
detected for each MAC by reading RX_CTL pull resistor state early on boot.
Make use of this, detect the exact PHY configuration, and patch control DT
accordingly so that the ethernet is configured correctly in U-Boot.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: u-boot@lists.denx.de
---
 .../dh_imx8mp/imx8mp_dhcom_pdk2.c | 228 ++
 1 file changed, 228 insertions(+)

diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c 
b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index 5edb85e1de5..760ea4be35c 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -5,12 +5,16 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -116,3 +120,227 @@ enum env_location env_get_location(enum env_operation op, 
int prio)
 {
return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
 }
+
+static const char *iomuxc_compat = "fsl,imx8mp-iomuxc";
+static const char *lan_compat = "ethernet-phy-id0007.c110";
+static const char *ksz_compat = "ethernet-phy-id0022.1642";
+
+static int dh_dt_patch_som_eqos(const void *fdt_blob)
+{
+   const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
+   FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24);
+   int mac_node, mdio_node, iomuxc_node, ksz_node, lan_node, subnode;
+   const char *mac_compat = "nxp,imx8mp-dwmac-eqos";
+   void *blob = (void *)fdt_blob;
+   const fdt32_t *clk_prop;
+   bool is_gigabit;
+   u32 handle;
+   u32 clk[6];
+
+   setbits_le32(mux, IOMUX_CONFIG_SION);
+   is_gigabit = !(readl(GPIO1_BASE_ADDR) & BIT(24));
+   clrbits_le32(mux, IOMUX_CONFIG_SION);
+
+   /* Adjust EQoS node for Gigabit KSZ9131RNXI or Fast LAN8740Ai PHY */
+   mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
+   if (mac_node < 0)
+   return 0;
+
+   mdio_node = fdt_first_subnode(blob, mac_node);
+   if (mdio_node < 0)
+   return 0;
+
+   /* KSZ9131RNXI */
+   ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat);
+   if (ksz_node < 0)
+   return 0;
+
+   /* LAN8740Ai */
+   lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
+   if (lan_node < 0)
+   return 0;
+
+   iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat);
+   if (iomuxc_node < 0)
+   return 0;
+
+   /*
+* The code below adjusts the following DT properties:
+* - assigned-clock-parents .. 125 MHz RGMII / 50 MHz RMII ref clock
+* - assigned-clock-rates  125 MHz RGMII / 50 MHz RMII ref clock
+* - phy-handle .. KSZ9131RNXI RGMII / LAN8740Ai RMII
+* - phy-mode  RGMII / RMII
+* - pinctrl-0 ... RGMII / RMII
+* - PHY subnode status .. "disabled"/"okay" per RGMII / RMII
+*/
+
+   /* Perform all inplace changes first, string changes last. */
+   clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL);
+   if (!clk_prop)
+   return 0;
+   clk[0] = clk_prop[0];
+   clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M);
+   clk[2] = clk_prop[2];
+   clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M);
+   clk[4] = clk_prop[4];
+   clk[5] = is_gigabit ? cpu_to_fdt32(IMX8MP_SYS_PLL2_125M) :
+ cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
+   fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents",
+   clk, 6 * sizeof(u32));
+
+   clk[0] = cpu_to_fdt32(0);
+   clk[1] = cpu_to_fdt32(1);
+   clk[2] = is_gigabit ? cpu_to_fdt32(12500) :
+ cpu_to_fdt32(5000);
+   fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates",
+   clk, 3 * sizeof(u32));
+
+   handle = fdt_get_phandle(blob, is_gigabit ? ksz_node : lan_node);
+   fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle);
+
+   fdt_for_each_subnode(subnode, blob, iomuxc_node) {
+   if (!strstr(fdt_get_name(blob, subnode, NULL),
+   is_gigabit ? "eqos-rgmii" : "eqos-rmii"))
+   continue;
+
+   handle = fdt_get_phandle(blob, subnode);
+   fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle);
+   break;
+   }
+
+   fdt_setprop_string(blob, mac_node, "phy-mode",
+  is_gigabit ? "rgmii-id" : "rmii");
+
+   mac_node 

[PATCH 4/4] arm64: dts: imx8mp: Do not delete PHY nodes on i.MX8MP DHCOM PDK2

[Marek Vasut]

The PHY nodes may be activated via DTO in case another SoM variant
is populated into the development kit. Do not delete the nodes.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: u-boot@lists.denx.de
---
 arch/arm/dts/imx8mp-dhcom-pdk2.dts | 12 
 1 file changed, 12 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts 
b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
index ac104cd3e62..8f4eff37c40 100644
--- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
@@ -104,18 +104,6 @@
};
 };
 
-/*
- * PDK2 carrier board uses SoM with KSZ9131 populated and connected to
- * SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node.
- */
-/delete-node/ 
-
-/*
- * PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC
- * ethernet RGMII interface. The SoM is not populated with second FEC PHY.
- */
-/delete-node/ 
-
  { /* Second ethernet */
pinctrl-0 = <_fec_rgmii>;
phy-handle = <>;
-- 
2.39.1

[PATCH 3/4] arm64: dts: imx8mp: Add FEC RMII pin mux on i.MX8MP DHCOM

[Marek Vasut]

The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for both options, so that DT overlay can override these
settings on SoM variant with the LAN8740Ai PHY.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: u-boot@lists.denx.de
---
 arch/arm/dts/imx8mp-dhcom-pdk2.dts |  2 ++
 arch/arm/dts/imx8mp-dhcom-som.dtsi | 22 +++---
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts 
b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
index 382fbedaf6b..ac104cd3e62 100644
--- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
@@ -117,7 +117,9 @@
 /delete-node/ 
 
  { /* Second ethernet */
+   pinctrl-0 = <_fec_rgmii>;
phy-handle = <>;
+   phy-mode = "rgmii";
 
mdio {
ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi 
b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index b56607dfb39..9fd8bce8065 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -129,9 +129,9 @@
 
  { /* Second ethernet */
pinctrl-names = "default";
-   pinctrl-0 = <_fec>;
+   pinctrl-0 = <_fec_rmii>;
phy-handle = <>;
-   phy-mode = "rgmii";
+   phy-mode = "rmii";
fsl,magic-packet;
status = "okay";
 
@@ -723,7 +723,7 @@
>;
};
 
-   pinctrl_fec: dhcom-fec-grp {
+   pinctrl_fec_rgmii: dhcom-fec-rgmii-grp {/* RGMII */
fsl,pins = <
MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK0x1f
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC   0x3
@@ -744,6 +744,22 @@
>;
};
 
+   pinctrl_fec_rmii: dhcom-fec-rmii-grp {  /* RMII */
+   fsl,pins = <
+   MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC   0x3
+   MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO  0x3
+   MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
+   MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
+   MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL  0x91
+   MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x91
+   MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
+   MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
+   MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL  0x1f
+   /* Clock */
+   MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK
0x401f
+   >;
+   };
+
pinctrl_flexcan1: dhcom-flexcan1-grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX  0x154
-- 
2.39.1

[PATCH 2/4] arm64: dts: imx8mp: Add EQoS RMII pin mux on i.MX8MP DHCOM

[Marek Vasut]

The i.MX8MP DHCOM SoM may come with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY on the SoM attached to EQoS MAC. Add pin
mux settings for both options, so that DT overlay can override
these settings on SoM variant with the LAN8740Ai PHY.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: u-boot@lists.denx.de
---
 arch/arm/dts/imx8mp-dhcom-som.dtsi | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi 
b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index 304c94557ed..b56607dfb39 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -83,7 +83,7 @@
 
  {/* First ethernet */
pinctrl-names = "default";
-   pinctrl-0 = <_eqos>;
+   pinctrl-0 = <_eqos_rgmii>;
phy-handle = <>;
phy-mode = "rgmii-id";
status = "okay";
@@ -664,7 +664,7 @@
>;
};
 
-   pinctrl_eqos: dhcom-eqos-grp {  /* RGMII */
+   pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp {  /* RGMII */
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO   0x3
@@ -683,6 +683,22 @@
>;
};
 
+   pinctrl_eqos_rmii: dhcom-eqos-rmii-grp {/* RMII */
+   fsl,pins = <
+   MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+   MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO   0x3
+   MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+   MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0   0x1f
+   MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1   0x1f
+   MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER   0x1f
+   MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+   MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0   0x91
+   MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1   0x91
+   /* Clock */
+   
MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK  0x401f
+   >;
+   };
+
pinctrl_enet_vio: dhcom-enet-vio-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO100x22
-- 
2.39.1

[PATCH 1/4] arm64: dts: imx8mp: Adjust FEC PHY address on i.MX8MP DHCOM

[Marek Vasut]

The current variant of the SoM has LAN8740Ai PHY connected to FEC
strapped to MDIO address 0 , adjust the MDIO address to match the
hardware.

Signed-off-by: Marek Vasut 
---
Cc: "NXP i.MX U-Boot Team" 
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
Cc: u-boot@lists.denx.de
---
 arch/arm/dts/imx8mp-dhcom-som.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi 
b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index 0f13ee36277..304c94557ed 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -94,14 +94,14 @@
#size-cells = <0>;
 
/* Up to one of these two PHYs may be populated. */
-   ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
+   ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
compatible = "ethernet-phy-id0007.c110",
 "ethernet-phy-ieee802.3-c22";
interrupt-parent = <>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <_ethphy0>;
pinctrl-names = "default";
-   reg = <1>;
+   reg = <0>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = < 20 GPIO_ACTIVE_LOW>;
-- 
2.39.1

[PATCH] ARM: imx: Add 2 GiB DRAM support for DH electronics i.MX8M Plus DHCOM

[Marek Vasut]

The DH electronics i.MX8M Plus DHCOM SoM currently supports only 4 GiB
of DRAM population option. Add another population option with 2 GiB of
DRAM. The chips used on the 2 GiB option are 2x K4F6E3S4HM-MGCJ .

Signed-off-by: Marek Vasut 
---
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
---
 board/dhelectronics/dh_imx8mp/Makefile|2 +-
 board/dhelectronics/dh_imx8mp/lpddr4_timing.h |1 +
 .../dh_imx8mp/lpddr4_timing_2G_32.c   | 1845 +
 board/dhelectronics/dh_imx8mp/spl.c   |2 +-
 4 files changed, 1848 insertions(+), 2 deletions(-)
 create mode 100644 board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c

diff --git a/board/dhelectronics/dh_imx8mp/Makefile 
b/board/dhelectronics/dh_imx8mp/Makefile
index 86ffc31fed8..e5a29fdd122 100644
--- a/board/dhelectronics/dh_imx8mp/Makefile
+++ b/board/dhelectronics/dh_imx8mp/Makefile
@@ -5,7 +5,7 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o lpddr4_timing_4G_32.o
+obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o
 else
 obj-y += imx8mp_dhcom_pdk2.o
 endif
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h 
b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
index 6d496a970be..7894da3b918 100644
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
@@ -6,6 +6,7 @@
 #ifndef __LPDDR4_TIMING_H__
 #define __LPDDR4_TIMING_H__
 
+extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
 extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
 
 u8 dh_get_memcfg(void);
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c 
b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
new file mode 100644
index 000..51b8c4cf7ba
--- /dev/null
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
@@ -0,0 +1,1845 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut 
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include 
+#include 
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+   /** Initialize DDRC registers **/
+   { 0x3d400304, 0x1 },
+   { 0x3d400030, 0x1 },
+   { 0x3d40, 0xa1080020 },
+   { 0x3d400020, 0x1323 },
+   { 0x3d400024, 0x1c79100 },
+   { 0x3d400064, 0x710106 },
+   { 0x3d400070, 0x7027f90 },
+   { 0x3d400074, 0x790 },
+   { 0x3d4000d0, 0xc0030720 },
+   { 0x3d4000d4, 0xb8 },
+   { 0x3d4000dc, 0xe40036 },
+   { 0x3d4000e0, 0x33 },
+   { 0x3d4000e8, 0x660048 },
+   { 0x3d4000ec, 0x160048 },
+   { 0x3d400100, 0x1e262028 },
+   { 0x3d400104, 0x7073b },
+   { 0x3d40010c, 0xe0e000 },
+   { 0x3d400110, 0x11040a11 },
+   { 0x3d400114, 0x2050e0e },
+   { 0x3d400118, 0x1010008 },
+   { 0x3d40011c, 0x502 },
+   { 0x3d400130, 0x20700 },
+   { 0x3d400134, 0xd12 },
+   { 0x3d400138, 0x10d },
+   { 0x3d400144, 0xbb005e },
+   { 0x3d400180, 0x3a5001c },
+   { 0x3d400184, 0x2f071e5 },
+   { 0x3d400188, 0x0 },
+   { 0x3d400190, 0x49b820c },
+   { 0x3d400194, 0x80303 },
+   { 0x3d4001b4, 0x1b0c },
+   { 0x3d4001a0, 0xe0400018 },
+   { 0x3d4001a4, 0xdf00e4 },
+   { 0x3d4001a8, 0x8000 },
+   { 0x3d4001b0, 0x11 },
+   { 0x3d4001c0, 0x1 },
+   { 0x3d4001c4, 0x1 },
+   { 0x3d4000f4, 0x799 },
+   { 0x3d400108, 0x810191a },
+   { 0x3d400200, 0x1f },
+   { 0x3d400208, 0x0 },
+   { 0x3d40020c, 0x0 },
+   { 0x3d400210, 0x1f1f },
+   { 0x3d400204, 0x80808 },
+   { 0x3d400214, 0x7070707 },
+   { 0x3d400218, 0x7070707 },
+   { 0x3d40021c, 0xf0f },
+   { 0x3d400250, 0x1705 },
+   { 0x3d400254, 0x2c },
+   { 0x3d40025c, 0x430 },
+   { 0x3d400264, 0x900093e7 },
+   { 0x3d40026c, 0x2005574 },
+   { 0x3d400400, 0x111 },
+   { 0x3d400404, 0x72ff },
+   { 0x3d400408, 0x72ff },
+   { 0x3d400494, 0x2100e07 },
+   { 0x3d400498, 0x620096 },
+   { 0x3d40049c, 0x1100e07 },
+   { 0x3d4004a0, 0xc8012c },
+   { 0x3d402020, 0x1021 },
+   { 0x3d402024, 0x30d400 },
+   { 0x3d402050, 0x20d000 },
+   { 0x3d402064, 0xc001c },
+   { 0x3d4020dc, 0x84 },
+   { 0x3d4020e0, 0x33 },
+   { 0x3d4020e8, 0x660048 },
+   { 0x3d4020ec, 0x160048 },
+   { 0x3d402100, 0xa040305 },
+   { 0x3d402104, 0x30407 },
+   { 0x3d402108, 0x203060b },
+   { 0x3d40210c, 0x505000 },
+   { 0x3d402110, 0x2040202 },
+   { 0x3d402114, 0x2030202 },
+   { 0x3d402118, 0x1010004 },
+   { 0x3d40211c, 0x302 },
+   { 0x3d402130, 0x20300 },
+   { 0x3d402134, 0xa12 },
+   { 0x3d402138, 0x1d },
+   { 0x3d402144, 0x14000a },
+   { 0x3d402180, 0x640004 },
+   { 0x3d402190, 0x3818200 },
+   { 0x3d402194, 0x80303 },
+   { 0x3d4021b4, 0x100 },
+   { 0x3d4020f4, 0x599 },
+   { 0x3d403020, 0x1021 },
+   { 0x3d403024, 0xc3500 },
+   { 0x3d403050, 0x20d000 },
+   { 0x3d403064, 0x30007 },
+   { 

[PATCH] ARM: imx: Enable LTO for DH electronics i.MX8M Plus DHCOM

[Marek Vasut]

Enable LTO to reduce the size of SPL, which with multiple DRAM
calibration tables may be close to the limit.

Signed-off-by: Marek Vasut 
---
Cc: Fabio Estevam 
Cc: Peng Fan 
Cc: Stefano Babic 
---
 configs/imx8mp_dhcom_pdk2_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/imx8mp_dhcom_pdk2_defconfig 
b/configs/imx8mp_dhcom_pdk2_defconfig
index 7986d81d672..b1b21639ec1 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -29,6 +29,7 @@ CONFIG_IMX_BOOTAUX=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800
 CONFIG_SYS_LOAD_ADDR=0x5000
 CONFIG_DEBUG_UART=y
+CONFIG_LTO=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_SYS_MONITOR_LEN=1048576
 CONFIG_FIT=y
-- 
2.39.1

[PATCH v3 14/14] arm64: imx8mm: imx8mn: imx8mp: Drop FEC GPR[1] board workaround

[Marek Vasut]

The FEC interface mode is now configured in common board_interface_eth_init()
and called by FEC MAC driver when appropriate. Drop the board side duplicates
if the same functionality.

Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V3: New patch
---
 arch/arm/mach-imx/imx8m/clock_imx8mm.c| 51 +--
 .../dh_imx8mp/imx8mp_dhcom_pdk2.c | 12 -
 board/engicam/imx8mm/icore_mx8mm.c| 15 +-
 board/kontron/pitx_imx8m/pitx_imx8m.c | 14 +
 4 files changed, 3 insertions(+), 89 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 3f03b515a63..51ebc27244d 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -868,55 +868,7 @@ static int imx8mp_eqos_interface_init(struct udevice *dev,
 }
 #endif
 
-#ifdef CONFIG_FEC_MXC
-int set_clk_enet(enum enet_freq type)
-{
-   u32 target;
-   u32 enet1_ref;
-
-   switch (type) {
-   case ENET_125MHZ:
-   enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
-   break;
-   case ENET_50MHZ:
-   enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
-   break;
-   case ENET_25MHZ:
-   enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
-   break;
-   default:
-   return -EINVAL;
-   }
-
-   /* disable the clock first */
-   clock_enable(CCGR_ENET1, 0);
-   clock_enable(CCGR_SIM_ENET, 0);
-
-   /* set enet axi clock 266Mhz */
-   target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
-CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
-   clock_set_target_val(ENET_AXI_CLK_ROOT, target);
-
-   target = CLK_ROOT_ON | enet1_ref |
-CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
-   clock_set_target_val(ENET_REF_CLK_ROOT, target);
-
-   target = CLK_ROOT_ON |
-   ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
-   CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-   CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
-   clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
-
-   /* enable clock */
-   clock_enable(CCGR_SIM_ENET, 1);
-   clock_enable(CCGR_ENET1, 1);
-
-   return 0;
-}
-
-#ifdef CONFIG_IMX8MP
+#if defined(CONFIG_IMX8MP) && defined(CONFIG_FEC_MXC)
 static int imx8mp_fec_interface_init(struct udevice *dev,
 phy_interface_t interface_type,
 bool mx8mp)
@@ -948,7 +900,6 @@ static int imx8mp_fec_interface_init(struct udevice *dev,
return 0;
 }
 #endif
-#endif
 
 int board_interface_eth_init(struct udevice *dev, phy_interface_t 
interface_type)
 {
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c 
b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index cb9973900bd..5edb85e1de5 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -37,17 +37,6 @@ int board_phys_sdram_size(phys_size_t *size)
return 0;
 }
 
-static void setup_fec(void)
-{
-   struct iomuxc_gpr_base_regs *gpr =
-   (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-   /* Enable RGMII TX clk output. */
-   setbits_le32(>gpr[1], BIT(22));
-
-   set_clk_enet(ENET_125MHZ);
-}
-
 static int dh_imx8_setup_ethaddr(void)
 {
unsigned char enetaddr[6];
@@ -114,7 +103,6 @@ int dh_setup_mac_address(void)
 
 int board_init(void)
 {
-   setup_fec();
return 0;
 }
 
diff --git a/board/engicam/imx8mm/icore_mx8mm.c 
b/board/engicam/imx8mm/icore_mx8mm.c
index 4f7c699d7d1..320388faae3 100644
--- a/board/engicam/imx8mm/icore_mx8mm.c
+++ b/board/engicam/imx8mm/icore_mx8mm.c
@@ -29,7 +29,7 @@ static iomux_v3_cfg_t const fec1_rst_pads[] = {
IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-static void setup_iomux_fec(void)
+static void setup_fec(void)
 {
imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
 ARRAY_SIZE(fec1_rst_pads));
@@ -40,19 +40,6 @@ static void setup_iomux_fec(void)
gpio_direction_output(FEC_RST_PAD, 1);
 }
 
-static int setup_fec(void)
-{
-   struct iomuxc_gpr_base_regs *gpr =
-   (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-   setup_iomux_fec();
-
-   /* Use 125M anatop REF_CLK1 for ENET1, not from external */
-   clrsetbits_le32(>gpr[1], 13, 0);
-
-   return 

[PATCH v3 13/14] arm64: imx8mp: Drop EQoS GPR[1] board workaround

[Marek Vasut]

The EQoS interface mode is now configured in common board_interface_eth_init()
and called by EQoS MAC driver when appropriate. Drop the board side duplicates
if the same functionality.

Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V2: Fix the advantech board build
V3: Drop now unused architecture set_clk_eqos() code as well
---
 arch/arm/include/asm/arch-imx8m/clock.h   |  1 -
 arch/arm/mach-imx/imx8m/clock_imx8mm.c| 47 ---
 .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c   | 17 +--
 .../dh_imx8mp/imx8mp_dhcom_pdk2.c | 14 --
 board/engicam/imx8mp/icore_mx8mp.c| 16 ---
 board/freescale/imx8mp_evk/imx8mp_evk.c   | 17 ---
 board/gateworks/venice/venice.c   | 15 --
 board/msc/sm2s_imx8mp/sm2s_imx8mp.c   | 15 --
 board/toradex/verdin-imx8mp/verdin-imx8mp.c   | 16 ---
 9 files changed, 1 insertion(+), 157 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8m/clock.h 
b/arch/arm/include/asm/arch-imx8m/clock.h
index e4433763bc4..a861cd6db3a 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -276,5 +276,4 @@ int set_clk_qspi(void);
 void enable_ocotp_clk(unsigned char enable);
 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
 int set_clk_enet(enum enet_freq type);
-int set_clk_eqos(enum enet_freq type);
 void hab_caam_clock_enable(unsigned char enable);
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 94b15a86acc..3f03b515a63 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -827,53 +827,6 @@ u32 mxc_get_clock(enum mxc_clock clk)
 }
 
 #if defined(CONFIG_IMX8MP) && defined(CONFIG_DWC_ETH_QOS)
-int set_clk_eqos(enum enet_freq type)
-{
-   u32 target;
-   u32 enet1_ref;
-
-   switch (type) {
-   case ENET_125MHZ:
-   enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
-   break;
-   case ENET_50MHZ:
-   enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
-   break;
-   case ENET_25MHZ:
-   enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
-   break;
-   default:
-   return -EINVAL;
-   }
-
-   /* disable the clock first */
-   clock_enable(CCGR_QOS_ETHENET, 0);
-   clock_enable(CCGR_SDMA2, 0);
-
-   /* set enet axi clock 266Mhz */
-   target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
-CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
-   clock_set_target_val(ENET_AXI_CLK_ROOT, target);
-
-   target = CLK_ROOT_ON | enet1_ref |
-CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
-   clock_set_target_val(ENET_QOS_CLK_ROOT, target);
-
-   target = CLK_ROOT_ON |
-   ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
-   CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-   CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
-   clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
-
-   /* enable clock */
-   clock_enable(CCGR_QOS_ETHENET, 1);
-   clock_enable(CCGR_SDMA2, 1);
-
-   return 0;
-}
-
 static int imx8mp_eqos_interface_init(struct udevice *dev,
  phy_interface_t interface_type)
 {
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c 
b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index 34109c69ddb..9191ddbb682 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -113,7 +113,7 @@ static const iomux_v3_cfg_t eqos_rst_pads[] = {
MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-static void setup_iomux_eqos(void)
+static void setup_eqos(void)
 {
imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
 ARRAY_SIZE(eqos_rst_pads));
@@ -124,21 +124,6 @@ static void setup_iomux_eqos(void)
gpio_direction_output(EQOS_RST_PAD, 1);
mdelay(100);
 }
-
-static int setup_eqos(void)
-{
-   struct iomuxc_gpr_base_regs *gpr =
-   (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-   setup_iomux_eqos();
-
-   /* set INTF as RGMII, enable RGMII TXC clock */
-   clrsetbits_le32(>gpr[1],
-   IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-   setbits_le32(>gpr[1], BIT(19) | BIT(21));
-
-   return set_clk_eqos(ENET_125MHZ);
-}
 #endif /* 

[PATCH v3 12/14] arm64: dts: imx8mp: Drop EQoS clock workaround

[Marek Vasut]

The assigned-clock no longer have to be dropped, the clock are now
defined in clk-imx8mp.c and used by DWMAC driver to configure the
DWMAC clock. Drop the workarounds from U-Boot specific DT extras.

Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V2: No change
V3: No change
---
 arch/arm/dts/imx8mp-dhcom-u-boot.dtsi| 6 --
 arch/arm/dts/imx8mp-evk-u-boot.dtsi  | 6 --
 arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi | 6 --
 arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi| 6 --
 arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi  | 6 --
 5 files changed, 30 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi 
b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
index ae838caebcf..ea6ab9f2e17 100644
--- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
@@ -33,12 +33,6 @@
u-boot,dm-spl;
 };
 
- {
-   /delete-property/ assigned-clocks;
-   /delete-property/ assigned-clock-parents;
-   /delete-property/ assigned-clock-rates;
-};
-
  {
u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi 
b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index f43eb6238d0..cd0fb815c79 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -131,12 +131,6 @@
u-boot,dm-spl;
 };
 
- {
-   /delete-property/ assigned-clocks;
-   /delete-property/ assigned-clock-parents;
-   /delete-property/ assigned-clock-rates;
-};
-
  {
reset-gpios = < 22 GPIO_ACTIVE_LOW>;
reset-delay-us = <15000>;
diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi 
b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
index 342c523b0c5..3e48cf8ec5c 100644
--- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
@@ -130,12 +130,6 @@
u-boot,dm-spl;
 };
 
- {
-   /delete-property/ assigned-clocks;
-   /delete-property/ assigned-clock-parents;
-   /delete-property/ assigned-clock-rates;
-};
-
  {
reset-gpios = < 22 GPIO_ACTIVE_LOW>;
reset-delay-us = <15000>;
diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi 
b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
index d8721124526..849950fe026 100644
--- a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
@@ -20,12 +20,6 @@
};
 };
 
- {
-   /delete-property/ assigned-clocks;
-   /delete-property/ assigned-clock-parents;
-   /delete-property/ assigned-clock-rates;
-};
-
  {
reset-gpios = < 30 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi 
b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
index 8a4cdc717d2..5f021d17230 100644
--- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
@@ -39,12 +39,6 @@
u-boot,dm-spl;
 };
 
- {
-   /delete-property/ assigned-clocks;
-   /delete-property/ assigned-clock-parents;
-   /delete-property/ assigned-clock-rates;
-};
-
  {
u-boot,dm-spl;
 };
-- 
2.39.1

[PATCH v3 11/14] net: fec_mxc: Add board_interface_eth_init() for i.MX8M Mini/Nano/Plus

[Marek Vasut]

Implement common board_interface_eth_init() and call it from the FEC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side
configuration of the same IOMUX GPR[1] duplicated in the board files.

Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V3: New patch
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h |  2 +
 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 48 ++
 drivers/net/fec_mxc.c  |  4 ++
 3 files changed, 54 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h 
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 1818b459fa6..6e2fc82a0e4 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -89,6 +89,7 @@
 #define DDRC_IPS_BASE_ADDR(X)  (0x3d40 + ((X) * 0x200))
 #define DDR_CSD1_BASE_ADDR 0x4000
 
+#define IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN BIT(22)
 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN  BIT(21)
 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SELBIT(20)
 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_ENBIT(19)
@@ -96,6 +97,7 @@
 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII  (0 << 16)
 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII(1 << 16)
 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL   BIT(13)
 #define FEC_QUIRK_ENET_MAC
 
 #ifdef CONFIG_ARMV8_PSCI   /* Final jump location */
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index fb102ae2059..94b15a86acc 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -962,10 +962,58 @@ int set_clk_enet(enum enet_freq type)
 
return 0;
 }
+
+#ifdef CONFIG_IMX8MP
+static int imx8mp_fec_interface_init(struct udevice *dev,
+phy_interface_t interface_type,
+bool mx8mp)
+{
+   /* i.MX8MP has extra RGMII_EN bit in IOMUXC GPR1 register */
+   const u32 rgmii_en = mx8mp ? IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN : 0;
+   struct iomuxc_gpr_base_regs *gpr =
+   (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+   clrbits_le32(>gpr[1],
+rgmii_en |
+IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
+
+   switch (interface_type) {
+   case PHY_INTERFACE_MODE_MII:
+   case PHY_INTERFACE_MODE_RMII:
+   setbits_le32(>gpr[1], 
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
+   break;
+   case PHY_INTERFACE_MODE_RGMII:
+   case PHY_INTERFACE_MODE_RGMII_ID:
+   case PHY_INTERFACE_MODE_RGMII_RXID:
+   case PHY_INTERFACE_MODE_RGMII_TXID:
+   setbits_le32(>gpr[1], rgmii_en);
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   return 0;
+}
+#endif
 #endif
 
 int board_interface_eth_init(struct udevice *dev, phy_interface_t 
interface_type)
 {
+   if (IS_ENABLED(CONFIG_IMX8MM) &&
+   IS_ENABLED(CONFIG_FEC_MXC) &&
+   device_is_compatible(dev, "fsl,imx8mm-fec"))
+   return imx8mp_fec_interface_init(dev, interface_type, false);
+
+   if (IS_ENABLED(CONFIG_IMX8MN) &&
+   IS_ENABLED(CONFIG_FEC_MXC) &&
+   device_is_compatible(dev, "fsl,imx8mn-fec"))
+   return imx8mp_fec_interface_init(dev, interface_type, false);
+
+   if (IS_ENABLED(CONFIG_IMX8MP) &&
+   IS_ENABLED(CONFIG_FEC_MXC) &&
+   device_is_compatible(dev, "fsl,imx8mp-fec"))
+   return imx8mp_fec_interface_init(dev, interface_type, true);
+
if (IS_ENABLED(CONFIG_IMX8MP) &&
IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
device_is_compatible(dev, "nxp,imx8mp-dwmac-eqos"))
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 7a8577158ae..ac937676f9c 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1232,6 +1232,10 @@ static int fecmxc_probe(struct udevice *dev)
uint32_t start;
int ret;
 
+   ret = board_interface_eth_init(dev, pdata->phy_interface);
+   if (ret)
+   return ret;
+
if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
if (enet_fused((ulong)priv->eth)) {
printf("SoC fuse indicates Ethernet@0x%lx is 
unavailable.\n", (ulong)priv->eth);
-- 
2.39.1

[PATCH v3 10/14] net: fec_mxc: Add ref clock setup support for i.MX8M Mini/Nano/Plus

[Marek Vasut]

The FEC ref clock frequency on i.MX8M Mini/Nano/Plus was so far configured
via ad-hoc board code. Replace that with DM clock clk_set_rate() instead.
This way, the driver claims all its required clock and sets the ref clock
rate, without any need of architecture specific register fiddling.

Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V3: New patch
---
 drivers/net/fec_mxc.c | 32 
 1 file changed, 32 insertions(+)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 1a6c18a441f..7a8577158ae 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1196,6 +1196,33 @@ static void fec_gpio_reset(struct fec_priv *priv)
 }
 #endif
 
+static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface)
+{
+   unsigned int freq;
+   int ret;
+
+   if (!CONFIG_IS_ENABLED(CLK_CCF))
+   return 0;
+
+   if (interface == PHY_INTERFACE_MODE_MII)
+   freq = 2500;
+   else if (interface == PHY_INTERFACE_MODE_RMII)
+   freq = 5000;
+   else if (interface == PHY_INTERFACE_MODE_RGMII ||
+interface == PHY_INTERFACE_MODE_RGMII_ID ||
+interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+interface == PHY_INTERFACE_MODE_RGMII_TXID)
+   freq = 12500;
+   else
+   return -EINVAL;
+
+   ret = clk_set_rate(clk_ref, freq);
+   if (ret < 0)
+   return ret;
+
+   return 0;
+}
+
 static int fecmxc_probe(struct udevice *dev)
 {
bool dm_mii_bus = true;
@@ -1253,6 +1280,11 @@ static int fecmxc_probe(struct udevice *dev)
 
ret = clk_get_by_name(dev, "enet_clk_ref", >clk_ref);
if (!ret) {
+   ret = fecmxc_set_ref_clk(>clk_ref,
+pdata->phy_interface);
+   if (ret)
+   return ret;
+
ret = clk_enable(>clk_ref);
if (ret)
return ret;
-- 
2.39.1

[PATCH v3 09/14] net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus

[Marek Vasut]

Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX GPR[1] duplicated in the board files.

Reviewed-by: Ramon Fried 
Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V2: - Add RB from Ramon
- Handle RGMII_ID/RGMII_RXID/RGMII_TXID just like plain RGMII
V3: Make the function more generic, so it can be shared by eqos and fec
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h |  8 +++-
 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 +-
 drivers/net/dwc_eth_qos_imx.c  |  4 ++
 3 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h 
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 1559bf6d218..1818b459fa6 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -89,7 +89,13 @@
 #define DDRC_IPS_BASE_ADDR(X)  (0x3d40 + ((X) * 0x200))
 #define DDR_CSD1_BASE_ADDR 0x4000
 
-#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x7
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN  BIT(21)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SELBIT(20)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_ENBIT(19)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(18, 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII  (0 << 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII(1 << 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16)
 #define FEC_QUIRK_ENET_MAC
 
 #ifdef CONFIG_ARMV8_PSCI   /* Final jump location */
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 494bfbedc8c..fb102ae2059 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -825,7 +826,7 @@ u32 mxc_get_clock(enum mxc_clock clk)
return 0;
 }
 
-#ifdef CONFIG_DWC_ETH_QOS
+#if defined(CONFIG_IMX8MP) && defined(CONFIG_DWC_ETH_QOS)
 int set_clk_eqos(enum enet_freq type)
 {
u32 target;
@@ -872,6 +873,46 @@ int set_clk_eqos(enum enet_freq type)
 
return 0;
 }
+
+static int imx8mp_eqos_interface_init(struct udevice *dev,
+ phy_interface_t interface_type)
+{
+   struct iomuxc_gpr_base_regs *gpr =
+   (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+   clrbits_le32(>gpr[1],
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN);
+
+   switch (interface_type) {
+   case PHY_INTERFACE_MODE_MII:
+   setbits_le32(>gpr[1],
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII);
+   break;
+   case PHY_INTERFACE_MODE_RMII:
+   setbits_le32(>gpr[1],
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII);
+   break;
+   case PHY_INTERFACE_MODE_RGMII:
+   case PHY_INTERFACE_MODE_RGMII_ID:
+   case PHY_INTERFACE_MODE_RGMII_RXID:
+   case PHY_INTERFACE_MODE_RGMII_TXID:
+   setbits_le32(>gpr[1],
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII);
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   return 0;
+}
 #endif
 
 #ifdef CONFIG_FEC_MXC
@@ -922,3 +963,13 @@ int set_clk_enet(enum enet_freq type)
return 0;
 }
 #endif
+
+int board_interface_eth_init(struct udevice *dev, phy_interface_t 
interface_type)
+{
+   if (IS_ENABLED(CONFIG_IMX8MP) &&
+   IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
+   device_is_compatible(dev, "nxp,imx8mp-dwmac-eqos"))
+   return imx8mp_eqos_interface_init(dev, interface_type);
+
+   return -EINVAL;
+}
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index 962c5373243..60f3f3f5a10 100644
--- 

[PATCH v3 08/14] net: dwc_eth_qos: Add i.MX8M Plus RMII support

[Marek Vasut]

With DM clock support in place, it is easy to add RMII support into the
MAC driver. The RMII cannot operate at 1000 Mbps and at 100 and 10 Mbps
the clock frequency is 50 MHz and 5 MHz instead of 25 MHz and 2.5 MHz.

The board DT requires the following adjustments to EQoS node:
  phy-mode = "rmii";
  assigned-clock-parents = < IMX8MP_SYS_PLL1_266M>,
< IMX8MP_SYS_PLL2_100M>,
< IMX8MP_SYS_PLL2_50M>;
  assigned-clock-rates = <0>, <1>, <5000>;

Reviewed-by: Ramon Fried 
Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V2: Add RB from Ramon
V3: Handle RGMII_*ID variants
---
 drivers/net/dwc_eth_qos_imx.c | 29 ++---
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index f5f3f2099f0..962c5373243 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -179,21 +179,28 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
 
debug("%s(dev=%p):\n", __func__, dev);
 
-   switch (eqos->phy->speed) {
-   case SPEED_1000:
-   rate = 125 * 1000 * 1000;
-   break;
-   case SPEED_100:
-   rate = 25 * 1000 * 1000;
-   break;
-   case SPEED_10:
-   rate = 2.5 * 1000 * 1000;
-   break;
-   default:
+   if (eqos->phy->interface == PHY_INTERFACE_MODE_RMII)
+   rate = 5000;/* 5000 kHz = 5 MHz */
+   else
+   rate = 2500;/* 2500 kHz = 2.5 MHz */
+
+   if (eqos->phy->speed == SPEED_1000 &&
+   (eqos->phy->interface == PHY_INTERFACE_MODE_RGMII ||
+eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
+   rate *= 50; /* Use 50x base rate i.e. 125 MHz */
+   } else if (eqos->phy->speed == SPEED_100) {
+   rate *= 10; /* Use 10x base rate */
+   } else if (eqos->phy->speed == SPEED_10) {
+   rate *= 1;  /* Use base rate */
+   } else {
pr_err("invalid speed %d", eqos->phy->speed);
return -EINVAL;
}
 
+   rate *= 1000;   /* clk_set_rate() operates in Hz */
+
ret = clk_set_rate(>clk_tx, rate);
if (ret < 0) {
pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
-- 
2.39.1

[PATCH v3 07/14] net: dwc_eth_qos: Add DM CLK support for i.MX8M Plus

[Marek Vasut]

The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc
architecture code. Replace that with DM clock instead. This way,
the driver claims all its required clock, enables and disables
them, and even gets the CSR clock rate and sets the TX clock rate,
without any need of architecture specific register fiddling. Drop
the architecture specific code while at it too.

The adjustment here is modeled after STM32MP15xx clock handling
in this driver.

Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V2: Turn all the pr_err() into dev_dbg()
V3: No change
---
 arch/arm/mach-imx/imx8m/clock_imx8mm.c |  41 
 drivers/net/dwc_eth_qos_imx.c  | 131 +++--
 2 files changed, 121 insertions(+), 51 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 64ad57e9b39..494bfbedc8c 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -872,47 +872,6 @@ int set_clk_eqos(enum enet_freq type)
 
return 0;
 }
-
-int imx_eqos_txclk_set_rate(ulong rate)
-{
-   u32 val;
-   u32 eqos_post_div;
-
-   /* disable the clock first */
-   clock_enable(CCGR_QOS_ETHENET, 0);
-   clock_enable(CCGR_SDMA2, 0);
-
-   switch (rate) {
-   case 12500:
-   eqos_post_div = 1;
-   break;
-   case 2500:
-   eqos_post_div = 12500 / 2500;
-   break;
-   case 250:
-   eqos_post_div = 12500 / 250;
-   break;
-   default:
-   return -EINVAL;
-   }
-
-   clock_get_target_val(ENET_QOS_CLK_ROOT, );
-   val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
-   val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-  CLK_ROOT_POST_DIV(eqos_post_div - 1);
-   clock_set_target_val(ENET_QOS_CLK_ROOT, val);
-
-   /* enable clock */
-   clock_enable(CCGR_QOS_ETHENET, 1);
-   clock_enable(CCGR_SDMA2, 1);
-
-   return 0;
-}
-
-u32 imx_get_eqos_csr_clk(void)
-{
-   return get_root_clk(ENET_AXI_CLK_ROOT);
-}
 #endif
 
 #ifdef CONFIG_FEC_MXC
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index 42cb164ad14..f5f3f2099f0 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -32,20 +33,18 @@ __weak u32 imx_get_eqos_csr_clk(void)
return 100 * 100;
 }
 
-__weak int imx_eqos_txclk_set_rate(unsigned long rate)
-{
-   return 0;
-}
-
 static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
 {
-   return imx_get_eqos_csr_clk();
+   struct eqos_priv *eqos = dev_get_priv(dev);
+
+   return clk_get_rate(>clk_master_bus);
 }
 
 static int eqos_probe_resources_imx(struct udevice *dev)
 {
struct eqos_priv *eqos = dev_get_priv(dev);
phy_interface_t interface;
+   int ret;
 
debug("%s(dev=%p):\n", __func__, dev);
 
@@ -56,6 +55,118 @@ static int eqos_probe_resources_imx(struct udevice *dev)
return -EINVAL;
}
 
+   eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
+
+   ret = clk_get_by_name(dev, "stmmaceth", >clk_master_bus);
+   if (ret) {
+   dev_dbg(dev, "clk_get_by_name(master_bus) failed: %d", ret);
+   goto err_probe;
+   }
+
+   ret = clk_get_by_name(dev, "ptp_ref", >clk_ptp_ref);
+   if (ret) {
+   dev_dbg(dev, "clk_get_by_name(ptp_ref) failed: %d", ret);
+   goto err_free_clk_master_bus;
+   }
+
+   ret = clk_get_by_name(dev, "tx", >clk_tx);
+   if (ret) {
+   dev_dbg(dev, "clk_get_by_name(tx) failed: %d", ret);
+   goto err_free_clk_ptp_ref;
+   }
+
+   ret = clk_get_by_name(dev, "pclk", >clk_ck);
+   if (ret) {
+   dev_dbg(dev, "clk_get_by_name(pclk) failed: %d", ret);
+   goto err_free_clk_tx;
+   }
+
+   debug("%s: OK\n", __func__);
+   return 0;
+
+err_free_clk_tx:
+   clk_free(>clk_tx);
+err_free_clk_ptp_ref:
+   clk_free(>clk_ptp_ref);
+err_free_clk_master_bus:
+   clk_free(>clk_master_bus);
+err_probe:
+
+   debug("%s: returns %d\n", __func__, ret);
+   return ret;
+}
+
+static int eqos_remove_resources_imx(struct udevice *dev)
+{
+   struct eqos_priv *eqos = dev_get_priv(dev);
+
+   debug("%s(dev=%p):\n", __func__, dev);
+
+   clk_free(>clk_ck);
+   clk_free(>clk_tx);
+   clk_free(>clk_ptp_ref);
+   clk_free(>clk_master_bus);
+
+   debug("%s: OK\n", __func__);
+   return 0;

[PATCH v3 06/14] net: dwc_eth_qos: Set DMA_MODE SWR bit to reset the MAC

[Marek Vasut]

The driver currently only waits for DMA_MODE SWR bit to clear itself.
This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset
before IOMUX GPR[1] content is latched into the MAC and used. Without
the proper reset, the i.MX8M Plus MAC variant does not take the value
in IOMUX GPR[1] into account, which makes it impossible e.g. to switch
interface mode from RGMII to any other.

Since proper reset is desired in general to put the block into defined
state, always assert the DMA_MODE SWR bit before waiting for the bit
to clear itself.

Reviewed-by: Ramon Fried 
Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V2: Add RB from Ramon
V3: No change
---
 drivers/net/dwc_eth_qos.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9a5575e7b83..ec58697b311 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -761,6 +761,12 @@ static int eqos_start(struct udevice *dev)
 
eqos->reg_access_ok = true;
 
+   /*
+* Assert the SWR first, the actually reset the MAC and to latch in
+* e.g. i.MX8M Plus GPR[1] content, which selects interface mode.
+*/
+   setbits_le32(>dma_regs->mode, EQOS_DMA_MODE_SWR);
+
ret = wait_for_bit_le32(>dma_regs->mode,
EQOS_DMA_MODE_SWR, false,
eqos->config->swr_wait, false);
-- 
2.39.1

[PATCH v3 05/14] net: dwc_eth_qos: Staticize eqos_inval_buffer_tegra186()

[Marek Vasut]

This function is only used within the driver, staticize it.

Fixes: 149e80f74b6 ("net: dwc_eth_qos: public some functions")
Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V2: - New patch
V3: No change
---
 drivers/net/dwc_eth_qos.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index b97b3ea2db6..9a5575e7b83 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -108,7 +108,7 @@ void eqos_flush_desc_generic(void *desc)
flush_dcache_range(start, end);
 }
 
-void eqos_inval_buffer_tegra186(void *buf, size_t size)
+static void eqos_inval_buffer_tegra186(void *buf, size_t size)
 {
unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
-- 
2.39.1

[PATCH v3 04/14] net: dwc_eth_qos: Drop unused dm_gpio_free() on STM32

[Marek Vasut]

The dm_gpio_free() is never called, because for stm32, the phy_reset_gpio
pointer is never valid. This is because only tegra186 ever claims the
phy_reset_gpio, all other platforms use the PHY framework to reset the
PHY instead. Drop the dm_gpio_free() and dm_gpio_is_valid().

Reviewed-by: Ramon Fried 
Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V2: - Add RB from Ramon
- Mark eqos variable in eqos_remove_resources_stm32() with __maybe_unused
V3: No change
---
 drivers/net/dwc_eth_qos.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 00690b28ca6..b97b3ea2db6 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1493,7 +1493,7 @@ static int eqos_remove_resources_tegra186(struct udevice 
*dev)
 
 static int eqos_remove_resources_stm32(struct udevice *dev)
 {
-   struct eqos_priv *eqos = dev_get_priv(dev);
+   struct eqos_priv * __maybe_unused eqos = dev_get_priv(dev);
 
debug("%s(dev=%p):\n", __func__, dev);
 
@@ -1505,9 +1505,6 @@ static int eqos_remove_resources_stm32(struct udevice 
*dev)
clk_free(>clk_ck);
 #endif
 
-   if (dm_gpio_is_valid(>phy_reset_gpio))
-   dm_gpio_free(dev, >phy_reset_gpio);
-
debug("%s: OK\n", __func__);
return 0;
 }
-- 
2.39.1

[PATCH v3 03/14] net: dwc_eth_qos: Drop bogus return after goto

[Marek Vasut]

The return is never triggered due to the goto just above it.
Drop it. No functional change.

Reviewed-by: Ramon Fried 
Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V2: Add RB from Ramon
V3: No change
---
 drivers/net/dwc_eth_qos.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 0cae2cf2064..00690b28ca6 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1383,7 +1383,6 @@ static int eqos_probe_resources_tegra186(struct udevice 
*dev)
if (ret) {
pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
goto err_free_clk_rx;
-   return ret;
}
 
ret = clk_get_by_name(dev, "tx", >clk_tx);
-- 
2.39.1

[PATCH v3 02/14] net: Pull board_interface_eth_init() into common code

[Marek Vasut]

Move the board_interface_eth_init() into common ethernet uclass code,
since this function could be shared by multiple drivers.

Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V3: New patch
---
 drivers/net/dwc_eth_qos.c | 7 ---
 net/eth-uclass.c  | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 112deb546de..0cae2cf2064 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1412,13 +1412,6 @@ err_free_reset_eqos:
return ret;
 }
 
-/* board-specific Ethernet Interface initializations. */
-__weak int board_interface_eth_init(struct udevice *dev,
-   phy_interface_t interface_type)
-{
-   return 0;
-}
-
 static int eqos_probe_resources_stm32(struct udevice *dev)
 {
struct eqos_priv *eqos = dev_get_priv(dev);
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index b01a910938e..c393600fabc 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -49,6 +49,13 @@ struct eth_uclass_priv {
 /* eth_errno - This stores the most recent failure code from DM functions */
 static int eth_errno;
 
+/* board-specific Ethernet Interface initializations. */
+__weak int board_interface_eth_init(struct udevice *dev,
+   phy_interface_t interface_type)
+{
+   return 0;
+}
+
 static struct eth_uclass_priv *eth_get_uclass_priv(void)
 {
struct uclass *uc;
-- 
2.39.1

[PATCH v3 01/14] clk: imx8mp: Add EQoS MAC clock

[Marek Vasut]

Add clock for the DWMAC EQoS block. This is used among other things
to configure the MII clock via DM CLK.

Acked-by: Sean Anderson 
Signed-off-by: Marek Vasut 
---
Cc: "Ariel D'Alessandro" 
Cc: "NXP i.MX U-Boot Team" 
Cc: Andrey Zhizhikin 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Cc: Lukasz Majewski 
Cc: Marcel Ziswiler 
Cc: Marek Vasut 
Cc: Michael Trimarchi 
Cc: Peng Fan 
Cc: Ramon Fried 
Cc: Sean Anderson 
Cc: Stefano Babic 
Cc: Tim Harvey 
Cc: Tommaso Merciai 
Cc: u-boot@lists.denx.de
---
V2: Add AB from Sean
V3: No change
---
 drivers/clk/imx/clk-imx8mp.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index ffbc1d1ba9f..6dda0403e35 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -70,6 +70,14 @@ static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", 
"sys_pll1_160m", "sys_
 "sys_pll3_out", "audio_pll1_out", 
"video_pll1_out",
 "audio_pll2_out", "sys_pll1_133m", };
 
+static const char *imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", 
"sys_pll2_50m",
+"sys_pll2_100m", "sys_pll1_160m", 
"audio_pll1_out",
+"video_pll1_out", "clk_ext4", };
+
+static const char *imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", 
"sys_pll2_100m", "audio_pll1_out",
+  "clk_ext1", "clk_ext2", 
"clk_ext3",
+  "clk_ext4", 
"video_pll1_out", };
+
 static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", 
"sys_pll1_800m",
   "sys_pll2_500m", "sys_pll3_out", 
"sys_pll1_266m",
   "audio_pll2_out", "sys_pll1_100m", };
@@ -250,6 +258,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", 
imx8mp_dram_apb_sels, base + 0xa080));
clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, 
base + 0xa480));
clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, 
base + 0xa500));
+   clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", 
imx8mp_enet_qos_sels, base + 0xa880));
+   clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", 
imx8mp_enet_qos_timer_sels, base + 0xa900));
clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", 
imx8mp_enet_ref_sels, base + 0xa980));
clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", 
imx8mp_enet_timer_sels, base + 0xaa00));
clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", 
imx8mp_enet_phy_ref_sels, base + 0xaa80));
@@ -292,10 +302,13 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", 
base + 0x4180, 0));
clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", 
base + 0x4190, 0));
clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", 
base + 0x41a0, 0));
+   clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", 
base + 0x42c0, 0));
+   clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", 
"ipg_root", base + 0x42e0, 0));
clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", 
base + 0x42f0, 0));
clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", 
base + 0x4330, 0));
clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", 
base + 0x4340, 0));
clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", 
"enet_axi", base + 0x4400, 0));
+   clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", 
"sim_enet_root_clk", base + 0x43b0, 0));
clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", 
base + 0x4490, 0));
clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", 
base + 0x44a0, 0));
clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", 
base + 0x44b0, 0));
-- 
2.39.1

[PATCH v2 10/10] mtd: rawnand: brcmnand: fix OOB R/W with Hamming ECC

[Linus Walleij]

From: Álvaro Fernández Rojas 

Hamming ECC doesn't cover the OOB data, so reading or writing OOB shall
always be done without ECC enabled.
This is a problem when adding JFFS2 cleanmarkers to erased blocks. If JFFS2
clenmarkers are added to the OOB with ECC enabled, OOB bytes will be changed
from ff ff ff to 00 00 00, reporting incorrect ECC errors.

Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB 
NAND controller")
Signed-off-by: Álvaro Fernández Rojas 
Acked-by: Brian Norris 
Signed-off-by: Miquel Raynal 
Link: https://lore.kernel.org/linux-mtd/20210224080210.23686-1-nolt...@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij 
---
 drivers/mtd/nand/raw/brcmnand/brcmnand.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c 
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index b2ebcaf7a5bf..efbf9a3120a4 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -2515,6 +2515,12 @@ static int brcmnand_init_cs(struct brcmnand_host *host, 
ofnode dn)
ret = nand_register(0, mtd);
 #endif /* __UBOOT__ */
 
+   /* If OOB is written with ECC enabled it will cause ECC errors */
+   if (is_hamming_ecc(host->ctrl, >hwcfg)) {
+   chip->ecc.write_oob = brcmnand_write_oob_raw;
+   chip->ecc.read_oob = brcmnand_read_oob_raw;
+   }
+
return ret;
 }
 
-- 
2.39.1

[PATCH v2 09/10] mtd: rawnand: brcmnand: support v2.1-v2.2 controllers

[Linus Walleij]

From: Álvaro Fernández Rojas 

v2.1: tested on Netgear DGND3700v1 (BCM6368)
v2.2: tested on Netgear DGND3700v2 (BCM6362)

Signed-off-by: Álvaro Fernández Rojas 
Acked-by: Florian Fainelli 
Signed-off-by: Miquel Raynal 
Link: 
https://lore.kernel.org/linux-mtd/20200522121524.4161539-6-nolt...@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij 
---
 drivers/mtd/nand/raw/brcmnand/brcmnand.c | 85 +---
 1 file changed, 76 insertions(+), 9 deletions(-)

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c 
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 10a2e2c0f599..b2ebcaf7a5bf 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -217,6 +217,7 @@ struct brcmnand_controller {
const unsigned int  *block_sizes;
unsigned intmax_page_size;
const unsigned int  *page_sizes;
+   unsigned intpage_size_shift;
unsigned intmax_oob;
u32 features;
 
@@ -293,6 +294,36 @@ enum brcmnand_reg {
BRCMNAND_FC_BASE,
 };
 
+/* BRCMNAND v2.1-v2.2 */
+static const u16 brcmnand_regs_v21[] = {
+   [BRCMNAND_CMD_START]=  0x04,
+   [BRCMNAND_CMD_EXT_ADDRESS]  =  0x08,
+   [BRCMNAND_CMD_ADDRESS]  =  0x0c,
+   [BRCMNAND_INTFC_STATUS] =  0x5c,
+   [BRCMNAND_CS_SELECT]=  0x14,
+   [BRCMNAND_CS_XOR]   =  0x18,
+   [BRCMNAND_LL_OP]= 0,
+   [BRCMNAND_CS0_BASE] =  0x40,
+   [BRCMNAND_CS1_BASE] = 0,
+   [BRCMNAND_CORR_THRESHOLD]   = 0,
+   [BRCMNAND_CORR_THRESHOLD_EXT]   = 0,
+   [BRCMNAND_UNCORR_COUNT] = 0,
+   [BRCMNAND_CORR_COUNT]   = 0,
+   [BRCMNAND_CORR_EXT_ADDR]=  0x60,
+   [BRCMNAND_CORR_ADDR]=  0x64,
+   [BRCMNAND_UNCORR_EXT_ADDR]  =  0x68,
+   [BRCMNAND_UNCORR_ADDR]  =  0x6c,
+   [BRCMNAND_SEMAPHORE]=  0x50,
+   [BRCMNAND_ID]   =  0x54,
+   [BRCMNAND_ID_EXT]   = 0,
+   [BRCMNAND_LL_RDATA] = 0,
+   [BRCMNAND_OOB_READ_BASE]=  0x20,
+   [BRCMNAND_OOB_READ_10_BASE] = 0,
+   [BRCMNAND_OOB_WRITE_BASE]   =  0x30,
+   [BRCMNAND_OOB_WRITE_10_BASE]= 0,
+   [BRCMNAND_FC_BASE]  = 0x200,
+};
+
 /* BRCMNAND v3.3-v4.0 */
 static const u16 brcmnand_regs_v33[] = {
[BRCMNAND_CMD_START]=  0x04,
@@ -491,6 +522,9 @@ enum {
CFG_BUS_WIDTH   = BIT(CFG_BUS_WIDTH_SHIFT),
CFG_DEVICE_SIZE_SHIFT   = 24,
 
+   /* Only for v2.1 */
+   CFG_PAGE_SIZE_SHIFT_v2_1= 30,
+
/* Only for pre-v7.1 (with no CFG_EXT register) */
CFG_PAGE_SIZE_SHIFT = 20,
CFG_BLK_SIZE_SHIFT  = 28,
@@ -526,12 +560,16 @@ static int brcmnand_revision_init(struct 
brcmnand_controller *ctrl)
 {
static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 
1024, 2048, 0 };
static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 
1024, 2048, 0 };
+   static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 
0 };
+   static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 
0 };
+   static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
+   static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
 
ctrl->nand_version = nand_readreg(ctrl, 0) & 0x;
 
-   /* Only support v4.0+? */
-   if (ctrl->nand_version < 0x0400) {
+   /* Only support v2.1+ */
+   if (ctrl->nand_version < 0x0201) {
dev_err(ctrl->dev, "version %#x not supported\n",
ctrl->nand_version);
return -ENODEV;
@@ -548,6 +586,8 @@ static int brcmnand_revision_init(struct 
brcmnand_controller *ctrl)
ctrl->reg_offsets = brcmnand_regs_v50;
else if (ctrl->nand_version >= 0x0303)
ctrl->reg_offsets = brcmnand_regs_v33;
+   else if (ctrl->nand_version >= 0x0201)
+   ctrl->reg_offsets = brcmnand_regs_v21;
 
/* Chip-select stride */
if (ctrl->nand_version >= 0x0701)
@@ -573,14 +613,32 @@ static int brcmnand_revision_init(struct 
brcmnand_controller *ctrl)
ctrl->max_page_size = 16 * 1024;
ctrl->max_block_size = 2 * 1024 * 1024;
} else {
-   ctrl->page_sizes = page_sizes_v3_4;
+   if (ctrl->nand_version >= 0x0304)
+   ctrl->page_sizes = page_sizes_v3_4;
+   else if (ctrl->nand_version >= 0x0202)
+   ctrl->page_sizes = page_sizes_v2_2;
+   else
+   ctrl->page_sizes = 

[PATCH v2 07/10] mtd: rawnand: brcmnand: fix CS0 layout

[Linus Walleij]

From: Álvaro Fernández Rojas 

Only v3.3-v5.0 have a different CS0 layout.
Controllers before v3.3 use the same layout for every CS.

Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB 
NAND controller")
Signed-off-by: Álvaro Fernández Rojas 
Acked-by: Florian Fainelli 
Signed-off-by: Miquel Raynal 
Link: 
https://lore.kernel.org/linux-mtd/20200522121524.4161539-3-nolt...@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij 
---
 drivers/mtd/nand/raw/brcmnand/brcmnand.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c 
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index ee7c3a21602e..1ea9091e6497 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -561,8 +561,9 @@ static int brcmnand_revision_init(struct 
brcmnand_controller *ctrl)
} else {
ctrl->cs_offsets = brcmnand_cs_offsets;
 
-   /* v5.0 and earlier has a different CS0 offset layout */
-   if (ctrl->nand_version <= 0x0500)
+   /* v3.3-5.0 have a different CS0 offset layout */
+   if (ctrl->nand_version >= 0x0303 &&
+   ctrl->nand_version <= 0x0500)
ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
}
 
-- 
2.39.1

[PATCH v2 08/10] mtd: rawnand: brcmnand: rename page sizes

[Linus Walleij]

From: Álvaro Fernández Rojas 

Current pages sizes apply to controllers after v3.4

Signed-off-by: Álvaro Fernández Rojas 
Acked-by: Florian Fainelli 
Signed-off-by: Miquel Raynal 
Link: 
https://lore.kernel.org/linux-mtd/20200522121524.4161539-4-nolt...@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij 
---
 drivers/mtd/nand/raw/brcmnand/brcmnand.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c 
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 1ea9091e6497..10a2e2c0f599 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -526,7 +526,7 @@ static int brcmnand_revision_init(struct 
brcmnand_controller *ctrl)
 {
static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 
1024, 2048, 0 };
static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 
1024, 2048, 0 };
-   static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
+   static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 
0 };
 
ctrl->nand_version = nand_readreg(ctrl, 0) & 0x;
 
@@ -573,7 +573,7 @@ static int brcmnand_revision_init(struct 
brcmnand_controller *ctrl)
ctrl->max_page_size = 16 * 1024;
ctrl->max_block_size = 2 * 1024 * 1024;
} else {
-   ctrl->page_sizes = page_sizes;
+   ctrl->page_sizes = page_sizes_v3_4;
if (ctrl->nand_version >= 0x0600)
ctrl->block_sizes = block_sizes_v6;
else
-- 
2.39.1

[PATCH v2 06/10] mtd: rawnand: brcmnand: rename v4 registers

[Linus Walleij]

From: Álvaro Fernández Rojas 

These registers are also used on v3.3.

Signed-off-by: Álvaro Fernández Rojas 
Reviewed-by: Miquel Raynal 
Acked-by: Florian Fainelli 
Signed-off-by: Miquel Raynal 
Link: 
https://lore.kernel.org/linux-mtd/20200522121524.4161539-2-nolt...@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij 
---
 drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c 
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 5d3fb460d89a..ee7c3a21602e 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -293,8 +293,8 @@ enum brcmnand_reg {
BRCMNAND_FC_BASE,
 };
 
-/* BRCMNAND v4.0 */
-static const u16 brcmnand_regs_v40[] = {
+/* BRCMNAND v3.3-v4.0 */
+static const u16 brcmnand_regs_v33[] = {
[BRCMNAND_CMD_START]=  0x04,
[BRCMNAND_CMD_EXT_ADDRESS]  =  0x08,
[BRCMNAND_CMD_ADDRESS]  =  0x0c,
@@ -546,8 +546,8 @@ static int brcmnand_revision_init(struct 
brcmnand_controller *ctrl)
ctrl->reg_offsets = brcmnand_regs_v60;
else if (ctrl->nand_version >= 0x0500)
ctrl->reg_offsets = brcmnand_regs_v50;
-   else if (ctrl->nand_version >= 0x0400)
-   ctrl->reg_offsets = brcmnand_regs_v40;
+   else if (ctrl->nand_version >= 0x0303)
+   ctrl->reg_offsets = brcmnand_regs_v33;
 
/* Chip-select stride */
if (ctrl->nand_version >= 0x0701)
-- 
2.39.1

[PATCH v2 05/10] mtd: rawnand: brcmnand: correctly verify erased pages

[Linus Walleij]

From: Álvaro Fernández Rojas 

The current code checks that the whole OOB area is erased.
This is a problem when JFFS2 cleanmarkers are added to the OOB, since it will
fail due to the usable OOB bytes not being 0xff.
Correct this by only checking that data and ECC bytes aren't 0xff.

Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips")
Signed-off-by: Álvaro Fernández Rojas 
Signed-off-by: Miquel Raynal 
Link: 
https://lore.kernel.org/linux-mtd/20200512082451.771212-1-nolt...@gmail.com
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij 
---
 drivers/mtd/nand/raw/brcmnand/brcmnand.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c 
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index a934373a2992..5d3fb460d89a 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -1777,11 +1777,12 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, 
struct nand_chip *chip,
 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
  struct nand_chip *chip, void *buf, u64 addr)
 {
-   int i, sas;
-   void *oob = chip->oob_poi;
+   struct mtd_oob_region ecc;
+   int i;
int bitflips = 0;
int page = addr >> chip->page_shift;
int ret;
+   void *ecc_bytes;
void *ecc_chunk;
 
if (!buf) {
@@ -1794,18 +1795,20 @@ static int brcmstb_nand_verify_erased_page(struct 
mtd_info *mtd,
chip->pagebuf = -1;
}
 
-   sas = mtd->oobsize / chip->ecc.steps;
-
/* read without ecc for verification */
ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
if (ret)
return ret;
 
-   for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
+   for (i = 0; i < chip->ecc.steps; i++) {
ecc_chunk = buf + chip->ecc.size * i;
-   ret = nand_check_erased_ecc_chunk(ecc_chunk,
- chip->ecc.size,
- oob, sas, NULL, 0,
+
+   mtd_ooblayout_ecc(mtd, i, );
+   ecc_bytes = chip->oob_poi + ecc.offset;
+
+   ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
+ ecc_bytes, ecc.length,
+ NULL, 0,
  chip->ecc.strength);
if (ret < 0)
return ret;
-- 
2.39.1

[PATCH v2 04/10] mtd: nand: brcmnand: Add support for flash-dma v0

[Linus Walleij]

From: Kamal Dasu 

This change adds support for flash dma v0.0.

Signed-off-by: Kamal Dasu 
Signed-off-by: Miquel Raynal 
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij 
---
 drivers/mtd/nand/raw/brcmnand/brcmnand.c | 21 +++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c 
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 0402cb06a74b..a934373a2992 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -120,6 +120,18 @@ enum flash_dma_reg {
 };
 
 #ifndef __UBOOT__
+/* flash_dma registers v0*/
+static const u16 flash_dma_regs_v0[] = {
+   [FLASH_DMA_REVISION]= 0x00,
+   [FLASH_DMA_FIRST_DESC]  = 0x04,
+   [FLASH_DMA_CTRL]= 0x08,
+   [FLASH_DMA_MODE]= 0x0c,
+   [FLASH_DMA_STATUS]  = 0x10,
+   [FLASH_DMA_INTERRUPT_DESC]  = 0x14,
+   [FLASH_DMA_ERROR_STATUS]= 0x18,
+   [FLASH_DMA_CURRENT_DESC]= 0x1c,
+};
+
 /* flash_dma registers v1*/
 static const u16 flash_dma_regs_v1[] = {
[FLASH_DMA_REVISION]= 0x00,
@@ -614,6 +626,8 @@ static void brcmnand_flash_dma_revision_init(struct 
brcmnand_controller *ctrl)
/* flash_dma register offsets */
if (ctrl->nand_version >= 0x0703)
ctrl->flash_dma_offsets = flash_dma_regs_v4;
+   else if (ctrl->nand_version == 0x0602)
+   ctrl->flash_dma_offsets = flash_dma_regs_v0;
else
ctrl->flash_dma_offsets = flash_dma_regs_v1;
 }
@@ -1645,8 +1659,11 @@ static void brcmnand_dma_run(struct brcmnand_host *host, 
dma_addr_t desc)
 
flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
(void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
-   flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
-   (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
+   if (ctrl->nand_version > 0x0602) {
+   flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT,
+upper_32_bits(desc));
+   (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
+   }
 
/* Start FLASH_DMA engine */
ctrl->dma_pending = true;
-- 
2.39.1

[PATCH v2 03/10] mtd: rawnand: brcmnand: Fix ecc chunk calculation for erased page bitfips

[Linus Walleij]

From: Claire Lin 

In brcmstb_nand_verify_erased_page(), the ECC chunk pointer calculation
while correcting erased page bitflips is wrong, fix it.

Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips")
Signed-off-by: Claire Lin 
Reviewed-by: Ray Jui 
Signed-off-by: Kamal Dasu 
Signed-off-by: Miquel Raynal 
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij 
---
 drivers/mtd/nand/raw/brcmnand/brcmnand.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c 
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 170aece0aa79..0402cb06a74b 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -1765,6 +1765,7 @@ static int brcmstb_nand_verify_erased_page(struct 
mtd_info *mtd,
int bitflips = 0;
int page = addr >> chip->page_shift;
int ret;
+   void *ecc_chunk;
 
if (!buf) {
 #ifndef __UBOOT__
@@ -1784,7 +1785,9 @@ static int brcmstb_nand_verify_erased_page(struct 
mtd_info *mtd,
return ret;
 
for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
-   ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
+   ecc_chunk = buf + chip->ecc.size * i;
+   ret = nand_check_erased_ecc_chunk(ecc_chunk,
+ chip->ecc.size,
  oob, sas, NULL, 0,
  chip->ecc.strength);
if (ret < 0)
-- 
2.39.1

[PATCH v2 02/10] mtd: rawnand: brcmnand: Add support for v7.3 controller

[Linus Walleij]

From: Kamal Dasu 

This change adds support for brcm NAND v7.3 controller. This controller
uses a newer version of flash_dma engine and change mostly implements
these differences.

Signed-off-by: Kamal Dasu 
Signed-off-by: Miquel Raynal 
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij 
---
 drivers/mtd/nand/raw/brcmnand/brcmnand.c | 106 ++-
 1 file changed, 84 insertions(+), 22 deletions(-)

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c 
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 571f1c795da0..170aece0aa79 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -86,6 +86,12 @@ struct brcm_nand_dma_desc {
 #define FLASH_DMA_ECC_ERROR(1 << 8)
 #define FLASH_DMA_CORR_ERROR   (1 << 9)
 
+/* Bitfields for DMA_MODE */
+#define FLASH_DMA_MODE_STOP_ON_ERROR   BIT(1) /* stop in Uncorr ECC error */
+#define FLASH_DMA_MODE_MODEBIT(0) /* link list */
+#define FLASH_DMA_MODE_MASK(FLASH_DMA_MODE_STOP_ON_ERROR | \
+   FLASH_DMA_MODE_MODE)
+
 /* 512B flash cache in the NAND controller HW */
 #define FC_SHIFT   9U
 #define FC_BYTES   512U
@@ -98,6 +104,53 @@ struct brcm_nand_dma_desc {
 #define NAND_CTRL_RDY  (INTFC_CTLR_READY | INTFC_FLASH_READY)
 #define NAND_POLL_STATUS_TIMEOUT_MS100
 
+/* flash_dma registers */
+enum flash_dma_reg {
+   FLASH_DMA_REVISION = 0,
+   FLASH_DMA_FIRST_DESC,
+   FLASH_DMA_FIRST_DESC_EXT,
+   FLASH_DMA_CTRL,
+   FLASH_DMA_MODE,
+   FLASH_DMA_STATUS,
+   FLASH_DMA_INTERRUPT_DESC,
+   FLASH_DMA_INTERRUPT_DESC_EXT,
+   FLASH_DMA_ERROR_STATUS,
+   FLASH_DMA_CURRENT_DESC,
+   FLASH_DMA_CURRENT_DESC_EXT,
+};
+
+#ifndef __UBOOT__
+/* flash_dma registers v1*/
+static const u16 flash_dma_regs_v1[] = {
+   [FLASH_DMA_REVISION]= 0x00,
+   [FLASH_DMA_FIRST_DESC]  = 0x04,
+   [FLASH_DMA_FIRST_DESC_EXT]  = 0x08,
+   [FLASH_DMA_CTRL]= 0x0c,
+   [FLASH_DMA_MODE]= 0x10,
+   [FLASH_DMA_STATUS]  = 0x14,
+   [FLASH_DMA_INTERRUPT_DESC]  = 0x18,
+   [FLASH_DMA_INTERRUPT_DESC_EXT]  = 0x1c,
+   [FLASH_DMA_ERROR_STATUS]= 0x20,
+   [FLASH_DMA_CURRENT_DESC]= 0x24,
+   [FLASH_DMA_CURRENT_DESC_EXT]= 0x28,
+};
+
+/* flash_dma registers v4 */
+static const u16 flash_dma_regs_v4[] = {
+   [FLASH_DMA_REVISION]= 0x00,
+   [FLASH_DMA_FIRST_DESC]  = 0x08,
+   [FLASH_DMA_FIRST_DESC_EXT]  = 0x0c,
+   [FLASH_DMA_CTRL]= 0x10,
+   [FLASH_DMA_MODE]= 0x14,
+   [FLASH_DMA_STATUS]  = 0x18,
+   [FLASH_DMA_INTERRUPT_DESC]  = 0x20,
+   [FLASH_DMA_INTERRUPT_DESC_EXT]  = 0x24,
+   [FLASH_DMA_ERROR_STATUS]= 0x28,
+   [FLASH_DMA_CURRENT_DESC]= 0x30,
+   [FLASH_DMA_CURRENT_DESC_EXT]= 0x34,
+};
+#endif /* __UBOOT__ */
+
 /* Controller feature flags */
 enum {
BRCMNAND_HAS_1K_SECTORS = BIT(0),
@@ -135,6 +188,8 @@ struct brcmnand_controller {
/* List of NAND hosts (one for each chip-select) */
struct list_head host_list;
 
+   /* flash_dma reg */
+   const u16   *flash_dma_offsets;
struct brcm_nand_dma_desc *dma_desc;
dma_addr_t  dma_pa;
 
@@ -473,7 +528,7 @@ static int brcmnand_revision_init(struct 
brcmnand_controller *ctrl)
/* Register offsets */
if (ctrl->nand_version >= 0x0702)
ctrl->reg_offsets = brcmnand_regs_v72;
-   else if (ctrl->nand_version >= 0x0701)
+   else if (ctrl->nand_version == 0x0701)
ctrl->reg_offsets = brcmnand_regs_v71;
else if (ctrl->nand_version >= 0x0600)
ctrl->reg_offsets = brcmnand_regs_v60;
@@ -518,7 +573,7 @@ static int brcmnand_revision_init(struct 
brcmnand_controller *ctrl)
}
 
/* Maximum spare area sector size (per 512B) */
-   if (ctrl->nand_version >= 0x0702)
+   if (ctrl->nand_version == 0x0702)
ctrl->max_oob = 128;
else if (ctrl->nand_version >= 0x0600)
ctrl->max_oob = 64;
@@ -553,6 +608,17 @@ static int brcmnand_revision_init(struct 
brcmnand_controller *ctrl)
return 0;
 }
 
+#ifndef __UBOOT__
+static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl)
+{
+   /* flash_dma register offsets */
+   if (ctrl->nand_version >= 0x0703)
+   ctrl->flash_dma_offsets = flash_dma_regs_v4;
+   else
+   ctrl->flash_dma_offsets = flash_dma_regs_v1;
+}
+#endif /* __UBOOT__ */
+
 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
enum brcmnand_reg reg)
 {
@@ -675,7 +741,7 @@ static void brcmnand_wr_corr_thresh(struct brcmnand_host 
*host, u8 val)
enum brcmnand_reg 

[PATCH v2 01/10] mtd: rawnand: brcmnand: Refactored code to introduce helper functions

[Linus Walleij]

From: Kamal Dasu 

Refactored NAND ECC and CMD address configuration code to use helper
functions.

Signed-off-by: Kamal Dasu 
Signed-off-by: Miquel Raynal 
[Ported to U-Boot from the Linux kernel]
Signed-off-by: Linus Walleij 
---
 drivers/mtd/nand/raw/brcmnand/brcmnand.c | 100 ++-
 1 file changed, 62 insertions(+), 38 deletions(-)

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c 
b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index 74c9348f7fc4..571f1c795da0 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -595,6 +595,54 @@ static inline void brcmnand_write_fc(struct 
brcmnand_controller *ctrl,
__raw_writel(val, ctrl->nand_fc + word * 4);
 }
 
+static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl)
+{
+
+   /* Clear error addresses */
+   brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
+   brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
+   brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
+   brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
+}
+
+static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl)
+{
+   u64 err_addr;
+
+   err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR);
+   err_addr |= ((u64)(brcmnand_read_reg(ctrl,
+BRCMNAND_UNCORR_EXT_ADDR)
+& 0x) << 32);
+
+   return err_addr;
+}
+
+static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl)
+{
+   u64 err_addr;
+
+   err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR);
+   err_addr |= ((u64)(brcmnand_read_reg(ctrl,
+BRCMNAND_CORR_EXT_ADDR)
+& 0x) << 32);
+
+   return err_addr;
+}
+
+static void brcmnand_set_cmd_addr(struct mtd_info *mtd, u64 addr)
+{
+   struct nand_chip *chip =  mtd_to_nand(mtd);
+   struct brcmnand_host *host = nand_get_controller_data(chip);
+   struct brcmnand_controller *ctrl = host->ctrl;
+
+   brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
+  (host->cs << 16) | ((addr >> 32) & 0x));
+   (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
+   brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
+  lower_32_bits(addr));
+   (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
+}
+
 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
 enum brcmnand_cs_reg reg)
 {
@@ -1190,9 +1238,12 @@ static void brcmnand_send_cmd(struct brcmnand_host 
*host, int cmd)
 {
struct brcmnand_controller *ctrl = host->ctrl;
int ret;
+   u64 cmd_addr;
+
+   cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
+
+   dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr);
 
-   dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
-   brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
BUG_ON(ctrl->cmd_pending != 0);
ctrl->cmd_pending = cmd;
 
@@ -1365,12 +1416,7 @@ static void brcmnand_cmdfunc(struct mtd_info *mtd, 
unsigned command,
if (!native_cmd)
return;
 
-   brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
-   (host->cs << 16) | ((addr >> 32) & 0x));
-   (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
-   brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
-   (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
-
+   brcmnand_set_cmd_addr(mtd, addr);
brcmnand_send_cmd(host, native_cmd);
brcmnand_waitfunc(mtd, chip);
 
@@ -1600,20 +1646,10 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, 
struct nand_chip *chip,
struct brcmnand_controller *ctrl = host->ctrl;
int i, j, ret = 0;
 
-   /* Clear error addresses */
-   brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
-   brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
-   brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
-   brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
-
-   brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
-   (host->cs << 16) | ((addr >> 32) & 0x));
-   (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
+   brcmnand_clear_ecc_addr(ctrl);
 
for (i = 0; i < trans; i++, addr += FC_BYTES) {
-   brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
-  lower_32_bits(addr));
-   (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
+   brcmnand_set_cmd_addr(mtd, addr);
/* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
brcmnand_send_cmd(host, CMD_PAGE_READ);
brcmnand_waitfunc(mtd, chip);
@@ -1633,21 +1669,15 @@ static int brcmnand_read_by_pio(struct 

[PATCH v2 00/10] Backport BRCMNAND changes from Linux

[Linus Walleij]

Hunting down a bug on my system I took to back-porting
all reasonable changes from the Linux brcmnand driver that
were not yet in the U-Boot derivative.

I noticed that a simple diff -ur between brcmnand.c
between the file in Linux and U-Boot was possible to see
what differs. Combining this with some git log --oneline
manual comparison, fuzzing and manual intervention I
backported a set of relevant patches from Linux that
compiles and WorksForMe(TM).

The diff between Linux and U-Boot is much smaller after
this, the main missing part are subsystem cosmetics
changes and the EDU DMA mode support.

This was as much as I could bite off in one go.

All patches countersigned-off and marked as [backported].

ChangeLog v1->v2:
- Drop the patch to use the new OOB data layout helpers
  "mtd: nand: brcm: switch to mtd_ooblayout_ops"
- Drop all patches depending on the previous patch, in
  total 4 patches.

Claire Lin (1):
  mtd: rawnand: brcmnand: Fix ecc chunk calculation for erased page
bitfips

Kamal Dasu (3):
  mtd: rawnand: brcmnand: Refactored code to introduce helper functions
  mtd: rawnand: brcmnand: Add support for v7.3 controller
  mtd: nand: brcmnand: Add support for flash-dma v0

Álvaro Fernández Rojas (6):
  mtd: rawnand: brcmnand: correctly verify erased pages
  mtd: rawnand: brcmnand: rename v4 registers
  mtd: rawnand: brcmnand: fix CS0 layout
  mtd: rawnand: brcmnand: rename page sizes
  mtd: rawnand: brcmnand: support v2.1-v2.2 controllers
  mtd: rawnand: brcmnand: fix OOB R/W with Hamming ECC

 drivers/mtd/nand/raw/brcmnand/brcmnand.c | 353 +--
 1 file changed, 268 insertions(+), 85 deletions(-)

-- 
2.39.1

Re: [PATCH v2] riscv: cancel the limitation that NR_CPUS is less than or equal to 32

[Xiang W]

在 2023-02-10星期五的 07:25 +，Leo Liang写道：
> Hi Xiang,
> 
> On Fri, Feb 03, 2023 at 03:24:37PM +0100, David Abdurachmanov wrote:
> > On Mon, Jan 3, 2022 at 1:13 PM Leo Liang  wrote:
> > > 
> > > On Thu, Dec 30, 2021 at 01:55:15AM +0800, Xiang W wrote:
> > > > 在 2021-12-29星期三的 17:23 +0800，Leo Liang写道：
> > > > > Hi Xiang,
> > > > > On Wed, Dec 22, 2021 at 07:32:53AM +0800, Xiang W wrote:
> > > > > > Various specifications of riscv allow the number of hart to be
> > > > > > greater than 32. The limit of 32 is determined by
> > > > > > gd->arch.available_harts. We can eliminate this limitation through
> > > > > > bitmaps. Currently, the number of hart is limited to 4095, and 4095
> > > > > > is the limit of the RISC-V Advanced Core Local Interruptor
> > > > > > Specification.
> > > > > > 
> > > > > > Test on sifive unmatched.
> > > > > > 
> > > > > > Signed-off-by: Xiang W 
> > > > > > ---
> > > > > > Changes since v1:
> > > > > > 
> > > > > > * When NR_CPUS is very large, the value of GD_AVAILABLE_HARTS will
> > > > > >   overflow the immediate range of ld/lw. This patch fixes this
> > > > > >   problem
> > > > > > 
> > > > > >  arch/riscv/Kconfig   |  4 ++--
> > > > > >  arch/riscv/cpu/start.S   | 21 -
> > > > > >  arch/riscv/include/asm/global_data.h |  4 +++-
> > > > > >  arch/riscv/lib/smp.c |  2 +-
> > > > > >  4 files changed, 22 insertions(+), 9 deletions(-)
> > > > > > 
> > 
> > I noticed that this has never landed in U-Boot. Was this forgotten or
> > dropped for some reason (couldn't find anything)?
> > 
> > The current limit on the Linux kernel side is 512. The default on
> > 64-bit (riscv64) is 64.
> > 
> > david
> 
> The patch seems to cause some CI error (timeout on QEMU).
> (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15076)
> Could you take a look at it if you have time?
> 
> Best regards,
> Leo

sorry! I missing a bug. There is an error in calculating the starting address
of available_harts. The patch for start.S needs to be updated.

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 76850ec9be..92f3b78f29 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -166,11 +166,22 @@ wait_for_gd_init:
mv  gp, s0
 
/* register available harts in the available_harts mask */
-   li  t1, 1
-   sll t1, t1, tp
-   LREGt2, GD_AVAILABLE_HARTS(gp)
-   or  t2, t2, t1
-   SREGt2, GD_AVAILABLE_HARTS(gp)
+   li  t1, GD_AVAILABLE_HARTS
+   add t1, t1, gp
+#if defined(CONFIG_ARCH_RV64I)
+   srlit2, tp, 6
+   sllit2, t2, 3
+#elif defined(CONFIG_ARCH_RV32I)
+   srlit2, tp, 5
+   sllit2, t2, 2
+#endif
+   add t1, t1, t2
+   LREGt2, 0(t1)
+   li  t3, 1
+   sll t3, t3, tp
+   or  t2, t2, t3
+   SREGt2, 0(t1)
 
amoswap.w.rl zero, zero, 0(t0)

The mailing list cannot receive my mail, please help to update

Re: [PATCH 1/6] nvmem: core: add nvmem_dev_size() helper

[kernel test robot]

Hi Rafał,

I love your patch! Perhaps something to improve:

[auto build test WARNING on next-20230110]
[also build test WARNING on v6.2-rc7]
[cannot apply to robh/for-next shawnguo/for-next mtd/mtd/next mtd/mtd/fixes 
linus/master v6.2-rc3 v6.2-rc2 v6.2-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:
https://github.com/intel-lab-lkp/linux/commits/Rafa-Mi-ecki/nvmem-core-allow-read_post_process-callbacks-to-adjust-data-length/20230110-185915
patch link:
https://lore.kernel.org/r/20230110105425.13188-1-zajec5%40gmail.com
patch subject: [PATCH 1/6] nvmem: core: add nvmem_dev_size() helper
config: m68k-allyesconfig 
(https://download.01.org/0day-ci/archive/20230211/202302112138.xodxy4yf-...@intel.com/config)
compiler: m68k-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://github.com/intel-lab-lkp/linux/commit/4d5cc61f8d02a82344468f172a852ffc56cf0d5c
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review 
Rafa-Mi-ecki/nvmem-core-allow-read_post_process-callbacks-to-adjust-data-length/20230110-185915
git checkout 4d5cc61f8d02a82344468f172a852ffc56cf0d5c
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 
O=build_dir ARCH=m68k olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 
O=build_dir ARCH=m68k SHELL=/bin/bash drivers/nvmem/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot 
| Link: 
https://lore.kernel.org/oe-kbuild-all/202302112138.xodxy4yf-...@intel.com/

All warnings (new ones prefixed by >>):

   In file included from drivers/nvmem/core.c:16:
>> include/linux/nvmem-consumer.h:81:1: warning: type qualifiers ignored on 
>> function return type [-Wignored-qualifiers]
  81 | const size_t nvmem_dev_size(struct nvmem_device *nvmem);
 | ^
>> drivers/nvmem/core.c:2070:1: warning: type qualifiers ignored on function 
>> return type [-Wignored-qualifiers]
2070 | const size_t nvmem_dev_size(struct nvmem_device *nvmem)
 | ^
--
   In file included from drivers/nvmem/brcm_nvram.c:10:
>> include/linux/nvmem-consumer.h:81:1: warning: type qualifiers ignored on 
>> function return type [-Wignored-qualifiers]
  81 | const size_t nvmem_dev_size(struct nvmem_device *nvmem);
 | ^


vim +81 include/linux/nvmem-consumer.h

49  
50  /* Cell based interface */
51  struct nvmem_cell *nvmem_cell_get(struct device *dev, const char *id);
52  struct nvmem_cell *devm_nvmem_cell_get(struct device *dev, const char 
*id);
53  void nvmem_cell_put(struct nvmem_cell *cell);
54  void devm_nvmem_cell_put(struct device *dev, struct nvmem_cell *cell);
55  void *nvmem_cell_read(struct nvmem_cell *cell, size_t *len);
56  int nvmem_cell_write(struct nvmem_cell *cell, void *buf, size_t len);
57  int nvmem_cell_read_u8(struct device *dev, const char *cell_id, u8 
*val);
58  int nvmem_cell_read_u16(struct device *dev, const char *cell_id, u16 
*val);
59  int nvmem_cell_read_u32(struct device *dev, const char *cell_id, u32 
*val);
60  int nvmem_cell_read_u64(struct device *dev, const char *cell_id, u64 
*val);
61  int nvmem_cell_read_variable_le_u32(struct device *dev, const char 
*cell_id,
62  u32 *val);
63  int nvmem_cell_read_variable_le_u64(struct device *dev, const char 
*cell_id,
64  u64 *val);
65  
66  /* direct nvmem device read/write interface */
67  struct nvmem_device *nvmem_device_get(struct device *dev, const char 
*name);
68  struct nvmem_device *devm_nvmem_device_get(struct device *dev,
69 const char *name);
70  void nvmem_device_put(struct nvmem_device *nvmem);
71  void devm_nvmem_device_put(struct device *dev, struct nvmem_device 
*nvmem);
72  int nvmem_device_read(struct nvmem_device *nvmem, unsigned int offset,
73size_t bytes, void *buf);
74  int nvmem_device_write(struct nvmem_device *nvmem, unsigned int offset,
75 size_t bytes, void *buf);
76  ssize_t nvmem_device_cell_read(struct nvmem_device *nvmem,
77 struct nvmem_cell_info *info, void *buf);
78  int nvmem_device_cell_write(struct nvmem_device *nvmem,
79  struct nvmem_cell_info *info, void *buf);
80  
  > 81  const size_t nvmem_dev

Dependency issue on SPL_MXC_OCOTP

[Jean-Marie Lemetayer]

TLDR: In the configuration SPL_MXC_OCOTP, the dependency on SPL_MISC
should be replaced by SPL_DRIVERS_MISC.

Hi folks,

I was creating a new imx6 board with an SPL and without enabling the
"driver model for SPL" to keep a pretty simple SPL.

Then I wanted to enable the secure boot, and so the IMX_HAB option,
which needs at compile time the "fuse_read" function.

This function is provided by the "mxc_ocotp" driver (in the misc
section). This driver is totally not "driver model" oriented. It can
be enabled for regular builds and SPL builds using the (SPL_)MXC_OCOTP
option.

For the regular build, MXC_OCOTP does not have any dependency (except
for the arch dependency), so no DM dependency here. But for the SPL
build, the SPL_MXC_OCOTP needs the SPL_MISC option which is directly
linked to the SPL_DM option.

I think this is just a typo and this should be only dependent on the
"support of misc drivers in the SPL" so the SPL_DRIVERS_MISC option.

Am I right ? If someone confirms this point, I will propose a patch.

Best regards,
Jean-Marie

[PATCH] socfpga: fix the serial console on DE1-SoC

[Jade Lovelace]

Previously, the TX LED would flash but nothing would appear on the
serial port, and the board would appear dead with a build of the
socfpga_cyclone5_defconfig. I have verified that adding the frequency to
the uart will fix the serial console on my board.

Thanks to @ehoffman on the Rocketboards forum:
https://forum.rocketboards.org/t/cyclonev-programming-fpga-from-u-boot/2230/30

Signed-off-by: Jade Lovelace 
---

 arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts 
b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
index ff1e61e0cb..b71496bfb5 100644
--- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -75,6 +75,7 @@
 };
 
  {
+   clock-frequency = <1>;
u-boot,dm-pre-reloc;
 };
 
-- 
2.39.1

[PATCH] doc: board: bcm7xxx: Convert to reStructuredText format

[Thomas Fitzsimmons]

Convert the documentation for the Broadcom BCM7445 and BCM7260 boards
to reStructuredText format and add the new filename to
doc/board/broadcom/index.rst.
---
 doc/README.bcm7xxx | 156 ---
 doc/board/broadcom/bcm7xxx.rst | 186 +
 doc/board/broadcom/index.rst   |   1 +
 3 files changed, 187 insertions(+), 156 deletions(-)
 delete mode 100644 doc/README.bcm7xxx
 create mode 100644 doc/board/broadcom/bcm7xxx.rst

diff --git a/doc/README.bcm7xxx b/doc/README.bcm7xxx
deleted file mode 100644
index 6839da5f97..00
--- a/doc/README.bcm7xxx
+++ /dev/null
@@ -1,156 +0,0 @@
-Summary
-===
-
-This document describes how to use U-Boot on the Broadcom 7445 SoC, as
-a third stage bootloader loaded by Broadcom's BOLT bootloader.
-
-BOLT loads U-Boot as a generic ELF binary.  Some U-Boot features such
-as networking are not yet available but other important features are,
-including:
-
-   - ext4 file system traversal
-
-   - support for loading FIT images
-
-   - advanced scripting
-
-   - support for FIT-provided DTBs instead of relying on the
- BOLT-provided DTB
-
-A customized version of this port has been used in production.  The
-same approach may work on other BCM7xxx boards, with some
-configuration adjustments and memory layout experimentation.
-
-Build
-=
-
-make bcm7445_defconfig
-make
-${CROSS_COMPILE}strip u-boot
-
-Run
-===
-
-To tell U-Boot which serial port to use for its console, set the
-"stdout-path" property in the "/chosen" node of the BOLT-generated
-device tree.  For example:
-
-BOLT> dt add prop chosen stdout-path s serial0:115200n8
-
-Flash the u-boot binary into board storage, then invoke it from BOLT.
-For example:
-
-BOLT> boot -bsu -elf flash0.u-boot1
-
-This port assumes that I-cache and D-cache are already enabled when
-U-Boot is entered.
-
-Flattened Image Tree Support
-
-
-What follows is an example FIT image source file.  Build it with:
-
-mkimage -f image.its image.itb
-
-Booting the resulting image.itb was tested on BOLT v1.20, with the
-following kernels:
-
-https://github.com/Broadcom/stblinux-3.14
-https://github.com/Broadcom/stblinux-4.1
-https://github.com/Broadcom/stblinux-4.9
-
-and with a generic ARMv7 root file system.
-
-image.its:
-/dts-v1/;
-/ {
-   description = "BCM7445 FIT";
-   images {
-   kernel@1 {
-   description = "Linux kernel";
-   /*
-* This kernel image output format can be
-* generated with:
-*
-* make vmlinux
-* ${CROSS_COMPILE}objcopy -O binary -S vmlinux 
vmlinux.bin
-* gzip -9 vmlinux.bin
-*
-* For stblinux-3.14, the specific Broadcom
-* board type should be configured in the
-* kernel, for example CONFIG_BCM7445D0=y.
-*/
-   data = /incbin/("");
-   type = "kernel";
-   arch = "arm";
-   os = "linux";
-   compression = "gzip";
-   load = <0x8000>;
-   entry = <0x8000>;
-   hash@1 {
-   algo = "sha256";
-   };
-   };
-   ramdisk@1 {
-   description = "Initramfs root file system";
-   data = /incbin/("");
-   type = "ramdisk";
-   arch = "arm";
-   os = "linux";
-   compression = "gzip";
-   /*
-* Set the environment variable initrd_high to
-* 0x, and set "load" and "entry" here
-* to 0x0 to keep initramfs in-place and to
-* accommodate stblinux bmem/CMA reservations.
-*/
-   load = <0x0>;
-   entry = <0x0>;
-   hash@1 {
-   algo = "sha256";
-   };
-   };
-   fdt@1 {
-   description = "Device tree dumped from BOLT";
-   /*
-* This DTB should be similar to the
-* BOLT-generated device tree, after BOLT has
-* done its runtime modifications to it.  For
-* example, it can be dumped from within
-* U-Boot (at ${fdtcontroladdr}), after BOLT
-* has loaded U-Boot.  The result can be added
-* to the Linux source tree as a .dts file.
-*
-* To support modifications to 

[PATCH 3/4] mtd/fpga: add fpga directory to mtd (with Cyclone 10)

[u-boot]

From: Ulf Samuelsson 

Signed-off-by: Ulf Samuelsson 
---
 drivers/mtd/fpga/Kconfig  |  47 ++
 drivers/mtd/fpga/Makefile |   6 +
 drivers/mtd/fpga/cyclone_10.c | 278 ++
 3 files changed, 331 insertions(+)
 create mode 100644 drivers/mtd/fpga/Kconfig
 create mode 100644 drivers/mtd/fpga/Makefile
 create mode 100644 drivers/mtd/fpga/cyclone_10.c

diff --git a/drivers/mtd/fpga/Kconfig b/drivers/mtd/fpga/Kconfig
new file mode 100644
index 00..e3aa8c4522
--- /dev/null
+++ b/drivers/mtd/fpga/Kconfig
@@ -0,0 +1,47 @@
+menu "SPI FPGA Support"
+
+config DM_SPI_FPGA
+   bool "Enable Driver Model for FPGA configuration"
+   depends on DM && DM_SPI
+   imply SPI_FPGA
+   help
+ Enable driver model for FPGAs configurable using SPI.
+ This SPI FPGA interface
+ (spi_fpga_probe(), spi_fpga_write(), etc.) is then
+ implemented by the SPI FPGA uclass.
+ There is one standard SPI FPGA driver which knows how to probe
+ chips supported by U-Boot. The uclass interface is defined in
+ include/spi_fpga.h
+ SPI and SPI FPGA must be enabled together
+ (it is not possible to use driver model for one and not the other).
+
+if DM_SPI_FPGA
+
+config SPI_FPGA_MTD
+   bool "SPI FPGA MTD support"
+   depends on MTD
+   help
+ Enable the MTD support for the FPGA SPI Passive Serial,
+ This allows mtd_write commands to load an FPGA using passive serial
+ If unsure, say N
+
+config SPI_FPGA_INTEL
+   bool "Intel/Altera FPGA Passive Serial configuration using SPI"
+   help
+ Add support for various Intel SPI FPGA chips
+
+config SPI_FPGA_XILINX
+   bool "Xilinx FPGA Passive Serial configuration using SPI"
+   help
+ Add support for various Xilinx FPGA chips
+
+config SPI_FPGA_CYCLONE10
+   bool "Cyclone 10 SPI FPGA MTD support"
+   depends on SPI_FPGA_MTD && SPI_FPGA_INTEL
+   help
+ Enable the MTD support for the Cyclone 10 FPGA
+ If unsure, say N
+
+endif
+
+endmenu # menu "SPI FPGA Support"
diff --git a/drivers/mtd/fpga/Makefile b/drivers/mtd/fpga/Makefile
new file mode 100644
index 00..2cf19fc7cf
--- /dev/null
+++ b/drivers/mtd/fpga/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+
+obj-$(CONFIG_SPI_FPGA_CYCLONE10) += cyclone_10.o
diff --git a/drivers/mtd/fpga/cyclone_10.c b/drivers/mtd/fpga/cyclone_10.c
new file mode 100644
index 00..41e273211e
--- /dev/null
+++ b/drivers/mtd/fpga/cyclone_10.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * MTD Driver for Passive Serial configuration of Cyclone 10
+ *
+ * Copyright (C) 2020 Bombardier Transportation
+ * Ulf Samuelsson 
+ * Ulf Samuelsson 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+//#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * How many milliseconds from CONF_DONE high to enter user mode
+ * Datasheet says 650 us, Delay 2 ms to be safe...
+ */
+#defineUSER_MODE_DELAY 2
+
+struct cyc10_plat {
+   struct udevice  *dev;
+   struct spi_slave*spi;
+   charname[8];
+   struct gpio_descnconfig;
+   struct gpio_descnstatus;
+   struct gpio_descconf_done;
+   struct gpio_desccrc_error;
+   u32 cs;
+   int flags;
+   int config_size;
+};
+
+static inline void write_nCONFIG(struct cyc10_plat *fpga, int value)
+{
+   dm_gpio_set_value(>nconfig, value);
+}
+
+static inline int read_nSTATUS(struct cyc10_plat *fpga)
+{
+   int val = dm_gpio_get_value(>nstatus);
+   if (val < 0) {
+   printf("%s: Failure reading nSTATUS; error=%d\n", fpga->name, 
val);
+   }
+   return val;
+}
+
+static inline int read_CONFIG_DONE(struct cyc10_plat *fpga)
+{
+   int val = dm_gpio_get_value(>conf_done);
+   if (val < 0) {
+   printf("%s: Failure reading CONFIG_DONE; error=%d\n", 
fpga->name, val);
+   }
+   return val;
+}
+
+static inline int read_CRC_ERROR(struct cyc10_plat *fpga)
+{
+   int val = dm_gpio_get_value(>crc_error);
+   if (val < 0) {
+   printf("%s: Failure reading CRC_ERROR; error=%d\n", fpga->name, 
val);
+   }
+   return val;
+}
+
+/*
+ * Service routine to read status register until ready, or timeout occurs.
+ * Returns non-zero if error.
+ */
+static int cyc10_wait_until_conf_done(struct cyc10_plat *fpga)
+{
+   unsigned long timebase;
+   timebase = get_timer(0);
+
+   while (get_timer(timebase) < USER_MODE_DELAY) {
+   if (read_nSTATUS(fpga) == 0)/* Bad configuration */
+   return -EIO;
+   

[PATCH 4/4] mtd/Kconfig,Makefile support FPGA

[u-boot]

From: Ulf Samuelsson 

Signed-off-by: Ulf Samuelsson 
---
 drivers/mtd/Kconfig  | 2 ++
 drivers/mtd/Makefile | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index af45ef00da..495211e314 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -238,6 +238,8 @@ config SYS_MAX_FLASH_BANKS_DETECT
 to reduce the effective number of flash bank, between 0 and
 CONFIG_SYS_MAX_FLASH_BANKS
 
+source "drivers/mtd/fpga/Kconfig"
+
 source "drivers/mtd/nand/Kconfig"
 
 config SYS_NAND_MAX_OOBFREE
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 3a78590aaa..d15ca24ec5 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -24,6 +24,7 @@ endif
 obj-y += nand/
 obj-y += onenand/
 obj-y += spi/
+obj-$(CONFIG_DM_SPI_FPGA) += fpga/
 obj-$(CONFIG_MTD_UBI) += ubi/
 
 #SPL/TPL build
-- 
2.17.1

[PATCH 1/4] include/mtd/mtd-abi.h: Add FPGA as MTD device

[u-boot]

From: Ulf Samuelsson 

Signed-off-by: Ulf Samuelsson 
---
 include/mtd/mtd-abi.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h
index ea244fbaeb..cd826b64dd 100644
--- a/include/mtd/mtd-abi.h
+++ b/include/mtd/mtd-abi.h
@@ -89,6 +89,7 @@ struct mtd_write_req {
 #define MTD_DATAFLASH  6
 #define MTD_UBIVOLUME  7
 #define MTD_MLCNANDFLASH   8   /* MLC NAND (including TLC) */
+#defineMTD_FPGA9
 
 #define MTD_WRITEABLE  0x400   /* Device is writeable */
 #define MTD_BIT_WRITEABLE  0x800   /* Single bits can be flipped */
@@ -100,6 +101,7 @@ struct mtd_write_req {
 #define MTD_CAP_RAM(MTD_WRITEABLE | MTD_BIT_WRITEABLE | 
MTD_NO_ERASE)
 #define MTD_CAP_NORFLASH   (MTD_WRITEABLE | MTD_BIT_WRITEABLE)
 #define MTD_CAP_NANDFLASH  (MTD_WRITEABLE)
+#define MTD_CAP_FPGA   (MTD_WRITEABLE | MTD_NO_ERASE)
 
 /* Obsolete ECC byte placement modes (used with obsolete MEMGETOOBSEL) */
 #define MTD_NANDECC_OFF0   // Switch off ECC (Not 
recommended)
-- 
2.17.1

[PATCH 2/4] cmd/mtd.c: Support FPGAs in mtd command

[u-boot]

From: Ulf Samuelsson 

Signed-off-by: Ulf Samuelsson 
---
 cmd/mtd.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/cmd/mtd.c b/cmd/mtd.c
index eb6e2d6892..09d5fdaa11 100644
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -158,6 +158,9 @@ static void mtd_show_device(struct mtd_info *mtd)
case MTD_MLCNANDFLASH:
printf("MLC NAND flash\n");
break;
+   case MTD_FPGA:
+   printf("FPGA\n");
+   break;
case MTD_ABSENT:
default:
printf("Unknown\n");
@@ -275,6 +278,11 @@ static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int 
argc,
raw = strstr(cmd, ".raw");
woob = strstr(cmd, ".oob");
write_empty_pages = !has_pages || strstr(cmd, ".dontskipff");
+   if (mtd->type == MTD_FPGA) {
+   raw = true;
+   woob = false;
+   write_empty_pages = true;
+   }
 
argc -= 2;
argv += 2;
-- 
2.17.1

[PATCH 0/4] FPGAs as Memory Technology Devices in U-Boot

[u-boot]

As shown at a presentation in the recent OpenEmbedded Workshop,
it is possible to configure an FPGA in Passive Serial mode
using a standard SPI controller, each FPGA getting its own chipselect.

https://pretalx.com/openembedded-workshop-2023/talk/D3AQ3R/

This allows you to add the FPGA to the devicetree and to use standard MTD 
commands, instead of the FPGA commands.


I.E: The SPI portion is

 {
u-boot,dm-spl;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_pins>;
num-cs = <4>; /* Needed for GPIO cs */
cs-gpios =
< 12 GPIO_ACTIVE_LOW>, /* D18,0:12 uart1_ctsn.spi1_cs0 */
< 13 GPIO_ACTIVE_LOW>, /* D17,0:13 uart1_rtsn.spi1_cs1 */
< 17 GPIO_ACTIVE_LOW>, /* K15,0:17 mii_txd2.spi1_cs2 */
< 16 GPIO_ACTIVE_LOW>; /* J18,0:16 mii_txd3.spi1_cs3 */
spi-max-frequency = <1000>; ;
gpio_spi0: gpio_spi@0 {...}
gpio_spi1: gpio_spi@1 {...}
spi-fpga-cfg@2 {...} /* FPGA #1 */
spy-fpga-cfg@3 {...} /* FPGA #2 */
};

The FPGA part is.

spi-fpga-cfg@2 { /* Intel Cyclone 10, 10CL010 */
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,cyclone10";
reg = <2>; /* Chip select 2 */
spi-max-frequency = <1000>;
fpga = "spif"; /* Installed as /dev/spif */
config-size = <368011>;
nconfig-gpios = < 15 GPIO_ACTIVE_HIGH>; /* ,3:15 */
nstat-gpios = < 19 GPIO_ACTIVE_HIGH>; /* ,3:19 */
confd-gpios = < 18 GPIO_ACTIVE_HIGH>; /* ,3:18 */
crc-error-gpios= < 1 GPIO_ACTIVE_HIGH>; /* ,2:01 */
partition@0 {
label = "spi-fpga";
reg = <0x000 0x8000>;
};
};

To configure the FPGA, you load the config info into RAM and write it to the 
FPGA.

U-BOOT> mtd read spi1 ${loadaddr} 0 ${filesize} # read from SPI
U-BOOT> mtd write fpga0 ${loadaddr} 0 ${filesize} # configure FPGA

A driver will pulse the nCONFIG pin of the FPGA, do an SPI transfer
and then check the FPGA status outputs.

Since the MTD command set can be used (and is needed anyway)
the FPGA command set can be removed from the U-Boot both simplifying
the user interface and reducing code size of the u-boot image.

It relies on the (hopefully) existing SPI driver for the chip in u-boot
so it should be easy to use in most systems (as long as the H/W is designed for 
it)


A linux driver, using the same principle would allow the FPGA to be
configured using a simple statement.

$ cat  > /dev/fpga


The approach has been tested on a development board using an AM335x and 2 x 
Cyclone 10.

The changes needed are
* adding the FPGA class in mtd-abi.h
* The "mtd" command hardwires the transfer to be RAW and no OOB.
* A driver wrapping the control signals around an SPI transfer
  1.Claim SPI bus
  2.Pulse nCONFIG low for 40 us,
  3.Wait for nSTATUS high
  4.Transfer bitstream using U-Boot SPI transfer
  5.Release SPI bus
  6.Wait until CONFIG_DONE (or error on nSTATUS)

[PATCH 1/4] include/mtd/mtd-abi.h: Add FPGA as MTD device
[PATCH 2/4] cmd/mtd.c: Support FPGAs in mtd command
[PATCH 3/4] mtd/fpga: add fpga directory to mtd (with Cyclone 10)
[PATCH 4/4] mtd/Kconfig,Makefile support FPGA

Re: [PATCH 01/14] mtd: nand: brcm: switch to mtd_ooblayout_ops

[Michael Nazzareno Trimarchi]

Hi Linus

On Fri, Feb 3, 2023 at 6:23 PM William Zhang  wrote:
>
> Hi Linus and Michael,
>
> On 02/03/2023 03:10 AM, Linus Walleij wrote:
> > On Fri, Feb 3, 2023 at 9:48 AM Michael Nazzareno Trimarchi
> >  wrote:
> >> On Thu, Jan 26, 2023 at 6:39 PM William Zhang
> >>  wrote:
> >>>
> >>>
> >>>
> >>> On 01/26/2023 12:43 AM, Linus Walleij wrote:
>  On Thu, Jan 26, 2023 at 2:02 AM William Zhang
>   wrote:
> 
> >>
> >> Can you add your review-by?
> >
> > I think maybe I need to rebase the series and take out all the changes
> > that does not relate to patch 1 that changes the way we handle the
> > OOB layout so William can test the result?
> >
> Yeah I think that is a good idea and I can add my review-by and test-by
> tag if everything is good.
>
> > Yours,
> > Linus Walleij
> >

Can you repost your patchset?

Thanks
Michael

[PATCH v2 7/8] board: cssi: Add new board MCR3000_2G

[Christophe Leroy]

This adds a new board from CS GROUP. The board is called
MCR3000_2G, and has a CPU board called CMPC885.

That CPU board is shared with another equipment that will
be added in a later patch.

That board stores Ethernet MAC addresses in an EEPROM which
is accessed using SPI bus.

This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.

Signed-off-by: Christophe Leroy 
Reviewed-by: FRANJOU Stephane 
---
 arch/powerpc/cpu/mpc8xx/Kconfig |   4 +
 arch/powerpc/dts/Makefile   |   1 +
 arch/powerpc/dts/cmpc885.dts|  94 
 board/cssi/MAINTAINERS  |   2 +
 board/cssi/cmpc885/Kconfig  |  23 +
 board/cssi/cmpc885/Makefile |  10 +
 board/cssi/cmpc885/cmpc885.c| 830 
 board/cssi/cmpc885/cmpc885.env  |   7 +
 board/cssi/cmpc885/nand.c   |  47 ++
 board/cssi/cmpc885/sdram.c  | 107 
 board/cssi/cmpc885/u-boot.lds   |  95 
 configs/CMPC885_defconfig   | 110 +
 include/configs/cmpc885.h   |  29 ++
 13 files changed, 1359 insertions(+)
 create mode 100644 arch/powerpc/dts/cmpc885.dts
 create mode 100644 board/cssi/cmpc885/Kconfig
 create mode 100644 board/cssi/cmpc885/Makefile
 create mode 100644 board/cssi/cmpc885/cmpc885.c
 create mode 100644 board/cssi/cmpc885/cmpc885.env
 create mode 100644 board/cssi/cmpc885/nand.c
 create mode 100644 board/cssi/cmpc885/sdram.c
 create mode 100644 board/cssi/cmpc885/u-boot.lds
 create mode 100644 configs/CMPC885_defconfig
 create mode 100644 include/configs/cmpc885.h

diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 65293ae728..628d3617bc 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -11,6 +11,9 @@ choice
 config TARGET_MCR3000
bool "Support MCR3000 board from CSSI"
 
+config TARGET_CMPC885
+   bool "Support CMPC885 board from CSSI"
+
 endchoice
 
 choice
@@ -86,4 +89,5 @@ config SYS_DER
 
 source "board/cssi/mcr3000/Kconfig"
 
+source "board/cssi/cmpc885/Kconfig"
 endmenu
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index a4b0d7ddc4..26b592b85d 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb
 dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb
 dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
 dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
+dtb-$(CONFIG_TARGET_CMPC885) += cmpc885.dtb
 
 include $(srctree)/scripts/Makefile.dts
 
diff --git a/arch/powerpc/dts/cmpc885.dts b/arch/powerpc/dts/cmpc885.dts
new file mode 100644
index 00..adda0f3e9d
--- /dev/null
+++ b/arch/powerpc/dts/cmpc885.dts
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CMPC885 Device Tree Source
+ *
+ * Copyright 2020 CS Group
+ *
+ */
+
+/dts-v1/;
+
+/ {
+   model = "CMPC885";
+   compatible = "fsl, cmpc885", "fsl,mod885";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   chosen {
+   stdout-path = 
+   };
+
+   WDT: watchdog@0 {
+   device_type = "watchdog";
+   compatible = "fsl,pq1-wdt";
+   };
+
+   SERIAL: serial {
+   compatible = "fsl,pq1-smc";
+   };
+
+   FEC1: fec@0 {
+   compatible = "fsl,pq1-fec1";
+   };
+
+   FEC2: fec@1 {
+   compatible = "fsl,pq1-fec2";
+   };
+
+   soc: immr@ff00 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   device-type = "soc";
+   compatible = "simple-bus";
+   ranges = <0 0xff00 0x4000>;
+   reg = <0xff00 0x0200>;
+
+   CPM1_PIO_B: gpio-controller@ab8 {
+   #gpio-cells = <2>;
+   compatible = "fsl,cpm1-pario-bank-b";
+   reg = <0xab8 0x10>;
+   gpio-controller;
+   };
+
+   CPM1_PIO_D: gpio-controller@970 {
+   #gpio-cells = <2>;
+   compatible = "fsl,cpm1-pario-bank-d";
+   reg = <0x970 0x10>;
+   gpio-controller;
+   };
+
+   CPM1_PIO_A: gpio-controller@950 {
+   #gpio-cells = <2>;
+   compatible = "fsl,cpm1-pario-bank-a";
+   reg = <0x950 0x10>;
+   gpio-controller;
+   };
+
+   CPM1_PIO_C: gpio-controller@960 {
+   #gpio-cells = <2>;
+   compatible = "fsl,cpm1-pario-bank-c";
+   reg = <0x960 0x10>;
+   gpio-controller;
+   };
+
+   CPM1_PIO_E: gpio-controller@ac8 {
+   #gpio-cells = <2>;
+   compatible = "fsl,cpm1-pario-bank-e";
+   reg = <0xac8 0x18>;
+   gpio-controller;
+   };
+
+  

[PATCH v2 8/8] board: cssi: Add MIAE & VGoIP devices

[Christophe Leroy]

This adds support for the MIAE and VGoIP devices.
Those devices have the same CPU board that the MCR3000_2G board.

The devices are very modular, they are provided with
interchangeable front and back panels.

Linux kernel is shipped with a device tree which contains all
possible setups, and U-boot eliminates unrelated nodes based on
detected hardware.

This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.

Signed-off-by: Christophe Leroy 
Reviewed-by: FRANJOU Stephane 
---
 board/cssi/cmpc885/cmpc885.c | 286 ++-
 1 file changed, 281 insertions(+), 5 deletions(-)

diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c
index cde9a558ef..5233c24aae 100644
--- a/board/cssi/cmpc885/cmpc885.c
+++ b/board/cssi/cmpc885/cmpc885.c
@@ -29,8 +29,16 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define BOARD_CMPC885  "cmpc885"
 #define BOARD_MCR3000_2G   "mcr3k_2g"
+#define BOARD_VGOIP"vgoip"
+#define BOARD_MIAE "miae"
 
 #define TYPE_MCR   0x22
+#define TYPE_MIAE  0x23
+
+#define FAR_CASRSA 2
+#define FAR_VGOIP  4
+#define FAV_CLA7
+#define FAV_SRSA   8
 
 #define ADDR_CPLD_R_RESET  ((unsigned short __iomem 
*)CONFIG_CPLD_BASE)
 #define ADDR_CPLD_R_ETAT   ((unsigned short __iomem 
*)(CONFIG_CPLD_BASE + 2))
@@ -38,6 +46,12 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define ADDR_FPGA_R_BASE   ((unsigned char  __iomem 
*)CONFIG_FPGA_BASE)
 #define ADDR_FPGA_R_ALARMES_IN ((unsigned char  __iomem 
*)CONFIG_FPGA_BASE + 0x31)
+#define ADDR_FPGA_R_FAV((unsigned char  __iomem 
*)CONFIG_FPGA_BASE + 0x44)
+
+#define PATH_PHY2  "/soc@ff00/mdio@e00/ethernet-phy@2"
+#define PATH_PHY3  "/soc@ff00/mdio@e00/ethernet-phy@3"
+#define PATH_ETH1  "/soc@ff00/ethernet@1e00"
+#define FIBER_PHY PATH_PHY2
 
 #define FPGA_R_ACQ_AL_FAV  0x04
 #define R_ETAT_PRES_BASE   0x0040
@@ -45,15 +59,68 @@ DECLARE_GLOBAL_DATA_PTR;
 #define R_RESET_STATUS 0x0400
 #define R_RST_STATUS   0x0004
 
+static int fdt_set_node_and_value(void *blob, char *node, const char *prop,
+ void *var, int size)
+{
+   int ret, off;
+
+   off = fdt_path_offset(blob, node);
+
+   if (off < 0) {
+   printf("Cannot find %s node err:%s\n", node, fdt_strerror(off));
+
+   return off;
+   }
+
+   ret = fdt_setprop(blob, off, prop, var, size);
+
+   if (ret < 0)
+   printf("Cannot set %s/%s prop err: %s\n", node, prop, 
fdt_strerror(ret));
+
+   return ret;
+}
+
+/* Checks front/rear id and remove unneeded nodes from the blob */
+static void ft_cleanup(void *blob, uint32_t id, const char *prop, const char 
*compatible)
+{
+   int off;
+
+   off = fdt_node_offset_by_compatible(blob, -1, compatible);
+
+   while (off != -FDT_ERR_NOTFOUND) {
+   const struct fdt_property *ids;
+   int nb_ids, idx;
+   int tmp = -1;
+
+   ids = fdt_get_property(blob, off, prop, _ids);
+
+   for (idx = 0; idx < nb_ids; idx += 4) {
+   if (*((uint32_t *)>data[idx]) == id)
+   break;
+   }
+
+   if (idx >= nb_ids)
+   fdt_del_node(blob, off);
+   else
+   tmp = off;
+
+   off = fdt_node_offset_by_compatible(blob, tmp, compatible);
+   }
+
+   fdt_set_node_and_value(blob, "/", prop, , sizeof(uint32_t));
+}
+
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
+   u8 fav_id, far_id;
+
const char *sync = "receive";
 
ft_cpu_setup(blob, bd);
 
/* BRG */
-   do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
-bd->bi_busfreq, 1);
+   do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency", bd->bi_busfreq, 
1);
+
/* MAC addr */
fdt_fixup_ethernet(blob);
 
@@ -67,8 +134,33 @@ int ft_board_setup(void *blob, struct bd_info *bd)
do_fixup_by_path_u32(blob, "/localbus/e1", "channel-phase", 0, 1);
 
/* E1 interface - rising edge sync pulse transmit */
-   do_fixup_by_path(blob, "/localbus/e1", "rising-edge-sync-pulse",
-sync, strlen(sync), 1);
+   do_fixup_by_path(blob, "/localbus/e1", "rising-edge-sync-pulse", sync, 
strlen(sync), 1);
+
+   /* MIAE only */
+   if (!(in_be16(ADDR_CPLD_R_ETAT) & R_ETAT_PRES_BASE) || 
in_8(ADDR_FPGA_R_BASE) != TYPE_MIAE)
+   return 0;
+
+   far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
+   ft_cleanup(blob, (u32)far_id, "far-id", "cs,mia-far");
+
+   /*
+* special case, with CASRSA (far_id: 2)
+* FAV-SRSA register itself as FAV-CLA
+*/
+   fav_id = in_8(ADDR_FPGA_R_BASE + 0x44) >> 5;
+
+ 

[PATCH v2 5/8] driver, gpio: Add support for MPC 8xx CPU ports

[Christophe Leroy]

Ports A, C and D are 16 bits ports.
Ports B and E are 32 bits ports.

The "compatible" is used to determine each port type.

This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.

Signed-off-by: Christophe Leroy 
Reviewed-by: FRANJOU Stephane 
---
 arch/powerpc/Kconfig|   1 +
 arch/powerpc/include/asm/arch-mpc8xx/gpio.h |  12 +
 drivers/gpio/Kconfig|   7 +
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/mpc8xx_gpio.c  | 347 
 5 files changed, 368 insertions(+)
 create mode 100644 arch/powerpc/include/asm/arch-mpc8xx/gpio.h
 create mode 100644 drivers/gpio/mpc8xx_gpio.c

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index e0801c2594..bee59c3bea 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -28,6 +28,7 @@ config MPC85xx
 
 config MPC8xx
bool "MPC8xx"
+   select CREATE_ARCH_SYMLINK
select BOARD_EARLY_INIT_F
imply CMD_REGINFO
imply WDT_MPC8xx
diff --git a/arch/powerpc/include/asm/arch-mpc8xx/gpio.h 
b/arch/powerpc/include/asm/arch-mpc8xx/gpio.h
new file mode 100644
index 00..6b73acbaee
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc8xx/gpio.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _MPC8XX_GPIO_H_
+#define _MPC8XX_GPIO_H_
+
+struct mpc8xx_gpio_plat {
+   ulong addr;
+   unsigned long size;
+   uint ngpios;
+};
+
+#endif /* MPC8XX_GPIO_H_ */
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 365615a53f..7d5ddbdee0 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -547,6 +547,13 @@ config MPC8XXX_GPIO
  value setting, the open-drain feature, which can configure individual
  GPIOs to work as open-drain outputs, is supported.
 
+config MPC8XX_GPIO
+   bool "Freescale MPC8XX GPIO driver"
+   depends on DM_GPIO
+   help
+ This driver supports parallel IO ports from MPC8XX CPUs.
+ Each GPIO bank is identified by its own entry in the device tree.
+
 config MPC83XX_SPISEL_BOOT
bool "Freescale MPC83XX SPISEL_BOOT driver"
depends on DM_GPIO && ARCH_MPC830X
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7235714fcc..baceb54d31 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
 obj-$(CONFIG_ALTERA_PIO)   += altera_pio.o
 obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
 obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o
+obj-$(CONFIG_MPC8XX_GPIO)  += mpc8xx_gpio.o
 obj-$(CONFIG_MPC83XX_SPISEL_BOOT)  += mpc83xx_spisel_boot.o
 obj-$(CONFIG_SH_GPIO_PFC)  += sh_pfc.o
 obj-$(CONFIG_OMAP_GPIO)+= omap_gpio.o
diff --git a/drivers/gpio/mpc8xx_gpio.c b/drivers/gpio/mpc8xx_gpio.c
new file mode 100644
index 00..2f65346533
--- /dev/null
+++ b/drivers/gpio/mpc8xx_gpio.c
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 CS Group
+ * Charles Frey 
+ *
+ * based on driver/gpio/mpc8xxx_gpio.c, which is
+ * Copyright 2016 Mario Six, Guntermann & Drunck GmbH, mario@gdsys.cc
+ *
+ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
+ * Copyright 2010 eXMeritus, A Boeing Company
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+enum {
+   MPC8XX_CPM1_PORTA,
+   MPC8XX_CPM1_PORTB,
+   MPC8XX_CPM1_PORTC,
+   MPC8XX_CPM1_PORTD,
+   MPC8XX_CPM1_PORTE,
+};
+
+/*
+ * The MPC885 CPU CPM has 5 I/O ports, and each ports has different
+ * register length : 16 bits for ports A,C,D and 32 bits for ports
+ * B and E.
+ *
+ * This structure allows us to select the accessors according to the
+ * port we are configuring.
+ */
+struct mpc8xx_gpio_data {
+   /* The bank's register base in memory */
+   void __iomem *base;
+   /* The address of the registers; used to identify the bank */
+   ulong addr;
+   /* The GPIO count of the bank */
+   uint gpio_count;
+   /* Type needed to use the correct accessors */
+   int type;
+};
+
+/* Structure for ports A, C, D */
+struct iop_16 {
+   u16 pdir;
+   u16 ppar;
+   u16 podr;
+   u16 pdat;
+};
+
+/* Port B */
+struct iop_32_b {
+   u32 pdir;
+   u32 ppar;
+   u32 podr;
+   u32 pdat;
+};
+
+/* Port E */
+struct iop_32_e {
+   u32 pdir;
+   u32 ppar;
+   u32 psor;
+   u32 podr;
+   u32 pdat;
+};
+
+union iop_32 {
+   struct iop_32_b b;
+   struct iop_32_e e;
+};
+
+inline u32 gpio_mask(uint gpio, int type)
+{
+   if (type == MPC8XX_CPM1_PORTB || type == MPC8XX_CPM1_PORTE)
+   return 1U << (31 - (gpio));
+   else
+   return 1U << (15 - (gpio));
+}
+
+static inline u16 gpio16_get_val(void __iomem *base, u16 mask, int type)
+{
+   struct iop_16 *regs = base;
+
+   return in_be16(>pdat) & mask;
+}
+
+static inline 

[PATCH v2 2/8] board: MCR3000: Migrate to using CONFIG_EXTRA_ENV_TEXT

[Christophe Leroy]

We can move all of the environment changes to come
from CONFIG_EXTRA_ENV_TEXT.

Suggested-by: Tom Rini 
Signed-off-by: Christophe Leroy 
---
 board/cssi/mcr3000/mcr3000.env | 14 +++
 include/configs/mcr3000.h  | 43 --
 2 files changed, 14 insertions(+), 43 deletions(-)
 create mode 100644 board/cssi/mcr3000/mcr3000.env

diff --git a/board/cssi/mcr3000/mcr3000.env b/board/cssi/mcr3000/mcr3000.env
new file mode 100644
index 00..542d90e3ae
--- /dev/null
+++ b/board/cssi/mcr3000/mcr3000.env
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+sdram_type=SDRAM
+flash_type=AM29LV160DB
+loadaddr=0x40
+filename=uImage.lzma
+nfsroot=/opt/ofs
+dhcp_ip=ip=:eth0:dhcp
+console_args=console=ttyCPM0,115200N8
+flashboot=setenv bootargs ${console_args} 
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off;${ofl_args}; 
bootm 0x0406 - 0x0405
+tftpboot=setenv bootargs ${console_args} 
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off ${ofl_args}; 
tftp ${loadaddr} ${filename};tftp 0xf0 mcr3000.dtb;bootm ${loadaddr} - 
0xf0
+netboot=dhcp ${loadaddr} ${filename};tftp 0xf0 mcr3000.dtb;setenv bootargs 
root=/dev/nfs rw ${console_args} ${dhcp_ip};bootm ${loadaddr} - 0xf0
+nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} 
${console_args} 
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off;bootm 
0x0406 - 0x0405
+dhcpboot=dhcp ${loadaddr} ${filename};tftp 0xf0 mcr3000.dtb;setenv 
bootargs ${console_args} ${dhcp_ip} ${ofl_args}; bootm ${loadaddr} - 0xf0
diff --git a/include/configs/mcr3000.h b/include/configs/mcr3000.h
index c6929c1b98..8d78fd362a 100644
--- a/include/configs/mcr3000.h
+++ b/include/configs/mcr3000.h
@@ -9,49 +9,6 @@
 
 /* High Level Configuration Options */
 
-#define CFG_EXTRA_ENV_SETTINGS \
-   "sdram_type=SDRAM\0"\
-   "flash_type=AM29LV160DB\0"  \
-   "loadaddr=0x40\0"   \
-   "filename=uImage.lzma\0"\
-   "nfsroot=/opt/ofs\0"\
-   "dhcp_ip=ip=:eth0:dhcp\0"   \
-   "console_args=console=ttyCPM0,115200N8\0"   \
-   "flashboot=setenv bootargs "\
-   "${console_args} "  \
-   "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
-   "mcr3k:eth0:off;"   \
-   "${ofl_args}; " \
-   "bootm 0x0406 - 0x0405\0"   \
-   "tftpboot=setenv bootargs " \
-   "${console_args} "  \
-   "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
-   "mcr3k:eth0:off "   \
-   "${ofl_args}; " \
-   "tftp ${loadaddr} ${filename};" \
-   "tftp 0xf0 mcr3000.dtb;"\
-   "bootm ${loadaddr} - 0xf0\0"\
-   "netboot=dhcp ${loadaddr} ${filename};" \
-   "tftp 0xf0 mcr3000.dtb;"\
-   "setenv bootargs "  \
-   "root=/dev/nfs rw " \
-   "${console_args} "  \
-   "${dhcp_ip};"   \
-   "bootm ${loadaddr} - 0xf0\0"\
-   "nfsboot=setenv bootargs "  \
-   "root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} "  \
-   "${console_args} "  \
-   "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
-   "mcr3k:eth0:off;"   \
-   "bootm 0x0406 - 0x0405\0"   \
-   "dhcpboot=dhcp ${loadaddr} ${filename};"\
-   "tftp 0xf0 mcr3000.dtb;"\
-   "setenv bootargs "  \
-   "${console_args} "  \
-   "${dhcp_ip} "   \
-   "${ofl_args}; " \
-   "bootm ${loadaddr} - 0xf0\0"
-
 /* Miscellaneous configurable options */
 
 /* Definitions for initial 

[PATCH v2 3/8] board: MCR3000: Modernise the settings to properly work on lastest u-boot version

[Christophe Leroy]

Both U-boot and Linux kernel have grown over the last releases
and don't fit anymore in the 2M EPROM of the board.

So, rework the setup to allow storing the Linux kernel image
on the UBIFS NAND Flash.

Also add support to FIT images as this is what the Linux kernel
look like nowadays.

Also increase CFG_SYS_BOOTMAPSZ to 32Mbytes and define
CONFIG_SYS_BOOTM_LEN with the same value, otherwise it defaults
to 8M which is not sufficient anymore with nowadays Linux kernels.

And set the netmask to 255.255.255.0 as a class C address is used.

Signed-off-by: Christophe Leroy 
Reviewed-by: FRANJOU Stephane 
---
 board/cssi/mcr3000/mcr3000.env | 16 
 configs/MCR3000_defconfig  | 10 +++---
 include/configs/mcr3000.h  |  4 ++--
 3 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/board/cssi/mcr3000/mcr3000.env b/board/cssi/mcr3000/mcr3000.env
index 542d90e3ae..372ab09094 100644
--- a/board/cssi/mcr3000/mcr3000.env
+++ b/board/cssi/mcr3000/mcr3000.env
@@ -2,13 +2,13 @@
 
 sdram_type=SDRAM
 flash_type=AM29LV160DB
-loadaddr=0x40
-filename=uImage.lzma
-nfsroot=/opt/ofs
+loadaddr=0x120
+filename=mcr3000.itb
 dhcp_ip=ip=:eth0:dhcp
 console_args=console=ttyCPM0,115200N8
-flashboot=setenv bootargs ${console_args} 
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off;${ofl_args}; 
bootm 0x0406 - 0x0405
-tftpboot=setenv bootargs ${console_args} 
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off ${ofl_args}; 
tftp ${loadaddr} ${filename};tftp 0xf0 mcr3000.dtb;bootm ${loadaddr} - 
0xf0
-netboot=dhcp ${loadaddr} ${filename};tftp 0xf0 mcr3000.dtb;setenv bootargs 
root=/dev/nfs rw ${console_args} ${dhcp_ip};bootm ${loadaddr} - 0xf0
-nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} 
${console_args} 
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off;bootm 
0x0406 - 0x0405
-dhcpboot=dhcp ${loadaddr} ${filename};tftp 0xf0 mcr3000.dtb;setenv 
bootargs ${console_args} ${dhcp_ip} ${ofl_args}; bootm ${loadaddr} - 0xf0
+loadkernel=ubi part nand0;ubifsmount ubi0;ubifsload ${loadaddr} 
/boot/${filename};ubifsumount; ubi detach
+bootcmd=run flashboot
+flashboot=setenv bootargs ${console_args} 
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off;${ofl_args}; 
run loadkernel; bootm ${loadaddr}
+tftpboot=setenv bootargs ${console_args} 
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off ${ofl_args}; 
tftp ${loadaddr} ${filename}; bootm ${loadaddr}
+dhcpboot=dhcp ${loadaddr} ${filename};setenv bootargs ${console_args} 
${dhcp_ip} ${ofl_args}; bootm ${loadaddr}
+update=echo 'Updating ubi image'; if tftp 0x2000 $ubifile; then nand 
erase.chip; nand write 0x2000 0x00 $filesize; fi
diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
index 3e16ffc2ef..f96e9f06e1 100644
--- a/configs/MCR3000_defconfig
+++ b/configs/MCR3000_defconfig
@@ -20,6 +20,7 @@ CONFIG_SYS_SCCR=0x00C2
 CONFIG_SYS_SCCR_MASK=0x6000
 CONFIG_SYS_DER=0x2002000F
 CONFIG_SYS_MONITOR_LEN=327680
+CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_MONITOR_BASE=0x0400
 CONFIG_BOOTDELAY=5
@@ -36,11 +37,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PBSIZE=278
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
-CONFIG_SYS_BOOTM_LEN=0x80
+CONFIG_SYS_BOOTM_LEN=0x200
 # CONFIG_CMD_IMI is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND=y
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
@@ -51,6 +53,8 @@ CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_SLEEP is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
@@ -58,7 +62,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.0.3"
 CONFIG_USE_NETMASK=y
-CONFIG_NETMASK="255.0.0.0"
+CONFIG_NETMASK="255.255.255.0"
 CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.0.1"
 CONFIG_SYS_BR0_PRELIM_BOOL=y
@@ -87,6 +91,7 @@ CONFIG_SYS_BR7_PRELIM=0x1C01
 CONFIG_SYS_OR7_PRELIM=0x810A
 # CONFIG_MMC is not set
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_FLASH_SHOW_PROGRESS=0
@@ -97,5 +102,4 @@ CONFIG_MPC8XX_FEC=y
 # CONFIG_PCI is not set
 CONFIG_DM_SERIAL=y
 CONFIG_WDT=y
-CONFIG_SHA256=y
 CONFIG_LZMA=y
diff --git a/include/configs/mcr3000.h b/include/configs/mcr3000.h
index 8d78fd362a..6b16b050ff 100644
--- a/include/configs/mcr3000.h
+++ b/include/configs/mcr3000.h
@@ -23,10 +23,10 @@
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 32 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#defineCFG_SYS_BOOTMAPSZ   (8 << 20)
+#defineCFG_SYS_BOOTMAPSZ   (32 << 20)
 
 /* Environment Configuration */
 
-- 
2.39.1

[PATCH v2 1/8] board: MCR3000: Use lowercase filenames

[Christophe Leroy]

Rename MCR3000.* to mcr3000.* to be more in line with
other boards.

Signed-off-by: Christophe Leroy 
---
 arch/powerpc/cpu/mpc8xx/Kconfig | 2 +-
 board/cssi/MAINTAINERS  | 2 +-
 board/cssi/{MCR3000 => mcr3000}/Kconfig | 4 ++--
 board/cssi/{MCR3000 => mcr3000}/Makefile| 2 +-
 board/cssi/{MCR3000/MCR3000.c => mcr3000/mcr3000.c} | 0
 board/cssi/{MCR3000 => mcr3000}/nand.c  | 0
 board/cssi/{MCR3000 => mcr3000}/u-boot.lds  | 0
 include/configs/{MCR3000.h => mcr3000.h}| 0
 8 files changed, 5 insertions(+), 5 deletions(-)
 rename board/cssi/{MCR3000 => mcr3000}/Kconfig (78%)
 rename board/cssi/{MCR3000 => mcr3000}/Makefile (90%)
 rename board/cssi/{MCR3000/MCR3000.c => mcr3000/mcr3000.c} (100%)
 rename board/cssi/{MCR3000 => mcr3000}/nand.c (100%)
 rename board/cssi/{MCR3000 => mcr3000}/u-boot.lds (100%)
 rename include/configs/{MCR3000.h => mcr3000.h} (100%)

diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index d63071104c..65293ae728 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -84,6 +84,6 @@ config SYS_DER
help
  Debug Event Register (37-47)
 
-source "board/cssi/MCR3000/Kconfig"
+source "board/cssi/mcr3000/Kconfig"
 
 endmenu
diff --git a/board/cssi/MAINTAINERS b/board/cssi/MAINTAINERS
index 7d237b0b20..e1c0baa708 100644
--- a/board/cssi/MAINTAINERS
+++ b/board/cssi/MAINTAINERS
@@ -2,5 +2,5 @@ BOARDS from CS GROUP France
 M: Christophe Leroy 
 S: Maintained
 F: board/cssi/
-F: include/configs/MCR3000.h
+F: include/configs/mcr3000.h
 F: configs/MCR3000_defconfig
diff --git a/board/cssi/MCR3000/Kconfig b/board/cssi/mcr3000/Kconfig
similarity index 78%
rename from board/cssi/MCR3000/Kconfig
rename to board/cssi/mcr3000/Kconfig
index dbe2d5f0a3..ea073d9140 100644
--- a/board/cssi/MCR3000/Kconfig
+++ b/board/cssi/mcr3000/Kconfig
@@ -1,13 +1,13 @@
 if TARGET_MCR3000
 
 config SYS_BOARD
-   default "MCR3000"
+   default "mcr3000"
 
 config SYS_VENDOR
default "cssi"
 
 config SYS_CONFIG_NAME
-   default "MCR3000"
+   default "mcr3000"
 
 config TEXT_BASE
default 0x0400
diff --git a/board/cssi/MCR3000/Makefile b/board/cssi/mcr3000/Makefile
similarity index 90%
rename from board/cssi/MCR3000/Makefile
rename to board/cssi/mcr3000/Makefile
index 68d6812a89..7803016af3 100644
--- a/board/cssi/MCR3000/Makefile
+++ b/board/cssi/mcr3000/Makefile
@@ -4,5 +4,5 @@
 # Christophe Leroy 
 #
 
-obj-y += MCR3000.o
+obj-y += mcr3000.o
 obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/mcr3000/mcr3000.c
similarity index 100%
rename from board/cssi/MCR3000/MCR3000.c
rename to board/cssi/mcr3000/mcr3000.c
diff --git a/board/cssi/MCR3000/nand.c b/board/cssi/mcr3000/nand.c
similarity index 100%
rename from board/cssi/MCR3000/nand.c
rename to board/cssi/mcr3000/nand.c
diff --git a/board/cssi/MCR3000/u-boot.lds b/board/cssi/mcr3000/u-boot.lds
similarity index 100%
rename from board/cssi/MCR3000/u-boot.lds
rename to board/cssi/mcr3000/u-boot.lds
diff --git a/include/configs/MCR3000.h b/include/configs/mcr3000.h
similarity index 100%
rename from include/configs/MCR3000.h
rename to include/configs/mcr3000.h
-- 
2.39.1

[PATCH v2 0/8] Add new equipment from CSSI - v2

[Christophe Leroy]

This series adds a new CPU board called CMPC885 which
is used on two equipments called MCR3000 second generation
and MIAE/VGoIP devices, manufactured by former CSSI company
now called CS GROUP France.

This new board has a mpc 885 cpu.

The four first patches of the series update the already
included MCR3000 board in order to get more similarities.

Changes in v2:
- Migrate existing board to CONFIG_EXTRA_ENV_TEXT and also use
that for the new board
- Rebased on top of 2023.04-rc1
- More aggressive filename changes to lowercase
- CI: https://source.denx.de/u-boot/custodians/u-boot-mpc8xx/-/pipelines/15137

Christophe Leroy (8):
  board: MCR3000: Use lowercase filenames
  board: MCR3000: Migrate to using CONFIG_EXTRA_ENV_TEXT
  board: MCR3000: Modernise the settings to properly work on lastest
u-boot version
  board: MCR3000: Remove update of non-existing e1-wan DT node
  driver, gpio: Add support for MPC 8xx CPU ports
  spi, mpc8xx: Add support for chipselect via GPIO and fixups
  board: cssi: Add new board MCR3000_2G
  board: cssi: Add MIAE & VGoIP devices

 arch/powerpc/Kconfig  |1 +
 arch/powerpc/cpu/mpc8xx/Kconfig   |6 +-
 arch/powerpc/dts/Makefile |1 +
 arch/powerpc/dts/cmpc885.dts  |   94 ++
 arch/powerpc/include/asm/arch-mpc8xx/gpio.h   |   12 +
 board/cssi/MAINTAINERS|4 +-
 board/cssi/cmpc885/Kconfig|   23 +
 board/cssi/{MCR3000 => cmpc885}/Makefile  |6 +-
 board/cssi/cmpc885/cmpc885.c  | 1106 +
 board/cssi/cmpc885/cmpc885.env|7 +
 board/cssi/cmpc885/nand.c |   47 +
 board/cssi/cmpc885/sdram.c|  107 ++
 board/cssi/{MCR3000 => cmpc885}/u-boot.lds|2 +-
 board/cssi/{MCR3000 => mcr3000}/Kconfig   |4 +-
 board/cssi/{MCR3000 => mcr3000}/Makefile  |2 +-
 .../{MCR3000/MCR3000.c => mcr3000/mcr3000.c}  |   12 -
 board/cssi/mcr3000/mcr3000.env|   14 +
 board/cssi/{MCR3000 => mcr3000}/nand.c|0
 board/cssi/{MCR3000 => mcr3000}/u-boot.lds|0
 .../{MCR3000_defconfig => CMPC885_defconfig}  |   87 +-
 configs/MCR3000_defconfig |   10 +-
 drivers/gpio/Kconfig  |7 +
 drivers/gpio/Makefile |1 +
 drivers/gpio/mpc8xx_gpio.c|  347 ++
 drivers/spi/mpc8xx_spi.c  |   96 +-
 include/configs/MCR3000.h |   83 --
 include/configs/cmpc885.h |   29 +
 include/configs/mcr3000.h |   40 +
 28 files changed, 1966 insertions(+), 182 deletions(-)
 create mode 100644 arch/powerpc/dts/cmpc885.dts
 create mode 100644 arch/powerpc/include/asm/arch-mpc8xx/gpio.h
 create mode 100644 board/cssi/cmpc885/Kconfig
 copy board/cssi/{MCR3000 => cmpc885}/Makefile (52%)
 create mode 100644 board/cssi/cmpc885/cmpc885.c
 create mode 100644 board/cssi/cmpc885/cmpc885.env
 create mode 100644 board/cssi/cmpc885/nand.c
 create mode 100644 board/cssi/cmpc885/sdram.c
 copy board/cssi/{MCR3000 => cmpc885}/u-boot.lds (97%)
 rename board/cssi/{MCR3000 => mcr3000}/Kconfig (78%)
 rename board/cssi/{MCR3000 => mcr3000}/Makefile (90%)
 rename board/cssi/{MCR3000/MCR3000.c => mcr3000/mcr3000.c} (90%)
 create mode 100644 board/cssi/mcr3000/mcr3000.env
 rename board/cssi/{MCR3000 => mcr3000}/nand.c (100%)
 rename board/cssi/{MCR3000 => mcr3000}/u-boot.lds (100%)
 copy configs/{MCR3000_defconfig => CMPC885_defconfig} (54%)
 create mode 100644 drivers/gpio/mpc8xx_gpio.c
 delete mode 100644 include/configs/MCR3000.h
 create mode 100644 include/configs/cmpc885.h
 create mode 100644 include/configs/mcr3000.h

-- 
2.39.1

[PATCH v2 6/8] spi, mpc8xx: Add support for chipselect via GPIO and fixups

[Christophe Leroy]

This patch fixes the mpc8xx SPI driver:
- A stub callbacks for mode and speed,
- Use chip selects defined as GPIOs,
- Write proper value to disable relocation, other it fails on mpc885,
- Don't modify ports setup, ports can be different from one board to
another and are already set by board_early_init_r().

This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.

Signed-off-by: Christophe Leroy 
Reviewed-by: FRANJOU Stephane 
---
 drivers/spi/mpc8xx_spi.c | 96 
 1 file changed, 59 insertions(+), 37 deletions(-)

diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c
index 0026ad23e3..d84d7aea88 100644
--- a/drivers/spi/mpc8xx_spi.c
+++ b/drivers/spi/mpc8xx_spi.c
@@ -24,12 +24,29 @@
 
 #include 
 #include 
+#include 
 
 #define CPM_SPI_BASE_RXCPM_SPI_BASE
 #define CPM_SPI_BASE_TX(CPM_SPI_BASE + sizeof(cbd_t))
 
 #define MAX_BUFFER 0x104
 
+struct mpc8xx_priv {
+   spi_t __iomem *spi;
+   struct gpio_desc gpios[16];
+   int max_cs;
+};
+
+static int mpc8xx_spi_set_mode(struct udevice *dev, uint mod)
+{
+   return 0;
+}
+
+static int mpc8xx_spi_set_speed(struct udevice *dev, uint speed)
+{
+   return 0;
+}
+
 static int mpc8xx_spi_probe(struct udevice *dev)
 {
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -38,42 +55,9 @@ static int mpc8xx_spi_probe(struct udevice *dev)
cbd_t __iomem *tbdf, *rbdf;
 
/* Disable relocation */
-   out_be16(>spi_rpbase, 0);
+   out_be16(>spi_rpbase, 0x1d80);
 
 /* 1 */
-   /* 
-* Initialize Port B SPI pins -> page 34-8 MPC860UM
-* (we are only in Master Mode !)
-*  */
-
-   /* 
-* GPIO or per. Function
-* PBPAR[28] = 1 [0x0008] -> PERI: (SPIMISO)
-* PBPAR[29] = 1 [0x0004] -> PERI: (SPIMOSI)
-* PBPAR[30] = 1 [0x0002] -> PERI: (SPICLK)
-* PBPAR[31] = 0 [0x0001] -> GPIO: (CS for PCUE/CCM-EEPROM)
-*  */
-   clrsetbits_be32(>cp_pbpar, 0x0001, 0x000E); /* set  bits */
-
-   /* --
-* In/Out or per. Function 0/1
-* PBDIR[28] = 1 [0x0008] -> PERI1: SPIMISO
-* PBDIR[29] = 1 [0x0004] -> PERI1: SPIMOSI
-* PBDIR[30] = 1 [0x0002] -> PERI1: SPICLK
-* PBDIR[31] = 1 [0x0001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
-* -- */
-   setbits_be32(>cp_pbdir, 0x000F);
-
-   /* --
-* open drain or active output
-* PBODR[28] = 1 [0x0008] -> open drain: SPIMISO
-* PBODR[29] = 0 [0x0004] -> active output SPIMOSI
-* PBODR[30] = 0 [0x0002] -> active output: SPICLK
-* PBODR[31] = 0 [0x0001] -> active output GPIO OUT: CS for PCUE/CCM
-* -- */
-
-   clrsetbits_be16(>cp_pbodr, 0x0007, 0x0008);
-
/* Initialize the parameter ram.
 * We need to make sure many things are initialized to zero
 */
@@ -143,6 +127,22 @@ static int mpc8xx_spi_probe(struct udevice *dev)
return 0;
 }
 
+static void mpc8xx_spi_cs_activate(struct udevice *dev)
+{
+   struct mpc8xx_priv *priv = dev_get_priv(dev->parent);
+   struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev);
+
+   dm_gpio_set_value(>gpios[platdata->cs], 1);
+}
+
+static void mpc8xx_spi_cs_deactivate(struct udevice *dev)
+{
+   struct mpc8xx_priv *priv = dev_get_priv(dev->parent);
+   struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev);
+
+   dm_gpio_set_value(>gpios[platdata->cs], 0);
+}
+
 static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
 {
@@ -159,7 +159,8 @@ static int mpc8xx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
rbdf = (cbd_t __iomem *)>cp_dpmem[CPM_SPI_BASE_RX];
 
/* Set CS for device */
-   clrbits_be32(>cp_pbdat, 0x0001);
+   if (flags & SPI_XFER_BEGIN)
+   mpc8xx_spi_cs_activate(dev);
 
/* Setting tx bd status and data length */
out_be32(>cbd_bufaddr, (ulong)dout);
@@ -186,21 +187,40 @@ static int mpc8xx_spi_xfer(struct udevice *dev, unsigned 
int bitlen,
for (tm = 0; tm < 1000; ++tm) {
if (in_8(>cp_spie) & SPI_TXB)   /* Tx Buffer Empty */
break;
+
if ((in_be16(>cbd_sc) & BD_SC_READY) == 0)
break;
udelay(1000);
}
+
if (tm >= 1000)
printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
 

[PATCH v2 4/8] board: MCR3000: Remove update of non-existing e1-wan DT node

[Christophe Leroy]

e1-wan device-tree node doesn't exist. Remove related update
to avoid following warning at startup:

 Loading Device Tree to 007fa000, end 007ff951 ... OK
Unable to update property /localbus/e1-wan:data-rate, 
err=FDT_ERR_NOTFOUND
Unable to update property /localbus/e1-wan:channel-phase, 
err=FDT_ERR_NOTFOUND
Unable to update property /localbus/e1-wan:rising-edge-sync-pulse, 
err=FDT_ERR_NOTFOUND

Signed-off-by: Christophe Leroy 
Reviewed-by: FRANJOU Stephane 
---
 board/cssi/mcr3000/mcr3000.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/board/cssi/mcr3000/mcr3000.c b/board/cssi/mcr3000/mcr3000.c
index e95e04a30a..7b3ab12bd5 100644
--- a/board/cssi/mcr3000/mcr3000.c
+++ b/board/cssi/mcr3000/mcr3000.c
@@ -58,8 +58,6 @@ static const uint cs1_dram_table_66[] = {
 
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
-   const char *sync = "receive";
-
ft_cpu_setup(blob, bd);
 
/* BRG */
@@ -72,16 +70,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
/* Bus Frequency for CPM */
do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
 
-   /* E1 interface - Set data rate */
-   do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
-
-   /* E1 interface - Set channel phase to 0 */
-   do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
-
-   /* E1 interface - rising edge sync pulse transmit */
-   do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
-sync, strlen(sync), 1);
-
return 0;
 }
 
-- 
2.39.1