Re: [PATCH 1/8] video: rockchip: vop: Fix whitespace

[Kever Yang]

Hi Ondrej,

    Thanks for you patches.

On 2023/5/23 05:47, m...@xff.cz wrote:

From: Ondrej Jirman 

Fix confusing use of indentation.

Signed-off-by: Ondrej Jirman 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  drivers/video/rockchip/rk_vop.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index dab9902fda73..c514e2a0e449 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -432,7 +432,7 @@ int rk_vop_probe(struct udevice *dev)
ret = reset_assert(_rst);
if (ret) {
dev_err(dev, "failed to assert ahb reset (ret=%d)\n", ret);
-   return ret;
+   return ret;
}
udelay(20);
  

Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU

[Sam Edwards]

Hi again Andre,

On 12/5/22 17:45, Andre Przywara wrote:

+static struct ccu_clk_gate d1_gates[] = {
+   [CLK_BUS_MMC0]  = GATE(0x84c, BIT(0)),
+   [CLK_BUS_MMC1]  = GATE(0x84c, BIT(1)),
+   [CLK_BUS_MMC2]  = GATE(0x84c, BIT(2)),
+   [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
+   [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
+   [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
+   [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
+   [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
+   [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
+   [CLK_BUS_I2C0]  = GATE(0x91c, BIT(0)),
+   [CLK_BUS_I2C1]  = GATE(0x91c, BIT(1)),
+   [CLK_BUS_I2C2]  = GATE(0x91c, BIT(2)),
+   [CLK_BUS_I2C3]  = GATE(0x91c, BIT(3)),
+   [CLK_SPI0]  = GATE(0x940, BIT(31)),
+   [CLK_SPI1]  = GATE(0x944, BIT(31)),
+   [CLK_BUS_SPI0]  = GATE(0x96c, BIT(0)),
+   [CLK_BUS_SPI1]  = GATE(0x96c, BIT(1)),
+
+   [CLK_BUS_EMAC]  = GATE(0x97c, BIT(0)),
+
+   [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
+   [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
+   [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
+   [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
+   [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
+   [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
+   [CLK_BUS_OTG]   = GATE(0xa8c, BIT(8)),
+   [CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)),
+
+   [CLK_RISCV] = GATE(0xd04, BIT(31)),
+};


Would it be reasonable to add (possibly one for APB1 also):
[CLK_APB0] = GATE_DUMMY,

...in order to suppress this warning at init:
sunxi_set_gate: (CLK#24) unhandled

As I understand it, CLK_APB0 is only for speed control and doesn't have 
a gate, but since the FDT references it, other drivers are asking the 
clock driver to ungate it, resulting in that (safe-to-ignore) warning.


Warm regards,
Sam

PS: Do you have any plans for PSCI support, so we can get the second 
core up too? I'd like to patch that in and include it in your series 
once my available time permits. Just thought I'd check that you/someone 
wasn't working on it already. :)

[PATCH v5 3/3] Load option with short device path for boot vars

[Raymond Mao]

The boot variables automatically generated for removable medias
should be with short form of device path without device nodes.
This is a requirement for the case that a removable media is
plugged into a different port but is still able to work with the
existing boot variables.

Signed-off-by: Raymond Mao 
---
Changes in v2
- Ignore EFI_NOT_FOUND returned from
  efi_bootmgr_update_media_device_boot_option which means no boot
  options scanned.
Changes in v3
- Split the patch into moving and renaming functions and
  individual patches for each changed functionality
Changes in v4
- Revert the change of introducing a bool parameter when updating
  the boot option. Use short-form of device path by default
Changes in v5
- Move function call of efi_bootmgr_update_media_device_boot_option()
  from efi_init_variables() to efi_init_obj_list()
- Add warning log when a short-form device path doesn't exist

 lib/efi_loader/efi_bootmgr.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index c329428973..67e833141f 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -387,6 +387,13 @@ static efi_status_t 
efi_bootmgr_enumerate_boot_option(struct eficonfig_media_boo
p = dev_name;
utf8_utf16_strncpy(, buf, strlen(buf));
 
+   /* use short form device path */
+   device_path = efi_dp_shorten(device_path);
+   if (!device_path) {
+   log_warning("No short-form device path for device %s, 
skip it\n", buf);
+   continue;
+   }
+
lo.label = dev_name;
lo.attributes = LOAD_OPTION_ACTIVE;
lo.file_path = device_path;
-- 
2.25.1

[PATCH v5 2/3] Boot var automatic management for removable medias

[Raymond Mao]

Changes for complying to EFI spec §3.5.1.1
'Removable Media Boot Behavior'.
Boot variables can be automatically generated during a removable
media is probed. At the same time, unused boot variables will be
detected and removed.

Signed-off-by: Raymond Mao 
---
Changes in v2
- Ignore EFI_NOT_FOUND returned from
  efi_bootmgr_update_media_device_boot_option which means no boot
  options scanned.
Changes in v3
- Split the patch into moving and renaming functions and
  individual patches for each changed functionality
Changes in v4
- Revert the change of introducing a bool parameter when updating
  the boot option. Use short-form of device path by default
Changes in v5
- Move function call of efi_bootmgr_update_media_device_boot_option()
  from efi_init_variables() to efi_init_obj_list()
- Add warning log when a short-form device path doesn't exist

 lib/efi_loader/efi_disk.c | 7 +++
 lib/efi_loader/efi_setup.c| 5 +
 lib/efi_loader/efi_variable.c | 1 -
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index d2256713a8..ca5f07f2ec 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -687,6 +687,13 @@ int efi_disk_probe(void *ctx, struct event *event)
return -1;
}
 
+   /* only do the boot option management when UEFI sub-system is 
initialized */
+   if (efi_obj_list_initialized == EFI_SUCCESS) {
+   ret = efi_bootmgr_update_media_device_boot_option();
+   if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
+   return -1;
+   }
+
return 0;
 }
 
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index 58d4e13402..4686374995 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -245,6 +245,11 @@ efi_status_t efi_init_obj_list(void)
if (ret != EFI_SUCCESS)
goto out;
 
+   /* update boot option after variable service initialized */
+   ret = efi_bootmgr_update_media_device_boot_option();
+   if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
+   goto out;
+
/* Define supported languages */
ret = efi_init_platform_lang();
if (ret != EFI_SUCCESS)
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index be95ed44e6..1529fffd1d 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -476,6 +476,5 @@ efi_status_t efi_init_variables(void)
log_err("Invalid EFI variable seed\n");
}
 
-
return efi_init_secure_state();
 }
-- 
2.25.1

[PATCH v5 1/3] Move bootorder and bootoption apis to lib

[Raymond Mao]

Rename and move bootorder and bootoption apis from cmd to lib
for re-use between eficonfig and bootmgr

Signed-off-by: Raymond Mao 
---
Changes in v2
- Ignore EFI_NOT_FOUND returned from
  efi_bootmgr_update_media_device_boot_option which means no boot
  options scanned.
Changes in v3
- Split the patch into moving and renaming functions and
  individual patches for each changed functionality
Changes in v4
- Revert the change of introducing a bool parameter when updating
  the boot option. Use short-form of device path by default
Changes in v5
- Move function call of efi_bootmgr_update_media_device_boot_option()
  from efi_init_variables() to efi_init_obj_list()
- Add warning log when a short-form device path doesn't exist

 cmd/bootmenu.c   |   2 +-
 cmd/eficonfig.c  | 408 +--
 include/efi_config.h |   5 -
 include/efi_loader.h |  11 +
 lib/efi_loader/efi_bootmgr.c | 380 
 lib/efi_loader/efi_helper.c  |  25 +++
 6 files changed, 423 insertions(+), 408 deletions(-)

diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index 6baeedc69f..01daddca7b 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -351,7 +351,7 @@ static struct bootmenu_data *bootmenu_create(int delay)
 * UEFI specification requires booting from removal media using
 * a architecture-specific default image name such as 
BOOTAA64.EFI.
 */
-   efi_ret = eficonfig_generate_media_device_boot_option();
+   efi_ret = efi_bootmgr_update_media_device_boot_option();
if (efi_ret != EFI_SUCCESS && efi_ret != EFI_NOT_FOUND)
goto cleanup;
 
diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
index 720f52b48b..82a80306f4 100644
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -1134,43 +1134,6 @@ out:
return ret;
 }
 
-/**
- * eficonfig_get_unused_bootoption() - get unused "Boot" index
- *
- * @buf:   pointer to the buffer to store boot option variable name
- * @buf_size:  buffer size
- * @index: pointer to store the index in the BootOrder variable
- * Return: status code
- */
-efi_status_t eficonfig_get_unused_bootoption(u16 *buf, efi_uintn_t buf_size,
-unsigned int *index)
-{
-   u32 i;
-   efi_status_t ret;
-   efi_uintn_t size;
-
-   if (buf_size < u16_strsize(u"Boot"))
-   return EFI_BUFFER_TOO_SMALL;
-
-   for (i = 0; i <= 0x; i++) {
-   size = 0;
-   efi_create_indexed_name(buf, buf_size, "Boot", i);
-   ret = efi_get_variable_int(buf, _global_variable_guid,
-  NULL, , NULL, NULL);
-   if (ret == EFI_BUFFER_TOO_SMALL)
-   continue;
-   else
-   break;
-   }
-
-   if (i > 0x)
-   return EFI_OUT_OF_RESOURCES;
-
-   *index = i;
-
-   return EFI_SUCCESS;
-}
-
 /**
  * eficonfig_set_boot_option() - set boot option
  *
@@ -1208,46 +1171,6 @@ static efi_status_t eficonfig_set_boot_option(u16 
*varname, struct efi_device_pa
return ret;
 }
 
-/**
- * eficonfig_append_bootorder() - append new boot option in BootOrder variable
- *
- * @index: "Boot" index to append to BootOrder variable
- * Return: status code
- */
-efi_status_t eficonfig_append_bootorder(u16 index)
-{
-   u16 *bootorder;
-   efi_status_t ret;
-   u16 *new_bootorder = NULL;
-   efi_uintn_t last, size, new_size;
-
-   /* append new boot option */
-   bootorder = efi_get_var(u"BootOrder", _global_variable_guid, );
-   last = size / sizeof(u16);
-   new_size = size + sizeof(u16);
-   new_bootorder = calloc(1, new_size);
-   if (!new_bootorder) {
-   ret = EFI_OUT_OF_RESOURCES;
-   goto out;
-   }
-   memcpy(new_bootorder, bootorder, size);
-   new_bootorder[last] = index;
-
-   ret = efi_set_variable_int(u"BootOrder", _global_variable_guid,
-  EFI_VARIABLE_NON_VOLATILE |
-  EFI_VARIABLE_BOOTSERVICE_ACCESS |
-  EFI_VARIABLE_RUNTIME_ACCESS,
-  new_size, new_bootorder, false);
-   if (ret != EFI_SUCCESS)
-   goto out;
-
-out:
-   free(bootorder);
-   free(new_bootorder);
-
-   return ret;
-}
-
 /**
  * create_boot_option_entry() - create boot option entry
  *
@@ -1619,7 +1542,7 @@ static efi_status_t 
eficonfig_process_add_boot_option(void *data)
if (!bo)
return EFI_OUT_OF_RESOURCES;
 
-   ret = eficonfig_get_unused_bootoption(varname, sizeof(varname), 
>boot_index);
+   ret = efi_bootmgr_get_unused_bootoption(varname, sizeof(varname), 
>boot_index);
if (ret != EFI_SUCCESS)
return ret;
 
@@ -1627,7 +1550,7 @@ static 

Re: Pull request: please pull u-boot-imx-20230525

[Tom Rini]

On Thu, May 25, 2023 at 09:05:07AM +0200, Stefano Babic wrote:

> Hi Tom,
> 
> please pull from u-boot-imx, thanks !
> 
> This PR conbtains :
> 
>   - Fixes
>   - Improvement support for i.MX93
> 
> 
> The following changes since commit 6e1852ca2c418e2536ead4b51c4d84a59926b3f1:
> 
>   Merge tag 'efi-2023-07-rc3' of
> https://source.denx.de/u-boot/custodians/u-boot-efi (2023-05-16 11:23:30
> -0400)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
> tags/u-boot-imx-20230525
> 
> for you to fetch changes up to ff476897ed698eae1fa439d52b30694a2b40464a:
> 
>   serial: mxs: Add MXS AUART driver (2023-05-21 16:54:41 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature

[PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration

[Hugo Villeneuve]

From: Hugo Villeneuve 

For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
therefore not used.

For SOM without EC configuration, the ethernet PHY on the carrier
board is connected to the CPU ethernet controller. It has a reset line
controlled via the GPIO expander PCA9534_IO5.

The hardware configuration (EC) is determined at runtime by
reading from the SOM EEPROM.

To support both hardware configurations (EC and non-EC), adjust/fix
the PHY reset gpios according to the hardware configuration
read at runtime from the SOM EEPROM. This adjustement is done in
U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.

Signed-off-by: Hugo Villeneuve 
---
 arch/arm/dts/imx8mn-var-som-symphony.dts  |  4 -
 .../variscite/imx8mn_var_som/imx8mn_var_som.c | 80 +++
 configs/imx8mn_var_som_defconfig  |  2 +
 3 files changed, 82 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts 
b/arch/arm/dts/imx8mn-var-som-symphony.dts
index 3ed7021a48..5c8e4e8175 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony.dts
+++ b/arch/arm/dts/imx8mn-var-som-symphony.dts
@@ -56,10 +56,6 @@
};
 };
 
- {
-   reset-gpios = < 5 GPIO_ACTIVE_HIGH>;
-};
-
  {
clock-frequency = <40>;
pinctrl-names = "default";
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c 
b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index a89457e8f5..61b9455a8f 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -161,4 +162,83 @@ int checkboard(void)
 
 #endif /* CONFIG_DISPLAY_BOARDINFO */
 
+static int insert_gpios_prop(void *blob, int node, const char *prop,
+unsigned int phandle, u32 gpio, u32 flags)
+{
+   fdt32_t val[3] = { cpu_to_fdt32(phandle), cpu_to_fdt32(gpio),
+  cpu_to_fdt32(flags) };
+   return fdt_setprop(blob, node, prop, , sizeof(val));
+}
+
+static int configure_phy_reset_gpios(void *blob)
+{
+   int node;
+   int phynode;
+   int ret;
+   u32 handle;
+   u32 gpio;
+   u32 flags;
+   char path[1024];
+   const char *eth_alias = "ethernet0";
+
+   snprintf(path, sizeof(path), "%s/mdio/ethernet-phy@4",
+fdt_get_alias(blob, eth_alias));
+
+   phynode = fdt_path_offset(blob, path);
+   if (phynode < 0) {
+   pr_err("%s(): unable to locate PHY node: %s\n", __func__, path);
+   return 0;
+   }
+
+   if (gd_board_type() & VAR_EEPROM_F_ETH) {
+   snprintf(path, sizeof(path), "%s",
+fdt_get_alias(blob, "gpio0")); /* Alias to gpio1 */
+   gpio = 9;
+   flags = GPIO_ACTIVE_LOW;
+   } else {
+   snprintf(path, sizeof(path), "%s/gpio@20",
+fdt_get_alias(blob, "i2c1")); /* Alias to i2c2 */
+   gpio = 5;
+   flags = GPIO_ACTIVE_HIGH;
+   }
+
+   node = fdt_path_offset(blob, path);
+   if (node < 0) {
+   pr_err("%s(): unable to locate GPIO node: %s\n", __func__,
+  path);
+   return 0;
+   }
+
+   handle = fdt_get_phandle(blob, node);
+   if (handle < 0) {
+   pr_err("%s(): unable to locate GPIO controller handle: %s\n",
+  __func__, path);
+   }
+
+   ret = insert_gpios_prop(blob, phynode, "reset-gpios",
+   handle, gpio, flags);
+   if (ret < 0) {
+   pr_err("%s(): failed to set reset-gpios property\n", __func__);
+   return ret;
+   }
+
+   return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+   /* Fix U-Boot device tree: */
+   return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_FIXUP */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+   /* Fix kernel device tree: */
+   return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
 #endif /* CONFIG_SPL_BUILD */
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index f0e232081f..d8a442d623 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -22,10 +22,12 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800
 CONFIG_SYS_LOAD_ADDR=0x4048
+CONFIG_OF_BOARD_FIXUP=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DISTRO_DEFAULTS=y
 

[PATCH v2 3/5] arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay

[Hugo Villeneuve]

From: Hugo Villeneuve 

While testing the ethernet interface on a Variscite symphony carrier
board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware
configuration), the ethernet PHY is not detected.

The ADIN1300 datasheet indicate that the "Management interface
active (t4)" state is reached at most 5ms after the reset signal is
deasserted.

The device tree in Variscite custom git repository uses the following
property:

phy-reset-post-delay = <20>;

Add a new MDIO property 'reset-deassert-us' of 20ms to have the same
delay inside the ethphy node. Adding this property fixes the problem
with the PHY detection.

Note that this SOM can also have an Atheros AR8033 PHY. In this case,
a 1ms deassert delay is sufficient. Add a comment to that effect.

Fixes: c4c1ed68c1e8 ("imx8mn_var_som: Add support for Variscite
VAR-SOM-MX8M-NANO board")

Signed-off-by: Hugo Villeneuve 
---
 arch/arm/dts/imx8mn-var-som.dtsi | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
index dea9eff3f0..4eb578a03f 100644
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -102,11 +102,17 @@
#address-cells = <1>;
#size-cells = <0>;
 
-   ethphy: ethernet-phy@4 {
+   ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
reset-gpios = < 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <1>;
+   /*
+* Deassert delay:
+* ADIN1300 requires 5ms.
+* AR8033   requires 1ms.
+*/
+   reset-deassert-us = <2>;
};
};
 };
-- 
2.30.2

[PATCH v2 4/5] imx8mn-var-som: read eth MAC address from EEPROM

[Hugo Villeneuve]

From: Hugo Villeneuve 

Read ethernet MAC address from EEPROM located on the SOM.

Signed-off-by: Hugo Villeneuve 
---
 arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 13 +
 arch/arm/mach-imx/imx8m/Kconfig  |  1 +
 2 files changed, 14 insertions(+)

diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi 
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index 7272fc2b4c..e0caf3179e 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -13,6 +13,19 @@
bootph-pre-ram;
 };
 
+_som {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   eth_mac_address: eth-mac-address@19 {
+   reg = <0x19 0x06>;
+   };
+};
+
+ {
+   nvmem-cells = <_mac_address>;
+   nvmem-cell-names = "mac-address";
+};
+
  {
bootph-pre-ram;
 };
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index a940d8a950..67db3e46ec 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -248,6 +248,7 @@ config TARGET_IMX8MN_VAR_SOM
select MISC
select I2C_EEPROM
select DM_ETH_PHY
+   select NVMEM
 
 config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
-- 
2.30.2

[PATCH v2 1/5] imx8mn-var-som: read and print SoM infos from eeprom on startup

[Hugo Villeneuve]

From: Hugo Villeneuve 

Enable support to read and display configuration/manufacturing infos
from 4Kbit EEPROM located on SOM board.

Note: CONFIG_DISPLAY_BOARDINFO is automatically selected for ARM arch.

Signed-off-by: Hugo Villeneuve 
---
 .../dts/imx8mn-var-som-symphony-u-boot.dtsi   |   4 +
 arch/arm/dts/imx8mn-var-som.dtsi  |  10 ++
 arch/arm/mach-imx/imx8m/Kconfig   |   2 +
 .../variscite/imx8mn_var_som/imx8mn_var_som.c | 134 ++
 configs/imx8mn_var_som_defconfig  |   1 +
 5 files changed, 151 insertions(+)

diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi 
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index af80aaea0b..7272fc2b4c 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -68,3 +68,7 @@
  {
bootph-pre-ram;
 };
+
+_som {
+   bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
index 87b5e23c76..dea9eff3f0 100644
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -11,6 +11,10 @@
model = "Variscite VAR-SOM-MX8MN module";
compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
 
+   aliases {
+   eeprom-som = _som;
+   };
+
chosen {
stdout-path = 
};
@@ -222,6 +226,12 @@
};
};
};
+
+   eeprom_som: eeprom@52 {
+   compatible = "atmel,24c04";
+   reg = <0x52>;
+   pagesize = <16>;
+   };
 };
 
  {
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 7639439bdc..3450399d6f 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -245,6 +245,8 @@ config TARGET_IMX8MN_VAR_SOM
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
+   select MISC
+   select I2C_EEPROM
 
 config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c 
b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index d40f4d0176..a89457e8f5 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -1,11 +1,49 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2021 Collabora Ltd.
+ * Copyright 2018-2020 Variscite Ltd.
+ * Copyright 2023 DimOnOff Inc.
  */
 
 #include 
+#include 
 #include 
+#include 
+#include 
+#include 
+#include 
 #include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Optional SOM features flags. */
+#define VAR_EEPROM_F_WIFI  BIT(0)
+#define VAR_EEPROM_F_ETH   BIT(1) /* Ethernet PHY on SOM. */
+#define VAR_EEPROM_F_AUDIO BIT(2)
+#define VAR_EEPROM_F_MX8M_LVDS BIT(3) /* i.MX8MM, i.MX8MN, i.MX8MQ 
only */
+#define VAR_EEPROM_F_MX8Q_SOC_ID   BIT(3) /* 0 = i.MX8QM, 1 = i.MX8QP */
+#define VAR_EEPROM_F_NAND  BIT(4)
+
+#define VAR_IMX8_EEPROM_MAGIC  0x384D /* "8M" */
+
+/* Number of DRAM adjustment tables. */
+#define DRAM_TABLES_NUM 7
+
+struct var_imx8_eeprom_info {
+   u16 magic;
+   u8 partnumber[3]; /* Part number */
+   u8 assembly[10];  /* Assembly number */
+   u8 date[9];   /* Build date */
+   u8 mac[6];/* MAC address */
+   u8 somrev;
+   u8 eeprom_version;
+   u8 features;  /* SOM features */
+   u8 dramsize;  /* DRAM size */
+   u8 off[DRAM_TABLES_NUM + 1]; /* DRAM table offsets */
+   u8 partnumber2[5];/* Part number 2 */
+} __packed;
 
 static void setup_fec(void)
 {
@@ -28,3 +66,99 @@ int board_mmc_get_env_dev(int devno)
 {
return devno;
 }
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+
+static void display_som_infos(struct var_imx8_eeprom_info *info)
+{
+   char partnumber[sizeof(info->partnumber) +
+   sizeof(info->partnumber2) + 1];
+   char assembly[sizeof(info->assembly) + 1];
+   char date[sizeof(info->date) + 1];
+
+   /* Read first part of P/N. */
+   memcpy(partnumber, info->partnumber, sizeof(info->partnumber));
+
+   /* Read second part of P/N. */
+   if (info->eeprom_version >= 3)
+   memcpy(partnumber + sizeof(info->partnumber), info->partnumber2,
+  sizeof(info->partnumber2));
+
+   memcpy(assembly, info->assembly, sizeof(info->assembly));
+   memcpy(date, info->date, sizeof(info->date));
+
+   /* Make sure strings are null terminated. */
+   partnumber[sizeof(partnumber) - 1] = '\0';
+   assembly[sizeof(assembly) - 1] = '\0';
+   date[sizeof(date) - 1] = '\0';
+
+   printf("SOM board: P/N: %s, Assy: %s, Date: %s\n"
+  "   Wifi: %s, EthPhy: %s, Rev: %d\n",
+  partnumber, assembly, date,
+  info->features & 

[PATCH v2 2/5] imx8mn-var-som: fix non-applied PHY reset-gpios properties

[Hugo Villeneuve]

From: Hugo Villeneuve 

Select DM_ETH_PHY so that the reset-gpios property of the ethphy node
can be used.

Also select DM_PCA953X, which is needed for resetting the
ethernet PHY on the carrier board via the PCA9534 I/O expander.

Commit 4e5114daf9eb ("imx8mn: synchronise device tree with linux") did
synchronise device tree with linux, which in effect removed obsolete
PHY reset properties and replaced them with new mdio DM
properties. But the commit didn't activate DM_ETH_PHY or DM_PCA953X.

Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux")

Signed-off-by: Hugo Villeneuve 
---
 arch/arm/mach-imx/imx8m/Kconfig  | 1 +
 configs/imx8mn_var_som_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 3450399d6f..a940d8a950 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -247,6 +247,7 @@ config TARGET_IMX8MN_VAR_SOM
select IMX8M_DDR4
select MISC
select I2C_EEPROM
+   select DM_ETH_PHY
 
 config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index f8bbdb6935..f0e232081f 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -77,6 +77,7 @@ CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_UUU_SUPPORT=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=2
 CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
-- 
2.30.2

[PATCH v2 0/5] imx8mn-var-som: fix ethernet for Variscite symphony board and imx8m nano SOM

[Hugo Villeneuve]

From: Hugo Villeneuve 

Hello,
This patch series fixes bugs and add missing features related to the ethernet
PHY on Variscite symphony carrier board with an imx8m nano SOM
(P/N VAR-SOM-MX8M-NANO).

Ethernet functionality is currently broken for the VAR-SOM-MX8M-NANO.

Variscite imx8m nano SOM comes in multiple hardware configuration options.
One of this hardware configuration option is called EC:
EC: Ethernet Controller PHY assembled on SOM

For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
therefore not used.

For SOM without EC configuration, the ethernet PHY on the carrier
board is connected to the CPU ethernet controller. It has a reset line
controlled via the GPIO expander PCA9534_IO5.

Patch 1 add code to read and display the SOM configuration stored in the SOM
EEPROM. Part of this patch was submitted and accepted to the Linux kernel
(section that adds the EEPROM to the device tree), so that it will be easier to
sync the DT between kernel and U-Boot.

Patch 2 fixes bugs with the PHY reset properties.

Patch 3 fixes a bug with a missing PHY reset deassert delay (also submitted and
accepted to kernel).

Patch 4 enables automatic read of PHY MAC address from the SOM EEPROM.

Patch 5 is used for auto-detecting at runtime the SOM hardware configuration
option related to the PHY (EC), and dynamically adjust the device tree to
support both SOM PHY options.

I have succesfully tested the changes on a Variscite symphony carrier board with
a VAR-SOM-MX8M-NANO having the EC configuration option.

Unfortunately, I do not have a VAR-SOM-MX8M-NANO with a non-EC configuration
option so I couldn't test it on real hardware, altough I simulated it and
confirmed that the device tree fixing seems to be correct by using debug/print
statements.

Thank you.

Link: [v1] 
https://lore.kernel.org/u-boot/20230501200121.3137519-1-h...@hugovil.com/

Changes for V2:
- Resend since I received 0 answers/comments after almost 4 weeks and I have a
  few minor updates to add:
  - Update defconfig using savedefconfig
  - Remove requirement about required patch (now in master)
  - Update status of patches also sent to the Linux kernel

Hugo Villeneuve (5):
  imx8mn-var-som: read and print SoM infos from eeprom on startup
  imx8mn-var-som: fix non-applied PHY reset-gpios properties
  arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert
delay
  imx8mn-var-som: read eth MAC address from EEPROM
  imx8mn-var-som: adjust PHY reset gpios according to hardware
configuration

 .../dts/imx8mn-var-som-symphony-u-boot.dtsi   |  17 ++
 arch/arm/dts/imx8mn-var-som-symphony.dts  |   4 -
 arch/arm/dts/imx8mn-var-som.dtsi  |  18 +-
 arch/arm/mach-imx/imx8m/Kconfig   |   4 +
 .../variscite/imx8mn_var_som/imx8mn_var_som.c | 214 ++
 configs/imx8mn_var_som_defconfig  |   4 +
 6 files changed, 256 insertions(+), 5 deletions(-)


base-commit: 62df7a39442902a71259568c13a4d496d5a514f4
-- 
2.30.2

Re: [PATCH v4 2/3] Boot var automatic management for removable medias

[Raymond Mao]

On Thu, 25 May 2023 at 09:55, Ilias Apalodimas 
wrote:

> On Tue, May 23, 2023 at 12:18:20PM -0700, Raymond Mao wrote:
> > Changes for complying to EFI spec §3.5.1.1
> > 'Removable Media Boot Behavior'.
> > Boot variables can be automatically generated during a removable
> > media is probed. At the same time, unused boot variables will be
> > detected and removed.
> >
> > Signed-off-by: Raymond Mao 
> > ---
> > Changes in v2
> > - Ignore EFI_NOT_FOUND returned from
> >   efi_bootmgr_update_media_device_boot_option which means no boot
> >   options scanned.
> > Changes in v3
> > - Split the patch into moving and renaming functions and
> >   individual patches for each changed functionality
> > Changes in v4
> > - Revert the change of introducing a bool parameter when updating
> >   the boot option. Use short-form of device path by default
> >
> >  lib/efi_loader/efi_disk.c |  7 +++
> >  lib/efi_loader/efi_variable.c | 10 +-
> >  lib/efi_loader/efi_variable_tee.c |  5 +
> >  3 files changed, 21 insertions(+), 1 deletion(-)
> >
> > diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
> > index d2256713a8..ca5f07f2ec 100644
> > --- a/lib/efi_loader/efi_disk.c
> > +++ b/lib/efi_loader/efi_disk.c
> > @@ -687,6 +687,13 @@ int efi_disk_probe(void *ctx, struct event *event)
> >   return -1;
> >   }
> >
> > + /* only do the boot option management when UEFI sub-system is
> initialized */
> > + if (efi_obj_list_initialized == EFI_SUCCESS) {
> > + ret = efi_bootmgr_update_media_device_boot_option();
> > + if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
> > + return -1;
> > + }
> > +
> >   return 0;
> >  }
> >
> > diff --git a/lib/efi_loader/efi_variable.c
> b/lib/efi_loader/efi_variable.c
> > index be95ed44e6..fe71144358 100644
> > --- a/lib/efi_loader/efi_variable.c
> > +++ b/lib/efi_loader/efi_variable.c
> > @@ -476,6 +476,14 @@ efi_status_t efi_init_variables(void)
> >   log_err("Invalid EFI variable seed\n");
> >   }
> >
> > + ret = efi_init_secure_state();
> > + if (ret != EFI_SUCCESS)
> > + return ret;
> >
> > - return efi_init_secure_state();
> > + /* update boot option management after variable service
> initialized */
> > + ret = efi_bootmgr_update_media_device_boot_option();
> > + if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
> > + return ret;
> > +
> > + return EFI_SUCCESS;
> >  }
> > diff --git a/lib/efi_loader/efi_variable_tee.c
> b/lib/efi_loader/efi_variable_tee.c
> > index dfef18435d..2995d4a583 100644
> > --- a/lib/efi_loader/efi_variable_tee.c
> > +++ b/lib/efi_loader/efi_variable_tee.c
> > @@ -748,5 +748,10 @@ efi_status_t efi_init_variables(void)
> >   if (ret != EFI_SUCCESS)
> >   return ret;
> >
> > + /* update boot option management after variable service
> initialized */
> > + ret = efi_bootmgr_update_media_device_boot_option();
> > + if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
> > + return ret;
> > +
> >   return EFI_SUCCESS;
>
> Instead of having to add identical code in the variable init code why dont
> we add this in efi_setup.c, right under the efi_init_variables() call?
>
[RM] Because I think the purpose of the
function efi_bootmgr_update_media_device_boot_option
is to update the boot option which belongs to part of variable
initialization.
So it is better to be inside efi_init_variables() other
than efi_init_obj_list().

>
> Thanks
> /Ilias
> >  }
> > --
> > 2.25.1
> >
>

Re: USB mass storage gadget on SAMA5D2

[Cristian.Birsan]

Hi,

On 5/22/23 12:00, admin LI wrote:
>   
> 
> I think there may be some racing in the driver. (Purely assumption as a 
> tinyusb maintainer)
> If I enable DBG_ALL in atmel_usba_udc.h, the block device is enermurated 
> although with I/O error.

What are you trying to achieve ? If you want to just program the eMMC you can 
do it easily with SAM-BA[1].

The mass storage gadget works well in Linux kernel. You can have a look at the 
driver we have in the kernel
here[2].


[1] https://www.microchip.com/en-us/development-tool/SAM-BA-In-system-Programmer
[2] 
https://github.com/linux4microchip/linux/blob/linux-6.1-mchp/drivers/usb/gadget/udc/atmel_usba_udc.c

Regards,
Cristian

> 
> [1337613.189788] usb 1-1: new high-speed USB device number 7 using xhci_hcd
> [1337613.674551] usb 1-1: New USB device found, idVendor=dead, 
> idProduct=beef, bcdDevice= 2.17
> [1337613.674565] usb 1-1: New USB device strings: Mfr=1, Product=2, 
> SerialNumber=0
> [1337613.674568] usb 1-1: Product: USB download gadget
> [1337613.674572] usb 1-1: Manufacturer: U-Boot
> [1337613.866033] usb-storage 1-1:1.0: USB Mass Storage device detected
> [1337613.866645] scsi host0: usb-storage 1-1:1.0
> [1337614.997803] scsi 0:0:0:0: Direct-Access     Linux    UMS disk 0       
>  PQ: 0 ANSI: 2
> [1337615.230004] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337615.706637] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337616.183308] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337616.659937] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337617.140086] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337617.616632] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337618.073323] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337618.549927] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337619.026540] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337619.499944] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337619.976679] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337620.453285] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337620.916597] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337621.393267] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337621.869676] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337622.346597] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337622.823361] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337623.293287] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337623.635357] sd 0:0:0:0: [sda] Read Capacity(10) failed: Result: 
> hostbyte=DID_ERROR driverbyte=DRIVER_OK
> [1337623.635369] sd 0:0:0:0: [sda] Sense not available.
> [1337623.635376] sd 0:0:0:0: [sda] 0 512-byte logical blocks: (0 B/0 B)
> [1337623.635379] sd 0:0:0:0: [sda] 0-byte physical blocks
> [1337623.756597] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337624.233274] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337624.709945] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337625.186639] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337625.663266] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337626.136617] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337626.478078] sd 0:0:0:0: [sda] Write Protect is off
> [1337626.478088] sd 0:0:0:0: [sda] Mode Sense: 00 00 00 00
> [1337626.599928] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337627.076606] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337627.553276] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337628.029936] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337628.499858] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337628.973267] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337629.313846] sd 0:0:0:0: [sda] Asking for cache data failed
> [1337629.313861] sd 0:0:0:0: [sda] Assuming drive cache: write through
> [1337629.314517] sd 0:0:0:0: [sda] Attached SCSI removable disk
> [1337629.436603] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337629.906353] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337630.373268] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337630.843284] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337631.306595] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337631.783253] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337632.259935] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337632.736612] usb 1-1: reset high-speed USB device number 7 using xhci_hcd
> [1337633.213283] usb 1-1: reset 

Re: [PATCH v4 2/3] Boot var automatic management for removable medias

[Ilias Apalodimas]

On Thu, 25 May 2023 at 19:42, Raymond Mao  wrote:
>
>
>
> On Thu, 25 May 2023 at 09:55, Ilias Apalodimas  
> wrote:
>>
>> On Tue, May 23, 2023 at 12:18:20PM -0700, Raymond Mao wrote:
>> > Changes for complying to EFI spec §3.5.1.1
>> > 'Removable Media Boot Behavior'.
>> > Boot variables can be automatically generated during a removable
>> > media is probed. At the same time, unused boot variables will be
>> > detected and removed.
>> >
>> > Signed-off-by: Raymond Mao 
>> > ---
>> > Changes in v2
>> > - Ignore EFI_NOT_FOUND returned from
>> >   efi_bootmgr_update_media_device_boot_option which means no boot
>> >   options scanned.
>> > Changes in v3
>> > - Split the patch into moving and renaming functions and
>> >   individual patches for each changed functionality
>> > Changes in v4
>> > - Revert the change of introducing a bool parameter when updating
>> >   the boot option. Use short-form of device path by default
>> >
>> >  lib/efi_loader/efi_disk.c |  7 +++
>> >  lib/efi_loader/efi_variable.c | 10 +-
>> >  lib/efi_loader/efi_variable_tee.c |  5 +
>> >  3 files changed, 21 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
>> > index d2256713a8..ca5f07f2ec 100644
>> > --- a/lib/efi_loader/efi_disk.c
>> > +++ b/lib/efi_loader/efi_disk.c
>> > @@ -687,6 +687,13 @@ int efi_disk_probe(void *ctx, struct event *event)
>> >   return -1;
>> >   }
>> >
>> > + /* only do the boot option management when UEFI sub-system is 
>> > initialized */
>> > + if (efi_obj_list_initialized == EFI_SUCCESS) {
>> > + ret = efi_bootmgr_update_media_device_boot_option();
>> > + if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
>> > + return -1;
>> > + }
>> > +
>> >   return 0;
>> >  }
>> >
>> > diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
>> > index be95ed44e6..fe71144358 100644
>> > --- a/lib/efi_loader/efi_variable.c
>> > +++ b/lib/efi_loader/efi_variable.c
>> > @@ -476,6 +476,14 @@ efi_status_t efi_init_variables(void)
>> >   log_err("Invalid EFI variable seed\n");
>> >   }
>> >
>> > + ret = efi_init_secure_state();
>> > + if (ret != EFI_SUCCESS)
>> > + return ret;
>> >
>> > - return efi_init_secure_state();
>> > + /* update boot option management after variable service initialized 
>> > */
>> > + ret = efi_bootmgr_update_media_device_boot_option();
>> > + if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
>> > + return ret;
>> > +
>> > + return EFI_SUCCESS;
>> >  }
>> > diff --git a/lib/efi_loader/efi_variable_tee.c 
>> > b/lib/efi_loader/efi_variable_tee.c
>> > index dfef18435d..2995d4a583 100644
>> > --- a/lib/efi_loader/efi_variable_tee.c
>> > +++ b/lib/efi_loader/efi_variable_tee.c
>> > @@ -748,5 +748,10 @@ efi_status_t efi_init_variables(void)
>> >   if (ret != EFI_SUCCESS)
>> >   return ret;
>> >
>> > + /* update boot option management after variable service initialized 
>> > */
>> > + ret = efi_bootmgr_update_media_device_boot_option();
>> > + if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
>> > + return ret;
>> > +
>> >   return EFI_SUCCESS;
>>
>> Instead of having to add identical code in the variable init code why dont
>> we add this in efi_setup.c, right under the efi_init_variables() call?
>
> [RM] Because I think the purpose of the function 
> efi_bootmgr_update_media_device_boot_option
> is to update the boot option which belongs to part of variable initialization.
> So it is better to be inside efi_init_variables() other than 
> efi_init_obj_list().

We also have efi_init_platform_lang(), efi_init_os_indications() which
also 'just' initialize variables. So I think having it in the
efi_setup() makes sense.

Thanks
/Ilias
>>
>>
>> Thanks
>> /Ilias
>> >  }
>> > --
>> > 2.25.1
>> >

Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model

[Maksim Kiselev]

Hi, Andre

Could you please include this fix for i2c in the next version of this 
series.


diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 93bbc6916e..d088ea75b9 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -124,7 +124,7 @@ enum mvtwsi_ctrl_register_fields {
  * on other platforms, it is a normal r/w bit, which is cleared by 
writing 0.

  */

-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || 
defined(CONFIG_SUNXI_GEN_NCAT2)

 #define    MVTWSI_CONTROL_CLEAR_IFLG   0x0008
 #else
 #define    MVTWSI_CONTROL_CLEAR_IFLG   0x

Re: [PATCH v2] PCI: zynqmp: Add ZynqMP NWL PCIe root port driver

[Michal Simek]

On 5/25/23 11:49, Stefan Roese wrote:

This patch adds the PCIe controller driver for the Xilinx / AMD ZynqMP
NWL PCIe Bridge as root port. The driver source is partly copied from
the Linux PCI driver and modified to enable usage in U-Boot (e.g.
simplified and interrupt support removed).

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Pali Rohár 
Cc: Bin Meng 
Cc: Michal Simek 
---
v2:
- Remove some unused members from struct nwl_pcie
- Fix usage of dev_seq() in nwl_pcie_config_address()
- Remove writing to PCI_PRIMARY_BUS reg as this is done by the
   common U-Boot PCI code later

  MAINTAINERS   |   1 +
  drivers/pci/Kconfig   |   7 +
  drivers/pci/Makefile  |   1 +
  drivers/pci/pcie-xilinx-nwl.c | 352 ++
  4 files changed, 361 insertions(+)
  create mode 100644 drivers/pci/pcie-xilinx-nwl.c


Tested-by: Michal Simek 
Acked-by: Michal Simek 

I am happy to take this via my tree if you like.
We should also enable this driver by default in xilinx_zynqmp_virt_defconfig and 
likely any pcie driver to be able to test it.

I used e1000 based card and it works as expected.

Thanks,
Michal

Re: Fit Signature booting without public key

[Tom Rini]

On Thu, May 25, 2023 at 11:21:44AM +0530, Manorit Chawdhry wrote:
> Hi Tom,
> 
> On 11:30-20230516, Tom Rini wrote:
> > On Tue, May 16, 2023 at 12:11:24PM +0530, Manorit Chawdhry wrote:
> > 
> > > Hi All,
> > > 
> > > I recently came upon a discussion that had happened a while back [0].
> > > I want to continue the discussion as I believe the issue still persists
> > > and the checks around fit signature booting are still the same, that
> > > allows booting the fit without changing the uboot dtb.
> > > 
> > > Allowing the signed fit image without this seems to be a bypass that is
> > > available and should not be allowed without any gate to it for people
> > > who'd like to enforce these signing checks. Let me know if there is a
> > > config already available for it and if not, are there any plans to
> > > enable such a config in future. Would like to hear your opinions on
> > > this as I believe this should be fixed as soon as possible.
> > > 
> > > [0]: 
> > > https://u-boot.denx.narkive.com/dEClg9dW/signed-fit-image-boots-without-public-key
> > 
> > Yes, can you please reproduce the issue in question on the current tree,
> > with a supported platform and provide the defconfig and steps you used
> > for this issue? Thanks.
> > 
> > -- 
> 
> I've created a branch with some custom patches to make the fitimage
> booting currently, please try with the branch and the fitimage that are
> also committed [0].
> 
> The devices that I've tested this with is j721e-hs-evm, the defconfig to
> use for the builds are j721e_evm_r5_defconfig and
> j721e_evm_a72_defconfig. Although not synced up with the latest changes
> but for reference the SDK documentation can help if required [1].
> 
> Attached the logs for reference with the signed fitimage and an unsigned
> uboot without any modifications[2].
> 
> [0]: https://github.com/manorit2001/u-boot/tree/fit-image-poc
> [1]: 
> https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/08_06_00_11/exports/docs/linux/Foundational_Components/U-Boot/UG-General-Info.html
> [2]: https://gist.github.com/manorit2001/3c49cfc19bf937783efb75fd4cddc58f

I don't see the problem there, but please go and investigate what
problem you're seeing.  The intention is that yes, with the appropriate
CONFIG settings, you can set U-Boot to only boot signed FIT
configurations and unsigned ones should not boot.

-- 
Tom


signature.asc
Description: PGP signature

Re: [PATCH v4 2/3] Boot var automatic management for removable medias

[Ilias Apalodimas]

On Tue, May 23, 2023 at 12:18:20PM -0700, Raymond Mao wrote:
> Changes for complying to EFI spec §3.5.1.1
> 'Removable Media Boot Behavior'.
> Boot variables can be automatically generated during a removable
> media is probed. At the same time, unused boot variables will be
> detected and removed.
>
> Signed-off-by: Raymond Mao 
> ---
> Changes in v2
> - Ignore EFI_NOT_FOUND returned from
>   efi_bootmgr_update_media_device_boot_option which means no boot
>   options scanned.
> Changes in v3
> - Split the patch into moving and renaming functions and
>   individual patches for each changed functionality
> Changes in v4
> - Revert the change of introducing a bool parameter when updating
>   the boot option. Use short-form of device path by default
>
>  lib/efi_loader/efi_disk.c |  7 +++
>  lib/efi_loader/efi_variable.c | 10 +-
>  lib/efi_loader/efi_variable_tee.c |  5 +
>  3 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
> index d2256713a8..ca5f07f2ec 100644
> --- a/lib/efi_loader/efi_disk.c
> +++ b/lib/efi_loader/efi_disk.c
> @@ -687,6 +687,13 @@ int efi_disk_probe(void *ctx, struct event *event)
>   return -1;
>   }
>
> + /* only do the boot option management when UEFI sub-system is 
> initialized */
> + if (efi_obj_list_initialized == EFI_SUCCESS) {
> + ret = efi_bootmgr_update_media_device_boot_option();
> + if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
> + return -1;
> + }
> +
>   return 0;
>  }
>
> diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
> index be95ed44e6..fe71144358 100644
> --- a/lib/efi_loader/efi_variable.c
> +++ b/lib/efi_loader/efi_variable.c
> @@ -476,6 +476,14 @@ efi_status_t efi_init_variables(void)
>   log_err("Invalid EFI variable seed\n");
>   }
>
> + ret = efi_init_secure_state();
> + if (ret != EFI_SUCCESS)
> + return ret;
>
> - return efi_init_secure_state();
> + /* update boot option management after variable service initialized */
> + ret = efi_bootmgr_update_media_device_boot_option();
> + if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
> + return ret;
> +
> + return EFI_SUCCESS;
>  }
> diff --git a/lib/efi_loader/efi_variable_tee.c 
> b/lib/efi_loader/efi_variable_tee.c
> index dfef18435d..2995d4a583 100644
> --- a/lib/efi_loader/efi_variable_tee.c
> +++ b/lib/efi_loader/efi_variable_tee.c
> @@ -748,5 +748,10 @@ efi_status_t efi_init_variables(void)
>   if (ret != EFI_SUCCESS)
>   return ret;
>
> + /* update boot option management after variable service initialized */
> + ret = efi_bootmgr_update_media_device_boot_option();
> + if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
> + return ret;
> +
>   return EFI_SUCCESS;

Instead of having to add identical code in the variable init code why dont
we add this in efi_setup.c, right under the efi_init_variables() call?

Thanks
/Ilias
>  }
> --
> 2.25.1
>

[PATCH] pinephone-pro: Fix I/O port voltage (GPIO3D4A is 1.8V)

[Ondřej Jirman]

From: Ondrej Jirman 

This fixes access to camera sensor over I2C during probe time in
the kernel. (Kernel will fix I/0 port voltage by itself, but the
timing depends on probe order of the drivers, so the fix can
come after the camera sensor driver already failed to probe.)

Signed-off-by: Ondrej Jirman 
Cc: Kever Yang 
---
 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c 
b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
index eb639cd0d070..b6ccbb9c1c4b 100644
--- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
@@ -15,7 +15,8 @@
 #include 
 #include 
 
-#define GRF_IO_VSEL_BT565_SHIFT 0
+#define GRF_IO_VSEL_BT565_GPIO2AB 1
+#define GRF_IO_VSEL_AUDIO_GPIO3D4A 2
 #define PMUGRF_CON0_VSEL_SHIFT 8
 
 #ifndef CONFIG_SPL_BUILD
@@ -48,7 +49,8 @@ static void setup_iodomain(void)
   syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 
/* BT565 is in 1.8v domain */
-   rk_setreg(>io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
+   rk_setreg(>io_vsel,
+ GRF_IO_VSEL_BT565_GPIO2AB | GRF_IO_VSEL_AUDIO_GPIO3D4A);
 
/* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
rk_setreg(>soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
-- 
2.40.1

[PATCH v1] common/memsize.c: Fix get_ram_size() when cache is enabled

[Francesco Dolcini]

From: Emanuele Ghidoli 

Ensure that every write is flushed to memory and afterward reads are
from memory.
Since the algorithm rely on the fact that accessing to not existent
memory lead to write at addr / 2 without this modification accesses
to aliased (not physically present) addresses are cached and
wrong size is returned.

This was discovered while working on a TI AM625 based board
where cache is normally enabled, see commit c02712a74849 ("arm: mach-k3: Enable 
dcache in SPL").

Signed-off-by: Emanuele Ghidoli 
Signed-off-by: Francesco Dolcini 
---
 common/memsize.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/common/memsize.c b/common/memsize.c
index 66d5be6a1ff3..f3cd28a06cc6 100644
--- a/common/memsize.c
+++ b/common/memsize.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -20,6 +21,16 @@ DECLARE_GLOBAL_DATA_PTR;
 # define sync()/* nothing */
 #endif
 
+static void dcache_flush_invalidate(volatile long *p)
+{
+   phys_addr_t start, stop;
+
+   start = ALIGN_DOWN((phys_addr_t)p, CONFIG_SYS_CACHELINE_SIZE);
+   stop = start + CONFIG_SYS_CACHELINE_SIZE;
+   flush_dcache_range(start, stop);
+   invalidate_dcache_range(start, stop);
+}
+
 /*
  * Check memory range for valid RAM. A simple memory test determines
  * the actually available RAM size between addresses `base' and
@@ -41,6 +52,7 @@ long get_ram_size(long *base, long maxsize)
save[i++] = *addr;
sync();
*addr = ~cnt;
+   dcache_flush_invalidate(addr);
}
 
addr = base;
@@ -50,6 +62,8 @@ long get_ram_size(long *base, long maxsize)
*addr = 0;
 
sync();
+   dcache_flush_invalidate(addr);
+
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function. */
sync();
-- 
2.25.1

Re: mmc: Read eMMC partition access bits before card reset

[Stefan Roese]

Hi Tony,
Hi Pali,

On 5/18/23 22:55, Tony Dinh wrote:

Hi Stefan,

On Wed, May 17, 2023 at 1:26 AM Stefan Roese  wrote:


Hi Pali,

On 5/17/23 00:30, Pali Rohár wrote:

On Tuesday 16 May 2023 14:56:46 Tom Rini wrote:

On Tue, May 16, 2023 at 08:52:23PM +0200, Pali Rohár wrote:

On Tuesday 16 May 2023 11:36:20 Tom Rini wrote:

On Tue, May 16, 2023 at 09:04:27AM +0200, Pali Rohár wrote:

On Sunday 07 May 2023 22:36:16 Pali Rohár wrote:

On Sunday 07 May 2023 12:45:11 Tom Rini wrote:

On Sun, May 07, 2023 at 04:56:04PM +0200, Pali Rohár wrote:

On Sunday 07 May 2023 10:40:44 Tom Rini wrote:

On Sun, May 07, 2023 at 04:01:04PM +0200, Pali Rohár wrote:

On Sunday 07 May 2023 09:54:52 Tom Rini wrote:

On Fri, May 05, 2023 at 09:37:10PM +0200, Pali Rohár wrote:

On Wednesday 03 May 2023 13:14:56 Tom Rini wrote:

On Wed, May 03, 2023 at 11:18:39AM +0200, Stefan Roese wrote:


Hi Tom,

please pull this next batch of mostly Marvell related patches:


NAK.  With commit:
commit 461fa17970de418a93832f734a595031c0b72128
Author: Pali Rohár 
Date:   Thu Apr 13 22:57:48 2023 +0200

  mmc: Read eMMC partition access bits before card reset

  eMMC specification in section "Access partitions" says that all reset
  events will restore the access bits in PARTITION_CONFIG CSD register to
  default User Data Area value (0b000).

  So read partition access bits from PARTITION_CONFIG CSD register before
  issuing card reset. This allows SPL/U-Boot to get information which eMMC
  partition was in use before SPL/U-Boot was booted. For some platforms this
  is the way how to determinate boot partition from which BootROM loaded 
SPL.

  Signed-off-by: Pali Rohár 

My am335x_evm now fails to boot with:

U-Boot SPL 2023.07-rc1-00021-g461fa17970de (May 03 2023 - 13:10:10 -0400)
Trying to boot from MMC1
omap_hsmmc_send_cmd: timedout waiting on cmd inhibit to clear
spl: mmc init failed with error: -110
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

I can provide more details / test patches as needed.

--
Tom


I do not know what to do with this... The only idea is to hide this code
behind CONFIG symbol and enable it only for mvebu. For example by this:


Well, maybe the problem is we're trying this on uSD cards? The failure I
reported was uSD and not eMMC.


Maybe it is that reason. Problem is that at this stage we do not know if
card is SD or MMC.

Martin, can you check if booting from SD card is working fine on mvebu
clearfog?


I see a failure with this commit on
rpi_3_32b, also from uSD boot.  This time it's:
Loading Environment from FAT... fsm 0, hsts 
fsm 0, hsts 
...

once in U-Boot itself.  Going to the commit prior to the above one and
the board is fine again.

--
Tom


Immediately after that "problematic code" is card reset function. So
another reason for failure is that card reset functionality does not
work correctly on your board / platform.


Well, we're at two different platforms and controllers that this change
breaks things on, so I'm not sure where the fault is exactly.  My
mx6cuboxi is still fine booting from uSD.  Another TI platform from the
same general era as am335x fails the same way (not a surprise), amlogic
libretech-cc is fine, pine64_plus is fine, and my newer TI platforms are
also fine with this.  So maybe the Kconfig is fine, but we just want
default y, default n if ARCH_OMAP2PLUS || ARCH_BCM283X (the TI platforms
that work are not ARCH_OMAP2PLUS).

--
Tom


And do you see this problem in SPL or in proper U-Boot?

If omap2plus is problematic then I can do tests on Nokia N900 or at its
qemu emulated version (to which can be attached gdb). But Nokia N900 is
without SPL.



OK, so on am335x_evm mine is setup so I can X/Y modem boot it before it
tries uSD.  In this case, full U-Boot also fails:
Loading Environment from FAT... omap_hsmmc_send_cmd: timedout waiting on
cmd inhibit to clear
** Bad device specification mmc 0 **

Note that N900 in QEMU passes, but I suspect that's a matter of the
emulator not being faithful to some undocumented bug/feature of the
chipset and that it would also fail like this on real HW or that we
aren't relying on MMC in such a way that the QEMU tests actually report
failure.  When I booted the above, it was not a lock-up since we can
continue on in this case, rather than failure to load U-Boot itself.


--
Tom


Ok, I have tested it on Nokia N900 HW and interesting is that SD card is
also working fine. But its initialization is slower and prints warning:

   omap_hsmmc_send_cmd: timeout waiting on cmd inhibit to clear


Ok, so what with it?


Seems like this change is a real bad idea to introduce on ARCH_OMAP2PLUS
platforms, and probably ARCH_BCM283X too, so rework with a Kconfig
option that defaults to on except for the above as I suggested?

--
Tom


Ok, patch is on the list... I'm curious if patch stay here on the list
more than one year like some other...


I mean, since I asked you to spin a 

[PATCH] video: hx8394: Add panel driver for hannstar,hsd060bhw4

[Ondřej Jirman]

From: Ondrej Jirman 

The driver is for panels based on the Himax HX8394 controller, such as the
HannStar HSD060BHW4 720x1440 TFT LCD panel that uses a MIPI-DSI interface.
This panel is used in Pinephone Pro.

Signed-off-by: Ondrej Jirman 
Cc: Anatolij Gustschin 
---
 drivers/video/Kconfig|   8 ++
 drivers/video/Makefile   |   1 +
 drivers/video/himax-hx8394.c | 237 +++
 3 files changed, 246 insertions(+)
 create mode 100644 drivers/video/himax-hx8394.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1e2f4e6de4a5..9efe69361ca6 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -477,6 +477,14 @@ config VIDEO_LCD_ENDEAVORU
  using the same DSI command sequence. The panel has a 720x1280
  resolution and uses 24 bit RGB per pixel.
 
+config VIDEO_LCD_HIMAX_HX8394
+   bool "Himax HX8394 DSI LCD panel support"
+   depends on PANEL && BACKLIGHT
+   select VIDEO_MIPI_DSI
+   help
+   Say Y here if you want to enable support for Himax HX8394
+   dsi 4dl panel.
+
 config VIDEO_LCD_ORISETECH_OTM8009A
bool "OTM8009A DSI LCD panel support"
select VIDEO_MIPI_DSI
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9a53cd141875..5dcc3fea08cb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_VIDEO_IPUV3) += imx/
 obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o
+obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
diff --git a/drivers/video/himax-hx8394.c b/drivers/video/himax-hx8394.c
new file mode 100644
index ..63637b4db022
--- /dev/null
+++ b/drivers/video/himax-hx8394.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Ondrej Jirman 
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct hx8394_panel_priv {
+   struct udevice *reg_vcc;
+   struct udevice *reg_iovcc;
+   struct gpio_desc reset;
+   struct udevice *backlight;
+};
+
+static const struct display_timing default_timing = {
+   .pixelclock.typ = 7425,
+   .hactive.typ= 720,
+   .hfront_porch.typ   = 40,
+   .hback_porch.typ= 40,
+   .hsync_len.typ  = 46,
+   .vactive.typ= 1440,
+   .vfront_porch.typ   = 7,
+   .vback_porch.typ= 9,
+   .vsync_len.typ  = 7,
+   .flags  = DISPLAY_FLAGS_VSYNC_LOW | 
DISPLAY_FLAGS_HSYNC_LOW,
+};
+
+#define dsi_dcs_write_seq(device, seq...) do { 
\
+   static const u8 d[] = { seq };  
\
+   int ret;
\
+   ret = mipi_dsi_dcs_write_buffer(device, d, ARRAY_SIZE(d));  
\
+   if (ret < 0)
\
+   return ret; 
\
+   } while (0)
+
+static int hx8394_init_sequence(struct udevice *dev)
+{
+   struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+   struct mipi_dsi_device *device = plat->device;
+   int ret;
+
+   dsi_dcs_write_seq(device, 0xb9, 0xff, 0x83, 0x94);
+   dsi_dcs_write_seq(device, 0xb1, 0x48, 0x11, 0x71, 0x09, 0x32, 0x24,
+ 0x71, 0x31, 0x55, 0x30);
+   dsi_dcs_write_seq(device, 0xba, 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
+   dsi_dcs_write_seq(device, 0xb2, 0x00, 0x80, 0x78, 0x0c, 0x07);
+   dsi_dcs_write_seq(device, 0xb4, 0x12, 0x63, 0x12, 0x63, 0x12, 0x63,
+ 0x01, 0x0c, 0x7c, 0x55, 0x00, 0x3f, 0x12, 0x6b, 0x12,
+ 0x6b, 0x12, 0x6b, 0x01, 0x0c, 0x7c);
+   dsi_dcs_write_seq(device, 0xd3, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c,
+ 0x00, 0x00, 0x32, 0x10, 0x09, 0x00, 0x09, 0x32, 0x15,
+ 0xad, 0x05, 0xad, 0x32, 0x00, 0x00, 0x00, 0x00, 0x37,
+ 0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00, 0x00, 0x0c, 0x40);
+   dsi_dcs_write_seq(device, 0xd5, 0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b,
+ 0x1a, 0x1a, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
+ 0x07, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x24, 0x25, 0x18,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18);
+   dsi_dcs_write_seq(device, 0xd6, 0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b,
+ 0x1a, 0x1a, 

modified UBoot to include I2C communication

[Andy Goh]

Dear Sir,
I am working on a project based on NXP's iMX8M mini board, to include I2C 
library in the UBoot , I had browse thru UBoot website below, could anyone 
kindly advise which source file to amend and what are the code to include for 
I2C? like CONFIG_SYS_NUM_I2C_BUSES etc... is the modification to be done on 
Yocto project?
Any help on source code or documentation are welcome, thanks.

https://source.denx.de/u-boot/u-boot/tree/master/

Cheers,
Andy
andy@stengg.com

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retain, monitor, and intercept email messages to and from our systems. Thank 
you.

[PATCH] mmc: rpmb: poll mmc status after sending rpmb request

[Ji Luo]

polling the mmc status to make sure the rpmb request has been
sent and the mmc is not in BUSY state. This avoids potential
rpmb request failure during rpmb data write.

Signed-off-by: Ji Luo 
---
 drivers/mmc/rpmb.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c
index b68d98573c..8bf19fd696 100644
--- a/drivers/mmc/rpmb.c
+++ b/drivers/mmc/rpmb.c
@@ -94,6 +94,7 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct 
s_rpmb *s,
struct mmc_cmd cmd = {0};
struct mmc_data data;
struct sdhci_host *host = mmc->priv;
+   int timeout_ms = 1000;
int ret;
 
ret = mmc_set_blockcount(mmc, count, is_rel_write);
@@ -123,6 +124,15 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct 
s_rpmb *s,
 #endif
return 1;
}
+
+   /* poll for the ready status */
+   if (mmc_poll_for_busy(mmc, timeout_ms)) {
+#ifdef CONFIG_MMC_RPMB_TRACE
+   printf("%s:mmc is busy!\n", __func__);
+#endif
+   return 1;
+   }
+
return 0;
 }
 static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s,
-- 
2.25.1

[PATCH v5 2/2] serial: zynqmp: Fetch baudrate from dtb and update

[Venkatesh Yadav Abbarapu]

From: Algapally Santosh Sagar 

The baudrate configured in .config is taken by default by serial. If
change of baudrate is required then the .config needs to changed and
u-boot recompilation is required or the u-boot environment needs to be
updated.

To avoid this, support is added to fetch the baudrate directly from the
device tree file and update.
The serial, prints the log with the configured baudrate in the dtb.
The commit c4df0f6f315c ("arm: mvebu: Espressobin: Set default value for
$fdtfile env variable") is taken as reference for changing the default
environment variable.

The default environment stores the default baudrate value, When default
baudrate and dtb baudrate are not same glitches are seen on the serial.
So, the environment also needs to be updated with the dtb baudrate to
avoid the glitches on the serial.

Signed-off-by: Algapally Santosh Sagar 
Signed-off-by: Venkatesh Yadav Abbarapu 
---
 doc/README.serial_dt_baud  | 41 +
 drivers/core/ofnode.c  | 20 
 drivers/serial/Kconfig |  9 
 drivers/serial/serial-uclass.c | 42 ++
 include/dm/ofnode.h| 14 ++--
 include/env_default.h  |  6 -
 include/serial.h   | 15 
 7 files changed, 144 insertions(+), 3 deletions(-)
 create mode 100644 doc/README.serial_dt_baud

diff --git a/doc/README.serial_dt_baud b/doc/README.serial_dt_baud
new file mode 100644
index 00..02974ab1a7
--- /dev/null
+++ b/doc/README.serial_dt_baud
@@ -0,0 +1,41 @@
+Fetch serial baudrate from DT
+-
+
+To support fetching of baudrate from DT, the following is done:-
+
+The baudrate configured in Kconfig symbol CONFIG_BAUDRATE is taken by default 
by serial.
+If change of baudrate is required then the Kconfig symbol CONFIG_BAUDRATE 
needs to
+changed and U-Boot recompilation is required or the U-Boot environment needs 
to be updated.
+
+To avoid this, add support to fetch the baudrate directly from the device tree 
file and
+update the environment.
+
+The default environment stores the default baudrate value. When default 
baudrate and dtb
+baudrate are not same glitches are seen on the serial.
+So, the environment also needs to be updated with the dtb baudrate to avoid 
the glitches on
+the serial which is enabled by SERIAL_DT_BAUD.
+
+The Kconfig SPL_ENV_SUPPORT needs to be enabled to allow patching in SPL.
+
+The Kconfig DEFAULT_ENV_IS_RW which is enabled by SERIAL_DT_BAUD with making 
the environment
+writable.
+
+The ofnode_read_baud() function parses and fetches the baudrate value from the 
DT. This value
+is validated and updated to baudrate during serial init. Padding is added at 
the end of the
+default environment and the dt baudrate is updated with the latest value.
+
+Example:-
+
+The serial port options are of the form "pnf", where "" is the baud 
rate, "p" is parity ("n", "o", or "e"),
+"n" is number of bits, and "f" is flow control ("r" for RTS or omit it). 
Default is "115200n8".
+
+chosen {
+   bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused 
root=/dev/ram0 rw init_fatal_sh=1";
+   stdout-path = "serial0:115200n8";
+   };
+
+From the chosen node, stdout-path property is obtained as string.
+
+   stdout-path = "serial0:115200n8";
+
+The string is parsed to get the baudrate 115200. This string is converted to 
integer and updated to the environment.
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index ec574c4460..04bdb30b24 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -870,6 +870,26 @@ ofnode ofnode_get_chosen_node(const char *name)
return ofnode_path(prop);
 }
 
+#ifdef CONFIG_OF_SERIAL_DT_BAUD
+int ofnode_read_baud(void)
+{
+   const char *str, *p;
+   u32 baud;
+
+   str = ofnode_read_chosen_string("stdout-path");
+   if (!str)
+   return -EINVAL;
+
+   /* Parse string serial0:115200n8 */
+   p = strchr(str, ':');
+   if (!p)
+   return -EINVAL;
+
+   baud = dectoul(p + 1, NULL);
+   return baud;
+}
+#endif
+
 const void *ofnode_read_aliases_prop(const char *propname, int *sizep)
 {
ofnode node;
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 5c9b924e73..ea2244e5db 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -24,6 +24,15 @@ config BAUDRATE
  in the SPL stage (most drivers) or for choosing a default baudrate
  in the absence of an environment setting (serial_mxc.c).
 
+config OF_SERIAL_DT_BAUD
+   bool "Fetch serial baudrate from device tree"
+   depends on DM_SERIAL && SPL_ENV_SUPPORT
+   select DEFAULT_ENV_IS_RW
+   help
+ Select this to enable fetching and setting of the baudrate
+ configured in the DT. Replace the default baudrate with the DT
+ baudrate and also set it to the environment.
+
 config 

[PATCH v5 0/2] Add support to fetch baudrate from dtb

[Venkatesh Yadav Abbarapu]

In this patch series
- Add support in Kconfig and convert for armada boards
- Fetch baudrate from the dtb and update

Changes in v5:
- Adding DEFAULT_ENV_IS_RW Kconfig in missing files
- Updating DEFAULT_ENV_IS_RW to CONFIG_DEFAULT_ENV_IS_RW

Changes in v4:
- Moved SERIAL_DT_BAUD to another patch
- Added doc file for fetching serial baudrate from DT.
- Changed Kconfig SERIAL_DT_BAUD to OF_SERIAL_DT_BAUD
- Added function docs wherever required.
- Moved changes from fdtdec api to ofnode
- Changed serial_get_valid_baudrate to check_valid_baudrate
- Added function fetch_baud_from_dtb to fetch baud from DT
- Used dectoul() for parsing baudrate

Changes in v3:
- Add SERIAL_DT_BAUD to Kconfig
- Moved DEFAULT_ENV_IS_RW to Kconfig also updated armada files
- Moved filler changes from zynqmp.h to generic file env_default.h
- Removed ENV_RW_FILLER and added padding in the generic file env_default.h.
- Print baudrate parameter properly when SERIAL_DT is enabled.

Changes in v2:
- Changed to #ifdef from #if CONFIG_IS_ENABLED to enable patching in
spl.
- Added SPL_ENV_SUPPORT dependency in SERIAL_DT_BAUD to allow SPL
compilation.
- Moved DEFAULT_ENV_IS_RW to Kconfig also updated armada files
- Moved ENV_RW_FILLER to generic file env_default.h.
- Increased the ENV_RW_FILLER padding to support 800 baud.

Algapally Santosh Sagar (2):
  configs: Add support in Kconfig and convert for armada boards
  serial: zynqmp: Fetch baudrate from dtb and update

 configs/eDPU_defconfig  |  1 +
 configs/mvebu_db-88f3720_defconfig  |  1 +
 configs/mvebu_espressobin-88f3720_defconfig |  1 +
 configs/uDPU_defconfig  |  1 +
 doc/README.serial_dt_baud   | 41 
 drivers/core/ofnode.c   | 20 ++
 drivers/serial/Kconfig  | 15 
 drivers/serial/serial-uclass.c  | 42 +
 include/configs/mvebu_armada-37xx.h |  1 -
 include/dm/ofnode.h | 14 ++-
 include/env_default.h   |  8 +++-
 include/env_internal.h  |  2 +-
 include/serial.h| 15 
 13 files changed, 156 insertions(+), 6 deletions(-)
 create mode 100644 doc/README.serial_dt_baud

-- 
2.17.1

[PATCH v5 1/2] configs: Add support in Kconfig and convert for armada boards

[Venkatesh Yadav Abbarapu]

From: Algapally Santosh Sagar 

The DEFAULT_ENV_IS_RW is moved to the Kconfig for easier configuration.
Hence, the CONFIG_DEFAULT_ENV_IS_RW config is added to the defconfig files
to allow enabling them for armada boards.

Signed-off-by: Algapally Santosh Sagar 
Signed-off-by: Venkatesh Yadav Abbarapu 
---
 configs/eDPU_defconfig  | 1 +
 configs/mvebu_db-88f3720_defconfig  | 1 +
 configs/mvebu_espressobin-88f3720_defconfig | 1 +
 configs/uDPU_defconfig  | 1 +
 drivers/serial/Kconfig  | 6 ++
 include/configs/mvebu_armada-37xx.h | 1 -
 include/env_default.h   | 2 +-
 include/env_internal.h  | 2 +-
 8 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/configs/eDPU_defconfig b/configs/eDPU_defconfig
index 77ea2b2eec..61fb9bd2a5 100644
--- a/configs/eDPU_defconfig
+++ b/configs/eDPU_defconfig
@@ -21,6 +21,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_USE_PREBOOT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DEFAULT_ENV_IS_RW=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/mvebu_db-88f3720_defconfig 
b/configs/mvebu_db-88f3720_defconfig
index 829567014f..e6fb80167a 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -22,6 +22,7 @@ CONFIG_USE_PREBOOT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DEFAULT_ENV_IS_RW=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/mvebu_espressobin-88f3720_defconfig 
b/configs/mvebu_espressobin-88f3720_defconfig
index fc394a7e9d..64ee99d64b 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -24,6 +24,7 @@ CONFIG_USE_PREBOOT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DEFAULT_ENV_IS_RW=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig
index fa1989518b..4d3d53ac7e 100644
--- a/configs/uDPU_defconfig
+++ b/configs/uDPU_defconfig
@@ -21,6 +21,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_USE_PREBOOT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DEFAULT_ENV_IS_RW=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SYS_MAXARGS=32
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f4767c838f..5c9b924e73 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -24,6 +24,12 @@ config BAUDRATE
  in the SPL stage (most drivers) or for choosing a default baudrate
  in the absence of an environment setting (serial_mxc.c).
 
+config DEFAULT_ENV_IS_RW
+   bool "Make default environment as writable"
+   help
+ Select this to enable to make default environment writable. This
+ allows modifying the default environment.
+
 config REQUIRE_SERIAL_CONSOLE
bool "Require a serial port for console"
# Running without a serial console is not supported by the
diff --git a/include/configs/mvebu_armada-37xx.h 
b/include/configs/mvebu_armada-37xx.h
index 76e148f55e..18b55be0d8 100644
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -30,7 +30,6 @@
 /*
  * Environment
  */
-#define DEFAULT_ENV_IS_RW  /* required for configuring default 
fdtfile= */
 
 #ifdef CONFIG_MMC
 #define BOOT_TARGET_DEVICES_MMC(func, i) func(MMC, mmc, i)
diff --git a/include/env_default.h b/include/env_default.h
index b16c22d5a2..227cad7c34 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -21,7 +21,7 @@ env_t embedded_environment __UBOOT_ENV_SECTION__(environment) 
= {
{
 #elif defined(DEFAULT_ENV_INSTANCE_STATIC)
 static char default_environment[] = {
-#elif defined(DEFAULT_ENV_IS_RW)
+#elif defined(CONFIG_DEFAULT_ENV_IS_RW)
 char default_environment[] = {
 #else
 const char default_environment[] = {
diff --git a/include/env_internal.h b/include/env_internal.h
index 6a69494646..fcb464263f 100644
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -89,7 +89,7 @@ typedef struct environment_s {
 extern env_t embedded_environment;
 #endif /* ENV_IS_EMBEDDED */
 
-#ifdef DEFAULT_ENV_IS_RW
+#ifdef CONFIG_DEFAULT_ENV_IS_RW
 extern char default_environment[];
 #else
 extern const char default_environment[];
-- 
2.17.1

[PATCH] video: rockchip: Add support for RK3399 to dw-mipi-dsi bridge

[Ondřej Jirman]

From: Ondrej Jirman 

This just needs some extra clocks enabled, and different registers
configured. Copied from Linux, just like the original submitter
of this driver did for rk3568.

Tested on Pinephone Pro.

Signed-off-by: Ondrej Jirman 
Cc: Anatolij Gustschin 
Cc: Simon Glass 
Cc: Philipp Tomsich 
Cc: Kever Yang 
Cc: Chris Morgan 
---
 drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 99 +++
 1 file changed, 99 insertions(+)

diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c 
b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index 1bb1c7c67d07..9ec3a48bf2a5 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -134,6 +134,32 @@
 #define HS_RX_CONTROL_OF_LANE_20x84
 #define HS_RX_CONTROL_OF_LANE_30x94
 
+#define DW_MIPI_NEEDS_PHY_CFG_CLK  BIT(0)
+#define DW_MIPI_NEEDS_GRF_CLK  BIT(1)
+
+#define RK3399_GRF_SOC_CON20   0x6250
+#define RK3399_DSI0_LCDC_SEL   BIT(0)
+#define RK3399_DSI1_LCDC_SEL   BIT(4)
+
+#define RK3399_GRF_SOC_CON22   0x6258
+#define RK3399_DSI0_TURNREQUEST(0xf << 12)
+#define RK3399_DSI0_TURNDISABLE(0xf << 8)
+#define RK3399_DSI0_FORCETXSTOPMODE(0xf << 4)
+#define RK3399_DSI0_FORCERXMODE(0xf << 0)
+
+#define RK3399_GRF_SOC_CON23   0x625c
+#define RK3399_DSI1_TURNDISABLE(0xf << 12)
+#define RK3399_DSI1_FORCETXSTOPMODE(0xf << 8)
+#define RK3399_DSI1_FORCERXMODE(0xf << 4)
+#define RK3399_DSI1_ENABLE (0xf << 0)
+
+#define RK3399_GRF_SOC_CON24   0x6260
+#define RK3399_TXRX_MASTERSLAVEZ   BIT(7)
+#define RK3399_TXRX_ENABLECLK  BIT(6)
+#define RK3399_TXRX_BASEDIRBIT(5)
+#define RK3399_TXRX_SRC_SEL_ISP0   BIT(4)
+#define RK3399_TXRX_TURNREQUESTGENMASK(3, 0)
+
 #define RK3568_GRF_VO_CON2 0x0368
 #define RK3568_DSI0_SKEWCALHS  (0x1f << 11)
 #define RK3568_DSI0_FORCETXSTOPMODE(0xf << 4)
@@ -209,6 +235,8 @@ struct dw_rockchip_dsi_priv {
 
struct clk *pclk;
struct clk *ref;
+   struct clk *grf_clk;
+   struct clk *phy_cfg_clk;
struct reset_ctl *rst;
unsigned int lane_mbps; /* per lane */
u16 input_div;
@@ -844,6 +872,28 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
}
}
 
+   if (cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
+   priv->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
+   if (IS_ERR(priv->phy_cfg_clk)) {
+   ret = PTR_ERR(priv->phy_cfg_clk);
+   dev_err(dev, "phy_cfg_clk clock get error %d\n", ret);
+   return ret;
+   }
+
+   clk_enable(priv->phy_cfg_clk);
+   }
+
+   if (cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
+   priv->grf_clk = devm_clk_get(dev, "grf");
+   if (IS_ERR(priv->grf_clk)) {
+   ret = PTR_ERR(priv->grf_clk);
+   dev_err(dev, "grf_clk clock get error %d\n", ret);
+   return ret;
+   }
+
+   clk_enable(priv->grf_clk);
+   }
+
priv->rst = devm_reset_control_get_by_index(device->dev, 0);
if (IS_ERR(priv->rst)) {
ret = PTR_ERR(priv->rst);
@@ -864,6 +914,52 @@ struct video_bridge_ops dw_mipi_dsi_rockchip_ops = {
.set_backlight = dw_mipi_dsi_rockchip_set_bl,
 };
 
+static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
+   {
+   .reg = 0xff96,
+   .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
+   .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
+   .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
+   RK3399_DSI0_LCDC_SEL),
+
+   .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
+   .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
+RK3399_DSI0_TURNDISABLE |
+RK3399_DSI0_FORCETXSTOPMODE |
+RK3399_DSI0_FORCERXMODE),
+
+   .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
+   .max_data_lanes = 4,
+   },
+   {
+   .reg = 0xff968000,
+   .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
+   .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
+   .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
+   RK3399_DSI1_LCDC_SEL),
+
+   .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
+   .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
+RK3399_DSI1_FORCETXSTOPMODE |
+RK3399_DSI1_FORCERXMODE |

[PATCH] i2c: rockchip: De-initialize the bus after start bit failure

[Ondřej Jirman]

From: Ondrej Jirman 

Failure can happen when i2c is used without initializing pinctrl properly,
which U-Boot happily allows in SPL. Without this fix, further I2C access would
fail, even after proper pinctrl initialization.

Signed-off-by: Ondrej Jirman 
Cc: Heiko Schocher 
---
 drivers/i2c/rk_i2c.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c
index f8fac45b6ca0..9927af94a80b 100644
--- a/drivers/i2c/rk_i2c.c
+++ b/drivers/i2c/rk_i2c.c
@@ -342,7 +342,7 @@ static int rockchip_i2c_xfer(struct udevice *bus, struct 
i2c_msg *msg,
 int nmsgs)
 {
struct rk_i2c *i2c = dev_get_priv(bus);
-   int ret;
+   int ret = 0;
 
debug("i2c_xfer: %d messages\n", nmsgs);
for (; nmsgs > 0; nmsgs--, msg++) {
@@ -356,14 +356,15 @@ static int rockchip_i2c_xfer(struct udevice *bus, struct 
i2c_msg *msg,
}
if (ret) {
debug("i2c_write: error sending\n");
-   return -EREMOTEIO;
+   ret = -EREMOTEIO;
+   break;
}
}
 
rk_i2c_send_stop_bit(i2c);
rk_i2c_disable(i2c);
 
-   return 0;
+   return ret;
 }
 
 int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
-- 
2.40.1

[PATCH] video: console: Fix default font selection

[Ondřej Jirman]

From: Ondrej Jirman 

Some callers expect to call this with NULL font name to select the
default font (eg. boot/scene.c). Without handling the NULL condition
U-Boot crashes instead of displaying a bootflow GUI menu.

Signed-off-by: Ondrej Jirman 
Cc: Anatolij Gustschin 
---
 drivers/video/console_core.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c
index 1f93b1b85fa5..b5d0e3dceca3 100644
--- a/drivers/video/console_core.c
+++ b/drivers/video/console_core.c
@@ -201,6 +201,12 @@ int console_simple_select_font(struct udevice *dev, const 
char *name, uint size)
 {
struct video_fontdata *font;
 
+   if (!name) {
+   if (fonts->name)
+   console_set_font(dev, fonts);
+   return 0;
+   }
+
for (font = fonts; font->name; font++) {
if (!strcmp(name, font->name)) {
console_set_font(dev, font);
-- 
2.40.1

Re: [PATCH] ARM: stm32: Add IWDG handling into PSCI suspend code

[Patrick DELAUNAY]

Hi

On 5/12/23 15:55, Marek Vasut wrote:

On 5/12/23 15:43, Patrick DELAUNAY wrote:

Hi,


Hi,


+    /* Ping IWDG2 and ACK pretimer IRQ */
+    if (iwdg2_wake) {
+    writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
+    writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
+    }
+    }
    writel(0x3, STM32_RCC_BASE + RCC_MP_SREQCLRR);
  ddr_sw_self_refresh_exit();



Reviewed-by: Patrice Chotard 


I feel like maybe I need to whack the IWDG also BEFORE entering 
suspend, expect a V2 shortly.


Do you think this IWDG approach is fine to keep the system from 
rebooting in suspend ? Or do you see any better option for the MP1 ?



I think it is fine if you want to have watchdog running in STANDBY 
even this patch force a wakeup.


but if IWDG 1 or 2 should be not running in STANDBY (but also for 
STOP) for your product,


Why ?

I want the watchdog to monitor that the platform is still OK, even in 
suspend. Also, as far as I can tell, once the IWDG is started, it 
cannot be stopped, right ?



without change OTP (so with the default behavior)

=> yes the watchdog IWDG is running without way to stop it.





it can be managed directly by the hardware with OTP, to freeze watchdog.

=> it is a decision for each product of the desired behavior of the 
IWDG in low power mode.



See Ref Manual: 48.3 IWDG implementation

Table 332. STM32MP157x IWDG features

Option bytes to control the activity in Standby mode (6)

6. Controlled via option bytes OTP_IWDG1_FZ_STANDBY and 
OTP_IWDG2_FZ_STANDBY, respectively, for IWDG1 and IWDG2.


and in Table17 => OTP 18 = HW2 bit 5 to 8


I saw the OTP fuses, but I don't want to blow them. Or is that really 
the suggestion ST would provide for suspend/resume, blow the fuses ?


(I wonder, why isn't the logic of those fuses inverted then, i.e. by 
default stop the watchdog in suspend AND blow fuses to keep it running 
in suspend?)



it is a SoC design choice => the default behavior is watchdog is running 
in standby and stop, so you need to reload it


That imply the limit of the duration of max duration of standby to avoid 
reset


and the usage of IWDG pre-timeout in this case it a good place to wakeup 
the SoC


and add sanity checks (check the system is still running) before to 
reload it.



Patrick

Re: [PATCH] riscv: add backtrace support

[Ben Dooks]

On 15/05/2023 14:03, Ben Dooks wrote:

When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the culprit.

Since this adds size to the build, do not add it by default
and avoid putting it in the SPL build if not needed.


Hi, has anyone had time to review this?

As a note, my sifive.com address may go soon, so please
add ben.do...@codethink.co.uk to any followups.


Signed-off-by: Ben Dooks 
---
  arch/riscv/Kconfig  | 10 ++
  arch/riscv/Makefile |  4 
  arch/riscv/cpu/start.S  |  1 +
  arch/riscv/lib/interrupts.c | 35 +++
  4 files changed, 50 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f6ed05906a..3f2316cfb5 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -98,6 +98,16 @@ config ARCH_RV64I
  
  endchoice
  
+config FRAMEPOINTER

+   bool "Build with frame pointer for stack unwinding"
+   help
+ Choose this option to use the frame pointer so the stack can be
+ unwound if needed. This is useful for tracing where faults came
+ from as the source may be several functions back
+
+ If you say Y here, then the code size will be increased due to
+ having to store the fp.
+
  choice
prompt "Code Model"
default CMODEL_MEDLOW
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 4963b5109b..0cb60c7c7e 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -45,6 +45,10 @@ endif
  ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
 -mcmodel=$(CMODEL)
  
+ifeq ($(CONFIG_$(SPL_)FRAMEPOINTER),y)

+   ARCH_FLAGS += -fno-omit-frame-pointer
+endif
+
  PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
  CFLAGS_EFI+= $(ARCH_FLAGS)
  
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S

index dad22bfea8..3d13722615 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -396,6 +396,7 @@ call_board_init_r:
   */
mv  a0, s3  /* gd_t */
mv  a1, s4  /* dest_addr */
+   mv  s0, zero/* fp == NULL */
  
  /*

   * jump to it ...
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index e966afa7e3..db3d7e294b 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -53,6 +53,40 @@ static void show_regs(struct pt_regs *regs)
  #endif
  }
  
+#if defined(CONFIG_FRAMEPOINTER) || defined(CONFIG_SPL_FRAMEPOINTER)

+static void show_backtrace(struct pt_regs *regs)
+{
+   uintptr_t *fp = (uintptr_t *)regs->s0;
+   unsigned count = 0;
+   ulong ra;
+
+   printf("backtrace:\n");
+
+   /* there are a few entry points where the s0 register is
+* set to gd, so to avoid changing those, just abort if
+* the value is the same */
+   while (fp != NULL && fp != (uintptr_t *)gd) {
+   ra = fp[-1];
+   printf("backtrace %2d: FP: " REG_FMT " RA: " REG_FMT,
+  count, (ulong)fp, ra);
+
+   if (gd && gd->flags & GD_FLG_RELOC)
+   printf(" - RA: " REG_FMT " reloc adjusted\n",
+   ra - gd->reloc_off);
+   else
+   printf("\n");
+
+   fp = (uintptr_t *)fp[-2];
+   count++;
+   }
+}
+#else
+static void show_backtrace(struct pt_regs *regs)
+{
+   printf("No backtrace support enabled\n");
+}
+#endif
+
  /**
   * instr_len() - get instruction length
   *
@@ -119,6 +153,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, 
struct pt_regs *regs)
   epc - gd->reloc_off, regs->ra - gd->reloc_off);
  
  	show_regs(regs);

+   show_backtrace(regs);
show_code(epc);
show_efi_loaded_images(epc);
panic("\n");


--
Ben Dooks   http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

Re: riscv: asm update for building ubifs

[Ben Dooks]

On 05/05/2023 09:02, Ben Dooks wrote:

Fix misisng atomic and test_and_{set,clear}_bit macros to allow
the ubi/ubifs code to be built for riscv. These are fairly simple
but are not being used outside of ubifs on our builds.


Has anyone had a chance to review these for merging?

I may be losing the ben.do...@sifive.com address soon,
so please cc ben.do...@codethink.co.uk in further discussions


Ben Dooks (3):
   riscv: add generic link for 
   riscv: implement local_irq_{save,restore} macros
   riscv: define test_and_{set,clear}_bit in asm/bitops.h

  arch/riscv/include/asm/atomic.h | 14 ++
  arch/riscv/include/asm/bitops.h |  3 +++
  arch/riscv/include/asm/system.h | 15 +++
  3 files changed, 28 insertions(+), 4 deletions(-)
  create mode 100644 arch/riscv/include/asm/atomic.h



--
Ben Dooks   http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

[PATCH v2] PCI: zynqmp: Add ZynqMP NWL PCIe root port driver

[Stefan Roese]

This patch adds the PCIe controller driver for the Xilinx / AMD ZynqMP
NWL PCIe Bridge as root port. The driver source is partly copied from
the Linux PCI driver and modified to enable usage in U-Boot (e.g.
simplified and interrupt support removed).

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Pali Rohár 
Cc: Bin Meng 
Cc: Michal Simek 
---
v2:
- Remove some unused members from struct nwl_pcie
- Fix usage of dev_seq() in nwl_pcie_config_address()
- Remove writing to PCI_PRIMARY_BUS reg as this is done by the
  common U-Boot PCI code later

 MAINTAINERS   |   1 +
 drivers/pci/Kconfig   |   7 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pcie-xilinx-nwl.c | 352 ++
 4 files changed, 361 insertions(+)
 create mode 100644 drivers/pci/pcie-xilinx-nwl.c

diff --git a/MAINTAINERS b/MAINTAINERS
index c8f72e9ec6a2..2bc19d9daa75 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -343,6 +343,7 @@ F:  drivers/rtc/armada38x.c
 F: drivers/spi/kirkwood_spi.c
 F: drivers/spi/mvebu_a3700_spi.c
 F: drivers/pci/pcie_dw_mvebu.c
+F: drivers/pci/pcie-xilinx-nwl.c
 F: drivers/watchdog/armada-37xx-wdt.c
 F: drivers/watchdog/orion_wdt.c
 F: include/configs/mv-common.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d26525b..60d98d14640d 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -374,4 +374,11 @@ config PCIE_UNIPHIER
  Say Y here if you want to enable PCIe controller support on
  UniPhier SoCs.
 
+config PCIE_XILINX_NWL
+   bool "Xilinx NWL PCIe controller"
+   depends on ARCH_ZYNQMP
+   help
+Say 'Y' here if you want support for Xilinx / AMD NWL PCIe
+controller as Root Port.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 49506e7ba59b..11f60c6991d9 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
 obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
diff --git a/drivers/pci/pcie-xilinx-nwl.c b/drivers/pci/pcie-xilinx-nwl.c
new file mode 100644
index ..7ef2bdf57b56
--- /dev/null
+++ b/drivers/pci/pcie-xilinx-nwl.c
@@ -0,0 +1,352 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host bridge driver for Xilinx / AMD ZynqMP NWL PCIe Bridge
+ *
+ * Based on the Linux driver which is:
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Author: Stefan Roese 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Bridge core config registers */
+#define BRCFG_PCIE_RX0 0x
+#define BRCFG_PCIE_RX1 0x0004
+#define BRCFG_INTERRUPT0x0010
+#define BRCFG_PCIE_RX_MSG_FILTER   0x0020
+
+/* Egress - Bridge translation registers */
+#define E_BREG_CAPABILITIES0x0200
+#define E_BREG_CONTROL 0x0208
+#define E_BREG_BASE_LO 0x0210
+#define E_BREG_BASE_HI 0x0214
+#define E_ECAM_CAPABILITIES0x0220
+#define E_ECAM_CONTROL 0x0228
+#define E_ECAM_BASE_LO 0x0230
+#define E_ECAM_BASE_HI 0x0234
+
+#define I_ISUB_CONTROL 0x03E8
+#define SET_ISUB_CONTROL   BIT(0)
+/* Rxed msg fifo  - Interrupt status registers */
+#define MSGF_MISC_STATUS   0x0400
+#define MSGF_MISC_MASK 0x0404
+#define MSGF_LEG_STATUS0x0420
+#define MSGF_LEG_MASK  0x0424
+#define MSGF_MSI_STATUS_LO 0x0440
+#define MSGF_MSI_STATUS_HI 0x0444
+#define MSGF_MSI_MASK_LO   0x0448
+#define MSGF_MSI_MASK_HI   0x044C
+
+/* Msg filter mask bits */
+#define CFG_ENABLE_PM_MSG_FWD  BIT(1)
+#define CFG_ENABLE_INT_MSG_FWD BIT(2)
+#define CFG_ENABLE_ERR_MSG_FWD BIT(3)
+#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD |\
+CFG_ENABLE_INT_MSG_FWD |   \
+CFG_ENABLE_ERR_MSG_FWD)
+
+/* Misc interrupt status mask bits */
+#define MSGF_MISC_SR_RXMSG_AVAIL   BIT(0)
+#define MSGF_MISC_SR_RXMSG_OVERBIT(1)
+#define MSGF_MISC_SR_SLAVE_ERR BIT(4)
+#define MSGF_MISC_SR_MASTER_ERRBIT(5)
+#define MSGF_MISC_SR_I_ADDR_ERRBIT(6)
+#define MSGF_MISC_SR_E_ADDR_ERRBIT(7)
+#define MSGF_MISC_SR_FATAL_AER BIT(16)
+#define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
+#define MSGF_MISC_SR_CORR_AER  BIT(18)
+#define MSGF_MISC_SR_UR_DETECT BIT(20)
+#define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
+#define MSGF_MISC_SR_FATAL_DEV BIT(23)

[PATCH v4 11/11] configs: starfive: Enable ID EEPROM configuration

[Yanhong Wang]

Enabled ID_EEPROM and I2C configuration for StarFive VisionFive2 board.

Signed-off-by: Yanhong Wang 
---
 configs/starfive_visionfive2_defconfig | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index c57708199d..570a1f53a1 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="StarFive #"
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
+CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK=0x818
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -23,6 +24,7 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
 CONFIG_CMODEL_MEDANY=y
 CONFIG_RISCV_SMODE=y
+# CONFIG_OF_BOARD_FIXUP is not set
 CONFIG_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_QSPI_BOOT=y
@@ -34,6 +36,8 @@ CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr 
${fdtcontroladdr};"
 CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=5
 CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x0
 CONFIG_SPL_BSS_START_ADDR=0x804
@@ -45,21 +49,34 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x40
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_I2C=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_EEPROM_SIZE=512
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_OF_BOARD=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
-# CONFIG_I2C is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SPL_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0X50
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_SPL_MMC_HS400_SUPPORT=y
 CONFIG_MMC_DW=y
-- 
2.17.1

[PATCH v4 10/11] configs: starfive: Enable ethernet configuration for StarFive VisionFive2

[Yanhong Wang]

Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet
function for StarFive VisionFive 2 board,including versions 1.2A and
1.3B.

Signed-off-by: Yanhong Wang 
---
 configs/starfive_visionfive2_defconfig | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index ffbc4b9476..c57708199d 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000
 CONFIG_SF_DEFAULT_SPEED=1
 CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
 CONFIG_SPL_TEXT_BASE=0x800
 CONFIG_SYS_PROMPT="StarFive #"
 CONFIG_OF_LIBFDT_OVERLAY=y
@@ -31,7 +31,7 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
 CONFIG_USE_PREBOOT=y
 CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
-CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_SPL_MAX_SIZE=0x4
@@ -54,6 +54,8 @@ CONFIG_SYS_BOOTM_LEN=0x400
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
@@ -66,6 +68,13 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_STARFIVE=y
+CONFIG_RGMII=y
+CONFIG_RMII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
-- 
2.17.1

[PATCH v4 09/11] doc: board: starfive: Reword the make defconfig information

[Yanhong Wang]

The defconfig file name for StarFive VisionFive2 has been changed, and
the documentation description has also changed.

Signed-off-by: Yanhong Wang 
---
 doc/board/starfive/visionfive2.rst | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/doc/board/starfive/visionfive2.rst 
b/doc/board/starfive/visionfive2.rst
index 4d43ac9729..951e0d80fb 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -62,7 +62,7 @@ Now build the U-Boot SPL and U-Boot proper
 .. code-block:: console
 
cd 
-   make starfive_visionfive2_13b_defconfig
+   make starfive_visionfive2_defconfig
make 
OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
 
 This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
@@ -118,7 +118,7 @@ Program the SD card
sudo cp u-boot.itb /mnt/
sudo cp Image.gz /mnt/
sudo cp initramfs.cpio.gz /mnt/
-   sudo cp jh7110-starfive-visionfive-2-v1.3b.dtb /mnt/
+   sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
sudo umount /mnt
 
 Booting
@@ -264,7 +264,7 @@ Sample boot log from StarFive VisionFive2 board
 
StarFive #fatload mmc 1:3 ${kernel_addr_r} Image.gz
6429424 bytes read in 394 ms (15.6 MiB/s)
-   StarFive #fatload mmc 1:3 ${fdt_addr_r} 
jh7110-starfive-visionfive-2-v1.3b.dtb
+   StarFive #fatload mmc 1:3 ${fdt_addr_r} jh7110-starfive-visionfive-2.dtb
11285 bytes read in 5 ms (2.2 MiB/s)
StarFive #fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
152848495 bytes read in 9271 ms (15.7 MiB/s)
-- 
2.17.1

[PATCH v4 07/11] riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B

[Yanhong Wang]

The difference between 1.2A and 1.3B is dynamically configured according
to the PCB version, and there is no difference on the board device tree,
so the same DT file can be used.

Signed-off-by: Yanhong Wang 
---
 arch/riscv/dts/Makefile   |  3 +-
 ... jh7110-starfive-visionfive-2-u-boot.dtsi} | 25 ++-
 .../jh7110-starfive-visionfive-2-v1.2a.dts| 12 
 ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 ---
 ...b.dts => jh7110-starfive-visionfive-2.dts} |  3 +-
 5 files changed, 26 insertions(+), 86 deletions(-)
 rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi => 
jh7110-starfive-visionfive-2-u-boot.dtsi} (66%)
 delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
 delete mode 100644 
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
 rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts => 
jh7110-starfive-visionfive-2.dts} (65%)

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 79a58694f5..7940fe466d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,8 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += 
jh7110-starfive-visionfive-2-v1.3b.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += 
jh7110-starfive-visionfive-2-v1.2a.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
 include $(srctree)/scripts/Makefile.dts
 
 targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
similarity index 66%
rename from arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
rename to arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 3c322c5c97..2afcec30b8 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0 OR MIT
 /*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
  */
 
 #include "binman.dtsi"
@@ -67,3 +67,26 @@
};
 };
 
+ {
+   itb {
+   fit {
+   images {
+   fdt-1 {
+   description = "NAME";
+   load = <0x4040>;
+   compression = "none";
+
+   uboot_fdt_blob: blob-ext {
+   filename = "u-boot.dtb";
+   };
+   };
+   };
+
+   configurations {
+   conf-1 {
+   fdt = "fdt-1";
+   };
+   };
+   };
+   };
+};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts 
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
deleted file mode 100644
index b9d26d7af7..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-/dts-v1/;
-#include "jh7110-starfive-visionfive-2.dtsi"
-
-/ {
-   model = "StarFive VisionFive 2 v1.2A";
-   compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
-};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
deleted file mode 100644
index 3c322c5c97..00
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-#include "binman.dtsi"
-#include "jh7110-u-boot.dtsi"
-/ {
-   chosen {
-   bootph-pre-ram;
-   };
-
-   firmware {
-   spi0 = 
-   bootph-pre-ram;
-   };
-
-   config {
-   bootph-pre-ram;
-   u-boot,spl-payload-offset = <0x10>;
-   };
-
-   memory@4000 {
-   bootph-pre-ram;
-   };
-};
-
- {
-   bootph-pre-ram;
-};
-
- {
-   bootph-pre-ram;
-};
-
- {
-   bootph-pre-ram;
-};
-
- {
-   bootph-pre-ram;
-
-   nor-flash@0 {
-   bootph-pre-ram;
-   };
-};
-
- {
-   bootph-pre-ram;
-};
-
-_pins {
-   bootph-pre-ram;
-   mmc0-pins-rest {
-   bootph-pre-ram;
-   };
-};
-
-_pins {
-   bootph-pre-ram;
-   mmc1-pins0 {
-   bootph-pre-ram;
-   };
-
-   

[PATCH v4 08/11] riscv: dts: starfive: Add support eeprom device tree node

[Yanhong Wang]

Add support "atmel,24c04" eeprom for StarFive VisionFive2 board.

Signed-off-by: Yanhong Wang 
---
 .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi   | 14 ++
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi   |  8 +++-
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 2afcec30b8..13f69da31e 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -67,6 +67,20 @@
};
 };
 
+_pins {
+   bootph-pre-ram;
+   i2c-pins {
+   bootph-pre-ram;
+   };
+};
+
+ {
+   bootph-pre-ram;
+   eeprom@50 {
+   bootph-pre-ram;
+   };
+};
+
  {
itb {
fit {
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index 0272369b24..710b082766 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -120,6 +120,12 @@
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "okay";
+
+   eeprom@50 {
+   compatible = "atmel,24c04";
+   reg = <0x50>;
+   pagesize = <16>;
+   };
 };
 
  {
@@ -350,4 +356,4 @@
reg = <0>;
};
};
-};
\ No newline at end of file
+};
-- 
2.17.1

[PATCH v4 06/11] riscv: dts: jh7110: Add ethernet device tree nodes

[Yanhong Wang]

Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.

Signed-off-by: Yanhong Wang 
---
 .../dts/jh7110-starfive-visionfive-2.dtsi | 34 +
 arch/riscv/dts/jh7110.dtsi| 69 +++
 2 files changed, 103 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..0272369b24 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -17,6 +17,8 @@
i2c2 = 
i2c5 = 
i2c6 = 
+   ethernet0 = 
+   ethernet1 = 
};
 
chosen {
@@ -317,3 +319,35 @@
assigned-clock-parents = <>;
assigned-clock-rates = <0>;
 };
+
+ {
+   phy-handle = <>;
+   phy-mode = "rgmii-id";
+   status = "okay";
+
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+   };
+};
+
+ {
+   phy-handle = <>;
+   phy-mode = "rgmii-id";
+   status = "okay";
+
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+
+   phy1: ethernet-phy@1 {
+   reg = <0>;
+   };
+   };
+};
\ No newline at end of file
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..58e332e9d7 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -235,6 +235,13 @@
#clock-cells = <0>;
};
 
+   stmmac_axi_setup: stmmac-axi-config {
+   snps,lpi_en;
+   snps,wr_osr_lmt = <4>;
+   snps,rd_osr_lmt = <4>;
+   snps,blen = <256 128 64 32 0 0 0>;
+   };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -539,6 +546,68 @@
status = "disabled";
};
 
+   gmac0: ethernet@1603 {
+   compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+   reg = <0x0 0x1603 0x0 0x1>;
+   clocks = < JH7110_AONCLK_GMAC0_AXI>,
+< JH7110_AONCLK_GMAC0_AHB>,
+< JH7110_SYSCLK_GMAC0_PTP>,
+< JH7110_AONCLK_GMAC0_TX_INV>,
+< JH7110_SYSCLK_GMAC0_GTXC>;
+   clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+   resets = < JH7110_AONRST_GMAC0_AXI>,
+< JH7110_AONRST_GMAC0_AHB>;
+   reset-names = "stmmaceth", "ahb";
+   interrupts = <7>, <6>, <5>;
+   interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+   snps,multicast-filter-bins = <64>;
+   snps,perfect-filter-entries = <8>;
+   rx-fifo-depth = <2048>;
+   tx-fifo-depth = <2048>;
+   snps,fixed-burst;
+   snps,no-pbl-x8;
+   snps,force_thresh_dma_mode;
+   snps,axi-config = <_axi_setup>;
+   snps,tso;
+   snps,en-tx-lpi-clockgating;
+   snps,txpbl = <16>;
+   snps,rxpbl = <16>;
+   starfive,syscon = <_syscon 0xc 0x12>;
+   status = "disabled";
+   };
+
+   gmac1: ethernet@1604 {
+   compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
+   reg = <0x0 0x1604 0x0 0x1>;
+   clocks = < JH7110_SYSCLK_GMAC1_AXI>,
+< JH7110_SYSCLK_GMAC1_AHB>,
+< JH7110_SYSCLK_GMAC1_PTP>,
+< JH7110_SYSCLK_GMAC1_TX_INV>,
+< JH7110_SYSCLK_GMAC1_GTXC>;
+   clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "gtx";
+   resets = < JH7110_SYSRST_GMAC1_AXI>,
+< JH7110_SYSRST_GMAC1_AHB>;
+   reset-names = "stmmaceth", "ahb";
+   interrupts = <78>, <77>, <76>;
+   interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+   snps,multicast-filter-bins = <64>;
+   snps,perfect-filter-entries = <8>;
+   rx-fifo-depth = <2048>;
+   tx-fifo-depth = <2048>;
+   snps,fixed-burst;
+

[PATCH v4 05/11] board: starfive: Dynamic configuration of DT for 1.2A and 1.3B

[Yanhong Wang]

The main difference between StarFive VisionFive 2 1.2A and 1.3B is gmac.
You can read the PCB version of the current board by
get_pcb_revision_from_eeprom(), and then dynamically configure the
difference of gmac in spl_perform_fixups() according to different PCB
versions, so that one DT and one defconfig can support both 1.2A and
1.3B versions, which is more user-friendly.

Signed-off-by: Yanhong Wang 
---
 board/starfive/visionfive2/spl.c  | 157 ++
 .../visionfive2/starfive_visionfive2.c|  13 ++
 2 files changed, 170 insertions(+)

diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index db0b4cb433..7acd3995aa 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -5,16 +5,173 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
 #define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
 #define JH7110_CLK_CPU_ROOT_SHIFT  24
 #define JH7110_CLK_CPU_ROOT_MASK   GENMASK(29, 24)
 
+struct starfive_vf2_pro {
+   const char *path;
+   const char *name;
+   const char *value;
+};
+
+static const struct starfive_vf2_pro starfive_vera[] = {
+   {"/soc/ethernet@1603/mdio/ethernet-phy@0", "rx-internal-delay-ps",
+   "1900"},
+   {"/soc/ethernet@1603/mdio/ethernet-phy@0", "tx-internal-delay-ps",
+   "1350"}
+};
+
+static const struct starfive_vf2_pro starfive_verb[] = {
+   {"/soc/ethernet@1603", "starfive,tx-use-rgmii-clk", NULL},
+   {"/soc/ethernet@1604", "starfive,tx-use-rgmii-clk", NULL},
+
+   {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+   "motorcomm,tx-clk-adj-enabled", NULL},
+   {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+   "motorcomm,tx-clk-100-inverted", NULL},
+   {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+   "motorcomm,tx-clk-1000-inverted", NULL},
+   {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+   "rx-internal-delay-ps", "1900"},
+   {"/soc/ethernet@1603/mdio/ethernet-phy@0",
+   "tx-internal-delay-ps", "1500"},
+
+   {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+   "motorcomm,tx-clk-adj-enabled", NULL},
+   { "/soc/ethernet@1604/mdio/ethernet-phy@1",
+   "motorcomm,tx-clk-100-inverted", NULL},
+   {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+   "rx-internal-delay-ps", "0"},
+   {"/soc/ethernet@1604/mdio/ethernet-phy@1",
+   "tx-internal-delay-ps", "0"},
+};
+
+void spl_fdt_fixup_version_a(void *fdt)
+{
+   u32 phandle;
+   u8 i;
+   int offset;
+   int ret;
+
+   fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+  "StarFive VisionFive 2 v1.2A");
+
+   offset = fdt_path_offset(fdt, "/soc/clock-controller@1302");
+   phandle = fdt_get_phandle(fdt, offset);
+   offset = fdt_path_offset(fdt, "/soc/ethernet@1604");
+
+   fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+   fdt_appendprop_u32(fdt, offset, "assigned-clocks", 
JH7110_SYSCLK_GMAC1_TX);
+   fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle);
+   fdt_appendprop_u32(fdt, offset, "assigned-clocks", 
JH7110_SYSCLK_GMAC1_RX);
+
+   fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
+   fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
+  JH7110_SYSCLK_GMAC1_RMII_RTX);
+   fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
+   fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
+  JH7110_SYSCLK_GMAC1_RMII_RTX);
+
+   fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@1604"),
+  "phy-mode", "rmii");
+
+   for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) {
+   offset = fdt_path_offset(fdt, starfive_vera[i].path);
+
+   if (starfive_vera[i].value)
+   ret = fdt_setprop_u32(fdt, offset,  
starfive_vera[i].name,
+ dectoul(starfive_vera[i].value, 
NULL));
+   else
+   ret = fdt_setprop_empty(fdt, offset, 
starfive_vera[i].name);
+
+   if (ret) {
+   pr_err("%s set prop %s fail.\n", __func__, 
starfive_vera[i].name);
+   break;
+   }
+   }
+}
+
+void spl_fdt_fixup_version_b(void *fdt)
+{
+   u32 phandle;
+   u8 i;
+   int offset;
+   int ret;
+
+   fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+  "StarFive VisionFive 2 v1.3B");
+
+   /* gmac0 */
+   offset = fdt_path_offset(fdt, "/soc/clock-controller@1700");
+   phandle = fdt_get_phandle(fdt, offset);
+   offset = 

[PATCH v4 03/11] eeprom: starfive: Enable ID EEPROM configuration

[Yanhong Wang]

Enabled ID_EEPROM configuration for StarFive VisionFive2 board.

Signed-off-by: Yanhong Wang 
---
 arch/riscv/include/asm/arch-jh7110/eeprom.h   |  13 +
 board/starfive/visionfive2/Makefile   |   1 +
 .../visionfive2/visionfive2-i2c-eeprom.c  | 561 ++
 3 files changed, 575 insertions(+)
 create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h
 create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c

diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h 
b/arch/riscv/include/asm/arch-jh7110/eeprom.h
new file mode 100644
index 00..f354d5c60c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#ifndef _ASM_RISCV_EEPROM_H
+#define _ASM_RISCV_EEPROM_H
+
+u8 get_pcb_revision_from_eeprom(void);
+u32 get_ddr_size_from_eeprom(void);
+
+#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/board/starfive/visionfive2/Makefile 
b/board/starfive/visionfive2/Makefile
index 66c854df39..c7ba4f7ed6 100644
--- a/board/starfive/visionfive2/Makefile
+++ b/board/starfive/visionfive2/Makefile
@@ -5,3 +5,4 @@
 
 obj-y  := starfive_visionfive2.o
 obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_ID_EEPROM) += visionfive2-i2c-eeprom.o
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c 
b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
new file mode 100644
index 00..befe7888c4
--- /dev/null
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define FORMAT_VERSION 0x2
+#define PCB_VERSION0xB1
+#define BOM_VERSION'A'
+/*
+ * BYTES_PER_EEPROM_PAGE: the 24FC04H datasheet says that data can
+ * only be written in page mode, which means 16 bytes at a time:
+ * 16-Byte Page Write Buffer
+ */
+#define BYTES_PER_EEPROM_PAGE  16
+
+/*
+ * EEPROM_WRITE_DELAY_MS: the 24FC04H datasheet says it takes up to
+ * 5ms to complete a given write:
+ * Write Cycle Time (byte or page) ro Page Write Time 5 ms, Maximum
+ */
+#define EEPROM_WRITE_DELAY_MS  5000
+/*
+ * StarFive OUI. Registration Date is 20xx-xx-xx
+ */
+#define STARFIVE_OUI_PREFIX"6C:CF:39:"
+#define STARFIVE_DEFAULT_MAC0  "6C:CF:39:6C:DE:AD"
+#define STARFIVE_DEFAULT_MAC1  "6C:CF:39:6C:DE:AE"
+
+/* Magic number at the first four bytes of EEPROM HATs */
+#define STARFIVE_EEPROM_HATS_SIG   "SFVF" /* StarFive VisionFive */
+
+#define STARFIVE_EEPROM_HATS_SIZE_MAX  256 /* Header + Atom1&4(v1) */
+#define STARFIVE_EEPROM_WP_OFFSET  0 /* Read only field */
+#define STARFIVE_EEPROM_ATOM1_PSTR "VF7110A1-2228-D008E000-0001\0"
+#define STARFIVE_EEPROM_ATOM1_PSTR_SIZE32
+#define STARFIVE_EEPROM_ATOM1_SN_OFFSET23
+#define STARFIVE_EEPROM_ATOM1_VSTR "StarFive Technology Co., Ltd.\0\0\0"
+#define STARFIVE_EEPROM_ATOM1_VSTR_SIZE32
+
+#define MAGIC_NUMBER_BYTES 4
+#define MAC_ADDR_BYTES 6
+#define MAC_ADDR_STRLEN17
+
+/*
+ * Atom Types
+ * 0x = invalid
+ * 0x0001 = vendor info
+ * 0x0002 = GPIO map
+ * 0x0003 = Linux device tree blob
+ * 0x0004 = manufacturer custom data
+ * 0x0005-0xfffe = reserved for future use
+ * 0x = invalid
+ */
+
+#define HATS_ATOM_INVALID  0x
+#define HATS_ATOM_VENDOR   0x0001
+#define HATS_ATOM_GPIO 0x0002
+#define HATS_ATOM_DTB  0x0003
+#define HATS_ATOM_CUSTOM   0x0004
+#define HATS_ATOM_INVALID_END  0x
+
+struct eeprom_header {
+   char signature[MAGIC_NUMBER_BYTES]; /* ASCII table signature */
+   u8 version; /* EEPROM data format version */
+   /* (0x00 reserved, 0x01 = first version) */
+   u8 reversed;/* 0x00, Reserved field */
+   u16 numatoms;   /* total atoms in EEPROM */
+   u32 eeplen; /* total length in bytes of all eeprom data */
+   /* (including this header) */
+};
+
+struct eeprom_atom_header {
+   u16 type;
+   u16 count;
+   u32 dlen;
+};
+
+struct eeprom_atom1_data {
+   u8 uuid[16];
+   u16 pid;
+   u16 pver;
+   u8 vslen;
+   u8 pslen;
+   uchar vstr[STARFIVE_EEPROM_ATOM1_VSTR_SIZE];
+   uchar pstr[STARFIVE_EEPROM_ATOM1_PSTR_SIZE]; /* product SN */
+};
+
+struct starfive_eeprom_atom1 {
+   struct eeprom_atom_header header;
+   struct eeprom_atom1_data data;
+   u16 crc;
+};
+
+struct eeprom_atom4_data {
+   u16 version;
+   u8 pcb_revision;/* PCB version */
+   u8 bom_revision;/* BOM version */
+   u8 mac0_addr[MAC_ADDR_BYTES];   /* Ethernet0 MAC */
+   u8 mac1_addr[MAC_ADDR_BYTES];   

[PATCH v4 04/11] ram: starfive: Read memory size information from EEPROM

[Yanhong Wang]

StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.

If there is no information in EEPROM, it is initialized with the default
size defined in DT.

Signed-off-by: Yanhong Wang 
---
 arch/riscv/cpu/jh7110/spl.c | 32 -
 drivers/ram/starfive/starfive_ddr.c |  2 --
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 104f0fe949..72adcefa0e 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -3,19 +3,49 @@
  * Copyright (C) 2022 StarFive Technology Co., Ltd.
  * Author: Yanhong Wang
  */
-
+#include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 
 #define CSR_U74_FEATURE_DISABLE0x7c1
 #define L2_LIM_MEM_END 0x81FUL
 
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool check_ddr_size(phys_size_t size)
+{
+   switch (size) {
+   case SZ_2:
+   case SZ_4:
+   case SZ_8:
+   case SZ_16:
+   return true;
+   default:
+   return false;
+   }
+}
+
 int spl_soc_init(void)
 {
int ret;
struct udevice *dev;
+   phys_size_t size;
+
+   ret = fdtdec_setup_mem_size_base();
+   if (ret)
+   return ret;
+
+   /* Read the definition of the DDR size from eeprom, and if not,
+* use the definition in DT
+*/
+   size = (get_ddr_size_from_eeprom() >> 16) & 0xFF;
+   if (check_ddr_size(size))
+   gd->ram_size = size << 30;
 
/* DDR init */
ret = uclass_get_device(UCLASS_RAM, 0, );
diff --git a/drivers/ram/starfive/starfive_ddr.c 
b/drivers/ram/starfive/starfive_ddr.c
index 553f2ce6f4..a0a3d6b33d 100644
--- a/drivers/ram/starfive/starfive_ddr.c
+++ b/drivers/ram/starfive/starfive_ddr.c
@@ -72,8 +72,6 @@ static int starfive_ddr_probe(struct udevice *dev)
u64 rate;
int ret;
 
-   /* Read memory base and size from DT */
-   fdtdec_setup_mem_size_base();
priv->info.base = gd->ram_base;
priv->info.size = gd->ram_size;
 
-- 
2.17.1

[PATCH v4 00/11] Add ethernet driver for StarFive JH7110 SoC

[Yanhong Wang]

This series of patches base on the latest branch/master,and
adds ethernet support for the StarFive JH7110 RISC-V SoC.
The series includes EEPROM, PHY and MAC drivers. The PHY model is
YT8531 (from Motorcomm Inc), and the MAC version is dwmac-5.20
(from Synopsys DesignWare). 

The implementation of the phy driver is ported from linux, but it
has been adjusted for the u-boot framework.

EEPROM stores board-related information, such as DDR capacity, 
PCB version, MAC address, etc.

The main difference between StarFive VisionFive 2 1.2A and 1.3B is 
gmac, but the difference in gmac is not defined in DT, but reads the 
PCB version from EEPROM, and then dynamically configures the difference
of gmac according to different PCB versions, which is compatible 
with 1.2A and 1.3B versions, which is more user-friendly.

The PHY and MAC driver has been tested on the StarFive VisionFive 2 1.2A
and 1.3B boards and works normally.

For more information and support,you can visit RVspace wiki[1]. 
[1] https://wiki.rvspace.org/

v4:
- Reworded the definition of the 'pbuf' variable in visionfive2-i2c-eeprom.c 
  from a const pointer to const union. 
- Added the section (".data") attribute to the 'pbuf' and 'has_been_read' 
global 
  variables in visionfive2-i2-eeprom.c.

v3:
- Added EEPROM support.
- Combine the board device tree of 1.2A and 1.3B into one.
- Removed the delay configuration of gmac phy clock from DT.
- Dynamically configure gmac differences of 1.2A and 1.3B to DT according to 
the PCB version.
- DDR capacity information is read from EEPROM first, if not, it is defined by 
default in DT.

v2:
- Reworded the phy driver. Added platform private data struct to save the 
  configuration data read from dts.
- Reworded the MAC driver. Added platform private data struct to save the 
  configuration data read from dts.

Previous versions:
v1 - 
https://patchwork.ozlabs.org/project/uboot/cover/20230317010536.17860-1-yanhong.w...@starfivetech.com/
v2 - 
https://patchwork.ozlabs.org/project/uboot/cover/20230329102720.25439-1-yanhong.w...@starfivetech.com/
v3 - 
https://patchwork.ozlabs.org/project/uboot/cover/20230428022515.29393-1-yanhong.w...@starfivetech.com/


Yanhong Wang (11):
  net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
  net: dwc_eth_qos: Add StarFive ethernet driver glue layer
  eeprom: starfive: Enable ID EEPROM configuration
  ram: starfive: Read memory size information from EEPROM
  board: starfive: Dynamic configuration of DT for 1.2A and 1.3B
  riscv: dts: jh7110: Add ethernet device tree nodes
  riscv: dts: jh7110: Combine the board device tree files of 1.2A and
1.3B
  riscv: dts: starfive: Add support eeprom device tree node
  doc: board: starfive:　Reword the make defconfig information
  configs: starfive: Enable ethernet configuration for StarFive
VisionFive2
  configs: starfive: Enable ID EEPROM configuration

 arch/riscv/cpu/jh7110/spl.c   |  32 +-
 arch/riscv/dts/Makefile   |   3 +-
 ... jh7110-starfive-visionfive-2-u-boot.dtsi} |  39 +-
 .../jh7110-starfive-visionfive-2-v1.2a.dts|  12 -
 ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi |  69 ---
 ...b.dts => jh7110-starfive-visionfive-2.dts} |   3 +-
 .../dts/jh7110-starfive-visionfive-2.dtsi |  40 ++
 arch/riscv/dts/jh7110.dtsi|  69 +++
 arch/riscv/include/asm/arch-jh7110/eeprom.h   |  13 +
 board/starfive/visionfive2/Makefile   |   1 +
 board/starfive/visionfive2/spl.c  | 157 +
 .../visionfive2/starfive_visionfive2.c|  13 +
 .../visionfive2/visionfive2-i2c-eeprom.c  | 561 ++
 configs/starfive_visionfive2_defconfig|  32 +-
 doc/board/starfive/visionfive2.rst|   6 +-
 drivers/net/Kconfig   |   7 +
 drivers/net/Makefile  |   1 +
 drivers/net/dwc_eth_qos.c |   6 +
 drivers/net/dwc_eth_qos.h |   1 +
 drivers/net/dwc_eth_qos_starfive.c| 249 
 drivers/net/phy/Kconfig   |   6 +
 drivers/net/phy/Makefile  |   1 +
 drivers/net/phy/motorcomm.c   | 437 ++
 drivers/ram/starfive/starfive_ddr.c   |   2 -
 24 files changed, 1665 insertions(+), 95 deletions(-)
 rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi => 
jh7110-starfive-visionfive-2-u-boot.dtsi} (58%)
 delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
 delete mode 100644 
arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
 rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts => 
jh7110-starfive-visionfive-2.dts} (65%)
 create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h
 create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c
 create mode 100644 drivers/net/dwc_eth_qos_starfive.c
 create mode 100644 drivers/net/phy/motorcomm.c


base-commit: 62df7a39442902a71259568c13a4d496d5a514f4

[PATCH v4 02/11] net: dwc_eth_qos: Add StarFive ethernet driver glue layer

[Yanhong Wang]

The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.

Signed-off-by: Yanhong Wang 
Reviewed-by: Ramon Fried 
---
 drivers/net/Kconfig|   7 +
 drivers/net/Makefile   |   1 +
 drivers/net/dwc_eth_qos.c  |   6 +
 drivers/net/dwc_eth_qos.h  |   1 +
 drivers/net/dwc_eth_qos_starfive.c | 249 +
 5 files changed, 264 insertions(+)
 create mode 100644 drivers/net/dwc_eth_qos_starfive.c

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 09039a283e..5540f0ea18 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
  The Synopsys Designware Ethernet QOS IP block with specific
  configuration used in Qcom QCS404 SoC.
 
+config DWC_ETH_QOS_STARFIVE
+   bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
+   depends on DWC_ETH_QOS
+   help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in STARFIVE  JH7110 soc.
+
 config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46a40e2ed9..d4af253b6f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
 obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
 obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
 obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
+obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
 obj-$(CONFIG_E1000) += e1000.o
 obj-$(CONFIG_E1000_SPI) += e1000_spi.o
 obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9bbba6eed0..1e92bd9ca9 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1725,6 +1725,12 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)_qcom_config
},
 #endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
+   {
+   .compatible = "starfive,jh7110-dwmac",
+   .data = (ulong)_jh7110_config
+   },
+#endif
 
{ }
 };
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index fddbe9336c..a6b719af80 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
 
 extern struct eqos_config eqos_imx_config;
 extern struct eqos_config eqos_qcom_config;
+extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_starfive.c 
b/drivers/net/dwc_eth_qos_starfive.c
new file mode 100644
index 00..5be8ac0f1a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "dwc_eth_qos.h"
+
+#define STARFIVE_DWMAC_PHY_INFT_RGMII  0x1
+#define STARFIVE_DWMAC_PHY_INFT_RMII   0x4
+#define STARFIVE_DWMAC_PHY_INFT_FIELD  0x7U
+
+struct starfive_platform_data {
+   struct regmap *regmap;
+   struct reset_ctl_bulk resets;
+   struct clk_bulk clks;
+   phy_interface_t interface;
+   u32 offset;
+   u32 shift;
+   bool tx_use_rgmii_clk;
+};
+
+static int eqos_interface_init_jh7110(struct udevice *dev)
+{
+   struct eth_pdata *pdata = dev_get_plat(dev);
+   struct starfive_platform_data *data = pdata->priv_pdata;
+   struct ofnode_phandle_args args;
+   unsigned int mode;
+   int ret;
+
+   switch (data->interface) {
+   case PHY_INTERFACE_MODE_RMII:
+   mode = STARFIVE_DWMAC_PHY_INFT_RMII;
+   break;
+
+   case PHY_INTERFACE_MODE_RGMII:
+   case PHY_INTERFACE_MODE_RGMII_ID:
+   mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
+   break;
+
+   default:
+   return -EINVAL;
+   }
+
+   ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
+2, 0, );
+   if (ret)
+   return ret;
+
+   if (args.args_count != 2)
+   return -EINVAL;
+
+   data->offset = args.args[0];
+   data->shift = args.args[1];
+   data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
+   if (IS_ERR(data->regmap)) {
+   ret = PTR_ERR(data->regmap);
+   pr_err("Failed to get regmap: %d\n", ret);
+   return ret;
+   }
+
+   return regmap_update_bits(data->regmap, data->offset,
+ STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
+ mode << data->shift);
+}
+
+static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
+{
+   struct eqos_priv *eqos = dev_get_priv(dev);
+   struct eth_pdata *pdata = 

[PATCH v4 01/11] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy

[Yanhong Wang]

Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
verified the driver on StarFive VisionFive2 board.

Signed-off-by: Yanhong Wang 
Reviewed-by: Ramon Fried 
---
 drivers/net/phy/Kconfig |   6 +
 drivers/net/phy/Makefile|   1 +
 drivers/net/phy/motorcomm.c | 437 
 3 files changed, 444 insertions(+)
 create mode 100644 drivers/net/phy/motorcomm.c

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 24158776f5..0c3c39a550 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -220,6 +220,12 @@ config PHY_MICREL_KSZ8XXX
 
 endif # PHY_MICREL
 
+config PHY_MOTORCOMM
+   tristate "Motorcomm PHYs"
+   help
+ Enables support for Motorcomm network PHYs.
+ Currently supports the YT8531 Gigabit Ethernet PHYs.
+
 config PHY_MSCC
bool "Microsemi Corp Ethernet PHYs support"
 
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 85d17f109c..2487f366e1 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o
 obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
 obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
 obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
+obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o
 obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
 obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
 obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
new file mode 100644
index 00..e822fd76f2
--- /dev/null
+++ b/drivers/net/phy/motorcomm.c
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Motorcomm 8531 PHY driver.
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PHY_ID_YT8531  0x4f51e91b
+#define PHY_ID_MASKGENMASK(31, 0)
+
+/* Extended Register's Address Offset Register */
+#define YTPHY_PAGE_SELECT  0x1E
+
+/* Extended Register's Data Register */
+#define YTPHY_PAGE_DATA0x1F
+
+#define YTPHY_SYNCE_CFG_REG0xA012
+
+#define YTPHY_DTS_OUTPUT_CLK_DIS   0
+#define YTPHY_DTS_OUTPUT_CLK_25M   2500
+#define YTPHY_DTS_OUTPUT_CLK_125M  12500
+
+#define YT8531_SCR_SYNCE_ENABLEBIT(6)
+/* 1b0 output 25m clock   *default*
+ * 1b1 output 125m clock
+ */
+#define YT8531_SCR_CLK_FRE_SEL_125MBIT(4)
+#define YT8531_SCR_CLK_SRC_MASKGENMASK(3, 1)
+#define YT8531_SCR_CLK_SRC_PLL_125M0
+#define YT8531_SCR_CLK_SRC_UTP_RX  1
+#define YT8531_SCR_CLK_SRC_SDS_RX  2
+#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL  3
+#define YT8531_SCR_CLK_SRC_REF_25M 4
+#define YT8531_SCR_CLK_SRC_SSC_25M 5
+
+/* 1b0 use original tx_clk_rgmii  *default*
+ * 1b1 use inverted tx_clk_rgmii.
+ */
+#define YT8531_RC1R_TX_CLK_SEL_INVERTEDBIT(14)
+#define YT8531_RC1R_RX_DELAY_MASK  GENMASK(13, 10)
+#define YT8531_RC1R_FE_TX_DELAY_MASK   GENMASK(7, 4)
+#define YT8531_RC1R_GE_TX_DELAY_MASK   GENMASK(3, 0)
+#define YT8531_RC1R_RGMII_0_000_NS 0
+#define YT8531_RC1R_RGMII_0_150_NS 1
+#define YT8531_RC1R_RGMII_0_300_NS 2
+#define YT8531_RC1R_RGMII_0_450_NS 3
+#define YT8531_RC1R_RGMII_0_600_NS 4
+#define YT8531_RC1R_RGMII_0_750_NS 5
+#define YT8531_RC1R_RGMII_0_900_NS 6
+#define YT8531_RC1R_RGMII_1_050_NS 7
+#define YT8531_RC1R_RGMII_1_200_NS 8
+#define YT8531_RC1R_RGMII_1_350_NS 9
+#define YT8531_RC1R_RGMII_1_500_NS 10
+#define YT8531_RC1R_RGMII_1_650_NS 11
+#define YT8531_RC1R_RGMII_1_800_NS 12
+#define YT8531_RC1R_RGMII_1_950_NS 13
+#define YT8531_RC1R_RGMII_2_100_NS 14
+#define YT8531_RC1R_RGMII_2_250_NS 15
+
+/* Phy gmii clock gating Register */
+#define YT8531_CLOCK_GATING_REG0xC
+#define YT8531_CGR_RX_CLK_EN   BIT(12)
+
+/* Specific Status Register */
+#define YTPHY_SPECIFIC_STATUS_REG  0x11
+#define YTPHY_DUPLEX_MASK  BIT(13)
+#define YTPHY_DUPLEX_SHIFT 13
+#define YTPHY_SPEED_MODE_MASK  GENMASK(15, 14)
+#define YTPHY_SPEED_MODE_SHIFT 14
+
+#define YT8531_EXTREG_SLEEP_CONTROL1_REG   0x27
+#define YT8531_ESC1R_SLEEP_SW  BIT(15)
+#define YT8531_ESC1R_PLLON_SLP BIT(14)
+
+#define YT8531_RGMII_CONFIG1_REG   0xA003
+
+#define YT8531_CHIP_CONFIG_REG 0xA001
+#define YT8531_CCR_SW_RST  BIT(15)
+/* 1b0 disable 1.9ns rxc clock delay  *default*
+ * 1b1 enable 1.9ns rxc clock delay
+ */
+#define YT8531_CCR_RXC_DLY_EN  

eMMC errors on RK3588 (rock5b)

[Eugen Hristev]

Hi Jonas,

I tried some basic eMMC read/write commands, and in my setup with 
rock5b, it fails at single/multiple block read/write , even if 
sometimes, the initial read works fine.


Here is some log :


=> mmc read 0x5000 64 1
CMD_SEND:0
ARG  0x
MMC_RSP_NONE
CMD_SEND:8
ARG  0x01aa
RET  -110
CMD_SEND:55
ARG  0x
RET  -110
CMD_SEND:0
ARG  0x
MMC_RSP_NONE
CMD_SEND:1
ARG  0x
MMC_RSP_R3,4 0x40ff8080
CMD_SEND:1
ARG  0x4006
MMC_RSP_R3,4 0x40ff8080
CMD_SEND:1
ARG  0x4006
MMC_RSP_R3,4 0x40ff8080
CMD_SEND:1
ARG  0x4006
MMC_RSP_R3,4 0xc0ff8080
CMD_SEND:2
ARG  0x
MMC_RSP_R2   0x15010042
 0x4a544434
 0x5203d923
 0x738d5900

DUMPING DATA
000 - 15 01 00 42
004 - 4a 54 44 34
008 - 52 03 d9 23
012 - 73 8d 59 00
CMD_SEND:3
ARG  0x0001
MMC_RSP_R1,5,6,7 0x0500
CMD_SEND:9
ARG  0x0001
MMC_RSP_R2   0xd0270132
 0x0f5903ff
 0xf6dbffef
 0x8e404000

DUMPING DATA
000 - d0 27 01 32
004 - 0f 59 03 ff
008 - f6 db ff ef
012 - 8e 40 40 00
CMD_SEND:7
ARG  0x0001
MMC_RSP_R1,5,6,7 0x0700
CMD_SEND:8
ARG  0x
MMC_RSP_R1,5,6,7 0x0900
CMD_SEND:6
ARG  0x03b70200
MMC_RSP_R1b  0x0900
CMD_SEND:13
ARG  0x0001
MMC_RSP_R1,5,6,7 0x0900
CURR STATE:4
CMD_SEND:6
ARG  0x03b90100
MMC_RSP_R1b  0x0900
CMD_SEND:13
ARG  0x0001
MMC_RSP_R1,5,6,7 0x0900
CURR STATE:4
CMD_SEND:6
ARG  0x03b70600
MMC_RSP_R1b  0x0900
CMD_SEND:13
ARG  0x0001
MMC_RSP_R1,5,6,7 0x0900
CURR STATE:4
CMD_SEND:8
ARG  0x
MMC_RSP_R1,5,6,7 0x0900

MMC read: dev # 0, block # 100, count 1 ... CMD_SEND:17
ARG  0x0064
MMC_RSP_R1,5,6,7 0x0900
1 blocks read: OK
=> mmc write 0x5000 64 1

MMC write: dev # 0, block # 100, count 1 ... mmc bwrite1
mmc bwrite2
CMD_SEND:17
ARG  0x
MMC_RSP_R1,5,6,7 0x0900
CMD_SEND:18
ARG  0x0040
MMC_RSP_R1,5,6,7 0x0900
CMD_SEND:12
ARG  0x
MMC_RSP_R1b  0x0b00
CMD_SEND:18
ARG  0x0002
MMC_RSP_R1,5,6,7 0x0900
CMD_SEND:12
ARG  0x
MMC_RSP_R1b  0x0b00
mmc bwrite3
CMD_SEND:24
ARG  0x0064
RET  -70
mmc write failed
0 blocks written: ERROR
=> mmc write 0x5000 64 5

MMC write: dev # 0, block # 100, count 5 ... mmc bwrite1
mmc bwrite2
mmc bwrite3
CMD_SEND:25
ARG  0x0064
RET  -70
mmc write failed
0 blocks written: ERROR
=> mmc read 0x5000 64 5

MMC read: dev # 0, block # 100, count 5 ... CMD_SEND:18
ARG  0x0064
RET  -110
0 blocks read: ERROR
=> mmc read 0x5000 64 1

MMC read: dev # 0, block # 100, count 1 ... CMD_SEND:17
ARG   

Re: [RFC PATCH v8 12/23] cli: Enables using hush 2021 parser as command line parser

[Patrick DELAUNAY]

Hi,

On 5/13/23 03:19, Heinrich Schuchardt wrote:

On 5/12/23 22:03, Francis Laniel wrote:
If one defines HUSH_2021_PARSER, it is then possible to use 2021 
parser with:

=> cli get
old
=> cli set 2021
=> cli get
2021


We don't need such a command. Just allow only one parser.



For information I made the same remarks on the config in V5

https://lore.kernel.org/all/7222357.bo2iyVLy2q@machine/


it seems a temporally solution for test the 2 parsers with a binary




Best regards

Heinrich



Patrick

[PATCH] mkimage: ecdsa: password for signing from environment

[Stefano Babic]

Use a variable (MKIMAGE_SIGN_PASSWORD) like already done for RSA to
allow the signing process to run in batch.

Signed-off-by: Stefano Babic 
---
 lib/ecdsa/ecdsa-libcrypto.c | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/lib/ecdsa/ecdsa-libcrypto.c b/lib/ecdsa/ecdsa-libcrypto.c
index d5939af2c5..5fa9be10b4 100644
--- a/lib/ecdsa/ecdsa-libcrypto.c
+++ b/lib/ecdsa/ecdsa-libcrypto.c
@@ -111,16 +111,30 @@ static size_t ecdsa_key_size_bytes(const EC_KEY *key)
return EC_GROUP_order_bits(group) / 8;
 }
 
+static int default_password(char *buf, int size, int rwflag, void *u)
+{
+   strncpy(buf, (char *)u, size);
+   buf[size - 1] = '\0';
+   return strlen(buf);
+}
+
 static int read_key(struct signer *ctx, const char *key_name)
 {
FILE *f = fopen(key_name, "r");
+   const char *key_pass;
 
if (!f) {
fprintf(stderr, "Can not get key file '%s'\n", key_name);
return -ENOENT;
}
 
-   ctx->evp_key = PEM_read_PrivateKey(f, NULL, NULL, NULL);
+   key_pass = getenv("MKIMAGE_SIGN_PASSWORD");
+   if (key_pass) {
+   ctx->evp_key = PEM_read_PrivateKey(f, NULL, default_password, 
(void *)key_pass);
+
+   } else {
+   ctx->evp_key = PEM_read_PrivateKey(f, NULL, NULL, NULL);
+   }
fclose(f);
if (!ctx->evp_key) {
fprintf(stderr, "Can not read key from '%s'\n", key_name);
-- 
2.34.1

Re: [PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

[Patrick DELAUNAY]

Hi Marek,

On 5/18/23 00:02, Marek Vasut wrote:

In case the DHSOM is in suspend state and either reset button is pushed
or IWDG2 triggers a watchdog reset, then DRAM initialization could fail
as follows:

   "
   RAM: DDR3L 32bits 2x4Gb 533MHz
   DDR invalid size : 0x4, expected 0x4000
   DRAM init failed: -22
   ### ERROR ### Please RESET the board ###
   "

Avoid this failure by not keeping any Buck regulators enabled during reset,
let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3
VDD enabled during reset is ST specific, move this addition to ST specific
SPL board initialization so that it wouldn't affect the DHSOM .



Signed-off-by: Marek Vasut 
---
NOTE: This is 2023.07 material
NOTE: d1a4b09de64 ("board: st: stpmic1: add function stpmic1_init")
   mentions 'keep vdd on during the reset cycle (to avoid issue
   when backup battery is absent)', but there is no further
   description of the 'issue'. Can you please elaborate ?




In the commit message of d1a4b09de643 ("board: st: stpmic1:

add function stpmic1_init"), I indicated

  - keep vdd on during the reset cycle (to avoid issue when backup battery
  is absent)


On ST boards we have support of cell coin to allow support of backup domain,

but by default this cell are absent and the backup domain is directly 
powered


by VDD (directly connected by resistor).


We keep powered this domain to don't loss the backup domain support,

to avoid to loss the information saved in backup RAM / registers,

and to be abble to keep DEBUG part powered also.


On this ST board, if the VDD is shut down with reset, the backup domain 
can't be


correctly managed for reboot.


And to handle correctly power OFF on ST boards with PMIC, we will don't 
shut down


the VDD (full PMIC shut down) but we keep it.


So the backup domain is loosed on ST board with STPMIC1 only when the power

is removed and not for reset or for power off.



---
Cc: Patrice Chotard 
Cc: Patrick Delaunay 
Cc: uboot-st...@st-md-mailman.stormreply.com
---
  board/st/common/stpmic1.c | 10 +++---
  board/st/common/stpmic1.h |  2 +-
  board/st/stm32mp1/spl.c   | 13 +++--
  3 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
index d52dce4f657..969ad484864 100644
--- a/board/st/common/stpmic1.c
+++ b/board/st/common/stpmic1.c
@@ -185,21 +185,17 @@ static int stmpic_buck1_set(struct udevice *dev, u32 
voltage_mv)
  }
  
  /* early init of PMIC */

-void stpmic1_init(u32 voltage_mv)
+struct udevice *stpmic1_init(u32 voltage_mv)
  {
struct udevice *dev;
  
  	if (uclass_get_device_by_driver(UCLASS_PMIC,

DM_DRIVER_GET(pmic_stpmic1), ))
-   return;
+   return NULL;
  
  	/* update VDDCORE = BUCK1 */

if (voltage_mv)
stmpic_buck1_set(dev, voltage_mv);
  
-	/* Keep vdd on during the reset cycle */

-   pmic_clrsetbits(dev,
-   STPMIC1_BUCKS_MRST_CR,
-   STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
-   STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
+   return dev;
  }
diff --git a/board/st/common/stpmic1.h b/board/st/common/stpmic1.h
index b17d6f16338..7a7169d7cea 100644
--- a/board/st/common/stpmic1.h
+++ b/board/st/common/stpmic1.h
@@ -3,4 +3,4 @@
   * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
   */
  
-void stpmic1_init(u32 voltage_mv);

+struct udevice *stpmic1_init(u32 voltage_mv);
diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c
index 747ec7e445a..8b4a529f759 100644
--- a/board/st/stm32mp1/spl.c
+++ b/board/st/stm32mp1/spl.c
@@ -5,6 +5,8 @@
  
  #include 

  #include 
+#include 
+#include 
  #include 
  #include "../common/stpmic1.h"
  
@@ -19,8 +21,15 @@ void board_vddcore_init(u32 voltage_mv)
  
  int board_early_init_f(void)

  {
-   if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER))
-   stpmic1_init(opp_voltage_mv);
+   if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) {
+   struct udevice *dev = stpmic1_init(opp_voltage_mv);
+
+   /* Keep vdd on during the reset cycle */
+   pmic_clrsetbits(dev,
+   STPMIC1_BUCKS_MRST_CR,
+   STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
+   STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
+   }
  
  	return 0;

  }


Reviewed-by: Patrick Delaunay 

Thanks
Patrick

Re: [PATCH] doc: android: Fix a typo

[Mattijs Korpershoek]

On jeu., mai 25, 2023 at 14:30, Bin Meng  wrote:

> %s/than/then
>
> Signed-off-by: Bin Meng 
> ---

Reviewed-by: Mattijs Korpershoek 

>
>  doc/android/boot-image.rst | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/doc/android/boot-image.rst b/doc/android/boot-image.rst
> index c719b4d711..8f247c7093 100644
> --- a/doc/android/boot-image.rst
> +++ b/doc/android/boot-image.rst
> @@ -11,7 +11,7 @@ Android Boot Image is used to boot Android OS. It usually 
> contains kernel image
>  (like ``zImage`` file) and ramdisk. Sometimes it can contain additional
>  binaries. This image is built as a part of AOSP (called ``boot.img``), and 
> being
>  flashed into ``boot`` partition on eMMC. Bootloader then reads that image 
> from
> -``boot`` partition to RAM and boots the kernel from it. Kernel than starts
> +``boot`` partition to RAM and boots the kernel from it. Kernel then starts
>  ``init`` process from the ramdisk. It should be mentioned that recovery image
>  (``recovery.img``) also has Android Boot Image format.
>  
> -- 
> 2.25.1

Re: [PATCH v4 3/3] Load option with short device path for boot vars

[Ilias Apalodimas]

Hi Raymond,

On Tue, May 23, 2023 at 12:18:22PM -0700, Raymond Mao wrote:
> The boot variables automatically generated for removable medias
> should be with short form of device path without device nodes.
> This is a requirement for the case that a removable media is
> plugged into a different port but is still able to work with the
> existing boot variables.
>
> Signed-off-by: Raymond Mao 
> ---
> Changes in v2
> - Ignore EFI_NOT_FOUND returned from
>   efi_bootmgr_update_media_device_boot_option which means no boot
>   options scanned.
> Changes in v3
> - Split the patch into moving and renaming functions and
>   individual patches for each changed functionality
> Changes in v4
> - Revert the change of introducing a bool parameter when updating
>   the boot option. Use short-form of device path by default
>
>  lib/efi_loader/efi_bootmgr.c | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
> index c329428973..336b9d2d8f 100644
> --- a/lib/efi_loader/efi_bootmgr.c
> +++ b/lib/efi_loader/efi_bootmgr.c
> @@ -387,6 +387,11 @@ static efi_status_t 
> efi_bootmgr_enumerate_boot_option(struct eficonfig_media_boo
>   p = dev_name;
>   utf8_utf16_strncpy(, buf, strlen(buf));
>
> + /* use short form device path */
> + device_path = efi_dp_shorten(device_path);
> + if (!device_path)

One nit here.  I think we should print a warning if shortening the path
fails.  Heinrich are you ok with this?  I think not falling back and adding
the long form DP is fine.

Thanks
/Ilias
> + continue;
> +
>   lo.label = dev_name;
>   lo.attributes = LOAD_OPTION_ACTIVE;
>   lo.file_path = device_path;
> --
> 2.25.1
>

Pull request: please pull u-boot-imx-20230525

[Stefano Babic]

Hi Tom,

please pull from u-boot-imx, thanks !

This PR conbtains :

- Fixes
- Improvement support for i.MX93


The following changes since commit 6e1852ca2c418e2536ead4b51c4d84a59926b3f1:

  Merge tag 'efi-2023-07-rc3' of 
https://source.denx.de/u-boot/custodians/u-boot-efi (2023-05-16 11:23:30 
-0400)


are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git 
tags/u-boot-imx-20230525


for you to fetch changes up to ff476897ed698eae1fa439d52b30694a2b40464a:

  serial: mxs: Add MXS AUART driver (2023-05-21 16:54:41 +0200)


u-boot-imx-20230525
---

- i.MX93 series
- Fixes

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16412


Fabio Estevam (1):
  ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operation

Fedor Ross (1):
  ARM: imx: Fix parsing of ROM log event IDs on iMX8M

Jacky Bai (4):
  ddr: imx9: Change the saved ddr data base to 0x2051c000
  ddr: imx93: Add 625M bypass clock support
  ddr: imx93: update the ddr init to support mult setpoints
  ddr: imx9: update the rank setting for multi fsp support

Marek Vasut (3):
  thermal: imx_tmu: Clean up all prints
  thermal: imx_tmu: Move architecture code into driver
  serial: mxs: Add MXS AUART driver

Peng Fan (33):
  imx8ulp: build ahab
  imx: spl_imx_romapi: typo fix
  imx: move imx8 sci header file to include/firmware/imx
  imx: firmware: sci: add inline functions when IMX8 not enabled
  imx: imx8_cpu: use static for local functions
  imx: imx8_cpu: support i.MX9
  imx: imx8_cpu: support get temperature for i.MX9
  imx: imx8_cpu: print cpu grade temperature
  imx9: configure M33 systick to 24M
  imx9: add more PLL settings
  imx9: use parameter freq when set_arm_clk
  imx9: correct getting LPI2C clk
  imx9: simplify clk settings
  imx9: cut off OPTEE memory region from U-Boot
  imx9: imx93_evk: enable CPU_IMX
  imx9: imx93_evk: drop unused macro
  imx9: imx93_evk: select IMX_TMU
  imx9: imx93_evk: enable CONFIG_WDT
  watchdog: ulp_wdog: guard reset_cpu with condition check
  imx9: soc: support reset cause
  imx9: Get market segment and speed grading
  imx9: clock: clear HW_CTRL_SEL
  imx9: clock: add CONFIG_IMX9_LOW_DRIVE_MODE support
  imx9: clock: config arm alt root to 500mhz
  imx9: add i.MX93 variants support
  imx9: correct coding style
  imx9: use i.MX generic rom api function
  imx9: imx93_evk: add low drive mode support on 11x11 EVK
  arm: dts: imx93: sync device tree with Linux
  arm: dts: imx93: add tmu
  imx9: imx93_evk: Update spl stack & bss base address
  imx9: imx93_evk: update ddr timing file
  imx9: imx93_evk: enable sysreset

Ye Li (5):
  thermal: imx_tmu: Update TMU driver to support iMX93
  imx9: Change hard coded MAC to read from fuse
  imx9: allow to bootaux Mcore with input address
  ddr: imx9: Add workaround for DDRPHY rank-to-rank errata
  imx9: Calculate DDR size from DDRC setting

 arch/arm/dts/imx7d-sdb-u-boot.dtsi 
 |   51 +++
 arch/arm/dts/imx93-11x11-evk-u-boot.dtsi 
 |   29 --
 arch/arm/dts/imx93-11x11-evk.dts 
 |  385 -
 arch/arm/dts/imx93-pinfunc.h 
 |  194 +
 arch/arm/dts/imx93.dtsi 
 |  618 +--
 arch/arm/include/asm/arch-imx/cpu.h 
 |7 +
 arch/arm/include/asm/arch-imx8/power-domain.h 
 |2 +-
 arch/arm/include/asm/arch-imx8/sci/sci.h 
 |  138 --
 arch/arm/include/asm/arch-imx8/sys_proto.h 
 |2 +-
 arch/arm/include/asm/arch-imx8m/ddr.h 
 |2 +-
 arch/arm/include/asm/arch-imx9/clock.h 
 |6 +
 arch/arm/include/asm/arch-imx9/ddr.h 
 |   23 +-
 arch/arm/include/asm/arch-imx9/imx-regs.h 
 |3 +
 arch/arm/include/asm/mach-imx/sys_proto.h 
 |   12 +-
 arch/arm/mach-imx/cmd_dek.c 
 |2 +-
 arch/arm/mach-imx/imx8/ahab.c 
 |2 +-
 arch/arm/mach-imx/imx8/cpu.c 
 |2 +-
 arch/arm/mach-imx/imx8/fdt.c 
 |2 +-
 arch/arm/mach-imx/imx8/iomux.c 
 |2 +-
 arch/arm/mach-imx/imx8/misc.c 
 |2 +-
 arch/arm/mach-imx/imx8/snvs_security_sc.c 
 |2 +-
 arch/arm/mach-imx/imx8m/soc.c 
 |   74 +---
 arch/arm/mach-imx/imx8ulp/Kconfig 
 |5 +
 arch/arm/mach-imx/imx8ulp/Makefile 
 |1 +
 arch/arm/mach-imx/imx9/Kconfig 
 |5 +
 arch/arm/mach-imx/imx9/clock.c 
 |  113 -
 arch/arm/mach-imx/imx9/imx_bootaux.c 
 |   10 +-
 arch/arm/mach-imx/imx9/soc.c 
 |  384 -
 arch/arm/mach-imx/parse-container.c 
 |2 +-
 arch/arm/mach-imx/spl_imx_romapi.c 
 |2 +-
 board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c 
 |2 +-
 board/advantech/imx8qm_dmsse20_a1/spl.c 
 |2 +-
 board/advan

[PATCH] doc: android: Fix a typo

[Bin Meng]

%s/than/then

Signed-off-by: Bin Meng 
---

 doc/android/boot-image.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/doc/android/boot-image.rst b/doc/android/boot-image.rst
index c719b4d711..8f247c7093 100644
--- a/doc/android/boot-image.rst
+++ b/doc/android/boot-image.rst
@@ -11,7 +11,7 @@ Android Boot Image is used to boot Android OS. It usually 
contains kernel image
 (like ``zImage`` file) and ramdisk. Sometimes it can contain additional
 binaries. This image is built as a part of AOSP (called ``boot.img``), and 
being
 flashed into ``boot`` partition on eMMC. Bootloader then reads that image from
-``boot`` partition to RAM and boots the kernel from it. Kernel than starts
+``boot`` partition to RAM and boots the kernel from it. Kernel then starts
 ``init`` process from the ramdisk. It should be mentioned that recovery image
 (``recovery.img``) also has Android Boot Image format.
 
-- 
2.25.1