u-boot fails to build on sparc64 due redefinition of 'struct termio'
Hello!
On Linux sparc64, building u-boot fails with [1]:
cc -o tools/mkenvimage tools/mkenvimage.o tools/os_support.o
tools/lib/crc32.o
In file included from /<>/tools/termios_linux.h:33,
from /<>/tools/kwboot.c:153:
/usr/include/sparc64-linux-gnu/asm/termbits.h:14:8: error: redefinition of
'struct termio'
14 | struct termio {
|^~
In file included from /usr/include/sparc64-linux-gnu/sys/ioctl.h:29,
from /<>/tools/termios_linux.h:30:
/usr/include/sparc64-linux-gnu/bits/ioctl-types.h:36:8: note: originally
defined here
36 | struct termio
|^~
Reading through tools/termios_linux.h, it seems like the problem is that
and are included at the same time. Not sure whether this is
allowed
according to the glibc documentation.
Full build log available in [1].
Adrian
> [1]
> https://buildd.debian.org/status/fetch.php?pkg=u-boot=sparc64=2023.07%2
> Bdfsg-1=1699723544=0
--
.''`. John Paul Adrian Glaubitz
: :' : Debian Developer
`. `' Physicist
`-GPG: 62FF 8A75 84E0 2956 9546 0006 7426 3B37 F5B5 F913
[PATCH] test/py: i2c: Add tests for i2c command
Add below test cases for i2c commands:
i2c_bus - To show i2c bus info,
i2c_dev - To set or show the current bus,
i2c_probe - To probe the i2c device,
i2c_eeprom - To test i2c eeprom device,
i2c_probe_all_buses - To list down all the buses and probes it
Signed-off-by: Love Kumar
---
test/py/tests/test_i2c.py | 107 ++
1 file changed, 107 insertions(+)
create mode 100644 test/py/tests/test_i2c.py
diff --git a/test/py/tests/test_i2c.py b/test/py/tests/test_i2c.py
new file mode 100644
index ..d4f533a3ba5e
--- /dev/null
+++ b/test/py/tests/test_i2c.py
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: GPL-2.0
+# (C) Copyright 2023, Advanced Micro Devices, Inc.
+
+import pytest
+import random
+import re
+
+"""
+Note: This test doesn't rely on boardenv_* configuration value but they can
+change test behavior.
+
+For example:
+
+# Setup env__i2c_device_test_skip to True if tests with i2c devices should be
+# skipped. For example: Missing QEMU model or broken i2c device
+env__i2c_device_test_skip = True
+
+# Setup env__i2c_eeprom_device_test to set the i2c bus number and eeprom
+# address for i2c_eeprom test case. Test will be skipped if
+# env__i2c_eeprom_device_test is not set
+env__i2c_eeprom_device_test = {
+"bus": 3,
+"eeprom_addr": 0x54,
+}
+
+# Setup env__i2c_device_test to provide the i2c bus list to test against it
+# for i2c_probe_all_buses case instead of probing all the buses available. If
+# it is not set, it list down all the buses and probes it
+env__i2c_device_test = {
+"bus_list": [0, 2, 5, 12, 16, 18]
+}
+"""
+
+@pytest.mark.buildconfigspec("cmd_i2c")
+def test_i2c_bus(u_boot_console):
+if u_boot_console.config.env.get("env__i2c_device_test_skip", False):
+pytest.skip("I2C device test is not enabled!")
+expected_response = "Bus"
+response = u_boot_console.run_command("i2c bus")
+assert expected_response in response
+
+@pytest.mark.buildconfigspec("cmd_i2c")
+def test_i2c_dev(u_boot_console):
+if u_boot_console.config.env.get("env__i2c_device_test_skip", False):
+pytest.skip("I2C device test is not enabled!")
+expected_response = "Current bus"
+response = u_boot_console.run_command("i2c dev")
+assert expected_response in response
+
+@pytest.mark.buildconfigspec("cmd_i2c")
+def test_i2c_probe(u_boot_console):
+if u_boot_console.config.env.get("env__i2c_device_test_skip", False):
+pytest.skip("I2C device test is not enabled!")
+expected_response = "Setting bus to 0"
+response = u_boot_console.run_command("i2c dev 0")
+assert expected_response in response
+expected_response = "Valid chip addresses:"
+response = u_boot_console.run_command("i2c probe")
+assert expected_response in response
+
+@pytest.mark.buildconfigspec("cmd_i2c")
+def test_i2c_eeprom(u_boot_console):
+f = u_boot_console.config.env.get("env__i2c_eeprom_device_test", None)
+if not f:
+pytest.skip("No I2C eeprom to test!")
+
+bus = f.get("bus", 0)
+if bus < 0:
+pytest.fail("No bus specified via env__i2c_eeprom_device_test!")
+
+addr = f.get("eeprom_addr", -1)
+if addr < 0:
+pytest.fail("No eeprom address specified via
env__i2c_eeprom_device_test!")
+
+# Enable i2c mux bridge
+u_boot_console.run_command("i2c dev %x" % bus)
+u_boot_console.run_command("i2c probe")
+val_int = random.randint(0, 255)
+value = format(val_int, "02x")
+u_boot_console.run_command("i2c mw %x 0 %x 5" % (addr, val_int))
+expected_response = f": {value} {value} {value} {value} {value} "
+response = u_boot_console.run_command("i2c md %x 0 5" % addr)
+assert expected_response in response
+
+@pytest.mark.buildconfigspec("cmd_i2c")
+def test_i2c_probe_all_buses(u_boot_console):
+if u_boot_console.config.env.get("env__i2c_device_test_skip", False):
+pytest.skip("I2C device test is not enabled!")
+expected_response = "Bus"
+response = u_boot_console.run_command("i2c bus")
+assert expected_response in response
+
+# Get all the bus list
+f = u_boot_console.config.env.get("env__i2c_device_test", None)
+if f:
+bus_list = f.get("bus_list")
+else:
+buses = re.findall("Bus (.+?):", response)
+bus_list = [int(x) for x in buses]
+
+for dev in bus_list:
+expected_response = f"Setting bus to {dev}"
+response = u_boot_console.run_command(f"i2c dev {dev}")
+assert expected_response in response
+expected_response = "Valid chip addresses:"
+response = u_boot_console.run_command("i2c probe")
+assert expected_response in response
--
2.25.1
Re: [PATCH 1/3] arm: mach-k3: Move R5 specific code into new r5/ directory
Hi Andrew
On 14/11/23 21:29, Andrew Davis wrote:
This makes it clear these are only to be used by the R5 builds of SPL.
And this will be used to later more cleanly split the two builds.
Signed-off-by: Andrew Davis
---
arch/arm/mach-k3/Makefile | 6 +-
arch/arm/mach-k3/r5/Makefile | 13 +
arch/arm/mach-k3/{ => r5}/am62ax/Makefile | 0
arch/arm/mach-k3/{ => r5}/am62ax/am62a_qos_data.c | 0
arch/arm/mach-k3/{ => r5}/am62ax/clk-data.c | 0
arch/arm/mach-k3/{ => r5}/am62ax/dev-data.c | 0
arch/arm/mach-k3/{ => r5}/am62x/Makefile | 0
arch/arm/mach-k3/{ => r5}/am62x/clk-data.c| 0
arch/arm/mach-k3/{ => r5}/am62x/dev-data.c| 0
arch/arm/mach-k3/{ => r5}/j7200/Makefile | 0
arch/arm/mach-k3/{ => r5}/j7200/clk-data.c| 0
arch/arm/mach-k3/{ => r5}/j7200/dev-data.c| 0
arch/arm/mach-k3/{ => r5}/j721e/Makefile | 0
arch/arm/mach-k3/{ => r5}/j721e/clk-data.c| 0
arch/arm/mach-k3/{ => r5}/j721e/dev-data.c| 0
arch/arm/mach-k3/{ => r5}/j721s2/Makefile | 0
arch/arm/mach-k3/{ => r5}/j721s2/clk-data.c | 0
arch/arm/mach-k3/{ => r5}/j721s2/dev-data.c | 0
arch/arm/mach-k3/{ => r5}/lowlevel_init.S | 0
arch/arm/mach-k3/{ => r5}/r5_mpu.c| 2 +-
20 files changed, 15 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/mach-k3/r5/Makefile
rename arch/arm/mach-k3/{ => r5}/am62ax/Makefile (100%)
rename arch/arm/mach-k3/{ => r5}/am62ax/am62a_qos_data.c (100%)
rename arch/arm/mach-k3/{ => r5}/am62ax/clk-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/am62ax/dev-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/am62x/Makefile (100%)
rename arch/arm/mach-k3/{ => r5}/am62x/clk-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/am62x/dev-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j7200/Makefile (100%)
rename arch/arm/mach-k3/{ => r5}/j7200/clk-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j7200/dev-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j721e/Makefile (100%)
rename arch/arm/mach-k3/{ => r5}/j721e/clk-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j721e/dev-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j721s2/Makefile (100%)
rename arch/arm/mach-k3/{ => r5}/j721s2/clk-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j721s2/dev-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/lowlevel_init.S (100%)
rename arch/arm/mach-k3/{ => r5}/r5_mpu.c (98%)
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index c7ca0fdce56..215c755c5dc 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -3,12 +3,8 @@
# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla
-obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/
-obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
-obj-$(CONFIG_SOC_K3_AM625) += am62x/
-obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_CPU_V7R) += r5/
obj-$(CONFIG_ARM64) += arm64-mmu.o
-obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_ARM64) += cache.o
obj-$(CONFIG_OF_LIBFDT) += common_fdt.o
ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy)
diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
new file mode 100644
index 000..8a6af73a44e
--- /dev/null
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis
+
+obj-$(CONFIG_SOC_K3_J721E) += j721e/
+obj-$(CONFIG_SOC_K3_J721E) += j7200/
+obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_AM625) += am62x/
+obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+
+obj-y += lowlevel_init.o
+obj-y += r5_mpu.o
diff --git a/arch/arm/mach-k3/am62ax/Makefile
b/arch/arm/mach-k3/r5/am62ax/Makefile
similarity index 100%
rename from arch/arm/mach-k3/am62ax/Makefile
rename to arch/arm/mach-k3/r5/am62ax/Makefile
diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c
b/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c
similarity index 100%
rename from arch/arm/mach-k3/am62ax/am62a_qos_data.c
rename to arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c
diff --git a/arch/arm/mach-k3/am62ax/clk-data.c
b/arch/arm/mach-k3/r5/am62ax/clk-data.c
similarity index 100%
rename from arch/arm/mach-k3/am62ax/clk-data.c
rename to arch/arm/mach-k3/r5/am62ax/clk-data.c
diff --git a/arch/arm/mach-k3/am62ax/dev-data.c
b/arch/arm/mach-k3/r5/am62ax/dev-data.c
similarity index 100%
rename from arch/arm/mach-k3/am62ax/dev-data.c
rename to arch/arm/mach-k3/r5/am62ax/dev-data.c
diff --git a/arch/arm/mach-k3/am62x/Makefile
b/arch/arm/mach-k3/r5/am62x/Makefile
similarity index 100%
rename from arch/arm/mach-k3/am62x/Makefile
rename to arch/arm/mach-k3/r5/am62x/Makefile
diff --git a/arch/arm/mach-k3/am62x/clk-data.c
b/arch/arm/mach-k3/r5/am62x/clk-data.c
similarity index 100%
rename from
Re: [PATCH v2 0/4] fix/add npcm845 serial and board error
Hi Tom Thanks for your check. These patches I have checked and tested on npcm845 evb. The compile log and boot log is as blow: https://drive.google.com/file/d/1v3PFArKiqpFc0l9i0fy1xj0AauKlKS0k/view?usp=sharing If you have any confusion or you can't see the log please let me know. Best regards, Jim On Wed, Nov 15, 2023 at 12:23 AM Tom Rini wrote: > > On Tue, Nov 14, 2023 at 04:51:55PM +0800, Jim Liu wrote: > > > 1. Fix serial error and add bypass serial setting. > > 2. Fix/Add dts node node. > > 3. Add full function defconfig > > > > Jim Liu (4): > > arm: dts: npcm845-evb: fix/add node and aliases > > configs: arbel: Enable full functions > > serial: npcm: support skip uart clock setting > > board: nuvoton: update console environment variable > > > > arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 11 ++- > > arch/arm/dts/nuvoton-npcm845-evb.dts | 29 ++-- > > arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi | 2 +- > > board/nuvoton/arbel_evb/Kconfig | 1 + > > board/nuvoton/arbel_evb/arbel_evb.c | 7 ++ > > board/nuvoton/common/Kconfig | 9 +++ > > board/nuvoton/common/Makefile | 1 + > > board/nuvoton/common/uart.c | 71 +++ > > board/nuvoton/common/uart.h | 11 +++ > > board/nuvoton/poleg_evb/Kconfig | 1 + > > board/nuvoton/poleg_evb/poleg_evb.c | 8 +++ > > configs/arbel_evb_defconfig | 16 - > > drivers/serial/serial_npcm.c | 39 ++ > > include/dt-bindings/phy/nuvoton,npcm-usbphy.h | 14 > > 14 files changed, 194 insertions(+), 26 deletions(-) > > create mode 100644 board/nuvoton/common/Kconfig > > create mode 100644 board/nuvoton/common/Makefile > > create mode 100644 board/nuvoton/common/uart.c > > create mode 100644 board/nuvoton/common/uart.h > > create mode 100644 include/dt-bindings/phy/nuvoton,npcm-usbphy.h > > I just want to make sure now that you've given this series a compile and > boot test on some platform, yes? Thanks. > > -- > Tom
Re: [PATCH 1/8] arm: mach-k3: am62a: Add main_timer0 id to the dev list
Hi Nishanth
On 13/11/23 20:21, Nishanth Menon wrote:
main_timer0 is used by u-boot as the tick-timer. Add it to the soc
devices list so it an be enabled via the k3 power controller.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-k3/am62ax/dev-data.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-k3/am62ax/dev-data.c
b/arch/arm/mach-k3/am62ax/dev-data.c
index abf5d8e91aa2..6cced9efd08a 100644
--- a/arch/arm/mach-k3/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/am62ax/dev-data.c
@@ -52,6 +52,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(161, _lpsc_list[5]),
PSC_DEV(162, _lpsc_list[6]),
PSC_DEV(75, _lpsc_list[7]),
+ PSC_DEV(36, _lpsc_list[8]),
PSC_DEV(102, _lpsc_list[8]),
PSC_DEV(146, _lpsc_list[8]),
PSC_DEV(166, _lpsc_list[9]),
Reviewed-by: Neha Malcom Francis
--
Thanking You
Neha Malcom Francis
[PATCH] mtd: rawnand: omap_gpmc: fix BCH8 HW based correction
commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction")
broke AM335x based boards booting from NAND with ECC BCH8 code.
Use omap_enable_hwecc() instead of omap_enable_hwecc_bch()
in SPL restores correct SPL nand_read_page functionality.
Tested on draco thuban board.
Signed-off-by: Heiko Schocher
---
fix NAND boot for BCH8 based TI AM335x boards
Fix is based on series from Enrico:
https://lists.denx.de/pipermail/u-boot/2023-November/536793.html
and fixes NAND boot for the draco thuban board. But this patch
apply also without the patches from above patchseries, see
azure build:
https://dev.azure.com/hs0298/hs/_build/results?buildId=111=results
which is clean.
Above commit seems to change only U-Boot code and did not
adapt am335x_spl_bch.c, which breaks nand_read_page in SPL
code for AM335x based boards. So use in SPL "old" hw setup
and reading page from NAND in SPL works again.
drivers/mtd/nand/raw/omap_gpmc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 1a5ed0de31..c9b66dadbd 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -983,7 +983,11 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
nand->ecc.strength = 8;
nand->ecc.size = SECTOR_BYTES;
nand->ecc.bytes = 14;
+#if defined(CONFIG_SPL_BUILD)
+ nand->ecc.hwctl = omap_enable_hwecc;
+#else
nand->ecc.hwctl = omap_enable_hwecc_bch;
+#endif
nand->ecc.correct = omap_correct_data_bch;
nand->ecc.calculate = omap_calculate_ecc_bch;
nand->ecc.read_page = omap_read_page_bch;
--
2.37.3
Re: [PATCH 2/6] led-uclass: honour ->label field populated by driver's own .bind
On 11/14/23 13:11, Christian Gmeiner wrote:
ping
Am Mo., 23. Okt. 2023 um 12:45 Uhr schrieb Marek Vasut :
On 10/23/23 10:51, Rasmus Villemoes wrote:
On 19/10/2023 15.54, Marek Vasut wrote:
On 10/19/23 11:58, Rasmus Villemoes wrote:
If the driver's own .bind method has populated uc_plat->label, don't
override that. This is necessary for an upcoming driver for ti,lp5562,
where the DT binding unfortunately says to use "chan-name" and not
"label".
Signed-off-by: Rasmus Villemoes
---
drivers/led/led-uclass.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c
index 5a5d07b9a7..0232fa84de 100644
--- a/drivers/led/led-uclass.c
+++ b/drivers/led/led-uclass.c
@@ -71,7 +71,9 @@ static int led_post_bind(struct udevice *dev)
struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
const char *default_state;
-uc_plat->label = dev_read_string(dev, "label");
+if (!uc_plat->label)
+uc_plat->label = dev_read_string(dev, "label");
+
One thing I have to wonder about is, why does this controller have label
property in the top-level node , what is that used for ?
(see Linux Documentation/devicetree/bindings/leds/leds-lp55xx.yaml)
Reviewed-by: Marek Vasut
Reading the linux driver, it seems that the top-level label, if any, is
used as part of the naming for individual channels if they don't have
individual chan-name properties:
if (pdata->led_config[chan].name) {
led->cdev.name = pdata->led_config[chan].name;
} else {
snprintf(name, sizeof(name), "%s:channel%d",
pdata->label ? : chip->cl->name, chan);
led->cdev.name = name;
}
but I think the rationale in d1188adb2dabc is a bit weak, since the only
example also does have individual chan-name properties.
[Complete aside: At first I thought it was related to the multi-color
LED work that has been ongoing for many many years (I think there was an
LWN article at some point), where this could be exposed as a single
multi-color LED, as opposed to the "traditional" three/four individual
LEDs. In the former case, there would only be one sysfs entry, but with
attributes exposing the multicolor functionality. I must admit I don't
know the status of that work, when something reaches v31,
http://archive.lwn.net:8080/linux-kernel/20200722071055.GA8984@amd/t/ ,
it's hard to know if it ever lands, or if pieces of it has landed.]
+CC Pavel
I think you want to coordinate the effort with Rasmus here .
Re: [PATCH] common: usb-hub: Reset hub port before scanning
On 11/14/23 21:49, Shantur Rathore wrote: +Patrice +Patrick from get_maintainer script What is the point of this growing CC list ?
RE: [PATCH] mmc: sdhci-cadence: Add support for Cadence sdmmc v6
Hi Jaehoon, If there are no more feedback, I will send out version2 patch soon. On 11/7/23 14:24, Kuan Lim Lee wrote: > > Hi Jaehoon, > > On 11/1/23 08:20, Jaehoon Chung wrote: > > From: Jaehoon Chung Hi > > > > On 10/3/23 16:22, Kuan Lim Lee wrote: > > > From: Kuan Lim Lee > > > > > > Cadence SDMMC v6 controller has a lot of changes on initialize > > > compared to v4 controller. PHY is needed by v6 controller. > > > > > > Signed-off-by: Kuan Lim Lee > > > Reviewed-by: Alex Soo > > > Reviewed-by: Wei Liang Lim > > > > I didn't see their Reviewed-by tag in mailing list. > They are my colleagues who collaborated develop code with me. > I think I should them in Signed-off-by, and put your name in Reviewed-by > > > > > > --- > > > drivers/mmc/Kconfig | 13 ++ > > > drivers/mmc/Makefile | 1 + > > > drivers/mmc/sdhci-cadence.c | 63 ++- > > > drivers/mmc/sdhci-cadence.h | 68 +++ > > > drivers/mmc/sdhci-cadence6-phy.c | 302 > > > +++ > > > 5 files changed, 396 insertions(+), 51 deletions(-) create mode > > > 100644 drivers/mmc/sdhci-cadence.h create mode 100644 > > > drivers/mmc/sdhci-cadence6-phy.c > > > > > > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index > > > de01b9687b..cec881d862 100644 > > > --- a/drivers/mmc/Kconfig > > > +++ b/drivers/mmc/Kconfig > > > @@ -573,6 +573,19 @@ config MMC_SDHCI_CADENCE > > > > > > If unsure, say N. > > > > > > +config MMC_SDHCI_CADENCE_V6 > > > + bool "SDHCI support for the Cadence SD/SDIO/eMMC controller & > > driver version 6" > > > + depends on BLK && DM_MMC > > > + depends on MMC_SDHCI > > > + depends on OF_CONTROL > > > + select MMC_SDHCI_CADENCE > > > + help > > > + This selects the Cadence SD/SDIO/eMMC driver version 6. > > > + > > > + If you have a controller with this interface, say Y here. > > > + > > > + If unsure, say N. > > > + > > > config MMC_SDHCI_AM654 > > > bool "SDHCI Controller on TI's Am654 devices" > > > depends on ARCH_K3 > > > diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index > > > 2c65c4765a..cdcce55b8b 100644 > > > --- a/drivers/mmc/Makefile > > > +++ b/drivers/mmc/Makefile > > > @@ -61,6 +61,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += > > atmel_sdhci.o > > > obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o > > > obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o > > > obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o > > > +obj-$(CONFIG_MMC_SDHCI_CADENCE_V6) += sdhci-cadence6-phy.o > > > obj-$(CONFIG_MMC_SDHCI_AM654)+= am654_sdhci.o > > > obj-$(CONFIG_MMC_SDHCI_IPROC)+= iproc_sdhci.o > > > obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o > > > diff --git a/drivers/mmc/sdhci-cadence.c > > > b/drivers/mmc/sdhci-cadence.c index 327a05ad11..d7a270e74c 100644 > > > --- a/drivers/mmc/sdhci-cadence.c > > > +++ b/drivers/mmc/sdhci-cadence.c > > > @@ -17,56 +17,7 @@ > > > #include > > > #include > > > #include > > > - > > > -/* HRS - Host Register Set (specific to Cadence) */ > > > -#define SDHCI_CDNS_HRS04 0x10/* PHY access > port */ > > > -#define SDHCI_CDNS_HRS04_ACK BIT(26) > > > -#define SDHCI_CDNS_HRS04_RDBIT(25) > > > -#define SDHCI_CDNS_HRS04_WRBIT(24) > > > -#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16) > > > -#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8) > > > -#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, > 0) > > > - > > > -#define SDHCI_CDNS_HRS06 0x18/* eMMC > control */ > > > -#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) > > > -#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, > 8) > > > -#define SDHCI_CDNS_HRS06_MODE GENMASK(2, > 0) > > > -#define SDHCI_CDNS_HRS06_MODE_SD 0x0 > > > -#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 > > > -#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 > > > -#define SDHCI_CDNS_HRS06_MODE_MMC_HS2000x4 > > > -#define SDHCI_CDNS_HRS06_MODE_MMC_HS4000x5 > > > -#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 > > > - > > > -/* SRS - Slot Register Set (SDHCI-compatible) */ > > > -#define SDHCI_CDNS_SRS_BASE 0x200 > > > - > > > -/* PHY */ > > > -#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 > > > -#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT0x01 > > > -#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 > > > -#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 > > > -#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 > > > -#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 > > > -#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 > > > -#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 > > > -#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 > > > -#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b > > > -#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c > > > -#define SDHCI_CDNS_PHY_DLY_STROBE0x0d > > > - > > > -/* > > > -
Re: [PATCH] arm: dts: k3-am625-verdin-wifi-dev-u-boot.dtsi: Fix DMA with BCDMA
On 22:28-20231114, Roger Quadros wrote:
> BCDMA can be used at SPL for OSPI boot and mem-to-mem DMA
> so add "bootph-all" to BCDMA node.
>
> Suggested-by: Nishanth Menon
> Fixes: 9a3f2b6798b0 ("arm: dts: k3-am625-verdin-wifi-dev-u-boot.dtsi: Fix
> DMA/Ethernet")
> Signed-off-by: Roger Quadros
> ---
> arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
> b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
> index 75cb60b57d..588d9594a8 100644
> --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
> +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
> @@ -53,6 +53,7 @@
> <0x00 0x484c2000 0x00 0x2000>;
> reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
> "ringrt" , "cfg", "tchan", "rchan";
> + bootph-all;
Reviewed-by: Nishanth Menon
> };
>
> _pktdma {
>
> base-commit: 92b27528d777ce85362af45e7d2974a6c856219b
> --
> 2.34.1
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5
849D 1736 249D
[PATCH V2 3/4] arm: dts: k3-am625-beagleplay-u-boot: drop duplicate bootph-nodes
Kernel dts import now provides bootph-all and bootph-pre-ram properties
for the properties we have been overriding so far. Drop the same.
Reviewed-by: Dhruva Gole
Tested-by: Dhruva Gole
Signed-off-by: Nishanth Menon
---
Changes since v1:
- tested and reviewed tags
V1: https://lore.kernel.org/r/20231113145919.1928812-4...@ti.com
arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 56
1 file changed, 56 deletions(-)
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
index 6f3a31558b20..7f8468f298f0 100644
--- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -13,36 +13,26 @@
tick-timer = _timer0;
};
- memory@8000 {
- bootph-all;
- };
-
/* Keep the LEDs on by default to indicate life */
leds {
- bootph-all;
led-0 {
default-state = "on";
- bootph-all;
};
led-1 {
default-state = "on";
- bootph-all;
};
led-2 {
default-state = "on";
- bootph-all;
};
led-3 {
default-state = "on";
- bootph-all;
};
led-4 {
default-state = "on";
- bootph-all;
};
};
};
@@ -58,45 +48,7 @@
};
};
-_uart0 {
- bootph-all;
-};
-
-_pins_default {
- bootph-all;
-};
-
-_i2c0 {
- bootph-all;
-};
-
-_i2c_pins_default {
- bootph-all;
-};
-
-_pins_default {
- bootph-all;
-};
-
-_gpio0 {
- bootph-all;
-};
-
-_gpio1 {
- bootph-all;
-};
-
- {
- /* EMMC */
- bootph-all;
-};
-
-_pins_default {
- bootph-all;
-};
-
_pins_default {
- bootph-all;
/* Force to use SDCD card detect pin */
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
@@ -109,14 +61,6 @@
>;
};
- {
- bootph-all;
-};
-
- {
- bootph-all;
-};
-
#ifdef CONFIG_TARGET_AM625_A53_EVM
#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb"
--
2.40.0
[PATCH V2 2/4] arm: dts: k3-am625: Drop SoC provided bootph params from board u-boot/r5 dtsi
k3-am62* SoC dtsi files now provide the following:
bootph-all: dmss secure_proxy_main dmsc k3_pds k3_clks k3_reset
main_pmx0 main_timer0 mcu_pmx0 wkup_conf chipid
bootph-pre-ram: secure_proxy_sa3 main_esm mcu_esm
Drop these from board r5 and u-boot.dtsi files as these are duplicate in
them now.
Acked-by: Francesco Dolcini
Tested-by: Dhruva Gole
Signed-off-by: Nishanth Menon
---
Changes since v1:
- just picked up acks and tested tags
V1: https://lore.kernel.org/r/20231113145919.1928812-3...@ti.com
arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 54 --
arch/arm/dts/k3-am625-r5-beagleplay.dts | 9 ---
arch/arm/dts/k3-am625-r5-sk.dts | 9 ---
arch/arm/dts/k3-am625-sk-u-boot.dtsi | 53 --
arch/arm/dts/k3-am625-verdin-r5.dts | 9 ---
.../dts/k3-am625-verdin-wifi-dev-u-boot.dtsi | 55 +--
6 files changed, 2 insertions(+), 187 deletions(-)
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
index d6c6baa5518b..6f3a31558b20 100644
--- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -47,59 +47,17 @@
};
};
-_main {
- bootph-all;
-};
-
_timer0 {
clock-frequency = <2500>;
- bootph-all;
-};
-
- {
- bootph-all;
-};
-
-_proxy_main {
- bootph-all;
-};
-
- {
- bootph-all;
-};
-
-_pds {
- bootph-all;
-};
-
-_clks {
- bootph-all;
-};
-
-_reset {
- bootph-all;
};
{
- bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
-_conf {
- bootph-all;
-};
-
- {
- bootph-all;
-};
-
-_pmx0 {
- bootph-all;
-};
-
_uart0 {
bootph-all;
};
@@ -108,18 +66,6 @@
bootph-all;
};
-_mcu {
- bootph-all;
-};
-
-_wakeup {
- bootph-all;
-};
-
-_pmx0 {
- bootph-all;
-};
-
_i2c0 {
bootph-all;
};
diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts
b/arch/arm/dts/k3-am625-r5-beagleplay.dts
index 9c9d0570592a..1f450f55c1d2 100644
--- a/arch/arm/dts/k3-am625-r5-beagleplay.dts
+++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts
@@ -54,12 +54,7 @@
ti,secure-host;
};
-_esm {
- bootph-pre-ram;
-};
-
_proxy_sa3 {
- bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
@@ -73,10 +68,6 @@
};
};
-_esm {
- bootph-pre-ram;
-};
-
_pktdma {
ti,sci = <_tifs>;
};
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index bf219226b974..55420b2f2c15 100644
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -55,20 +55,11 @@
ti,secure-host;
};
-_esm {
- bootph-pre-ram;
-};
-
_proxy_sa3 {
- bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
-_esm {
- bootph-pre-ram;
-};
-
_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
index 7ae5e01f7c7f..dcf7c7652d31 100644
--- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
@@ -25,49 +25,8 @@
bootph-all;
};
-_main {
- bootph-all;
-};
-
_timer0 {
clock-frequency = <2500>;
- bootph-all;
-};
-
- {
- bootph-all;
-};
-
-_proxy_main {
- bootph-all;
-};
-
- {
- bootph-all;
-};
-
-_pds {
- bootph-all;
-};
-
-_clks {
- bootph-all;
-};
-
-_reset {
- bootph-all;
-};
-
-_conf {
- bootph-all;
-};
-
- {
- bootph-all;
-};
-
-_pmx0 {
- bootph-all;
};
_uart0 {
@@ -78,18 +37,6 @@
bootph-all;
};
-_mcu {
- bootph-all;
-};
-
-_wakeup {
- bootph-all;
-};
-
-_pmx0 {
- bootph-all;
-};
-
{
bootph-all;
};
diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts
b/arch/arm/dts/k3-am625-verdin-r5.dts
index 0cae9c577732..305d199678b3 100644
--- a/arch/arm/dts/k3-am625-verdin-r5.dts
+++ b/arch/arm/dts/k3-am625-verdin-r5.dts
@@ -69,16 +69,7 @@
ti,secure-host;
};
-_esm {
- bootph-pre-ram;
-};
-
-_esm {
- bootph-pre-ram;
-};
-
_proxy_sa3 {
- bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
index 75cb60b57d79..86e2d111f541 100644
--- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
@@ -21,25 +21,8 @@
};
};
-_main {
- bootph-all;
-
- timer@240 {
- clock-frequency = <2500>;
- bootph-all;
- };
-};
-
-_mcu {
- bootph-all;
-};
-
-_wakeup {
- bootph-all;
-};
-
- {
- bootph-all;
+_timer0 {
+
[PATCH V2 4/4] arm: dts: k3-am625-sk-r5/u-boot: Drop duplicate bootph-nodes
Kernel dts import now provides bootph-all and bootph-pre-ram properties
for the properties we have been overriding so far. Drop the same.
While at this enable the DM and TIFS UARTs for programming pinmux
since they are marked reserved by board.dts
Reviewed-by: Dhruva Gole
Tested-by: Dhruva Gole
Signed-off-by: Nishanth Menon
---
Changes:
- capitalize TIFS and UART.
- pick up reviewed and tested tags
V1: https://lore.kernel.org/r/20231113145919.1928812-5...@ti.com
arch/arm/dts/k3-am625-r5-sk.dts | 12 +---
arch/arm/dts/k3-am625-sk-u-boot.dtsi | 92
2 files changed, 2 insertions(+), 102 deletions(-)
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index 55420b2f2c15..6b9f40e55581 100644
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -69,22 +69,14 @@
};
};
-_uart0_pins_default {
- bootph-pre-ram;
-};
-
-_uart1_pins_default {
- bootph-pre-ram;
-};
-
/* WKUP UART0 is used for DM firmware logs */
_uart0 {
- bootph-pre-ram;
+ status = "okay";
};
/* Main UART1 is used for TIFS firmware logs */
_uart1 {
- bootph-pre-ram;
+ status = "okay";
};
{
diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
index dcf7c7652d31..fa778b0ff4c1 100644
--- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
@@ -8,71 +8,14 @@
/ {
chosen {
- stdout-path = "serial2:115200n8";
tick-timer = _timer0;
};
-
- aliases {
- mmc1 =
- };
-
- memory@8000 {
- bootph-all;
- };
-};
-
-_conf {
- bootph-all;
};
_timer0 {
clock-frequency = <2500>;
};
-_uart0 {
- bootph-all;
-};
-
-_uart0_pins_default {
- bootph-all;
-};
-
- {
- bootph-all;
-};
-
-_mmc1_pins_default {
- bootph-all;
-};
-
- {
- bootph-all;
-};
-
-_pins_default {
- bootph-all;
-};
-
- {
- bootph-all;
-
- flash@0 {
- bootph-all;
-
- partitions {
- bootph-all;
-
- partition@3fc {
- bootph-all;
- };
- };
- };
-};
-
-_main_dmss {
- bootph-all;
-};
-
_bcdma {
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c00 0x00 0x2>,
@@ -100,41 +43,6 @@
bootph-all;
};
-_mdio {
- bootph-all;
-};
-
-_phy0 {
- bootph-all;
-};
-
-_phy1 {
- bootph-all;
-};
-
-_rgmii1_pins_default {
- bootph-all;
-};
-
-_rgmii2_pins_default {
- bootph-all;
-};
-
-_gmii_sel {
- bootph-all;
-};
-
- {
- bootph-all;
- ethernet-ports {
- bootph-all;
- };
-};
-
-_port1 {
- bootph-all;
-};
-
_port2 {
status = "disabled";
};
--
2.40.0
[PATCH V2 1/4] arm: dts: k3-am625*: Sync with kernel v6.7-rc1
Sync with kernel v6.7-rc1 and sync up the u-boot dts files accordingly.
Tested-by: Dhruva Gole
Signed-off-by: Nishanth Menon
---
Changes since v1:
- just tested-by tag.
V1: https://lore.kernel.org/r/20231113145919.1928812-2...@ti.com
arch/arm/dts/k3-am62-main.dtsi| 12 ++-
arch/arm/dts/k3-am62-mcu.dtsi | 2 +
arch/arm/dts/k3-am62-verdin-wifi.dtsi | 6 ++
arch/arm/dts/k3-am62-verdin.dtsi | 1 +
arch/arm/dts/k3-am62-wakeup.dtsi | 2 +
arch/arm/dts/k3-am62.dtsi | 3 +
arch/arm/dts/k3-am625-beagleplay.dts | 34 +++-
arch/arm/dts/k3-am625-sk.dts | 27 +++
arch/arm/dts/k3-am62x-sk-common.dtsi | 109 +-
9 files changed, 193 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi
index 284b90c94da8..e5c64c86d1d5 100644
--- a/arch/arm/dts/k3-am62-main.dtsi
+++ b/arch/arm/dts/k3-am62-main.dtsi
@@ -81,7 +81,8 @@
};
dmss: bus@4800 {
- compatible = "simple-mfd";
+ bootph-all;
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
@@ -90,6 +91,7 @@
ti,sci-dev-id = <25>;
secure_proxy_main: mailbox@4d00 {
+ bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
@@ -165,6 +167,7 @@
};
dmsc: system-controller@44043000 {
+ bootph-all;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
@@ -174,16 +177,19 @@
reg = <0x00 0x44043000 0x00 0xfe0>;
k3_pds: power-controller {
+ bootph-all;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
+ bootph-all;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
+ bootph-all;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
@@ -202,6 +208,7 @@
};
secure_proxy_sa3: mailbox@4360 {
+ bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
@@ -217,6 +224,7 @@
};
main_pmx0: pinctrl@f4000 {
+ bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
#pinctrl-cells = <1>;
@@ -225,12 +233,14 @@
};
main_esm: esm@42 {
+ bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x42 0x00 0x1000>;
ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
};
main_timer0: timer@240 {
+ bootph-all;
compatible = "ti,am654-timer";
reg = <0x00 0x240 0x00 0x400>;
interrupts = ;
diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi
index 80a3e1db26a9..0e0b234581c6 100644
--- a/arch/arm/dts/k3-am62-mcu.dtsi
+++ b/arch/arm/dts/k3-am62-mcu.dtsi
@@ -7,6 +7,7 @@
_mcu {
mcu_pmx0: pinctrl@4084000 {
+ bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0x04084000 0x00 0x88>;
#pinctrl-cells = <1>;
@@ -15,6 +16,7 @@
};
mcu_esm: esm@410 {
+ bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x410 0x00 0x1000>;
ti,esm-pins = <0>, <1>, <2>, <85>;
diff --git a/arch/arm/dts/k3-am62-verdin-wifi.dtsi
b/arch/arm/dts/k3-am62-verdin-wifi.dtsi
index 90ddc71bcd30..a6808b10c7b2 100644
--- a/arch/arm/dts/k3-am62-verdin-wifi.dtsi
+++ b/arch/arm/dts/k3-am62-verdin-wifi.dtsi
@@ -35,5 +35,11 @@
_uart5 {
pinctrl-names = "default";
pinctrl-0 = <_uart5>;
+ uart-has-rtscts;
status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ fw-init-baudrate = <300>;
+ };
};
diff --git a/arch/arm/dts/k3-am62-verdin.dtsi b/arch/arm/dts/k3-am62-verdin.dtsi
index 40992e7e4c30..5db52f237253 100644
--- a/arch/arm/dts/k3-am62-verdin.dtsi
+++ b/arch/arm/dts/k3-am62-verdin.dtsi
@@ -1061,6 +1061,7 @@
vddc-supply = <_1v2_dsi>;
vddmipi-supply = <_1v2_dsi>;
vddio-supply = <_1v8_dsi>;
+ status = "disabled";
dsi_bridge_ports: ports {
[PATCH V2 0/4] arm: dts: k3-am625*: Upgrade kernel dts to v6.7-rc1
Hi, rev 2 of the series to sync am62 with v6.7-rc1. Changes: - picked up reviews, tested tags. - minor commit message correction in patch #4. Boot logs: https://gist.github.com/nmenon/d62c4795c6d3d40c83ba36d1cd047c42 WARNING: This will have a minor conflict (binman) with: https://lore.kernel.org/u-boot/20231104080137.9628-1...@ti.com/ I haven't had a chance to test this out on verdin (only build tested) - going to depend on any checks folks can provide. V1: https://lore.kernel.org/all/20231113145919.1928812-1...@ti.com/ Nishanth Menon (4): arm: dts: k3-am625*: Sync with kernel v6.7-rc1 arm: dts: k3-am625: Drop SoC provided bootph params from board u-boot/r5 dtsi arm: dts: k3-am625-beagleplay-u-boot: drop duplicate bootph-nodes arm: dts: k3-am625-sk-r5/u-boot: Drop duplicate bootph-nodes arch/arm/dts/k3-am62-main.dtsi| 12 +- arch/arm/dts/k3-am62-mcu.dtsi | 2 + arch/arm/dts/k3-am62-verdin-wifi.dtsi | 6 + arch/arm/dts/k3-am62-verdin.dtsi | 1 + arch/arm/dts/k3-am62-wakeup.dtsi | 2 + arch/arm/dts/k3-am62.dtsi | 3 + arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 110 - arch/arm/dts/k3-am625-beagleplay.dts | 34 +++- arch/arm/dts/k3-am625-r5-beagleplay.dts | 9 -- arch/arm/dts/k3-am625-r5-sk.dts | 21 +-- arch/arm/dts/k3-am625-sk-u-boot.dtsi | 145 -- arch/arm/dts/k3-am625-sk.dts | 27 arch/arm/dts/k3-am625-verdin-r5.dts | 9 -- .../dts/k3-am625-verdin-wifi-dev-u-boot.dtsi | 55 +-- arch/arm/dts/k3-am62x-sk-common.dtsi | 109 - 15 files changed, 197 insertions(+), 348 deletions(-) -- 2.40.0
Re: Booting an x86-64 BIOS Machine
Hi Desone, On Tue, 14 Nov 2023 at 17:43, Desone Burns wrote: > > Hello, > > I have an application in which I need to boot an x86-64 machine with a > legacy BIOS. I've read about the U-Boot executable, the SPL, and the > TPL. I'm just having a bit of trouble figuring out which pieces are > supposed to go where. Looking to Grub, I see there exists a minimal > "boot.img" file, which gets installed into the MBR of the drive and > subsequently bootstraps the rest of the sequence. My impression was > that either the TPL or the SPL would play that same role, but even > removing basically all options, the binary produced is still too large > to fit in this 512 Byte area. Syslinux also works on my device, and > the "mbr.bin" and "gptmbr.bin" files play the same role for that > bootloader. How can I make optimizations to generate an image small > enough to fit into the MBR of my device to allow BIOS to load the rest > of the bootloader? Normally U-Boot would go in the SPI flash. If you are wanting to put U-Boot on a disk, then I suspect you need some code in the MBR to load it into RAM. Something like [1] perhaps? For that case, I doubt you need TPL and SPL...we use those on newer x86 machines, e.g. Apollo Lake - see [2] Regards, Simon [1] https://thestarman.pcministry.com/asm/mbr/STDMBR.htm [2] https://docs.u-boot.org/en/latest/board/google/chromebook_coral.html?highlight=coral
Re: [PATCH] riscv: binman: fix the load field format
Hi Randolph,
On Mon, 13 Nov 2023 at 23:26, Randolph Lin wrote:
>
> Hi Simon,
> Thanks a lot.
> On Fri, Nov 10, 2023 at 04:50:24AM -0700, Simon Glass wrote:
> > Hi Randolph,
> >
> > On Wed, Nov 8, 2023, 20:15 Randolph wrote:
> > >
> > > The #address-cells is now equal to 2. The format of the load field for
> > > the Linux kernel doesn't match.
> > >
> > > Signed-off-by: Randolph
> > > ---
> > > arch/riscv/dts/binman.dtsi | 3 ++-
> > > 1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
> > > index 6b4eb8dc7b..5117d7c8c9 100644
> > > --- a/arch/riscv/dts/binman.dtsi
> > > +++ b/arch/riscv/dts/binman.dtsi
> > > @@ -50,7 +50,8 @@
> > > os = "Linux";
> > > arch = "riscv";
> > > compression = "none";
> > > - load = ;
> > > + load =
> > > > > +
> > > U64_TO_U32_L(CONFIG_TEXT_BASE)>;
> >
> I just see the #address-cells changed from 1 to 2 in commit id: 5a348ccf0257.
> In my last commit for binman.dtsi (commit id: d311df8b3169), it is based on
> the value of #address-cells being 1. That's the reason for my patch
> submission.
> > Does this work?
> >
> > load = /bits 64/
> >
> Yes, it works. We use this way for the DDR memory start address above 4G
> platform. We find the example for 64bit address in the document
> tools/binman/binman.rst and use it.
> What is the method that we should continue to use in the binman.dtsi?
> 1. #address-cells = 2
> 2. append /bits/64
I believe these go together. Using (1) means you have a 2-cell value,
which is 64 bits since each cell is 32-bits.
Or perhaps I misunderstand what you are asking?
> > >
> > > linux_blob: blob-ext {
> > > filename = "Image";
> > > --
> > > 2.34.1
> > >
> >
Regards,
Simon
RE: [PATCH v2] timer: starfive: Add Starfive timer support
Hi,
May anyone please help to review to this version 2 patch?
Best Regards,
KL Lee
On 11/6/23 13:13, Kuan Lim Lee wrote:
> Subject: [PATCH v2] timer: starfive: Add Starfive timer support
>
> Add timer driver in Starfive SoC. It is an timer that outside of CPU core and
> inside Starfive SoC.
>
> Signed-off-by: Kuan Lim Lee
> Signed-off-by: Wei Liang Lim
> Reviewed-by: Simon Glass
>
> Changes for v2:
> - correct driver name, comment, variable
> ---
> drivers/timer/Kconfig | 7 +++
> drivers/timer/Makefile | 1 +
> drivers/timer/starfive-timer.c | 96 ++
> 3 files changed, 104 insertions(+)
> create mode 100644 drivers/timer/starfive-timer.c
>
> diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index
> 915b2af160..a98be9dfae 100644
> --- a/drivers/timer/Kconfig
> +++ b/drivers/timer/Kconfig
> @@ -326,4 +326,11 @@ config XILINX_TIMER
> Select this to enable support for the timer found on
> any Xilinx boards (axi timer).
>
> +config STARFIVE_TIMER
> + bool "Starfive timer support"
> + depends on TIMER
> + help
> + Select this to enable support for the timer found on
> + Starfive SoC.
> +
> endmenu
> diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index
> 1ca74805fd..1ef814970b 100644
> --- a/drivers/timer/Makefile
> +++ b/drivers/timer/Makefile
> @@ -34,3 +34,4 @@ obj-$(CONFIG_MTK_TIMER) +=
> mtk_timer.o
> obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o
> obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o
> obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o
> +obj-$(CONFIG_STARFIVE_TIMER) += starfive-timer.o
> diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c
> new
> file mode 100644 index 00..b9ba33277e
> --- /dev/null
> +++ b/drivers/timer/starfive-timer.c
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2022 StarFive, Inc. All rights reserved.
> + * Author: Lee Kuan Lim
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define STF_TIMER_INT_STATUS0x00
> +#define STF_TIMER_CTL0x04
> +#define STF_TIMER_LOAD 0x08
> +#define STF_TIMER_ENABLE 0x10
> +#define STF_TIMER_RELOAD 0x14
> +#define STF_TIMER_VALUE 0x18
> +#define STF_TIMER_INT_CLR0x20
> +#define STF_TIMER_INT_MASK 0x24
> +
> +struct starfive_timer_priv {
> + void __iomem *base;
> + u32 timer_size;
> +};
> +
> +static u64 notrace starfive_get_count(struct udevice *dev) {
> + struct starfive_timer_priv *priv = dev_get_priv(dev);
> +
> + /* Read decrement timer value and convert to increment value */
> + return priv->timer_size - readl(priv->base + STF_TIMER_VALUE); }
> +
> +static const struct timer_ops starfive_ops = {
> + .get_count = starfive_get_count,
> +};
> +
> +static int starfive_probe(struct udevice *dev) {
> + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> + struct starfive_timer_priv *priv = dev_get_priv(dev);
> + int timer_channel;
> + struct clk clk;
> + int ret;
> +
> + priv->base = dev_read_addr_ptr(dev);
> + if (!priv->base)
> + return -EINVAL;
> +
> + timer_channel = dev_read_u32_default(dev, "channel", 0);
> + priv->base = priv->base + (0x40 * timer_channel);
> +
> + /* Get clock rate from channel selectecd*/
> + ret = clk_get_by_index(dev, timer_channel, );
> + if (ret)
> + return ret;
> +
> + ret = clk_enable();
> + if (ret)
> + return ret;
> + uc_priv->clock_rate = clk_get_rate();
> +
> + /*
> + * Initiate timer, channel 0
> + * Unmask Interrupt Mask
> + */
> + writel(0, priv->base + STF_TIMER_INT_MASK);
> + /* Single run mode Setting */
> + if (dev_read_bool(dev, "single-run"))
> + writel(1, priv->base + STF_TIMER_CTL);
> + /* Set Reload value */
> + priv->timer_size = dev_read_u32_default(dev, "timer-size", -1U);
> + writel(priv->timer_size, priv->base + STF_TIMER_LOAD);
> + /* Enable to start timer */
> + writel(1, priv->base + STF_TIMER_ENABLE);
> +
> + return 0;
> +}
> +
> +static const struct udevice_id starfive_ids[] = {
> + { .compatible = "starfive,jh8100-timers" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(jh8100_starfive_timer) = {
> + .name = "starfive_timer",
> + .id = UCLASS_TIMER,
> + .of_match = starfive_ids,
> + .probe = starfive_probe,
> + .ops= _ops,
> + .priv_auto = sizeof(struct starfive_timer_priv),
> +};
> --
> 2.34.1
[PATCH] xen: pvblock: fix the maximum io size in one operation
The current implementation may cause BUG_ON() in blkfront_aio()
BUG_ON(n > BLKIF_MAX_SEGMENTS_PER_REQUEST);
In pvblock_iop(), a read/write operation will be split into smaller
chunks of data so that the size in one access (aio_nbytes) is limited
to, at the maximum,
BLKIF_MAX_SEGMENTS_PER_REQUEST * PAGE_SIZE
But this works only if when the *buffer* passed in to pvblock_io()
is page-aligned. If not, the given data region may stand across
(BLKIF_MAX_SEGMENTS_PER_REQUEST + 1) pages. See the logic in
blkfront_aio():
start = (uintptr_t)aiocbp->aio_buf & PAGE_MASK;
end = ((uintptr_t)aiocbp->aio_buf + aiocbp->aio_nbytes +
PAGE_SIZE - 1) & PAGE_MASK;
Then this will lead to BUG_ON() above.
This can be fixed by decreasing the maximum size of aio_nbytes.
Signed-off-by: AKASHI Takahiro
Fixes: commit 3a739cc6c948 ("xen: pvblock: Implement front-back protocol and do
IO")
---
drivers/xen/pvblock.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/xen/pvblock.c b/drivers/xen/pvblock.c
index 4ad548d599d5..1df04e239ad0 100644
--- a/drivers/xen/pvblock.c
+++ b/drivers/xen/pvblock.c
@@ -632,7 +632,8 @@ static ulong pvblock_iop(struct udevice *udev, lbaint_t
blknr,
memcpy(blk_dev->bounce_buffer, buffer, desc->blksz);
aiocb.aio_nbytes = unaligned ? desc->blksz :
- min((size_t)(BLKIF_MAX_SEGMENTS_PER_REQUEST *
PAGE_SIZE),
+ min((size_t)((BLKIF_MAX_SEGMENTS_PER_REQUEST - 1)
+ * PAGE_SIZE),
(size_t)(blocks_todo * desc->blksz));
blkfront_io(, write);
--
2.34.1
Re: [PATCH v4 09/12] x86: Enable SSE in 64-bit mode
On Sun, Nov 12, 2023 at 01:02:46PM -0700, Simon Glass wrote: > This is needed to support Truetype fonts. In any case, the compiler > expects SSE to be available in 64-bit mode. Provide an option to enable > SSE so that hardware floating-point arithmetic works. > > Signed-off-by: Simon Glass > Suggested-by: Bin Meng Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 09/12] x86: Enable SSE in 64-bit mode
On Wed, Nov 15, 2023 at 08:44:22AM +0800, Bin Meng wrote:
> Hi Tom,
>
> On Wed, Nov 15, 2023 at 12:22 AM Tom Rini wrote:
> >
> > On Tue, Nov 14, 2023 at 09:49:08AM +0800, Bin Meng wrote:
> > > Hi Tom,
> > >
> > > On Tue, Nov 14, 2023 at 7:52 AM Tom Rini wrote:
> > > >
> > > > On Tue, Nov 14, 2023 at 07:46:36AM +0800, Bin Meng wrote:
> > > > > Hi Tom,
> > > > >
> > > > > On Tue, Nov 14, 2023 at 6:59 AM Tom Rini wrote:
> > > > > >
> > > > > > On Mon, Nov 13, 2023 at 03:28:13PM -0700, Simon Glass wrote:
> > > > > > > Hi Bin,
> > > > > > >
> > > > > > > On Mon, 13 Nov 2023 at 15:08, Bin Meng wrote:
> > > > > > > >
> > > > > > > > Hi Simon,
> > > > > > > >
> > > > > > > > On Mon, Nov 13, 2023 at 4:03 AM Simon Glass
> > > > > > > > wrote:
> > > > > > > > >
> > > > > > > > > This is needed to support Truetype fonts. In any case, the
> > > > > > > > > compiler
> > > > > > > > > expects SSE to be available in 64-bit mode. Provide an option
> > > > > > > > > to enable
> > > > > > > > > SSE so that hardware floating-point arithmetic works.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Simon Glass
> > > > > > > > > Suggested-by: Bin Meng
> > > > > > > > > ---
> > > > > > > > >
> > > > > > > > > Changes in v4:
> > > > > > > > > - Use a Kconfig option
> > > > > > > > >
> > > > > > > > > arch/x86/Kconfig | 8
> > > > > > > > > arch/x86/config.mk| 4
> > > > > > > > > arch/x86/cpu/x86_64/cpu.c | 12
> > > > > > > > > drivers/video/Kconfig | 1 +
> > > > > > > > > 4 files changed, 25 insertions(+)
> > > > > > > > >
> > > > > > > > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> > > > > > > > > index 99e59d94c606..6b532d712ee8 100644
> > > > > > > > > --- a/arch/x86/Kconfig
> > > > > > > > > +++ b/arch/x86/Kconfig
> > > > > > > > > @@ -723,6 +723,14 @@ config ROM_TABLE_SIZE
> > > > > > > > > hex
> > > > > > > > > default 0x1
> > > > > > > > >
> > > > > > > > > +config X86_HARDFP
> > > > > > > > > + bool "Support hardware floating point"
> > > > > > > > > + help
> > > > > > > > > + U-Boot generally does not make use of floating
> > > > > > > > > point. Where this is
> > > > > > > > > + needed, it can be enabled using this option. This
> > > > > > > > > adjusts the
> > > > > > > > > + start-up code for 64-bit mode and changes the
> > > > > > > > > compiler options for
> > > > > > > > > + 64-bit to enable SSE.
> > > > > > > >
> > > > > > > > As discussed in another thread, this option should be made
> > > > > > > > global to
> > > > > > > > all architectures and by default no.
> > > > > > > >
> > > > > > > > > +
> > > > > > > > > config HAVE_ITSS
> > > > > > > > > bool "Enable ITSS"
> > > > > > > > > help
> > > > > > > > > diff --git a/arch/x86/config.mk b/arch/x86/config.mk
> > > > > > > > > index 26ec1af2f0b0..2e3a7119e798 100644
> > > > > > > > > --- a/arch/x86/config.mk
> > > > > > > > > +++ b/arch/x86/config.mk
> > > > > > > > > @@ -27,9 +27,13 @@ ifeq ($(IS_32BIT),y)
> > > > > > > > > PLATFORM_CPPFLAGS += -march=i386 -m32
> > > > > > > > > else
> > > > > > > > > PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic)
> > > > > > > > > -fno-common -march=core2 -m64
> > > > > > > > > +
> > > > > > > > > +ifndef CONFIG_X86_HARDFP
> > > > > > > > > PLATFORM_CPPFLAGS += -mno-mmx -mno-sse
> > > > > > > > > endif
> > > > > > > > >
> > > > > > > > > +endif # IS_32BIT
> > > > > > > > > +
> > > > > > > > > PLATFORM_RELFLAGS += -fdata-sections -ffunction-sections
> > > > > > > > > -fvisibility=hidden
> > > > > > > > >
> > > > > > > > > KBUILD_LDFLAGS += -Bsymbolic -Bsymbolic-functions
> > > > > > > > > diff --git a/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > > b/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > > index 2647bff891f8..5ea746ecce4d 100644
> > > > > > > > > --- a/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > > +++ b/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > > @@ -10,6 +10,7 @@
> > > > > > > > > #include
> > > > > > > > > #include
> > > > > > > > > #include
> > > > > > > > > +#include
> > > > > > > > >
> > > > > > > > > DECLARE_GLOBAL_DATA_PTR;
> > > > > > > > >
> > > > > > > > > @@ -39,11 +40,22 @@ int x86_mp_init(void)
> > > > > > > > > return 0;
> > > > > > > > > }
> > > > > > > > >
> > > > > > > > > +/* enable SSE features for hardware floating point */
> > > > > > > > > +static void setup_sse_features(void)
> > > > > > > > > +{
> > > > > > > > > + asm ("mov %%cr4, %%rax\n" \
> > > > > > > > > + "or %0, %%rax\n" \
> > > > > > > > > + "mov %%rax, %%cr4\n" \
> > > > > > > > > + : : "i" (X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT) :
> > > > > > > > > "eax");
> > > > > > > > > +}
> > > > > > > > > +
> > > > > > > > > int x86_cpu_reinit_f(void)
> > > > > > > > > {
> > > > > > > > > /* set the vendor to Intel so that
> > > > > > > > > native_calibrate_tsc() works */
> > > > > > > > > gd->arch.x86_vendor =
Re: [PATCH v4 09/12] x86: Enable SSE in 64-bit mode
Hi,
On Tue, 14 Nov 2023 at 17:44, Bin Meng wrote:
>
> Hi Tom,
>
> On Wed, Nov 15, 2023 at 12:22 AM Tom Rini wrote:
> >
> > On Tue, Nov 14, 2023 at 09:49:08AM +0800, Bin Meng wrote:
> > > Hi Tom,
> > >
> > > On Tue, Nov 14, 2023 at 7:52 AM Tom Rini wrote:
> > > >
> > > > On Tue, Nov 14, 2023 at 07:46:36AM +0800, Bin Meng wrote:
> > > > > Hi Tom,
> > > > >
> > > > > On Tue, Nov 14, 2023 at 6:59 AM Tom Rini wrote:
> > > > > >
> > > > > > On Mon, Nov 13, 2023 at 03:28:13PM -0700, Simon Glass wrote:
> > > > > > > Hi Bin,
> > > > > > >
> > > > > > > On Mon, 13 Nov 2023 at 15:08, Bin Meng wrote:
> > > > > > > >
> > > > > > > > Hi Simon,
> > > > > > > >
> > > > > > > > On Mon, Nov 13, 2023 at 4:03 AM Simon Glass
> > > > > > > > wrote:
> > > > > > > > >
> > > > > > > > > This is needed to support Truetype fonts. In any case, the
> > > > > > > > > compiler
> > > > > > > > > expects SSE to be available in 64-bit mode. Provide an option
> > > > > > > > > to enable
> > > > > > > > > SSE so that hardware floating-point arithmetic works.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Simon Glass
> > > > > > > > > Suggested-by: Bin Meng
> > > > > > > > > ---
> > > > > > > > >
> > > > > > > > > Changes in v4:
> > > > > > > > > - Use a Kconfig option
> > > > > > > > >
> > > > > > > > > arch/x86/Kconfig | 8
> > > > > > > > > arch/x86/config.mk| 4
> > > > > > > > > arch/x86/cpu/x86_64/cpu.c | 12
> > > > > > > > > drivers/video/Kconfig | 1 +
> > > > > > > > > 4 files changed, 25 insertions(+)
> > > > > > > > >
> > > > > > > > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> > > > > > > > > index 99e59d94c606..6b532d712ee8 100644
> > > > > > > > > --- a/arch/x86/Kconfig
> > > > > > > > > +++ b/arch/x86/Kconfig
> > > > > > > > > @@ -723,6 +723,14 @@ config ROM_TABLE_SIZE
> > > > > > > > > hex
> > > > > > > > > default 0x1
> > > > > > > > >
> > > > > > > > > +config X86_HARDFP
> > > > > > > > > + bool "Support hardware floating point"
> > > > > > > > > + help
> > > > > > > > > + U-Boot generally does not make use of floating
> > > > > > > > > point. Where this is
> > > > > > > > > + needed, it can be enabled using this option. This
> > > > > > > > > adjusts the
> > > > > > > > > + start-up code for 64-bit mode and changes the
> > > > > > > > > compiler options for
> > > > > > > > > + 64-bit to enable SSE.
> > > > > > > >
> > > > > > > > As discussed in another thread, this option should be made
> > > > > > > > global to
> > > > > > > > all architectures and by default no.
> > > > > > > >
> > > > > > > > > +
> > > > > > > > > config HAVE_ITSS
> > > > > > > > > bool "Enable ITSS"
> > > > > > > > > help
> > > > > > > > > diff --git a/arch/x86/config.mk b/arch/x86/config.mk
> > > > > > > > > index 26ec1af2f0b0..2e3a7119e798 100644
> > > > > > > > > --- a/arch/x86/config.mk
> > > > > > > > > +++ b/arch/x86/config.mk
> > > > > > > > > @@ -27,9 +27,13 @@ ifeq ($(IS_32BIT),y)
> > > > > > > > > PLATFORM_CPPFLAGS += -march=i386 -m32
> > > > > > > > > else
> > > > > > > > > PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic)
> > > > > > > > > -fno-common -march=core2 -m64
> > > > > > > > > +
> > > > > > > > > +ifndef CONFIG_X86_HARDFP
> > > > > > > > > PLATFORM_CPPFLAGS += -mno-mmx -mno-sse
> > > > > > > > > endif
> > > > > > > > >
> > > > > > > > > +endif # IS_32BIT
> > > > > > > > > +
> > > > > > > > > PLATFORM_RELFLAGS += -fdata-sections -ffunction-sections
> > > > > > > > > -fvisibility=hidden
> > > > > > > > >
> > > > > > > > > KBUILD_LDFLAGS += -Bsymbolic -Bsymbolic-functions
> > > > > > > > > diff --git a/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > > b/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > > index 2647bff891f8..5ea746ecce4d 100644
> > > > > > > > > --- a/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > > +++ b/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > > @@ -10,6 +10,7 @@
> > > > > > > > > #include
> > > > > > > > > #include
> > > > > > > > > #include
> > > > > > > > > +#include
> > > > > > > > >
> > > > > > > > > DECLARE_GLOBAL_DATA_PTR;
> > > > > > > > >
> > > > > > > > > @@ -39,11 +40,22 @@ int x86_mp_init(void)
> > > > > > > > > return 0;
> > > > > > > > > }
> > > > > > > > >
> > > > > > > > > +/* enable SSE features for hardware floating point */
> > > > > > > > > +static void setup_sse_features(void)
> > > > > > > > > +{
> > > > > > > > > + asm ("mov %%cr4, %%rax\n" \
> > > > > > > > > + "or %0, %%rax\n" \
> > > > > > > > > + "mov %%rax, %%cr4\n" \
> > > > > > > > > + : : "i" (X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT) :
> > > > > > > > > "eax");
> > > > > > > > > +}
> > > > > > > > > +
> > > > > > > > > int x86_cpu_reinit_f(void)
> > > > > > > > > {
> > > > > > > > > /* set the vendor to Intel so that
> > > > > > > > > native_calibrate_tsc() works */
> > > > > > > > > gd->arch.x86_vendor = X86_VENDOR_INTEL;
Re: [PATCH v4 09/12] x86: Enable SSE in 64-bit mode
Hi Tom,
On Wed, Nov 15, 2023 at 12:22 AM Tom Rini wrote:
>
> On Tue, Nov 14, 2023 at 09:49:08AM +0800, Bin Meng wrote:
> > Hi Tom,
> >
> > On Tue, Nov 14, 2023 at 7:52 AM Tom Rini wrote:
> > >
> > > On Tue, Nov 14, 2023 at 07:46:36AM +0800, Bin Meng wrote:
> > > > Hi Tom,
> > > >
> > > > On Tue, Nov 14, 2023 at 6:59 AM Tom Rini wrote:
> > > > >
> > > > > On Mon, Nov 13, 2023 at 03:28:13PM -0700, Simon Glass wrote:
> > > > > > Hi Bin,
> > > > > >
> > > > > > On Mon, 13 Nov 2023 at 15:08, Bin Meng wrote:
> > > > > > >
> > > > > > > Hi Simon,
> > > > > > >
> > > > > > > On Mon, Nov 13, 2023 at 4:03 AM Simon Glass
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > This is needed to support Truetype fonts. In any case, the
> > > > > > > > compiler
> > > > > > > > expects SSE to be available in 64-bit mode. Provide an option
> > > > > > > > to enable
> > > > > > > > SSE so that hardware floating-point arithmetic works.
> > > > > > > >
> > > > > > > > Signed-off-by: Simon Glass
> > > > > > > > Suggested-by: Bin Meng
> > > > > > > > ---
> > > > > > > >
> > > > > > > > Changes in v4:
> > > > > > > > - Use a Kconfig option
> > > > > > > >
> > > > > > > > arch/x86/Kconfig | 8
> > > > > > > > arch/x86/config.mk| 4
> > > > > > > > arch/x86/cpu/x86_64/cpu.c | 12
> > > > > > > > drivers/video/Kconfig | 1 +
> > > > > > > > 4 files changed, 25 insertions(+)
> > > > > > > >
> > > > > > > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> > > > > > > > index 99e59d94c606..6b532d712ee8 100644
> > > > > > > > --- a/arch/x86/Kconfig
> > > > > > > > +++ b/arch/x86/Kconfig
> > > > > > > > @@ -723,6 +723,14 @@ config ROM_TABLE_SIZE
> > > > > > > > hex
> > > > > > > > default 0x1
> > > > > > > >
> > > > > > > > +config X86_HARDFP
> > > > > > > > + bool "Support hardware floating point"
> > > > > > > > + help
> > > > > > > > + U-Boot generally does not make use of floating point.
> > > > > > > > Where this is
> > > > > > > > + needed, it can be enabled using this option. This
> > > > > > > > adjusts the
> > > > > > > > + start-up code for 64-bit mode and changes the
> > > > > > > > compiler options for
> > > > > > > > + 64-bit to enable SSE.
> > > > > > >
> > > > > > > As discussed in another thread, this option should be made global
> > > > > > > to
> > > > > > > all architectures and by default no.
> > > > > > >
> > > > > > > > +
> > > > > > > > config HAVE_ITSS
> > > > > > > > bool "Enable ITSS"
> > > > > > > > help
> > > > > > > > diff --git a/arch/x86/config.mk b/arch/x86/config.mk
> > > > > > > > index 26ec1af2f0b0..2e3a7119e798 100644
> > > > > > > > --- a/arch/x86/config.mk
> > > > > > > > +++ b/arch/x86/config.mk
> > > > > > > > @@ -27,9 +27,13 @@ ifeq ($(IS_32BIT),y)
> > > > > > > > PLATFORM_CPPFLAGS += -march=i386 -m32
> > > > > > > > else
> > > > > > > > PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic)
> > > > > > > > -fno-common -march=core2 -m64
> > > > > > > > +
> > > > > > > > +ifndef CONFIG_X86_HARDFP
> > > > > > > > PLATFORM_CPPFLAGS += -mno-mmx -mno-sse
> > > > > > > > endif
> > > > > > > >
> > > > > > > > +endif # IS_32BIT
> > > > > > > > +
> > > > > > > > PLATFORM_RELFLAGS += -fdata-sections -ffunction-sections
> > > > > > > > -fvisibility=hidden
> > > > > > > >
> > > > > > > > KBUILD_LDFLAGS += -Bsymbolic -Bsymbolic-functions
> > > > > > > > diff --git a/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > b/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > index 2647bff891f8..5ea746ecce4d 100644
> > > > > > > > --- a/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > +++ b/arch/x86/cpu/x86_64/cpu.c
> > > > > > > > @@ -10,6 +10,7 @@
> > > > > > > > #include
> > > > > > > > #include
> > > > > > > > #include
> > > > > > > > +#include
> > > > > > > >
> > > > > > > > DECLARE_GLOBAL_DATA_PTR;
> > > > > > > >
> > > > > > > > @@ -39,11 +40,22 @@ int x86_mp_init(void)
> > > > > > > > return 0;
> > > > > > > > }
> > > > > > > >
> > > > > > > > +/* enable SSE features for hardware floating point */
> > > > > > > > +static void setup_sse_features(void)
> > > > > > > > +{
> > > > > > > > + asm ("mov %%cr4, %%rax\n" \
> > > > > > > > + "or %0, %%rax\n" \
> > > > > > > > + "mov %%rax, %%cr4\n" \
> > > > > > > > + : : "i" (X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT) : "eax");
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > int x86_cpu_reinit_f(void)
> > > > > > > > {
> > > > > > > > /* set the vendor to Intel so that
> > > > > > > > native_calibrate_tsc() works */
> > > > > > > > gd->arch.x86_vendor = X86_VENDOR_INTEL;
> > > > > > > > gd->arch.has_mtrr = true;
> > > > > > > > + if (IS_ENABLED(CONFIG_X86_HARDFP))
> > > > > > > > + setup_sse_features();
> > > > > > > >
> > > > > > > > return 0;
> > > > > > > > }
> > > > > > > > diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> > >
Booting an x86-64 BIOS Machine
Hello, I have an application in which I need to boot an x86-64 machine with a legacy BIOS. I've read about the U-Boot executable, the SPL, and the TPL. I'm just having a bit of trouble figuring out which pieces are supposed to go where. Looking to Grub, I see there exists a minimal "boot.img" file, which gets installed into the MBR of the drive and subsequently bootstraps the rest of the sequence. My impression was that either the TPL or the SPL would play that same role, but even removing basically all options, the binary produced is still too large to fit in this 512 Byte area. Syslinux also works on my device, and the "mbr.bin" and "gptmbr.bin" files play the same role for that bootloader. How can I make optimizations to generate an image small enough to fit into the MBR of my device to allow BIOS to load the rest of the bootloader? -- Desone Burns II Software Engineer III seegrid.com • 412-379-4500 m: 623-258-7361
Re: [PATCH v3 2/5] firmware: scmi: support protocols on sandbox only if enabled
On Mon, 13 Nov 2023 at 19:14, AKASHI Takahiro wrote: > > This change will be useful when we manually test SCMI on sandbox > by enabling/disabling a specific SCMI protocol. > > Signed-off-by: AKASHI Takahiro > --- > v9 > * use CONFIG_IS_ENABLED() rather than IS_ENABLED() > * remove goto by introducing a not_supported() function > --- > drivers/firmware/scmi/sandbox-scmi_agent.c | 30 ++-- > drivers/firmware/scmi/sandbox-scmi_devices.c | 78 > 2 files changed, 71 insertions(+), 37 deletions(-) Reviewed-by: Simon Glass
Re: [PATCH] spl: fix TPL_SYS_MALLOC_F description
On Tue, 14 Nov 2023 at 04:30, John Keeping wrote: > > This config option enables the malloc() pool in TPL not the SPL. Fix > the description to accurately reflect this. > > Fixes: fd8497dae54 (spl: Create proper symbols for enabling the malloc() pool) > Signed-off-by: John Keeping > --- > Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass
Re: [PATCH v3 1/5] test: dm: skip scmi tests against disabled protocols
On Mon, 13 Nov 2023 at 19:14, AKASHI Takahiro wrote: > > This is a precautionary change to make scmi tests workable whether or not > a specific protocol be enabled. If a given protocol is not configured, > we skip the test by returning -EAGAIN. > > Signed-off-by: AKASHI Takahiro > --- > v9 > * return -EAGAIN if we want to skip a test > * use CONFIG_IS_ENABLED() rather than IS_ENABLED() > --- > test/dm/scmi.c | 12 > 1 file changed, 12 insertions(+) Reviewed-by: Simon Glass
Re: [PATCH 5/5] test: dm: add scmi command test
Hi,
On Mon, 13 Nov 2023 at 18:41, AKASHI Takahiro
wrote:
>
> On Mon, Nov 13, 2023 at 11:01:17AM -0700, Simon Glass wrote:
> > Hi,
> >
> > On Sun, 12 Nov 2023 at 18:46, AKASHI Takahiro
> > wrote:
> > >
> > > Hi Tom,
> > >
> > > On Fri, Nov 10, 2023 at 01:21:37PM -0500, Tom Rini wrote:
> > > > On Wed, Oct 25, 2023 at 02:14:27PM +0900, AKASHI Takahiro wrote:
> > > >
> > > > > In this test, "scmi" command is tested against different sub-commands.
> > > > > Please note that scmi command is for debug purpose and is not intended
> > > > > in production system.
> > > > >
> > > > > Signed-off-by: AKASHI Takahiro
> > > > > Reviewed-by: Simon Glass
> > > > > Reviewed-by: Etienne Carriere
> > > >
> > > > The test part of this still fails:
> > > > https://source.denx.de/u-boot/u-boot/-/jobs/732077
> > > >
> > > > I don't know why more output wasn't captured, when I run it locally
> > > > instead I get:
> > > > == FAILURES
> > > > ===
> > > > ___ test_ut[ut_dm_dm_test_scmi_cmd]
> > > > ___
> > > > test/py/u_boot_spawn.py:195: in expect
> > > > c = os.read(self.fd, 1024).decode(errors='replace')
> > > > E OSError: [Errno 5] Input/output error
> > > >
> > > > During handling of the above exception, another exception occurred:
> > > > test/py/tests/test_ut.py:502: in test_ut
> > > > output = u_boot_console.run_command('ut ' + ut_subtest)
> > > > test/py/u_boot_console_base.py:266: in run_command
> > > > m = self.p.expect([self.prompt_compiled] + self.bad_patterns)
> > > > test/py/u_boot_spawn.py:204: in expect
> > > > raise ValueError('U-Boot exited with %s' % info)
> > > > E ValueError: U-Boot exited with signal 11 (SIGSEGV)
> > >
> > >
> > > The command uses global variables which hold pointers to 'struct udevice'
> > > which are to be shared between the main and the sub-commands.
> > > Since pytest framework executes ut tests twice, once with a (normal?)
> > > device
> > > tree and once with a flat tree, udevices will be *voided* between
> > > two executions.
> >
> > Are you able to put the var in the uclass-priv data instead? The state
> > should be cleared before running each DM test.
>
> Well, I don't think we need such a trick.
> As you can see, we may simply fetch/find necessary udevices
> every time the command is called.
> It is enough given that the command is mainly for debug purpose.
OK. Let's see how it goes. When you mention global vars I get a bit
nervous, but we do have these in some places.
Regards,
Simon
>
> -Takahiro Akashi
>
>
> > Regards,
> > Simon
> >
> >
> > >
> > > I will fix it in v2.
> > >
> > > Thanks,
> > > -Takahiro Akashi
> > >
> > >
> > > > Captured stdout call
> > > > -
> > > > => ut dm dm_test_scmi_cmd
> > > > Test: dm_test_scmi_cmd: scmi.c
> > > > SCMI device: scmi
> > > > protocol version: 0x2
> > > > # of agents: 2
> > > > 0: platform
> > > > > 1: OSPM
> > > > # of protocols: 4
> > > > Power domain management
> > > > Clock management
> > > > Reset domain management
> > > > Voltage domain management
> > > > vendor: U-Boot
> > > > sub vendor: Sandbox
> > > > impl version: 0x1
> > > > Denying access to device:0 failed (-13)
> > > > Denying access to protocol:0x14 on device:0 failed (-13)
> > > > Reset failed (-13)
> > > > Test: dm_test_scmi_cmd: scmi.c (flat tree)
> > > > SCMI device: Q
> > > > === short test summary info
> > > > ===
> > > > FAILED test/py/tests/test_ut.py::test_ut[ut_dm_dm_test_scmi_cmd] -
> > > > ValueError: U-Boot exited...
> > > >
> > > > --
> > > > Tom
> > >
> > >
Re: [PATCH 01/13] sandbox: move asm-generic include to the end of file
On Tue, 14 Nov 2023 at 04:03, Igor Prusov wrote: > > Generic version of io.h should be included at the end of > architecture-specific ones to make sure that arch implementations are > used and to avoid redefinitions. > > Signed-off-by: Igor Prusov > --- > > arch/sandbox/include/asm/io.h | 28 ++-- > 1 file changed, 14 insertions(+), 14 deletions(-) Reviewed-by: Simon Glass
Re: [PATCH v2 1/1] efi_loader: expose the device-tree file name
On Tue, Nov 14, 2023 at 08:09:52PM +0100, Mark Kettenis wrote: > > From: Simon Glass > > Date: Fri, 3 Nov 2023 13:17:18 -0600 > > > > Hi, > > > > On Mon, 23 Oct 2023 at 11:06, Mark Kettenis wrote: > > > > > > > Date: Mon, 23 Oct 2023 12:34:55 -0400 > > > > From: Tom Rini > > > > > > > > On Mon, Oct 23, 2023 at 05:37:34PM +0200, Mark Kettenis wrote: > > > > > > From: Simon Glass > > > > > > Date: Mon, 23 Oct 2023 00:08:40 -0700 > > > > > > > > > > > > > > fdt_node_check_compatible() does most of the work...then you > > > > > > > > need to > > > > > > > > check which FDT has the most specific match (i.e. latest in the > > > > > > > > string > > > > > > > > list). That handles things like board revisions, variants, etc. > > > > > > > > > > > > > > > > My concern is about adding a feature when there is already a > > > > > > > > defined > > > > > > > > spec and mechanism for this to work. What happens when we load > > > > > > > > the > > > > > > > > file and the compatible is wrong? > > > > > > > > > > > > > > > > At best, I see the filename as a hint. > > > > > > > > > > > > > > > > [Perhaps this is the wrong time to ask, but why are kernels +DT > > > > > > > > not > > > > > > > > shipped in FIT on ARM?] > > > > > > > > > > > > > > FIT is U-Boot specific. For Linux distributions it is easier to > > > > > > > use a > > > > > > > firmware agnostic method of booting. > > > > > > > > > > > > I'd like to suggest that distros use both. Then U-Boot can work as > > > > > > it > > > > > > was designed and we can avoid these work-arounds. > > > > > > > > > > > > FIT is actually implemented in various other bootloaders. In fact > > > > > > perhaps grub is the only one that doesn't? I can't think of any > > > > > > others. > > > > > > > > > > Simon, please stop pushing this. OpenBSD's bootloader does not > > > > > support FIT and we have no interest in supporting it. Our users > > > > > expect to be able to just copy a new kernel in place and use it and > > > > > our OS upgrade procedure depends on this as well. And this is > > > > > incompatble with FIT. I've explained this about a dozen times to you > > > > > now. > > > > > > > > In the context of this thread, genuinely, how will OpenBSD (and the rest > > > > of the BSD families) operate? I agree U-Boot doesn't want to have to > > > > know all of the UFSes, so that means the SCT will be populated either by > > > > the DT passed to U-Boot, or the DT we were built with. Is it that since > > > > the next stage is an EFI app, it will check that variable and use that > > > > hint? > > > > > > Yes, that is exactly what I want to do. Hopefully the DT that is > > > passed to U-Boot or that U-Boot was built with will be good enough in > > > most cases. But when it isn't users can use the OpenBSD bootloader > > > (which is an EFI app) to load an updated DT. > > > > > > I can't speak for the other BSDs, but I think both FreeBSD and NetBSD > > > have a very similar boot mechanism. > > > > I've been thinking about this patch a bit more, and I have grave misgivings. > > > > I predict that if we take this, it will become an ABI from U-Boot and > > we will not be able to drop it. > > Why would we want to drop it? Because filename isn't an obvious great idea to encode as ABI? It's not formally one right now, even with the Linux Kernel installing the ARM=arm dtb files in a single directory even after re-organizing the source directory to match ARCH=arm64 with per-vendor directories. > > Here is what I suggest instead: provide a protocol for U-Boot to > > provide the DT over EFI. Provide any information needed by U-Boot, > > such as the directory containing the files. > > So you want something more complicated than a simple EFI variable? Why? I think part of this all came out of the issues Fedora was having where they (a) need to override the DTB to ensure the kernel boots and (b) oops, the logic they had been using wasn't being invoked (unexpected Fedora-based change). Some way to say "here is the device tree you should use" needs to come from somewhere. It would be great if the running device tree was already correct, but we don't know that it will be, and that's also still not a U-Boot problem. One of the examples here was that the Pi firmware DTB wasn't 100% correct. I forget what the exact fixup ended up being there. So, some sort of hint for the board to say "here is the device tree you should use". I know you earlier noted that you didn't think U-Boot would want to know how to read N different UFS formats, and yes, true. Maybe that just means that it needs to reside on some other filesystem format, like Linux has to do? I don't know. How to best do that, I don't know. > > We already have the ability to put a DT in the system table. We > > already have a way to package DT into a FIT and allow U-Boot to select > > the correct one. > > Please stop pushing FIT for use cases where it doesn't make sense. OK, but where is that? At least part of the "we
Re: [PATCH v2 2/5] image: Show the load address when decompressing
On Sat, Nov 11, 2023 at 08:49:54PM -0700, Simon Glass wrote: > The destination address for decompression (or copying) is useful > information. Show this to the user while booting, e.g.: > >Uncompressing Kernel Image (no loading done) to 208 > > Signed-off-by: Simon Glass Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
[PATCH] timer-uclass: Always use "clock-frequency" property as fallback
Currently the "clock-frequency" DT property is only being considered as an
fallback if either there is no clock driver, the clock driver implements
the request-op correctly or there is no clock defined for the timer at all.
This patch makes "clock-frequency" also being picked as a fallback if
getting the clock-rate fails, since clk_get(_by_index) will return no
error, if a clock driver does not implement the request-op and does also
not support getting the rate of the clock in question.
timer_post_probe will take care if the property does not exist in the DT or
is defined as 0.
Signed-off-by: Alex Bee
---
This is currently an issue for Rockchip RK3188 and potentially also for RK3368:
The clock driver does not implement the request-op. Even if we would add it:
timer-uclass always picks the first clock and the DT bindings for Rockchip timer
requires us to place the pclk first and and the timer source clock second.
drivers/timer/timer-uclass.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index 0c2018bfe3..60ff65529a 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -66,13 +66,13 @@ static int timer_pre_probe(struct udevice *dev)
err = clk_get_by_index(dev, 0, _clk);
if (!err) {
ret = clk_get_rate(_clk);
- if (IS_ERR_VALUE(ret))
- return ret;
- uc_priv->clock_rate = ret;
- } else {
- uc_priv->clock_rate =
- dev_read_u32_default(dev, "clock-frequency", 0);
+ if (!IS_ERR_VALUE(ret)) {
+ uc_priv->clock_rate = ret;
+ return 0;
+ }
}
+
+ uc_priv->clock_rate = dev_read_u32_default(dev,
"clock-frequency", 0);
}
return 0;
--
2.42.0
Re: [PATCH] configs: rockpro64: Enable SPI command and full BOOTSTD
Hi Jonas / Simon, I have submitted a patch based on Jonas's suggestion. Apologies, I am new to email based patch management and it went as new thread (at least for me) It's here - https://lore.kernel.org/u-boot/20231114203309.852289-...@shantur.com/ Kind regards, Shantur On Mon, Nov 13, 2023 at 12:07 AM Shantur Rathore wrote: > > Hey Jonas, > > This sounds like a good idea. > Please implement this. > > Kind regards, > Shantur > > On Sun, Nov 12, 2023 at 3:01 PM Jonas Karlman wrote: > > > > Hi Shantur, > > > > On 2023-11-12 15:21, Shantur Rathore wrote: > > > Hey Jonas, > > > > > >> For normal generic use the full bootstd commands should not be needed, > > >> do you have special scripting requirements that require access to full > > >> bootstd commands? > > >> > > >> All rockchip boards use standard boot, this only enables full commands > > >> for one particular board, why is this board special? Or > > > > > > This board isn't special. > > > > > >> is there merit > > >> to imply enable of full commands for all rockchip boards? > > > > > > Maybe not only on rockchip boards but all boards. > > > > > > Do we need full commands in general ? - Maybe not > > > > > > Then why did you need to enable full commands ? > > > Bootstd works when the distro used is supporting it. In my case when I > > > installed the distro (Armbian), EFI was installed to > > > /boot/efi/EFI/debian by default instead of /boot/efi/EFI/boot as > > > expected by Bootstd. > > > Bootstd couldn't find the EFI and failed to boot. In this scenario > > > there is no way to figure out what's going on, what bootmethods / > > > bootflows is bootstd able to find or try to manually boot some. > > > To be able to support the smallest bit of debugging you end up > > > building U-Boot from scratch to enable bootstd full for bootstd info > > > commands. > > > All other commands in U-boot by default come with options to display > > > more information ( for ex. nvme info, nvme detail, usb tree, usb info, > > > usb dev, fatinfo and many more ) then why is bootstd restricted? > > > Thus, in my opinion we should enable BOOTSTD_FULL for users to be able > > > to see more information. > > > Restricting might be beneficial for end user devices but atleast > > > development devices like RockPro64 should come with BOOTSTD_FULL by > > > default. > > > > Thanks for clarifying the need! And I also see the benefit of having > > full feature commands enabled. > > > > For RK35xx family of devices I have tried to ensure all boards have same > > features and sounds like something like below could benefit all rk > > boards, or at least for ROCKCHIP_RK3568 and ROCKCHIP_RK3588 boards. > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index c39ae40335a0..07e93a9c7ad5 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -1987,6 +1987,7 @@ config ARCH_ROCKCHIP > > imply CMD_DM > > imply DEBUG_UART_BOARD_INIT > > imply BOOTSTD_DEFAULTS > > + imply BOOTSTD_FULL if BOOTSTD_DEFAULTS > > imply FAT_WRITE > > imply SARADC_ROCKCHIP > > imply SPL_SYSRESET > > > > > > Regards, > > Jonas > > > > > > > > Kind regards, > > > Shantur > > > > > > On Sun, Nov 12, 2023 at 12:50 PM Jonas Karlman wrote: > > >> > > >> Hi Shantur, > > >> > > >> On 2023-11-12 13:34, Shantur Rathore wrote: > > >>> Hi Jonas, > > >>> > > The CMD_SPI is not used to interact with the SPI flash. > > > > CMD_SF is already enabled and you can use "sf probe" and any other sf > > related action to interact with the SPI flash on this board. > > > > >>> > > >>> You are right, this is not needed, thanks for correcting me. > > >>> I will update my patch. > > >>> > > What is the reasoning behind enabling full bootstd commands? Especially > > why just this board need it enabled by default. > > > > Standard boot is already fully functional, it just does not have full > > features commands enabled by default. > > >>> > > >>> By default standard boot only allows you to boot from the first > > >>> available boot device. > > >>> This board supports SDCard, NVME (via PCIe port), USB and network boot > > >>> and with BOOTSTD_FULL we can choose what to exactly boot. > > >>> The boot_targets environment variable only allows you to choose which > > >>> device to boot, not which boot method / flow to use. > > >>> We have ample space in SPI Flash, so why not let it have the full > > >>> potential of U-Boot by default. > > >> > > >> You can control boot targets using the boot_targets env var and boot > > >> methods using the bootmeths env var. > > >> > > >> https://docs.u-boot.org/en/latest/develop/bootstd.html#controlling-ordering > > >> > > >> For normal generic use the full bootstd commands should not be needed, > > >> do you have special scripting requirements that require access to full > > >> bootstd commands? > > >> > > >> All rockchip boards use standard boot, this only enables full commands > > >>
Re: [PATCH] common: usb-hub: Reset hub port before scanning
+Patrice +Patrick from get_maintainer script
On Mon, Nov 13, 2023 at 1:28 PM Shantur Rathore wrote:
>
> +Simon +Trini
>
> On Fri, Nov 10, 2023 at 2:13 PM Shantur Rathore wrote:
> >
> > Currently when a hub is turned on, all the ports are powered on.
> > This works well for hubs which have individual power control.
> >
> > For the hubs without individual power control this has no effect.
> > Mostly in these scenarios the hub port is powered before the USB
> > controller is enabled, this can lead to some devices in unexpected
> > state.
> >
> > With this patch, we explicitly reset the port while powering up hub
> > This resets the port for hubs without port power control and has
> > no effect on hubs with port power control as the port is still off.
> >
> > Before this patch AMicro AM8180 based NVME to USB adapter won't be
> > detected as a USB3.0 Mass Storage device but with this it works as
> > expected.
> >
> > Tested working after this patch:
> > 1. AMicro AM8180 based NVME to USB Adapter
> > 2. Kingston DataTraveler 3.0
> > 3. GenesysLogic USB3.0 Hub
> >
> > The drives were tested while connected directly and via the hub.
> > ---
> > common/usb_hub.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/common/usb_hub.c b/common/usb_hub.c
> > index 85c0822d8b..06fe436add 100644
> > --- a/common/usb_hub.c
> > +++ b/common/usb_hub.c
> > @@ -174,8 +174,10 @@ static void usb_hub_power_on(struct usb_hub_device
> > *hub)
> >
> > debug("enabling power on all ports\n");
> > for (i = 0; i < dev->maxchild; i++) {
> > + usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_RESET);
> > + debug("Reset : port %d returns %lX\n", i + 1, dev->status);
> > usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
> > - debug("port %d returns %lX\n", i + 1, dev->status);
> > + debug("PowerOn : port %d returns %lX\n", i + 1,
> > dev->status);
> > }
> >
> > #ifdef CONFIG_SANDBOX
> > --
> > 2.40.1
> >
[PATCH v2] arch: arm: Kconfig: Enable BOOTSTD_FULL for Rockchip SoCs
Signed-off-by: Shantur Rathore --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c98..fca6ef6d7e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1986,6 +1986,7 @@ config ARCH_ROCKCHIP imply CMD_DM imply DEBUG_UART_BOARD_INIT imply BOOTSTD_DEFAULTS + imply BOOTSTD_FULL if BOOTSTD_DEFAULTS imply FAT_WRITE imply SARADC_ROCKCHIP imply SPL_SYSRESET -- 2.40.1
[PATCH] arm: dts: k3-am625-verdin-wifi-dev-u-boot.dtsi: Fix DMA with BCDMA
BCDMA can be used at SPL for OSPI boot and mem-to-mem DMA
so add "bootph-all" to BCDMA node.
Suggested-by: Nishanth Menon
Fixes: 9a3f2b6798b0 ("arm: dts: k3-am625-verdin-wifi-dev-u-boot.dtsi: Fix
DMA/Ethernet")
Signed-off-by: Roger Quadros
---
arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
index 75cb60b57d..588d9594a8 100644
--- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
@@ -53,6 +53,7 @@
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
"ringrt" , "cfg", "tchan", "rchan";
+ bootph-all;
};
_pktdma {
base-commit: 92b27528d777ce85362af45e7d2974a6c856219b
--
2.34.1
Re: [PATCH v2 1/1] efi_loader: expose the device-tree file name
> From: Simon Glass > Date: Fri, 3 Nov 2023 13:17:18 -0600 > > Hi, > > On Mon, 23 Oct 2023 at 11:06, Mark Kettenis wrote: > > > > > Date: Mon, 23 Oct 2023 12:34:55 -0400 > > > From: Tom Rini > > > > > > On Mon, Oct 23, 2023 at 05:37:34PM +0200, Mark Kettenis wrote: > > > > > From: Simon Glass > > > > > Date: Mon, 23 Oct 2023 00:08:40 -0700 > > > > > > > > > > > > fdt_node_check_compatible() does most of the work...then you need > > > > > > > to > > > > > > > check which FDT has the most specific match (i.e. latest in the > > > > > > > string > > > > > > > list). That handles things like board revisions, variants, etc. > > > > > > > > > > > > > > My concern is about adding a feature when there is already a > > > > > > > defined > > > > > > > spec and mechanism for this to work. What happens when we load the > > > > > > > file and the compatible is wrong? > > > > > > > > > > > > > > At best, I see the filename as a hint. > > > > > > > > > > > > > > [Perhaps this is the wrong time to ask, but why are kernels +DT > > > > > > > not > > > > > > > shipped in FIT on ARM?] > > > > > > > > > > > > FIT is U-Boot specific. For Linux distributions it is easier to use > > > > > > a > > > > > > firmware agnostic method of booting. > > > > > > > > > > I'd like to suggest that distros use both. Then U-Boot can work as it > > > > > was designed and we can avoid these work-arounds. > > > > > > > > > > FIT is actually implemented in various other bootloaders. In fact > > > > > perhaps grub is the only one that doesn't? I can't think of any > > > > > others. > > > > > > > > Simon, please stop pushing this. OpenBSD's bootloader does not > > > > support FIT and we have no interest in supporting it. Our users > > > > expect to be able to just copy a new kernel in place and use it and > > > > our OS upgrade procedure depends on this as well. And this is > > > > incompatble with FIT. I've explained this about a dozen times to you > > > > now. > > > > > > In the context of this thread, genuinely, how will OpenBSD (and the rest > > > of the BSD families) operate? I agree U-Boot doesn't want to have to > > > know all of the UFSes, so that means the SCT will be populated either by > > > the DT passed to U-Boot, or the DT we were built with. Is it that since > > > the next stage is an EFI app, it will check that variable and use that > > > hint? > > > > Yes, that is exactly what I want to do. Hopefully the DT that is > > passed to U-Boot or that U-Boot was built with will be good enough in > > most cases. But when it isn't users can use the OpenBSD bootloader > > (which is an EFI app) to load an updated DT. > > > > I can't speak for the other BSDs, but I think both FreeBSD and NetBSD > > have a very similar boot mechanism. > > I've been thinking about this patch a bit more, and I have grave misgivings. > > I predict that if we take this, it will become an ABI from U-Boot and > we will not be able to drop it. Why would we want to drop it? > Here is what I suggest instead: provide a protocol for U-Boot to > provide the DT over EFI. Provide any information needed by U-Boot, > such as the directory containing the files. So you want something more complicated than a simple EFI variable? Why? > We already have the ability to put a DT in the system table. We > already have a way to package DT into a FIT and allow U-Boot to select > the correct one. Please stop pushing FIT for use cases where it doesn't make sense. > With something like this it will be impossible for U-Boot to boot a > distro without using grub, etc. since it won't know what DT to use. > This information would be held in a script somewhere which no one can > figure out without executing it. Huh? U-Boot already knows the name of name of the DT filename. It is what we currently use in the distroboot scripts. You are free to use a U-Boot specific bootflow based on that if you really want to. But many distros (or other OSes like OpenBSD) really don't want to maintain support for multiple boot flows.
Re: [PATCH v2 3/5] bootm: Allow omitting the load address
On Tue, Nov 14, 2023 at 11:38:46AM -0500, Tom Rini wrote: > On Sat, Nov 11, 2023 at 08:49:55PM -0700, Simon Glass wrote: > > > The kernel_noload image type indicates that no loading is to be done by > > U-Boot. This works well when the image is uncompressed. > > > > When the image is compressed, loading is of course required. The load > > address in the FIT is used for loading. > > > > However a FIT built from Linux v6.6 supports about 990 boards. Each has > > a different memory arrangement, so no one load address is suitable. > > Therefore the 'load' address in the kernel node is not useful. > > > > It would be better in this case to be able to omit the load address and > > have U-Boot choose something suitable. The kernel_addr_r environment > > variable seems to be a more reliable final address for the kernel. Use > > that as a backup when the load address is missing. > > > > Similarly, use the load address as the entry address when the latter is > > omitted. > > > > Update the FIT documentation accordingly. > > > > Note that mkimage still requires each image in a FIT to have a load > > address, at least for now. > > > > Another option would be to create a new Kconfig for this, or to use a > > region of memory known to be free, e.g. calculated from the DRAM banks. > > But in any case we should try to avoid conflicting with the > > kernel_addr_r variable. So the approach in this patch seems reasonable > > to me. > > > > It might perhaps be useful to introduce an 'entry-offset' property > > which allows the entry to be set as an offset from the load address, > > whether that is explicit or calculated. > > > > Signed-off-by: Simon Glass > > OK, so I dug out what I was trying to determine before, and while I > might see if I can bisect down to when this regressed, it might be a > little hard given that my previously functional image is from 2013. > > What should happen in the case of kernel_noload, and why the later patch > to fail on kernel_noload + compression, is that we don't move the kernel > contents of the FIT. We don't need the load address to be set because > we're using it where it is. What happened before in the case of the > ramdisk, and more importantly device tree, is what I why I want to > bisect down to when my image stopped working. But: Well, it seems I was wrong. I was able to (with only minor difficulty) go back to v2013.04, which was just after I made the fitImage I was trying to test and it doesn't bootm as-is. So whereas I had thought we had a defined and working case for kernel_noload and FIT images as you describe them, that does not seem to be the case. So please disregard this and I will review the patch again in light of what I've confirmed now, sorry for the incorrect feedback here and in the other thread. -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 1/5] image: Correct load_bug typo
On Sat, Nov 11, 2023 at 08:49:53PM -0700, Simon Glass wrote: > Correct a typo in the function comment for image_decomp(). > > Signed-off-by: Simon Glass Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
[PATCH 1/1] acpi: consider XSDT in acpi_find_table()
The RSDT table is deprecated and does not exist on all systems.
By preference scan XSDT for the table to find. If no XSDT table exists, try
to use the RSDT table.
Signed-off-by: Heinrich Schuchardt
---
lib/acpi/acpi.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/lib/acpi/acpi.c b/lib/acpi/acpi.c
index 14b15754f4..3938946fc6 100644
--- a/lib/acpi/acpi.c
+++ b/lib/acpi/acpi.c
@@ -16,18 +16,30 @@ struct acpi_table_header *acpi_find_table(const char *sig)
{
struct acpi_rsdp *rsdp;
struct acpi_rsdt *rsdt;
+ struct acpi_xsdt *xsdt;
int len, i, count;
rsdp = map_sysmem(gd_acpi_start(), 0);
if (!rsdp)
return NULL;
- rsdt = map_sysmem(rsdp->rsdt_address, 0);
- len = rsdt->header.length - sizeof(rsdt->header);
- count = len / sizeof(u32);
+ xsdt = map_sysmem(rsdp->xsdt_address, 0);
+ if (xsdt) {
+ len = xsdt->header.length - sizeof(xsdt->header);
+ count = len / sizeof(u64);
+ } else {
+ rsdt = map_sysmem(rsdp->rsdt_address, 0);
+ if (!rsdt)
+ return NULL;
+ len = rsdt->header.length - sizeof(rsdt->header);
+ count = len / sizeof(u32);
+ }
for (i = 0; i < count; i++) {
struct acpi_table_header *hdr;
- hdr = map_sysmem(rsdt->entry[i], 0);
+ if (xsdt)
+ hdr = map_sysmem(xsdt->entry[i], 0);
+ else
+ hdr = map_sysmem(rsdt->entry[i], 0);
if (!memcmp(hdr->signature, sig, ACPI_NAME_LEN))
return hdr;
if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN)) {
--
2.40.1
Re: [PATCH v2 3/5] bootm: Allow omitting the load address
On Sat, Nov 11, 2023 at 08:49:55PM -0700, Simon Glass wrote:
> The kernel_noload image type indicates that no loading is to be done by
> U-Boot. This works well when the image is uncompressed.
>
> When the image is compressed, loading is of course required. The load
> address in the FIT is used for loading.
>
> However a FIT built from Linux v6.6 supports about 990 boards. Each has
> a different memory arrangement, so no one load address is suitable.
> Therefore the 'load' address in the kernel node is not useful.
>
> It would be better in this case to be able to omit the load address and
> have U-Boot choose something suitable. The kernel_addr_r environment
> variable seems to be a more reliable final address for the kernel. Use
> that as a backup when the load address is missing.
>
> Similarly, use the load address as the entry address when the latter is
> omitted.
>
> Update the FIT documentation accordingly.
>
> Note that mkimage still requires each image in a FIT to have a load
> address, at least for now.
>
> Another option would be to create a new Kconfig for this, or to use a
> region of memory known to be free, e.g. calculated from the DRAM banks.
> But in any case we should try to avoid conflicting with the
> kernel_addr_r variable. So the approach in this patch seems reasonable
> to me.
>
> It might perhaps be useful to introduce an 'entry-offset' property
> which allows the entry to be set as an offset from the load address,
> whether that is explicit or calculated.
>
> Signed-off-by: Simon Glass
OK, so I dug out what I was trying to determine before, and while I
might see if I can bisect down to when this regressed, it might be a
little hard given that my previously functional image is from 2013.
What should happen in the case of kernel_noload, and why the later patch
to fail on kernel_noload + compression, is that we don't move the kernel
contents of the FIT. We don't need the load address to be set because
we're using it where it is. What happened before in the case of the
ramdisk, and more importantly device tree, is what I why I want to
bisect down to when my image stopped working. But:
> @@ -177,10 +177,17 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int
> flag, int argc,
> images.os.end = fit_get_end(images.fit_hdr_os);
>
> if (fit_image_get_load(images.fit_hdr_os, images.fit_noffset_os,
> -)) {
> - puts("Can't get image load address!\n");
> - bootstage_error(BOOTSTAGE_ID_FIT_LOADADDR);
> - return 1;
> + )) {
> + ulong load;
> +
> + load = env_get_hex("kernel_addr_r", -1UL);
> + if (load == -1UL) {
> + puts("Can't get image load address!\n");
> + bootstage_error(BOOTSTAGE_ID_FIT_LOADADDR);
> + return 1;
> + }
> + printf("Using kernel load address %lx\n", load);
> + images.os.load = load;
The load address shouldn't be what kernel_addr_r is set to, it should be
where exactly the kernel portion is in memory, right now. We don't move
it, it XIPs. That's what used to happen, and how we could avoid having
to put in a load address. And so long as we then later ensure it's
properly aligned for the underlying image, it should be fine. _That_
however might be the harder case to deal with and then we need to
perhaps note-and-move (not warn, it'll be scary sounding for just a
memmove) as it's probably not the case that we've got the Image itself,
for aarch64, at a 2MiB aligned boundary. The FIT was probably loaded
there rather than 2MiB-sizeof(FIT header). And we need to not overwrite
other contents too.
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH v2 5/5] boot: Don't allow kernel_noload with compression
On Sat, Nov 11, 2023 at 08:49:57PM -0700, Simon Glass wrote: > It is not possible to execute the kernel in-place without loading it. > Detect this and show an error, to avoid a crash. > > Signed-off-by: Simon Glass Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 0/4] fix/add npcm845 serial and board error
On Tue, Nov 14, 2023 at 04:51:55PM +0800, Jim Liu wrote: > 1. Fix serial error and add bypass serial setting. > 2. Fix/Add dts node node. > 3. Add full function defconfig > > Jim Liu (4): > arm: dts: npcm845-evb: fix/add node and aliases > configs: arbel: Enable full functions > serial: npcm: support skip uart clock setting > board: nuvoton: update console environment variable > > arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 11 ++- > arch/arm/dts/nuvoton-npcm845-evb.dts | 29 ++-- > arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi | 2 +- > board/nuvoton/arbel_evb/Kconfig | 1 + > board/nuvoton/arbel_evb/arbel_evb.c | 7 ++ > board/nuvoton/common/Kconfig | 9 +++ > board/nuvoton/common/Makefile | 1 + > board/nuvoton/common/uart.c | 71 +++ > board/nuvoton/common/uart.h | 11 +++ > board/nuvoton/poleg_evb/Kconfig | 1 + > board/nuvoton/poleg_evb/poleg_evb.c | 8 +++ > configs/arbel_evb_defconfig | 16 - > drivers/serial/serial_npcm.c | 39 ++ > include/dt-bindings/phy/nuvoton,npcm-usbphy.h | 14 > 14 files changed, 194 insertions(+), 26 deletions(-) > create mode 100644 board/nuvoton/common/Kconfig > create mode 100644 board/nuvoton/common/Makefile > create mode 100644 board/nuvoton/common/uart.c > create mode 100644 board/nuvoton/common/uart.h > create mode 100644 include/dt-bindings/phy/nuvoton,npcm-usbphy.h I just want to make sure now that you've given this series a compile and boot test on some platform, yes? Thanks. -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 09/12] x86: Enable SSE in 64-bit mode
On Tue, Nov 14, 2023 at 09:49:08AM +0800, Bin Meng wrote:
> Hi Tom,
>
> On Tue, Nov 14, 2023 at 7:52 AM Tom Rini wrote:
> >
> > On Tue, Nov 14, 2023 at 07:46:36AM +0800, Bin Meng wrote:
> > > Hi Tom,
> > >
> > > On Tue, Nov 14, 2023 at 6:59 AM Tom Rini wrote:
> > > >
> > > > On Mon, Nov 13, 2023 at 03:28:13PM -0700, Simon Glass wrote:
> > > > > Hi Bin,
> > > > >
> > > > > On Mon, 13 Nov 2023 at 15:08, Bin Meng wrote:
> > > > > >
> > > > > > Hi Simon,
> > > > > >
> > > > > > On Mon, Nov 13, 2023 at 4:03 AM Simon Glass
> > > > > > wrote:
> > > > > > >
> > > > > > > This is needed to support Truetype fonts. In any case, the
> > > > > > > compiler
> > > > > > > expects SSE to be available in 64-bit mode. Provide an option to
> > > > > > > enable
> > > > > > > SSE so that hardware floating-point arithmetic works.
> > > > > > >
> > > > > > > Signed-off-by: Simon Glass
> > > > > > > Suggested-by: Bin Meng
> > > > > > > ---
> > > > > > >
> > > > > > > Changes in v4:
> > > > > > > - Use a Kconfig option
> > > > > > >
> > > > > > > arch/x86/Kconfig | 8
> > > > > > > arch/x86/config.mk| 4
> > > > > > > arch/x86/cpu/x86_64/cpu.c | 12
> > > > > > > drivers/video/Kconfig | 1 +
> > > > > > > 4 files changed, 25 insertions(+)
> > > > > > >
> > > > > > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> > > > > > > index 99e59d94c606..6b532d712ee8 100644
> > > > > > > --- a/arch/x86/Kconfig
> > > > > > > +++ b/arch/x86/Kconfig
> > > > > > > @@ -723,6 +723,14 @@ config ROM_TABLE_SIZE
> > > > > > > hex
> > > > > > > default 0x1
> > > > > > >
> > > > > > > +config X86_HARDFP
> > > > > > > + bool "Support hardware floating point"
> > > > > > > + help
> > > > > > > + U-Boot generally does not make use of floating point.
> > > > > > > Where this is
> > > > > > > + needed, it can be enabled using this option. This
> > > > > > > adjusts the
> > > > > > > + start-up code for 64-bit mode and changes the compiler
> > > > > > > options for
> > > > > > > + 64-bit to enable SSE.
> > > > > >
> > > > > > As discussed in another thread, this option should be made global to
> > > > > > all architectures and by default no.
> > > > > >
> > > > > > > +
> > > > > > > config HAVE_ITSS
> > > > > > > bool "Enable ITSS"
> > > > > > > help
> > > > > > > diff --git a/arch/x86/config.mk b/arch/x86/config.mk
> > > > > > > index 26ec1af2f0b0..2e3a7119e798 100644
> > > > > > > --- a/arch/x86/config.mk
> > > > > > > +++ b/arch/x86/config.mk
> > > > > > > @@ -27,9 +27,13 @@ ifeq ($(IS_32BIT),y)
> > > > > > > PLATFORM_CPPFLAGS += -march=i386 -m32
> > > > > > > else
> > > > > > > PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic)
> > > > > > > -fno-common -march=core2 -m64
> > > > > > > +
> > > > > > > +ifndef CONFIG_X86_HARDFP
> > > > > > > PLATFORM_CPPFLAGS += -mno-mmx -mno-sse
> > > > > > > endif
> > > > > > >
> > > > > > > +endif # IS_32BIT
> > > > > > > +
> > > > > > > PLATFORM_RELFLAGS += -fdata-sections -ffunction-sections
> > > > > > > -fvisibility=hidden
> > > > > > >
> > > > > > > KBUILD_LDFLAGS += -Bsymbolic -Bsymbolic-functions
> > > > > > > diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
> > > > > > > index 2647bff891f8..5ea746ecce4d 100644
> > > > > > > --- a/arch/x86/cpu/x86_64/cpu.c
> > > > > > > +++ b/arch/x86/cpu/x86_64/cpu.c
> > > > > > > @@ -10,6 +10,7 @@
> > > > > > > #include
> > > > > > > #include
> > > > > > > #include
> > > > > > > +#include
> > > > > > >
> > > > > > > DECLARE_GLOBAL_DATA_PTR;
> > > > > > >
> > > > > > > @@ -39,11 +40,22 @@ int x86_mp_init(void)
> > > > > > > return 0;
> > > > > > > }
> > > > > > >
> > > > > > > +/* enable SSE features for hardware floating point */
> > > > > > > +static void setup_sse_features(void)
> > > > > > > +{
> > > > > > > + asm ("mov %%cr4, %%rax\n" \
> > > > > > > + "or %0, %%rax\n" \
> > > > > > > + "mov %%rax, %%cr4\n" \
> > > > > > > + : : "i" (X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT) : "eax");
> > > > > > > +}
> > > > > > > +
> > > > > > > int x86_cpu_reinit_f(void)
> > > > > > > {
> > > > > > > /* set the vendor to Intel so that native_calibrate_tsc()
> > > > > > > works */
> > > > > > > gd->arch.x86_vendor = X86_VENDOR_INTEL;
> > > > > > > gd->arch.has_mtrr = true;
> > > > > > > + if (IS_ENABLED(CONFIG_X86_HARDFP))
> > > > > > > + setup_sse_features();
> > > > > > >
> > > > > > > return 0;
> > > > > > > }
> > > > > > > diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> > > > > > > index 6f319ba0d544..39c82521be16 100644
> > > > > > > --- a/drivers/video/Kconfig
> > > > > > > +++ b/drivers/video/Kconfig
> > > > > > > @@ -180,6 +180,7 @@ config CONSOLE_ROTATION
> > > > > > >
> > > > > > > config CONSOLE_TRUETYPE
> > > > > > > bool "Support a console that uses TrueType fonts"
> > > > > > > +
[PATCH 1/1] docs: Fix the docs build with Sphinx 6.0
From: Jonathan Corbet
Sphinx 6.0 removed the execfile_() function, which we use as part of the
configuration process. They *did* warn us... Just open-code the
functionality as is done in Sphinx itself.
Tested (using SPHINX_CONF, since this code is only executed with an
alternative config file) on various Sphinx versions from 2.5 through 6.0.
Reported-by: Martin Liška
Cc: sta...@vger.kernel.org
Signed-off-by: Jonathan Corbet
Rebased for U-Boot
Signed-off-by: Heinrich Schuchardt
---
doc/sphinx/load_config.py | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/doc/sphinx/load_config.py b/doc/sphinx/load_config.py
index eeb394b39e..8b416bfd75 100644
--- a/doc/sphinx/load_config.py
+++ b/doc/sphinx/load_config.py
@@ -3,7 +3,7 @@
import os
import sys
-from sphinx.util.pycompat import execfile_
+from sphinx.util.osutil import fs_encoding
#
--
def loadConfig(namespace):
@@ -48,7 +48,9 @@ def loadConfig(namespace):
sys.stdout.write("load additional sphinx-config: %s\n" %
config_file)
config = namespace.copy()
config['__file__'] = config_file
-execfile_(config_file, config)
+with open(config_file, 'rb') as f:
+code = compile(f.read(), fs_encoding, 'exec')
+exec(code, config)
del config['__file__']
namespace.update(config)
else:
--
2.40.1
Re: [PATCH] doc: avoid using deprecated sphinx function
On 14/11/2023 15:58, Heinrich Schuchardt wrote: > On 11/14/23 16:46, Tom Rini wrote: >> On Tue, Nov 14, 2023 at 03:18:02PM +, Caleb Connolly wrote: >> >>> The execfile_() function in sphinx has been removed after being >>> deprecated for some time. Follow what sphinx upstream does in [1] to >>> avoid using this function. This fixes "make htmldocs" on at least Arch >>> Linux but likely other distros too. > > Hello Caleb, > > Did you set up an environment as described in > https://docs.u-boot.org/en/latest/build/documentation.html? No, I used the version of the sphinx library included in my distribution... Certainly this would have been a good place to check >< > > Or did you try to build with other versions of packages than those > described in doc/sphinx/requirements.txt? > > It would well make sense to rework our requirements as the Sphinx 3.4.3 > we are using is getting dated. > > Best regards > > Heinrich > >>> >>> [1]: >>> https://github.com/sphinx-doc/sphinx/commit/9ced1e355ad6baecd4e755a598a54877dc0aad44 >>> >>> Signed-off-by: Caleb Connolly >>> --- >>> base-commit: 92b27528d777ce85362af45e7d2974a6c856219b >> >> I think we should cherry-pick: >> commit 0283189e8f3d0917e2ac399688df85211f48447b >> Author: Jonathan Corbet >> Date: Wed Jan 4 10:47:39 2023 -0700 >> >> docs: Fix the docs build with Sphinx 6.0 >> >> from the kernel, to keep the file in-sync. That's the only commit to >> load_config.py since I believe we synced last, but there might be other >> changes in Documentation/sphinx/ to grab as well. Ah, I wasn't aware that this was pulled from Linux, that makes a lot more sense then :) >> > -- // Caleb (they/them)
[PATCH 3/3] arm: mach-k3: Move sysfw-loader into R5 directory
SYSFW is only ever loaded by the R5 core, move the code into that
directory. While here also move the related Kconfig symbols.
Signed-off-by: Andrew Davis
---
arch/arm/mach-k3/Kconfig | 51 ++--
arch/arm/mach-k3/Makefile| 1 -
arch/arm/mach-k3/r5/Kconfig | 45 +
arch/arm/mach-k3/r5/Makefile | 4 ++
arch/arm/mach-k3/{ => r5}/sysfw-loader.c | 2 +-
5 files changed, 54 insertions(+), 49 deletions(-)
create mode 100644 arch/arm/mach-k3/r5/Kconfig
rename arch/arm/mach-k3/{ => r5}/sysfw-loader.c (99%)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 4d19cf3e353..ced7d3bcba6 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -109,53 +109,6 @@ config K3_EARLY_CONS_IDX
Use this option to set the index of the serial device to be used
for the early console during SPL execution.
-config K3_LOAD_SYSFW
- bool
- depends on CPU_V7R
-
-config K3_SYSFW_IMAGE_NAME
- string "File name of SYSFW firmware and configuration blob"
- depends on K3_LOAD_SYSFW
- default "sysfw.itb"
- help
- Filename of the combined System Firmware and configuration image tree
- blob to be loaded when booting from a filesystem.
-
-config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
- hex "MMC sector to load SYSFW firmware and configuration blob from"
- depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
- default 0x3600
- help
- Address on the MMC to load the combined System Firmware and
- configuration image tree blob from, when the MMC is being used
- in raw mode. Units: MMC sectors (1 sector = 512 bytes).
-
-config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
- hex "MMC partition to load SYSFW firmware and configuration blob from"
- depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- default 2
- help
- Partition on the MMC to the combined System Firmware and configuration
- image tree blob from, when the MMC is being used in raw mode.
-
-config K3_SYSFW_IMAGE_SIZE_MAX
- int "Amount of memory dynamically allocated for loading SYSFW blob"
- depends on K3_LOAD_SYSFW
- default 28
- help
- Amount of memory (in bytes) reserved through dynamic allocation at
- runtime for loading the combined System Firmware and configuration
image
- tree blob. Keep it as tight as possible, as this directly affects the
- overall SPL memory footprint.
-
-config K3_SYSFW_IMAGE_SPI_OFFS
- hex "SPI offset of SYSFW firmware and configuration blob"
- depends on K3_LOAD_SYSFW
- default 0x6C
- help
- Offset of the combined System Firmware and configuration image tree
- blob to be loaded when booting from a SPI flash memory.
-
config SYS_K3_SPL_ATF
bool "Start Cortex-A from SPL"
depends on CPU_V7R
@@ -187,6 +140,10 @@ config K3_X509_SWRV
help
SWRV for X509 certificate used for boot images
+if CPU_V7R
+source "arch/arm/mach-k3/r5/Kconfig"
+endif
+
source "board/ti/am65x/Kconfig"
source "board/ti/am64x/Kconfig"
source "board/ti/am62x/Kconfig"
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 215c755c5dc..42161376469 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -20,6 +20,5 @@ obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
-obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
endif
obj-y += common.o security.o
diff --git a/arch/arm/mach-k3/r5/Kconfig b/arch/arm/mach-k3/r5/Kconfig
new file mode 100644
index 000..ae79f8ff6cd
--- /dev/null
+++ b/arch/arm/mach-k3/r5/Kconfig
@@ -0,0 +1,45 @@
+config K3_LOAD_SYSFW
+ bool
+
+config K3_SYSFW_IMAGE_NAME
+ string "File name of SYSFW firmware and configuration blob"
+ depends on K3_LOAD_SYSFW
+ default "sysfw.itb"
+ help
+ Filename of the combined System Firmware and configuration image tree
+ blob to be loaded when booting from a filesystem.
+
+config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
+ hex "MMC sector to load SYSFW firmware and configuration blob from"
+ depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ default 0x3600
+ help
+ Address on the MMC to load the combined System Firmware and
+ configuration image tree blob from, when the MMC is being used
+ in raw mode. Units: MMC sectors (1 sector = 512 bytes).
+
+config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
+ hex "MMC partition to load SYSFW firmware and configuration blob from"
+ depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ default 2
+ help
+ Partition on the MMC to the combined System
[PATCH 1/3] arm: mach-k3: Move R5 specific code into new r5/ directory
This makes it clear these are only to be used by the R5 builds of SPL.
And this will be used to later more cleanly split the two builds.
Signed-off-by: Andrew Davis
---
arch/arm/mach-k3/Makefile | 6 +-
arch/arm/mach-k3/r5/Makefile | 13 +
arch/arm/mach-k3/{ => r5}/am62ax/Makefile | 0
arch/arm/mach-k3/{ => r5}/am62ax/am62a_qos_data.c | 0
arch/arm/mach-k3/{ => r5}/am62ax/clk-data.c | 0
arch/arm/mach-k3/{ => r5}/am62ax/dev-data.c | 0
arch/arm/mach-k3/{ => r5}/am62x/Makefile | 0
arch/arm/mach-k3/{ => r5}/am62x/clk-data.c| 0
arch/arm/mach-k3/{ => r5}/am62x/dev-data.c| 0
arch/arm/mach-k3/{ => r5}/j7200/Makefile | 0
arch/arm/mach-k3/{ => r5}/j7200/clk-data.c| 0
arch/arm/mach-k3/{ => r5}/j7200/dev-data.c| 0
arch/arm/mach-k3/{ => r5}/j721e/Makefile | 0
arch/arm/mach-k3/{ => r5}/j721e/clk-data.c| 0
arch/arm/mach-k3/{ => r5}/j721e/dev-data.c| 0
arch/arm/mach-k3/{ => r5}/j721s2/Makefile | 0
arch/arm/mach-k3/{ => r5}/j721s2/clk-data.c | 0
arch/arm/mach-k3/{ => r5}/j721s2/dev-data.c | 0
arch/arm/mach-k3/{ => r5}/lowlevel_init.S | 0
arch/arm/mach-k3/{ => r5}/r5_mpu.c| 2 +-
20 files changed, 15 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/mach-k3/r5/Makefile
rename arch/arm/mach-k3/{ => r5}/am62ax/Makefile (100%)
rename arch/arm/mach-k3/{ => r5}/am62ax/am62a_qos_data.c (100%)
rename arch/arm/mach-k3/{ => r5}/am62ax/clk-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/am62ax/dev-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/am62x/Makefile (100%)
rename arch/arm/mach-k3/{ => r5}/am62x/clk-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/am62x/dev-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j7200/Makefile (100%)
rename arch/arm/mach-k3/{ => r5}/j7200/clk-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j7200/dev-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j721e/Makefile (100%)
rename arch/arm/mach-k3/{ => r5}/j721e/clk-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j721e/dev-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j721s2/Makefile (100%)
rename arch/arm/mach-k3/{ => r5}/j721s2/clk-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/j721s2/dev-data.c (100%)
rename arch/arm/mach-k3/{ => r5}/lowlevel_init.S (100%)
rename arch/arm/mach-k3/{ => r5}/r5_mpu.c (98%)
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index c7ca0fdce56..215c755c5dc 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -3,12 +3,8 @@
# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla
-obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/
-obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
-obj-$(CONFIG_SOC_K3_AM625) += am62x/
-obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_CPU_V7R) += r5/
obj-$(CONFIG_ARM64) += arm64-mmu.o
-obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_ARM64) += cache.o
obj-$(CONFIG_OF_LIBFDT) += common_fdt.o
ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy)
diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
new file mode 100644
index 000..8a6af73a44e
--- /dev/null
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis
+
+obj-$(CONFIG_SOC_K3_J721E) += j721e/
+obj-$(CONFIG_SOC_K3_J721E) += j7200/
+obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_AM625) += am62x/
+obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+
+obj-y += lowlevel_init.o
+obj-y += r5_mpu.o
diff --git a/arch/arm/mach-k3/am62ax/Makefile
b/arch/arm/mach-k3/r5/am62ax/Makefile
similarity index 100%
rename from arch/arm/mach-k3/am62ax/Makefile
rename to arch/arm/mach-k3/r5/am62ax/Makefile
diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c
b/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c
similarity index 100%
rename from arch/arm/mach-k3/am62ax/am62a_qos_data.c
rename to arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c
diff --git a/arch/arm/mach-k3/am62ax/clk-data.c
b/arch/arm/mach-k3/r5/am62ax/clk-data.c
similarity index 100%
rename from arch/arm/mach-k3/am62ax/clk-data.c
rename to arch/arm/mach-k3/r5/am62ax/clk-data.c
diff --git a/arch/arm/mach-k3/am62ax/dev-data.c
b/arch/arm/mach-k3/r5/am62ax/dev-data.c
similarity index 100%
rename from arch/arm/mach-k3/am62ax/dev-data.c
rename to arch/arm/mach-k3/r5/am62ax/dev-data.c
diff --git a/arch/arm/mach-k3/am62x/Makefile
b/arch/arm/mach-k3/r5/am62x/Makefile
similarity index 100%
rename from arch/arm/mach-k3/am62x/Makefile
rename to arch/arm/mach-k3/r5/am62x/Makefile
diff --git a/arch/arm/mach-k3/am62x/clk-data.c
b/arch/arm/mach-k3/r5/am62x/clk-data.c
similarity index 100%
rename from arch/arm/mach-k3/am62x/clk-data.c
rename to arch/arm/mach-k3/r5/am62x/clk-data.c
diff --git
[PATCH 2/3] arm: mach-k3: Remove incorrect checks for SPL build
The kconfig option SPL means this build supports SPL but not that this build is SPL, nor that this build is the SPL running on R5. For options that are for R5 SPL use CPU_V7R. Signed-off-by: Andrew Davis --- arch/arm/mach-k3/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 9168bf842dc..4d19cf3e353 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -111,7 +111,7 @@ config K3_EARLY_CONS_IDX config K3_LOAD_SYSFW bool - depends on SPL + depends on CPU_V7R config K3_SYSFW_IMAGE_NAME string "File name of SYSFW firmware and configuration blob" @@ -158,7 +158,7 @@ config K3_SYSFW_IMAGE_SPI_OFFS config SYS_K3_SPL_ATF bool "Start Cortex-A from SPL" - depends on SPL && CPU_V7R + depends on CPU_V7R help Enabling this will try to start Cortex-A (typically with ATF) after SPL from R5. @@ -172,7 +172,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM -- 2.39.2
Re: [PATCH] doc: avoid using deprecated sphinx function
On 11/14/23 16:46, Tom Rini wrote: On Tue, Nov 14, 2023 at 03:18:02PM +, Caleb Connolly wrote: The execfile_() function in sphinx has been removed after being deprecated for some time. Follow what sphinx upstream does in [1] to avoid using this function. This fixes "make htmldocs" on at least Arch Linux but likely other distros too. Hello Caleb, Did you set up an environment as described in https://docs.u-boot.org/en/latest/build/documentation.html? Or did you try to build with other versions of packages than those described in doc/sphinx/requirements.txt? It would well make sense to rework our requirements as the Sphinx 3.4.3 we are using is getting dated. Best regards Heinrich [1]: https://github.com/sphinx-doc/sphinx/commit/9ced1e355ad6baecd4e755a598a54877dc0aad44 Signed-off-by: Caleb Connolly --- base-commit: 92b27528d777ce85362af45e7d2974a6c856219b I think we should cherry-pick: commit 0283189e8f3d0917e2ac399688df85211f48447b Author: Jonathan Corbet Date: Wed Jan 4 10:47:39 2023 -0700 docs: Fix the docs build with Sphinx 6.0 from the kernel, to keep the file in-sync. That's the only commit to load_config.py since I believe we synced last, but there might be other changes in Documentation/sphinx/ to grab as well.
Re: [PATCH] doc: avoid using deprecated sphinx function
On Tue, Nov 14, 2023 at 03:18:02PM +, Caleb Connolly wrote: > The execfile_() function in sphinx has been removed after being > deprecated for some time. Follow what sphinx upstream does in [1] to > avoid using this function. This fixes "make htmldocs" on at least Arch > Linux but likely other distros too. > > [1]: > https://github.com/sphinx-doc/sphinx/commit/9ced1e355ad6baecd4e755a598a54877dc0aad44 > > Signed-off-by: Caleb Connolly > --- > base-commit: 92b27528d777ce85362af45e7d2974a6c856219b I think we should cherry-pick: commit 0283189e8f3d0917e2ac399688df85211f48447b Author: Jonathan Corbet Date: Wed Jan 4 10:47:39 2023 -0700 docs: Fix the docs build with Sphinx 6.0 from the kernel, to keep the file in-sync. That's the only commit to load_config.py since I believe we synced last, but there might be other changes in Documentation/sphinx/ to grab as well. -- Tom signature.asc Description: PGP signature
[PATCH] doc: avoid using deprecated sphinx function
The execfile_() function in sphinx has been removed after being
deprecated for some time. Follow what sphinx upstream does in [1] to
avoid using this function. This fixes "make htmldocs" on at least Arch
Linux but likely other distros too.
[1]:
https://github.com/sphinx-doc/sphinx/commit/9ced1e355ad6baecd4e755a598a54877dc0aad44
Signed-off-by: Caleb Connolly
---
base-commit: 92b27528d777ce85362af45e7d2974a6c856219b
// Caleb (they/them)
---
doc/sphinx/load_config.py | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/doc/sphinx/load_config.py b/doc/sphinx/load_config.py
index eeb394b39e2c..977b27084780 100644
--- a/doc/sphinx/load_config.py
+++ b/doc/sphinx/load_config.py
@@ -3,7 +3,6 @@
import os
import sys
-from sphinx.util.pycompat import execfile_
#
--
def loadConfig(namespace):
@@ -48,7 +47,7 @@ def loadConfig(namespace):
sys.stdout.write("load additional sphinx-config: %s\n" %
config_file)
config = namespace.copy()
config['__file__'] = config_file
-execfile_(config_file, config)
+exec(config_file.read_text(), config)
del config['__file__']
namespace.update(config)
else:
Re: [PATCH 1/2] serial: msm-geni: don't rely on parent misc device
> diff --git a/drivers/serial/serial_msm_geni.c
> b/drivers/serial/serial_msm_geni.c
> index 78fd9389c036..3e2e15b6cefe 100644
> --- a/drivers/serial/serial_msm_geni.c
> +++ b/drivers/serial/serial_msm_geni.c
[...]
> @@ -499,16 +499,22 @@ static void geni_set_oversampling(struct udevice *dev)
>* It could happen that GENI SE IP is missing in the board's device
>* tree or GENI UART node is a direct child of SoC device tree node.
>*/
> - if (device_get_uclass_id(parent_dev) != UCLASS_MISC)
> - return;
> + if (!ofnode_device_is_compatible(parent_node, "qcom,geni-se-qup")) {
> + pr_err("%s: UART node must be a child of geniqup node\n",
> +__func__);
> + return -ENODEV;
> + }
>
> - ret = misc_read(parent_dev, QUP_HW_VER_REG,
> - _se_version, sizeof(geni_se_version));
> - if (ret != sizeof(geni_se_version))
> - return;
> + /* Read the HW_VER register relative to the parents address space */
> + addr = ofnode_get_addr(parent_node);
> + geni_se_version = readl(addr + QUP_HW_VER_REG);
> +
> + printf("geni_se_version: %x\n", geni_se_version);
Drop this debugging printf
>
> if (geni_se_version >= QUP_SE_VERSION_2_5)
> priv->oversampling /= 2;
> +
> + return 0;
> }
>
> static inline void geni_serial_init(struct udevice *dev)
> @@ -553,8 +559,11 @@ static inline void geni_serial_init(struct udevice *dev)
> static int msm_serial_probe(struct udevice *dev)
> {
> struct msm_serial_data *priv = dev_get_priv(dev);
> + int ret;
>
> - geni_set_oversampling(dev);
> + ret = geni_set_oversampling(dev);
> + if (ret < 0)
> + return ret;
>
> /* No need to reinitialize the UART after relocation */
> if (gd->flags & GD_FLG_RELOC)
>
--
// Caleb (they/them)
Re: [PATCH 3/4] arm: dts: k3-am625-beagleplay-u-boot: drop duplicate bootph-nodes
On 09:03-20231114, Dhruva Gole wrote: [...] > > #ifdef CONFIG_TARGET_AM625_A53_EVM > > > > #define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb" > > You didn't talk about this in the commit message? There is nothing changing in this patch here. -- Regards, Nishanth Menonh Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Re: [PATCH 1/4] rockchip: rk3588: Fix boot from SPI flash
Hi Jonas,
On 11/12/23 11:26, Jonas Karlman wrote:
The commit fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI
NOR flash") added a new BROM_BOOTSOURCE_SPINOR_RK3588 with value 6.
At the time the reason for this new bootsource id value 6 was unknown.
We now know that the BootRom on RK3588 use different bootsource id
values depending on the iomux used by the flash spi controller, and not
by the type of spi nor or spi nand flash used.
Add the following defines and use them for RK3588 boot_devices.
- BROM_BOOTSOURCE_FSPI_M0 = 3
- BROM_BOOTSOURCE_FSPI_M1 = 4
- BROM_BOOTSOURCE_FSPI_M2 = 6
Fixes: fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash")
Signed-off-by: Jonas Karlman
---
arch/arm/include/asm/arch-rockchip/bootrom.h | 4 +++-
arch/arm/mach-rockchip/rk3588/rk3588.c | 5 +++--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h
b/arch/arm/include/asm/arch-rockchip/bootrom.h
index 7dab18fbc3fb..f78337397d63 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -47,8 +47,10 @@ enum {
BROM_BOOTSOURCE_EMMC = 2,
BROM_BOOTSOURCE_SPINOR = 3,
BROM_BOOTSOURCE_SPINAND = 4,
+ BROM_BOOTSOURCE_FSPI_M0 = 3,
+ BROM_BOOTSOURCE_FSPI_M1 = 4,
I'm a bit wary of two pairs of enums sharing the same value, especially
when we want to use them as offset in a static definition of an array.
Should we #ifdef it (meh) for RK3588?
Should we add a suffix like before for identifying RK3588-specific options?
At the very least explicit that those are RK3588-specific in a comment
for both conflicts (the ones that apply to everything except RK3588 to
say to use only for !RK3588, and the ones that apply to RK3588 only)?
Cheers,
Quentin
[PATCH v3 5/5] pmic: qcom: dont use dev_read_addr to get USID
Linux DTs stuff a value indicating if the USID is a USID or a GSID in the
reg property, the Linux SPMI driver then reads the two address cells
separately. U-boot's dev_read_addr() doesn't know how to handle this, so
use ofnode_read_u32_index() to get just the USID.
The Qcom pmic driver doesn't have support for GSID handling, so just
ignore the second value for now.
Signed-off-by: Caleb Connolly
---
drivers/power/pmic/pmic_qcom.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/power/pmic/pmic_qcom.c b/drivers/power/pmic/pmic_qcom.c
index ad8daf43f06f..f2ac6494811d 100644
--- a/drivers/power/pmic/pmic_qcom.c
+++ b/drivers/power/pmic/pmic_qcom.c
@@ -66,12 +66,19 @@ static const struct udevice_id pmic_qcom_ids[] = {
static int pmic_qcom_probe(struct udevice *dev)
{
struct pmic_qcom_priv *priv = dev_get_priv(dev);
+ int ret;
- priv->usid = dev_read_addr(dev);
-
- if (priv->usid == FDT_ADDR_T_NONE)
+ /*
+* dev_read_addr() can't be used here because the reg property actually
+* contains two discrete values, not a single 64-bit address.
+* The address is the first value.
+*/
+ ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, >usid);
+ if (ret < 0)
return -EINVAL;
+ debug("usid: %d\n", priv->usid);
+
return 0;
}
--
2.42.1
[PATCH v3 4/5] spmi: msm: fix register range names
The core and chnl register ranges were swapped on SDM845. Fix it, and
fetch the register ranges by name instead of by index.
Drop the cosmetic "version" variable and clean up the debug logging.
Signed-off-by: Caleb Connolly
---
arch/arm/dts/sdm845.dtsi | 2 +-
drivers/spmi/spmi-msm.c | 46 ++
2 files changed, 19 insertions(+), 29 deletions(-)
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index a26e9f411ee0..96c9749a52c0 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -63,7 +63,7 @@
reg = <0xc44 0x1100>,
<0xc60 0x200>,
<0xe60 0x10>;
- reg-names = "cnfg", "core", "obsrvr";
+ reg-names = "core", "chnls", "obsrvr";
#address-cells = <0x1>;
#size-cells = <0x1>;
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
index 27a035c0a595..f8834e60c266 100644
--- a/drivers/spmi/spmi-msm.c
+++ b/drivers/spmi/spmi-msm.c
@@ -70,7 +70,7 @@ enum pmic_arb_channel {
struct msm_spmi_priv {
phys_addr_t arb_chnl; /* ARB channel mapping base */
- phys_addr_t spmi_core; /* SPMI core */
+ phys_addr_t spmi_chnls; /* SPMI core */
phys_addr_t spmi_obs; /* SPMI observer */
/* SPMI channel map */
uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
@@ -95,10 +95,10 @@ static int msm_spmi_write(struct udevice *dev, int usid,
int pid, int off,
/* Disable IRQ mode for the current channel*/
writel(0x0,
- priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
+ priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
/* Write single byte */
- writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
+ writel(val, priv->spmi_chnls + SPMI_CH_OFFSET(channel) +
SPMI_REG_WDATA);
/* Prepare write command */
reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
@@ -113,12 +113,12 @@ static int msm_spmi_write(struct udevice *dev, int usid,
int pid, int off,
ch_offset = SPMI_CH_OFFSET(channel);
/* Send write command */
- writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+ writel(reg, priv->spmi_chnls + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
/* Wait till CMD DONE status */
reg = 0;
while (!reg) {
- reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
+ reg = readl(priv->spmi_chnls + SPMI_CH_OFFSET(channel) +
SPMI_REG_STATUS);
}
@@ -186,47 +186,37 @@ static struct dm_spmi_ops msm_spmi_ops = {
static int msm_spmi_probe(struct udevice *dev)
{
struct msm_spmi_priv *priv = dev_get_priv(dev);
- phys_addr_t config_addr;
+ phys_addr_t core_addr;
u32 hw_ver;
- u32 version;
int i;
- int err;
- config_addr = dev_read_addr_index(dev, 0);
- priv->spmi_core = dev_read_addr_index(dev, 1);
- priv->spmi_obs = dev_read_addr_index(dev, 2);
+ core_addr = dev_read_addr_name(dev, "core");
+ priv->spmi_chnls = dev_read_addr_name(dev, "chnls");
+ priv->spmi_obs = dev_read_addr_name(dev, "obsrvr");
- hw_ver = readl(config_addr + PMIC_ARB_VERSION);
+ hw_ver = readl(core_addr + PMIC_ARB_VERSION);
if (hw_ver < PMIC_ARB_VERSION_V3_MIN) {
priv->arb_ver = V2;
- version = 2;
- priv->arb_chnl = config_addr + APID_MAP_OFFSET_V1_V2_V3;
+ priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3;
} else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) {
priv->arb_ver = V3;
- version = 3;
- priv->arb_chnl = config_addr + APID_MAP_OFFSET_V1_V2_V3;
+ priv->arb_chnl = core_addr + APID_MAP_OFFSET_V1_V2_V3;
} else {
priv->arb_ver = V5;
- version = 5;
- priv->arb_chnl = config_addr + APID_MAP_OFFSET_V5;
-
- if (err) {
- dev_err(dev, "could not read APID->PPID mapping table,
rc= %d\n", err);
- return -1;
- }
+ priv->arb_chnl = core_addr + APID_MAP_OFFSET_V5;
}
- dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", version, hw_ver);
+ dev_dbg(dev, "PMIC Arb Version-%d (%#x)\n", hw_ver >> 28, hw_ver);
if (priv->arb_chnl == FDT_ADDR_T_NONE ||
- priv->spmi_core == FDT_ADDR_T_NONE ||
+ priv->spmi_chnls == FDT_ADDR_T_NONE ||
priv->spmi_obs == FDT_ADDR_T_NONE)
return -EINVAL;
- dev_dbg(dev, "priv->arb_chnl address (%llu)\n", priv->arb_chnl);
- dev_dbg(dev, "priv->spmi_core address (%llu)\n", priv->spmi_core);
- dev_dbg(dev,
[PATCH v3 3/5] gpio: qcom_pmic: fix support for upstream DT
Linux devicetrees use the "gpio-ranges" property, add support for
parsing it instead of "gpio-count" so that upstream DTs can be used with
U-Boot.
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard410c.dts | 3 +--
arch/arm/dts/dragonboard820c.dts | 3 +--
arch/arm/dts/qcs404-evb.dts | 2 +-
arch/arm/dts/sdm845.dtsi | 3 +--
drivers/gpio/qcom_pmic_gpio.c| 38 ++
5 files changed, 34 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index c41fee977813..6a4e3ccf17b1 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -170,9 +170,8 @@
compatible = "qcom,pm8916-gpio";
reg = <0xc000 0x400>;
gpio-controller;
- gpio-count = <4>;
+ gpio-ranges = <_gpios 0 0 4>;
#gpio-cells = <2>;
- gpio-bank-name="pmic";
};
};
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index 0d9c9f7a4922..146a0af8aafe 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -132,9 +132,8 @@
compatible = "qcom,pm8994-gpio";
reg = <0xc000 0x400>;
gpio-controller;
- gpio-count = <24>;
+ gpio-ranges = <_gpios 0 0 22>;
#gpio-cells = <2>;
- gpio-bank-name="pm8994.";
};
};
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts
index 84224a8a3d39..3bb580ba4e17 100644
--- a/arch/arm/dts/qcs404-evb.dts
+++ b/arch/arm/dts/qcs404-evb.dts
@@ -378,7 +378,7 @@
compatible = "qcom,pms405-gpio";
reg = <0xc000 0x400>;
gpio-controller;
- gpio-count = <12>;
+ gpio-ranges = <_gpios 0 0 12>;
#gpio-cells = <2>;
gpio-bank-name="pmic";
};
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index cd5d890e9a45..a26e9f411ee0 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -103,9 +103,8 @@
compatible = "qcom,pm8998-gpio";
reg = <0xc000 0x1a00>;
gpio-controller;
- gpio-count = <21>;
+ gpio-ranges = <_gpios 0 0 26>;
#gpio-cells = <2>;
- gpio-bank-name = "pm8998.";
};
};
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 7b83c67fa464..f2424766e5cc 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -245,23 +245,45 @@ static int qcom_gpio_probe(struct udevice *dev)
return 0;
}
+/*
+ * Parse basic GPIO count specified via the gpio-ranges property
+ * as specified in Linux devicetrees
+ * Returns < 0 on error, otherwise gpio count
+ */
+static int qcom_gpio_of_parse_ranges(struct udevice *dev)
+{
+ int ret;
+ struct ofnode_phandle_args args;
+
+ ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges",
+NULL, 3, 0, );
+ if (ret)
+ return log_msg_ret("gpio-ranges", ret);
+
+ return args.args[2];
+}
+
static int qcom_gpio_of_to_plat(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ int ret;
- uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 0);
- uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
- if (uc_priv->bank_name == NULL)
- uc_priv->bank_name = "qcom_pmic";
+ ret = qcom_gpio_of_parse_ranges(dev);
+ if (ret > 0)
+ uc_priv->gpio_count = ret;
+ else
+ return ret;
+
+ uc_priv->bank_name = (const char *)dev->driver_data;
return 0;
}
static const struct udevice_id qcom_gpio_ids[] = {
- { .compatible = "qcom,pm8916-gpio" },
- { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
- { .compatible = "qcom,pm8998-gpio" },
- { .compatible = "qcom,pms405-gpio" },
+
[PATCH v3 2/5] gpio: qcom_pmic: rework pwrkey driver into a button driver
The power and resin keys were implemented as GPIOs here, but their only
use would be as buttons. Avoid the additional layer of introspection and
rework this driver into a button driver.
While we're here, replace the "qcom,pm8998-pwrkey" compatible with
"qcom,pm8941-pwrkey" to match upstream (Linux).
The dragonboard410c and 820c boards are adjusted to benefit from this
change too, simplify their custom board init code.
Signed-off-by: Caleb Connolly
---
MAINTAINERS | 1 +
arch/arm/dts/dragonboard410c-uboot.dtsi | 11 --
arch/arm/dts/dragonboard410c.dts | 22 ++-
arch/arm/dts/dragonboard820c-uboot.dtsi | 12 --
arch/arm/dts/dragonboard820c.dts | 23 +++-
arch/arm/dts/dragonboard845c-uboot.dtsi | 11 --
arch/arm/dts/dragonboard845c.dts | 4 +
arch/arm/dts/sdm845.dtsi | 23 +++-
arch/arm/dts/starqltechn-uboot.dtsi | 10 --
arch/arm/dts/starqltechn.dts | 20 +--
arch/arm/mach-snapdragon/Kconfig | 3 +
arch/arm/mach-snapdragon/init_sdm845.c | 45 ++-
board/qualcomm/dragonboard410c/dragonboard410c.c | 31 ++---
board/qualcomm/dragonboard820c/dragonboard820c.c | 29 ++--
drivers/button/Kconfig | 9 ++
drivers/button/Makefile | 1 +
drivers/button/button-qcom-pmic.c| 165 +++
drivers/gpio/Kconfig | 3 +-
drivers/gpio/qcom_pmic_gpio.c| 104 --
19 files changed, 269 insertions(+), 258 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index f6d63c8ab563..8cd102eaa070 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -572,6 +572,7 @@ M: Neil Armstrong
R: Sumit Garg
S: Maintained
F: arch/arm/mach-snapdragon/
+F: drivers/button/button-qcom-pmic.c
F: drivers/clk/qcom/
F: drivers/gpio/msm_gpio.c
F: drivers/mmc/msm_sdhci.c
diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi
b/arch/arm/dts/dragonboard410c-uboot.dtsi
index 3b0bd0ed0a1b..cec64bf80f99 100644
--- a/arch/arm/dts/dragonboard410c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard410c-uboot.dtsi
@@ -42,14 +42,3 @@
gpios = <_gpios 3 0>;
};
};
-
-
-_pon {
- key_vol_down {
- gpios = <_pon 1 0>;
- };
-
- key_power {
- gpios = <_pon 0 0>;
- };
-};
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 9230dd3fd96c..c41fee977813 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -147,11 +147,23 @@
#address-cells = <0x1>;
#size-cells = <0x1>;
- pm8916_pon: pm8916_pon@800 {
- compatible = "qcom,pm8916-pwrkey";
- reg = <0x800 0x96>;
- #gpio-cells = <2>;
- gpio-controller;
+ pon@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x800 0x100>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pwrkey {
+ compatible =
"qcom,pm8941-pwrkey";
+ debounce = <15625>;
+ bias-pull-up;
+ };
+
+ pm8916_resin: resin {
+ compatible =
"qcom,pm8941-resin";
+ debounce = <15625>;
+ bias-pull-up;
+ };
};
pm8916_gpios: pm8916_gpios@c000 {
diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi
b/arch/arm/dts/dragonboard820c-uboot.dtsi
index 457728a43ecb..d93c7c1fbdee 100644
--- a/arch/arm/dts/dragonboard820c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard820c-uboot.dtsi
@@ -30,15 +30,3 @@
};
};
};
-
-_pon {
- key_vol_down {
- gpios = <_pon 1 0>;
- label = "key_vol_down";
- };
-
- key_power {
- gpios = <_pon 0 0>;
- label = "key_power";
- };
-};
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index ad201d48749c..0d9c9f7a4922 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -109,12 +109,23 @@
#address-cells = <0x1>;
[PATCH v3 1/5] gpio: qcom_pmic: fix silent dev_read_addr downcast
priv->pid is uint32_t, but dev_read_addr() returns a uint64_t on arm64,
with the upper bits being used for error codes. Do error checking before
downcasting to u32 to prevent errors being silently ignored.
Signed-off-by: Caleb Connolly
---
drivers/gpio/qcom_pmic_gpio.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 65feb453ebc3..e5841f502953 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -221,11 +221,14 @@ static int qcom_gpio_probe(struct udevice *dev)
{
struct qcom_gpio_bank *priv = dev_get_priv(dev);
int reg;
+ u64 pid;
- priv->pid = dev_read_addr(dev);
- if (priv->pid == FDT_ADDR_T_NONE)
+ pid = dev_read_addr(dev);
+ if (pid == FDT_ADDR_T_NONE)
return log_msg_ret("bad address", -EINVAL);
+ priv->pid = pid;
+
/* Do a sanity check */
reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
if (reg != REG_TYPE_VAL)
@@ -328,11 +331,14 @@ static int qcom_pwrkey_probe(struct udevice *dev)
{
struct qcom_gpio_bank *priv = dev_get_priv(dev);
int reg;
+ u64 pid;
- priv->pid = dev_read_addr(dev);
- if (priv->pid == FDT_ADDR_T_NONE)
+ pid = dev_read_addr(dev);
+ if (pid == FDT_ADDR_T_NONE)
return log_msg_ret("bad address", -EINVAL);
+ priv->pid = pid;
+
/* Do a sanity check */
reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
if (reg != 0x1)
--
2.42.1
[PATCH v3 0/5] Qualcomm PMIC fixes
This series addresses some long-standing issues with the SPMI arb
driver, the PMIC, and the PMIC GPIO. It fixes compatibility with
upstream Linux devicetrees, and simplifies pwrkey/resin support by
rewriting the pon driver to be a button driver rather than a GPIO
driver.
Existing users are adjusted to use the new button driver in their
oard init code.
This series is based on the pinctrl [1] and clock [2] cleanup series.
There may be some DTS conflicts applying it standalone.
[1]:
https://lore.kernel.org/u-boot/20231106-b4-qcom-pinctrl-v2-0-406e8d868...@linaro.org/
[2]:
https://lore.kernel.org/u-boot/20231103-b4-qcom-clk-v3-0-8d2d460ec...@linaro.org/
---
Changes in v3:
* Remove now-unneeded header includes in dragonboard{410,820}c-uboot.dtsi
* Drop non-standard DTS support from PMIC GPIO driver
* Also remove old gpio-keys nodes from starqltechn-uboot.dtsi
* Link to v2:
https://lore.kernel.org/r/20231108-b4-qcom-dt-compat-v2-0-713233c72...@linaro.org
Changes in v2:
* Avoid using non-standard "label" and "linux,code" properties for
buttons
* Add missing sdm845 DTS parts
* Put button driver in drivers/button
* Link to v1:
https://lore.kernel.org/r/20231106-b4-qcom-dt-compat-v1-0-0ccbb7841...@linaro.org
---
Caleb Connolly (5):
gpio: qcom_pmic: fix silent dev_read_addr downcast
gpio: qcom_pmic: rework pwrkey driver into a button driver
gpio: qcom_pmic: fix support for upstream DT
spmi: msm: fix register range names
pmic: qcom: dont use dev_read_addr to get USID
MAINTAINERS | 1 +
arch/arm/dts/dragonboard410c-uboot.dtsi | 11 --
arch/arm/dts/dragonboard410c.dts | 25 +++-
arch/arm/dts/dragonboard820c-uboot.dtsi | 12 --
arch/arm/dts/dragonboard820c.dts | 26 ++--
arch/arm/dts/dragonboard845c-uboot.dtsi | 11 --
arch/arm/dts/dragonboard845c.dts | 4 +
arch/arm/dts/qcs404-evb.dts | 2 +-
arch/arm/dts/sdm845.dtsi | 28 ++--
arch/arm/dts/starqltechn-uboot.dtsi | 10 --
arch/arm/dts/starqltechn.dts | 20 +--
arch/arm/mach-snapdragon/Kconfig | 3 +
arch/arm/mach-snapdragon/init_sdm845.c | 45 ++-
board/qualcomm/dragonboard410c/dragonboard410c.c | 31 ++---
board/qualcomm/dragonboard820c/dragonboard820c.c | 29 ++--
drivers/button/Kconfig | 9 ++
drivers/button/Makefile | 1 +
drivers/button/button-qcom-pmic.c| 165 +++
drivers/gpio/Kconfig | 3 +-
drivers/gpio/qcom_pmic_gpio.c| 146 +---
drivers/power/pmic/pmic_qcom.c | 13 +-
drivers/spmi/spmi-msm.c | 46 +++
22 files changed, 337 insertions(+), 304 deletions(-)
---
base-commit: d1efa48e205960b15656eb0c13227110895f1cc9
// Caleb (they/them)
Re: [PATCH 1/2] dt-bindings: misc: Move esm-k3.txt to ti,j721e-esm.yaml
On Mon, Nov 13, 2023 at 01:52:16PM -0600, Nishanth Menon wrote: > On 10:00-20231113, Neha Malcom Francis wrote: > > Move esm-k3.txt to ti,j721e-esm.yaml in line with the devicetree > > documentation in kernel. > > > > Signed-off-by: Neha Malcom Francis > > --- > > doc/device-tree-bindings/misc/esm-k3.txt | 25 - > > .../misc/ti,j721e-esm.yaml| 53 +++ > > What is the rule here? > https://tgit.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml > we have the binding in upstream kernel. Not to cause anyone undue worry but part of me wants to just submodule/subtree https://github.com/devicetree-org/dt-schema/tree/main/dtschema/schemas as that looks like Rob syncs it with the kernel periodically and since in turn we're working with Rob to upstream our unique bindings there here and not there list should be shrinking, not growing. Since we say "use the kernel device trees" and we don't have the validation make targets, the content of the copies of the schema in our trees is more of a promise that it's true than used anywhere. So perhaps it would be better if something was written down to that effect. -- Tom signature.asc Description: PGP signature
Re: U-Booters at LPC
Hi Simon, On 11/13/23 15:26, Simon Glass wrote: Hi Sean, On Mon, 13 Nov 2023 at 11:15, Sean Anderson wrote: Hi All, I'm at LPC this week, and I'd love to chat with anyone else who's there in person. That would be good, but sadly I am not :-( Ah, well, there's always more conferences. Maybe EOSS next year? --Sean
Re: [PATCH 2/3] sunxi: H616: remove default AXP305 selection
On 11/14/23 10:31, Andre Przywara wrote: > The original H616 devices released about three years ago were typically > paired with an X-Powers AXP305 PMIC. Newer devices uses the smaller > AXP313, and there seem to be far more systems with this PMIC around now. > > Remove the default AXP305 selection for the H616 SoC from the Kconfig, > and move the PMIC selection into the board defconfig files instead. > > Signed-off-by: Andre Przywara Reviewed-by: Jaehoon Chung Best Regards, Jaehoon Chung > --- > configs/orangepi_zero2_defconfig | 1 + > configs/x96_mate_defconfig | 1 + > drivers/power/Kconfig| 1 - > 3 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/configs/orangepi_zero2_defconfig > b/configs/orangepi_zero2_defconfig > index f13735e91c7..127cf9e365a 100644 > --- a/configs/orangepi_zero2_defconfig > +++ b/configs/orangepi_zero2_defconfig > @@ -19,6 +19,7 @@ CONFIG_SYS_I2C_SPEED=40 > CONFIG_SPI_FLASH_MACRONIX=y > CONFIG_PHY_REALTEK=y > CONFIG_SUN8I_EMAC=y > +CONFIG_AXP305_POWER=y > CONFIG_SPI=y > CONFIG_USB_EHCI_HCD=y > CONFIG_USB_OHCI_HCD=y > diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig > index 318951e19c2..e805e0952b3 100644 > --- a/configs/x96_mate_defconfig > +++ b/configs/x96_mate_defconfig > @@ -18,6 +18,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y > CONFIG_SYS_I2C_MVTWSI=y > CONFIG_SYS_I2C_SLAVE=0x7f > CONFIG_SYS_I2C_SPEED=40 > +CONFIG_AXP305_POWER=y > CONFIG_SUPPORT_EMMC_BOOT=y > CONFIG_USB_EHCI_HCD=y > CONFIG_USB_OHCI_HCD=y > diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig > index 2395720c99c..33b8bc1214d 100644 > --- a/drivers/power/Kconfig > +++ b/drivers/power/Kconfig > @@ -56,7 +56,6 @@ choice > depends on ARCH_SUNXI > default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I > default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 > || MACH_SUN8I_R40 > - default AXP305_POWER if MACH_SUN50I_H616 > default AXP818_POWER if MACH_SUN8I_A83T > default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || > MACH_SUN8I_V3S >
Re: [PATCH v3] clk: nuvoton: add read only feature for clk driver
On 11/14/23 04:00, Jim Liu wrote:
Add a flag to set ahb/apb/fiu/spi clock divider as read-only
The spi clock setting is related to booting flash, it is setup by early
bootloader.
It just protects the clock source and can't modify it in uboot.
Signed-off-by: Jim Liu
---
Changes for v3:
- add commit message
Changes for v2:
- add commit message
---
drivers/clk/nuvoton/clk_npcm.c| 15 ---
drivers/clk/nuvoton/clk_npcm.h| 1 +
drivers/clk/nuvoton/clk_npcm8xx.c | 12 ++--
3 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/nuvoton/clk_npcm.c b/drivers/clk/nuvoton/clk_npcm.c
index 8d71f2a24b..18cb9cddbf 100644
--- a/drivers/clk/nuvoton/clk_npcm.c
+++ b/drivers/clk/nuvoton/clk_npcm.c
@@ -135,7 +135,7 @@ static u32 npcm_clk_get_div(struct clk *clk)
return div;
}
-static u32 npcm_clk_set_div(struct clk *clk, u32 div)
+static int npcm_clk_set_div(struct clk *clk, u32 div)
{
struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
struct npcm_clk_div *divider;
@@ -145,6 +145,9 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div)
if (!divider)
return -EINVAL;
+ if (divider->flags & DIV_RO)
+ return 0;
+
if (divider->flags & PRE_DIV2)
div = div >> 1;
@@ -153,6 +156,12 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div)
else
clkdiv = ilog2(div);
+ if (clkdiv > (divider->mask >> (ffs(divider->mask) - 1))) {
+ printf("clkdiv(%d) for clk(%ld) is over limit\n",
+ clkdiv, clk->id);
+ return -EINVAL;
+ }
+
val = readl(priv->base + divider->reg);
val &= ~divider->mask;
val |= (clkdiv << (ffs(divider->mask) - 1)) & divider->mask;
@@ -253,8 +262,8 @@ static ulong npcm_clk_set_rate(struct clk *clk, ulong rate)
if (ret)
return ret;
- debug("%s: rate %lu, new rate (%lu / %u)\n", __func__, rate, parent_rate, div);
- return (parent_rate / div);
+ debug("%s: rate %lu, new rate %lu\n", __func__, rate,
npcm_clk_get_rate(clk));
+ return npcm_clk_get_rate(clk);
}
static int npcm_clk_set_parent(struct clk *clk, struct clk *parent)
diff --git a/drivers/clk/nuvoton/clk_npcm.h b/drivers/clk/nuvoton/clk_npcm.h
index 06b60dc8b8..b4726d8381 100644
--- a/drivers/clk/nuvoton/clk_npcm.h
+++ b/drivers/clk/nuvoton/clk_npcm.h
@@ -50,6 +50,7 @@
#define PRE_DIV2 BIT(2) /* Pre divisor = 2 */
#define POST_DIV2 BIT(3) /* Post divisor = 2 */
#define FIXED_PARENT BIT(4) /* clock source is fixed */
+#define DIV_RO BIT(5) /* divider is read-only */
/* Parameters of PLL configuration */
struct npcm_clk_pll {
diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c
b/drivers/clk/nuvoton/clk_npcm8xx.c
index 27e3cfcf55..d1b32e3237 100644
--- a/drivers/clk/nuvoton/clk_npcm8xx.c
+++ b/drivers/clk/nuvoton/clk_npcm8xx.c
@@ -45,12 +45,12 @@ static struct npcm_clk_select npcm8xx_clk_selectors[] = {
};
static struct npcm_clk_div npcm8xx_clk_dividers[] = {
- {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2},
- {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2},
- {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2},
- {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1},
- {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1},
- {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1},
+ {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2 | DIV_RO},
+ {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2 | DIV_RO},
+ {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2 | DIV_RO},
+ {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1 | DIV_RO},
+ {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1 | DIV_RO},
+ {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1 | DIV_RO},
{NPCM8XX_CLK_SPIX, CLKDIV3, SPIXCKDIV, DIV_TYPE1},
{NPCM8XX_CLK_UART, CLKDIV1, UARTDIV1, DIV_TYPE1},
{NPCM8XX_CLK_UART2, CLKDIV3, UARTDIV2, DIV_TYPE1},
Reviewed-by: Sean Anderson
[PATCH v3 4/4] msm_gpio: use unsigned int
Replaces the uses of "unsigned" with "unsigned int".
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
drivers/gpio/msm_gpio.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
index d9355ed4430c..80cd28bb231f 100644
--- a/drivers/gpio/msm_gpio.c
+++ b/drivers/gpio/msm_gpio.c
@@ -46,7 +46,7 @@ static int msm_gpio_direction_input(struct udevice *dev,
unsigned int gpio)
return 0;
}
-static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
+static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int
value)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
@@ -57,7 +57,7 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned
gpio, int value)
return 0;
}
-static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio,
+static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio,
int value)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
@@ -72,14 +72,14 @@ static int msm_gpio_direction_output(struct udevice *dev,
unsigned gpio,
return 0;
}
-static int msm_gpio_get_value(struct udevice *dev, unsigned gpio)
+static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
}
-static int msm_gpio_get_function(struct udevice *dev, unsigned gpio)
+static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
--
2.42.1
[PATCH v3 3/4] pinctrl: qcom: make compatible with linux DTs
The pinctrl and GPIO drivers are currently heavily incompatible with
upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at
it's own address. Introduce support for these by allowing the soc driver
to specify per-pin register offsets similarly to the Linux driver.
Adjust the GPIO driver to handle these too, and finally enable support
for all pins with the same numbering as used in Linux.
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard845c-uboot.dtsi | 2 +-
arch/arm/dts/sdm845.dtsi | 16 ++
arch/arm/dts/starqltechn-uboot.dtsi | 5 +---
arch/arm/dts/starqltechn.dts | 16 +-
arch/arm/mach-snapdragon/include/mach/gpio.h | 28 ++---
drivers/gpio/msm_gpio.c | 36 --
drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 +-
drivers/pinctrl/qcom/pinctrl-apq8096.c | 2 +-
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
drivers/pinctrl/qcom/pinctrl-qcom.c | 31 ---
drivers/pinctrl/qcom/pinctrl-qcom.h | 5 +++-
drivers/pinctrl/qcom/pinctrl-qcs404.c| 2 +-
drivers/pinctrl/qcom/pinctrl-sdm845.c| 45 ++--
13 files changed, 130 insertions(+), 62 deletions(-)
diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi
b/arch/arm/dts/dragonboard845c-uboot.dtsi
index 7106db8a7348..7728f4f4a3e5 100644
--- a/arch/arm/dts/dragonboard845c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard845c-uboot.dtsi
@@ -19,7 +19,7 @@
bootph-all;
};
- pinctrl_north@390 {
+ pinctrl@340 {
bootph-all;
};
};
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 3b86b9328fc6..4798ace0ff8b 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -26,23 +26,13 @@
#power-domain-cells = <1>;
};
- gpio_north: gpio_north@390 {
- #gpio-cells = <2>;
+ tlmm: pinctrl@340 {
compatible = "qcom,sdm845-pinctrl";
- reg = <0x390 0x40>;
- gpio-count = <150>;
- gpio-controller;
- gpio-ranges = <_north 0 0 150>;
- gpio-bank-name = "soc_north.";
- };
-
- tlmm_north: pinctrl_north@390 {
- compatible = "qcom,sdm845-pinctrl";
- reg = <0x390 0x40>;
+ reg = <0x340 0xc0>;
gpio-count = <150>;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <_north 0 0 150>;
+ gpio-ranges = < 0 0 150>;
/* DEBUG UART */
qup_uart9: qup-uart9-default {
diff --git a/arch/arm/dts/starqltechn-uboot.dtsi
b/arch/arm/dts/starqltechn-uboot.dtsi
index d81a22ffe492..034d5c1c07ed 100644
--- a/arch/arm/dts/starqltechn-uboot.dtsi
+++ b/arch/arm/dts/starqltechn-uboot.dtsi
@@ -19,10 +19,7 @@
clock-controller@10 {
bootph-all;
};
- gpio_north@390 {
- bootph-all;
- };
- pinctrl_north@390 {
+ pinctrl@340 {
bootph-all;
};
};
diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
index eec51d165f98..5b6372bee79a 100644
--- a/arch/arm/dts/starqltechn.dts
+++ b/arch/arm/dts/starqltechn.dts
@@ -65,15 +65,15 @@
serial@a84000 {
status = "okay";
};
+ };
+};
- pinctrl_north@390 {
- muic_i2c: muic_i2c {
- pins = "GPIO_33", "GPIO_34";
- drive-strength = <0x2>;
- function = "gpio";
- bias-disable;
- };
- };
+ {
+ muic_i2c: muic-i2c-n {
+ pins = "GPIO_33", "GPIO_34";
+ drive-strength = <0x2>;
+ function = "gpio";
+ bias-disable;
};
};
diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h
b/arch/arm/mach-snapdragon/include/mach/gpio.h
index bbc2bc16175d..8dac62f870b9 100644
--- a/arch/arm/mach-snapdragon/include/mach/gpio.h
+++ b/arch/arm/mach-snapdragon/include/mach/gpio.h
@@ -1,8 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Empty gpio.h
+ * Qualcomm common pin control data.
*
- * This file must stay as arch/arm/include/asm/gpio.h requires it.
- *
- * (C) Copyright 2015 Mateusz Kulikowski
+ * Copyright (C) 2023 Linaro Ltd.
*/
+#ifndef
[PATCH v3 2/4] pinctrl: qcom: move ipq4019 driver from mach-ipq40xx
Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add
it to drivers/pinctrl/qcom.
Acked-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
arch/arm/Kconfig | 1 +
arch/arm/mach-ipq40xx/Makefile | 8 -
arch/arm/mach-ipq40xx/pinctrl-snapdragon.c | 166 -
arch/arm/mach-ipq40xx/pinctrl-snapdragon.h | 30
drivers/pinctrl/qcom/Kconfig | 7 +
drivers/pinctrl/qcom/Makefile | 1 +
.../pinctrl/qcom}/pinctrl-ipq4019.c| 23 ++-
7 files changed, 27 insertions(+), 209 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 69144ff9cdab..bd48131292e3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -767,6 +767,7 @@ config ARCH_IPQ40XX
select SMEM
select OF_CONTROL
select CLK_QCOM_IPQ4019
+ select PINCTRL_QCOM_IPQ4019
imply CMD_DM
config ARCH_KEYSTONE
diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile
deleted file mode 100644
index b36a935c6f9f..
--- a/arch/arm/mach-ipq40xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2019 Sartura Ltd.
-#
-# Author: Robert Marko
-
-obj-y += pinctrl-snapdragon.o
-obj-y += pinctrl-ipq4019.o
diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c
b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c
deleted file mode 100644
index 036fec93d727..
--- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c
+++ /dev/null
@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * TLMM driver for Qualcomm IPQ40xx
- *
- * (C) Copyright 2018 Ramon Fried
- *
- * Copyright (c) 2020 Sartura Ltd.
- *
- * Author: Robert Marko
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "pinctrl-snapdragon.h"
-
-struct msm_pinctrl_priv {
- phys_addr_t base;
- struct msm_pinctrl_data *data;
-};
-
-#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000)
-#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
-#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
-#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_DISABLE BIT(9)
-
-static const struct pinconf_param msm_conf_params[] = {
- { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
- { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
- { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 2 },
-};
-
-static int msm_get_functions_count(struct udevice *dev)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- return priv->data->functions_count;
-}
-
-static int msm_get_pins_count(struct udevice *dev)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- return priv->data->pin_count;
-}
-
-static const char *msm_get_function_name(struct udevice *dev,
-unsigned int selector)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- return priv->data->get_function_name(dev, selector);
-}
-
-static int msm_pinctrl_probe(struct udevice *dev)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- priv->base = devfdt_get_addr(dev);
- priv->data = (struct msm_pinctrl_data *)dev->driver_data;
-
- return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
-}
-
-static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- return priv->data->get_pin_name(dev, selector);
-}
-
-static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
- unsigned int func_selector)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
- TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
- priv->data->get_function_mux(func_selector) << 2);
- return 0;
-}
-
-static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
- unsigned int param, unsigned int argument)
-{
- struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
- switch (param) {
- case PIN_CONFIG_DRIVE_STRENGTH:
- clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
- TLMM_DRV_STRENGTH_MASK, argument << 6);
- break;
- case PIN_CONFIG_BIAS_DISABLE:
- clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-TLMM_GPIO_PULL_MASK);
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-TLMM_GPIO_PULL_MASK, argument);
- break;
- default:
- return 0;
- }
-
- return 0;
-}
-
-static int msm_pinctrl_bind(struct udevice *dev)
-{
- ofnode node = dev_ofnode(dev);
-
[PATCH v3 1/4] pinctrl: qcom: move out of mach-snapdragon
Move the Qualcomm pinctrl drivers out of mach-snapdragon and over to the rest of the pinctrl drivers, adjust the drivers so that support for each platform can be enabled/disabled individually and introduce platform specific configuration options. Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- MAINTAINERS| 1 + arch/arm/mach-snapdragon/Kconfig | 4 +++ arch/arm/mach-snapdragon/Makefile | 5 --- drivers/pinctrl/Kconfig| 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/qcom/Kconfig | 39 ++ drivers/pinctrl/qcom/Makefile | 9 + .../pinctrl/qcom}/pinctrl-apq8016.c| 19 +-- .../pinctrl/qcom}/pinctrl-apq8096.c| 19 +-- .../pinctrl/qcom/pinctrl-qcom.c| 39 -- .../pinctrl/qcom/pinctrl-qcom.h| 11 +++--- .../pinctrl/qcom}/pinctrl-qcs404.c | 19 +-- .../pinctrl/qcom}/pinctrl-sdm845.c | 19 +-- 13 files changed, 149 insertions(+), 37 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index b483fa2ea95a..f6d63c8ab563 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -576,6 +576,7 @@ F: drivers/clk/qcom/ F: drivers/gpio/msm_gpio.c F: drivers/mmc/msm_sdhci.c F: drivers/phy/msm8916-usbh-phy.c +F: drivers/pinctrl/qcom/ F: drivers/serial/serial_msm.c F: drivers/serial/serial_msm_geni.c F: drivers/smem/msm_smem.c diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index dde37eccc55e..3c9f3bee3f18 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -16,6 +16,7 @@ config SDM845 bool "Qualcomm Snapdragon 845 SoC" select LINUX_KERNEL_IMAGE_HEADER imply CLK_QCOM_SDM845 + imply PINCTRL_QCOM_SDM845 config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x8000 @@ -28,6 +29,7 @@ config TARGET_DRAGONBOARD410C select BOARD_LATE_INIT select ENABLE_ARM_SOC_BOOT0_HOOK imply CLK_QCOM_APQ8016 + imply PINCTRL_QCOM_APQ8016 help Support for 96Boards Dragonboard 410C. This board complies with 96Board Open Platform Specifications. Features: @@ -42,6 +44,7 @@ config TARGET_DRAGONBOARD410C config TARGET_DRAGONBOARD820C bool "96Boards Dragonboard 820C" imply CLK_QCOM_APQ8096 + imply PINCTRL_QCOM_APQ8096 help Support for 96Boards Dragonboard 820C. This board complies with 96Board Open Platform Specifications. Features: @@ -76,6 +79,7 @@ config TARGET_QCS404EVB bool "Qualcomm Technologies, Inc. QCS404 EVB" select LINUX_KERNEL_IMAGE_HEADER imply CLK_QCOM_QCS404 + imply PINCTRL_QCOM_QCS404 help Support for Qualcomm Technologies, Inc. QCS404 evaluation board. Features: diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 497ee35cf7d3..3a3a297c1768 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -8,9 +8,4 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o obj-y += misc.o obj-y += dram.o -obj-y += pinctrl-snapdragon.o -obj-y += pinctrl-apq8016.o -obj-y += pinctrl-apq8096.o -obj-y += pinctrl-qcs404.o -obj-y += pinctrl-sdm845.o obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 75b3ff47a2e8..53f32ea1612e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -355,6 +355,7 @@ source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nexell/Kconfig" source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/nxp/Kconfig" +source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/rockchip/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index fc1f01a02cbd..603c2e0a2da2 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ obj-$(CONFIG_ARCH_RZN1) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_PINCTRL_SUNXI)+= sunxi/ +obj-$(CONFIG_PINCTRL_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl_pic32.o obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig new file mode 100644 index ..412925c48788 --- /dev/null +++ b/drivers/pinctrl/qcom/Kconfig @@ -0,0 +1,39 @@ +if ARCH_SNAPDRAGON + +config PINCTRL_QCOM + depends on PINCTRL_GENERIC + def_bool n + +menu "Qualcomm pinctrl drivers" + +config PINCTRL_QCOM_APQ8016 +
[PATCH v3 0/4] arm: mach-snapdragon: Qualcomm pinctrl driver cleanup
This series moves the Qualcomm pinctrl drivers from mach-snapdragon and mach-ipq40xx to drivers/pinctrl/qcom. It then makes the necessary changes to enable compatibility with Linux DTs. The pinctrl hardware on most Qualcomm platforms is made up of "tiles", these are just banks of pins at different register addresses. The mapping between pin number and tile is totally arbitrary, this unfortunately means that it is necessary to have a map of pin to tile in order to support all pins. Up until now this driver has ignored tiles, meaning that the pin numbers and DT nodes are entirely different to the Linux DT and only a subset of pins are addressable. Patch 2 solves this by introducing the pin_offset map, initially supporting SDM845. This map is used for all pin register lookups for both the pinctrl and GPIO drivers. Similarly to the clock/reset drivers these are both associated with a single DT node, where the pinctrl driver is responsible for binding the GPIO drivers. Patch 3 introduces support for gpio-reserved-ranges, this property is used on some boards to mark pin ranges that shouldn't be touched (else firmware will trigger a fault and reset the board). This series loosely depends on the associated clock driver cleanup which can be found here (Makefile and perhaps DTS conflicts): https://lore.kernel.org/u-boot/20231103-b4-qcom-clk-v3-0-8d2d460ec...@linaro.org --- Changes in v3: * Fix header in msm_gpio.c * Link to v2: https://lore.kernel.org/r/20231106-b4-qcom-pinctrl-v2-0-406e8d868...@linaro.org Changes in v2: * Drop msm -> qcom rename (will be handled in a future patch) * Drop "handle reserved ranges" patch to be introduced alongside a user * Re-order APQ4019 move to be the second patch * Change driver name to pinctrl_qcom instead of qcom_pinctrl * Add MAINTAINERS entry * Move shared GPIO header to mach-snapdragon * Link to v1: https://lore.kernel.org/r/20231025-b4-qcom-pinctrl-v1-0-9123d6a21...@linaro.org --- Caleb Connolly (4): pinctrl: qcom: move out of mach-snapdragon pinctrl: qcom: move ipq4019 driver from mach-ipq40xx pinctrl: qcom: make compatible with linux DTs msm_gpio: use unsigned int MAINTAINERS| 1 + arch/arm/Kconfig | 1 + arch/arm/dts/dragonboard845c-uboot.dtsi| 2 +- arch/arm/dts/sdm845.dtsi | 16 +- arch/arm/dts/starqltechn-uboot.dtsi| 5 +- arch/arm/dts/starqltechn.dts | 16 +- arch/arm/mach-ipq40xx/Makefile | 8 - arch/arm/mach-ipq40xx/pinctrl-snapdragon.c | 166 - arch/arm/mach-snapdragon/Kconfig | 4 + arch/arm/mach-snapdragon/Makefile | 5 - arch/arm/mach-snapdragon/include/mach/gpio.h | 28 +++- arch/arm/mach-snapdragon/pinctrl-sdm845.c | 44 -- arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 33 drivers/gpio/msm_gpio.c| 42 +++--- drivers/pinctrl/Kconfig| 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/qcom/Kconfig | 46 ++ drivers/pinctrl/qcom/Makefile | 10 ++ .../pinctrl/qcom}/pinctrl-apq8016.c| 21 ++- .../pinctrl/qcom}/pinctrl-apq8096.c| 21 ++- .../pinctrl/qcom}/pinctrl-ipq4019.c| 25 +++- .../pinctrl/qcom/pinctrl-qcom.c| 70 + .../pinctrl/qcom/pinctrl-qcom.h| 15 +- .../pinctrl/qcom}/pinctrl-qcs404.c | 21 ++- drivers/pinctrl/qcom/pinctrl-sdm845.c | 100 + 25 files changed, 350 insertions(+), 352 deletions(-) --- base-commit: 8c5e4ddf52ea3c1e85c44cdd5d5b2e2f6c892b4f // Caleb (they/them)
[PATCH 2/2] serial: msm-geni: handle devm_clk_get() errors
devm_clk_get() returns an ERR_PTR on failure, not null. Fix the check to
avoid the board crashing when the clock isn't available.
Additionally, add the missing error handling for this function.
Fixes: 324df15a292e ("serial: qcom: add support for GENI serial driver")
Signed-off-by: Caleb Connolly
---
drivers/serial/serial_msm_geni.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 3e2e15b6cefe..0eee776fe8a4 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -189,8 +189,8 @@ static int geni_serial_set_clock_rate(struct udevice *dev,
u64 rate)
int ret;
clk = devm_clk_get(dev, NULL);
- if (!clk)
- return -EINVAL;
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
ret = clk_set_rate(clk, rate);
return ret;
@@ -249,11 +249,16 @@ static int msm_serial_setbrg(struct udevice *dev, int
baud)
struct msm_serial_data *priv = dev_get_priv(dev);
u64 clk_rate;
u32 clk_div;
+ int ret;
priv->baud = baud;
clk_rate = get_clk_div_rate(baud, priv->oversampling, _div);
- geni_serial_set_clock_rate(dev, clk_rate);
+ ret = geni_serial_set_clock_rate(dev, clk_rate);
+ if (ret < 0) {
+ pr_err("%s: Couldn't set clock rate: %d\n", __func__, ret);
+ return ret;
+ }
geni_serial_baud(priv->base, clk_div, baud);
return 0;
--
2.42.1
[PATCH 1/2] serial: msm-geni: don't rely on parent misc device
commit 1b15483deb3f ("misc: add Qualcomm GENI SE QUP device driver")
introduced support for platform-specific oversampling values, necessary
to configure the UART clocks on all platforms at runtime. However it
relies in probing a parent device. Despite the DM_FLAG_PRE_RELOC flag,
this is not done consistently during boot.
Instead, take another approach by relying on ofnode_ helpers to read the
serial engine base address and do the read directly. This fixes early
UART on boards with a non-default oversampling rate.
Signed-off-by: Caleb Connolly
---
drivers/misc/Kconfig | 7 ---
drivers/misc/Makefile| 1 -
drivers/misc/qcom-geni-se.c | 41
drivers/serial/Kconfig | 2 --
drivers/serial/serial_msm_geni.c | 29 ++--
5 files changed, 19 insertions(+), 61 deletions(-)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 97057de8bf92..423cf22949aa 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -527,13 +527,6 @@ config WINBOND_W83627
legacy UART or other devices in the Winbond Super IO chips
on X86 platforms.
-config QCOM_GENI_SE
- bool "Qualcomm GENI Serial Engine Driver"
- depends on ARCH_SNAPDRAGON
- help
- The driver manages Generic Interface (GENI) firmware based
- Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper.
-
config QFW
bool
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index b67b82358a6c..2d08181251c7 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -60,7 +60,6 @@ obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
obj-$(CONFIG_P2SB) += p2sb-uclass.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
-obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
ifdef CONFIG_QFW
obj-y += qfw.o
obj-$(CONFIG_QFW_PIO) += qfw_pio.o
diff --git a/drivers/misc/qcom-geni-se.c b/drivers/misc/qcom-geni-se.c
deleted file mode 100644
index 281a5ec819a9..
--- a/drivers/misc/qcom-geni-se.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm Generic Interface (GENI) Serial Engine (SE) Wrapper
- *
- * Copyright (C) 2023 Linaro Ltd.
- */
-
-#include
-#include
-#include
-#include
-
-static int geni_se_qup_read(struct udevice *dev, int offset,
- void *buf, int size)
-{
- fdt_addr_t base = dev_read_addr(dev);
-
- if (size != sizeof(u32))
- return -EINVAL;
-
- *(u32 *)buf = readl(base + offset);
-
- return size;
-}
-
-static struct misc_ops geni_se_qup_ops = {
- .read = geni_se_qup_read,
-};
-
-static const struct udevice_id geni_se_qup_ids[] = {
- { .compatible = "qcom,geni-se-qup" },
- {}
-};
-
-U_BOOT_DRIVER(geni_se_qup) = {
- .name = "geni_se_qup",
- .id = UCLASS_MISC,
- .of_match = geni_se_qup_ids,
- .ops = _se_qup_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 9f0f84c9b426..81fdac047824 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -957,8 +957,6 @@ config MSM_SERIAL
config MSM_GENI_SERIAL
bool "Qualcomm on-chip GENI UART"
- select MISC
- imply QCOM_GENI_SE
help
Support UART based on Generic Interface (GENI) Serial Engine (SE),
used on Qualcomm Snapdragon SoCs. Should support all qualcomm SOCs
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 78fd9389c036..3e2e15b6cefe 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -486,12 +486,12 @@ static const struct dm_serial_ops msm_serial_ops = {
.setbrg = msm_serial_setbrg,
};
-static void geni_set_oversampling(struct udevice *dev)
+static int geni_set_oversampling(struct udevice *dev)
{
struct msm_serial_data *priv = dev_get_priv(dev);
- struct udevice *parent_dev = dev_get_parent(dev);
+ ofnode parent_node = ofnode_get_parent(dev_ofnode(dev));
u32 geni_se_version;
- int ret;
+ fdt_addr_t addr;
priv->oversampling = UART_OVERSAMPLING;
@@ -499,16 +499,22 @@ static void geni_set_oversampling(struct udevice *dev)
* It could happen that GENI SE IP is missing in the board's device
* tree or GENI UART node is a direct child of SoC device tree node.
*/
- if (device_get_uclass_id(parent_dev) != UCLASS_MISC)
- return;
+ if (!ofnode_device_is_compatible(parent_node, "qcom,geni-se-qup")) {
+ pr_err("%s: UART node must be a child of geniqup node\n",
+ __func__);
+ return -ENODEV;
+ }
- ret = misc_read(parent_dev, QUP_HW_VER_REG,
- _se_version, sizeof(geni_se_version));
- if (ret != sizeof(geni_se_version))
- return;
[PATCH 0/2] serial: msm-geni: rework oversampling and fix clk API bug
These patches improve GENI UART support during init by implementing the parent property read directly rather than via a misc device, and fixing the error path when the clock can't be found. In my testing, the first few lines of UART output on platforms with non-default oversampling values is often garbled, this is because the parent misc device hasn't yet probed and so the clock rate is incorrect. It is simpler to just access the geni-se parent device directly rather than via a misc device, especially as we only need to read a single register for now. Additionally, this series makes it a hard requirement that the GENI UART node is a child of the generic geni-se controller. This allows us to print a useful error if DTS is incorrect rather than attempting to continue without reading the oversampling value could result in a lot of confusion during platform bringup. --- Caleb Connolly (2): serial: msm-geni: don't rely on parent misc device serial: msm-geni: handle devm_clk_get() errors drivers/misc/Kconfig | 7 --- drivers/misc/Makefile| 1 - drivers/misc/qcom-geni-se.c | 41 drivers/serial/Kconfig | 2 -- drivers/serial/serial_msm_geni.c | 40 ++- 5 files changed, 27 insertions(+), 64 deletions(-) --- base-commit: f3fc930d775ef5c1b7b74b1427491a17680e66ae // Caleb (they/them)
Re: [PATCH v12 9/9] doc: uefi: add HTTP Boot support
Hi Fabio, On Tue, 14 Nov 2023 at 18:05, Fabio Estevam wrote: > > Hi Masahisa, > > On Fri, Nov 10, 2023 at 1:29 AM Masahisa Kojima > wrote: > > > +Set up the load option specifying the target URI:: > > + > > +efidebug boot add -u 1 netinst http://foo/bar > > + > > +When this load option is selected as boot selection, resolve the > > +host ip address by dns, then download the file with wget. > > Just curious: what is the typical size of the file that is downloaded via > wget? > > We are observing some inconsistent behavior with wget as discussed in > this thread: > > https://lore.kernel.org/u-boot/caj+vnu2u9w2nrt6hf1caeq_56sdqviuezudd1iyopdf1cna...@mail.gmail.com/ > > Do you see the same problem? I use a 657MB file for my test. I have not focused on the downloading test before, but I also encountered the file size inconsistent behavior on my board(Socionext Developerbox). At the 15 trials of downloading the same file, unexpected file transfer behavior occurred. Packets received 475093, Transfer Successful Bytes transferred = 687929344 (2900f800 hex) Packets received 475105, Transfer Successful Bytes transferred = 687929344 (2900f800 hex) Packets received 475116, Transfer Successful Bytes transferred = 687929344 (2900f800 hex) Packets received 475096, Transfer Successful Bytes transferred = 5503 (34896f3 hex) <-- size is wrong Thanks, Masahisa Kojima > > Thanks, > > Fabio Estevam
[PATCH] spl: fix TPL_SYS_MALLOC_F description
This config option enables the malloc() pool in TPL not the SPL. Fix the description to accurately reflect this. Fixes: fd8497dae54 (spl: Create proper symbols for enabling the malloc() pool) Signed-off-by: John Keeping --- Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index 7df91d789f6..00ed1ecc173 100644 --- a/Kconfig +++ b/Kconfig @@ -327,7 +327,7 @@ config SPL_SYS_MALLOC_F_LEN malloc() region in SDRAM once it is inited. config TPL_SYS_MALLOC_F - bool "Enable malloc() pool in SPL" + bool "Enable malloc() pool in TPL" depends on SYS_MALLOC_F && TPL default y if SPL_SYS_MALLOC_F help -- 2.42.1
[PATCH 00/13] Import "string" I/O functions from Linux
This series imports generic versions of ioread_rep/iowrite_rep and
reads/writes from Linux. Some cleanup is done to make sure that all
platforms have proper defines for implemented functions and there are no
redefinitions.
Igor Prusov (13):
sandbox: move asm-generic include to the end of file
x86: Add defines for ins/outs functions
mips: io.h: Add const to reads functions params
mips: io.h: Add defines for read/write/in/out functions
riscv: io.h: Add defines for reads/writes functions
riscv: io.h: Fix signatures of reads/writes functions
nios2: io.h: Add defines for ins/outs functions
powerpc: io.h: Add defines for __raw_{read,write} functions
xtensa: io.h: Add defines for ins/outs functions
asm-generic: Import functions from Linux
spi: meson_spifc_a1: Switch to io{read,write}32_rep()
treewide: Include linux/io.h instead of asm-generic/io.h
musb-new: Remove implementation of io.h functions
arch/mips/include/asm/io.h | 35 +-
arch/nios2/include/asm/io.h | 6 +
arch/powerpc/include/asm/io.h| 11 +
arch/riscv/include/asm/io.h | 26 +-
arch/sandbox/include/asm/io.h| 28 +-
arch/x86/include/asm/io.h| 6 +
arch/xtensa/include/asm/io.h | 6 +
drivers/mtd/nand/raw/atmel/nand-controller.c | 34 --
drivers/mtd/nand/raw/nand_base.c | 33 --
drivers/spi/cadence_qspi.c | 2 +-
drivers/spi/meson_spifc_a1.c | 4 +-
drivers/usb/cdns3/cdns3-ti.c | 1 -
drivers/usb/dwc3/dwc3-meson-g12a.c | 2 +-
drivers/usb/dwc3/dwc3-meson-gxl.c| 2 +-
drivers/usb/musb-new/musb_io.h | 24 --
include/asm-generic/io.h | 348 +++
16 files changed, 450 insertions(+), 118 deletions(-)
--
2.34.1
Re: [PATCH v1 5/5] fastboot: add oem console command support
Hi Svyatoslav,
On mar., nov. 14, 2023 at 12:30, Svyatoslav Ryhel wrote:
> 14 листопада 2023 р. 12:24:52 GMT+02:00, Mattijs Korpershoek
> написав(-ла):
>>Hi Svyatoslav,
>>
>>Thank you for your patch.
>>
>>On mar., nov. 07, 2023 at 14:42, Svyatoslav Ryhel wrote:
>>
>>> From: Ion Agorria
>>>
>>> "oem console" serves to read console record buffer.
>>>
>>> Signed-off-by: Ion Agorria
>>> Signed-off-by: Svyatoslav Ryhel
>>> ---
>>> doc/android/fastboot.rst | 1 +
>>> drivers/fastboot/Kconfig | 7 +++
>>> drivers/fastboot/fb_command.c | 39 +++
>>> include/fastboot.h| 1 +
>>> 4 files changed, 48 insertions(+)
>>>
>>> diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst
>>> index 1ad8a897c8..05d8f77759 100644
>>> --- a/doc/android/fastboot.rst
>>> +++ b/doc/android/fastboot.rst
>>> @@ -29,6 +29,7 @@ The following OEM commands are supported (if enabled):
>>>with = boot_ack boot_partition
>>> - ``oem bootbus`` - this executes ``mmc bootbus %x %s`` to configure eMMC
>>> - ``oem run`` - this executes an arbitrary U-Boot command
>>> +- ``oem console`` - this dumps U-Boot console record buffer
>>>
>>> Support for both eMMC and NAND devices is included.
>>>
>>> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
>>> index 837c6f1180..58b08120a4 100644
>>> --- a/drivers/fastboot/Kconfig
>>> +++ b/drivers/fastboot/Kconfig
>>> @@ -241,6 +241,13 @@ config FASTBOOT_OEM_RUN
>>> this feature if you are using verified boot, as it will allow an
>>> attacker to bypass any restrictions you have in place.
>>>
>>> +config FASTBOOT_CMD_OEM_CONSOLE
>>> + bool "Enable the 'oem console' command"
>>> + depends on CONSOLE_RECORD
>>> + help
>>> + Add support for the "oem console" command to input and read console
>>> + record buffer.
>>> +
>>> endif # FASTBOOT
>>>
>>> endmenu
>>> diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
>>> index 6f621df074..acf5971108 100644
>>> --- a/drivers/fastboot/fb_command.c
>>> +++ b/drivers/fastboot/fb_command.c
>>> @@ -41,6 +41,7 @@ static void reboot_recovery(char *, char *);
>>> static void oem_format(char *, char *);
>>> static void oem_partconf(char *, char *);
>>> static void oem_bootbus(char *, char *);
>>> +static void oem_console(char *, char *);
>>> static void run_ucmd(char *, char *);
>>> static void run_acmd(char *, char *);
>>>
>>> @@ -108,6 +109,10 @@ static const struct {
>>> .command = "oem run",
>>> .dispatch = CONFIG_IS_ENABLED(FASTBOOT_OEM_RUN, (run_ucmd),
>>> (NULL))
>>> },
>>> + [FASTBOOT_COMMAND_OEM_CONSOLE] = {
>>> + .command = "oem console",
>>> + .dispatch = CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_CONSOLE,
>>> (oem_console), (NULL))
>>> + },
>>> [FASTBOOT_COMMAND_UCMD] = {
>>> .command = "UCmd",
>>> .dispatch = CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT, (run_ucmd),
>>> (NULL))
>>> @@ -159,6 +164,23 @@ void fastboot_multiresponse(int cmd, char *response)
>>> case FASTBOOT_COMMAND_GETVAR:
>>> fastboot_getvar_all(response);
>>> break;
>>> +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_CONSOLE)
>>
>>Checkpatch also complains about this.
>>
>>Can we rewrite this using if (IS_ENABLED(CONFIG...)) please ?
>>
>
> Please, do not relay on checkpatch that much. In this case #ifdef is better
> since in this case all under ifdef will be cut off while using if(...)
> requires all code under the if to be able to be run even if config is not
> enabled. Thanks.
I understand that sometimes, checkpatch generates false positives or bad
suggestions.
I also understand the differences between #ifdef and if (IS_ENABLED()).
I did not measure whether the binary size is bigger when switching from
#ifdef to "if IS_ENABLED()" but I suspect that the compiler can
optimize this out as it's known at compile-time.
This file (and the fastboot code in general) mostly uses
"if (IS_ENABLED())" and to keep the code consistent I recommend using it.
Therefore, can we please use if (IS_ENABLED()) here ?
Thank you
Mattijs
>
>>> + case FASTBOOT_COMMAND_OEM_CONSOLE:
>>> + char buf[FASTBOOT_RESPONSE_LEN] = { 0 };
>>> +
>>> + if (console_record_isempty()) {
>>> + console_record_reset();
>>> + fastboot_okay(NULL, response);
>>> + } else {
>>> + int ret = console_record_readline(buf, sizeof(buf) - 5);
>>> +
>>> + if (ret < 0)
>>> + fastboot_fail("Error reading console",
>>> response);
>>> + else
>>> + fastboot_response("INFO", response, "%s", buf);
>>> + }
>>> + break;
>>> +#endif
>>> default:
>>> fastboot_fail("Unknown multiresponse command", response);
>>> break;
>>> @@ -503,3 +525,20 @@ static void __maybe_unused oem_bootbus(char
Re: [PATCH 2/6] led-uclass: honour ->label field populated by driver's own .bind
ping
Am Mo., 23. Okt. 2023 um 12:45 Uhr schrieb Marek Vasut :
>
> On 10/23/23 10:51, Rasmus Villemoes wrote:
> > On 19/10/2023 15.54, Marek Vasut wrote:
> >> On 10/19/23 11:58, Rasmus Villemoes wrote:
> >>> If the driver's own .bind method has populated uc_plat->label, don't
> >>> override that. This is necessary for an upcoming driver for ti,lp5562,
> >>> where the DT binding unfortunately says to use "chan-name" and not
> >>> "label".
> >>>
> >>> Signed-off-by: Rasmus Villemoes
> >>> ---
> >>>drivers/led/led-uclass.c | 4 +++-
> >>>1 file changed, 3 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c
> >>> index 5a5d07b9a7..0232fa84de 100644
> >>> --- a/drivers/led/led-uclass.c
> >>> +++ b/drivers/led/led-uclass.c
> >>> @@ -71,7 +71,9 @@ static int led_post_bind(struct udevice *dev)
> >>>struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
> >>>const char *default_state;
> >>>-uc_plat->label = dev_read_string(dev, "label");
> >>> +if (!uc_plat->label)
> >>> +uc_plat->label = dev_read_string(dev, "label");
> >>> +
> >>
> >> One thing I have to wonder about is, why does this controller have label
> >> property in the top-level node , what is that used for ?
> >>
> >> (see Linux Documentation/devicetree/bindings/leds/leds-lp55xx.yaml)
> >>
> >> Reviewed-by: Marek Vasut
> >
> > Reading the linux driver, it seems that the top-level label, if any, is
> > used as part of the naming for individual channels if they don't have
> > individual chan-name properties:
> >
> >
> > if (pdata->led_config[chan].name) {
> > led->cdev.name = pdata->led_config[chan].name;
> > } else {
> > snprintf(name, sizeof(name), "%s:channel%d",
> > pdata->label ? : chip->cl->name, chan);
> > led->cdev.name = name;
> > }
> >
> > but I think the rationale in d1188adb2dabc is a bit weak, since the only
> > example also does have individual chan-name properties.
> >
> > [Complete aside: At first I thought it was related to the multi-color
> > LED work that has been ongoing for many many years (I think there was an
> > LWN article at some point), where this could be exposed as a single
> > multi-color LED, as opposed to the "traditional" three/four individual
> > LEDs. In the former case, there would only be one sysfs entry, but with
> > attributes exposing the multicolor functionality. I must admit I don't
> > know the status of that work, when something reaches v31,
> > http://archive.lwn.net:8080/linux-kernel/20200722071055.GA8984@amd/t/ ,
> > it's hard to know if it ever lands, or if pieces of it has landed.]
>
> +CC Pavel
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info/privacypolicy
Re: [PATCH] led: Do not overwrite label
ping
Am Mo., 23. Okt. 2023 um 10:26 Uhr schrieb Marek Vasut :
>
> On 10/23/23 10:21, Christian Gmeiner wrote:
> > label might have been set by a non device-tree based U-Boot driver already.
> >
> > In my concrete case there is a PCI driver that uses device_bind_driver(..)
> > for different class types. The UCLASS_LED specific driver sets label
> > in its bind function.
> >
> > Without this change the LEDs exposed by the PCI device are not available.
> >
> > Fixes: 83c63f0d11 ("led: Move OF "label" property parsing to core")
> > Signed-off-by: Christian Gmeiner
> > ---
> > drivers/led/led-uclass.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c
> > index 68ca3c2970..aebdfdeb95 100644
> > --- a/drivers/led/led-uclass.c
> > +++ b/drivers/led/led-uclass.c
> > @@ -71,9 +71,10 @@ static int led_post_bind(struct udevice *dev)
> > struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
> > const char *default_state;
> >
> > - uc_plat->label = dev_read_string(dev, "label");
> > if (!uc_plat->label)
> > - uc_plat->label = ofnode_get_name(dev_ofnode(dev));
> > + uc_plat->label = dev_read_string(dev, "label");
> > + if (!uc_plat->label)
> > + uc_plat->label = ofnode_get_name(dev_ofnode(dev));
> >
> > uc_plat->default_state = LEDST_COUNT;
>
> +CC Rasmus, you really do want to review this one.
>
> There is existing and more extensive series from Rasmus addressing the
> same issue.
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info/privacypolicy
[PATCH 13/13] musb-new: Remove implementation of io.h functions
Since {read,write}s{l, w, b}() functions are now supported in linux/io.h
there is no need to add custom implementation to driver.
Signed-off-by: Igor Prusov
---
drivers/usb/musb-new/musb_io.h | 24
1 file changed, 24 deletions(-)
diff --git a/drivers/usb/musb-new/musb_io.h b/drivers/usb/musb-new/musb_io.h
index 72a5365632..19b12f36a5 100644
--- a/drivers/usb/musb-new/musb_io.h
+++ b/drivers/usb/musb-new/musb_io.h
@@ -14,31 +14,7 @@
#ifndef __MUSB_LINUX_PLATFORM_ARCH_H__
#define __MUSB_LINUX_PLATFORM_ARCH_H__
-#ifndef __UBOOT__
#include
-#else
-#include
-#endif
-
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \
- && !defined(CONFIG_PPC32) \
- && !defined(CONFIG_PPC64) && !defined(CONFIG_MIPS) \
- && !defined(CONFIG_M68K)
-static inline void readsl(const void __iomem *addr, void *buf, int len)
- { insl((unsigned long)addr, buf, len); }
-static inline void readsw(const void __iomem *addr, void *buf, int len)
- { insw((unsigned long)addr, buf, len); }
-static inline void readsb(const void __iomem *addr, void *buf, int len)
- { insb((unsigned long)addr, buf, len); }
-
-static inline void writesl(const void __iomem *addr, const void *buf, int len)
- { outsl((unsigned long)addr, buf, len); }
-static inline void writesw(const void __iomem *addr, const void *buf, int len)
- { outsw((unsigned long)addr, buf, len); }
-static inline void writesb(const void __iomem *addr, const void *buf, int len)
- { outsb((unsigned long)addr, buf, len); }
-
-#endif
/* NOTE: these offsets are all in bytes */
--
2.34.1
[PATCH 12/13] treewide: Include linux/io.h instead of asm-generic/io.h
Directly including asm-generic/io.h may break build because it will cause redefenition of generic io macros if linux/io.h gets included later, hence replace it with direct include of linux/io.h Signed-off-by: Igor Prusov --- drivers/spi/cadence_qspi.c | 2 +- drivers/usb/cdns3/cdns3-ti.c | 1 - drivers/usb/dwc3/dwc3-meson-g12a.c | 2 +- drivers/usb/dwc3/dwc3-meson-gxl.c | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index cc3a54f295..23240c1302 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -17,6 +16,7 @@ #include #include #include +#include #include #include #include "cadence_qspi.h" diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c index 92a7941ed1..2e44aadea4 100644 --- a/drivers/usb/cdns3/cdns3-ti.c +++ b/drivers/usb/cdns3/cdns3-ti.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index e0356e653f..196035215a 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -8,13 +8,13 @@ #include #include -#include #include #include #include #include #include #include +#include #include #include #include diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c index d56f2747b6..cbe8aaa005 100644 --- a/drivers/usb/dwc3/dwc3-meson-gxl.c +++ b/drivers/usb/dwc3/dwc3-meson-gxl.c @@ -8,12 +8,12 @@ #define DEBUG #include -#include #include #include #include #include #include +#include #include #include #include -- 2.34.1
[PATCH 11/13] spi: meson_spifc_a1: Switch to io{read,write}32_rep()
Use io{read,write}32_rep() functions to sync code with Linux version.
Signed-off-by: Igor Prusov
---
drivers/spi/meson_spifc_a1.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/meson_spifc_a1.c b/drivers/spi/meson_spifc_a1.c
index 099c4c037d..a33b1a3879 100644
--- a/drivers/spi/meson_spifc_a1.c
+++ b/drivers/spi/meson_spifc_a1.c
@@ -129,7 +129,7 @@ static void amlogic_spifc_a1_drain_buffer(struct
amlogic_spifc_a1 *spifc,
writel(SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
spifc->base + SPIFC_A1_DBUF_CTRL_REG);
- readsl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
+ ioread32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
if (pad) {
data = readl(spifc->base + SPIFC_A1_DBUF_DATA_REG);
@@ -146,7 +146,7 @@ static void amlogic_spifc_a1_fill_buffer(struct
amlogic_spifc_a1 *spifc,
writel(SPIFC_A1_DBUF_DIR | SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
spifc->base + SPIFC_A1_DBUF_CTRL_REG);
- writesl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
+ iowrite32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
if (pad) {
memcpy(, buf + len - pad, pad);
--
2.34.1
[PATCH 10/13] asm-generic: Import functions from Linux
Currently {read,write}s{b,w,lq}() functions are available only on some
architectures, and there are no io{read,write}{8,16,32,64}_rep()
functions in u-boot. This patch adds generic versions that may be used
without arch-specific implementation.
Since some of added functions were already added locally in some files,
remove them to avoid redeclaration errors.
Signed-off-by: Igor Prusov
---
drivers/mtd/nand/raw/atmel/nand-controller.c | 34 --
drivers/mtd/nand/raw/nand_base.c | 33 --
include/asm-generic/io.h | 348 +++
3 files changed, 348 insertions(+), 67 deletions(-)
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c
b/drivers/mtd/nand/raw/atmel/nand-controller.c
index fa962ba591..37b0c3a5cd 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -352,40 +352,6 @@ static int atmel_nfc_wait(struct
atmel_hsmc_nand_controller *nc, bool poll,
return ret;
}
-static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- writeb(buf[i], addr);
-}
-
-static void ioread8_rep(void *addr, uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- buf[i] = readb(addr);
-}
-
-static void ioread16_rep(void *addr, void *buf, int len)
-{
- int i;
- u16 *p = (u16 *)buf;
-
- for (i = 0; i < len; i++)
- p[i] = readw(addr);
-}
-
-static void iowrite16_rep(void *addr, const void *buf, int len)
-{
- int i;
- u16 *p = (u16 *)buf;
-
- for (i = 0; i < len; i++)
- writew(p[i], addr);
-}
-
static u8 atmel_nand_read_byte(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd_to_nand(mtd);
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 6b4adcf6bd..815ddf5d8d 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -245,39 +245,6 @@ static void nand_write_byte16(struct mtd_info *mtd,
uint8_t byte)
chip->write_buf(mtd, (uint8_t *), 2);
}
-static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- writeb(buf[i], addr);
-}
-static void ioread8_rep(void *addr, uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- buf[i] = readb(addr);
-}
-
-static void ioread16_rep(void *addr, void *buf, int len)
-{
- int i;
- u16 *p = (u16 *) buf;
-
- for (i = 0; i < len; i++)
- p[i] = readw(addr);
-}
-
-static void iowrite16_rep(void *addr, void *buf, int len)
-{
- int i;
-u16 *p = (u16 *) buf;
-
-for (i = 0; i < len; i++)
-writew(p[i], addr);
-}
-
/**
* nand_write_buf - [DEFAULT] write buffer to chip
* @mtd: MTD device structure
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index 7a2f0dba31..13d99cfb59 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -105,5 +105,353 @@ static inline void unmap_physmem(void *vaddr, unsigned
long flags)
}
#endif
+/*
+ * __raw_{read,write}{b,w,l,q}() access memory in native endianness.
+ *
+ * On some architectures memory mapped IO needs to be accessed differently.
+ * On the simple architectures, we just read/write the memory location
+ * directly.
+ */
+
+#ifndef __raw_readb
+#define __raw_readb __raw_readb
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+ return *(const volatile u8 __force *)addr;
+}
+#endif
+
+#ifndef __raw_readw
+#define __raw_readw __raw_readw
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+ return *(const volatile u16 __force *)addr;
+}
+#endif
+
+#ifndef __raw_readl
+#define __raw_readl __raw_readl
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+ return *(const volatile u32 __force *)addr;
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef __raw_readq
+#define __raw_readq __raw_readq
+static inline u64 __raw_readq(const volatile void __iomem *addr)
+{
+ return *(const volatile u64 __force *)addr;
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+#ifndef __raw_writeb
+#define __raw_writeb __raw_writeb
+static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
+{
+ *(volatile u8 __force *)addr = value;
+}
+#endif
+
+#ifndef __raw_writew
+#define __raw_writew __raw_writew
+static inline void __raw_writew(u16 value, volatile void __iomem *addr)
+{
+ *(volatile u16 __force *)addr = value;
+}
+#endif
+
+#ifndef __raw_writel
+#define __raw_writel __raw_writel
+static inline void __raw_writel(u32 value, volatile void __iomem *addr)
+{
+ *(volatile u32 __force *)addr = value;
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef __raw_writeq
+#define __raw_writeq __raw_writeq
+static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
+{
+ *(volatile u64 __force *)addr = value;
[PATCH 09/13] xtensa: io.h: Add defines for ins/outs functions
Add defines for {in,out}s{b,w,l}() functions to make asm-generic/io.h
aware of them.
Signed-off-by: Igor Prusov
---
arch/xtensa/include/asm/io.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index 76a646e882..87ad9faa29 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -76,6 +76,12 @@ void insl(unsigned long port, void *dst, unsigned long
count);
void outsb(unsigned long port, const void *src, unsigned long count);
void outsw(unsigned long port, const void *src, unsigned long count);
void outsl(unsigned long port, const void *src, unsigned long count);
+#define insb insb
+#define insw insw
+#define insl insl
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
#define IO_SPACE_LIMIT ~0
--
2.34.1
[PATCH 08/13] powerpc: io.h: Add defines for __raw_{read, write} functions
Add defines for __raw_{read,write}{b,w,l}() functions to make
make asm-generic/io.h aware of them.
Signed-off-by: Igor Prusov
---
arch/powerpc/include/asm/io.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index f63cae0bc8..2412bb9d7c 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -138,26 +138,37 @@ static inline unsigned char __raw_readb(const volatile
void __iomem *addr)
{
return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
}
+#define __raw_readb __raw_readb
+
static inline unsigned short __raw_readw(const volatile void __iomem *addr)
{
return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
}
+#define __raw_readw __raw_readw
+
static inline unsigned int __raw_readl(const volatile void __iomem *addr)
{
return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
}
+#define __raw_readl __raw_readl
+
static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
{
*(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
}
+#define __raw_writeb __raw_writeb
+
static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
{
*(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
}
+#define __raw_writew __raw_writew
+
static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
{
*(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
}
+#define __raw_writel __raw_writel
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
--
2.34.1
[PATCH 07/13] nios2: io.h: Add defines for ins/outs functions
Add defines for {in,out}s{b,w,l} functions to make asm-generic/io.h
aware of them.
Signed-off-by: Igor Prusov
---
arch/nios2/include/asm/io.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h
index 817cd72e00..321e4fd1ca 100644
--- a/arch/nios2/include/asm/io.h
+++ b/arch/nios2/include/asm/io.h
@@ -94,6 +94,9 @@ static inline void insl (unsigned long port, void *dst,
unsigned long count)
unsigned long *p = dst;
while (count--) *p++ = inl (port);
}
+#define insb insb
+#define insw insw
+#define insl insl
static inline void outsb (unsigned long port, const void *src, unsigned long
count)
{
@@ -111,6 +114,9 @@ static inline void outsl (unsigned long port, const void
*src, unsigned long cou
const unsigned long *p = src;
while (count--) outl (*p++, port);
}
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
/*
* Clear and set bits in one shot. These macros can be used to clear and
--
2.34.1
[PATCH 06/13] riscv: io.h: Fix signatures of reads/writes functions
Change type of address parameter from int* to volatile void* for
{read,write}s{b,w,l}() functions and add const qualifier for reads. This
is done to keep function signatures in sync with asm-generic/io.h and
other platforms.
Signed-off-by: Igor Prusov
---
arch/riscv/include/asm/io.h | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index cedd5375d6..da16585803 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -218,7 +218,8 @@ static inline u64 readq(const volatile void __iomem *addr)
#define insw(p, d, l) readsw(__io(p), d, l)
#define insl(p, d, l) readsl(__io(p), d, l)
-static inline void readsb(unsigned int *addr, void *data, int bytelen)
+static inline void readsb(const volatile void __iomem *addr, void *data,
+ unsigned int bytelen)
{
unsigned char *ptr;
unsigned char *ptr2;
@@ -233,7 +234,8 @@ static inline void readsb(unsigned int *addr, void *data,
int bytelen)
}
}
-static inline void readsw(unsigned int *addr, void *data, int wordlen)
+static inline void readsw(const volatile void __iomem *addr, void *data,
+ unsigned int wordlen)
{
unsigned short *ptr;
unsigned short *ptr2;
@@ -248,7 +250,8 @@ static inline void readsw(unsigned int *addr, void *data,
int wordlen)
}
}
-static inline void readsl(unsigned int *addr, void *data, int longlen)
+static inline void readsl(const volatile void __iomem *addr, void *data,
+ unsigned int longlen)
{
unsigned int *ptr;
unsigned int *ptr2;
@@ -263,7 +266,8 @@ static inline void readsl(unsigned int *addr, void *data,
int longlen)
}
}
-static inline void writesb(unsigned int *addr, const void *data, int bytelen)
+static inline void writesb(volatile void __iomem *addr, const void *data,
+ unsigned int bytelen)
{
unsigned char *ptr;
unsigned char *ptr2;
@@ -278,7 +282,8 @@ static inline void writesb(unsigned int *addr, const void
*data, int bytelen)
}
}
-static inline void writesw(unsigned int *addr, const void *data, int wordlen)
+static inline void writesw(volatile void __iomem *addr, const void *data,
+ unsigned int wordlen)
{
unsigned short *ptr;
unsigned short *ptr2;
@@ -293,7 +298,8 @@ static inline void writesw(unsigned int *addr, const void
*data, int wordlen)
}
}
-static inline void writesl(unsigned int *addr, const void *data, int longlen)
+static inline void writesl(volatile void __iomem *addr, const void *data,
+ unsigned int longlen)
{
unsigned int *ptr;
unsigned int *ptr2;
--
2.34.1
[PATCH 05/13] riscv: io.h: Add defines for reads/writes functions
Add defines for {read,write}s{b,w,l} functions to make asm-generic/io.h
aware of them.
Signed-off-by: Igor Prusov
---
arch/riscv/include/asm/io.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 4170877a1a..cedd5375d6 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -307,6 +307,14 @@ static inline void writesl(unsigned int *addr, const void
*data, int longlen)
longlen--;
}
}
+
+#define readsb readsb
+#define readsw readsw
+#define readsl readsl
+#define writesb writesb
+#define writesw writesw
+#define writesl writesl
+
#endif
#define outb_p(val, port) outb((val), (port))
--
2.34.1
[PATCH 04/13] mips: io.h: Add defines for read/write/in/out functions
Add defines for {read,write}{b,w,l,q}(), {read,write}s{b,w,l,q}() and
{in,out}s{b,w,l,q}() functions to make asm-generic/io.h aware of them.
Signed-off-by: Igor Prusov
---
arch/mips/include/asm/io.h | 32
1 file changed, 32 insertions(+)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 12595c4334..3774acaadc 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -336,6 +336,22 @@ BUILDIO_MEM(b, u8)
BUILDIO_MEM(w, u16)
BUILDIO_MEM(l, u32)
BUILDIO_MEM(q, u64)
+#define __raw_readb __raw_readb
+#define __raw_readw __raw_readw
+#define __raw_readl __raw_readl
+#define __raw_readq __raw_readq
+#define __raw_writeb __raw_writeb
+#define __raw_writew __raw_writew
+#define __raw_writel __raw_writel
+#define __raw_writeq __raw_writeq
+#define readb readb
+#define readw readw
+#define readl readl
+#define readq readq
+#define writeb writeb
+#define writew writew
+#define writel writel
+#define writeq writeq
#define __BUILD_IOPORT_PFX(bus, bwlq, type)\
__BUILD_IOPORT_SINGLE(bus, bwlq, type, )\
@@ -449,8 +465,24 @@ __BUILD_IOPORT_STRING(bwlq, type)
BUILDSTRING(b, u8)
BUILDSTRING(w, u16)
BUILDSTRING(l, u32)
+#define readsb readsb
+#define readsw readsw
+#define readsl readsl
+#define writesb writesb
+#define writesw writesw
+#define writesl writesl
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
+#define insb insb
+#define insw insw
+#define insl insl
#ifdef CONFIG_64BIT
BUILDSTRING(q, u64)
+#define readsq readsq
+#define writesq writesq
+#define insq insq
+#define outsq outsq
#endif
--
2.34.1
[PATCH 03/13] mips: io.h: Add const to reads functions params
Currently reads{b,w,l}() functions don't have const qualifier for their
address parameter. Since asm-generic/io.h in Linux has const for all
read functions, add it here as well to keep signatures in sync.
Signed-off-by: Igor Prusov
---
arch/mips/include/asm/io.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index d3ad669301..12595c4334 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -405,7 +405,8 @@ static inline void writes##bwlq(volatile void __iomem *mem,
\
} \
} \
\
-static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
+static inline void reads##bwlq(const volatile void __iomem *mem, \
+ void *addr, \
unsigned int count) \
{ \
volatile type *__addr = addr; \
--
2.34.1
[PATCH 02/13] x86: Add defines for ins/outs functions
Add defines for {in,out}s{b,w,l}() functions to make sure that
they will be used by asm-generic/io.h
Signed-off-by: Igor Prusov
---
arch/x86/include/asm/io.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 83dc09757e..5efb2e1b21 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -202,10 +202,16 @@ __OUT(l,,int)
__INS(b)
__INS(w)
__INS(l)
+#define insb insb
+#define insw insw
+#define insl insl
__OUTS(b)
__OUTS(w)
__OUTS(l)
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
/* IO space accessors */
#define clrio(type, addr, clear) \
--
2.34.1
[PATCH 01/13] sandbox: move asm-generic include to the end of file
Generic version of io.h should be included at the end of
architecture-specific ones to make sure that arch implementations are
used and to avoid redefinitions.
Signed-off-by: Igor Prusov
---
arch/sandbox/include/asm/io.h | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index 31ab7289b4..77a02e5f52 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -28,20 +28,6 @@ void *map_physmem(phys_addr_t paddr, unsigned long len,
unsigned long flags);
void unmap_physmem(const void *vaddr, unsigned long flags);
#define unmap_physmem unmap_physmem
-#include
-
-/* For sandbox, we want addresses to point into our RAM buffer */
-static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
-{
- return map_physmem(paddr, len, MAP_WRBACK);
-}
-
-/* Remove a previous mapping */
-static inline void unmap_sysmem(const void *vaddr)
-{
- unmap_physmem(vaddr, MAP_WRBACK);
-}
-
/* Map from a pointer to our RAM buffer */
phys_addr_t map_to_sysmem(const void *ptr);
@@ -229,5 +215,19 @@ static inline void memcpy_toio(volatile void *dst, const
void *src, int count)
#include
#include
+#include
+
+/* For sandbox, we want addresses to point into our RAM buffer */
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+ return map_physmem(paddr, len, MAP_WRBACK);
+}
+
+/* Remove a previous mapping */
+static inline void unmap_sysmem(const void *vaddr)
+{
+ unmap_physmem(vaddr, MAP_WRBACK);
+}
+
#endif
--
2.34.1
Re: [PATCH] clk: exynos: Add header guard for clk-pll.h
Hi,
2023년 11월 9일 (목) 04:54, Sean Anderson 님이 작성:
> On 11/7/23 16:22, Sam Protsenko wrote:
> > The clk-pll.h is going to be included in multiple files soon. Add
> > missing header guard to prevent possible build errors in future.
> >
> > Signed-off-by: Sam Protsenko
> > Fixes: 166097e87753 ("clk: exynos: add clock driver for Exynos7420 Soc")
> > ---
> > drivers/clk/exynos/clk-pll.h | 5 +
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
> > index c79aac44258b..7b7af5e67612 100644
> > --- a/drivers/clk/exynos/clk-pll.h
> > +++ b/drivers/clk/exynos/clk-pll.h
> > @@ -5,4 +5,9 @@
> >* Thomas Abraham
> >*/
> >
> > +#ifndef __EXYNOS_CLK_PLL_H
> > +#define __EXYNOS_CLK_PLL_H
> > +
> > unsigned long pll145x_get_rate(unsigned int *con1, unsigned long
> fin_freq);
> > +
> > +#endif /* __EXYNOS_CLK_PLL_H */
>
> Reviewed-by: Sean Anderson
applied to u-boot-samsung.
Thanks.
Minkyu Kang.
Re: [PATCH] serial: s5p: Fix clk_get_by_index() error code check
Hi
2023년 11월 8일 (수) 03:39, Sam Protsenko 님이 작성:
> clk_get_by_index() returns negative number on error. Assigning it to
> unsigned int makes the subsequent "ret < 0" check always false, leading
> in turn to possible unhandled errors. Change 'ret' variable type to
> signed int so the code checks and handles clk_get_by_index() return code
> properly.
>
> Signed-off-by: Sam Protsenko
> Fixes: cf75cdf96ef2 ("serial: s5p: use clock api to get clock rate")
> ---
> drivers/serial/serial_s5p.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
> index 7aeb8c0f8cb7..fe52580d64de 100644
> --- a/drivers/serial/serial_s5p.c
> +++ b/drivers/serial/serial_s5p.c
> @@ -118,7 +118,7 @@ int s5p_serial_setbrg(struct udevice *dev, int
> baudrate)
>
> #if IS_ENABLED(CONFIG_CLK_EXYNOS) || IS_ENABLED(CONFIG_ARCH_APPLE)
> struct clk clk;
> - u32 ret;
> + int ret;
>
> ret = clk_get_by_index(dev, 1, );
> if (ret < 0)
> --
> 2.39.2
>
applied to u-boot-samsung.
Thanks.
Minkyu Kang.
Re: [PATCH] exynos: Avoid duplicate reset_cpu with SYSRESET enabled
Hi,
2023년 10월 31일 (화) 02:36, Tom Rini 님이 작성:
> On Mon, Oct 30, 2023 at 11:55:02AM -0500, Sam Protsenko wrote:
>
> > The sysreset uclass unconditionally provides a definition of the
> > reset_cpu() function. So does the exynos soc code. Fix the build with
> > SYSRESET enabled by omitting the function from the soc code in that
> > case. The code still needs to be kept around for use in SPL.
> >
> > This commit was inspired by commit 6e19dc84c14b ("sunxi: Avoid duplicate
> > reset_cpu with SYSRESET enabled").
> >
> > Signed-off-by: Sam Protsenko
>
> Reviewed-by: Tom Rini
>
> --
> Tom
applied to u-boot-samsung.
Thanks.
Minkyu Kang.
Re: [PATCH 0/3] exynos: Include missing CPU headers
Hi 2023년 10월 21일 (토) 06:46, Sam Protsenko 님이 작성: > During porting a new Exynos-based board to U-Boot I faced a couple of > similar build errors due to missing inclusion. This > series make sure it's fixed in all places I found. > > Sam Protsenko (3): > arm: exynos: Include missing CPU header in soc.c > arm: exynos: Include missing CPU header in gpio.h > watchdog: s5p_wdt: Include missing CPU header > > arch/arm/mach-exynos/include/mach/gpio.h | 3 +++ > arch/arm/mach-exynos/soc.c | 1 + > drivers/watchdog/s5p_wdt.c | 1 + > 3 files changed, 5 insertions(+) > > -- > 2.39.2 > applied to u-boot-samsung. Thanks. Minkyu Kang.
Re: [PATCH v1 5/5] fastboot: add oem console command support
14 листопада 2023 р. 12:24:52 GMT+02:00, Mattijs Korpershoek
написав(-ла):
>Hi Svyatoslav,
>
>Thank you for your patch.
>
>On mar., nov. 07, 2023 at 14:42, Svyatoslav Ryhel wrote:
>
>> From: Ion Agorria
>>
>> "oem console" serves to read console record buffer.
>>
>> Signed-off-by: Ion Agorria
>> Signed-off-by: Svyatoslav Ryhel
>> ---
>> doc/android/fastboot.rst | 1 +
>> drivers/fastboot/Kconfig | 7 +++
>> drivers/fastboot/fb_command.c | 39 +++
>> include/fastboot.h| 1 +
>> 4 files changed, 48 insertions(+)
>>
>> diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst
>> index 1ad8a897c8..05d8f77759 100644
>> --- a/doc/android/fastboot.rst
>> +++ b/doc/android/fastboot.rst
>> @@ -29,6 +29,7 @@ The following OEM commands are supported (if enabled):
>>with = boot_ack boot_partition
>> - ``oem bootbus`` - this executes ``mmc bootbus %x %s`` to configure eMMC
>> - ``oem run`` - this executes an arbitrary U-Boot command
>> +- ``oem console`` - this dumps U-Boot console record buffer
>>
>> Support for both eMMC and NAND devices is included.
>>
>> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
>> index 837c6f1180..58b08120a4 100644
>> --- a/drivers/fastboot/Kconfig
>> +++ b/drivers/fastboot/Kconfig
>> @@ -241,6 +241,13 @@ config FASTBOOT_OEM_RUN
>>this feature if you are using verified boot, as it will allow an
>>attacker to bypass any restrictions you have in place.
>>
>> +config FASTBOOT_CMD_OEM_CONSOLE
>> +bool "Enable the 'oem console' command"
>> +depends on CONSOLE_RECORD
>> +help
>> + Add support for the "oem console" command to input and read console
>> + record buffer.
>> +
>> endif # FASTBOOT
>>
>> endmenu
>> diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
>> index 6f621df074..acf5971108 100644
>> --- a/drivers/fastboot/fb_command.c
>> +++ b/drivers/fastboot/fb_command.c
>> @@ -41,6 +41,7 @@ static void reboot_recovery(char *, char *);
>> static void oem_format(char *, char *);
>> static void oem_partconf(char *, char *);
>> static void oem_bootbus(char *, char *);
>> +static void oem_console(char *, char *);
>> static void run_ucmd(char *, char *);
>> static void run_acmd(char *, char *);
>>
>> @@ -108,6 +109,10 @@ static const struct {
>> .command = "oem run",
>> .dispatch = CONFIG_IS_ENABLED(FASTBOOT_OEM_RUN, (run_ucmd),
>> (NULL))
>> },
>> +[FASTBOOT_COMMAND_OEM_CONSOLE] = {
>> +.command = "oem console",
>> +.dispatch = CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_CONSOLE,
>> (oem_console), (NULL))
>> +},
>> [FASTBOOT_COMMAND_UCMD] = {
>> .command = "UCmd",
>> .dispatch = CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT, (run_ucmd),
>> (NULL))
>> @@ -159,6 +164,23 @@ void fastboot_multiresponse(int cmd, char *response)
>> case FASTBOOT_COMMAND_GETVAR:
>> fastboot_getvar_all(response);
>> break;
>> +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_CONSOLE)
>
>Checkpatch also complains about this.
>
>Can we rewrite this using if (IS_ENABLED(CONFIG...)) please ?
>
Please, do not relay on checkpatch that much. In this case #ifdef is better
since in this case all under ifdef will be cut off while using if(...) requires
all code under the if to be able to be run even if config is not enabled.
Thanks.
>> +case FASTBOOT_COMMAND_OEM_CONSOLE:
>> +char buf[FASTBOOT_RESPONSE_LEN] = { 0 };
>> +
>> +if (console_record_isempty()) {
>> +console_record_reset();
>> +fastboot_okay(NULL, response);
>> +} else {
>> +int ret = console_record_readline(buf, sizeof(buf) - 5);
>> +
>> +if (ret < 0)
>> +fastboot_fail("Error reading console",
>> response);
>> +else
>> +fastboot_response("INFO", response, "%s", buf);
>> +}
>> +break;
>> +#endif
>> default:
>> fastboot_fail("Unknown multiresponse command", response);
>> break;
>> @@ -503,3 +525,20 @@ static void __maybe_unused oem_bootbus(char
>> *cmd_parameter, char *response)
>> else
>> fastboot_okay(NULL, response);
>> }
>> +
>> +/**
>> + * oem_console() - Execute the OEM console command
>> + *
>> + * @cmd_parameter: Pointer to command parameter
>> + * @response: Pointer to fastboot response buffer
>> + */
>> +static void __maybe_unused oem_console(char *cmd_parameter, char *response)
>> +{
>> +if (cmd_parameter)
>> +console_in_puts(cmd_parameter);
>> +
>> +if (console_record_isempty())
>> +fastboot_fail("Empty console", response);
>> +else
>> +fastboot_response("MORE", response, NULL);
>
>MORE -> TEXT
>
>> +}
>> diff --git a/include/fastboot.h b/include/fastboot.h
>>
Re: [PATCH] clk: meson: add Hardware Clock measure driver
Hi,
On 13/11/2023 19:00, Igor Prusov wrote:
Hi Neil,
On Mon, Nov 13, 2023 at 09:49:32AM +0100, Neil Armstrong wrote:
Amlogic SoCs embeds an hardware clock measure block, port it
from Linux and implement it as a UCLK_CLK with only the dump
op and fail-only xlate.
Signed-off-by: Neil Armstrong
---
drivers/clk/meson/Kconfig | 9 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/clk-measure.c | 634
3 files changed, 644 insertions(+)
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index cdc9d6f76c..da097ae7b8 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -29,3 +29,12 @@ config CLK_MESON_A1
help
Enable clock support for the Amlogic A1 SoC family, such as
the A113L
+
+config CLK_MESON_MSR
+ bool "Enable clock measure driver for Amlogic SoCs"
+ depends on CLK && ARCH_MESON
+ depends on CMD_CLK
+ default ARCH_MESON
+ help
+ Enable clock support for the Hardware Clock Measure for various
+ Amlogic SoCs.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index d975f07aab..c7a446e86c 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_CLK_MESON_AXG) += axg-ao.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o
obj-$(CONFIG_CLK_MESON_A1) += a1.o
+obj-$(CONFIG_CLK_MESON_MSR) += clk-measure.o
diff --git a/drivers/clk/meson/clk-measure.c b/drivers/clk/meson/clk-measure.c
new file mode 100644
index 00..abb038647a
--- /dev/null
+++ b/drivers/clk/meson/clk-measure.c
@@ -0,0 +1,634 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Based on Linux driver from:
+ * (C) Copyright 2018 - BayLibre, SAS
+ * Author: Neil Armstrong
+ * (C) Copyright 2023 - Neil Armstrong
+ */
+
+#include
Looks like we only need common.h for get_timer(), that is used by
regmap_read_poll_timeout(), so we can either include time.h here or
rather include it in regmap.h, otherwise LGTM.
I'll fix that, and post a v2 when your soc_clk_dump serie is merged.
Thanks,
Neil
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MSR_CLK_DUTY 0x0
+#define MSR_CLK_REG0 0x4
+#define MSR_CLK_REG1 0x8
+#define MSR_CLK_REG2 0xc
+
+#define MSR_DURATION GENMASK(15, 0)
+#define MSR_ENABLE BIT(16)
+#define MSR_CONT BIT(17) /* continuous measurement */
+#define MSR_INTR BIT(18) /* interrupts */
+#define MSR_RUNBIT(19)
+#define MSR_CLK_SRCGENMASK(26, 20)
+#define MSR_BUSY BIT(31)
+
+#define MSR_VAL_MASK GENMASK(15, 0)
+
+#define DIV_MIN32
+#define DIV_STEP 32
+#define DIV_MAX640
+
+#define CLK_MSR_MAX128
+
+struct meson_msr_id {
+ unsigned int id;
+ const char *name;
+};
+
+struct meson_msr {
+ struct regmap *regmap;
+ struct meson_msr_id *msr_table;
+};
+
+#define CLK_MSR_ID(__id, __name) \
+ [__id] = {.id = __id, .name = __name,}
+
+static struct meson_msr_id clk_msr_m8[CLK_MSR_MAX] = {
+ CLK_MSR_ID(0, "ring_osc_out_ee0"),
+ CLK_MSR_ID(1, "ring_osc_out_ee1"),
+ CLK_MSR_ID(2, "ring_osc_out_ee2"),
+ CLK_MSR_ID(3, "a9_ring_osck"),
+ CLK_MSR_ID(6, "vid_pll"),
+ CLK_MSR_ID(7, "clk81"),
+ CLK_MSR_ID(8, "encp"),
+ CLK_MSR_ID(9, "encl"),
+ CLK_MSR_ID(11, "eth_rmii"),
+ CLK_MSR_ID(13, "amclk"),
+ CLK_MSR_ID(14, "fec_clk_0"),
+ CLK_MSR_ID(15, "fec_clk_1"),
+ CLK_MSR_ID(16, "fec_clk_2"),
+ CLK_MSR_ID(18, "a9_clk_div16"),
+ CLK_MSR_ID(19, "hdmi_sys"),
+ CLK_MSR_ID(20, "rtc_osc_clk_out"),
+ CLK_MSR_ID(21, "i2s_clk_in_src0"),
+ CLK_MSR_ID(22, "clk_rmii_from_pad"),
+ CLK_MSR_ID(23, "hdmi_ch0_tmds"),
+ CLK_MSR_ID(24, "lvds_fifo"),
+ CLK_MSR_ID(26, "sc_clk_int"),
+ CLK_MSR_ID(28, "sar_adc"),
+ CLK_MSR_ID(30, "mpll_clk_test_out"),
+ CLK_MSR_ID(31, "audac_clkpi"),
+ CLK_MSR_ID(32, "vdac"),
+ CLK_MSR_ID(33, "sdhc_rx"),
+ CLK_MSR_ID(34, "sdhc_sd"),
+ CLK_MSR_ID(35, "mali"),
+ CLK_MSR_ID(36, "hdmi_tx_pixel"),
+ CLK_MSR_ID(38, "vdin_meas"),
+ CLK_MSR_ID(39, "pcm_sclk"),
+ CLK_MSR_ID(40, "pcm_mclk"),
+ CLK_MSR_ID(41, "eth_rx_tx"),
+ CLK_MSR_ID(42, "pwm_d"),
+ CLK_MSR_ID(43, "pwm_c"),
+ CLK_MSR_ID(44, "pwm_b"),
+ CLK_MSR_ID(45, "pwm_a"),
+ CLK_MSR_ID(46, "pcm2_sclk"),
+ CLK_MSR_ID(47, "ddr_dpll_pt"),
+ CLK_MSR_ID(48, "pwm_f"),
+ CLK_MSR_ID(49, "pwm_e"),
+ CLK_MSR_ID(59, "hcodec"),
+ CLK_MSR_ID(60, "usb_32k_alt"),
+ CLK_MSR_ID(61, "gpio"),
+ CLK_MSR_ID(62, "vid2_pll"),
+ CLK_MSR_ID(63,
Re: [PATCH v1 5/5] fastboot: add oem console command support
Hi Svyatoslav,
Thank you for your patch.
On mar., nov. 07, 2023 at 14:42, Svyatoslav Ryhel wrote:
> From: Ion Agorria
>
> "oem console" serves to read console record buffer.
>
> Signed-off-by: Ion Agorria
> Signed-off-by: Svyatoslav Ryhel
> ---
> doc/android/fastboot.rst | 1 +
> drivers/fastboot/Kconfig | 7 +++
> drivers/fastboot/fb_command.c | 39 +++
> include/fastboot.h| 1 +
> 4 files changed, 48 insertions(+)
>
> diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst
> index 1ad8a897c8..05d8f77759 100644
> --- a/doc/android/fastboot.rst
> +++ b/doc/android/fastboot.rst
> @@ -29,6 +29,7 @@ The following OEM commands are supported (if enabled):
>with = boot_ack boot_partition
> - ``oem bootbus`` - this executes ``mmc bootbus %x %s`` to configure eMMC
> - ``oem run`` - this executes an arbitrary U-Boot command
> +- ``oem console`` - this dumps U-Boot console record buffer
>
> Support for both eMMC and NAND devices is included.
>
> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
> index 837c6f1180..58b08120a4 100644
> --- a/drivers/fastboot/Kconfig
> +++ b/drivers/fastboot/Kconfig
> @@ -241,6 +241,13 @@ config FASTBOOT_OEM_RUN
> this feature if you are using verified boot, as it will allow an
> attacker to bypass any restrictions you have in place.
>
> +config FASTBOOT_CMD_OEM_CONSOLE
> + bool "Enable the 'oem console' command"
> + depends on CONSOLE_RECORD
> + help
> + Add support for the "oem console" command to input and read console
> + record buffer.
> +
> endif # FASTBOOT
>
> endmenu
> diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
> index 6f621df074..acf5971108 100644
> --- a/drivers/fastboot/fb_command.c
> +++ b/drivers/fastboot/fb_command.c
> @@ -41,6 +41,7 @@ static void reboot_recovery(char *, char *);
> static void oem_format(char *, char *);
> static void oem_partconf(char *, char *);
> static void oem_bootbus(char *, char *);
> +static void oem_console(char *, char *);
> static void run_ucmd(char *, char *);
> static void run_acmd(char *, char *);
>
> @@ -108,6 +109,10 @@ static const struct {
> .command = "oem run",
> .dispatch = CONFIG_IS_ENABLED(FASTBOOT_OEM_RUN, (run_ucmd),
> (NULL))
> },
> + [FASTBOOT_COMMAND_OEM_CONSOLE] = {
> + .command = "oem console",
> + .dispatch = CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_CONSOLE,
> (oem_console), (NULL))
> + },
> [FASTBOOT_COMMAND_UCMD] = {
> .command = "UCmd",
> .dispatch = CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT, (run_ucmd),
> (NULL))
> @@ -159,6 +164,23 @@ void fastboot_multiresponse(int cmd, char *response)
> case FASTBOOT_COMMAND_GETVAR:
> fastboot_getvar_all(response);
> break;
> +#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_CONSOLE)
Checkpatch also complains about this.
Can we rewrite this using if (IS_ENABLED(CONFIG...)) please ?
> + case FASTBOOT_COMMAND_OEM_CONSOLE:
> + char buf[FASTBOOT_RESPONSE_LEN] = { 0 };
> +
> + if (console_record_isempty()) {
> + console_record_reset();
> + fastboot_okay(NULL, response);
> + } else {
> + int ret = console_record_readline(buf, sizeof(buf) - 5);
> +
> + if (ret < 0)
> + fastboot_fail("Error reading console",
> response);
> + else
> + fastboot_response("INFO", response, "%s", buf);
> + }
> + break;
> +#endif
> default:
> fastboot_fail("Unknown multiresponse command", response);
> break;
> @@ -503,3 +525,20 @@ static void __maybe_unused oem_bootbus(char
> *cmd_parameter, char *response)
> else
> fastboot_okay(NULL, response);
> }
> +
> +/**
> + * oem_console() - Execute the OEM console command
> + *
> + * @cmd_parameter: Pointer to command parameter
> + * @response: Pointer to fastboot response buffer
> + */
> +static void __maybe_unused oem_console(char *cmd_parameter, char *response)
> +{
> + if (cmd_parameter)
> + console_in_puts(cmd_parameter);
> +
> + if (console_record_isempty())
> + fastboot_fail("Empty console", response);
> + else
> + fastboot_response("MORE", response, NULL);
MORE -> TEXT
> +}
> diff --git a/include/fastboot.h b/include/fastboot.h
> index d1a2b74b2f..23d26fb4be 100644
> --- a/include/fastboot.h
> +++ b/include/fastboot.h
> @@ -37,6 +37,7 @@ enum {
> FASTBOOT_COMMAND_OEM_PARTCONF,
> FASTBOOT_COMMAND_OEM_BOOTBUS,
> FASTBOOT_COMMAND_OEM_RUN,
> + FASTBOOT_COMMAND_OEM_CONSOLE,
> FASTBOOT_COMMAND_ACMD,
> FASTBOOT_COMMAND_UCMD,
> FASTBOOT_COMMAND_COUNT
> --
> 2.40.1
Re: [PATCH v1 2/5] fastboot: implement "getvar all"
14 листопада 2023 р. 11:32:35 GMT+02:00, Mattijs Korpershoek
написав(-ла):
>Hi Svyatoslav,
>
>Thank you for your patch.
>
>On mar., nov. 07, 2023 at 14:42, Svyatoslav Ryhel wrote:
>
>> From: Ion Agorria
>>
>> This commit implements "fastboot getvar all" listing
>> by iterating the existing dispatchers that don't require
>> parameters (as we pass NULL), uses fastboot multiresponse.
>>
>> Signed-off-by: Ion Agorria
>> Signed-off-by: Svyatoslav Ryhel
>
>Some small comments below.
>
>With those addressed, please add:
>
>Reviewed-by: Mattijs Korpershoek
>
>> ---
>> doc/android/fastboot-protocol.rst | 3 ++
>> drivers/fastboot/fb_command.c | 3 ++
>> drivers/fastboot/fb_getvar.c | 75 +--
>> include/fastboot-internal.h | 7 +++
>> 4 files changed, 75 insertions(+), 13 deletions(-)
>>
>> diff --git a/doc/android/fastboot-protocol.rst
>> b/doc/android/fastboot-protocol.rst
>> index e8cbd7f24e..8bd6d7168f 100644
>> --- a/doc/android/fastboot-protocol.rst
>> +++ b/doc/android/fastboot-protocol.rst
>> @@ -173,6 +173,9 @@ The various currently defined names are::
>>bootloader requiring a signature before
>>it will install or boot images.
>>
>> + all Provides all info from commands above as
>> + they were called one by one
>> +
>> Names starting with a lowercase character are reserved by this
>> specification. OEM-specific names should not start with lowercase
>> characters.
>> diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
>> index ab72d8c781..6f621df074 100644
>> --- a/drivers/fastboot/fb_command.c
>> +++ b/drivers/fastboot/fb_command.c
>> @@ -156,6 +156,9 @@ int fastboot_handle_command(char *cmd_string, char
>> *response)
>> void fastboot_multiresponse(int cmd, char *response)
>> {
>> switch (cmd) {
>> +case FASTBOOT_COMMAND_GETVAR:
>> +fastboot_getvar_all(response);
>> +break;
>> default:
>> fastboot_fail("Unknown multiresponse command", response);
>> break;
>> diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
>> index 8cb8ffa2c6..fc5e1dac87 100644
>> --- a/drivers/fastboot/fb_getvar.c
>> +++ b/drivers/fastboot/fb_getvar.c
>> @@ -29,53 +29,67 @@ static void getvar_is_userspace(char *var_parameter,
>> char *response);
>>
>> static const struct {
>> const char *variable;
>> +bool list;
>> void (*dispatch)(char *var_parameter, char *response);
>> } getvar_dispatch[] = {
>> {
>> .variable = "version",
>> -.dispatch = getvar_version
>> +.dispatch = getvar_version,
>> +.list = true,
>> }, {
>> .variable = "version-bootloader",
>> -.dispatch = getvar_version_bootloader
>> +.dispatch = getvar_version_bootloader,
>> +.list = true
>> }, {
>> .variable = "downloadsize",
>> -.dispatch = getvar_downloadsize
>> +.dispatch = getvar_downloadsize,
>> +.list = true
>> }, {
>> .variable = "max-download-size",
>> -.dispatch = getvar_downloadsize
>> +.dispatch = getvar_downloadsize,
>> +.list = true
>> }, {
>> .variable = "serialno",
>> -.dispatch = getvar_serialno
>> +.dispatch = getvar_serialno,
>> +.list = true
>> }, {
>> .variable = "version-baseband",
>> -.dispatch = getvar_version_baseband
>> +.dispatch = getvar_version_baseband,
>> +.list = true
>> }, {
>> .variable = "product",
>> -.dispatch = getvar_product
>> +.dispatch = getvar_product,
>> +.list = true
>> }, {
>> .variable = "platform",
>> -.dispatch = getvar_platform
>> +.dispatch = getvar_platform,
>> +.list = true
>> }, {
>> .variable = "current-slot",
>> -.dispatch = getvar_current_slot
>> +.dispatch = getvar_current_slot,
>> +.list = true
>> #if IS_ENABLED(CONFIG_FASTBOOT_FLASH)
>> }, {
>> .variable = "has-slot",
>> -.dispatch = getvar_has_slot
>> +.dispatch = getvar_has_slot,
>> +.list = false
>> #endif
>> #if IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC)
>> }, {
>> .variable = "partition-type",
>> -.dispatch = getvar_partition_type
>> +.dispatch = getvar_partition_type,
>> +.list = false
>> #endif
>> #if IS_ENABLED(CONFIG_FASTBOOT_FLASH)
>> }, {
>> .variable = "partition-size",
>> -.dispatch = getvar_partition_size
>> +.dispatch = getvar_partition_size,
>> +.list = false
>> #endif
>> }, {
>> .variable = "is-userspace",
>> -
