Hi list,
This is my first time to submit a patch to this list. I hope it is in the
correct format. All these patches are based on the Mar. 15's git tree plus
16 patches from TsiChung.
David Wu (7):
Colfdfire MCF5282: enable icache if CONFIG_SYS_ENABLE_ICACHE is
defined
AT49BV322A
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
CREDITS |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/CREDITS b/CREDITS
index 043ba6e..144fc27 100644
--- a/CREDITS
+++ b/CREDITS
@@ -513,7 +513,7 @@ D: Port to MPC555/556 microcontrollers and support for
cmi
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
cpu/mcf52x2/cpu_init.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 170bbfc..36f62cc 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
The device id for this Flash is 0xc8.
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
drivers/mtd/cfi_flash.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index fdba297..af86f99 100644
--- a/drivers
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
Makefile | 46 +
board/Arcturus/uC5272/Makefile | 44 +
board/Arcturus/uC5272/config.mk |1 +
board/Arcturus/uC5272/u-boot.lds | 142 +++
board/Arcturus/uC5272/uC5272.c | 57
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
Makefile | 21 +++
board/Arcturus/uC5275/Makefile | 44 +++
board/Arcturus/uC5275/config.mk | 23
board/Arcturus/uC5275/u-boot.lds | 139
board/Arcturus/uC5275/uC5275.c
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
board/Mercury/ep2500/Makefile | 44 ++
board/Mercury/ep2500/config.mk | 23 +++
board/Mercury/ep2500/ep2500.c | 191 +
board/Mercury/ep2500/u-boot.lds | 140 ++
include/configs
Hi Stefan,
I am new here and I am not quite clear about how to split this patch.
Any suggestion?
Regards,
David
On Thu, 08 Apr 2010 05:35:35 -0400, Stefan Roese s...@denx.de wrote:
On Thursday 08 April 2010 02:00:23 David Wu wrote:
The device id for this Flash is 0xc8.
Signed-off
Hi Stefan,
On Thu, 08 Apr 2010 11:21:45 -0400, Stefan Roese s...@denx.de wrote:
Hi David,
On Thursday 08 April 2010 17:16:26 David Wu wrote:
I am new here and I am not quite clear about how to split this patch.
Any suggestion?
I didn't mean that you should split this patch, but that you
Hi Stefan,
I think those patches if I resubmit are same as before except the subjects
differ.
Anyway If no one complains then I will send.
Regards,
David
On Fri, 09 Apr 2010 02:46:17 -0400, Stefan Roese s...@denx.de wrote:
Hi David,
On Thursday 08 April 2010 17:47:46 David Wu wrote:
I
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
cpu/mcf52x2/cpu_init.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 170bbfc..36f62cc 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
board/Mercury/ep2500/Makefile | 44 ++
board/Mercury/ep2500/config.mk | 23 +++
board/Mercury/ep2500/ep2500.c | 191 +
board/Mercury/ep2500/u-boot.lds | 140 ++
include
The device id for this Flash is 0xc8.
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
drivers/mtd/cfi_flash.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index fdba297..af86f99 100644
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
Makefile | 46 +
board/Arcturus/uC5272/Makefile | 44 +
board/Arcturus/uC5272/config.mk |1 +
board/Arcturus/uC5272/u-boot.lds | 142 +++
board/Arcturus/uC5272/uC5272.c
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
Makefile | 21 +++
board/Arcturus/uC5275/Makefile | 44 +++
board/Arcturus/uC5275/config.mk | 23
board/Arcturus/uC5275/u-boot.lds | 139
board/Arcturus/uC5275
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
CREDITS |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/CREDITS b/CREDITS
index 043ba6e..144fc27 100644
--- a/CREDITS
+++ b/CREDITS
@@ -513,7 +513,7 @@ D: Port to MPC555/556 microcontrollers and support
The device id for this Flash is 0xc8.
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
drivers/mtd/cfi_flash.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index fdba297..af86f99 100644
--- a/drivers
Hi Wolfgang,
Thanks for checking the patch, Please see inline.
On Fri, 09 Apr 2010 18:51:06 -0400, Wolfgang Denk w...@denx.de wrote:
Dear David Wu,
In message op.vatgy2wjqig...@cyprus.local you wrote:
Signed-off-by: David Wu davi...@arcturusnetworks.com
---
board/Mercury/ep2500/Makefile
If the tx_delay is not enabled, the RGMII/1000M can't work.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
b/ar
Unfortunately, the integrated macphy default is enabled, which will
increase power consuming, if we do not use this PHY. So let's disable
it at first, which will save power consuming. If we really use it, then
enable it in driver level.
Signed-off-by: David Wu <david...@rock-chips.com>
---
nt preview: The clk_saradc is dividing from the 24M,
clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width. Signed-off-by: David
Wu <david...@rock-chips.com> Acked-by: Philipp Tomsich
<philipp.toms...@theobroma-systems.com>
Review
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3288-popmetal.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3288-popmetal.dtsi
b/arch/arm/dts/rk3288-popmetal.dtsi
index dd6ce8b..63785eb 100644
--- a/arch/arm/dts/rk3288-popmetal.dtsi
+++
nt preview: Signed-off-by: David Wu <david...@rock-chips.com> ---
arch/arm/dts/rk3368-px5-evb.dts
| 4 1 file changed, 4 insertions(+) diff --git
a/arch/arm/dts/rk3368-px5-evb.dts
b/arch/arm/dts/rk3368-px5-evb.dts index c7478f7..e9c5eba 100644 ---
a/arch/arm/dts/rk3368-px5-evb.d
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3328-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 8a14c65..df44ccb 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-e
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich &
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
arch/arm/dts/rv1108.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --
nt preview: The clk_saradc is dividing from the 24M,
clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width. Signed-off-by:
David Wu <david...@rock-chips.com> Acked-by: Philipp Tomsich
<philipp.toms...@theobroma-systems.com>
Review
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich &
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rv1108-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts
index 0128dd8..e21b57f 100644
--- a/arch/arm/dts/rv1108-evb.dts
+++ b/arch/arm/dts/rv1108-e
The SARADC is used for adc keys and charging detect at uboot
loader. Except for the rk3036 and rk3228 Socs, the others
support the SARADC IP.
David Wu (14):
adc: Add driver for Rockchip SARADC
configs: rockchip: Enable the ROCKCHIP_SARADC config
clk: rockchip: Add rv1108 SARADC clock
Except for 3036 and 3228 Socs, which don't support SARADC,
enable the ROCKCHIP_SARADC config at the other Socs' defconfig.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Change in v2:
- Enable the ROCKCHIP_SARADC at other configs
configs/chromebit_mickey_defconfig | 2 ++
c
The ADC can support some channels signal-ended some bits Successive
Approximation
Register (SAR) A/D Converter, like 6-channel and 10-bit. It converts the analog
input signal into some bits binary digital codes.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp T
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich &
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich &
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add commit message
Changes in v2: None
arch/arm/dts/rv1108-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/a
nt preview: Except for 3036 and 3228 Socs, which don't support SARADC,
enable the ROCKCHIP_SARADC config at the other Socs' defconfig.
Signed-off-by:
David Wu <david...@rock-chips.com> --- [...]
Content analysis details: (5.6 points, 5.0 required)
pts rule name
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Acked-by: Philipp Tomsich &
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich &
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich &
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add commit message
Changes in v2: None
arch/arm/dts/rk3399-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/a
nt preview: Enable the SARADC for download key pressed detect.
Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v3: - Add commit message
[...]
Content analysis details: (5.6 points, 5.0 required)
pts rule name
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add commit message
Changes in v2: None
arch/arm/dts/rk3368-px5-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3368-px5-evb.dts b/ar
David Wu (14):
dm: adc: Add driver for Rockchip SARADC
rockchip: configs: Enable the ROCKCHIP_SARADC config
rockchip: clk: Add rv1108 SARADC clock support
rockchip: clk: Add SARADC clock support for rk3288
rockchip: clk: Add rk3328 SARADC clock support
rockchip: clk: Add rk3368 SARADC
nt preview: Enable the SARADC for download key pressed detect.
Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v3: - Add commit message
[...]
Content analysis details: (5.6 points, 5.0 required)
pts rule name
This serie of patches integrates the setup mac clock is
internal or external, as well as the way for setting rmii
or rgmii interface.
David Wu (6):
rockchip: clk: Add mac clock set for rk3399
rockchip: dts: rk3399-evb: Change the tx/rx delay value for
transmission quality
rockchip
If we include both the rk3288_grf.h and rv1108_grf.h, there is a
number of compiling error for redefinition. So we define the reg
structs of mac_grf at gmac_rockchip.c. Remove the rk**_grf.h files,
give them own grf offset for their use.
Signed-off-by: David Wu <david...@rock-chips.
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3399.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
If the Ethernet address is not set, the network can't work,
enable the random address config for default use.
Signed-off-by: David Wu <david...@rock-chips.com>
---
configs/evb-rk3288_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/evb-rk3288_defconfig b/confi
Give the mac controller the correct tx-delay and rx-delay value
for the rgmii mode transmission. If they are not matched, there
would be Ethernet packets lost, the net feature may not work.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3399-evb.dts | 4 ++--
If the mac clock if from the external IO, set clock rate with 0;
If the mac clock if from the internal divider pll, set 50M for
rmii mode and set 125M for rgmii.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 23 +++
1 file chang
The rv1108 mac only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 67 +++--
1 file chang
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
Saradc integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5
drivers/clk/rockchip/clk_rk
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
Saradc integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3399.c | 34 ++
1 file changed, 34 inse
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rv1108.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi
index 77ca24e..d6927ee 100644
--- a/arch/arm/dts/rv1108.dtsi
+++ b/arch/arm/dts/rv1108.dtsi
@@
The Saradc is used for adc keys and charging detect at uboot
loader. Except for the rk3036 and rk3228 Socs, the others
support the Saradc IP.
David Wu (8):
adc: Add driver for Rockchip saradc
configs: rockchip: Enable the ROCKCHIP_SARADC config
clk: rockchip: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
Saradc integer divider control register is 10-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3328.c | 37 +
1 file chang
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 5
drivers/clk/rockchip/clk_rv1108.c | 35 +
include/dt-bindings/clock/rv1108-cru.h | 2 ++
3 files changed, 42 insertions(+)
diff
The ADC can support some channels signal-ended some bits Successive
Approximation
Register (SAR) A/D Converter, like 6-channel and 10-bit. It converts the analog
input signal into some bits binary digital codes.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/adc/K
Except for 3036 and 3228 Socs, which don't support Saradc,
enable the ROCKCHIP_SARADC config at the other Socs' defconfig.
Signed-off-by: David Wu <david...@rock-chips.com>
---
configs/evb-rk3288_defconfig | 2 ++
configs/evb-rk3328_defconfig | 2 ++
configs/evb-rk3399_def
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3288.c | 45 +++
1 file changed, 45 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3288.c
b/drivers/clk/rockchip/clk_rk3288.c
index 478195b..29652b0 100644
--- a/d
Add rk3328-evb gmac support.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
arch/arm/dts/rk3328-evb.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 3
If the Ethernet address is not set, the network can't work,
enable the random address config for default use.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobr
The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/ar
nt preview: Give the mac controller the correct tx-delay and rx-delay
value for the rgmii mode transmission. If they are not matched, there would
be Ethernet packets lost, the net feature may not work. Signed-off-by: David
Wu <david...@rock-chips.com> Acked-by: Philipp Tomsic
The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.
Signed-off-by: David Wu <david...@rock-chips.
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk3328.c | 20
incl
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/net/gmac_rockchip.c | 85 +
1 file changed, 85 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 22e3941..f24c347 1006
nt preview: If we include both the rk3288_grf.h and rv1108_grf.h, it will
cause the conflicts of redefinition. Clean the iomux definitions at
grf_rv1108.h,
and move them into pinctrl-driver. Signed-off-by: David Wu
<david...@rock-chips.com>
--- [...]
Content analysis details:
Set gmac pins iomux and rgmii tx pins to 12ma drive-strength,
clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 138 ++
1 file changed, 138 insertions(+)
diff
nt preview: Add basic dts configuration for rk3328 gmac2io. Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v2: - New patch [...]
Content analysis details: (5.7 points, 5.0 required)
pts rule name
Enable GMAC configs for evb-rk3328
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
configs/evb-rk3328_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 3b8b104..3d8c04d
nt preview: Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface. Signed-off-by:
David Wu <david...@rock-chips.com> Acked-by: Philipp Tomsich
<philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp
the grf offset at gmac_rockchip.c
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
David Wu (18):
rockchip: clk: Add mac clock set for rk3399
rockchip: dts: rk3399-evb: Change the tx/rx delay value
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2
and bit10 at com iomux register. After that, set rgmii m1 tx
pins to 12ma drive-strength, and clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/pinctrl/ro
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk322x.c | 13 +
1 file changed, 13 inse
nt preview: Clean the iomux definitions at grf_rk3328.h, and move them
into pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v2: - New patch [...]
Content analysis details: (6.5 points, 5.0 required)
nt preview: Clean the iomux definitions at grf_rk322x.h, and move them
into pinctrl-driver for resolving the compiling error of redefinition. After
that, define the uart2 iomux at rk322x-board file. Signed-off-by: David Wu
<david...@rock-chips.com> --- [...]
Content analysis detail
use defined symbolic constants for drive-strength
Changes in v2:
- Add check whether the set rgmii/rmii function is a valid function pointer
- Clean the grf offset at gmac_rockchip.c
- New patch
- None
- Use current phy interface to set mac clock rate
David Wu (20):
rockchip: dts:
If the Ethernet address is not set, the network can't work,
enable the random address config for default use.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobr
If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h,
and move them into pinctrl-driver.
Signed-off-by: David Wu <david...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-sy
Give the mac controller the correct tx-delay and rx-delay value
for the rgmii mode transmission. If they are not matched, there
would be Ethernet packets lost, the net feature may not work.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@
The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.
Signed-off-by: David Wu <david...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8
Clean the iomux definitions at grf_rk322x.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
After that, define the uart2 iomux at rk322x-board file.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Fix the wrong define for uart2
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add "set parent" for gmac
- Add internal mac clk div_sel for gmac
Changes in v2:
- New
Add basic dts configuration for rk3328 gmac2io.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/dts/rk3328.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/a
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add "set parent" for gmac2io
- Add internal mac clk div_sel for gmac2i
The GMAC2IO in the RK3328 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3328-specific logic necessary to reuse this driver.
Signed-off-by: David Wu <david...@r
Enable GMAC configs for evb-rk3328
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
configs/evb-rk3328_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
Set gmac pins iomux and rgmii tx pins to 12ma drive-strength,
clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- adhere to the established way of writing this to avoid future confusion
- use defined symbolic constants for drive-strength
Changes
to signal success.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- New patch
Changes in v2: None
drivers/clk/rockchip/clk_rk3288.c | 106 ++---
include/dt-bindings/clock/rk3288-cru.h | 1 +
2 files changed, 99 insertions(+), 8 del
The LCDC assigned rate is 0, it will make boot error,
error log:"pll_para_config: the frequency can not be
0 Hz". Remove them, and the lcdc driver will do the
correct clock rate setting.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- New patch
Changes in
Add gmac config support for rk3229 evb.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
configs/evb-rk3229_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_def
Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- New patch
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 7 ++
drivers/clk/rockchip/clk_rk
Add rk3328-evb gmac support.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/dts/rk3328-evb.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/
The GMAC in the RK3228 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3368-specific logic necessary to reuse this driver.
Signed-off-by: David Wu <david...@r
Clean the iomux definitions at grf_rk3328.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rk3328.h
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2
and bit10 at com iomux register. After that, set rgmii m1 tx
pins to 12ma drive-strength, and clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- adhere to the established way of w
The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.
Signed-off-by: David Wu <david...@rock-chips.
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/mach-rockchip/rk3288-board-spl.c | 79 ---
1 file changed, 79 del
The fdedesc is requested for new pinctrl driver, disable SPL_OF_PLATDATA
to make fdedesc be built in.
Signed-off-by: David Wu <david...@rock-chips.com>
---
configs/evb-rk3399_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_def
1 - 100 of 240 matches
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