To reduce the pinctrl driver, implement the mux/drive/pull/schmitt
func at per Soc.
David Wu (10):
pinctrl: rockchip: Add pull-pin-default param and remove unused param
pinctrl: rockchip: Remove redundant spaces
pinctrl: rockchip: Split the common set_mux() into per Soc
pinctrl
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu
---
Change in
Some Socs use the pull-pin-default config param, need to add it.
And input-enable/disable config params are not necessary, remove it.
Signed-off-by: David Wu
---
Change in v3:
- Add some commit message
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 3 +--
1 file changed, 1 insertion(+), 2
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu
---
Change in v3:
- Add some comment
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff
Some files have the redundant spaces, remove them.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 12 ++--
drivers/pinctrl/rockchip/pinctrl-rk3188.c | 12 ++--
drivers/pinctrl/rockchip/pinctrl-rk322x.c | 18
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk322x.c | 25 -
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 35 +--
drivers/pinctrl/rockchip/pinctrl-rk3328.c
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
corresponding bits, need to read before write the register.
Signed-off-by: David Wu
---
Change in v3:
- Add some comment
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 23 -
drivers/pinctrl/rockchip/pinctrl-rk3128.c | 23 -
drivers/pinctrl/rockchip/pinctrl-rk3188.c
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a
As the mux/pull/drive feature implement at own file,
the type and label are not necessary.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 2 --
drivers/pinctrl/rockchip/pinctrl-rk3128.c | 2 --
drivers/pinctrl/rockchip/pinctrl-rk3188.c
Only some Soc need Schmitter feature, so move the
implementation into their own files.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk3328.c | 17 -
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 19 +++
drivers/pinctrl
.
Thanks,
Philipp.
On 12.02.2019, at 12:55, Philipp Tomsich
<mailto:philipp.toms...@theobroma-systems.com>> wrote:
On 12.02.2019, at 12:51, David Wu <mailto:david...@rock-chips.com>> wrote:
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/
Hi Philipp,
This config does not look like it will be used in SPL and can be
deleted.
Reviewed-by: David Wu
在 2019/2/28 上午3:05, Heinrich Schuchardt 写道:
The SPL for the Tinker Board has to fit into 32 KiB. Currently this limit
is exceeded.
CONFIG_SPL_I2C_SUPPORT is not needed to move to main
To reduce the pinctrl driver, implement the mux/drive/pull/schmitt
func at per Soc.
David Wu (10):
pinctrl: rockchip: Add pull-pin-default param and remove unused param
pinctrl: rockchip: Remove redundant spaces
pinctrl: rockchip: Split the common set_mux() into per Soc
pinctrl
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl
Some Socs use the pull-pin-default config param, need to add it.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
b/drivers/pinctrl/rockchip
Some files have the redundant spaces, remove them.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 12 ++--
drivers/pinctrl/rockchip/pinctrl-rk3188.c | 12 ++--
drivers/pinctrl/rockchip/pinctrl-rk322x.c | 18 -
drivers/pinctrl/rockchip
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu
---
drive
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk322x.c | 25 -
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 35 +--
drivers/pinctrl/rockchip/pinctrl-rk3328.c | 26 -
drivers
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
corresponding bits, need to read before write the register.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 23 -
drivers/pinctrl/rockchip/pinctrl-rk3128.c | 23 -
drivers/pinctrl/rockchip/pinctrl-rk3188.c | 29 +-
drivers
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/rockchip
Only some Soc need Schmitter feature, so move the
implementation into their own files.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3328.c | 17 -
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 19 +++
drivers/pinctrl/rockchip/pinctrl
As the mux/pull/drive feature implement at own file,
the type and label are not necessary.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 2 --
drivers/pinctrl/rockchip/pinctrl-rk3128.c | 2 --
drivers/pinctrl/rockchip/pinctrl-rk3188.c | 2 --
drivers/pinctrl
Hi Philipp,
在 2019/4/4 下午3:19, Philipp Tomsich 写道:
On 04.04.2019, at 05:51, David Wu wrote:
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 8
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pull at rk3288, need to read the value from register
firstly. Add the flag to distinguish it from normal registers.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 17 ++--
.../pi
can’t
test or debug on the rk3288 due to a lack of hardware.
If you want to start digging, that the changes in
commit 08c817c39908f9d120df1e4c90ddad4a11fc3891
Author: David Wu
Date: Wed Jan 2 20:51:00 2019 +0800
ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
Hi Philipp,
在 2019/2/10 上午2:24, Philipp Tomsich 写道:
That said, I have been fighting issues from this patchset when trying to read
from devices on the i2c0 bus on a RK3399—which had me add a “simple”
pinctrl device again, as pulling all the dependencies into the SPL is a pain.
I think you can
Hi Philipp,
在 2019/2/12 下午9:54, Philipp Tomsich 写道:
On 12.02.2019, at 13:38, David Wu wrote:
Hi Philipp,
在 2019/2/10 上午2:24, Philipp Tomsich 写道:
That said, I have been fighting issues from this patchset when trying to read
from devices on the i2c0 bus on a RK3399—which had me add a
Hi Philipp,
在 2019/2/12 下午9:53, Philipp Tomsich 写道:
On 12.02.2019, at 13:38, David Wu wrote:
Hi Philipp,
在 2019/2/10 上午2:24, Philipp Tomsich 写道:
That said, I have been fighting issues from this patchset when trying to read
from devices on the i2c0 bus on a RK3399—which had me add a
在 2019/2/13 下午6:13, Philipp Tomsich 写道:
On 13.02.2019, at 11:10, David Wu wrote:
Hi Philipp,
在 2019/2/12 下午9:54, Philipp Tomsich 写道:
On 12.02.2019, at 13:38, David Wu wrote:
Hi Philipp,
在 2019/2/10 上午2:24, Philipp Tomsich 写道:
That said, I have been fighting issues from this patchset
Hi Philipp,
在 2019/2/13 下午6:30, Philipp Tomsich 写道:
The 10k comes from a direct comparison on our RK3399-Q7, after pulling in all
the required DTS nodes and properties vs. a minimal simple pinctrl for I2C only
(which is ~ 100 bytes of code).
So according to your mind, do not use DTS at the SPL
Hi philipp,
在 2019/2/13 下午6:47, Philipp Tomsich 写道:
On 13.02.2019, at 11:33, David Wu wrote:
在 2019/2/13 下午6:13, Philipp Tomsich 写道:
On 13.02.2019, at 11:10, David Wu wrote:
Hi Philipp,
在 2019/2/12 下午9:54, Philipp Tomsich 写道:
On 12.02.2019, at 13:38, David Wu wrote:
Hi Philipp,
在
Hi Henrich,
在 2019/2/16 下午5:53, Heinrich Schuchardt 写道:
On 2/13/19 11:56 AM, Philipp Tomsich wrote:
On 13.02.2019, at 11:52, David Wu wrote:
Hi philipp,
在 2019/2/13 下午6:47, Philipp Tomsich 写道:
On 13.02.2019, at 11:33, David Wu wrote:
在 2019/2/13 下午6:13, Philipp Tomsich 写道:
On
causes SPL not to start.
CONFIG_SYS_MALLOC_F_LEN=0x4000
does not solve the problem.
Best regards
Heinrich
Michael
On Sun., 17 Feb. 2019, 1:11 pm Heinrich Schuchardt mailto:xypron.g...@gmx.de> wrote:
On 2/17/19 9:19 AM, David Wu wrote:
> Hi Henrich,
>
> 在 2019
Hi Philipp,
在 2019/2/28 下午8:36, Philipp Tomsich 写道:
On 28.02.2019, at 11:50, Heiko Stübner <mailto:he...@sntech.de>> wrote:
Hi David,
Am Montag, 18. Februar 2019, 02:05:12 CET schrieb David Wu:
Hi Heinrich and Michael,
Another thing i see is that I missed a patch, for the 3288 g
:05:12 CET schrieb David Wu:
Hi Heinrich and Michael,
Another thing i see is that I missed a patch, for the 3288 gpio0, its
iomux is special, there is no high 16-bit write-enabled bit. For Tinker
board, it uses I2C0, the current driver will overwrite the I2C0 iomux,
while request the GPIO0A4. It
The new PWM driver supports PWM polarity, lock and more functions.
Signed-off-by: David Wu
---
arch/arm/include/asm/arch-rockchip/pwm.h | 17 ++-
drivers/pwm/rk_pwm.c | 139 +++
2 files changed, 131 insertions(+), 25 deletions(-)
diff --git a/arch/arm
The most pins of rk3308 are 2bits iomux, but the banks's register
width is 0x8.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3308.c | 464 ++
.../pinctrl/rockchip/pinctrl-rockchip-core.c
When we want to use plus iomux feature, we need to enable
them at spl.
Signed-off-by: David Wu
---
arch/arm/mach-rockchip/rk3308/rk3308.c | 33 ++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c
b/arch/arm/mach-rockchip/rk3308
Add the glue code to allow the rk3308 variant of the Rockchip gmac
to provide network functionality.
Signed-off-by: David Wu
---
drivers/net/gmac_rockchip.c | 65 +
1 file changed, 65 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net
The rk3308 only support RMII mode, and if it is output clock
mode, better to use ref_clk pin with drive strength 12ma.
Signed-off-by: David Wu
---
arch/arm/dts/rk3308.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308
The Firefly ROC_RK3308_CC use ref_clock of input mode,
and rmii pins of m1 group.
Signed-off-by: David Wu
---
arch/arm/dts/rk3308-roc-cc.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts
index e10aa638a3..b4a54a852c
Hi Kever,
在 2019/11/27 下午2:23, Kever Yang 写道:
David,
On 2019/11/26 上午9:39, David Wu wrote:
The rk3308 only support RMII mode, and if it is output clock
mode, better to use ref_clk pin with drive strength 12ma.
Signed-off-by: David Wu
Did you send this to kernel list at the same time?
I
,
configure duty, period and polarity at next same period, to
prevent the intermediate temporary state.
Signed-off-by: David Wu
---
Change in v2: None
- Remove RK3399 compatible
arch/arm/include/asm/arch-rockchip/pwm.h | 17 ++-
drivers/pwm/rk_pwm.c | 138
An iomux register contains 8 pins, each of which is represented
by 2 bits, but the register offset is 0x8.
For example, GRF_GPIO0A_IOMUX offset is 0x0, but GRF_GPIO0B_IOMUX
offset is 0x8, the offset 0x4 is reserved.
So add a type IOMUX_8WIDTH_2BIT to calculate offset.
Signed-off-by: David Wu
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