From: Kuo-Jung Su dant...@faraday-tech.com
With MMU/D-Cache enabled, data might be retained at cache
rather than at DRAM when we execute 'go' command, and some
of the bare-metal softwares would always invalidate the entire
data cache at start-up, and causes data lost issue.
This patch
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
drivers/mtd/spi/winbond.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index 2716209..2a27837 100644
From: Kuo-Jung Su dant...@faraday-tech.com
To: u-boot@lists.denx.de
CC: Albert Aribaud albert.u.b...@aribaud.net
These patches introduce Faraday A36x SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/ftgmac100.c | 70 +--
1 file changed, 49 insertions(+), 21 deletions(-)
diff --git a/drivers
From: Kuo-Jung Su dant...@faraday-tech.com
This patch updates the map_physmem()/unmap_physmem(), and use
them to implement dma_alloc_coherent(), dma_free_coherent().
It uses 1MB section for each mapping, and thus waste lots of
address space, however this should still be good enough for
tiny
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux.
However it has a weird DMA alignment issue:
(1) Tx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: O.K
(2) Rx DMA Buffer Address
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTI2C010 is a multi-function I2C controller
which supports both master and slave mode.
This patch simplily implements the master mode only.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Heiko Schocher h...@denx.de
---
drivers/i2c
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF.
This patch simpily implements the SPI mode only.
BTW the DMA and CS/Clock control logic has been
altered since revision 1.19.0. So this patch
would 1st detects
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTNANDC021 is a integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.
For example:
Issuing a command 0x10 to FTNANDC021 would result in
a page write + a read status operation
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTSDC010 is a MMC/SD host controller.
Although there is already a driver in current u-boot release,
which is modified from eSHDC and contributed by Andes Tech.
Its performance is too terrible on Faraday A36x SoC platforms,
so I turn to implement
From: Kuo-Jung Su dant...@faraday-tech.com
This patch add supports to both Faraday FUSBH200 and FOTG210,
these controllers slightly differ from standard EHCI specification.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Marek Vasut ma...@denx.de
---
common/usb_hub.c
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FOTG210 is an OTG chip which could operate
as either an EHCI Host or a USB Device as a time.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Marek Vasut ma...@denx.de
---
drivers/usb/gadget/Makefile |1 +
drivers/usb
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1
2013/4/26 Wolfgang Denk w...@denx.de:
Dear Kuo-Jung Su,
In message 1366963312-2901-1-git-send-email-dant...@gmail.com you wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
With MMU/D-Cache enabled, data might be retained at cache
rather than at DRAM when we execute 'go' command, and some
From: Kuo-Jung Su dant...@faraday-tech.com
With MMU/D-Cache enabled, data might be retained at d-cache
rather than at DRAM when we execute 'go' command, and some
of the bare-metal softwares would always invalidate the entire
data cache at start-up, and then leads to a data lost issue.
Furthermore
2013/4/26 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
This patch add supports to both Faraday FUSBH200 and FOTG210,
these controllers slightly differ from standard EHCI specification.
How do they differ?
1. The reserved registers (0x1C - 0x3F
2013/4/26 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FOTG210 is an OTG chip which could operate
as either an EHCI Host or a USB Device as a time.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Marek Vasut ma...@denx.de
2013/4/27 Scott Wood scottw...@freescale.com:
On 04/26/2013 03:02:36 AM, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTNANDC021 is a integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.
For example
2013/4/30 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/4/26 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
This patch add supports to both Faraday FUSBH200 and FOTG210,
these controllers slightly differ from standard EHCI specification
2013/4/30 Scott Wood scottw...@freescale.com:
On 04/28/2013 10:28:14 PM, Kuo-Jung Su wrote:
2013/4/27 Scott Wood scottw...@freescale.com:
Shouldn't .eccpos depend on HWECC?
Actually it means nothing here, the ECC function is designed to be some
kind of
a blackbox to users (i.e
2013/5/2 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/4/30 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/4/26 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
This patch add supports to both Faraday FUSBH200 and FOTG210
2013/5/3 Tom Rini tr...@ti.com:
On Fri, Apr 26, 2013 at 04:02:32PM +0800, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
[snip]
+ | (phyaddr PHYCR_ADDR_SHIFT)
+ | (phyreg PHYCR_REG_SHIFT)
+ | 0x3000;
Magic number.
It's the HW
2013/5/3 Tom Rini tr...@ti.com:
On Fri, Apr 26, 2013 at 04:02:29PM +0800, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
To: u-boot@lists.denx.de
CC: Albert Aribaud albert.u.b...@aribaud.net
These patches introduce Faraday A36x SoC platform support.
Here are some public
2013/5/4 Andy Fleming aflem...@gmail.com:
On Fri, Apr 26, 2013 at 3:02 AM, Kuo-Jung Su dant...@gmail.com wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTSDC010 is a MMC/SD host controller.
Although there is already a driver in current u-boot release,
which is modified from
From: Kuo-Jung Su dant...@faraday-tech.com
These patches introduce Faraday A36x SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
There is also a A369 QEMU emulator available at my github account:
https
From: Kuo-Jung Su dant...@faraday-tech.com
This patch updates the map_physmem()/unmap_physmem(), and use
them to implement dma_alloc_coherent(), dma_free_coherent().
It uses 1MB section for each mapping, and thus waste lots of
address space, however this should still be good enough for
tiny
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday A36x SoC platform support]
- Drop reset.c and get the reset_cpu
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday A36x SoC platform support]
Changes for v3:
- Coding Style cleanup
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday A36x SoC platform support]
Changes for v3:
- Coding Style cleanup
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday A36x SoC platform support]
Changes for v3:
- Coding Style cleanup
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday A36x SoC platform support]
Changes for v3:
- Coding Style cleanup
From: Kuo-Jung Su dant...@faraday-tech.com
This patch add supports to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI as
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
This patch add supports to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI as
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FOTG210 is an OTG chip which could operate
as either an EHCI Host or a USB Device as a time.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Marek Vasut ma...@denx.de
---
Changes for v4:
- Use only macro constants and named bit
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTI2C010 is a multi-function I2C controller
which supports both master and slave mode.
This patch simplily implements the master mode only.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Heiko Schocher h...@denx.de
---
Changes for v4
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTSDC010 is a MMC/SD host controller.
Although there is already a driver in current u-boot release,
which is modified from eSHDC and contributed by Andes Tech.
Its performance is too terrible on Faraday A36x SoC platforms,
so I turn to implement
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTNANDC021 is a integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.
For example:
Issuing a command 0x10 to FTNANDC021 would result in
a page write + a read status operation
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux.
However it has a weird DMA alignment issue:
(1) Tx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: O.K
(2) Rx DMA Buffer Address
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Joe Hershberger joe.hershber...@gmail.com
CC: Tom Rini tr...@ti.com
---
Changes for v4:
- Make it a separate patch, rather then a part of
Faraday A36x patch series
Changes for v3
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.
NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1
2013/5/7 Heiko Schocher h...@denx.de:
Hello Kuo-Jung,
Am 07.05.2013 08:32, schrieb Kuo-Jung Su:
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTI2C010 is a multi-function I2C controller
which supports both master and slave mode.
This patch simplily implements the master mode only
2013/5/8 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
This patch add supports to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI as
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2
2013/5/8 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FOTG210 is an OTG chip which could operate
as either an EHCI Host or a USB Device as a time.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Marek Vasut ma...@denx.de
2013/5/8 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
[...]
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -419,6 +419,14 @@ static int usb_hub_configure(struct usb_device
*dev)
portstatus = le16_to_cpu(portsts-wPortStatus
2013/5/8 Heiko Schocher h...@denx.de:
Hello Kuo-Jung,
Am 08.05.2013 03:51, schrieb Kuo-Jung Su:
2013/5/7 Heiko Schocher h...@denx.de:
Hello Kuo-Jung,
Am 07.05.2013 08:32, schrieb Kuo-Jung Su:
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTI2C010 is a multi-function I2C controller
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTI2C010 is a multi-function I2C controller
which supports both master and slave mode.
This patch simplily implements the master mode only.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Heiko Schocher h...@denx.de
---
Changes for v5
2013/5/9 Scott Wood scottw...@freescale.com:
On 05/07/2013 01:33:11 AM, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTNANDC021 is a integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.
For example
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTNANDC021 is a integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.
For example:
Issuing a command 0x10 to FTNANDC021 would result in
a page write + a read status operation
2013/5/8 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/5/8 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
[...]
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -419,6 +419,14 @@ static int usb_hub_configure(struct usb_device
*dev)
portstatus
From: Kuo-Jung Su dant...@faraday-tech.com
This patch adds support to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI are
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
This patch makes the minimum power-on delay for USB HUB
become configurable. The original design waits at least
100 msec here, but some EHCI controlers(e.g. Faraday EHCI)
are known to require much longer delay interval.
NOTE:
The minimal delay is still
From: Kuo-Jung Su dant...@faraday-tech.com
There is at least one non-EHCI compliant controller (i.e. Faraday EHCI)
known to implement a non-standard TDI stuff.
Futhermore, it not only leave reserved and CONFIGFLAG registers
un-implemented but also has their address spaces removed.
And thus, we
From: Kuo-Jung Su dant...@faraday-tech.com
This patch adds support to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI are
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FOTG210 is an OTG chip which could operate
as either an EHCI Host or a USB Device as a time.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Marek Vasut ma...@denx.de
---
Changes for v5:
- Coding Style cleanup.
- Drop postfix
2013/5/10 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
There is at least one non-EHCI compliant controller (i.e. Faraday EHCI)
known to implement a non-standard TDI stuff.
Futhermore, it not only leave reserved and CONFIGFLAG registers
un
2013/5/10 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
This patch makes the minimum power-on delay for USB HUB
become configurable. The original design waits at least
100 msec here, but some EHCI controlers(e.g. Faraday EHCI)
are known to require
From: Kuo-Jung Su dant...@faraday-tech.com
This patch adds support to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI are
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
This patch makes the minimum power-on delay for USB HUB
become configurable. The original design waits at least
100 msec here, but some EHCI controlers(e.g. Faraday EHCI)
are known to require much longer delay interval.
Signed-off-by: Kuo-Jung Su dant
From: Kuo-Jung Su dant...@faraday-tech.com
There is at least one non-EHCI compliant controller (i.e. Faraday EHCI)
known to implement a non-standard TDI stuff.
Futhermore, it not only leave reserved and CONFIGFLAG registers
un-implemented but also has their address spaces removed.
And thus, we
From: Kuo-Jung Su dant...@faraday-tech.com
This patch adds support to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI are
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FOTG210 is an OTG chip which could operate
as either an EHCI Host or a USB Device at a time.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Marek Vasut ma...@denx.de
---
Changes for v6:
- Nothing updates
Changes for v5
2013/5/13 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
There is at least one non-EHCI compliant controller (i.e. Faraday EHCI)
known to implement a non-standard TDI stuff.
Futhermore, it not only leave reserved and CONFIGFLAG registers
un
2013/5/13 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
This patch makes the minimum power-on delay for USB HUB
become configurable. The original design waits at least
100 msec here, but some EHCI controlers(e.g. Faraday EHCI)
are known to require
From: Kuo-Jung Su dant...@faraday-tech.com
This patch adds support to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI are
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
This patch makes the minimum power-on delay for USB HUB
become configurable. The original design waits at least
100 msec here, but some EHCI controlers(e.g. Faraday EHCI)
are known to require much longer delay interval.
Signed-off-by: Kuo-Jung Su dant
From: Kuo-Jung Su dant...@faraday-tech.com
There is at least one non-EHCI compliant controller (i.e. Faraday EHCI)
not only leave RESERVED and CONFIGFLAG registers un-implemented
but also has their address spaces removed.
As an result, the PORTSC register of Faraday EHCI always
starts from 0x30
From: Kuo-Jung Su dant...@faraday-tech.com
This patch adds support to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI are
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FOTG210 is an OTG chip which could operate
as either an EHCI Host or a USB Device at a time.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Marek Vasut ma...@denx.de
---
Changes for v7:
- Nothing updates
Changes for v6
2013/5/13 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/5/13 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
There is at least one non-EHCI compliant controller (i.e. Faraday EHCI)
known to implement a non-standard TDI stuff.
Futhermore
From: Kuo-Jung Su dant...@faraday-tech.com
This patch adds support to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI are
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
There is at least one non-EHCI compliant controller (i.e. Faraday EHCI)
not only leave RESERVED and CONFIGFLAG registers un-implemented
but also has their address spaces removed.
As an result, the PORTSC register of Faraday EHCI always
starts from 0x30
From: Kuo-Jung Su dant...@faraday-tech.com
This patch adds support to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI are
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
This patch makes the minimum power-on delay for USB HUB
become configurable. The original design waits at least
100 msec here, but some EHCI controlers(e.g. Faraday EHCI)
are known to require much longer delay interval.
Signed-off-by: Kuo-Jung Su dant
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FOTG210 is an OTG chip which could operate
as either an EHCI Host or a USB Device at a time.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Marek Vasut ma...@denx.de
---
Changes for v8:
- Nothing updates
Changes for v7
2013/5/14 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/5/13 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/5/13 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
There is at least one non-EHCI compliant controller (i.e. Faraday
2013/5/15 Kuo-Jung Su dant...@gmail.com:
2013/5/14 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/5/13 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/5/13 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
There is at least one
2013/5/15 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/5/15 Kuo-Jung Su dant...@gmail.com:
2013/5/14 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/5/13 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
2013/5/13 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From
From: Kuo-Jung Su dant...@faraday-tech.com
This patch adds support to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI are
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
1. The 'index' of ehci_submit_root() is not always 0.
e.g.
While it gets invoked from usb_get_descriptor(),
the 'index' is always a '0'. (See ch.9 of USB2.0)
2. The PORTSC register is not always required, and thus it
should only report
From: Kuo-Jung Su dant...@faraday-tech.com
There is at least one non-EHCI compliant controller (i.e. Faraday EHCI)
not only leave RESERVED and CONFIGFLAG registers un-implemented
but also has their address spaces removed.
As an result, the PORTSC register of Faraday EHCI always
starts from 0x30
From: Kuo-Jung Su dant...@faraday-tech.com
This patch adds support to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI are
listed bellow:
1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
also has its
From: Kuo-Jung Su dant...@faraday-tech.com
This patch makes the minimum power-on delay for USB HUB
become configurable. The original design waits at least
100 msec here, but some EHCI controlers(e.g. Faraday EHCI)
are known to require much longer delay interval.
Signed-off-by: Kuo-Jung Su dant
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FOTG210 is an OTG chip which could operate
as either an EHCI Host or a USB Device at a time.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Marek Vasut ma...@denx.de
---
Changes for v9:
- Nothing updates
Changes for v8
it invoked
in both bootm go?
It looks much pretty to me, and we don't even worry about the i-cache issues.
--
Best wishes,
Kuo-Jung Su
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2013/5/20 Marek Vasut ma...@denx.de:
Dear Kuo-Jung Su,
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FOTG210 is an OTG chip which could operate
as either an EHCI Host or a USB Device at a time.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Marek Vasut ma...@denx.de
for approval.
Here is the link to u-boot patchwork:
http://patchwork.ozlabs.org/patch/242006/
Thanks,
Jagan.
On Fri, Apr 26, 2013 at 1:32 PM, Kuo-Jung Su dant...@gmail.com wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
drivers/mtd/spi
2013/5/23 Jagan Teki jagannadh.t...@gmail.com:
Hi,
On Wed, May 22, 2013 at 6:31 AM, Kuo-Jung Su dant...@gmail.com wrote:
2013/5/22 Jagan Teki jagannadh.t...@gmail.com:
Hi,
I have a simple question like these parts are legacy flashes i guess.
Could you please tell me on which boards
2013/5/23 Jagan Teki jagannadh.t...@gmail.com:
On Thu, May 23, 2013 at 3:24 PM, Kuo-Jung Su dant...@gmail.com wrote:
2013/5/23 Jagan Teki jagannadh.t...@gmail.com:
Hi,
On Wed, May 22, 2013 at 6:31 AM, Kuo-Jung Su dant...@gmail.com wrote:
2013/5/22 Jagan Teki jagannadh.t...@gmail.com:
Hi
From: Kuo-Jung Su dant...@faraday-tech.com
Add support for Winbond's W25PXX SPI flash.
These devices is used on Faraday A369 evaluation board.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Jagan Teki jagannadh.t...@gmail.com
CC: Tom Rini tr...@ti.com
---
Changes for v2:
- Update
toolchain, so I didn't run the compiling test
for NDS32 platforms.
Cc: Kuo-Jung Su dant...@faraday-tech.com
Cc: Macpaul Lin macp...@andestech.com
Signed-off-by: Gabor Juhos juh...@openwrt.org
---
drivers/mmc/ftsdc010_mci.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
2013/6/11 Albert ARIBAUD albert.u.b...@aribaud.net:
Hi Kuo-Jung,
On Tue, 7 May 2013 14:25:12 +0800, Kuo-Jung Su dant...@gmail.com
wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
2013/6/11 Albert ARIBAUD albert.u.b...@aribaud.net:
Hi Kuo-Jung,
On Tue, 7 May 2013 14:25:13 +0800, Kuo-Jung Su dant...@gmail.com
wrote:
arch/arm/cpu/faraday/a360/Makefile| 49 +
arch/arm/cpu/faraday/a369/Makefile| 50 +
arch/arm/cpu/faraday/a369/cmd_fa606.c
2013/6/11 Albert ARIBAUD albert.u.b...@aribaud.net:
Hi Kuo-Jung,
On Tue, 7 May 2013 14:25:08 +0800, Kuo-Jung Su dant...@gmail.com
wrote:
diff --git a/arch/arm/include/asm/mach-types.h
b/arch/arm/include/asm/mach-types.h
index 440b041..a103922 100644
--- a/arch/arm/include/asm/mach
2013/6/11 Albert ARIBAUD albert.u.b...@aribaud.net:
Hi Kuo-Jung,
On Tue, 7 May 2013 14:25:07 +0800, Kuo-Jung Su dant...@gmail.com
wrote:
diff --git a/arch/arm/include/asm/dma-mapping.h
b/arch/arm/include/asm/dma-mapping.h
index 5bbb0a0..5a13af5 100644
--- a/arch/arm/include/asm/dma
2013/6/11 Albert ARIBAUD albert.u.b...@aribaud.net:
Hi Kuo-Jung,
On Tue, 11 Jun 2013 11:09:57 +0800, Kuo-Jung Su dant...@gmail.com
wrote:
2013/6/11 Albert ARIBAUD albert.u.b...@aribaud.net:
Hi Kuo-Jung,
On Tue, 7 May 2013 14:25:07 +0800, Kuo-Jung Su dant...@gmail.com
wrote:
diff
2013/6/13 Jagan Teki jagannadh.t...@gmail.com:
Hi,
Few comments, please get back your inputs.
Use commit header as spi: ftssp010_spi:
Got it, thanks
On 07-05-2013 12:04, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
The Faraday FTSSP010 is a multi-function controller
From: Kuo-Jung Su dant...@faraday-tech.com
These patches introduce Faraday A36x SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
There is also a A369 QEMU emulator available at my github account:
https
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux.
However it has a weird DMA alignment issue:
(1) Tx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: O.K
(2) Rx DMA Buffer Address
From: Kuo-Jung Su dant...@faraday-tech.com
Even though the MMU/D-cache is off, some DMA engines still
expect strict address alignment.
For example, the incoming Faraday FTMAC110 FTGMAC100 ethernet
controllers expect the tx/rx descriptors should always be aligned
to 16-bytes boundary.
Signed
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