[PATCH] net: phy: xilinx-gmii2rgmii: Removed hardcoded phy address 0 for bridge

Current code expects bridge phy address at 0 which is not correct expectation because bridge phy address is configurable. That's why update the code to read reg property to figure it out where bridge is and use it in phy creation code. Signed-off-by: Michal Simek Signed-off-by: Tejas Bhumkar

[PATCH] arm64: zynqmp: Disable Tri-state for MIO38 Pin

7a3 0540 Tri-state enable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7e3 0540 Signed-off-by: Tejas Bhumkar --- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 25 + arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 25 + 2 files changed, 50 insertions(+)

[PATCH] efi_loader : Suppress error print message

Signed-off-by: Tejas Bhumkar --- lib/efi_loader/efi_memory.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index edfad2d95a..821fe7616e 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -71

[PATCH] mtd: spi-nor: Add NO_CHIP_ERASE flag

Since the opcode SPINOR_OP_CHIP_ERASE (0xc7) is not supported for the mt35xu02g flash, the NO_CHIP_ERASE flag has been added to enable sector erase functionality instead. Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH] mtd: spi-nor: Add support for Macronix flash part

Added support for Macronix OSPI flash parts MX25UM51345G and MX66UM2G45G, with initial testing conducted on the Tenzing-se1 board using STR mode for basic erase, write, and readback operations. Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions

[PATCH] mtd: spi-nor: ids: Add is25lx512 chip

Added support for the ISSI OSPI flash part IS25LX512M. Initial testing was performed on the Tenzing-se1 board using SDR mode, covering basic erase, write, and readback operations. Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

[PATCH] xilinx: Enable the NFS command by default

Enabled the default utilization of the NFS command across all Xilinx platforms to facilitate the booting of images through the network using the NFS protocol. Signed-off-by: Tejas Bhumkar --- configs/xilinx_versal_net_virt_defconfig | 2 ++ configs/xilinx_versal_virt_defconfig | 2

[PATCH v2] xilinx: Enable the NFS command by default

Enabled the default utilization of the NFS command across all Xilinx platforms to facilitate the booting of images through the network using the NFS protocol. Fixes: 10de12570799 ("disable NFS support by default") Signed-off-by: Tejas Bhumkar --- Changes in v2: - Updated comm

[PATCH] cmd: net: nfs: Enable the NFS command by default

Activated the default use of NFS command for booting images via network using the NFS protocol. Signed-off-by: Tejas Bhumkar --- cmd/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index df6d71c103..a51b2d532f 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig

[PATCH 01/30] mtd: spi-nor: Add config to enable flash DTR

. Signed-off-by: T Karthik Reddy Co-developed-by: Tejas Bhumkar Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/Kconfig| 7 +++ drivers/mtd/spi/spi-nor-core.c | 12 +--- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi

[PATCH 00/30] Fix issues with QSPI and OSPI compare failures

mode in cadence qspi driver spi: cadence-qspi: Switch SDR/DTR using SPI_FLASH_DTR_ENABLE config spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal driver spi: cadence_qspi: Add spi mem dtr support ops mtd: spi-nor: Add block protection support for micron flashes Tejas

[PATCH 02/30] mtd: spi-nor-core: Set dummy buswidth equal to data buswidth

-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 473d9f41f3..8949dab548 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drive

[PATCH 05/30] mtd: spi-nor: Add support for cross die read in dual flash configuration

of bytes. Extend support for cross-die reads in flash memory devices that contain multiple dies within them. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 61 ++ include/spi.h

[PATCH 07/30] spi: mtd: Use split reads if multi-die flag is set

nfig and related code from the zynq and zynqmp qspi drivers as it is redundant. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi-nor-core.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/dri

[PATCH 03/30] arm64: versal: Enable defconfig for Micron octal flashes

The Micron MT35 series octal flashes can be activated through the configuration option CONFIG_SPI_FLASH_MT35XU. To ensure their detection, enable this option in the default defconfig for octal flashes. Signed-off-by: Tejas Bhumkar --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed

[PATCH 04/30] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes

led and SPI_NOR_OCTAL_DTR_READ flag is set in id table. Additionally, a new flag, "SPI_XFER_SET_DDR," has been introduced to instruct the Ospi controller driver to switch to DDR mode. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 8 +++-

[PATCH 06/30] mtd: spi-nor: Enable DTR octal flash program

From: Ashok Reddy Soma Define a flag SPI_NOR_OCTAL_DTR_PP and if enabled in spi-nor-ids table, enable octal DTR page program in the framework. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi-nor-core.c | 3 ++- 2

[PATCH 10/30] mtd: spi-nor: program quad enable bit for winbond flashes

than the Configuration Register (CR). Signed-off-by: T Karthik Reddy Co-developed-by: Tejas Bhumkar Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 48 ++ include/linux/mtd/spi-nor.h| 2 ++ 2 files changed, 50 insertions(+) diff --git

[PATCH 08/30] mtd: spi-nor: Update block protection flags for flash parts

and mt35xu02g have been incorporated into the CONFIG_SPI_FLASH_MT35XU configuration, so that in driver mt35xu512aba_fixups will be applied. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-ids.c | 34 -- 1 file changed, 20

[PATCH 09/30] mtd: spi-nor-ids: Add support for W25Q02NW

From: Algapally Santosh Sagar Add support for Winbond 256MB flash W25Q02NW which supports 4byte opcodes and also dual and quad read. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-ids.c | 6 ++ 1 file

[PATCH 14/30] spi: cadence_qspi: Setup ddr mode in cadence qspi driver

-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_ospi_versal.c | 25 +++ drivers/spi/cadence_qspi.c| 321 +- drivers/spi/cadence_qspi.h| 52 + drivers/spi/cadence_qspi_apb.c| 33 ++- 4 files changed, 416 inserti

[PATCH 15/30] spi: cadence-qspi: Switch SDR/DTR using SPI_FLASH_DTR_ENABLE config

directly using register writes. The configuration of the chip select in the Cadence QSPI driver is now determined based on the flags received from SPI-NOR framework. Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_ospi_versal.c | 29 + drivers/spi

[PATCH 13/30] mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP is enabled

Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 43435e79cc..ccda722df5 100644 --- a/drivers/mtd/spi/spi-

[PATCH 12/30] mtd: spi-nor: Update erase operation function

the flag for the relevant flash. Consequently, the argument for the spi_nor_erase_sector function has been modified from addr to offset. Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor

[PATCH 11/30] mtd: spi-nor: Send write disable cmd after every write enable

of the places in the driver, add it to clear write enable latch. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar Acked-by: Amit Kumar Mahapatra --- drivers/mtd/spi/spi-nor-core.c | 47 +- 1 file changed, 41 insertions(+), 6 deletions(-) diff --git

[PATCH 18/30] spi: cadence_qspi: Set tshsl_ns to at least one sclk_ns

-asserted within one SCLK period. That is why tshsl_ns delay should be at least one sclk_ns value. If it is less than sclk_ns, set it equal to sclk_ns. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi_apb.c | 4 1 file changed, 4 insertions(+) diff

[PATCH 16/30] spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal driver

r places. Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_ospi_versal.c | 23 +++ 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 243de6efaf..9db19

[PATCH 17/30] spi: cadence_qspi: Fix versal ospi indirect write timed out issue

readl_poll_timeout function to poll for Indirect Operation Complete bit gets set. Here not enabling IRQ coming to GIC, only IRQ from IP itself is able to poll bits. It is observed that the Indirect Operation Complete bit is getting set at an average time of 0.172 usec. Signed-off-by: Tejas Bhumkar

[PATCH 19/30] spi: cadence_qspi: Clean up registers in init

-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi_apb.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 0bb46f6ac2..5fc5279061 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi

[PATCH 20/30] spi: cadence_qspi: Initialize read and write watermark registers

. Write watermark indicates the maximum fill level of SRAM when write is performed to device. These values of 1/2 for read and 1/8 for write are chosen similar to Linux driver. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi_apb.c | 8 1 file

[PATCH 21/30] spi: cadence_qspi: Enable ECO bit for higher frequencies

From: Ashok Reddy Soma Enable ECO bit for Versal for frequencies above 120Mhz for octal spi to work properly. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 4 2 files changed, 5 insertions(+) diff

[PATCH 29/30] mtd: spi-nor: Add support for locking on GIGADEVICE nor flashes

-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 309 + include/linux/mtd/spi-nor.h| 2 + 2 files changed, 311 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c i

[PATCH 25/30] arm64: versal: Enable octal DTR mode

, signaling that the controller does not support DTR. Signed-off-by: Tejas Bhumkar --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index ee247b905f..69835fce55 100644

[PATCH 28/30] mtd: spi-nor: Add support for locking on ISSI nor flashes

Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/sf_internal.h | 6 + drivers/mtd/spi/spi-nor-core.c | 340 + include/linux/mtd/spi-nor.h| 7 + 3 files changed, 353 insertions(+) diff --git a/drivers/mtd/spi/sf_internal.h

[PATCH 27/30] mtd: spi-nor: Add support for locking on Macronix nor flashes

in the same way. Used bottom protect to test the locking and unlocking functionality on the zc1751+dc1 board. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 259 + include/linux/mtd/spi-nor.h| 3 + 2

[PATCH 30/30] mtd: spi-nor: Add support for locking on Spansion nor flashes

of that, reading the configuration register uses a different opcode (0x15) than the existing SPINOR_OP_RDCR (0x35). Used bottom protect to test s25fl512s flash part lock/unlock on zc1751+dc1 board. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c

[PATCH 26/30] mtd: spi-nor: Add block protection support for micron flashes

-off-by: Ashok Reddy Soma Signed-off-by: T Karthik Reddy Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 255 + include/linux/mtd/spi-nor.h| 7 + 2 files changed, 262 insertions(+) diff --git a/drivers

[PATCH 24/30] arm64: versal: Enable soft reset support for xspi flashes

Activate the xSPI Software Reset support, which will be utilized to transition from octal DTR mode to legacy mode during shutdown and boot (if enabled). Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- configs/xilinx_versal_virt_defconfig | 2 ++ 1 file changed, 2 insertions

[PATCH 23/30] spi: cadence_qspi: Write aligned byte length to ahbbase

From: Ashok Reddy Soma Incase of non-aligned length of flash data, ahbbase address is written directly with byte count. This is causing AHB bus error's sometimes and resulting in kernel crash while booting linux. To avoid this write 4 byte aligned byte count to ahbbase address. Also use a

[PATCH 22/30] spi: cadence_qspi: Add spi mem dtr support ops

protocol. Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 710c4a532d..282028c845 100644 --- a/drivers

[PATCH v2 01/30] mtd: spi-nor: Add config to enable flash DTR

. Signed-off-by: T Karthik Reddy Co-developed-by: Tejas Bhumkar Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/Kconfig| 7 +++ drivers/mtd/spi/spi-nor-core.c | 12 +--- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi

[PATCH v2 02/30] mtd: spi-nor-core: Set dummy buswidth equal to data buswidth

-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 473d9f41f3..8949dab548 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drive

[PATCH v2 11/30] mtd: spi-nor: Send write disable cmd after every write enable

of the places in the driver, add it to clear write enable latch. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar Acked-by: Amit Kumar Mahapatra --- drivers/mtd/spi/spi-nor-core.c | 47 +- 1 file changed, 41 insertions(+), 6 deletions(-) diff --git

[PATCH v2 08/30] mtd: spi-nor: Update block protection flags for flash parts

and mt35xu02g have been incorporated into the CONFIG_SPI_FLASH_MT35XU configuration, so that in driver mt35xu512aba_fixups will be applied. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-ids.c | 28 1 file changed, 16

[PATCH v2 10/30] mtd: spi-nor: program quad enable bit for winbond flashes

than the Configuration Register (CR). Signed-off-by: T Karthik Reddy Co-developed-by: Tejas Bhumkar Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 48 ++ include/linux/mtd/spi-nor.h| 2 ++ 2 files changed, 50 insertions(+) diff --git

[PATCH v2 15/30] spi: cadence-qspi: Switch SDR/DTR using SPI_FLASH_DTR_ENABLE config

directly using register writes. The configuration of the chip select in the Cadence QSPI driver is now determined based on the flags received from SPI-NOR framework. Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_ospi_versal.c | 29 + drivers/spi

[PATCH v2 13/30] mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP is enabled

Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 43435e79cc..ccda722df5 100644 --- a/drivers/mtd/spi/spi-

[PATCH v2 12/30] mtd: spi-nor: Update erase operation function

the flag for the relevant flash. Consequently, the argument for the spi_nor_erase_sector function has been modified from addr to offset. Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor

[PATCH v2 21/30] spi: cadence_qspi: Enable ECO bit for higher frequencies

From: Ashok Reddy Soma Enable ECO bit for Versal for frequencies above 120Mhz for octal spi to work properly. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 4 2 files changed, 5 insertions(+) diff

[PATCH v2 22/30] spi: cadence_qspi: Add spi mem dtr support ops

protocol. Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 710c4a532d..282028c845 100644 --- a/drivers

[PATCH v2 23/30] spi: cadence_qspi: Write aligned byte length to ahbbase

a temporary variable with 0x data and overwrite this temp with unaligned bytes data before writing to ahbbase. The value 0x is chosen as this is flash memory, worst case we will write 0xff to any location which doesn't effect any bits. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas

[PATCH v2 26/30] mtd: spi-nor: Add block protection support for micron flashes

-off-by: Ashok Reddy Soma Signed-off-by: T Karthik Reddy Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 255 + include/linux/mtd/spi-nor.h| 7 + 2 files changed, 262 insertions(+) diff --git a/drivers

[PATCH v2 25/30] arm64: versal: Enable octal DTR mode

, signaling that the controller does not support DTR. Signed-off-by: Tejas Bhumkar --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index ee247b905f..69835fce55 100644

[PATCH v2 24/30] arm64: versal: Enable soft reset support for xspi flashes

Activate the xSPI Software Reset support, which will be utilized to transition from octal DTR mode to legacy mode during shutdown and boot (if enabled). Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- configs/xilinx_versal_virt_defconfig | 2 ++ 1 file changed, 2 insertions

[PATCH v2 09/30] mtd: spi-nor-ids: Add support for W25Q02NW

From: Algapally Santosh Sagar Add support for Winbond 256MB flash W25Q02NW which supports 4byte opcodes and also dual and quad read. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-ids.c | 6 ++ 1 file

[PATCH v2 06/30] mtd: spi-nor: Enable DTR octal flash program

From: Ashok Reddy Soma Define a flag SPI_NOR_OCTAL_DTR_PP and if enabled in spi-nor-ids table, enable octal DTR page program in the framework. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi-nor-core.c | 3 ++- 2

[PATCH v2 05/30] mtd: spi-nor: Add support for cross die read in dual flash configuration

of bytes. Extend support for cross-die reads in flash memory devices that contain multiple dies within them. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 61 ++ include/spi.h

[PATCH v2 00/30] Fix issues with QSPI and OSPI compare failures

driver spi: cadence_qspi: Add spi mem dtr support ops mtd: spi-nor: Add block protection support for micron flashes Tejas Bhumkar (5): arm64: versal: Enable defconfig for Micron octal flashes mtd: spi-nor: Update erase operation function spi: cadence_qspi: Fix versal ospi indirect write timed

[PATCH v2 04/30] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes

led and SPI_NOR_OCTAL_DTR_READ flag is set in id table. Additionally, a new flag, "SPI_XFER_SET_DDR," has been introduced to instruct the Ospi controller driver to switch to DDR mode. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 8 +++-

[PATCH v2 07/30] spi: mtd: Use split reads if multi-die flag is set

nfig and related code from the zynq and zynqmp qspi drivers as it is redundant. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi-nor-core.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/dri

[PATCH v2 03/30] arm64: versal: Enable defconfig for Micron octal flashes

The Micron MT35 series octal flashes can be activated through the configuration option CONFIG_SPI_FLASH_MT35XU. To ensure their detection, enable this option in the default defconfig for octal flashes. Signed-off-by: Tejas Bhumkar --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed

[PATCH v2 14/30] spi: cadence_qspi: Setup ddr mode in cadence qspi driver

-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_ospi_versal.c | 25 +++ drivers/spi/cadence_qspi.c| 321 +- drivers/spi/cadence_qspi.h| 52 + drivers/spi/cadence_qspi_apb.c| 33 ++- 4 files changed, 416 inserti

[PATCH v2 19/30] spi: cadence_qspi: Clean up registers in init

-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi_apb.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 0bb46f6ac2..5fc5279061 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi

[PATCH v2 20/30] spi: cadence_qspi: Initialize read and write watermark registers

. Write watermark indicates the maximum fill level of SRAM when write is performed to device. These values of 1/2 for read and 1/8 for write are chosen similar to Linux driver. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi_apb.c | 8 1 file

[PATCH v2 17/30] spi: cadence_qspi: Fix versal ospi indirect write timed out issue

readl_poll_timeout function to poll for Indirect Operation Complete bit gets set. Here not enabling IRQ coming to GIC, only IRQ from IP itself is able to poll bits. It is observed that the Indirect Operation Complete bit is getting set at an average time of 0.172 usec. Signed-off-by: Tejas Bhumkar

[PATCH v2 18/30] spi: cadence_qspi: Set tshsl_ns to at least one sclk_ns

-asserted within one SCLK period. That is why tshsl_ns delay should be at least one sclk_ns value. If it is less than sclk_ns, set it equal to sclk_ns. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi_apb.c | 4 1 file changed, 4 insertions(+) diff

[PATCH v2 16/30] spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal driver

r places. Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_ospi_versal.c | 23 +++ 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 243de6efaf..9db19

[PATCH v2 27/30] mtd: spi-nor: Add support for locking on Macronix nor flashes

in the same way. Used bottom protect to test the locking and unlocking functionality on the zc1751+dc1 board. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 259 + include/linux/mtd/spi-nor.h| 3 + 2

[PATCH v2 28/30] mtd: spi-nor: Add support for locking on ISSI nor flashes

Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/sf_internal.h | 6 + drivers/mtd/spi/spi-nor-core.c | 340 + include/linux/mtd/spi-nor.h| 7 + 3 files changed, 353 insertions(+) diff --git a/drivers/mtd/spi/sf_internal.h

[PATCH v2 30/30] mtd: spi-nor: Add support for locking on Spansion nor flashes

of that, reading the configuration register uses a different opcode (0x15) than the existing SPINOR_OP_RDCR (0x35). Used bottom protect to test s25fl512s flash part lock/unlock on zc1751+dc1 board. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c

[PATCH v2 29/30] mtd: spi-nor: Add support for locking on GIGADEVICE nor flashes

-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 309 + include/linux/mtd/spi-nor.h| 2 + 2 files changed, 311 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c i

[PATCH v2] spi: cadence_qspi: Address the comparison failure for 0-8 bytes of data

el.org/all/cover.1701853668.git.tejas.arvind.bhum...@amd.com/ Signed-off-by: Tejas Bhumkar --- Changes in v2: - Resolve the duplication in the usage of the macro definition. drivers/spi/cadence_ospi_versal.c | 3 --- drivers/spi/cadence_qspi.h| 4 drivers/spi/cadence_qspi_ap

[PATCH] spi: cadence_qspi: Address the comparison failure for 0-8 bytes of data

quot; flag and attempting to read less than 8 bytes in STIG mode results in a read failure, leading to a compare test failure. To resolve this issue, the CMD_4BYTE_FAST_READ opcode is now utilized instead of CMD_4BYTE_OCTAL_READ, specifically in SDR mode. Signed-off-by: Tejas Bhumkar --- drivers/spi/cade

[PATCH RFC] spi: cadence_qspi: Address the comparison failure for 0-8

n achieves this, it still results in a compare test failure. Therefore, the code has been revised to include DMA read for operations involving less than 8 bytes as well. Fixes: 53f4ef0 ("spi: cadence_qspi: use STIG mode for small reads") Signed-off-by: Tejas Bhumkar --- drivers/spi/cade

[PATCH] arm64: zynqmp: Disable Tri-state for SDIO

ard did not respond to voltage select! : -110 To address this problem, configure the SDIO pins for output-enable to enable MMC detection. Signed-off-by: Michal Simek Signed-off-by: Tejas Bhumkar --- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 1 + arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 1 + 2 fi

[PATCH] arm64: zynqmp: Disable Tri-state for SDIO

ard did not respond to voltage select! : -110 To address this problem, configure the SDIO pins for output-enable to enable MMC detection. Signed-off-by: Michal Simek Signed-off-by: Tejas Bhumkar --- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 1 + arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 1 + 2 fi

[PATCH] configs: zynqmp_kria: Deactivate CONFIG_SPI_FLASH_BAR

Disable CONFIG_SPI_FLASH_BAR, which activates 4-byte opcodes. Signed-off-by: Tejas Bhumkar --- configs/xilinx_zynqmp_kria_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 7cb8b62d32..7af8b27be9 100644

[PATCH] mtd: spi-nor: Disable chip erase for n25q512ax3 flash

Chip erase not functioning for n25q512ax3 flash so enabled sector erase instead. Tested on: zc1751-dc1 board Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi

[PATCH 01/19] spi: cadence_qspi: Add support for DDR PHY mode

. Moreover, support has been extended to enable DDR mode for Micron flash. In the spi_nor_micron_octal_dtr_enable function, the cmd->buf is utilized to read the flash ID during RX DLL tuning. Signed-off-by: Ashok Reddy Soma Signed-off-by: T Karthik Reddy Co-developed-by: Tejas Bhumkar Signed-

[PATCH 02/19] spi: cadence-qspi: reset the ospi controller

in the Cadence QSPI driver is now determined based on the flags received from the SPI-NOR framework. Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_ospi_versal.c | 29 ++ drivers/spi/cadence_qspi.c| 63 --- drivers/spi

[PATCH 03/19] spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal driver

r places. Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_ospi_versal.c | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 30abb7b431..2c5bdd5f2

[PATCH 00/19] Add support for DDR PHY mode

: cadence_qspi: Add support for DDR PHY mode spi: cadence-qspi: reset the ospi controller spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal driver spi: cadence_qspi: Add spi mem dtr support ops spi: mtd: Use split reads if multi-die flag is set Tejas Bhumkar (6): arm64: versal

[PATCH 04/19] spi: cadence_qspi: Write aligned byte length to ahbbase

a temporary variable with 0x data and overwrite this temp with unaligned bytes data before writing to ahbbase. The value 0x is chosen as this is flash memory, worst case we will write 0xff to any location which doesn't effect any bits. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas

[PATCH 09/19] mtd: spi-nor: Update block protection flags for flash parts

and mt35xu02g have been incorporated into the CONFIG_SPI_FLASH_MT35XU configuration, so that in driver mt35xu512aba_fixups will be applied. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-ids.c | 28 1 file changed, 16

[PATCH 07/19] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes

led and SPI_NOR_OCTAL_DTR_READ flag is set in id table. Additionally, a new flag, "SPI_XFER_SET_DDR," has been introduced to instruct the Ospi controller driver to switch to DDR mode. Signed-off-by: Ashok Reddy Soma Co-developed-by: Tejas Bhumkar Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-n

[PATCH 08/19] arm64: versal: Enable defconfig for Micron octal flashes

The Micron MT35 series octal flashes can be activated through the configuration option CONFIG_SPI_FLASH_MT35XU. To ensure their detection, enable this option in the default defconfig for octal flashes. Signed-off-by: Tejas Bhumkar --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed

[PATCH 05/19] spi: cadence_qspi: Clean up registers in init

-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi_apb.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 7576dacfb0..35a21a2727 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi

[PATCH 06/19] spi: cadence_qspi: Initialize read and write watermark registers

. Write watermark indicates the maximum fill level of SRAM when write is performed to device. These values of 1/2 for read and 1/8 for write are chosen similar to Linux driver. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi_apb.c | 8 1 file

[PATCH 14/19] mtd: spi-nor: Enable DTR octal flash program

From: Ashok Reddy Soma Define a flag SPI_NOR_OCTAL_DTR_PP and if enabled in spi-nor-ids table, enable octal DTR page program in the framework. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi-nor-core.c | 7 +-- 2

[PATCH 10/19] mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP is enabled

Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e8640cbf07..b9326d2b47 100644 --- a/drivers/mtd/spi/spi-

[PATCH 13/19] mtd: spi-nor: Add support for cross die read in dual flash configuration

of bytes. Extend support for cross-die reads in flash memory devices that contain multiple dies within them. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 42 ++ include/spi.h

[PATCH 12/19] mtd: spi-nor: Update erase operation function

the flag for the relevant flash. Consequently, the argument for the spi_nor_erase_sector function has been modified from addr to offset. Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor

[PATCH 11/19] spi: cadence_qspi: Add spi mem dtr support ops

protocol. Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index d312bafd90..f1c8efe59c 100644 --- a/drivers

[PATCH 17/19] mtd: spi-nor: Enable DDR mode functionality with ISSI flash

Enable the utilization of mt35xu512aba_fixups for ISSI octal flash to operate in DDR mode. Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 10 +- drivers/mtd/spi/spi-nor-ids.c | 4 ++-- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi

[PATCH 19/19] mtd: spi-nor: Enable DDR mode functionality with Macronix flash

Added SFDP fixups for Macronix octal flash, with the requirement of the Invert Dual-byte opcode in Octal DDR mode. Reference: linux-xlnx@08cf794 Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 49 +- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 2

[PATCH 16/19] arm64: versal: Enable soft reset support for xspi flashes

Activate the xSPI Software Reset support, which will be utilized to transition from octal DTR mode to legacy mode during shutdown and boot (if enabled). Signed-off-by: T Karthik Reddy Signed-off-by: Tejas Bhumkar --- configs/xilinx_versal_virt_defconfig | 2 ++ 1 file changed, 2 insertions

[PATCH 18/19] mtd: spi-nor: Enable DDR mode functionality with Gigadevice flash

Enable the utilization of mt35xu512aba_fixups for GIGADEVICE octal flash to operate in DDR mode. Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 9 - drivers/mtd/spi/spi-nor-ids.c | 2 +- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi

[PATCH 15/19] spi: mtd: Use split reads if multi-die flag is set

nfig and related code from the zynq and zynqmp qspi drivers as it is redundant. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi-nor-core.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/dri

[PATCH] mtd: spi-nor: Add support to exit 4-byte mode

a nor read. Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f86003ca8c..47f65a4f5e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi

[PATCH v2] configs: zynqmp_kria: Deactivate CONFIG_SPI_FLASH_BAR

. However, there's no code or reset lines connected to the flash that could return it to 3B mode. To resolve this issue, changes were made to disable CONFIG_SPI_FLASH_BAR, which activates 4-byte opcodes. Signed-off-by: Tejas Bhumkar --- Changes in v2: Updated commit message. configs

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