+ Ashish,
On 02/04/19 6:22 AM, Marek Vasut wrote:
> Replace the ad-hoc erase operation implementation with a simple spi_mem_op
> implementation of the same functionality. This is a minor optimization and
> removal of the ad-hoc code.
>
> This however also changes the behavior of the execution of
Ashish,
>
> Hi Vignesh,
> This is working now(READ, WRITE), after some change in fsl_qspi driver, where
> I check for 4byte op codes now.
> But now I see that erase is getting address as ZERO. Which in my opinion is
> because
> spi_nor_erase_sector() call write_reg which has
On 26/03/19 10:36 AM, Ashish Kumar wrote:
> Hello Maintainers,
>
>
>
> With latest commit I see that saveenv command corrupts QSPI-flash,
> meaning if I read QSPI-flash at 0x0 offset RCW(reset configuration word)
> is erased after saveenv command was executed.
>
> This is tested on
On 28/03/19 3:37 PM, Ashish Kumar wrote:
>> -Original Message-
>> From: Vignesh Raghavendra
>> Sent: Wednesday, March 27, 2019 9:44 AM
>> To: Ashish Kumar ; Jagan Teki
>> ; u-boot@lists.denx.de; Tom Rini
>>
>> Cc: Kuldeep Singh
>> Subj
This series adds a Kconfig to disable cache maintenance operations on
a coherent architectures. And disable cache flush/invalidate ops for
SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent)
Vignesh Raghavendra (2):
arch: armv8: Provide a way to disable cache maintenance ops
of same Kconfig across different
architecture, I have added the symbol to top level arch/Kconfig file.
Patch currently disables cache maintenance ops for arm64 only.
Signed-off-by: Vignesh Raghavendra
---
Changes since RFC:
Rename config option to SYS_DISABLE_DCACHE_OPS
arch/Kconfig
AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.
Signed-off-by: Vignesh Raghavendra
---
Changes since RFC:
Rename config option to SYS_DISABLE_DCACHE_OPS
board/ti/am65x/Kconfig | 1 +
1 file changed, 1 insertion
of same Kconfig across different
architecture, I have added the symbol to top level arch/Kconfig file.
Patch currently disables cache maintenance ops for arm64 only.
Signed-off-by: Vignesh Raghavendra
---
arch/Kconfig | 7 +++
arch/arm/cpu/armv8/cache_v8.c | 18
This series adds a Kconfig to disable cache maintenance operations on
a coherent architectures. And disable cache flush/invalidate ops for
SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent)
Vignesh Raghavendra (2):
arch: armv8: Provide a way to disable cache maintenance ops
AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_ARCH_IS_COHERENT to avoid cache operations in A53 SPL/U-Boot.
Signed-off-by: Vignesh Raghavendra
---
board/ti/am65x/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index
On 26/03/19 7:11 PM, Ashish Kumar wrote:
>>
>> On 26/03/19 10:36 AM, Ashish Kumar wrote:
>>> Hello Maintainers,
>>>
>>>
>>>
>>> With latest commit I see that saveenv command corrupts QSPI-flash,
>>> meaning if I read QSPI-flash at 0x0 offset RCW(reset configuration
>>> word) is erased after
On 01/03/19 7:00 AM, Chris Packham wrote:
> On Fri, Mar 1, 2019 at 11:15 AM Chris Packham wrote:
>>
>> Hi All,
>>
>> I was just testing out the db-88f6820-amc on u-boot#master and found
>> that the SPL can't fetch then next stage from SPI.
>>
>> U-Boot SPL 2019.04-rc2-00139-g91c56ed98da7 (Mar
On 02-Mar-19 1:15 PM, Chris Packham wrote:
> This board uses Micron N25Q256A SPI flash. Enable SPI_FLASH_BAR to allow
> us to access the whole chip.
>
> Signed-off-by: Chris Packham
> Cc: Vignesh R
> ---
>
Could add imply SPI_FLASH_BAR to KIRKWOOD_SPI instead? So that we don't
have to fix
On 02-Mar-19 5:02 PM, Stefan Roese wrote:
[...]
>>
>> It would be great if driver could be modified to support 3 and 4 byte
>> addressing modes.
>
> I fail to see, what really is needed to make the SPI driver support
> 3 and 4 byte addressing modes. I recently added the MT7688 SPI
> driver
Hi Stefan,
On 02-Mar-19 3:56 PM, Stefan Roese wrote:
> Hi Chris,
> Hi Vignesh,
>
> On 02.03.19 09:36, Vignesh Raghavendra wrote:
>>
>>
>> On 02-Mar-19 1:15 PM, Chris Packham wrote:
>>> This board uses Micron N25Q256A SPI flash. Enable SPI_FLASH_BAR t
On 01/03/19 1:42 PM, Chris Packham wrote:
> On Fri, Mar 1, 2019 at 8:40 PM Chris Packham wrote:
>>
>> On Fri, Mar 1, 2019 at 5:12 PM Vignesh Raghavendra wrote:
>>>
>>>
>>>
>>> On 01/03/19 7:00 AM, Chris Packham wrote:
>>>
On 05/04/19 2:24 PM, Rajat Srivastava wrote:
> Incorporate write enable and status check in the write data
> function itself.
>
> Formerly, Write data function used to break the data to be
> written into smaller chunks and used to send the smaller
> chunks without write enable or status check
On 12/04/19 10:46 AM, Jagan Teki wrote:
On 02/04/19 6:22 AM, Marek Vasut wrote:
> Replace the ad-hoc erase operation implementation with a simple
> spi_mem_op implementation of the same functionality. This is a minor
> optimization and removal of the ad-hoc code.
>
Convert driver to use spi-mem ops in order to support accelerated MMIO
flash interface in generic way and for better performance.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tom Rini
---
drivers/spi/ti_qspi.c | 132 ++
1 file changed, 68 insertions
Now that all boards using TI QSPI have moved to DM and DT, drop non DM
code completely.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tom Rini
---
drivers/spi/Kconfig | 13 +-
drivers/spi/Makefile | 2 +-
drivers/spi/ti_qspi.c| 231
, dra7xx EVMs. Build tested for all TI platforms using
buildman
v2
* Rebase on top of latest master and Uri's patch [1] removing
cl-som-am57x_defconfig
* Remove more un-needed CONFIGs related to TI QSPI that have not been
* Collect Reviewed-bys
[1] http://patchwork.ozlabs.org/patch/1085281/
Vignesh
Tom, Jagan
On 16/04/19 9:31 PM, Vignesh Raghavendra wrote:
Now that SPI NOR Supports MMIO SPI controllers via spi-mem framework,
move TI QSPI to SPI MEM framework for better performance and avoid
repeating SPI NOR generic code in the driver.
While at that get rid of non DM code, as all boards
Hi Ashish,
> Hi Vignesh
>
> Is this taken care now, plain text version was posted here
> http://patchwork.ozlabs.org/patch/1090121/
>
A similar patch[1] was proposed in meantime which has been merged to
mainline U-Boot. So this issue must now be resolved. Let me know if the
issue still
On 05/06/19 8:17 PM, Bin Meng wrote:
> Hi Vignesh,
>
> On Wed, Jun 5, 2019 at 9:40 PM Bin Meng wrote:
>>
>> Hi Vignesh,
>>
>> On Sat, Apr 27, 2019 at 12:26 AM Vignesh Raghavendra wrote:
>>>
>>> Bin,
>>>
>>> On 26/04/19 7
Hi,
+Jagan
On 26/04/19 2:52 PM, Weijie Gao wrote:
> Some SPI controllers can't write nor->page_size bytes in a single step
> because their TX FIFO is too small, but when that happens we should
> make sure a WRITE_EN command before each write access and READ_SR command
> after each write access
On 30/04/19 1:13 PM, Schrempf Frieder wrote:
> Hi,
>
> On 26.04.19 06:58, Vignesh Raghavendra wrote:
>>
>>
>> On 25/04/19 5:20 PM, Rajat Srivastava wrote:
>>>
>>>
>>>> -Original Message-
>>>> From: Vignesh Ragh
Hi,
On 08/04/19 10:32 PM, Vignesh Raghavendra wrote:
> This series adds a Kconfig to disable cache maintenance operations on
> a coherent architectures. And disable cache flush/invalidate ops for
> SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent)
>
> Vignesh
On 10/07/19 2:53 PM, Ye Li wrote:
> When slave drivers don't set the max_read_size, the spi-mem should directly
> use data.nbytes and not limit to any size. But current logic will limit to
> the max_write_size.
>
Indeed. Thanks for catching this!
Acked-by: Vignesh Raghavendra
Hi.
On 24-Apr-19 6:10 PM, Rajat Srivastava wrote:
> From: Ashish Kumar
>
> Signed-off-by: Ashish Kumar
> ---
> drivers/mtd/spi/spi-nor-ids.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index
On 24-Apr-19 6:10 PM, Rajat Srivastava wrote:
> Signed-off-by: Ashish Kumar
> Signed-off-by: Rajat Srivastava
Commit message is missing. But from $patch subject, I infer that $patch
is adding new feature and not actually fixing something broken?
If so, you should move the driver over to use
purposes.
Signed-off-by: Peter Ujfalusi
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 33 +
1 file changed, 9 insertions(+), 24 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index f78a01aa8f8c..f896e2958755 100644
to 4c96c61216719155b3a1d51f6373e996335861de:
spi: ti_qspi: Convert to spi-mem ops (2019-04-17 17:43:54 +0530)
Vignesh Raghavendra (2):
spi: ti_qspi: Drop non DM code
spi: ti_qspi: Convert to spi-mem ops
doc/driver-model
On 16/04/19 5:29 PM, Rajat Srivastava wrote:
Maximum write size in a single write operation in
spi_nor_write_data() function can be equal to slave
tx buffer, which is adjusted in spi_mem_adjust_op_size()
and write operation gets fragmented.
Previously data write for the above fragmentation
.
Signed-off-by: Vignesh Raghavendra
---
arch/Kconfig | 9 +
arch/arm/cpu/armv8/cache_v8.c | 10 ++
2 files changed, 19 insertions(+)
diff --git a/arch/Kconfig b/arch/Kconfig
index 2f3d07c13a18..760023b19a81 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -227,6
/disabling dcache by U-Boot and are special case.
Vignesh Raghavendra (2):
arch: armv8: Provide a way to disable cache maintenance ops
board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build
arch/Kconfig | 9 +
arch/arm/cpu/armv8/cache_v8.c | 10
AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.
Signed-off-by: Vignesh Raghavendra
---
board/ti/am65x/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index
On 26/04/19 4:56 AM, Simon Glass wrote:
> Hi Bin,
>
> I find that 'sf test 0 1000' does not work anymore since this commit:
>
> c4e8862308 mtd: spi: Switch to new SPI NOR framework
>
> Have you seen any problems? This seems to prevent proper SPI flash
> writing (not sure about reading).
>
Hi,
On 24/04/19 6:32 PM, Rajat Srivastava wrote:
> Some Freescale QSPI controllers require driver to send only 16 bytes
> aligned data to TxFIFO while performing flash write operation. The extra
> data is not actually written on flash. The patch enables driver to send
> 16 bytes aligned data to
On 25/04/19 5:20 PM, Rajat Srivastava wrote:
>
>
>> -Original Message-----
>> From: Vignesh Raghavendra
>> Sent: Wednesday, April 24, 2019 10:17 PM
>> To: Rajat Srivastava ; u-boot@lists.denx.de;
>> ja...@openedev.com
>> Cc: Ashish Kumar
Bin,
On 26/04/19 7:33 PM, Bin Meng wrote:
> Hi Simon,
>
> On Fri, Apr 26, 2019 at 7:26 AM Simon Glass wrote:
>>
>> Hi Bin,
>>
>> I find that 'sf test 0 1000' does not work anymore since this commit:
>>
>> c4e8862308 mtd: spi: Switch to new SPI NOR framework
>>
>> Have you seen any problems?
SB:
>>
>> usbss0: cdns_usb@4104000 {
>> compatible = "ti,j721e-usb";
>> []
>> usb0: usb@600 {
>> compatible = "cdns,usb3-1.0.1";
>>
>> The driver selection (host or device) could
Hi Sherry,
On 21/08/19 8:05 PM, Sherry Sun wrote:
> These patches introduce new Cadence driver to U-Boot.
> The first patch is to add the Cadence USB3 IP(CDNS3) core and driver for
> the usb gadget.
> The second patch introduce the xhci-imx8 usb host driver separately.
> The third patch
Hi,
On 28/08/19 7:52 PM, Sherry Sun wrote:
> Hi Vignesh,
[...]
>> I see that Cadence USB driver for Linux kernel is still under development and
>> DT compatible binding is supposed to be "cdns,usb3" not "cdns,usb3-1.0.0".
>> See v11:
>>
In case dma_ring_reset_quirk is not set the k3_ringacc_ring_reset_dma will
just exit without ring reset. Fix it, by adding ring reset call in case
dma_ring_reset_quirk is not.
Signed-off-by: Grygorii Strashko
Signed-off-by: Vignesh Raghavendra
---
drivers/soc/ti/k3-navss-ringacc.c | 4 +++-
1
Hi Sherry,
[...]
>> AFAIK, U-Boot does not support runtime switching of USB port to host from
>> device and vice versa. This is the case for existing driver like DWC3/MUSB
>> etc.
>>
>> Ideally we would need a role switch driver that unbinds and rebinds host vs
>> device driver as when required
Hi,
On 04/09/19 11:37 PM, Eugeniy Paltsev wrote:
> We faced with regressions caused by
> commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework)
> This switch was performed by removing entire u-boot spi-flash
> core implementation and copying it from another project.
> However the switch
probe" should be sufficient.
Regards
Vignesh
On 10/09/19 5:24 PM, Vignesh Raghavendra wrote:
>
>
> On 10/09/19 5:11 PM, Eugeniy Paltsev wrote:
>> Hi Vignesh,
>>
>> that patch helps - both erase and write works fine.
>>
>
> Thanks for testing! I
: "Eugeniy Paltsev "
>
> ---
> Eugeniy Paltsev
>
>
> ____________
> From: Vignesh Raghavendra
> Sent: Tuesday, September 10, 2019 08:07
> To: Eugeniy Paltsev; Jagan Teki
> Cc: u-boot@lists.denx.de; uboot-snps-...@synopsys.com; Alexey
Hi Ashish, Simon,
On 11/09/19 3:11 PM, Simon Goldschmidt wrote:
>
>
> Ashish Kumar mailto:ashish.ku...@nxp.com>>
> schrieb am Mi., 11. Sep. 2019, 10:49:
>
>
>
> > -Original Message-
> > From: Vignesh Raghavendra mailto:vigne...@ti.co
Not all variants of n25q256* and n25q512* support 4 Byte stateless
addressing opcodes and there is no easy way to discover at runtime
whether the flash supports this feature or not.
Therefore don't set SPI_NOR_4B_OPCODES for these flashes.
Signed-off-by: Vignesh Raghavendra
For n25q512ax3
either of them.
With that we can have single entry for n25q512a and mt25qu512a.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi-nor-ids.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index a39
On 09/09/19 1:49 PM, Faiz Abbas wrote:
> Add Support for UFS Host Controller Interface (UFSHCI) for communicating
> with Universal Flash Storage (UFS) devices. The steps to initialize the
> host controller interface are the following:
>
> - Initiate the Host Controller Initialization process by
On 09/09/19 1:49 PM, Faiz Abbas wrote:
> Add glue layer driver for the controller present on TI's J721E devices.
>
> Signed-off-by: Faiz Abbas
> ---
> drivers/ufs/Kconfig| 6 +++
> drivers/ufs/Makefile | 1 +
> drivers/ufs/ti-j721e-ufs.c | 75
On 09/09/19 1:49 PM, Faiz Abbas wrote:
> diff --git a/include/scsi.h b/include/scsi.h
> index 81ab43c842..076bdbc6a0 100644
> --- a/include/scsi.h
> +++ b/include/scsi.h
> @@ -168,6 +168,7 @@ struct scsi_platdata {
> unsigned long base;
> unsigned long max_lun;
> unsigned long
e failed
and Read status/Read flag status register should have reported error values.
Anyways, I guess I found a wrt how 4 Byte addressing is handled wrt n25q512*
series.
Could you try with below patch helps[1]?
If not please provide logs similar what you have provide now.
If below patch doe
This series adds support for HyperBus Memory Controller of TI's J721e
and AM654 SoCs.
Vignesh Raghavendra (6):
mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined
mtd: Add TI HyperBus Memory Controller driver
arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node
arm: dts
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node for the
same.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/dts/k3-j721e-som-p0.dtsi | 34 +++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi
b/arch/arm/dts/k3-j721e
Define CONFIG_SYS_MAX_FLASH_BANKS_DETECT so that number of flash banks
are automatically detected by CFI flash driver
Signed-off-by: Vignesh Raghavendra
---
include/configs/j721e_evm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/configs/j721e_evm.h b/include/configs
-by: Vignesh Raghavendra
---
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index 01a8f4a9908f..bb652f2fb8d4 100644
--- a/arch/arm/dts/k3-j721e-mcu
Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build
error when CONFIG_SYS_MONITOR_BASE is not defined.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/cfi_flash.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd
Enable HBMC and HyperFlash in A72 SPL and A72 U-Boot
Signed-off-by: Vignesh Raghavendra
---
configs/j721e_evm_a72_defconfig | 12
1 file changed, 12 insertions(+)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 56df452fb6ca..ef91d07aa33f 100644
-off-by: Vignesh Raghavendra
---
drivers/mtd/Kconfig | 7 +++
drivers/mtd/Makefile | 1 +
drivers/mtd/hbmc-am654.c | 105 +++
3 files changed, 113 insertions(+)
create mode 100644 drivers/mtd/hbmc-am654.c
diff --git a/drivers/mtd/Kconfig b/drivers
On 18/07/19 4:29 PM, Jagan Teki wrote:
> On Thu, Jul 18, 2019 at 4:15 PM Ashish Kumar wrote:
>>
>>
>>
>>> -Original Message-
>>> From: Jagan Teki
>>> Sent: Thursday, July 18, 2019 3:59 PM
>>> To: Ashish Kumar ; Vignesh R
>>> Cc: U-Boot-Denx
>>> Subject: [EXT] Re: [Patch V3] drivers:
>> s25fs512s and s25fl512s which has same JEDEC ID but only varies in
>> operating volatge so s25fs512s shares same command set as
>> mentioned
>> below:
>> – Serial Command subset and footprint compatible with S25FL-A,
>> S25FL-K, S25FL-P, and S25FL-S SPI families – Multi I/O
Import for_each_set_bit() and associated macros and functions from
Linux. This is useful in parsing interrupt registers and take action on
each bit that is set.
Signed-off-by: Vignesh Raghavendra
---
include/linux/bitmap.h | 61 ++
1 file changed, 61
by the gadget controller driver
Signed-off-by: Vignesh Raghavendra
---
drivers/usb/gadget/epautoconf.c | 3 +++
include/linux/usb/gadget.h | 23 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index
Add driver to handle TI specific wrapper for Cadence USB3 controller
present on J721e SoC. Based on Linux driver for the same.
Signed-off-by: Vignesh Raghavendra
---
drivers/usb/cdns3/Kconfig| 7 ++
drivers/usb/cdns3/Makefile | 2 +
drivers/usb/cdns3/cdns3-ti.c | 193
Add a new bcdDevice entry for Cadence USB gadget controller similar to
other controller and add gadget_is_cdns3() macro as well.
Signed-off-by: Vignesh Raghavendra
---
drivers/usb/gadget/gadget_chips.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/usb/gadget/gadget_chips.h
Implement udc_set_speed() callback to limit Controller's speed to
high-speed/full-speed when working with gadgets that are high-speed or
full-speed only
Signed-off-by: Vignesh Raghavendra
---
drivers/usb/cdns3/gadget.c | 30 ++
1 file changed, 26 insertions(+), 4
: Introduce ->udc_set_speed() method
Vignesh Raghavendra (7):
list: import list_first_entry_or_null()
bitmaps: import for_each_set_bit() macro
usb: gadget: Add match_ep() op to usb_gadget_ops
usb: Add Cadence USB3 host and gadget driver
usb: cdns3: gadget: Implement udc_set_speed() callb
Import list_first_entry_or_null() macro from Linux that would be used
by Cadence USB driver
Signed-off-by: Vignesh Raghavendra
---
include/linux/list.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/linux/list.h b/include/linux/list.h
index 5b8d1df5dfee
that will just fail.
So here introduce a new optional ->udc_set_speed() method which can be
implemented by interested UDC drivers to achieve this purpose.
Signed-off-by: Sherry Sun
Signed-off-by: Vignesh Raghavendra
---
drivers/usb/gadget/udc/udc-core.c | 23 +++
include/li
U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector
support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS.
Reported-by: Eugeniy Paltsev
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi-nor-core.c | 2 +-
drivers/mtd/spi/spi-nor-ids.c | 2 +-
2 files changed, 2
Use dev_err() when reporting reason for erase/write failures so that
users can be made aware of the reason for failure.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi-nor-core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c
First patch improves error reporting on erase/write failures
Second patch makes sure small sector is used even when SFDP is enabled
and CONFIG_SPI_FLASH_USE_4K_SECTORS is set.
Jagan,
Could you please consider these patches for next -rc?
Vignesh Raghavendra (2):
mtd: spi-nor-core: Use dev_err
Newer variants of mt25q* flashes support 4 Byte addressing opcodes. Add
entries for the same. These flashes have bit 6 set in 5th byte of READ ID
response.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi-nor-ids.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/spi
Older variants of n25q256* and n25q512* do not support 4 Byte stateless
addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these
entries.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi-nor-ids.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
supports flag registers
Tested on mt25qu512a variant
Simon, Euginey,
Could you test this patch series on your boards as well?
Changes since v1:
Rename newer variants as mt25*
Add a patch to enable flag register parsing for mt25qu512a
Vignesh Raghavendra (3):
spi-nor: spi-nor-ids: Disable
mt25qu512a flash has Flag status register that indicates various errors
that may be encountered during erase/write operations. Therefore add
USE_FSR flag to the entry
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi-nor-ids.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
Hi Simon,
On 24/09/19 12:32 PM, Simon Goldschmidt wrote:
> Hi Vignesh,
>
> On Tue, Sep 24, 2019 at 7:55 AM Vignesh Raghavendra wrote:
>>
>> This series removes SPI_NOR_4B_OPCODES flags from legacy variants of
>> n25q256* and n25q512* and adds entries for newer v
On 24/09/19 2:13 PM, Simon Goldschmidt wrote:
> HI Vignesh,
>
> On Tue, Sep 24, 2019 at 9:59 AM Vignesh Raghavendra wrote:
>>
>> Hi Simon,
>>
>> On 24/09/19 12:32 PM, Simon Goldschmidt wrote:
>>> Hi Vignesh,
>>>
>>>
eries
fixing those entries.
Regards
Vignesh
> Regards
> Ashish
>>
>> Regards
>> Vignesh
>>
>>> Still, so we have such an op-in possibility to enable 4 byte opcodes
>>> on these chips?
>>>
>>> Regards,
>>> Simon
>
Simon,
On 24-Sep-19 5:15 PM, Simon Goldschmidt wrote:
> Hi Tudor,
>
> On Tue, Sep 24, 2019 at 1:36 PM wrote:
>>
[...]
Simon,
Could you provide dump of SFDP tables and all the 6 bytes READ ID of the
flash that you have?
>>>
>>> I have a n251256a with JEDEC ID 20, ba, 19, 10,
Older variants of n25q256* and n25q512* do not support 4 Byte stateless
addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these
entries.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi-nor-ids.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
Newer variants of n25q256* and n25q512* flashes support 4 Byte
addressing opcodes. Add entries for the same. These flashes Bit 6 set in
5th byte of READ ID response.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi-nor-ids.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
these patches and make sure
4 Byte opcodes are being used. (Probably by enabling/adding prints to
cmd->opcode in spi_mem_exec_op() in drivers/spi/spi-mem.c
Euginey,
Could you test this series on top of latest u-boot master and confirm
that your test cases still work?
Regards
Vignesh
Vign
mt25qu512a is just a rebranded name for n25q512a. All the 6 bytes of JEDEC
ID bytes are same for mt25qu512a and n25q512a. Therefore rename
mt25qu512a to "mt25qu512a (n25q512a)", so that its much clearer to user.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi-nor-ids.c | 2
On 12/06/19 9:26 PM, Jagan Teki wrote:
> + Vignesh
>
> On Tue, May 14, 2019 at 7:11 AM Weijie Gao wrote:
>>
>> This patch adds spi-mem driver for MediaTek MT7629 SoC to access SPI-NOR
>> and SPI-NAND flashes.
>>
>> Cc: Jagan Teki
>> Signed-off-by: Weijie Gao
>> ---
>> Changes since v1:
On 10/11/19 5:11 PM, Vignesh Raghavendra wrote:
> Hi Simon,
>
> On 24-Oct-19 11:53 PM, Simon Goldschmidt wrote:
>> From: Simon Goldschmidt
>>
>> Support loading clk speed via DM instead of requiring ad-hoc code.
>>
>> Signed-off-by: Simon Goldschmi
Static checker warns 'ret' variable may be used uninitialized in
spi_nor_erase() and spi_nor_write() in case of zero length requests.
Fix these warnings by checking for zero length requests and returning
early.
Reported-by: Dan Murphy
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi
Hi Simon,
On 24-Oct-19 11:53 PM, Simon Goldschmidt wrote:
> From: Simon Goldschmidt
>
> Support loading clk speed via DM instead of requiring ad-hoc code.
>
> Signed-off-by: Simon Goldschmidt
> Signed-off-by: Simon Goldschmidt
> ---
[...]
> @@ -22,12 +23,29 @@ static int
will be accessible
> by getting the UCLASS_SPI_FLASH's private data.
>
> The SST's SFDP table is particularly of interest because contains
> pre-programmed globally unique EUI-48 and EUI-64 identifiers.
>
> Signed-off-by: Tudor Ambarus
> ---
Reviewed-by: Vignesh Raghavendr
Get flow ID information for RX DMA channel using dma_get_cfg() interface
instead of reading from DT. This is required in order to avoid DT update
whenever there is change in the range of flow ID allocated to the host.
Signed-off-by: Vignesh Raghavendra
---
drivers/net/ti/am65-cpsw-nuss.c | 13
. Clients can use unique configuration ID flags to get different
configuration data from DMA driver.
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/dma-uclass.c | 12
include/dma-uclass.h | 11 +++
include/dma.h| 11 +++
3 files changed, 34 insertions
Enable configs related to DMA and Ethernet so as to support networking at
U-Boot prompt
Signed-off-by: Vignesh Raghavendra
---
configs/j721e_evm_a72_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index
MA channel. In order for basic ethernet to work, CPSW slave must be
aware of the flow ID allocated for the RX channel by the DMA driver.
This interface allows CPSW to query flow ID from DMA provider and
configure it in CPSW HW.
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c
and configs.
Vignesh Raghavendra (6):
dma: Introduce dma_get_cfg() interface
dma: ti: k3-udma: Implement dma_get_cfg() interface
net: ti: am65-cpsw-nuss: Rework RX flow ID handling
net: ti: am65-cpsw-nuss: Add new compatible for J721e
arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW
Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
up on J721e EVM.
Signed-off-by: Vignesh Raghavendra
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 268 ++
1 file changed, 268 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u
Add new compatible to handle J721e SoC
Signed-off-by: Vignesh Raghavendra
---
drivers/net/ti/am65-cpsw-nuss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 2e14f4be862f..b606ff0ade2a 100644
--- a/drivers/net/ti/am65
J721e has two instances of Cadence USB3 controller. Add DT nodes for the
same. USB0 is configured to device mode and USB1 is configured to host
mode. For now only high speed mode is supported.
Signed-off-by: Vignesh Raghavendra
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 14
arch
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