*** This patch set adds the support for new st architecure stv0991 ***
Vikas Manocha (3):
stv0991 : Add basic stv0991 architecture support.
stv0991 : enable ethernet support.
stv0991: default + misc command configs enabled.
arch/arm/Kconfig |4 +
arch
stv0991 architecture support added. It contains the support for
following blocks
- Timer
- uart
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
arch/arm/Kconfig |4 +
arch/arm/cpu/armv7/stv0991/Makefile|9 ++
arch/arm/cpu/armv7
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
arch/arm/cpu/armv7/stv0991/clock.c | 14
arch/arm/cpu/armv7/stv0991/pinmux.c| 14
arch/arm/include/asm/arch-stv0991/gpio.h | 22
arch/arm/include/asm/arch-stv0991
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
include/configs/stv0991.h | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index a7181b1..d6ff243 100644
--- a/include/configs/stv0991.h
+++ b
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2: None
include/configs/stv0991.h | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index a7181b1..d6ff243 100644
--- a/include
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2: None
arch/arm/cpu/armv7/stv0991/clock.c | 14
arch/arm/cpu/armv7/stv0991/pinmux.c| 14
arch/arm/include/asm/arch-stv0991/gpio.h | 22
arch/arm
stv0991 architecture support added. It contains the support for
following blocks
- Timer
- uart
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2:
- corrected files license to GPL-2.0+
- replaced printf() usage with puts() for string print
- sorted sourcing of board Kconfig
This patchset add support for new arch stv0991.
Changes in v3:
- removed period from commit messages
Changes in v2:
- corrected files license to GPL-2.0+
- replaced printf() usage with puts() for string print
- sorted sourcing of board Kconfig
Vikas Manocha (3):
stv0991: Add basic stv0991
stv0991 architecture support added. It contains the support for
following blocks
- Timer
- uart
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3:
- removed period from commit message
Changes in v2:
- corrected files license to GPL-2.0+
- replaced printf() usage with puts
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3:
- removed period from commit message
Changes in v2: None
arch/arm/cpu/armv7/stv0991/clock.c | 14
arch/arm/cpu/armv7/stv0991/pinmux.c| 14
arch/arm/include/asm/arch
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3:
- removed period from commit message
Changes in v2: None
include/configs/stv0991.h | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/include/configs/stv0991.h b/include/configs
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/serial/serial_pl01x.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 758684f..3fc1db5 100644
--- a/drivers/serial/serial_pl01x.c
UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which
is updated on a single write strobe generated by a UART_LCR_H write. So, to
internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H
must always be performed at the end.
Signed-off-by: Vikas
Receive line control uses same setting as transmit line control, also one lcrh
write is effective for both baud rate receive line control internal update.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/serial/serial_pl01x.c | 40 +++-
1 file
Although we were checking the pl01x type, seems like PL010 type was being
passed by mistake.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/serial/serial_pl01x.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial
This patchset fixes the pl01x driver esp for pl011 baudrate line
control.
Vikas Manocha (5):
serial: pl01x: pass pl01x_type to set baudrate
serial: pl01x: fix pl011 baud rate configuration
serial: pl01x: move all line control at same place
serial: pl01x: disable as per type of pl01x
pl010 pl011 have different control register offsets, setting it as per
the pl01x type.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/serial/serial_pl01x.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial
stv0991 architecture support added. It contains the support for
following blocks
- Timer
- uart
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4:
- added maintainers info
- rebased to current master
Changes in v3:
- removed period from commit message
Changes in v2
of board Kconfig
Vikas Manocha (4):
stv0991: Add basic stv0991 architecture support
stv0991: enable ethernet support
stv0991: default + misc command configs enabled
stv0991: add maintainer information
MAINTAINERS|6 +
arch/arm/Kconfig
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: None
Changes in v3:
- removed period from commit message
Changes in v2: None
include/configs/stv0991.h | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/include/configs/stv0991.h b
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4:
- added maintainers info
MAINTAINERS |6 ++
board/st/stv0991/MAINTAINERS |5 +
2 files changed, 11 insertions(+)
create mode 100644 board/st/stv0991/MAINTAINERS
diff --git a/MAINTAINERS b
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: None
Changes in v3:
- removed period from commit message
Changes in v2: None
arch/arm/cpu/armv7/stv0991/clock.c | 14
arch/arm/cpu/armv7/stv0991/pinmux.c| 14
arch/arm
Thanks Albert,
I rebased the patchset on current master today submitted the v4.
Rgds,
Vikas
-Original Message-
From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
Sent: Wednesday, November 12, 2014 1:08 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; vk.vi...@gmail.com
Subject
stv0991 architecture support added. It contains the support for
following blocks
- Timer
- uart
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v5:
- added maintainers info
Changes in v4:
- added maintainers info
- rebased to current master
Changes in v3:
- removed period from
Changes in v3:
- removed period from commit messages
Changes in v2:
- corrected files license to GPL-2.0+
- replaced printf() usage with puts() for string print
- sorted sourcing of board Kconfig
Vikas Manocha (3):
stv0991: Add basic stv0991 architecture support
stv0991: enable ethernet support
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- removed period from commit message
arch/arm/cpu/armv7/stv0991/clock.c | 14
arch/arm/cpu/armv7/stv0991/pinmux.c| 14
arch/arm
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v5:
- replaced '+' with 'and' in the patch subject line
- patch subject changed to active voice from passive
Changes in v4: None
Changes in v3:
- removed period from commit message
Changes in v2: None
include/configs/stv0991.h
Although we were checking the pl01x type, seems like PL010 type was being
passed by mistake.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/serial/serial_pl01x.c |2 +-
1 file changed, 1 insertion(+), 1 deletion
This patchset fixes the pl01x driver esp for pl011 baudrate line
control.
Changes in v2:
- fix the comment style
Vikas Manocha (5):
serial: pl01x: pass pl01x_type to set baudrate
serial: pl01x: fix pl011 baud rate configuration
serial: pl01x: move all line control at same place
serial
pl010 pl011 have different control register offsets, setting it as per
the pl01x type.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/serial/serial_pl01x.c |7 ---
1 file changed, 4 insertions(+), 3 deletions
Receive line control uses same setting as transmit line control, also one lcrh
write is effective for both baud rate receive line control internal update.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2:
- fixed comment style
drivers
UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which
is updated on a single write strobe generated by a UART_LCR_H write. So, to
internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H
must always be performed at the end.
Signed-off-by: Vikas
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/serial/serial_pl01x.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
board/st/stv0991/stv0991.c | 13 +
include/configs/stv0991.h | 17 -
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c
index 989fb5e
It is done to make space available for driver model memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
include/configs/stv0991.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index f95de06..80652a8 100644
This patchset adds driver model support in stv0991 configures serial
ip to driver model.
Vikas Manocha (2):
stv0991: increase the initial ram size config
dm: stv0991: Move serial to driver model
board/st/stv0991/stv0991.c | 13 +
include/configs/stv0991.h | 19
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
arch/arm/dts/Makefile |1 +
arch/arm/dts/stv0991.dts | 23 +++
configs/stv0991_defconfig |1 +
include/configs/stv0991.h |3 +++
4 files changed, 28 insertions(+)
create mode 100644 arch/arm/dts/stv0991
This patchset adds device tree support for stv0991 soc.
Changes in v2:
- added commit messages for both patches.
Vikas Manocha (2):
stv0991: fdt: add stv0991 device tree
stv0991: use fdt for serial port platform data
arch/arm/dts/Makefile |1 +
arch/arm/dts/stv0991.dts | 23
This patch adds device tree for the ST Micro stv0991 board enables
device tree control. Progressively device tree support for the drivers
being used will also be added.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2:
- added commit message.
arch/arm/dts/Makefile
This patch ignores the serial port static platform data at compilation time
in case of device tree control.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes in v2:
- added commit message.
board/st/stv0991/stv0991.c |2 ++
1 file
This patchset adds device tree support for stv0991 soc.
Vikas Manocha (2):
stv0991: fdt: add stv0991 device tree
stv0991: use fdt for serial port platform data
arch/arm/dts/Makefile |1 +
arch/arm/dts/stv0991.dts | 23 +++
board/st/stv0991/stv0991.c |2
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
board/st/stv0991/stv0991.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c
index 38f6e1d..09f973f 100644
--- a/board/st/stv0991/stv0991.c
+++ b/board/st/stv0991/stv0991.c
This patch adds device tree for the ST Micro stv0991 board enables
device tree control. Progressively device tree support for the drivers
being used will also be added.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v3:
- CONFIG_OF_EMBED replaced with CONFIG_OF_SEPARATE
This patch ignores the serial port static platform data at compilation time
in case of device tree control.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- added commit message.
board/st/stv0991/stv0991.c
This patchset adds device tree support for stv0991 soc.
Changes in v3:
- CONFIG_OF_EMBED replaced with CONFIG_OF_SEPARATE
Changes in v2:
- added commit messages for both patches.
Vikas Manocha (2):
stv0991: fdt: add stv0991 device tree
stv0991: use fdt for serial port platform data
arch
This patch adds device tree support for arm pl010/pl011 driver.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
doc/device-tree-bindings/serial/pl01x.txt |7 +
drivers/serial/serial_pl01x.c | 41 -
2 files changed, 47 insertions(+), 1
This patch adds device tree support for arm pl010/pl011 driver.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v2:
- removed #ifdef CONFIG_OF_CONTROL from driver structure used of_match_ptr
doc/device-tree-bindings/serial/pl01x.txt |7 +++
drivers/serial
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
configs/stv0991_defconfig |1 +
include/configs/stv0991.h |1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index 2be3f82..817a832 100644
--- a/configs
This patchset does changes in stv0991 board file to enable saving
environments in spi flash moves CONFIG_OF in the defconfig file.
Vikas Manocha (3):
stv0991: enable saving enrironment in spi flash
stv0991: move OF_CONTROL config to defconfig
stv0991: remove define CONFIG_OF_SEPARATE from
CONFIG_OF_SEPARATE is default define with CONFIG_OF_CONTROL, removing
this define from the board file to avoid multiple definition warning.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
include/configs/stv0991.h |1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
include/configs/stv0991.h |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 4138b32..ea62f43 100644
--- a/include/configs/stv0991.h
+++ b/include/configs
This patchset adds support to get controller sram size from device tree
fix to support different FIFO widths.
Vikas Manocha (3):
spi: cadence_qspi: move the sram partition in init
spi: cadence_qspi: get sram size from device tree
spi: cadence_qspi: support FIFO width other than 4 bytes
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read half for write once at initialization.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c | 16
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
arch/arm/dts/socfpga.dtsi |1 +
arch/arm/dts/stv0991.dts |1
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c | 47
1 file changed, 24 insertions(+), 23 deletions
Hi Stefan,
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: Friday, June 12, 2015 5:10 AM
To: Vikas MANOCHA; u-boot@lists.denx.de;
grmo...@opensource.altera.com; dingu...@opensource.altera.com
Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT fix
Hi Graham,
-Original Message-
From: Graham Moore [mailto:grmo...@opensource.altera.com]
Sent: Tuesday, June 23, 2015 7:37 AM
To: Vikas MANOCHA
Cc: Stefan Roese; u-boot@lists.denx.de; dingu...@opensource.altera.com;
jt...@openedev.com
Subject: Re: [PATCH RESEND 0/7] spi
Thanks Stefan,
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: Monday, June 22, 2015 1:35 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; grmo...@opensource.altera.com;
dingu...@opensource.altera.com; jt...@openedev.com
Subject: Re: [PATCH RESEND 0/7] spi
Thanks Stefan,
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: Thursday, June 18, 2015 11:16 PM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; grmo...@opensource.altera.com;
dingu...@opensource.altera.com; jt...@openedev.com
Subject: Re: [PATCH RESEND 0/7] spi
Thanks Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Wednesday, June 24, 2015 11:54 AM
To: Vikas MANOCHA
Cc: Stefan Roese; u-boot@lists.denx.de; grmo...@opensource.altera.com
Subject: Re: [U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT
fix
stv0991 has cadence qspi controller for flash interfacing, this
patch configures the device pads clock for the controller.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2:
- removed checkpatch.pl error.
arch/arm/cpu/armv7/stv0991/clock.c |4 +++-
arch
Thanks Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Wednesday, June 24, 2015 12:00 PM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; tr...@konsulko.com
Subject: Re: [U-Boot] [PATCH 0/3] stv0991: spi env configs related board
changes
Please test
This patch does all the board configurations required to use the qspi
controller attached spi flash memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2: None
include/configs/stv0991.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/include
CONFIG_OF_SEPARATE is default define with CONFIG_OF_CONTROL, removing
this define from the board file to avoid multiple definition warning.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2: None
include/configs/stv0991.h |1 -
1 file changed, 1 deletion(-)
diff --git
This patch add the device tree entry for qspi controller spi flash
memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2: None
arch/arm/dts/stv0991.dts | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/dts/stv0991.dts b
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2: None
configs/stv0991_defconfig |1 +
include/configs/stv0991.h |1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index f8ec5db..1d47178 100644
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changed in v2: None
include/configs/stv0991.h |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index d8f51d8..fe5b2fe 100644
--- a/include/configs/stv0991.h
board changes
Changed in v2:
- remove checkpatch.pl error from patch stv0991: configure clock...
- clubbed two patchsets mentioned above.
Vikas Manocha (6):
stv0991: enable saving enrironment in spi flash
stv0991: move OF_CONTROL config to defconfig
stv0991: remove define CONFIG_OF_SEPARATE
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes in v2: Fixed the checkpatch.pl error
drivers/spi/cadence_qspi_apb.c | 46
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read half for write once at initialization.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes in v2: None
arch/arm/dts/socfpga.dtsi
This patchset adds support to get controller sram size from device tree
fix to support different FIFO widths.
Changes in v2:
- fix the checkpatch error from patch 3/3
Vikas Manocha (3):
spi: cadence_qspi: move the sram partition in init
spi: cadence_qspi: get sram size from device tree
Thanks Stefan,
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: Thursday, June 18, 2015 5:02 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; grmo...@opensource.altera.com;
dingu...@opensource.altera.com; jt...@openedev.com
Subject: Re: [PATCH RESEND 0/7] spi
Thanks Stefan,
Adding Jagan to apply the patchset.
Rgds,
Vikas
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: Wednesday, June 24, 2015 3:09 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; grmo...@opensource.altera.com;
dingu...@opensource.altera.com
Subject: Re
Hi Stephen,
Any comments on the patchset.
Rgds,
Vikas
-Original Message-
From: Vikas MANOCHA
Sent: Tuesday, June 09, 2015 6:25 PM
To: u-boot@lists.denx.de; s...@denx.de; grmo...@opensource.altera.com;
dingu...@opensource.altera.com
Cc: Vikas MANOCHA
Subject: [PATCH 0/3] spi
Thanks Jagan.
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Tuesday, June 16, 2015 3:50 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; tr...@konsulko.com
Subject: Re: [U-Boot] [PATCH 0/3] stv0991: spi env configs related board
changes
As these were new
for synchronization. For example in case we are
getting SRAM fill level equal to 10 locations but in reality there were 2
another words completed and actual level is 12 but information may not be
synchronized yet because of the synchronization latency on APB domain.
Signed-off-by: Vikas Manocha
Fifo width could be different on different socs, e.g. stv0991 altera soc
have different fifo width.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
arch/arm/dts/socfpga.dtsi |1 +
arch/arm/dts/stv0991.dts |1 +
drivers/spi/cadence_qspi.c |1 +
drivers/spi
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 8eeb423..794d51d 100644
--- a/drivers/spi
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 403230a..e1e1315 100644
--- a/drivers/spi/cadence_qspi_apb.c
This patchset:
- removes sram polling while reading/writing from flash.
- fixes trigger base transfer start address register programming. This fix
superseeds the previous patch spi: cadence_qspi: Fix the indirect ahb trigger
address setting
- adds support to get fifo width from device tree
Vikas
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c |6 --
1 file changed, 4 insertions(+), 2
/write start addresses (offset 0x68/0x78)should be programmed with
the absolute flash address to be read/written.
plat-ahbbase has been renamed to plat-flashbase for clarity.
plat-triggerbase is added in device tree for mapped spi flash address.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
There is no need to poll sram level before writing to flash, data going to SRAM
till sram is full, after that backpressure will take over.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c | 59 ++--
1 file changed, 15
This patchset:
- removes sram polling while reading/writing from flash.
- fixes trigger base transfer start address register programming. This fix
superseeds the previous patch spi: cadence_qspi: Fix the indirect ahb trigger
address setting
- adds support to get fifo width from device tree
Vikas
There is no need to poll sram level before writing to flash, data going to SRAM
till sram is full, after that backpressure will take over.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c | 63 ++--
1 file changed, 16
for synchronization. For example in case we are
getting SRAM fill level equal to 10 locations but in reality there were 2
another words completed and actual level is 12 but information may not be
synchronized yet because of the synchronization latency on APB domain.
Signed-off-by: Vikas Manocha
) with addition
of this patchset. With it, all the patches will apply on master.
- wait for the previous patchset to get in mainline(might take some time).
Rgds,
Vikas
-Original Message-
From: Vikas MANOCHA
Sent: Monday, June 15, 2015 11:19 AM
To: u-boot@lists.denx.de; s...@denx.de
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c |6 --
1 file changed, 4 insertions(+), 2
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c |6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 313f6ac..515d88e 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b
/write start addresses (offset 0x68/0x78)should be programmed with
the absolute flash address to be read/written.
plat-ahbbase has been renamed to plat-flashbase for clarity.
plat-triggerbase is added in device tree for mapped spi flash address.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Fifo width could be different on different socs, e.g. stv0991 altera soc
have different fifo width.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
arch/arm/dts/socfpga.dtsi |1 +
arch/arm/dts/stv0991.dts |1 +
drivers/spi/cadence_qspi.c |1 +
drivers/spi
Thanks Jagan.
Rgds,
Vikas
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Monday, June 15, 2015 12:31 PM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; s...@denx.de; grmo...@opensource.altera.com;
dingu...@opensource.altera.com
Subject: Re: [U-Boot] [PATCH 0/6
Hi Tom,
Can you please apply the stv0991 patchset.
Rgds,
Vikas
-Original Message-
From: Vikas MANOCHA
Sent: Wednesday, May 27, 2015 6:43 PM
To: u-boot@lists.denx.de
Cc: Vikas MANOCHA
Subject: [PATCH 0/3] stv0991: enable cadence qspi controller spi flash
This patchset enables
Hi Tom,
Can you please apply these patchset for stv0991.
Rgds,
Vikas
-Original Message-
From: Vikas MANOCHA
Sent: Monday, June 08, 2015 5:47 PM
To: u-boot@lists.denx.de
Cc: Vikas MANOCHA
Subject: [PATCH 0/3] stv0991: spi env configs related board changes
This patchset does
of
addresses from this trigger address to the trigger address + 15, then the AHB
request is completed by fetching/storing data from/to the Controllers SRAM.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c |7 ++-
1 file changed, 2 insertions(+), 5
This patchset enables cadence qspi controller for stv0991 soc.
Vikas Manocha (3):
stv0991: configure clock pad muxing for qspi
stv0991: enable cadence qspi controller spi flash
stv0991: configure device tree for cadence qspi flash
arch/arm/cpu/armv7/stv0991/clock.c
stv0991 has cadence qspi controller for flash interfacing, this
patch configures the device pads clock for the controller.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
arch/arm/cpu/armv7/stv0991/clock.c |4 +++-
arch/arm/cpu/armv7/stv0991/pinmux.c
This patch does all the board configurations required to use the qspi
controller attached spi flash memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
include/configs/stv0991.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/include/configs/stv0991.h b
This patch add the device tree entry for qspi controller spi flash
memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
arch/arm/dts/stv0991.dts | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
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