From: Hou Zhiqiang b48...@freescale.com
Enter 3 Byte address mode at first, because it may change to 4 Byte
address mode in kernel driver and not reset to 3 Byte address mode
after reboot.
Add clear flag status register operation that some Micron SPI flash
chips required after reading the flag
From: Hou Zhiqiang b48...@freescale.com
The clear flag status register operation was required by Micron
SPI flash chips, which support FSR. And if an error bit of FSR
have been set, it must be cleared by the clear FSR operation.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
Signed-off-by:
From: Hou Zhiqiang b48...@freescale.com
It doesn't make sense to compare a 'u8' element with Zero.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
drivers/mtd/spi/sf_ops.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c
From: Hou Zhiqiang b48...@freescale.com
For more than 16MiB SPI flash chips, there are 3-Byte and 4-Byte address
mode, and only the 3-Byte address mode is supported in U-Boot so far.
So, reset the SPI flash to 3-Byte address mode in probe to ensure the SPI
flash work correctly, because it may has
From: Hou Zhiqiang b48...@freescale.com
Add clear flag status register operation that was required by Micron SPI
flash chips, which support FSR. And if an error bit of FSR have been set,
it must be cleared by the clear FSR operation.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
From: Hou Zhiqiang b48...@freescale.com
For more than 16MiB SPI flash chips, there are 3-Byte and 4-Byte address
mode, and only the 3-Byte address mode is supported in U-Boot so far.
So, reset the SPI flash to 3-Byte address mode in probe to ensure the SPI
flash work correctly, because it may has
From: Hou Zhiqiang b48...@freescale.com
Add clear flag status register operation that was required by Micron SPI
flash chips after reading the flag status register to check if the erase
and program operations complete or an error occur.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
From: Hou Zhiqiang b48...@freescale.com
For more than 16MiB Micron chips, there are 3-Byte and 4-Byte address mode,
and only the 3-Byte address mode is supported in u-boot.
So, reset the SPI flash to 3-Byte address mode in probe to ensure the SPI
flash work correctly, because it may be in 4-Byte
Hi York,
> -Original Message-
> From: Zhiqiang Hou
> Sent: 2016年6月12日 12:31
> To: york sun <york@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingkai...@freescale.com; york...@freescale.com; le...@freescale.com;
&
From: Hou Zhiqiang
The register CLKCNCSR controls the frequency of all cores in the same
cluster.
Signed-off-by: Hou Zhiqiang
---
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff
Hi York,
Thanks for your comments!
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: 2016年6月8日 8:56
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingka
Hi Scott,
Thanks for your comments!
> -Original Message-
> From: Scott Wood
> Sent: 2016年6月12日 12:10
> To: Zhiqiang Hou <zhiqiang@nxp.com>; york sun <york@nxp.com>; u-
> b...@lists.denx.de; albert.u.b...@aribaud.net; scottw...@freescale.com;
>
Hi York,
Thanks for your comments!
> -Original Message-
> From: york sun
> Sent: 2016年6月12日 12:07
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingkai...@freescale.com; york...@freescale.
Hi York,
Thanks for your comments!
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: 2016年6月8日 8:51
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingka
Hi York,
Thanks for your comments!
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: 2016年6月8日 8:51
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingka
From: Hou Zhiqiang
Set the enable-method in the cpu node to PSCI, and create device
node for PSCI.
Signed-off-by: Hou Zhiqiang
---
V5:
- Moved the weak func sec_firmware_support_psci_version to sec_firmware.c.
- Correct the PSCI version value in
From: Hou Zhiqiang
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has
From: Hou Zhiqiang
So far, the PPA use PSCI to make secondary cores bootup. So when
PPA is enabled, add the CONFIG_ARMV8_PSCI to identify the SMP
boot-method between PSCI and spin-table.
Signed-off-by: Hou Zhiqiang
---
V5:
- Merged the 7th patch of
From: Hou Zhiqiang
The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.
Signed-off-by: Hou Zhiqiang
---
V5:
- Added API sec_firmware_init() implementation.
From: Hou Zhiqiang
If the PSCI and PPA is ready, skip the fixup for spin-table and
waking secondary cores. If not, change SMP method to spin-table,
and the device node of PSCI will be removed.
Signed-off-by: Hou Zhiqiang
---
V5:
- Changed the
From: Hou Zhiqiang
The sec_firmware.h is the common header file for secure monitor
firmware under ARMv8. The declaration of common APIs can be
added to this file. And the implementation of common APIs will
be abstracted to sec_firmware.c, up to now there are some weak
Hi York,
Thanks a lot for your comments and suggestions!
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: 2016年5月28日 2:06
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@fre
Hi York,
Thanks for your comments and suggestion!
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: 2016年5月28日 2:06
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
>
Hi York,
Thanks for your comments!
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: 2016年5月28日 3:59
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingka
From: Hou Zhiqiang
This framework is introduced for ARMv8 secure monitor mode firmware.
The main functions of the framework are, on EL3, verify the firmware,
load it to the secure memory and jump into it, and while it returned
to U-Boot, do some necessary setups at the
From: Hou Zhiqiang
The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.
Use the secure firmware framework to integrate FSL PPA into U-Boot.
Signed-off-by: Hou Zhiqiang
From: Hou Zhiqiang
The PPA use PSCI to make secondary cores bootup. So when PPA was
enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method
between PSCI and spin-table.
Signed-off-by: Hou Zhiqiang
---
V6:
- Refactor the integration of
From: Hou Zhiqiang
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has
From: Hou Zhiqiang
Set the enable-method in the cpu node to PSCI, and create device
node for PSCI, when PSCI was enabled.
Signed-off-by: Hou Zhiqiang
---
V6:
- Removed PSCI version 0.1 support.
V5:
- Moved the weak func
From: Hou Zhiqiang
If the PSCI and PPA is ready, skip the fixup for spin-table and
waking secondary cores. Otherwise, change SMP method to spin-table,
and the device node of PSCI will be removed.
Signed-off-by: Hou Zhiqiang
---
V6:
- no change
V5:
Hi ChenYu,
Thanks for your comments!
> -Original Message-
> From: Chen-Yu Tsai [mailto:w...@csie.org]
> Sent: 2016年6月22日 12:05
> To: Zhiqiang Hou <zhiqiang@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Albert ARIBAUD
> <albert.u.b...
Hi York,
Thanks for your comments!
> -Original Message-
> From: york sun
> Sent: 2016年6月23日 0:52
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingkai...@freescale.com; york...@freescale.
Hi York,
Thanks for your comments!
> -Original Message-
> From: york sun
> Sent: 2016年6月23日 0:22
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingkai...@freescale.com; york...@freescale.
Hi York,
Thanks for your comments!
> -Original Message-
> From: york sun
> Sent: 2016年6月23日 0:13
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingkai...@freescale.com; york...@freescale.
Hi York,
Thanks for your comments!
> -Original Message-
> From: york sun
> Sent: 2016年6月23日 0:20
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingkai...@freescale.com; york...@freescale.
Hi York,
Thanks for your comments!
> -Original Message-
> From: york sun
> Sent: 2016年6月23日 0:11
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingkai...@freescale.com; york...@freescale.
com
> > > Cc: Sun York-R58495; Hu Mingkai-B21284; nofooter
> > > Subject: RE: [PATCH V6] sf: Turn SPI flash chip into 3-Byte address
> > > mode
> > >
> > > Hi Zhiqiang,
> > >
> > > > -Original Message-
> > > > From:
From: Hou Zhiqiang
For more than 16MiB SPI flash chips, there are 3-Byte and 4-Byte address
mode, and only the 3-Byte address mode is supported in U-Boot so far.
So, reset the SPI flash to 3-Byte address mode in probe to ensure the SPI
flash work correctly, because it
From: Hou Zhiqiang
For the Spansion style SPI flashs, the Extended address control
bit (EXTADD) that control the switching between 3-Byte and 4-Byte
addressing mode is also in BAR[7]. Even if without the macro
CONFIG_SPI_FLASH_BAR, the BAR[7] should be abled to
Hi York,
> -Original Message-
> From: york sun
> Sent: 2016年1月20日 23:55
> To: Zhiqiang Hou <zhiqiang@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushw...@nxp.com>; Zhiqiang Hou <zhiqiang@freescale.com>;
> u-boot@lists.denx.de; albert.u.b...@a
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
V2
- No change.
board/freescale/ls1043ardb/ls1043ardb.c | 11 +++
include/configs/ls1043ardb.h| 9 +
2 files changed, 20 insertions(+)
diff --git
From: Hou Zhiqiang
The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.
Signed-off-by: Hou Zhiqiang
---
Tested on LS1043A RDB board
V2:
- Added
From: Hou Zhiqiang
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE
From: Hou Zhiqiang
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE
Hi Rod and Chenhui,
Can you help to answer the questions about PSCI?
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: 2016年1月23日 4:09
> To: york sun <york@nxp.com>; Zhiqiang Hou <zhiqiang@freescale.com>;
> u-boot@lists.denx.de
Hi Rod and Chenhui,
Can you help to answer the questions about PSCI?
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: 2016年1月23日 4:18
> To: Bhupesh Sharma <bhupesh.sha...@nxp.com>; york sun <york@nxp.com>;
> Zhiqiang Hou <zhiqi
+ Rod and Chenhui
> -Original Message-
> From: Zhiqiang Hou
> Sent: 2016年1月25日 11:16
> To: 'Scott Wood' <o...@buserror.net>; york sun <york@nxp.com>; Bhupesh
> Sharma <bhupesh.sha...@nxp.com>; Zhiqiang Hou
> <zhiqiang@freescale.c
Hi Rod and Chenhui,
Can you help to answer the questions about PSCI and PPA?
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: 2016年1月23日 4:22
> To: york sun <york@nxp.com>; Bhupesh Sharma <bhupesh.sha...@nxp.com>;
> Zhiqiang Hou
To: Zhiqiang Hou <zhiqiang@freescale.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; mingkai...@freescale.com; Stuart Yoder
> <stuart.yo...@nxp.com>; le...@freescale.com; prabha...@freescale.com;
> bhupesh.sha...@freescale.com; Zhiqiang Hou <zhiqiang@nxp.c
Hi Rod and Chenhui,
Can you help to answer the questions about PSCI and PPA?
> -Original Message-
> From: york sun
> Sent: 2016年1月23日 4:30
> To: Bhupesh Sharma <bhupesh.sha...@nxp.com>; Scott Wood
> <o...@buserror.net>; Zhiqiang Hou <zhiqiang@freescale
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
board/freescale/ls1043ardb/ls1043ardb.c | 11 +++
include/configs/ls1043ardb.h| 9 +
2 files changed, 20 insertions(+)
diff --git
From: Hou Zhiqiang
The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.
Signed-off-by: Hou Zhiqiang
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +
From: Hou Zhiqiang
Expose this API to make it reuseable when u-boot turn into other EL
from EL3.
Signed-off-by: Hou Zhiqiang
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 24
include/common.h| 1 +
2
Hi Prabhakar,
Thanks for your feedback!
> -Original Message-
> From: Prabhakar Kushwaha
> Sent: 2016年1月19日 22:07
> To: Zhiqiang Hou <zhiqiang@freescale.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; mingkai...@freescale.com; york...@freescale.com
>
Hi Prabhakar,
Thanks for your feedback!
> -Original Message-
> From: Prabhakar Kushwaha
> Sent: 2016年1月19日 21:54
> To: Zhiqiang Hou <zhiqiang@freescale.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; mingkai...@freescale.com; york...@freescale.com
>
Hi Chenhui,
Do you have any update about how to fixup the related device node according to
the PSCI and spin-table?
> -Original Message-
> From: york sun
> Sent: 2016年3月18日 5:09
> To: Zhiqiang Hou <zhiqiang@nxp.com>; Bhupesh Sharma
> <bhupesh.sha...
From: Hou Zhiqiang
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has
From: Hou Zhiqiang
If the PSCI and PPA is ready, skip the fixup for spin-table and
waking secondary cores. If not, change SMP method to spin-table,
and the device node of PSCI will be removed.
Signed-off-by: Hou Zhiqiang
---
V4:
- Reordered this
From: Hou Zhiqiang
So far, the PPA use PSCI to make secondary cores bootup. Add this
macro to identify the SMP boot-method between PSCI and spin-table.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change.
include/configs/ls1043ardb.h | 1 +
1 file
From: Hou Zhiqiang
The sec_firmware.h is a common header file for secure monitor
firmware under ARMv8. The common API can be added to this file.
Added APIs for secure firmware validation and getting supported
PSCI version.
Signed-off-by: Hou Zhiqiang
From: Hou Zhiqiang
The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.
Signed-off-by: Hou Zhiqiang
---
V4:
- Moved secure firmware validation API to this
From: Hou Zhiqiang
Set the enable-method in the cpu node to PSCI, and create device
node for PSCI.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change.
arch/arm/cpu/armv8/Makefile | 1 +
arch/arm/cpu/armv8/cpu-dt.c | 126
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
V4:
- Reordered this patch.
- Added checking the returned value of func ppa_init_pre().
board/freescale/ls1043ardb/ls1043ardb.c | 12
include/configs/ls1043ardb.h| 9
Hi York,
Thanks for your comments!
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: 2016年5月18日 23:16
> To: Zhiqiang Hou <zhiqiang@nxp.com>
> Cc: u-boot@lists.denx.de; albert.u.b...@aribaud.net; Scott Wood
> <o...@buserror.net>
Hi York,
Thanks a lot for your comments!
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: 2016年5月11日 3:58
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; scottw...@freescale.com;
> mingka
Hi York,
Thanks for your comments and sorry for my delay response due to PTO.
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: 2016年5月11日 3:48
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; sc
From: Hou Zhiqiang
Set the enable-method in the cpu node to PSCI, and reate device
node for PSCI.
Signed-off-by: Hou Zhiqiang
---
V3:
- new patch
arch/arm/cpu/armv8/Makefile | 1 +
arch/arm/cpu/armv8/cpu-dt.c | 126
From: Hou Zhiqiang
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
V3:
- no change
board/freescale/ls1043ardb/ls1043ardb.c | 11 +++
include/configs/ls1043ardb.h| 9 +
2 files changed, 20 insertions(+)
diff --git
From: Hou Zhiqiang
So far, the PPA use PSCI to make secondary cores bootup. Add this
macro to identify the SMP boot-method between PSCI and spin-table.
Signed-off-by: Hou Zhiqiang
---
V3:
- no change
include/configs/ls1043ardb.h | 1 +
1 file
From: Hou Zhiqiang
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE
From: Hou Zhiqiang
The sec_firmware.h is a common header file for secure monitor
firmware under ARMv8. The common API can be added to this file,
and added APIs for secure firmware validation and getting
supported PSCI version.
Signed-off-by: Hou Zhiqiang
From: Hou Zhiqiang
The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.
Signed-off-by: Hou Zhiqiang
---
V3:
- Refactor the code.
- Add secure
From: Hou Zhiqiang
If the PSCI and PPA is ready, skip the fixup for spin-table and
waking secondary cores. If not, change SMP method to spin-table,
and the device node of PSCI will be removed.
Signed-off-by: Hou Zhiqiang
---
V3:
- new patch
Hi York,
Thanks for your comments!
> -Original Message-
> From: york sun
> Sent: 2016年7月21日 5:15
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; w...@denx.de; Prabhakar Kushwaha
> <prabhakar.kushw...@nxp.com&
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
arch/arm/lib/psci-dt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index af49c24..baf6d70 100644
--- a/arch/arm/lib/psci-dt.c
+++
From: Hou Zhiqiang
Identify the PSCI node only by its name, so removed the code finding
it by compatible string.
Signed-off-by: Hou Zhiqiang
---
arch/arm/lib/psci-dt.c | 17 -
1 file changed, 17 deletions(-)
diff --git
From: Hou Zhiqiang
The PPA binary may be stored on QSPI flash instead of NOR.
So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
by addition of a new QSPI specific flag.
Signed-off-by: Hou Zhiqiang
From: Hou Zhiqiang
Appended the compatible strings of old version PSCI to the latest version
supported. And there are some psci functions' property must be added to DT
only for psci version 0.1, such as 'cpu_on' 'cpu_off' etc.
Note:
The PSCI version 0.1 isn't supported by
Hi York,
Thanks for your comments!
> -Original Message-
> From: york sun
> Sent: 2016年7月29日 23:37
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; hdego...@redhat.com; w...@csie.org; Hongbo
> Zhang <hongbo.zh...@nx
From: Hou Zhiqiang
Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the
From: Hou Zhiqiang
Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.
Signed-off-by: Hou Zhiqiang
Hi York,
Thanks for your comments!
> -Original Message-
> From: york sun
> Sent: 2016年8月2日 0:10
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; hdego...@redhat.com; w...@csie.org; Hongbo
> Zhang <hongbo.zh...@nx
Hi All,
Drop this patch.
> -Original Message-
> From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> Sent: 2016年8月2日 19:03
> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> <york@nxp.com>; w...@denx.de; Prabhakar Kushwaha
> <prabhakar.k
From: Hou Zhiqiang
Add this API to make the individual device is able to be set to
the specified permission.
Signed-off-by: Hou Zhiqiang
---
V2
- no change
board/freescale/common/ns_access.c | 34 --
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
.../include/asm/arch-fsl-layerscape/ns_access.h| 1 +
board/freescale/common/ns_access.c | 28 ++
include/fsl_csu.h | 1 +
3
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
V2
- mv disable_pcie_ns_access() to set_pcie_ns_access().
.../include/asm/arch-fsl-layerscape/ns_access.h| 1 +
board/freescale/common/ns_access.c | 28 ++
From: Hou Zhiqiang
As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang
Hi Prabhakar,
Thanks for your comments!
> -Original Message-
> From: Prabhakar Kushwaha
> Sent: 2016年7月21日 12:28
> To: york sun <york@nxp.com>; Zhiqiang Hou <zhiqiang@nxp.com>; u-
> b...@lists.denx.de; albert.u.b...@aribaud.net; w...@denx.de;
> alis
Hi Prabhakar,
Thanks for your comments!
> -Original Message-
> From: Prabhakar Kushwaha
> Sent: 2016年7月21日 12:39
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; york sun <york@nxp.com>; w...@denx.de;
> alis
Hi All,
Any comments?
> -Original Message-
> From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> Sent: 2016年7月4日 14:28
> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> <york@nxp.com>; w...@denx.de; Prabhakar Kushwaha
> <prabhakar.
Hi York,
Thanks for your comments!
> -Original Message-
> From: york sun
> Sent: 2016年7月19日 23:46
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; w...@denx.de; Prabhakar Kushwaha
> <prabhakar.kushw...@nxp.com&
Hi York,
Thanks a lot for your comments!
> -Original Message-
> From: york sun
> Sent: 2016年7月20日 0:02
> To: Zhiqiang Hou <zhiqiang@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; w...@denx.de; Prabhakar Kushwaha
> <prabhakar.kushw...@nxp.com&
From: Hou Zhiqiang
The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.
Use the secure firmware framework to integrate FSL PPA into U-Boot.
Signed-off-by: Hou Zhiqiang
From: Hou Zhiqiang
If the PSCI and PPA is ready, skip the fixup for spin-table and
waking secondary cores. Otherwise, change SMP method to spin-table,
and the device node of PSCI will be removed.
Signed-off-by: Hou Zhiqiang
---
V7:
- Removed the
From: Hou Zhiqiang
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has
From: Hou Zhiqiang
This framework is introduced for ARMv8 secure monitor mode firmware.
The main functions of the framework are, on EL3, verify the firmware,
load it to the secure memory and jump into it, and while it returned
to U-Boot, do some necessary setups at the
From: Hou Zhiqiang
Set the enable-method in the cpu node to PSCI, and create device
node for PSCI, when PSCI was enabled.
Signed-off-by: Hou Zhiqiang
---
V7:
- Moved the PSCI device node fixup code of both armv7 and armv8 to
arch/arm/lib/psci-dt.c.
From: Hou Zhiqiang
The PPA use PSCI to make secondary cores bootup. So when PPA was
enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method
between PSCI and spin-table.
Signed-off-by: Hou Zhiqiang
---
V7:
- No change.
V6:
- Refactor the
From: Hou Zhiqiang
Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the
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