Re: [U-Boot] [PATCH v2] ARM: tegra: Add support for norrin board
On Thu, Jul 31, 2014 at 04:21:43PM -0700, Stephen Warren wrote: On 07/31/2014 05:14 PM, Allen Martin wrote: Norrin (PM370) is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC. This board is also refered to as nyan in the ChromeOS trees. At a *very* quick glance, this looks OK. But, you'll need to do a bit of work to rebase it onto the latest u-boot/master. Kconfig has been introduced now, so you'll need to do at least: * Don't touch boards.cfg (it's been removed) * Add configs/norrin_defconfig * Add board/nvidia/norrin/MAINTAINERS I think that's it. I based the patch on u-boot-tegra/master, is there a tegra branch that has already been rebased? Or has the upstream workflow changed, so we're not collecting patches on u-boot-tegra for next merge window? -Allen nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] ARM: tegra: Add support for norrin board
Norrin (PM370) is a Tegra124 clamshell board that is very similar to
venice2, but it has a different panel, the sdcard cd and wp sense are
flipped, and it has a different revision of the AS3722 PMIC. This
board is also refered to as nyan in the ChromeOS trees.
Signed-off-by: Allen Martin amar...@nvidia.com
---
Changes from v2:
-Rebased to u-boot/master
-Changed from boards.cfg to Kconfig based configuration
-Added MAINTAINERS file for Norrin board
Changes from v1:
-Generated pinmux with tegra-pinmux-scripts directly from pinmux
spreadsheet.
-Don't try to reuse venice2 board files
---
arch/arm/Kconfig | 4 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra124-norrin.dts | 91 +
board/nvidia/norrin/Kconfig| 24 +++
board/nvidia/norrin/MAINTAINERS| 6 +
board/nvidia/norrin/Makefile | 9 +
board/nvidia/norrin/norrin.c | 29 +++
board/nvidia/norrin/pinmux-config-norrin.h | 287 +
board/nvidia/venice2/as3722_init.h | 2 +-
configs/norrin_defconfig | 4 +
include/configs/norrin.h | 81
11 files changed, 537 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/tegra124-norrin.dts
create mode 100644 board/nvidia/norrin/Kconfig
create mode 100644 board/nvidia/norrin/MAINTAINERS
create mode 100644 board/nvidia/norrin/Makefile
create mode 100644 board/nvidia/norrin/norrin.c
create mode 100644 board/nvidia/norrin/pinmux-config-norrin.h
create mode 100644 configs/norrin_defconfig
create mode 100644 include/configs/norrin.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e385eda94cdf..f4e0f5a42c14 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -716,6 +716,9 @@ config TARGET_DALMORE
config TARGET_JETSON_TK1
bool Support jetson-tk1
+config TARGET_NORRIN
+ bool Support norrin
+
config TARGET_VENICE2
bool Support venice2
@@ -912,6 +915,7 @@ source board/nvidia/cardhu/Kconfig
source board/nvidia/dalmore/Kconfig
source board/nvidia/harmony/Kconfig
source board/nvidia/jetson-tk1/Kconfig
+source board/nvidia/norrin/Kconfig
source board/nvidia/seaboard/Kconfig
source board/nvidia/venice2/Kconfig
source board/nvidia/ventana/Kconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6e2e313829c1..e61e306c5c23 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -24,6 +24,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra30-tec-ng.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
+ tegra124-norrin.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
diff --git a/arch/arm/dts/tegra124-norrin.dts b/arch/arm/dts/tegra124-norrin.dts
new file mode 100644
index ..fdf000cf75ec
--- /dev/null
+++ b/arch/arm/dts/tegra124-norrin.dts
@@ -0,0 +1,91 @@
+/dts-v1/;
+
+#include tegra124.dtsi
+
+/ {
+ model = NVIDIA Norrin;
+ compatible = nvidia,norrin, nvidia,tegra124;
+
+ aliases {
+ i2c0 = /i2c@7000d000;
+ i2c1 = /i2c@7000c000;
+ i2c2 = /i2c@7000c400;
+ i2c3 = /i2c@7000c500;
+ i2c4 = /i2c@7000c700;
+ i2c5 = /i2c@7000d100;
+ sdhci0 = /sdhci@700b0600;
+ sdhci1 = /sdhci@700b0400;
+ spi0 = /spi@7000d400;
+ spi1 = /spi@7000da00;
+ usb0 = /usb@7d00;
+ usb1 = /usb@7d008000;
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x8000 0x8000;
+ };
+
+ i2c@7000c000 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c400 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c500 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c700 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ i2c@7000d100 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ spi@7000d400 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
+
+ spi@7000da00 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
+
+ sdhci@700b0400 {
+ status = okay;
+ cd-gpios = gpio 170 1; /* gpio PV2 */
+ power-gpios = gpio 136 0; /* gpio PR0 */
+ bus-width = 4;
+ };
+
+ sdhci@700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ usb@7d00 {
+ status
[U-Boot] [PATCH v2] ARM: tegra: Add support for norrin board
Norrin (PM370) is a Tegra124 clamshell board that is very similar to
venice2, but it has a different panel, the sdcard cd and wp sense are
flipped, and it has a different revision of the AS3722 PMIC. This
board is also refered to as nyan in the ChromeOS trees.
Signed-off-by: Allen Martin amar...@nvidia.com
---
Changes from v1:
-Generated pinmux with tegra-pinmux-scripts directly from pinmux
spreadsheet.
-Don't try to reuse venice2 board files
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/tegra124-norrin.dts | 91 +
board/nvidia/norrin/Makefile | 9 +
board/nvidia/norrin/norrin.c | 29 +++
board/nvidia/norrin/pinmux-config-norrin.h | 287 +
board/nvidia/venice2/as3722_init.h | 2 +-
boards.cfg | 1 +
include/configs/norrin.h | 81
8 files changed, 500 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/tegra124-norrin.dts
create mode 100644 board/nvidia/norrin/Makefile
create mode 100644 board/nvidia/norrin/norrin.c
create mode 100644 board/nvidia/norrin/pinmux-config-norrin.h
create mode 100644 include/configs/norrin.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 55546152b94b..73a1f141cf04 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -23,6 +23,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra30-tec-ng.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
+ tegra124-norrin.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
diff --git a/arch/arm/dts/tegra124-norrin.dts b/arch/arm/dts/tegra124-norrin.dts
new file mode 100644
index ..fdf000cf75ec
--- /dev/null
+++ b/arch/arm/dts/tegra124-norrin.dts
@@ -0,0 +1,91 @@
+/dts-v1/;
+
+#include tegra124.dtsi
+
+/ {
+ model = NVIDIA Norrin;
+ compatible = nvidia,norrin, nvidia,tegra124;
+
+ aliases {
+ i2c0 = /i2c@7000d000;
+ i2c1 = /i2c@7000c000;
+ i2c2 = /i2c@7000c400;
+ i2c3 = /i2c@7000c500;
+ i2c4 = /i2c@7000c700;
+ i2c5 = /i2c@7000d100;
+ sdhci0 = /sdhci@700b0600;
+ sdhci1 = /sdhci@700b0400;
+ spi0 = /spi@7000d400;
+ spi1 = /spi@7000da00;
+ usb0 = /usb@7d00;
+ usb1 = /usb@7d008000;
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x8000 0x8000;
+ };
+
+ i2c@7000c000 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c400 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c500 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c700 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ i2c@7000d100 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ spi@7000d400 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
+
+ spi@7000da00 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
+
+ sdhci@700b0400 {
+ status = okay;
+ cd-gpios = gpio 170 1; /* gpio PV2 */
+ power-gpios = gpio 136 0; /* gpio PR0 */
+ bus-width = 4;
+ };
+
+ sdhci@700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ usb@7d00 {
+ status = okay;
+ dr_mode = otg;
+ nvidia,vbus-gpio = gpio 108 0; /* gpio PN4, USB_VBUS_EN0 */
+ };
+
+ usb@7d008000 {
+ status = okay;
+ nvidia,vbus-gpio = gpio 109 0; /* gpio PN5, USB_VBUS_EN1 */
+ };
+};
diff --git a/board/nvidia/norrin/Makefile b/board/nvidia/norrin/Makefile
new file mode 100644
index ..5e490bb38f30
--- /dev/null
+++ b/board/nvidia/norrin/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# NVIDIA Corporation www.nvidia.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ../venice2/as3722_init.o
+obj-y += norrin.o
diff --git a/board/nvidia/norrin/norrin.c b/board/nvidia/norrin/norrin.c
new file mode 100644
index ..6f0050c4cd2f
--- /dev/null
+++ b/board/nvidia/norrin/norrin.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation www.nvidia.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/gpio.h
+#include asm/arch/pinmux.h
+#include pinmux-config-norrin.h
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux
Re: [U-Boot] [PATCH] ARM: tegra: Add support for norrin board
On Mon, Jun 30, 2014 at 02:32:20PM -0700, Stephen Warren wrote: On 06/30/2014 02:53 PM, Allen Martin wrote: Norrin (PM370) is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd sense is flipped, and it has a different revision of the AS3722 PMIC. Reuse the venice2 config with a norrin dtb. This board is also refered to as nyan in the ChromeOS trees. Isn't the pinmux different too? I think this patch should contain board/nvidia/norrin/pinmux-config-norrin.h shouldn't it? That in turn would mean adding Norrin support to tegra-pinmux-scripts. Of course, if they really do have 100% identical pinmux, then there's no issue. I'm skeptical though. AFAIK they really do have identical pinmux, I'll double check the pinmux spreadsheet to make sure. There's another unintended side effect of reusing the venice2 board this way that I discovered after posting this. It causes CONFIG_SYS_BOARD to be set to venice2 still, which causes the board_name environment variable to be set to venice2, which causes boot.scr to look for a venice2 dtb. It may be cleaner to make norrin a proper board, and just have it #include the vencie2 pinmux. -Allen nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM: tegra: Add support for norrin board
Norrin (PM370) is a Tegra124 clamshell board that is very similar to
venice2, but it has a different panel, the sdcard cd sense is flipped,
and it has a different revision of the AS3722 PMIC. Reuse the venice2
config with a norrin dtb. This board is also refered to as nyan in
the ChromeOS trees.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/tegra124-norrin.dts | 91 ++
board/nvidia/venice2/as3722_init.h | 2 +-
boards.cfg | 1 +
include/configs/venice2.h | 9
5 files changed, 104 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/tegra124-norrin.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 55546152b94b..414f206cb6f0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -23,7 +23,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra30-tec-ng.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
- tegra124-venice2.dtb
+ tegra124-venice2.dtb \
+ tegra124-norrin.dtb
dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
diff --git a/arch/arm/dts/tegra124-norrin.dts b/arch/arm/dts/tegra124-norrin.dts
new file mode 100644
index ..fdf000cf75ec
--- /dev/null
+++ b/arch/arm/dts/tegra124-norrin.dts
@@ -0,0 +1,91 @@
+/dts-v1/;
+
+#include tegra124.dtsi
+
+/ {
+ model = NVIDIA Norrin;
+ compatible = nvidia,norrin, nvidia,tegra124;
+
+ aliases {
+ i2c0 = /i2c@7000d000;
+ i2c1 = /i2c@7000c000;
+ i2c2 = /i2c@7000c400;
+ i2c3 = /i2c@7000c500;
+ i2c4 = /i2c@7000c700;
+ i2c5 = /i2c@7000d100;
+ sdhci0 = /sdhci@700b0600;
+ sdhci1 = /sdhci@700b0400;
+ spi0 = /spi@7000d400;
+ spi1 = /spi@7000da00;
+ usb0 = /usb@7d00;
+ usb1 = /usb@7d008000;
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x8000 0x8000;
+ };
+
+ i2c@7000c000 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c400 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c500 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000c700 {
+ status = okay;
+ clock-frequency = 10;
+ };
+
+ i2c@7000d000 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ i2c@7000d100 {
+ status = okay;
+ clock-frequency = 40;
+ };
+
+ spi@7000d400 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
+
+ spi@7000da00 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
+
+ sdhci@700b0400 {
+ status = okay;
+ cd-gpios = gpio 170 1; /* gpio PV2 */
+ power-gpios = gpio 136 0; /* gpio PR0 */
+ bus-width = 4;
+ };
+
+ sdhci@700b0600 {
+ status = okay;
+ bus-width = 8;
+ };
+
+ usb@7d00 {
+ status = okay;
+ dr_mode = otg;
+ nvidia,vbus-gpio = gpio 108 0; /* gpio PN4, USB_VBUS_EN0 */
+ };
+
+ usb@7d008000 {
+ status = okay;
+ nvidia,vbus-gpio = gpio 109 0; /* gpio PN5, USB_VBUS_EN1 */
+ };
+};
diff --git a/board/nvidia/venice2/as3722_init.h
b/board/nvidia/venice2/as3722_init.h
index a7b24039f6aa..7c80ef09387b 100644
--- a/board/nvidia/venice2/as3722_init.h
+++ b/board/nvidia/venice2/as3722_init.h
@@ -18,7 +18,7 @@
#define AS3722_LDO6VOLTAGE_REG 0x16/* VDD_SDMMC */
#define AS3722_LDCONTROL_REG 0x4E
-#ifdef CONFIG_BOARD_JETSON_TK1
+#if defined(CONFIG_BOARD_JETSON_TK1) || defined(CONFIG_BOARD_NORRIN)
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
#else
#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
diff --git a/boards.cfg b/boards.cfg
index 5a85fad48095..3950688ba30b 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -395,6 +395,7 @@ Active arm armv7 zynqxilinx
zynq
Active arm armv7:arm720t tegra114nvidia dalmore
dalmore -
Tom Warren twar...@nvidia.com
Active arm armv7:arm720t tegra124nvidia jetson-tk1
jetson-tk1jetson-tk1:BOARD_JETSON_TK1=
Stephen Warren swar...@nvidia.com
Active
Re: [U-Boot] [PATCH v2 07/13] sf: winbond: add W25Q32DW
On Fri, May 24, 2013 at 01:39:51PM -0700, Jagan Teki wrote:
Hi,
Any update on this.
Thanks,
Jagan.
On Thu, May 23, 2013 at 1:15 PM, Jagan Teki jagannadh.t...@gmail.com wrote:
Hi Allen,
On Sun, Mar 17, 2013 at 10:28 AM, Allen Martin amar...@nvidia.com wrote:
Add support for Winbond W25Q32DW 32Mbit part
Signed-off-by: Allen Martin amar...@nvidia.com
---
drivers/mtd/spi/winbond.c |5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index 4418302..3560fcb 100644
--- a/drivers/mtd/spi/winbond.c
+++ b/drivers/mtd/spi/winbond.c
@@ -68,6 +68,11 @@ static const struct winbond_spi_flash_params
winbond_spi_flash_table[] = {
.name = W25Q80,
},
{
+ .id = 0x6016,
+ .nr_blocks = 512,
nr_blocks here should have 64 instead of 512.
please let me know, I will add correction-patch for this.
You're right, it's a 32Mbit part, so nr_blocks should be 64, thanks
for finding this.
-Allen
--
nvpublic
___
U-Boot mailing list
U-Boot@lists.denx.de
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Re: [U-Boot] [PATCH] Tegra: clk: always use find_best_divider() for periph clocks
On Mon, May 13, 2013 at 10:24:17AM -0700, Tom Warren wrote: Allen, -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Friday, May 10, 2013 8:06 PM To: Allen Martin Cc: Tom Warren; Stephen Warren; U-Boot Mailing List Subject: Re: [PATCH] Tegra: clk: always use find_best_divider() for periph clocks On Fri, May 10, 2013 at 8:56 PM, Allen Martin amar...@nvidia.com wrote: When adjusting peripheral clocks always use find_best_divider() instead of clk_get_divider() even when a secondary divider is not available. In the case where is requested clock is too slow to be derived from the parent clock this allows a best effort to get close to the requested clock. This comes up for commands like sf where the user can pass a clock speed on the command line or sspi where the clock is hardcoded to 1MHz, but the Tegra114 SPI controller can't go that low. Did you test all other periphs and check their config'd clocks to make sure this doesn't affect anything else negatively? This proc is pretty universal (called by clock_start_periph_pll, which is used by MMC/I2C/USB/display drivers). I tested a handful of peripherals on dalmore, but you're right this is generic enough that it warrants a more thorough test scrubbing. I'll try to hit all the peripherals I can across all chipsets and report back. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Tegra: clk: always use find_best_divider() for periph clocks
On Mon, May 13, 2013 at 10:24:17AM -0700, Tom Warren wrote: Allen, -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: Friday, May 10, 2013 8:06 PM To: Allen Martin Cc: Tom Warren; Stephen Warren; U-Boot Mailing List Subject: Re: [PATCH] Tegra: clk: always use find_best_divider() for periph clocks On Fri, May 10, 2013 at 8:56 PM, Allen Martin amar...@nvidia.com wrote: When adjusting peripheral clocks always use find_best_divider() instead of clk_get_divider() even when a secondary divider is not available. In the case where is requested clock is too slow to be derived from the parent clock this allows a best effort to get close to the requested clock. This comes up for commands like sf where the user can pass a clock speed on the command line or sspi where the clock is hardcoded to 1MHz, but the Tegra114 SPI controller can't go that low. Did you test all other periphs and check their config'd clocks to make sure this doesn't affect anything else negatively? This proc is pretty universal (called by clock_start_periph_pll, which is used by MMC/I2C/USB/display drivers). Testing done: tegra20 seaboard: usb read/write i2c read emmc read sdcard read/write lcd uart read/write tegra20 trimslice: spi read uart read/write tegra30 cardhu: spi read/write uart read/write i2c read sdcard read/write emmc read tegra114 dalmore: iwc read sdcard read/write emmc read uart read/write -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Tegra: clk: always use find_best_divider() for periph clocks
When adjusting peripheral clocks always use find_best_divider() instead of clk_get_divider() even when a secondary divider is not available. In the case where is requested clock is too slow to be derived from the parent clock this allows a best effort to get close to the requested clock. This comes up for commands like sf where the user can pass a clock speed on the command line or sspi where the clock is hardcoded to 1MHz, but the Tegra114 SPI controller can't go that low. Signed-off-by: Allen Martin amar...@nvidia.com --- arch/arm/cpu/tegra-common/clock.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 9156d00..268fb91 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -321,17 +321,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, unsigned effective_rate; int mux_bits, divider_bits, source; int divider; + int xdiv = 0; /* work out the source clock and set it */ source = get_periph_clock_source(periph_id, parent, mux_bits, divider_bits); + divider = find_best_divider(divider_bits, pll_rate[parent], + rate, xdiv); if (extra_div) - divider = find_best_divider(divider_bits, pll_rate[parent], - rate, extra_div); - else - divider = clk_get_divider(divider_bits, pll_rate[parent], - rate); + *extra_div = xdiv; + assert(divider = 0); if (adjust_periph_pll(periph_id, source, mux_bits, divider)) return -1U; -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] crc32: Correct endianness of crc32 result
On Fri, Apr 05, 2013 at 04:11:10PM -0700, Simon Glass wrote: When crc32 is handled by the hash library, it requires the data to be in big-endian format, since it reads it byte-wise. Thus at present the 'crc32' command reports incorrect data. For example, previously we might see: Peach # crc32 4000 100 CRC32 for 4000 ... 40ff == 0d968558 but instead with the hash library we see: Peach # crc32 4000 100 CRC32 for 4000 ... 40ff == 5885960d Correct this. Signed-off-by: Simon Glass s...@chromium.org Reviewed-by: Vadim Bendebury vben...@google.com --- lib/crc32.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/lib/crc32.c b/lib/crc32.c index 76205da..94720bf 100644 --- a/lib/crc32.c +++ b/lib/crc32.c @@ -10,6 +10,7 @@ #ifndef USE_HOSTCC #include common.h +#include asm/unaligned.h #endif #include compiler.h #include u-boot/crc.h @@ -256,5 +257,10 @@ void crc32_wd_buf(const unsigned char *input, unsigned int ilen, uint32_t crc; crc = crc32_wd(0, input, ilen, chunk_sz); +#ifdef USE_HOSTCC + crc = htobe32(crc); memcpy(output, crc, sizeof(crc)); +#else + put_unaligned_be32(crc, output); +#endif } -- 1.8.1.3 Tested on Tegra114 Dalmore, verified crc32 comes out as expected now. Reviewed-by: Allen Martin amar...@nvidia.com Tested-by: Allen Martin amar...@nvidia.com -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MAKEALL: Fix case substitution for old bash
On Fri, Mar 22, 2013 at 10:37:03AM -0700, York Sun wrote:
Bash ver 3.x doesn't support the parameter expansion with case
substitution. Use tr instead.
Signed-off-by: York Sun york...@freescale.com
Acked-by: Allen Martin amar...@nvidia.com
---
Removed RFC from subject line.
MAKEALL |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAKEALL b/MAKEALL
index c1d8957..ac92ef6 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -664,7 +664,7 @@ build_target() {
export BUILD_DIR=${output_dir}
target_arch=$(get_target_arch ${target})
- eval cross_toolchain=\$CROSS_COMPILE_${target_arch^^}
+ eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr
'[:lower:]' '[:upper:]'`
if [ ${cross_toolchain} ] ; then
MAKE=make CROSS_COMPILE=${cross_toolchain}
elif [ ${CROSS_COMPILE} ] ; then
--
1.7.9.5
--
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Re: [U-Boot] [RFC] MAKEALL: Fix case substitution for old bash
On Thu, Mar 21, 2013 at 12:58:15PM -0700, York Sun wrote:
Bash ver 3.x doesn't support the parameter expansion with case
substitution. Use tr instead.
Signed-off-by: York Sun york...@freescale.com
---
I am not sure if using 'tr' is a good idea. Any suggestion is welcomed.
MAKEALL |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAKEALL b/MAKEALL
index c1d8957..ac92ef6 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -664,7 +664,7 @@ build_target() {
export BUILD_DIR=${output_dir}
target_arch=$(get_target_arch ${target})
- eval cross_toolchain=\$CROSS_COMPILE_${target_arch^^}
+ eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr
'[:lower:]' '[:upper:]'`
Looks fine to me. I'm not sure if there's a preference between using
backtick or $() for shell commands, it looks like both are used in the
script.
if [ ${cross_toolchain} ] ; then
MAKE=make CROSS_COMPILE=${cross_toolchain}
elif [ ${CROSS_COMPILE} ] ; then
--
1.7.9.5
PS: What happened with your bool fixup patch? I'm a big fan of that
patch :^)
-Allen
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[U-Boot] [PATCH v2 10/13] tegra114: fdt: add SPI blocks
Add nodes for t114 SPI controller hardware
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/dts/tegra114.dtsi | 72
1 file changed, 72 insertions(+)
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 92e69f6..64e2e083 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -120,4 +120,76 @@
clocks = tegra_car 47;
status = disabled;
};
+
+ spi@7000d400 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000d400 0x200;
+ interrupts = 0 59 0x04;
+ nvidia,dma-request-selector = apbdma 15;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC1, PLLP_OUT0 */
+ clocks = tegra_car 41;
+ };
+
+ spi@7000d600 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000d600 0x200;
+ interrupts = 0 82 0x04;
+ nvidia,dma-request-selector = apbdma 16;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC2, PLLP_OUT0 */
+ clocks = tegra_car 44;
+ };
+
+ spi@7000d800 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000d480 0x200;
+ interrupts = 0 83 0x04;
+ nvidia,dma-request-selector = apbdma 17;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC3, PLLP_OUT0 */
+ clocks = tegra_car 46;
+ };
+
+ spi@7000da00 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000da00 0x200;
+ interrupts = 0 93 0x04;
+ nvidia,dma-request-selector = apbdma 18;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC4, PLLP_OUT0 */
+ clocks = tegra_car 68;
+ };
+
+ spi@7000dc00 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000dc00 0x200;
+ interrupts = 0 94 0x04;
+ nvidia,dma-request-selector = apbdma 27;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC5, PLLP_OUT0 */
+ clocks = tegra_car 104;
+ };
+
+ spi@7000de00 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000de00 0x200;
+ interrupts = 0 79 0x04;
+ nvidia,dma-request-selector = apbdma 28;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC6, PLLP_OUT0 */
+ clocks = tegra_car 105;
+ };
};
--
1.7.10.4
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[U-Boot] [PATCH v2 03/13] tegra: spi: remove non fdt support
Remove non fdt support from tegra20 and tegra30 SPI drivers in
preparation of new common fdt based SPI driver front end.
Signed-off-by: Allen Martin amar...@nvidia.com
---
drivers/spi/tegra20_sflash.c | 12
drivers/spi/tegra20_slink.c | 29 -
2 files changed, 4 insertions(+), 37 deletions(-)
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index c6af30f..3b1b6f8 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -61,6 +61,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
unsigned int max_hz, unsigned int mode)
{
struct tegra_spi_slave *spi;
+ int node;
if (!spi_cs_is_valid(bus, cs)) {
printf(SPI error: unsupported bus %d / chip select %d\n,
@@ -81,9 +82,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
}
spi-slave.bus = bus;
spi-slave.cs = cs;
-#ifdef CONFIG_OF_CONTROL
- int node = fdtdec_next_compatible(gd-fdt_blob, 0,
- COMPAT_NVIDIA_TEGRA20_SFLASH);
+
+ node = fdtdec_next_compatible(gd-fdt_blob, 0,
+ COMPAT_NVIDIA_TEGRA20_SFLASH);
if (node 0) {
debug(%s: cannot locate sflash node\n, __func__);
return NULL;
@@ -108,11 +109,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
debug(%s: could not decode periph id\n, __func__);
return NULL;
}
-#else
- spi-regs = (struct spi_tegra *)NV_PA_SPI_BASE;
- spi-freq = TEGRA_SPI_MAX_FREQ;
- spi-periph_id = PERIPH_ID_SPI1;
-#endif
if (max_hz spi-freq) {
debug(%s: limiting frequency from %u to %u\n, __func__,
spi-freq, max_hz);
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index a6de4ce..c794054 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -116,7 +116,6 @@ void spi_init(void)
{
struct tegra_spi_ctrl *ctrl;
int i;
-#ifdef CONFIG_OF_CONTROL
int node = 0;
int count;
int node_list[CONFIG_TEGRA_SLINK_CTRLS];
@@ -152,34 +151,6 @@ void spi_init(void)
debug(%s: found controller at %p, freq = %u, periph_id = %d\n,
__func__, ctrl-regs, ctrl-freq, ctrl-periph_id);
}
-#else
- for (i = 0; i CONFIG_TEGRA_SLINK_CTRLS; i++) {
- ctrl = spi_ctrls[i];
- u32 base_regs[] = {
- NV_PA_SLINK1_BASE,
- NV_PA_SLINK2_BASE,
- NV_PA_SLINK3_BASE,
- NV_PA_SLINK4_BASE,
- NV_PA_SLINK5_BASE,
- NV_PA_SLINK6_BASE,
- };
- int periph_ids[] = {
- PERIPH_ID_SBC1,
- PERIPH_ID_SBC2,
- PERIPH_ID_SBC3,
- PERIPH_ID_SBC4,
- PERIPH_ID_SBC5,
- PERIPH_ID_SBC6,
- };
- ctrl-regs = (struct slink_tegra *)base_regs[i];
- ctrl-freq = TEGRA_SPI_MAX_FREQ;
- ctrl-periph_id = periph_ids[i];
- ctrl-valid = 1;
-
- debug(%s: found controller at %p, freq = %u, periph_id = %d\n,
- __func__, ctrl-regs, ctrl-freq, ctrl-periph_id);
- }
-#endif
}
int spi_claim_bus(struct spi_slave *slave)
--
1.7.10.4
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[U-Boot] [PATCH v2 02/13] tegra: spi: rename tegra SPI drivers
Rename tegra SPI drivers to tegra20_flash and tegra20_slink in
preparation for commonization and addition of tegra114_spi.
Signed-off-by: Allen Martin amar...@nvidia.com
---
.../{arch-tegra/tegra_spi.h = arch-tegra20/tegra20_sflash.h}|6 +++---
.../{arch-tegra/tegra_slink.h = arch-tegra20/tegra20_slink.h} |6 +++---
board/nvidia/common/board.c |2 +-
drivers/spi/Makefile |4 ++--
drivers/spi/{tegra_spi.c = tegra20_sflash.c}|2 +-
drivers/spi/{tegra_slink.c = tegra20_slink.c} |2 +-
include/configs/cardhu.h |2 +-
include/configs/trimslice.h |2 +-
8 files changed, 13 insertions(+), 13 deletions(-)
rename arch/arm/include/asm/{arch-tegra/tegra_spi.h =
arch-tegra20/tegra20_sflash.h} (96%)
rename arch/arm/include/asm/{arch-tegra/tegra_slink.h =
arch-tegra20/tegra20_slink.h} (97%)
rename drivers/spi/{tegra_spi.c = tegra20_sflash.c} (99%)
rename drivers/spi/{tegra_slink.c = tegra20_slink.c} (99%)
diff --git a/arch/arm/include/asm/arch-tegra/tegra_spi.h
b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
similarity index 96%
rename from arch/arm/include/asm/arch-tegra/tegra_spi.h
rename to arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
index d53a93f..26a8402 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_spi.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
@@ -22,8 +22,8 @@
* MA 02111-1307 USA
*/
-#ifndef _TEGRA_SPI_H_
-#define _TEGRA_SPI_H_
+#ifndef _TEGRA20_SPI_H_
+#define _TEGRA20_SPI_H_
#include asm/types.h
@@ -72,4 +72,4 @@ struct spi_tegra {
#define SPI_TIMEOUT1000
#define TEGRA_SPI_MAX_FREQ 5200
-#endif /* _TEGRA_SPI_H_ */
+#endif /* _TEGRA20_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/tegra_slink.h
b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
similarity index 97%
rename from arch/arm/include/asm/arch-tegra/tegra_slink.h
rename to arch/arm/include/asm/arch-tegra20/tegra20_slink.h
index 74804b5..afa9b36 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_slink.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
@@ -22,8 +22,8 @@
* MA 02111-1307 USA
*/
-#ifndef _TEGRA_SLINK_H_
-#define _TEGRA_SLINK_H_
+#ifndef _TEGRA30_SPI_H_
+#define _TEGRA30_SPI_H_
#include asm/types.h
@@ -81,4 +81,4 @@ struct slink_tegra {
#define SPI_TIMEOUT1000
#define TEGRA_SPI_MAX_FREQ 5200
-#endif /* _TEGRA_SLINK_H_ */
+#endif /* _TEGRA30_SPI_H_ */
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index b6e6566..87a418b 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -132,7 +132,7 @@ int board_init(void)
clock_init();
clock_verify();
-#if defined(CONFIG_TEGRA_SPI) || defined(CONFIG_TEGRA_SLINK)
+#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK)
pin_mux_spi();
spi_init();
#endif
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 83abcbd..8470c34 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -45,8 +45,8 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
-COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o
-COBJS-$(CONFIG_TEGRA_SLINK) += tegra_slink.o
+COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
+COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS := $(COBJS-y)
diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra20_sflash.c
similarity index 99%
rename from drivers/spi/tegra_spi.c
rename to drivers/spi/tegra20_sflash.c
index 2662923..c6af30f 100644
--- a/drivers/spi/tegra_spi.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -29,7 +29,7 @@
#include asm/arch/clock.h
#include asm/arch/pinmux.h
#include asm/arch-tegra/clk_rst.h
-#include asm/arch-tegra/tegra_spi.h
+#include asm/arch-tegra20/tegra20_sflash.h
#include spi.h
#include fdtdec.h
diff --git a/drivers/spi/tegra_slink.c b/drivers/spi/tegra20_slink.c
similarity index 99%
rename from drivers/spi/tegra_slink.c
rename to drivers/spi/tegra20_slink.c
index 2c41fab..a6de4ce 100644
--- a/drivers/spi/tegra_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -27,7 +27,7 @@
#include asm/gpio.h
#include asm/arch/clock.h
#include asm/arch-tegra/clk_rst.h
-#include asm/arch-tegra/tegra_slink.h
+#include asm/arch-tegra20/tegra20_slink.h
#include spi.h
#include fdtdec.h
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 55dc83d..6a99175 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -60,7 +60,7 @@
#define CONFIG_SYS_MMC_ENV_PART2
/* SPI */
-#define CONFIG_TEGRA_SLINK
+#define CONFIG_TEGRA20_SLINK
#define CONFIG_TEGRA_SLINK_CTRLS 6
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
[U-Boot] [PATCH v2 05/13] tegra20: spi: move fdt probe to spi_init
Make the tegra20 SPI driver similar to the tegra30 (and soon to be
tegra114) SPI drivers in preparation of common fdt SPI driver front
end.
Signed-off-by: Allen Martin amar...@nvidia.com
---
drivers/spi/tegra20_sflash.c | 110 +-
1 file changed, 67 insertions(+), 43 deletions(-)
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 6e72c8e..bb1e57d 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012 NVIDIA Corporation
+ * Copyright (c) 2010-2013 NVIDIA Corporation
* With help from the mpc8xxx SPI driver
* With more help from omap3_spi SPI driver
*
@@ -80,14 +80,22 @@ struct spi_regs {
u32 rx_fifo;/* SPI_RX_FIFO_0 register */
};
-struct tegra_spi_slave {
- struct spi_slave slave;
+struct tegra_spi_ctrl {
struct spi_regs *regs;
unsigned int freq;
unsigned int mode;
int periph_id;
+ int valid;
+};
+
+struct tegra_spi_slave {
+ struct spi_slave slave;
+ struct tegra_spi_ctrl *ctrl;
};
+/* tegra20 only supports one SFLASH controller */
+static struct tegra_spi_ctrl spi_ctrls[1];
+
static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
{
return container_of(slave, struct tegra_spi_slave, slave);
@@ -106,7 +114,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct tegra_spi_slave *spi;
- int node;
if (!spi_cs_is_valid(bus, cs)) {
printf(SPI error: unsupported bus %d / chip select %d\n,
@@ -127,41 +134,19 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
}
spi-slave.bus = bus;
spi-slave.cs = cs;
-
- node = fdtdec_next_compatible(gd-fdt_blob, 0,
- COMPAT_NVIDIA_TEGRA20_SFLASH);
- if (node 0) {
- debug(%s: cannot locate sflash node\n, __func__);
- return NULL;
- }
- if (!fdtdec_get_is_enabled(gd-fdt_blob, node)) {
- debug(%s: sflash is disabled\n, __func__);
- return NULL;
- }
- spi-regs = (struct spi_regs *)fdtdec_get_addr(gd-fdt_blob,
- node, reg);
- if ((fdt_addr_t)spi-regs == FDT_ADDR_T_NONE) {
- debug(%s: no sflash register found\n, __func__);
+ spi-ctrl = spi_ctrls[bus];
+ if (!spi-ctrl) {
+ printf(SPI error: could not find controller for bus %d\n,
+ bus);
return NULL;
}
- spi-freq = fdtdec_get_int(gd-fdt_blob, node, spi-max-frequency, 0);
- if (!spi-freq) {
- debug(%s: no sflash max frequency found\n, __func__);
- return NULL;
- }
- spi-periph_id = clock_decode_periph_id(gd-fdt_blob, node);
- if (spi-periph_id == PERIPH_ID_NONE) {
- debug(%s: could not decode periph id\n, __func__);
- return NULL;
- }
- if (max_hz spi-freq) {
+
+ if (max_hz spi-ctrl-freq) {
debug(%s: limiting frequency from %u to %u\n, __func__,
- spi-freq, max_hz);
- spi-freq = max_hz;
+ spi-ctrl-freq, max_hz);
+ spi-ctrl-freq = max_hz;
}
- debug(%s: controller initialized at %p, freq = %u, periph_id = %d\n,
- __func__, spi-regs, spi-freq, spi-periph_id);
- spi-mode = mode;
+ spi-ctrl-mode = mode;
return spi-slave;
}
@@ -175,17 +160,54 @@ void spi_free_slave(struct spi_slave *slave)
void spi_init(void)
{
- /* do nothing */
+ struct tegra_spi_ctrl *ctrl;
+ int i;
+ int node = 0;
+ int count;
+ int node_list[1];
+
+ count = fdtdec_find_aliases_for_id(gd-fdt_blob, spi,
+ COMPAT_NVIDIA_TEGRA20_SFLASH,
+ node_list,
+ 1);
+ for (i = 0; i count; i++) {
+ ctrl = spi_ctrls[i];
+ node = node_list[i];
+
+ ctrl-regs = (struct spi_regs *)fdtdec_get_addr(gd-fdt_blob,
+ node, reg);
+ if ((fdt_addr_t)ctrl-regs == FDT_ADDR_T_NONE) {
+ debug(%s: no slink register found\n, __func__);
+ continue;
+ }
+ ctrl-freq = fdtdec_get_int(gd-fdt_blob, node,
+ spi-max-frequency, 0);
+ if (!ctrl-freq) {
+ debug(%s: no slink max frequency found\n, __func__);
+ continue;
+ }
+
+ ctrl-periph_id = clock_decode_periph_id(gd-fdt_blob, node);
+ if (ctrl
[U-Boot] [PATCH v2 00/13] tegra114 SPI driver
This series pulls fdt functionality from the existing tegra20 and
tegra30 SPI drivers into a new common fdt SPI driver front end,
then adds a new tegra114 SPI driver as an additional client of
the fdt SPI driver.
Changes in v2:
- Added a patch to remove SPI/UART switch support, this was only
useful for seaboard, which was never manufactured
- Renamed tegra_sflash and tegra_slink to tegra20_sflash and
tegra20_slink
- Moved SPI register definitions from header files into SPI driver
files, since those are the only users of those registers.
- Removed patch to add CAR node to dt, equivalent patch was already
upstreamed.
Allen Martin (13):
tegra: remove support for UART SPI switch
tegra: spi: rename tegra SPI drivers
tegra: spi: remove non fdt support
tegra: spi: pull register structs out of headers
tegra20: spi: move fdt probe to spi_init
spi: add common fdt SPI driver interface
sf: winbond: add W25Q32DW
tegra114: fdt: add compatible string for tegra114 SPI ctrl
tegra114: fdt: add apbdma block
tegra114: fdt: add SPI blocks
tegra114: dalmore: fdt: enable dalmore SPI controller
tegra114: add SPI driver
tegra114: dalmore: config: enable SPI
arch/arm/dts/tegra114.dtsi | 109 ++
arch/arm/include/asm/arch-tegra/board.h|3 +-
arch/arm/include/asm/arch-tegra/tegra_slink.h | 84
arch/arm/include/asm/arch-tegra/tegra_spi.h| 75
arch/arm/include/asm/arch-tegra114/tegra114_spi.h | 41 ++
arch/arm/include/asm/arch-tegra20/tegra20_sflash.h | 41 ++
arch/arm/include/asm/arch-tegra20/tegra20_slink.h | 41 ++
.../arm/include/asm/arch-tegra20/uart-spi-switch.h | 46 ---
board/nvidia/common/board.c|5 +-
board/nvidia/common/common.mk |1 -
board/nvidia/common/uart-spi-switch.c | 125 --
board/nvidia/dts/tegra114-dalmore.dts |5 +
board/nvidia/seaboard/seaboard.c |2 +-
drivers/mtd/spi/winbond.c |5 +
drivers/spi/Makefile |6 +-
drivers/spi/fdt_spi.c | 186 +
drivers/spi/tegra114_spi.c | 405
drivers/spi/{tegra_spi.c = tegra20_sflash.c} | 215 ++-
drivers/spi/{tegra_slink.c = tegra20_slink.c} | 128 ---
include/configs/cardhu.h |2 +-
include/configs/dalmore.h | 11 +
include/configs/tegra-common-post.h|4 +
include/configs/trimslice.h|2 +-
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
25 files changed, 1054 insertions(+), 490 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h
delete mode 100644 arch/arm/include/asm/arch-tegra/tegra_spi.h
create mode 100644 arch/arm/include/asm/arch-tegra114/tegra114_spi.h
create mode 100644 arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
create mode 100644 arch/arm/include/asm/arch-tegra20/tegra20_slink.h
delete mode 100644 arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
delete mode 100644 board/nvidia/common/uart-spi-switch.c
create mode 100644 drivers/spi/fdt_spi.c
create mode 100644 drivers/spi/tegra114_spi.c
rename drivers/spi/{tegra_spi.c = tegra20_sflash.c} (57%)
rename drivers/spi/{tegra_slink.c = tegra20_slink.c} (72%)
--
1.7.10.4
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[U-Boot] [PATCH v2 01/13] tegra: remove support for UART SPI switch
This feature was only used for tegra20 seaboard that had a pinmux
conflict on the SPI pins. These boards were never manufactured, so
remove this support to clean up SPI driver.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/board.h|3 +-
.../arm/include/asm/arch-tegra20/uart-spi-switch.h | 46 ---
board/nvidia/common/board.c|3 -
board/nvidia/common/common.mk |1 -
board/nvidia/common/uart-spi-switch.c | 125
board/nvidia/seaboard/seaboard.c |2 +-
drivers/spi/tegra_spi.c| 25 +---
7 files changed, 3 insertions(+), 202 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
delete mode 100644 board/nvidia/common/uart-spi-switch.c
diff --git a/arch/arm/include/asm/arch-tegra/board.h
b/arch/arm/include/asm/arch-tegra/board.h
index 3db0d93..1a66990 100644
--- a/arch/arm/include/asm/arch-tegra/board.h
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -25,8 +25,7 @@
#define _TEGRA_BOARD_H_
/* Set up pinmux to make UART usable */
-void gpio_config_uart(void); /* CONFIG_SPI_UART_SWITCH */
-void gpio_early_init_uart(void); /*!CONFIG_SPI_UART_SWITCH */
+void gpio_early_init_uart(void);
/* Set up early UART output */
void board_init_uart_f(void);
diff --git a/arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
b/arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
deleted file mode 100644
index 82ac180..000
--- a/arch/arm/include/asm/arch-tegra20/uart-spi-switch.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _UART_SPI_SWITCH_H
-#define _UART_SPI_SWITCH_H
-
-#if defined(CONFIG_SPI_UART_SWITCH)
-/*
- * Signal that we are about to use the UART. This unfortunate hack is
- * required by Seaboard, which cannot use its console and SPI at the same
- * time! If the board file provides this, the board config will declare it.
- * Let this be a lesson for others.
- */
-void pinmux_select_uart(void);
-
-/*
- * Signal that we are about the use the SPI bus.
- */
-void pinmux_select_spi(void);
-
-#else /* not CONFIG_SPI_UART_SWITCH */
-
-static inline void pinmux_select_uart(void) {}
-static inline void pinmux_select_spi(void) {}
-
-#endif
-
-#endif
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 7d9f361..b6e6566 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -132,9 +132,6 @@ int board_init(void)
clock_init();
clock_verify();
-#ifdef CONFIG_SPI_UART_SWITCH
- gpio_config_uart();
-#endif
#if defined(CONFIG_TEGRA_SPI) || defined(CONFIG_TEGRA_SLINK)
pin_mux_spi();
spi_init();
diff --git a/board/nvidia/common/common.mk b/board/nvidia/common/common.mk
index bd6202c..d9bcb85 100644
--- a/board/nvidia/common/common.mk
+++ b/board/nvidia/common/common.mk
@@ -1,4 +1,3 @@
# common options for all tegra boards
COBJS-y+= ../../nvidia/common/board.o
-COBJS-$(CONFIG_SPI_UART_SWITCH) += ../../nvidia/common/uart-spi-switch.o
COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o
diff --git a/board/nvidia/common/uart-spi-switch.c
b/board/nvidia/common/uart-spi-switch.c
deleted file mode 100644
index e9d445d..000
--- a/board/nvidia/common/uart-spi-switch.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program
[U-Boot] [PATCH v2 11/13] tegra114: dalmore: fdt: enable dalmore SPI controller
Dalmore has a SPI flash part attached to controller 4, so enable
controller 4 and set to 25MHz.
Signed-off-by: Allen Martin amar...@nvidia.com
---
board/nvidia/dts/tegra114-dalmore.dts |5 +
1 file changed, 5 insertions(+)
diff --git a/board/nvidia/dts/tegra114-dalmore.dts
b/board/nvidia/dts/tegra114-dalmore.dts
index 3e1e1ea..a446713 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -35,4 +35,9 @@
status = okay;
clock-frequency = 40;
};
+
+ spi@7000da00 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
};
--
1.7.10.4
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[U-Boot] [PATCH v2 08/13] tegra114: fdt: add compatible string for tegra114 SPI ctrl
Add nvidia,tegra114-spi to represent t114 SPI controller hardware.
Signed-off-by: Allen Martin amar...@nvidia.com
---
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 2189483..19c9707 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -75,6 +75,7 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_SDMMC,/* Tegra20 SDMMC controller */
COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */
COMPAT_NVIDIA_TEGRA20_SLINK,/* Tegra 2 SPI SLINK controller */
+ COMPAT_NVIDIA_TEGRA114_SPI, /* Tegra 114 SPI controller */
COMPAT_SMSC_LAN9215,/* SMSC 10/100 Ethernet LAN9215 */
COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 43f29f5..c56f7d4 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -50,6 +50,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA20_SDMMC, nvidia,tegra20-sdhci),
COMPAT(NVIDIA_TEGRA20_SFLASH, nvidia,tegra20-sflash),
COMPAT(NVIDIA_TEGRA20_SLINK, nvidia,tegra20-slink),
+ COMPAT(NVIDIA_TEGRA114_SPI, nvidia,tegra114-spi),
COMPAT(SMSC_LAN9215, smsc,lan9215),
COMPAT(SAMSUNG_EXYNOS5_SROMC, samsung,exynos-sromc),
COMPAT(SAMSUNG_S3C2440_I2C, samsung,s3c2440-i2c),
--
1.7.10.4
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[U-Boot] [PATCH v2 09/13] tegra114: fdt: add apbdma block
Add node for apbdma controller hardware.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/dts/tegra114.dtsi | 37 +
1 file changed, 37 insertions(+)
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index dfeac53..92e69f6 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -17,6 +17,43 @@
#clock-cells = 1;
};
+ apbdma: dma {
+ compatible = nvidia,tegra114-apbdma, nvidia,tegra30-apbdma,
nvidia,tegra20-apbdma;
+ reg = 0x6000a000 0x1400;
+ interrupts = 0 104 0x04
+ 0 105 0x04
+ 0 106 0x04
+ 0 107 0x04
+ 0 108 0x04
+ 0 109 0x04
+ 0 110 0x04
+ 0 111 0x04
+ 0 112 0x04
+ 0 113 0x04
+ 0 114 0x04
+ 0 115 0x04
+ 0 116 0x04
+ 0 117 0x04
+ 0 118 0x04
+ 0 119 0x04
+ 0 128 0x04
+ 0 129 0x04
+ 0 130 0x04
+ 0 131 0x04
+ 0 132 0x04
+ 0 133 0x04
+ 0 134 0x04
+ 0 135 0x04
+ 0 136 0x04
+ 0 137 0x04
+ 0 138 0x04
+ 0 139 0x04
+ 0 140 0x04
+ 0 141 0x04
+ 0 142 0x04
+ 0 143 0x04;
+ };
+
gpio: gpio {
compatible = nvidia,tegra114-gpio, nvidia,tegra30-gpio;
reg = 0x6000d000 0x1000;
--
1.7.10.4
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[U-Boot] [PATCH v2 13/13] tegra114: dalmore: config: enable SPI
Turn on SPI in dalmore config file Signed-off-by: Allen Martin amar...@nvidia.com --- include/configs/dalmore.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index b1a6e34..c7deea5 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -54,6 +54,17 @@ #define MACH_TYPE_DALMORE 4304/* not yet in mach-types.h */ +/* SPI */ +#define CONFIG_TEGRA114_SPI +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED2400 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 20) + #include tegra-common-post.h #endif /* __CONFIG_H */ -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 12/13] tegra114: add SPI driver
Add driver for tegra114 SPI controller. This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/include/asm/arch-tegra114/tegra114_spi.h | 41 +++
drivers/spi/Makefile |1 +
drivers/spi/fdt_spi.c | 15 +
drivers/spi/tegra114_spi.c| 405 +
include/configs/tegra-common-post.h |2 +-
5 files changed, 463 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-tegra114/tegra114_spi.h
create mode 100644 drivers/spi/tegra114_spi.c
diff --git a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h
b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h
new file mode 100644
index 000..48197bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h
@@ -0,0 +1,41 @@
+/*
+ * NVIDIA Tegra SPI controller
+ *
+ * Copyright 2010-2013 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA114_SPI_H_
+#define _TEGRA114_SPI_H_
+
+#include asm/types.h
+
+int tegra114_spi_init(int *node_list, int count);
+int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs);
+struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode);
+void tegra114_spi_free_slave(struct spi_slave *slave);
+int tegra114_spi_claim_bus(struct spi_slave *slave);
+void tegra114_spi_cs_activate(struct spi_slave *slave);
+void tegra114_spi_cs_deactivate(struct spi_slave *slave);
+int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+const void *data_out, void *data_in, unsigned long flags);
+
+#endif /* _TEGRA114_SPI_H_ */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3527729..57802ae 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -48,6 +48,7 @@ COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
+COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS := $(COBJS-y)
diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c
index c6ae719..58f139a 100644
--- a/drivers/spi/fdt_spi.c
+++ b/drivers/spi/fdt_spi.c
@@ -29,6 +29,7 @@
#include asm/arch-tegra/clk_rst.h
#include asm/arch-tegra20/tegra20_sflash.h
#include asm/arch-tegra20/tegra20_slink.h
+#include asm/arch-tegra114/tegra114_spi.h
#include spi.h
#include fdtdec.h
@@ -79,6 +80,20 @@ static struct fdt_spi_driver fdt_spi_drivers[] = {
.xfer = tegra30_spi_xfer,
},
#endif
+#ifdef CONFIG_TEGRA114_SPI
+ {
+ .compat = COMPAT_NVIDIA_TEGRA114_SPI,
+ .max_ctrls = CONFIG_TEGRA114_SPI_CTRLS,
+ .init = tegra114_spi_init,
+ .claim_bus = tegra114_spi_claim_bus,
+ .cs_is_valid= tegra114_spi_cs_is_valid,
+ .setup_slave= tegra114_spi_setup_slave,
+ .free_slave = tegra114_spi_free_slave,
+ .cs_activate= tegra114_spi_cs_activate,
+ .cs_deactivate = tegra114_spi_cs_deactivate,
+ .xfer = tegra114_spi_xfer,
+ },
+#endif
};
static struct fdt_spi_driver *driver;
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
new file mode 100644
index 000..b11a0a1
--- /dev/null
+++ b/drivers/spi/tegra114_spi.c
@@ -0,0 +1,405 @@
+/*
+ * NVIDIA Tegra SPI controller (T114 and later)
+ *
+ * Copyright (c) 2010-2013 NVIDIA Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY
[U-Boot] [PATCH v2 06/13] spi: add common fdt SPI driver interface
Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: Allen Martin amar...@nvidia.com --- arch/arm/include/asm/arch-tegra20/tegra20_sflash.h | 11 ++ arch/arm/include/asm/arch-tegra20/tegra20_slink.h | 11 ++ board/nvidia/common/board.c|2 +- drivers/spi/Makefile |1 + drivers/spi/fdt_spi.c | 171 drivers/spi/tegra20_sflash.c | 41 ++--- drivers/spi/tegra20_slink.c| 29 ++-- include/configs/tegra-common-post.h|4 + 8 files changed, 224 insertions(+), 46 deletions(-) create mode 100644 drivers/spi/fdt_spi.c diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h index 28775db..e8cc68c 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h +++ b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h @@ -27,4 +27,15 @@ #include asm/types.h +int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs); +struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); +void tegra20_spi_free_slave(struct spi_slave *slave); +int tegra20_spi_init(int *node_list, int count); +int tegra20_spi_claim_bus(struct spi_slave *slave); +void tegra20_spi_cs_activate(struct spi_slave *slave); +void tegra20_spi_cs_deactivate(struct spi_slave *slave); +int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, +const void *data_out, void *data_in, unsigned long flags); + #endif /* _TEGRA20_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h index fe8b534..5aa74dd 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h +++ b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h @@ -27,4 +27,15 @@ #include asm/types.h +int tegra30_spi_init(int *node_list, int count); +int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs); +struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); +void tegra30_spi_free_slave(struct spi_slave *slave); +int tegra30_spi_claim_bus(struct spi_slave *slave); +void tegra30_spi_cs_activate(struct spi_slave *slave); +void tegra30_spi_cs_deactivate(struct spi_slave *slave); +int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, +const void *data_out, void *data_in, unsigned long flags); + #endif /* _TEGRA30_SPI_H_ */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 87a418b..8d7a227 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -132,7 +132,7 @@ int board_init(void) clock_init(); clock_verify(); -#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) +#ifdef CONFIG_FDT_SPI pin_mux_spi(); spi_init(); #endif diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8470c34..3527729 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -45,6 +45,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o +COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c new file mode 100644 index 000..c6ae719 --- /dev/null +++ b/drivers/spi/fdt_spi.c @@ -0,0 +1,171 @@ +/* + * Common fdt based SPI driver front end + * + * Copyright (c) 2013 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include common.h +#include malloc.h +#include asm/io.h +#include asm/gpio.h +#include asm/arch/clock.h +#include asm/arch-tegra/clk_rst.h +#include asm/arch-tegra20/tegra20_sflash.h +#include asm/arch
[U-Boot] [PATCH v2 04/13] tegra: spi: pull register structs out of headers
Move register structs from headers into .c files and use common name.
This is in preparation of making common fdt front end for SPI
drivers.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/include/asm/arch-tegra20/tegra20_sflash.h | 45 -
arch/arm/include/asm/arch-tegra20/tegra20_slink.h | 54
drivers/spi/tegra20_sflash.c | 53 +--
drivers/spi/tegra20_slink.c| 68 ++--
4 files changed, 110 insertions(+), 110 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
index 26a8402..28775db 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
@@ -27,49 +27,4 @@
#include asm/types.h
-struct spi_tegra {
- u32 command;/* SPI_COMMAND_0 register */
- u32 status; /* SPI_STATUS_0 register */
- u32 rx_cmp; /* SPI_RX_CMP_0 register */
- u32 dma_ctl;/* SPI_DMA_CTL_0 register */
- u32 tx_fifo;/* SPI_TX_FIFO_0 register */
- u32 rsvd[3];/* offsets 0x14 to 0x1F reserved */
- u32 rx_fifo;/* SPI_RX_FIFO_0 register */
-};
-
-#define SPI_CMD_GO (1 30)
-#define SPI_CMD_ACTIVE_SCLK_SHIFT 26
-#define SPI_CMD_ACTIVE_SCLK_MASK (3 SPI_CMD_ACTIVE_SCLK_SHIFT)
-#define SPI_CMD_CK_SDA (1 21)
-#define SPI_CMD_ACTIVE_SDA_SHIFT 18
-#define SPI_CMD_ACTIVE_SDA_MASK(3 SPI_CMD_ACTIVE_SDA_SHIFT)
-#define SPI_CMD_CS_POL (1 16)
-#define SPI_CMD_TXEN (1 15)
-#define SPI_CMD_RXEN (1 14)
-#define SPI_CMD_CS_VAL (1 13)
-#define SPI_CMD_CS_SOFT(1 12)
-#define SPI_CMD_CS_DELAY (1 9)
-#define SPI_CMD_CS3_EN (1 8)
-#define SPI_CMD_CS2_EN (1 7)
-#define SPI_CMD_CS1_EN (1 6)
-#define SPI_CMD_CS0_EN (1 5)
-#define SPI_CMD_BIT_LENGTH (1 4)
-#define SPI_CMD_BIT_LENGTH_MASK0x001F
-
-#define SPI_STAT_BSY (1 31)
-#define SPI_STAT_RDY (1 30)
-#define SPI_STAT_RXF_FLUSH (1 29)
-#define SPI_STAT_TXF_FLUSH (1 28)
-#define SPI_STAT_RXF_UNR (1 27)
-#define SPI_STAT_TXF_OVF (1 26)
-#define SPI_STAT_RXF_EMPTY (1 25)
-#define SPI_STAT_RXF_FULL (1 24)
-#define SPI_STAT_TXF_EMPTY (1 23)
-#define SPI_STAT_TXF_FULL (1 22)
-#define SPI_STAT_SEL_TXRX_N(1 16)
-#define SPI_STAT_CUR_BLKCNT(1 15)
-
-#define SPI_TIMEOUT1000
-#define TEGRA_SPI_MAX_FREQ 5200
-
#endif /* _TEGRA20_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
index afa9b36..fe8b534 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
@@ -27,58 +27,4 @@
#include asm/types.h
-struct slink_tegra {
- u32 command;/* SLINK_COMMAND_0 register */
- u32 command2; /* SLINK_COMMAND2_0 reg */
- u32 status; /* SLINK_STATUS_0 register */
- u32 reserved; /* Reserved offset 0C */
- u32 mas_data; /* SLINK_MAS_DATA_0 reg */
- u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
- u32 dma_ctl;/* SLINK_DMA_CTL_0 register */
- u32 status2;/* SLINK_STATUS2_0 reg */
- u32 rsvd[56]; /* 0x20 to 0xFF reserved */
- u32 tx_fifo;/* SLINK_TX_FIFO_0 reg off 100h */
- u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
- u32 rx_fifo;/* SLINK_RX_FIFO_0 reg off 180h */
-};
-
-/* COMMAND */
-#define SLINK_CMD_ENB (1 31)
-#define SLINK_CMD_GO (1 30)
-#define SLINK_CMD_M_S (1 28)
-#define SLINK_CMD_CK_SDA (1 21)
-#define SLINK_CMD_CS_POL (1 13)
-#define SLINK_CMD_CS_VAL (1 12)
-#define SLINK_CMD_CS_SOFT (1 11)
-#define SLINK_CMD_BIT_LENGTH (1 4)
-#define SLINK_CMD_BIT_LENGTH_MASK 0x001F
-/* COMMAND2 */
-#define SLINK_CMD2_TXEN(1 30)
-#define SLINK_CMD2_RXEN(1 31)
-#define SLINK_CMD2_SS_EN (1 18)
-#define SLINK_CMD2_SS_EN_SHIFT 18
-#define SLINK_CMD2_SS_EN_MASK 0x000C
-#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 17)
-/* STATUS */
-#define SLINK_STAT_BSY (1 31)
-#define SLINK_STAT_RDY (1 30)
-#define SLINK_STAT_ERR (1 29)
-#define SLINK_STAT_RXF_FLUSH (1 27)
-#define SLINK_STAT_TXF_FLUSH (1 26)
-#define SLINK_STAT_RXF_OVF (1 25)
-#define SLINK_STAT_TXF_UNR (1 24)
-#define SLINK_STAT_RXF_EMPTY
[U-Boot] [PATCH v2 07/13] sf: winbond: add W25Q32DW
Add support for Winbond W25Q32DW 32Mbit part
Signed-off-by: Allen Martin amar...@nvidia.com
---
drivers/mtd/spi/winbond.c |5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index 4418302..3560fcb 100644
--- a/drivers/mtd/spi/winbond.c
+++ b/drivers/mtd/spi/winbond.c
@@ -68,6 +68,11 @@ static const struct winbond_spi_flash_params
winbond_spi_flash_table[] = {
.name = W25Q80,
},
{
+ .id = 0x6016,
+ .nr_blocks = 512,
+ .name = W25Q32DW,
+ },
+ {
.id = 0x6017,
.nr_blocks = 128,
.name = W25Q64DW,
--
1.7.10.4
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Re: [U-Boot] [PATCH 03/14] tegra: spi: pull register structs out of headers
On Wed, Feb 13, 2013 at 02:32:44PM -0800, Stephen Warren wrote: On 02/12/2013 08:23 PM, Allen Martin wrote: Move register structs from headers into .c files and use common name. This is in preparation of making common fdt front end for SPI drivers. Why not move all the register defines too? Sure, makes sense. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/14] tegra: spi: rename tegra SPI drivers
On Wed, Feb 13, 2013 at 02:30:26PM -0800, Stephen Warren wrote: On 02/12/2013 08:23 PM, Allen Martin wrote: Rename tegra SPI drivers to tegra20_spi and tegra30_spi in preparation for commonization and addition of tegra114_spi. This isn't logically quite right. Both types (sflash, slink) of SPI controller actually exist on Tegra20, so it isn't right to name them after the different chips. It is true that only one is kept for Tegra30 (slink). As such, it might make sense to simply drop this patch. Mostly my intention here was to try to make the SPI driver naming less confusing and to make room for the new tegra114 SPI driver. What do you think of the following: tegra_sflash: tegra20 sflash driver tegra_slink: tegra20 and tegra30 slink driver tegra_spi: tegra114 and later spi driver arch/arm/include/asm/arch-tegra/tegra_slink.h | 84 -- arch/arm/include/asm/arch-tegra/tegra_spi.h | 75 - arch/arm/include/asm/arch-tegra20/tegra20_spi.h | 75 + arch/arm/include/asm/arch-tegra30/tegra30_spi.h | 84 ++ board/nvidia/common/board.c |2 +- board/nvidia/common/uart-spi-switch.c |2 +- drivers/spi/Makefile|4 +- drivers/spi/tegra20_spi.c | 330 ++ drivers/spi/tegra30_spi.c | 343 +++ drivers/spi/tegra_slink.c | 343 --- drivers/spi/tegra_spi.c | 330 -- include/configs/cardhu.h|2 +- include/configs/trimslice.h |2 +- 13 files changed, 838 insertions(+), 838 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h delete mode 100644 arch/arm/include/asm/arch-tegra/tegra_spi.h create mode 100644 arch/arm/include/asm/arch-tegra20/tegra20_spi.h create mode 100644 arch/arm/include/asm/arch-tegra30/tegra30_spi.h create mode 100644 drivers/spi/tegra20_spi.c create mode 100644 drivers/spi/tegra30_spi.c delete mode 100644 drivers/spi/tegra_slink.c delete mode 100644 drivers/spi/tegra_spi.c git format-patch -M might have made this easier to spot the changes during the renames, assuming there weren't too many edits to make it worthwhile. Yes, sorry, I'll fix for next round. I didn't actually review the diffs, since I assume it was just a simple rename. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/14] tegra: spi: rename tegra SPI drivers
On Wed, Feb 13, 2013 at 02:36:10PM -0800, Stephen Warren wrote: On 02/12/2013 08:23 PM, Allen Martin wrote: Rename tegra SPI drivers to tegra20_spi and tegra30_spi in preparation for commonization and addition of tegra114_spi. board/nvidia/common/uart-spi-switch.c |2 +- I tend to think we should just rip out the UART/SPI switch cruft; it's just not that useful. Ok -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 05/14] spi: add common fdt SPI driver interface
On Wed, Feb 13, 2013 at 02:40:29PM -0800, Stephen Warren wrote:
On 02/12/2013 08:23 PM, Allen Martin wrote:
Add a common interface to fdt based SPI drivers. Each driver is
represented by a table entry in fdt_spi_drivers[]. If there are
multiple SPI drivers in the table, the first driver to return success
from spi_init() will be registered as the SPI driver.
I don't think there should be a global concept of the SPI driver;
instances of both SPI blocks exist on Tegra20, so they should be able to
co-exist, using the SFLASH driver for 1 SPI port, and the SLINK driver
for the other 4 ports.
I agree, but that's probably beyond the scope of this series, as
that's a more global problem. Other drivers call directly into the
SPI driver by use of well known function names, so that would need to
be abstracted to fix.
How does this patch interact with any SPI-related device manager work?
I'm not sure what device manager is in the context of u-boot. Is that
the same as the unified driver model that's being documented in
doc/driver-model? If so I think this fits in really well with that.
The struct ops described there is almost identical to the callbacks
I added in struct fdt_spi_driver
+void spi_init(void)
+{
+ int i;
+ int num_drivers = sizeof(fdt_spi_drivers) /
+ sizeof(struct fdt_spi_driver);
U-Boot doesn't have an ARSIZE/ARRAY_SIZE macro?
Will fix.
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
/* SPI */
#define CONFIG_TEGRA30_SPI
-#define CONFIG_TEGRA_SLINK_CTRLS 6
+#define CONFIG_TEGRA30_SPI_CTRLS 6
Should that be in one of the other patches?
Yes, probably the renaming patch if we decide to keep it.
--
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Re: [U-Boot] [PATCH 05/14] spi: add common fdt SPI driver interface
On Thu, Feb 14, 2013 at 12:21:34PM -0800, Stephen Warren wrote: On 02/14/2013 01:07 PM, Allen Martin wrote: On Wed, Feb 13, 2013 at 02:40:29PM -0800, Stephen Warren wrote: On 02/12/2013 08:23 PM, Allen Martin wrote: Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. I don't think there should be a global concept of the SPI driver; instances of both SPI blocks exist on Tegra20, so they should be able to co-exist, using the SFLASH driver for 1 SPI port, and the SLINK driver for the other 4 ports. I agree, but that's probably beyond the scope of this series, as that's a more global problem. Other drivers call directly into the SPI driver by use of well known function names, so that would need to be abstracted to fix. It should be simple to fix; you already have a table of all known (DT-based) SPI drivers; simply iterate over all entries in the table always, rather than stopping when you hit the first one. Also, don't store /a/ pointer to the driver, but store a pointer per instance. I think the modifications to your patch series to solve this shouldn't be large at all. I don't think it will be that easy. The different drivers would have to coordinate on bus numbering, or there would have to be a new adapter number addressing to differentiate the drivers, which would be hard to do without impacting all the other non-fdt drivers as well. How does this patch interact with any SPI-related device manager work? I'm not sure what device manager is in the context of u-boot. Is that the same as the unified driver model that's being documented in doc/driver-model? Yes. If so I think this fits in really well with that. The struct ops described there is almost identical to the callbacks I added in struct fdt_spi_driver The code certainly looks like a move in the right direction. I was thinking more along the lines of: Is anyone actively working on this right now, so your patches will conflict. I haven't seen any, but I haven't been looking out for those patches either, I'll look through the list archives and see if anyting turns up. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] tegra114: add SPI driver
On Thu, Feb 14, 2013 at 06:32:06AM -0800, Simon Glass wrote: Hi Allen, On Wed, Feb 13, 2013 at 2:59 PM, Stephen Warren swar...@wwwdotorg.org wrote: On 02/12/2013 08:23 PM, Allen Martin wrote: Subject: tegra114: add SPI driver This really touches the SPI sub-system more than Tegra, and the Tegra subsystem is just (and all of) Tegra not Tegra114-specific, so I'd re-title this: spi: tegra: add Tegra114 SPI driver similar s/tegra114:/tegra:/ in other patch subjects, many of which probably should be ARM: tegra: This driver seems to add a lot of duplication. What prevents using common code? Is it the register layout, differences in algorithm or something else? Yes, unfortunately there really are three different SPI controller hardware blocks. There's sflash which is a tegra20 only block, slink which is present in tegra20 and tegra30, and tegra114 has a new SPI controller which is functionally equivalent to slink, but the register interface is different. The programming model is quite similar, but not exactly the same between each. For example, the same function may be one register write on one chip and two or more register writes on another. It could be possible to hide some of those differences in macros or inline functions, but I'm not sure if that's more or less messy. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/14] tegra114: fdt: add compatible string for tegra114 SPI ctrl
Add nvidia,tegra114-spi to represent t114 SPI controller hardware.
Signed-off-by: Allen Martin amar...@nvidia.com
---
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 77f244f..1b20f72 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -72,6 +72,7 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */
COMPAT_NVIDIA_TEGRA20_SLINK,/* Tegra 2 SPI SLINK controller */
+ COMPAT_NVIDIA_TEGRA114_SPI, /* Tegra 114 SPI controller */
COMPAT_SMSC_LAN9215,/* SMSC 10/100 Ethernet LAN9215 */
COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 3ae348d..c68d05b 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -47,6 +47,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA20_DC, nvidia,tegra20-dc),
COMPAT(NVIDIA_TEGRA20_SFLASH, nvidia,tegra20-sflash),
COMPAT(NVIDIA_TEGRA20_SLINK, nvidia,tegra20-slink),
+ COMPAT(NVIDIA_TEGRA114_SPI, nvidia,tegra114-spi),
COMPAT(SMSC_LAN9215, smsc,lan9215),
COMPAT(SAMSUNG_EXYNOS5_SROMC, samsung,exynos-sromc),
COMPAT(SAMSUNG_S3C2440_I2C, samsung,s3c2440-i2c),
--
1.7.10.4
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[U-Boot] [PATCH 02/14] tegra: spi: remove non fdt support
Remove non fdt support from tegra20 and tegra30 SPI drivers in
preparation of new common fdt based SPI driver front end.
Signed-off-by: Allen Martin amar...@nvidia.com
---
drivers/spi/tegra20_spi.c | 12
drivers/spi/tegra30_spi.c | 29 -
2 files changed, 4 insertions(+), 37 deletions(-)
diff --git a/drivers/spi/tegra20_spi.c b/drivers/spi/tegra20_spi.c
index 8cc3e5d..9e5de68 100644
--- a/drivers/spi/tegra20_spi.c
+++ b/drivers/spi/tegra20_spi.c
@@ -68,6 +68,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
unsigned int max_hz, unsigned int mode)
{
struct tegra_spi_slave *spi;
+ int node;
if (!spi_cs_is_valid(bus, cs)) {
printf(SPI error: unsupported bus %d / chip select %d\n,
@@ -88,9 +89,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
}
spi-slave.bus = bus;
spi-slave.cs = cs;
-#ifdef CONFIG_OF_CONTROL
- int node = fdtdec_next_compatible(gd-fdt_blob, 0,
- COMPAT_NVIDIA_TEGRA20_SFLASH);
+
+ node = fdtdec_next_compatible(gd-fdt_blob, 0,
+ COMPAT_NVIDIA_TEGRA20_SFLASH);
if (node 0) {
debug(%s: cannot locate sflash node\n, __func__);
return NULL;
@@ -115,11 +116,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
debug(%s: could not decode periph id\n, __func__);
return NULL;
}
-#else
- spi-regs = (struct spi_tegra *)NV_PA_SPI_BASE;
- spi-freq = TEGRA_SPI_MAX_FREQ;
- spi-periph_id = PERIPH_ID_SPI1;
-#endif
if (max_hz spi-freq) {
debug(%s: limiting frequency from %u to %u\n, __func__,
spi-freq, max_hz);
diff --git a/drivers/spi/tegra30_spi.c b/drivers/spi/tegra30_spi.c
index b475090..2d788e6 100644
--- a/drivers/spi/tegra30_spi.c
+++ b/drivers/spi/tegra30_spi.c
@@ -116,7 +116,6 @@ void spi_init(void)
{
struct tegra_spi_ctrl *ctrl;
int i;
-#ifdef CONFIG_OF_CONTROL
int node = 0;
int count;
int node_list[CONFIG_TEGRA_SLINK_CTRLS];
@@ -152,34 +151,6 @@ void spi_init(void)
debug(%s: found controller at %p, freq = %u, periph_id = %d\n,
__func__, ctrl-regs, ctrl-freq, ctrl-periph_id);
}
-#else
- for (i = 0; i CONFIG_TEGRA_SLINK_CTRLS; i++) {
- ctrl = spi_ctrls[i];
- u32 base_regs[] = {
- NV_PA_SLINK1_BASE,
- NV_PA_SLINK2_BASE,
- NV_PA_SLINK3_BASE,
- NV_PA_SLINK4_BASE,
- NV_PA_SLINK5_BASE,
- NV_PA_SLINK6_BASE,
- };
- int periph_ids[] = {
- PERIPH_ID_SBC1,
- PERIPH_ID_SBC2,
- PERIPH_ID_SBC3,
- PERIPH_ID_SBC4,
- PERIPH_ID_SBC5,
- PERIPH_ID_SBC6,
- };
- ctrl-regs = (struct slink_tegra *)base_regs[i];
- ctrl-freq = TEGRA_SPI_MAX_FREQ;
- ctrl-periph_id = periph_ids[i];
- ctrl-valid = 1;
-
- debug(%s: found controller at %p, freq = %u, periph_id = %d\n,
- __func__, ctrl-regs, ctrl-freq, ctrl-periph_id);
- }
-#endif
}
int spi_claim_bus(struct spi_slave *slave)
--
1.7.10.4
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[U-Boot] [PATCH 14/14] tegra114: dalmore: config: enable SPI
Turn on SPI in dalmore config file Signed-off-by: Allen Martin amar...@nvidia.com --- include/configs/dalmore.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index ce32c80..e7df60b 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -45,6 +45,17 @@ #define MACH_TYPE_DALMORE 4304/* not yet in mach-types.h */ +/* SPI */ +#define CONFIG_TEGRA114_SPI +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED2400 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 20) + #include tegra-common-post.h #endif /* __CONFIG_H */ -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 00/14] tegra114 SPI driver
This series pulls fdt functionality from the existing tegra20 and tegra30 SPI drivers into a new common fdt SPI driver front end, then adds a new tegra114 SPI driver as an additional client of the fdt SPI driver. Allen Martin (14): tegra: spi: rename tegra SPI drivers tegra: spi: remove non fdt support tegra: spi: pull register structs out of headers tegra20: spi: move fdt probe to spi_init spi: add common fdt SPI driver interface sf: winbond: add W25Q32DW tegra114: dalmore: add SPI pinmux config tegra114: fdt: add compatible string for tegra114 SPI ctrl tegra114: fdt: add CAR block tegra114: fdt: add apbdma block tegra114: fdt: add SPI blocks tegra114: dalmore: fdt: enable dalmore SPI controller tegra114: add SPI driver tegra114: dalmore: config: enable SPI arch/arm/dts/tegra114.dtsi| 115 +++ arch/arm/include/asm/arch-tegra/tegra_slink.h | 84 - arch/arm/include/asm/arch-tegra/tegra_spi.h | 75 - arch/arm/include/asm/arch-tegra114/tegra114_spi.h | 91 ++ arch/arm/include/asm/arch-tegra20/tegra20_spi.h | 73 + arch/arm/include/asm/arch-tegra30/tegra30_spi.h | 77 + board/nvidia/common/board.c |2 +- board/nvidia/common/uart-spi-switch.c |2 +- board/nvidia/dalmore/pinmux-config-dalmore.h |9 +- board/nvidia/dts/tegra114-dalmore.dts |5 + drivers/mtd/spi/winbond.c |5 + drivers/spi/Makefile |6 +- drivers/spi/fdt_spi.c | 187 +++ drivers/spi/tegra114_spi.c| 355 + drivers/spi/tegra20_spi.c | 350 drivers/spi/tegra30_spi.c | 325 +++ drivers/spi/tegra_slink.c | 343 drivers/spi/tegra_spi.c | 330 --- include/configs/cardhu.h |4 +- include/configs/dalmore.h | 11 + include/configs/tegra-common-post.h |4 + include/configs/trimslice.h |2 +- include/fdtdec.h |1 + lib/fdtdec.c |1 + 24 files changed, 1615 insertions(+), 842 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h delete mode 100644 arch/arm/include/asm/arch-tegra/tegra_spi.h create mode 100644 arch/arm/include/asm/arch-tegra114/tegra114_spi.h create mode 100644 arch/arm/include/asm/arch-tegra20/tegra20_spi.h create mode 100644 arch/arm/include/asm/arch-tegra30/tegra30_spi.h create mode 100644 drivers/spi/fdt_spi.c create mode 100644 drivers/spi/tegra114_spi.c create mode 100644 drivers/spi/tegra20_spi.c create mode 100644 drivers/spi/tegra30_spi.c delete mode 100644 drivers/spi/tegra_slink.c delete mode 100644 drivers/spi/tegra_spi.c -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/14] tegra114: dalmore: add SPI pinmux config
Configure pinmux for SPI4 controller.
Signed-off-by: Allen Martin amar...@nvidia.com
---
board/nvidia/dalmore/pinmux-config-dalmore.h |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h
b/board/nvidia/dalmore/pinmux-config-dalmore.h
index 3dd47da..b337119 100644
--- a/board/nvidia/dalmore/pinmux-config-dalmore.h
+++ b/board/nvidia/dalmore/pinmux-config-dalmore.h
@@ -225,6 +225,12 @@ static struct pingroup_config tegra114_pinmux_common[] = {
DEFAULT_PINMUX(SPI2_SCK,GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+
+ /* SPI */
+ DEFAULT_PINMUX(GMI_AD5, SPI4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6, SPI4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS6_N, SPI4, NORMAL, NORMAL, OUTPUT),
};
static struct pingroup_config unused_pins_lowpower[] = {
@@ -237,9 +243,6 @@ static struct pingroup_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, INPUT),
- DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, TRISTATE, OUTPUT),
DEFAULT_PINMUX(GMI_AD11,NAND, NORMAL, TRISTATE, OUTPUT),
DEFAULT_PINMUX(GMI_AD13,NAND, UP, NORMAL, INPUT),
--
1.7.10.4
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[U-Boot] [PATCH 12/14] tegra114: dalmore: fdt: enable dalmore SPI controller
Dalmore has a SPI flash part attached to controller 4, so enable
controller 4 and set to 25MHz.
Signed-off-by: Allen Martin amar...@nvidia.com
---
board/nvidia/dts/tegra114-dalmore.dts |5 +
1 file changed, 5 insertions(+)
diff --git a/board/nvidia/dts/tegra114-dalmore.dts
b/board/nvidia/dts/tegra114-dalmore.dts
index 7315577..af50aed 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -10,4 +10,9 @@
device_type = memory;
reg = 0x8000 0x8000;
};
+
+ spi@7000da00 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
};
--
1.7.10.4
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[U-Boot] [PATCH 11/14] tegra114: fdt: add SPI blocks
Add nodes for t114 SPI controller hardware
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/dts/tegra114.dtsi | 72
1 file changed, 72 insertions(+)
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index f8b4605..a7bd3ca 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -45,4 +45,76 @@
0 142 0x04
0 143 0x04;
};
+
+ spi@7000d400 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000d400 0x200;
+ interrupts = 0 59 0x04;
+ nvidia,dma-request-selector = apbdma 15;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC1, PLLP_OUT0 */
+ clocks = tegra_car 41;
+ };
+
+ spi@7000d600 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000d600 0x200;
+ interrupts = 0 82 0x04;
+ nvidia,dma-request-selector = apbdma 16;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC2, PLLP_OUT0 */
+ clocks = tegra_car 44;
+ };
+
+ spi@7000d800 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000d480 0x200;
+ interrupts = 0 83 0x04;
+ nvidia,dma-request-selector = apbdma 17;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC3, PLLP_OUT0 */
+ clocks = tegra_car 46;
+ };
+
+ spi@7000da00 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000da00 0x200;
+ interrupts = 0 93 0x04;
+ nvidia,dma-request-selector = apbdma 18;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC4, PLLP_OUT0 */
+ clocks = tegra_car 68;
+ };
+
+ spi@7000dc00 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000dc00 0x200;
+ interrupts = 0 94 0x04;
+ nvidia,dma-request-selector = apbdma 27;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC5, PLLP_OUT0 */
+ clocks = tegra_car 104;
+ };
+
+ spi@7000de00 {
+ compatible = nvidia,tegra114-spi;
+ reg = 0x7000de00 0x200;
+ interrupts = 0 79 0x04;
+ nvidia,dma-request-selector = apbdma 28;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC6, PLLP_OUT0 */
+ clocks = tegra_car 105;
+ };
};
--
1.7.10.4
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[U-Boot] [PATCH 04/14] tegra20: spi: move fdt probe to spi_init
Make the tegra20 SPI driver similar to the tegra30 (and soon to be
tegra114) SPI drivers in preparation of common fdt SPI driver front
end.
Signed-off-by: Allen Martin amar...@nvidia.com
---
drivers/spi/tegra20_spi.c | 110 +++--
1 file changed, 67 insertions(+), 43 deletions(-)
diff --git a/drivers/spi/tegra20_spi.c b/drivers/spi/tegra20_spi.c
index d6567f8..f3985f2 100644
--- a/drivers/spi/tegra20_spi.c
+++ b/drivers/spi/tegra20_spi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012 NVIDIA Corporation
+ * Copyright (c) 2010-2013 NVIDIA Corporation
* With help from the mpc8xxx SPI driver
* With more help from omap3_spi SPI driver
*
@@ -55,14 +55,22 @@ struct spi_regs {
u32 rx_fifo;/* SPI_RX_FIFO_0 register */
};
-struct tegra_spi_slave {
- struct spi_slave slave;
+struct tegra_spi_ctrl {
struct spi_regs *regs;
unsigned int freq;
unsigned int mode;
int periph_id;
+ int valid;
+};
+
+struct tegra_spi_slave {
+ struct spi_slave slave;
+ struct tegra_spi_ctrl *ctrl;
};
+/* tegra20 only supports one SFLASH controller */
+static struct tegra_spi_ctrl spi_ctrls[1];
+
static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
{
return container_of(slave, struct tegra_spi_slave, slave);
@@ -81,7 +89,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
unsigned int max_hz, unsigned int mode)
{
struct tegra_spi_slave *spi;
- int node;
if (!spi_cs_is_valid(bus, cs)) {
printf(SPI error: unsupported bus %d / chip select %d\n,
@@ -102,41 +109,19 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
}
spi-slave.bus = bus;
spi-slave.cs = cs;
-
- node = fdtdec_next_compatible(gd-fdt_blob, 0,
- COMPAT_NVIDIA_TEGRA20_SFLASH);
- if (node 0) {
- debug(%s: cannot locate sflash node\n, __func__);
- return NULL;
- }
- if (!fdtdec_get_is_enabled(gd-fdt_blob, node)) {
- debug(%s: sflash is disabled\n, __func__);
- return NULL;
- }
- spi-regs = (struct spi_regs *)fdtdec_get_addr(gd-fdt_blob,
- node, reg);
- if ((fdt_addr_t)spi-regs == FDT_ADDR_T_NONE) {
- debug(%s: no sflash register found\n, __func__);
+ spi-ctrl = spi_ctrls[bus];
+ if (!spi-ctrl) {
+ printf(SPI error: could not find controller for bus %d\n,
+ bus);
return NULL;
}
- spi-freq = fdtdec_get_int(gd-fdt_blob, node, spi-max-frequency, 0);
- if (!spi-freq) {
- debug(%s: no sflash max frequency found\n, __func__);
- return NULL;
- }
- spi-periph_id = clock_decode_periph_id(gd-fdt_blob, node);
- if (spi-periph_id == PERIPH_ID_NONE) {
- debug(%s: could not decode periph id\n, __func__);
- return NULL;
- }
- if (max_hz spi-freq) {
+
+ if (max_hz spi-ctrl-freq) {
debug(%s: limiting frequency from %u to %u\n, __func__,
- spi-freq, max_hz);
- spi-freq = max_hz;
+ spi-ctrl-freq, max_hz);
+ spi-ctrl-freq = max_hz;
}
- debug(%s: controller initialized at %p, freq = %u, periph_id = %d\n,
- __func__, spi-regs, spi-freq, spi-periph_id);
- spi-mode = mode;
+ spi-ctrl-mode = mode;
return spi-slave;
}
@@ -150,17 +135,54 @@ void spi_free_slave(struct spi_slave *slave)
void spi_init(void)
{
- /* do nothing */
+ struct tegra_spi_ctrl *ctrl;
+ int i;
+ int node = 0;
+ int count;
+ int node_list[1];
+
+ count = fdtdec_find_aliases_for_id(gd-fdt_blob, spi,
+ COMPAT_NVIDIA_TEGRA20_SFLASH,
+ node_list,
+ 1);
+ for (i = 0; i count; i++) {
+ ctrl = spi_ctrls[i];
+ node = node_list[i];
+
+ ctrl-regs = (struct spi_regs *)fdtdec_get_addr(gd-fdt_blob,
+ node, reg);
+ if ((fdt_addr_t)ctrl-regs == FDT_ADDR_T_NONE) {
+ debug(%s: no slink register found\n, __func__);
+ continue;
+ }
+ ctrl-freq = fdtdec_get_int(gd-fdt_blob, node,
+ spi-max-frequency, 0);
+ if (!ctrl-freq) {
+ debug(%s: no slink max frequency found\n, __func__);
+ continue;
+ }
+
+ ctrl-periph_id = clock_decode_periph_id(gd-fdt_blob, node);
+ if (ctrl-periph_id
[U-Boot] [PATCH 09/14] tegra114: fdt: add CAR block
Add node for clock and reset controller hardware.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/dts/tegra114.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index d06cd12..bd969aa 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -2,4 +2,10 @@
/ {
compatible = nvidia,tegra114;
+
+ tegra_car: clock@60006000 {
+ compatible = nvidia,tegra114-car, nvidia,tegra30-car,
nvidia,tegra20-car;
+ reg = 0x60006000 0x1000;
+ #clock-cells = 1;
+ };
};
--
1.7.10.4
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[U-Boot] [PATCH 10/14] tegra114: fdt: add apbdma block
Add node for apbdma controller hardware.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/dts/tegra114.dtsi | 37 +
1 file changed, 37 insertions(+)
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index bd969aa..f8b4605 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -8,4 +8,41 @@
reg = 0x60006000 0x1000;
#clock-cells = 1;
};
+
+ apbdma: dma {
+ compatible = nvidia,tegra114-apbdma, nvidia,tegra30-apbdma,
nvidia,tegra20-apbdma;
+ reg = 0x6000a000 0x1400;
+ interrupts = 0 104 0x04
+ 0 105 0x04
+ 0 106 0x04
+ 0 107 0x04
+ 0 108 0x04
+ 0 109 0x04
+ 0 110 0x04
+ 0 111 0x04
+ 0 112 0x04
+ 0 113 0x04
+ 0 114 0x04
+ 0 115 0x04
+ 0 116 0x04
+ 0 117 0x04
+ 0 118 0x04
+ 0 119 0x04
+ 0 128 0x04
+ 0 129 0x04
+ 0 130 0x04
+ 0 131 0x04
+ 0 132 0x04
+ 0 133 0x04
+ 0 134 0x04
+ 0 135 0x04
+ 0 136 0x04
+ 0 137 0x04
+ 0 138 0x04
+ 0 139 0x04
+ 0 140 0x04
+ 0 141 0x04
+ 0 142 0x04
+ 0 143 0x04;
+ };
};
--
1.7.10.4
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[U-Boot] [PATCH 03/14] tegra: spi: pull register structs out of headers
Move register structs from headers into .c files and use common name.
This is in preparation of making common fdt front end for SPI
drivers.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/include/asm/arch-tegra20/tegra20_spi.h | 13 -
arch/arm/include/asm/arch-tegra30/tegra30_spi.h | 18 -
drivers/spi/tegra20_spi.c | 21 ---
drivers/spi/tegra30_spi.c | 32 ++-
4 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_spi.h
b/arch/arm/include/asm/arch-tegra20/tegra20_spi.h
index 26a8402..6789881 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra20_spi.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20_spi.h
@@ -27,16 +27,6 @@
#include asm/types.h
-struct spi_tegra {
- u32 command;/* SPI_COMMAND_0 register */
- u32 status; /* SPI_STATUS_0 register */
- u32 rx_cmp; /* SPI_RX_CMP_0 register */
- u32 dma_ctl;/* SPI_DMA_CTL_0 register */
- u32 tx_fifo;/* SPI_TX_FIFO_0 register */
- u32 rsvd[3];/* offsets 0x14 to 0x1F reserved */
- u32 rx_fifo;/* SPI_RX_FIFO_0 register */
-};
-
#define SPI_CMD_GO (1 30)
#define SPI_CMD_ACTIVE_SCLK_SHIFT 26
#define SPI_CMD_ACTIVE_SCLK_MASK (3 SPI_CMD_ACTIVE_SCLK_SHIFT)
@@ -69,7 +59,4 @@ struct spi_tegra {
#define SPI_STAT_SEL_TXRX_N(1 16)
#define SPI_STAT_CUR_BLKCNT(1 15)
-#define SPI_TIMEOUT1000
-#define TEGRA_SPI_MAX_FREQ 5200
-
#endif /* _TEGRA20_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/tegra30_spi.h
b/arch/arm/include/asm/arch-tegra30/tegra30_spi.h
index afa9b36..87a8169 100644
--- a/arch/arm/include/asm/arch-tegra30/tegra30_spi.h
+++ b/arch/arm/include/asm/arch-tegra30/tegra30_spi.h
@@ -27,21 +27,6 @@
#include asm/types.h
-struct slink_tegra {
- u32 command;/* SLINK_COMMAND_0 register */
- u32 command2; /* SLINK_COMMAND2_0 reg */
- u32 status; /* SLINK_STATUS_0 register */
- u32 reserved; /* Reserved offset 0C */
- u32 mas_data; /* SLINK_MAS_DATA_0 reg */
- u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
- u32 dma_ctl;/* SLINK_DMA_CTL_0 register */
- u32 status2;/* SLINK_STATUS2_0 reg */
- u32 rsvd[56]; /* 0x20 to 0xFF reserved */
- u32 tx_fifo;/* SLINK_TX_FIFO_0 reg off 100h */
- u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
- u32 rx_fifo;/* SLINK_RX_FIFO_0 reg off 180h */
-};
-
/* COMMAND */
#define SLINK_CMD_ENB (1 31)
#define SLINK_CMD_GO (1 30)
@@ -78,7 +63,4 @@ struct slink_tegra {
#define SLINK_STAT2_RXF_FULL_CNT (1 16)
#define SLINK_STAT2_TXF_FULL_CNT (1 0)
-#define SPI_TIMEOUT1000
-#define TEGRA_SPI_MAX_FREQ 5200
-
#endif /* _TEGRA30_SPI_H_ */
diff --git a/drivers/spi/tegra20_spi.c b/drivers/spi/tegra20_spi.c
index 9e5de68..d6567f8 100644
--- a/drivers/spi/tegra20_spi.c
+++ b/drivers/spi/tegra20_spi.c
@@ -36,15 +36,28 @@
DECLARE_GLOBAL_DATA_PTR;
+#define SPI_TIMEOUT1000
+#define TEGRA_SPI_MAX_FREQ 5200
+
#if defined(CONFIG_SPI_CORRUPTS_UART)
#define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
#else
#define corrupt_delay()
#endif
+struct spi_regs {
+ u32 command;/* SPI_COMMAND_0 register */
+ u32 status; /* SPI_STATUS_0 register */
+ u32 rx_cmp; /* SPI_RX_CMP_0 register */
+ u32 dma_ctl;/* SPI_DMA_CTL_0 register */
+ u32 tx_fifo;/* SPI_TX_FIFO_0 register */
+ u32 rsvd[3];/* offsets 0x14 to 0x1F reserved */
+ u32 rx_fifo;/* SPI_RX_FIFO_0 register */
+};
+
struct tegra_spi_slave {
struct spi_slave slave;
- struct spi_tegra *regs;
+ struct spi_regs *regs;
unsigned int freq;
unsigned int mode;
int periph_id;
@@ -100,7 +113,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
debug(%s: sflash is disabled\n, __func__);
return NULL;
}
- spi-regs = (struct spi_tegra *)fdtdec_get_addr(gd-fdt_blob,
+ spi-regs = (struct spi_regs *)fdtdec_get_addr(gd-fdt_blob,
node, reg);
if ((fdt_addr_t)spi-regs == FDT_ADDR_T_NONE) {
debug(%s: no sflash register found\n, __func__);
@@ -143,7 +156,7 @@ void spi_init(void)
int spi_claim_bus(struct spi_slave *slave)
{
struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_tegra *regs = spi-regs;
+ struct spi_regs *regs = spi-regs;
u32 reg;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
@@ -222,7 +235,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *data_out, void *data_in, unsigned long flags
[U-Boot] [PATCH 05/14] spi: add common fdt SPI driver interface
Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: Allen Martin amar...@nvidia.com --- arch/arm/include/asm/arch-tegra20/tegra20_spi.h | 11 ++ arch/arm/include/asm/arch-tegra30/tegra30_spi.h | 11 ++ board/nvidia/common/board.c |2 +- drivers/spi/Makefile|1 + drivers/spi/fdt_spi.c | 172 +++ drivers/spi/tegra20_spi.c | 41 ++ drivers/spi/tegra30_spi.c | 33 ++--- include/configs/cardhu.h|2 +- include/configs/tegra-common-post.h |4 + 9 files changed, 228 insertions(+), 49 deletions(-) create mode 100644 drivers/spi/fdt_spi.c diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_spi.h b/arch/arm/include/asm/arch-tegra20/tegra20_spi.h index 6789881..b272fc5 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra20_spi.h +++ b/arch/arm/include/asm/arch-tegra20/tegra20_spi.h @@ -59,4 +59,15 @@ #define SPI_STAT_SEL_TXRX_N(1 16) #define SPI_STAT_CUR_BLKCNT(1 15) +int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs); +struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); +void tegra20_spi_free_slave(struct spi_slave *slave); +int tegra20_spi_init(int *node_list, int count); +int tegra20_spi_claim_bus(struct spi_slave *slave); +void tegra20_spi_cs_activate(struct spi_slave *slave); +void tegra20_spi_cs_deactivate(struct spi_slave *slave); +int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, +const void *data_out, void *data_in, unsigned long flags); + #endif /* _TEGRA20_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/tegra30_spi.h b/arch/arm/include/asm/arch-tegra30/tegra30_spi.h index 87a8169..234a468 100644 --- a/arch/arm/include/asm/arch-tegra30/tegra30_spi.h +++ b/arch/arm/include/asm/arch-tegra30/tegra30_spi.h @@ -63,4 +63,15 @@ #define SLINK_STAT2_RXF_FULL_CNT (1 16) #define SLINK_STAT2_TXF_FULL_CNT (1 0) +int tegra30_spi_init(int *node_list, int count); +int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs); +struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); +void tegra30_spi_free_slave(struct spi_slave *slave); +int tegra30_spi_claim_bus(struct spi_slave *slave); +void tegra30_spi_cs_activate(struct spi_slave *slave); +void tegra30_spi_cs_deactivate(struct spi_slave *slave); +int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, +const void *data_out, void *data_in, unsigned long flags); + #endif /* _TEGRA30_SPI_H_ */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 18e6420..30e71a6 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -131,7 +131,7 @@ int board_init(void) #ifdef CONFIG_SPI_UART_SWITCH gpio_config_uart(); #endif -#if defined(CONFIG_TEGRA20_SPI) || defined(CONFIG_TEGRA30_SPI) +#ifdef CONFIG_FDT_SPI pin_mux_spi(); spi_init(); #endif diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index e9fccb5..5551d01 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -45,6 +45,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o +COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SPI) += tegra20_spi.o COBJS-$(CONFIG_TEGRA30_SPI) += tegra30_spi.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c new file mode 100644 index 000..1a3937a --- /dev/null +++ b/drivers/spi/fdt_spi.c @@ -0,0 +1,172 @@ +/* + * Common fdt based SPI driver front end + * + * Copyright (c) 2013 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include common.h +#include malloc.h
[U-Boot] [PATCH 06/14] sf: winbond: add W25Q32DW
Add support for Winbond W25Q32DW 32Mbit part
Signed-off-by: Allen Martin amar...@nvidia.com
---
drivers/mtd/spi/winbond.c |5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index f6aab3d..9156957 100644
--- a/drivers/mtd/spi/winbond.c
+++ b/drivers/mtd/spi/winbond.c
@@ -67,6 +67,11 @@ static const struct winbond_spi_flash_params
winbond_spi_flash_table[] = {
.nr_blocks = 128,
.name = W25Q80,
},
+ {
+ .id = 0x6016,
+ .nr_blocks = 512,
+ .name = W25Q32DW,
+ },
};
struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
--
1.7.10.4
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[U-Boot] [PATCH 13/14] tegra114: add SPI driver
Add driver for tegra114 SPI controller. This controller is not compatible with either the tegra20 or tegra30 controllers, so it requires a new driver. Signed-off-by: Allen Martin amar...@nvidia.com --- arch/arm/include/asm/arch-tegra114/tegra114_spi.h | 91 ++ drivers/spi/Makefile |1 + drivers/spi/fdt_spi.c | 15 + drivers/spi/tegra114_spi.c| 355 + include/configs/tegra-common-post.h |2 +- 5 files changed, 463 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-tegra114/tegra114_spi.h create mode 100644 drivers/spi/tegra114_spi.c diff --git a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h new file mode 100644 index 000..bfbfa21 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h @@ -0,0 +1,91 @@ +/* + * NVIDIA Tegra SPI controller + * + * Copyright 2010-2013 NVIDIA Corporation + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA114_SPI_H_ +#define _TEGRA114_SPI_H_ + +#include asm/types.h + +/* COMMAND1 */ +#define SPI_CMD1_GO(1 31) +#define SPI_CMD1_M_S (1 30) +#define SPI_CMD1_MODE_MASK 0x3 +#define SPI_CMD1_MODE_SHIFT28 +#define SPI_CMD1_CS_SEL_MASK 0x3 +#define SPI_CMD1_CS_SEL_SHIFT 26 +#define SPI_CMD1_CS_POL_INACTIVE3 (1 25) +#define SPI_CMD1_CS_POL_INACTIVE2 (1 24) +#define SPI_CMD1_CS_POL_INACTIVE1 (1 23) +#define SPI_CMD1_CS_POL_INACTIVE0 (1 22) +#define SPI_CMD1_CS_SW_HW (1 21) +#define SPI_CMD1_CS_SW_VAL (1 20) +#define SPI_CMD1_IDLE_SDA_MASK 0x3 +#define SPI_CMD1_IDLE_SDA_SHIFT18 +#define SPI_CMD1_BIDIR (1 17) +#define SPI_CMD1_LSBI_FE (1 16) +#define SPI_CMD1_LSBY_FE (1 15) +#define SPI_CMD1_BOTH_EN_BIT (1 14) +#define SPI_CMD1_BOTH_EN_BYTE (1 13) +#define SPI_CMD1_RX_EN (1 12) +#define SPI_CMD1_TX_EN (1 11) +#define SPI_CMD1_PACKED(1 5) +#define SPI_CMD1_BIT_LEN_MASK 0x1F +#define SPI_CMD1_BIT_LEN_SHIFT 0 + +/* COMMAND2 */ +#define SPI_CMD2_TX_CLK_TAP_DELAY (1 6) +#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F 6) +#define SPI_CMD2_RX_CLK_TAP_DELAY (1 0) +#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F 0) + +/* TRANSFER STATUS */ +#define SPI_XFER_STS_RDY (1 30) + +/* FIFO STATUS */ +#define SPI_FIFO_STS_CS_INACTIVE (1 31) +#define SPI_FIFO_STS_FRAME_END (1 30) +#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 15) +#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 14) +#define SPI_FIFO_STS_ERR (1 8) +#define SPI_FIFO_STS_TX_FIFO_OVF (1 7) +#define SPI_FIFO_STS_TX_FIFO_UNR (1 6) +#define SPI_FIFO_STS_RX_FIFO_OVF (1 5) +#define SPI_FIFO_STS_RX_FIFO_UNR (1 4) +#define SPI_FIFO_STS_TX_FIFO_FULL (1 3) +#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 2) +#define SPI_FIFO_STS_RX_FIFO_FULL (1 1) +#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 0) + +int tegra114_spi_init(int *node_list, int count); +int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs); +struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); +void tegra114_spi_free_slave(struct spi_slave *slave); +int tegra114_spi_claim_bus(struct spi_slave *slave); +void tegra114_spi_cs_activate(struct spi_slave *slave); +void tegra114_spi_cs_deactivate(struct spi_slave *slave); +int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, +const void *data_out, void *data_in, unsigned long flags); + +#endif /* _TEGRA114_SPI_H_ */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 5551d01..275b70f 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -48,6 +48,7 @@ COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SPI) += tegra20_spi.o COBJS-$(CONFIG_TEGRA30_SPI
[U-Boot] [PATCH 01/14] tegra: spi: rename tegra SPI drivers
Rename tegra SPI drivers to tegra20_spi and tegra30_spi in preparation
for commonization and addition of tegra114_spi.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/tegra_slink.h | 84 --
arch/arm/include/asm/arch-tegra/tegra_spi.h | 75 -
arch/arm/include/asm/arch-tegra20/tegra20_spi.h | 75 +
arch/arm/include/asm/arch-tegra30/tegra30_spi.h | 84 ++
board/nvidia/common/board.c |2 +-
board/nvidia/common/uart-spi-switch.c |2 +-
drivers/spi/Makefile|4 +-
drivers/spi/tegra20_spi.c | 330 ++
drivers/spi/tegra30_spi.c | 343 +++
drivers/spi/tegra_slink.c | 343 ---
drivers/spi/tegra_spi.c | 330 --
include/configs/cardhu.h|2 +-
include/configs/trimslice.h |2 +-
13 files changed, 838 insertions(+), 838 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h
delete mode 100644 arch/arm/include/asm/arch-tegra/tegra_spi.h
create mode 100644 arch/arm/include/asm/arch-tegra20/tegra20_spi.h
create mode 100644 arch/arm/include/asm/arch-tegra30/tegra30_spi.h
create mode 100644 drivers/spi/tegra20_spi.c
create mode 100644 drivers/spi/tegra30_spi.c
delete mode 100644 drivers/spi/tegra_slink.c
delete mode 100644 drivers/spi/tegra_spi.c
diff --git a/arch/arm/include/asm/arch-tegra/tegra_slink.h
b/arch/arm/include/asm/arch-tegra/tegra_slink.h
deleted file mode 100644
index 74804b5..000
--- a/arch/arm/include/asm/arch-tegra/tegra_slink.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * NVIDIA Tegra SPI-SLINK controller
- *
- * Copyright 2010-2013 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA_SLINK_H_
-#define _TEGRA_SLINK_H_
-
-#include asm/types.h
-
-struct slink_tegra {
- u32 command;/* SLINK_COMMAND_0 register */
- u32 command2; /* SLINK_COMMAND2_0 reg */
- u32 status; /* SLINK_STATUS_0 register */
- u32 reserved; /* Reserved offset 0C */
- u32 mas_data; /* SLINK_MAS_DATA_0 reg */
- u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
- u32 dma_ctl;/* SLINK_DMA_CTL_0 register */
- u32 status2;/* SLINK_STATUS2_0 reg */
- u32 rsvd[56]; /* 0x20 to 0xFF reserved */
- u32 tx_fifo;/* SLINK_TX_FIFO_0 reg off 100h */
- u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
- u32 rx_fifo;/* SLINK_RX_FIFO_0 reg off 180h */
-};
-
-/* COMMAND */
-#define SLINK_CMD_ENB (1 31)
-#define SLINK_CMD_GO (1 30)
-#define SLINK_CMD_M_S (1 28)
-#define SLINK_CMD_CK_SDA (1 21)
-#define SLINK_CMD_CS_POL (1 13)
-#define SLINK_CMD_CS_VAL (1 12)
-#define SLINK_CMD_CS_SOFT (1 11)
-#define SLINK_CMD_BIT_LENGTH (1 4)
-#define SLINK_CMD_BIT_LENGTH_MASK 0x001F
-/* COMMAND2 */
-#define SLINK_CMD2_TXEN(1 30)
-#define SLINK_CMD2_RXEN(1 31)
-#define SLINK_CMD2_SS_EN (1 18)
-#define SLINK_CMD2_SS_EN_SHIFT 18
-#define SLINK_CMD2_SS_EN_MASK 0x000C
-#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 17)
-/* STATUS */
-#define SLINK_STAT_BSY (1 31)
-#define SLINK_STAT_RDY (1 30)
-#define SLINK_STAT_ERR (1 29)
-#define SLINK_STAT_RXF_FLUSH (1 27)
-#define SLINK_STAT_TXF_FLUSH (1 26)
-#define SLINK_STAT_RXF_OVF (1 25)
-#define SLINK_STAT_TXF_UNR (1 24)
-#define SLINK_STAT_RXF_EMPTY (1 23)
-#define SLINK_STAT_RXF_FULL(1 22)
-#define SLINK_STAT_TXF_EMPTY (1 21)
-#define SLINK_STAT_TXF_FULL(1 20)
-#define SLINK_STAT_TXF_OVF (1 19)
-#define SLINK_STAT_RXF_UNR (1 18)
-#define SLINK_STAT_CUR_BLKCNT (1 15)
-/* STATUS2 */
-#define SLINK_STAT2_RXF_FULL_CNT (1 16)
-#define SLINK_STAT2_TXF_FULL_CNT (1
Re: [U-Boot] [PATCH v3 7/7] Tegra114: Add/enable Dalmore build (T114 reference board)
On Mon, Jan 28, 2013 at 03:32:13PM -0800, Tom Warren wrote: This build is stripped down. It boots to the command prompt. GPIO is the only peripheral supported. Others TBD. Signed-off-by: Tom Warren twar...@nvidia.com --- Changes in v2: - update all new copyright header dates to 2013 - use correct table names in pinmux_init Changes in v3: - none ... + +#define MACH_TYPE_DALMORE 4304/* not yet in mach-types.h */ + Why not just update mach-types.h? -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC Patch v6] Consolidate bool type
On Wed, Jan 30, 2013 at 11:47:57AM -0800, York Sun wrote: On 01/30/2013 11:40 AM, Allen Martin wrote: On Wed, Jan 30, 2013 at 10:37:30AM -0800, York Sun wrote: On 01/24/2013 05:00 PM, Allen Martin wrote: I think you can drop the RFC from your patch at this point. Built on all tegra20 and tegra30 devices with USE_PRIVATE_LIBGCC. Tested on seaboard (tegra20). I've also submitted your patch to my build regression script which will build all 1100+ boards against your patch and tell if there are any build regressions. I'll let you know the results tomorrow. Allen, Is any change needed? Hi York, sorry I forgot to get back to you. I ran your patch through all boards and so no warning or error build regressions. Looking at the logs it looks like I ran it on version 5 not version 6 of your patch though. I'll do another run tonight on version 6 and let you know the results. I don't anticipate any problems though as it looks like the only differences are dropping the python files and whitespace changes. Allen, Your help is greatly appreciated. York Compiled against all boards, no warning or error regressions detected. Tested on tegra20 trimslice and tegra30 cardhu. Acked-by: Allen Martin amar...@nvidia.com -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the README
On Tue, Jan 22, 2013 at 06:12:47AM -0800, Simon Glass wrote:
On Tue, Jan 22, 2013 at 2:15 AM, Lucas Stach d...@lynxeye.de wrote:
No one expects to end up in a delayed environment if
CONFIG_DELAY_ENVIRONMENT isn't defined.
Signed-off-by: Lucas Stach d...@lynxeye.de
Good with me, and solves the immediate problem. Thanks for doing the patch.
Acked-by: Simon Glass s...@chromium.org
Adding Tom Rini and Albert. What's the best way to get this up to
u-boot/master as quickly as possible? Environment is broken on all
boards that use fdt until this goes in.
-Allen
---
v2: keep preference of CONFIG_OF_CONTROL and just change default value
---
arch/arm/lib/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index cfe32cc..9f861cc 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -488,7 +488,7 @@ static char *failed = *** failed ***\n;
static int should_load_env(void)
{
#ifdef CONFIG_OF_CONTROL
- return fdtdec_get_config_int(gd-fdt_blob, load-environment, 0);
+ return fdtdec_get_config_int(gd-fdt_blob, load-environment, 1);
#elif defined CONFIG_DELAY_ENVIRONMENT
return 0;
#else
--
1.8.0.2
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Re: [U-Boot] [RFC Patch v6] Consolidate bool type
On Wed, Jan 30, 2013 at 03:09:56PM -0800, York Sun wrote: On 01/30/2013 02:53 PM, Allen Martin wrote: On Wed, Jan 30, 2013 at 11:47:57AM -0800, York Sun wrote: On 01/30/2013 11:40 AM, Allen Martin wrote: On Wed, Jan 30, 2013 at 10:37:30AM -0800, York Sun wrote: On 01/24/2013 05:00 PM, Allen Martin wrote: I think you can drop the RFC from your patch at this point. Built on all tegra20 and tegra30 devices with USE_PRIVATE_LIBGCC. Tested on seaboard (tegra20). I've also submitted your patch to my build regression script which will build all 1100+ boards against your patch and tell if there are any build regressions. I'll let you know the results tomorrow. Allen, Is any change needed? Hi York, sorry I forgot to get back to you. I ran your patch through all boards and so no warning or error build regressions. Looking at the logs it looks like I ran it on version 5 not version 6 of your patch though. I'll do another run tonight on version 6 and let you know the results. I don't anticipate any problems though as it looks like the only differences are dropping the python files and whitespace changes. Allen, Your help is greatly appreciated. York Compiled against all boards, no warning or error regressions detected. Tested on tegra20 trimslice and tegra30 cardhu. Acked-by: Allen Martin amar...@nvidia.com Thanks a lot, Allen. I will send v7 with RFC removed from subject and add your ack. York Thank you for taking on such a monster of a patch! Also, either my blackfin toolchain is broken, or every blackfin board doesn't compile (even without this patch). You may want to have someone who has a known working blackfin build check the patch too. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the README
On Wed, Jan 30, 2013 at 04:31:42PM -0800, Tom Rini wrote: * PGP Signed by an unknown key On Wed, Jan 30, 2013 at 03:04:53PM -0800, Allen Martin wrote: On Tue, Jan 22, 2013 at 06:12:47AM -0800, Simon Glass wrote: On Tue, Jan 22, 2013 at 2:15 AM, Lucas Stach d...@lynxeye.de wrote: No one expects to end up in a delayed environment if CONFIG_DELAY_ENVIRONMENT isn't defined. Signed-off-by: Lucas Stach d...@lynxeye.de Good with me, and solves the immediate problem. Thanks for doing the patch. Acked-by: Simon Glass s...@chromium.org Adding Tom Rini and Albert. What's the best way to get this up to u-boot/master as quickly as possible? Environment is broken on all boards that use fdt until this goes in. I can just grab this directly since everyone is happy. now. That would be great, thanks! -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] CONFIG_DELAY_ENVIRONMENT usage
On Tue, Jan 29, 2013 at 10:08:39PM -0800, Lucas Stach wrote:
Hi Allen,
Am Dienstag, den 29.01.2013, 19:05 -0800 schrieb Allen Martin:
The problem I'm seeing is that this regressed environment loading on
all boards that use fdt, because none of them have
/config/load-environment defined. If I read the commit message
correctly, I think the actual intention is:
static int should_load_env(void)
{
#ifdef CONFIG_DELAY_ENVIRONMENT
#ifdef CONFIG_OF_CONTROL
return fdtdec_get_config_int(gd-fdt_blob, load-environment,
0);
#else
return 0;
#endif
#else
return 1;
#endif
}
There is already a patch for that on the mailing list. See
http://www.mail-archive.com/u-boot@lists.denx.de/msg103841.html
We agreed that just swapping around the default value for the FDT case
is the right thing to do.
Thanks for the pointer Lucas, I didn't notice the previous patch.
-Allen
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Re: [U-Boot] [PATCH v2] arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the README
On Tue, Jan 22, 2013 at 02:15:49AM -0800, Lucas Stach wrote:
No one expects to end up in a delayed environment if
CONFIG_DELAY_ENVIRONMENT isn't defined.
Signed-off-by: Lucas Stach d...@lynxeye.de
---
v2: keep preference of CONFIG_OF_CONTROL and just change default value
---
arch/arm/lib/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index cfe32cc..9f861cc 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -488,7 +488,7 @@ static char *failed = *** failed ***\n;
static int should_load_env(void)
{
#ifdef CONFIG_OF_CONTROL
- return fdtdec_get_config_int(gd-fdt_blob, load-environment, 0);
+ return fdtdec_get_config_int(gd-fdt_blob, load-environment, 1);
#elif defined CONFIG_DELAY_ENVIRONMENT
return 0;
#else
--
1.8.0.2
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Tested on tegra20 trimslice
Acked-by: Allen Martin amar...@nvidia.com
--
nvpublic
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Re: [U-Boot] [RFC Patch v6] Consolidate bool type
On Wed, Jan 30, 2013 at 10:37:30AM -0800, York Sun wrote: On 01/24/2013 05:00 PM, Allen Martin wrote: I think you can drop the RFC from your patch at this point. Built on all tegra20 and tegra30 devices with USE_PRIVATE_LIBGCC. Tested on seaboard (tegra20). I've also submitted your patch to my build regression script which will build all 1100+ boards against your patch and tell if there are any build regressions. I'll let you know the results tomorrow. Allen, Is any change needed? Hi York, sorry I forgot to get back to you. I ran your patch through all boards and so no warning or error build regressions. Looking at the logs it looks like I ran it on version 5 not version 6 of your patch though. I'll do another run tonight on version 6 and let you know the results. I don't anticipate any problems though as it looks like the only differences are dropping the python files and whitespace changes. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 1/7] tegra20: fdt: add SPI SFLASH node
Add node for tegra20 SPI SFLASH controller to fdt.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/dts/tegra20.dtsi| 12
board/compulab/dts/tegra20-trimslice.dts |5 +
2 files changed, 17 insertions(+)
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 12049fd..9a89685 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -236,6 +236,18 @@
clocks = tegra_car 12, tegra_car 124;
};
+ spi@7000c380 {
+ compatible = nvidia,tegra20-sflash;
+ reg = 0x7000c380 0x80;
+ interrupts = 0 39 0x04;
+ nvidia,dma-request-selector = apbdma 11;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SPI1, PLLP_OUT0 */
+ clocks = tegra_car 43;
+ };
+
i2c@7000c400 {
#address-cells = 1;
#size-cells = 0;
diff --git a/board/compulab/dts/tegra20-trimslice.dts
b/board/compulab/dts/tegra20-trimslice.dts
index c8a4dd4..7aeed67 100644
--- a/board/compulab/dts/tegra20-trimslice.dts
+++ b/board/compulab/dts/tegra20-trimslice.dts
@@ -23,6 +23,11 @@
status = disabled;
};
+ spi@7000c380 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
+
i2c@7000c400 {
status = disabled;
};
--
1.7.10.4
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[U-Boot] [PATCH v4 3/7] tegra30: add SBC1 to periph id mapping table
SBC1 is SPI controller 1 on tegra30
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Simon Glass s...@chromium.org
---
arch/arm/cpu/tegra30-common/clock.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/tegra30-common/clock.c
b/arch/arm/cpu/tegra30-common/clock.c
index ee3c8b1..a93f2c9 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -290,7 +290,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
/* 40 */
NONE(KFUSE),
- NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
+ PERIPHC_SBC1,
PERIPHC_NOR,
NONE(RESERVED43),
PERIPHC_SBC2,
--
1.7.10.4
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[U-Boot] [PATCH v4 2/7] tegra: spi: add fdt support to tegra SPI SFLASH driver
Add support for configuring tegra SPI driver from devicetree.
Support is keyed off CONFIG_OF_CONTROL. Add entry in seaboard dts
file for spi controller to describe seaboard spi.
Signed-off-by: Allen Martin amar...@nvidia.com
---
drivers/spi/tegra_spi.c | 45 +++--
include/fdtdec.h|1 +
lib/fdtdec.c|1 +
3 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c
index 9bb34e2..ce19095 100644
--- a/drivers/spi/tegra_spi.c
+++ b/drivers/spi/tegra_spi.c
@@ -32,6 +32,9 @@
#include asm/arch-tegra/clk_rst.h
#include asm/arch-tegra/tegra_spi.h
#include spi.h
+#include fdtdec.h
+
+DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPI_CORRUPTS_UART)
#define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
@@ -44,6 +47,7 @@ struct tegra_spi_slave {
struct spi_tegra *regs;
unsigned int freq;
unsigned int mode;
+ int periph_id;
};
static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
@@ -84,8 +88,45 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
}
spi-slave.bus = bus;
spi-slave.cs = cs;
- spi-freq = max_hz;
+#ifdef CONFIG_OF_CONTROL
+ int node = fdtdec_next_compatible(gd-fdt_blob, 0,
+ COMPAT_NVIDIA_TEGRA20_SFLASH);
+ if (node 0) {
+ debug(%s: cannot locate sflash node\n, __func__);
+ return NULL;
+ }
+ if (!fdtdec_get_is_enabled(gd-fdt_blob, node)) {
+ debug(%s: sflash is disabled\n, __func__);
+ return NULL;
+ }
+ spi-regs = (struct spi_tegra *)fdtdec_get_addr(gd-fdt_blob,
+ node, reg);
+ if ((fdt_addr_t)spi-regs == FDT_ADDR_T_NONE) {
+ debug(%s: no sflash register found\n, __func__);
+ return NULL;
+ }
+ spi-freq = fdtdec_get_int(gd-fdt_blob, node, spi-max-frequency, 0);
+ if (!spi-freq) {
+ debug(%s: no sflash max frequency found\n, __func__);
+ return NULL;
+ }
+ spi-periph_id = clock_decode_periph_id(gd-fdt_blob, node);
+ if (spi-periph_id == PERIPH_ID_NONE) {
+ debug(%s: could not decode periph id\n, __func__);
+ return NULL;
+ }
+#else
spi-regs = (struct spi_tegra *)NV_PA_SPI_BASE;
+ spi-freq = TEGRA_SPI_MAX_FREQ;
+ spi-periph_id = PERIPH_ID_SPI1;
+#endif
+ if (max_hz spi-freq) {
+ debug(%s: limiting frequency from %u to %u\n, __func__,
+ spi-freq, max_hz);
+ spi-freq = max_hz;
+ }
+ debug(%s: controller initialized at %p, freq = %u, periph_id = %d\n,
+ __func__, spi-regs, spi-freq, spi-periph_id);
spi-mode = mode;
return spi-slave;
@@ -110,7 +151,7 @@ int spi_claim_bus(struct spi_slave *slave)
u32 reg;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi-freq);
+ clock_start_periph_pll(spi-periph_id, CLOCK_ID_PERIPH, spi-freq);
/* Clear stale status here */
reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
diff --git a/include/fdtdec.h b/include/fdtdec.h
index f77d195..5b67a77 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -70,6 +70,7 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
+ COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */
COMPAT_SMSC_LAN9215,/* SMSC 10/100 Ethernet LAN9215 */
COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 16921e1..385e0e5 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -45,6 +45,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA20_NAND, nvidia,tegra20-nand),
COMPAT(NVIDIA_TEGRA20_PWM, nvidia,tegra20-pwm),
COMPAT(NVIDIA_TEGRA20_DC, nvidia,tegra20-dc),
+ COMPAT(NVIDIA_TEGRA20_SFLASH, nvidia,tegra20-sflash),
COMPAT(SMSC_LAN9215, smsc,lan9215),
COMPAT(SAMSUNG_EXYNOS5_SROMC, samsung,exynos-sromc),
COMPAT(SAMSUNG_S3C2440_I2C, samsung,s3c2440-i2c),
--
1.7.10.4
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[U-Boot] [PATCH v4 5/7] tegra: add addresses of SPI SLINK controllers
Add I/O addresses of SPI SLINK controllers 1-6 Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Simon Glass s...@chromium.org --- arch/arm/include/asm/arch-tegra/tegra.h |6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index f97cfd0..bf7229d 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -40,6 +40,12 @@ #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) #define NV_PA_NAND_BASE(NV_PA_APB_MISC_BASE + 0x8000) #define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) +#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400) +#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600) +#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800) +#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00) +#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) +#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) #define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) #define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 7/7] tegra: cardhu: config: enable SPI
Turn on SPI in cardhu config file Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Simon Glass s...@chromium.org --- include/configs/cardhu.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index aa725ba..1616b39 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -49,6 +49,17 @@ #define CONFIG_ENV_IS_NOWHERE +/* SPI */ +#define CONFIG_TEGRA_SLINK +#define CONFIG_TEGRA_SLINK_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED2400 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 20) + #include tegra-common-post.h #endif /* __CONFIG_H */ -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/7] tegra: SPI drivers
This series updates the tegra20 SPI driver to add fdt support and adds a new tegra30 SPI driver. Testing was done on trimslice (tegra20) and cardhu (tegra30). Changes in v4: -Added support for fdt aliases to slink driver -Check status field of fdt node to make sure node is enabled Changes in v3: -Dropped some fdt patches from the series that were picked up in u-boot-tegra/next already -Removed SPI node from seaboard, added to trimslice -Incorporated feedback from Simon Glass and Stephen Warren to slink driver Changes in v2: -Added new patch to sort dts files prior to adding new nodes -Moved max-spi-frequency out to board dts files -Moved tegra20 SFLASH fdt changes out to separate patch -Added valid flag to slink driver controller structure Allen Martin (7): tegra20: fdt: add SPI SFLASH node tegra: spi: add fdt support to tegra SPI SFLASH driver tegra30: add SBC1 to periph id mapping table tegra30: fdt: add SPI SLINK nodes tegra: add addresses of SPI SLINK controllers tegra: add SPI SLINK driver tegra: cardhu: config: enable SPI arch/arm/cpu/tegra30-common/clock.c |2 +- arch/arm/dts/tegra20.dtsi | 12 + arch/arm/dts/tegra30.dtsi | 72 ++ arch/arm/include/asm/arch-tegra/tegra.h |6 + arch/arm/include/asm/arch-tegra/tegra_slink.h | 84 ++ board/compulab/dts/tegra20-trimslice.dts |5 + board/nvidia/common/board.c |3 +- board/nvidia/dts/tegra30-cardhu.dts |5 + drivers/spi/Makefile |1 + drivers/spi/tegra_slink.c | 343 + drivers/spi/tegra_spi.c | 45 +++- include/configs/cardhu.h | 11 + include/fdtdec.h |2 + lib/fdtdec.c |2 + 14 files changed, 589 insertions(+), 4 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h create mode 100644 drivers/spi/tegra_slink.c -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 6/7] tegra: add SPI SLINK driver
Add driver for tegra SPI SLINK style driver. This controller is
similar to the tegra20 SPI SFLASH controller. The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices. In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH. Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.
This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.
To enable this driver, use CONFIG_TEGRA_SLINK
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/tegra_slink.h | 84 ++
board/nvidia/common/board.c |3 +-
drivers/spi/Makefile |1 +
drivers/spi/tegra_slink.c | 343 +
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
6 files changed, 432 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h
create mode 100644 drivers/spi/tegra_slink.c
diff --git a/arch/arm/include/asm/arch-tegra/tegra_slink.h
b/arch/arm/include/asm/arch-tegra/tegra_slink.h
new file mode 100644
index 000..74804b5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/tegra_slink.h
@@ -0,0 +1,84 @@
+/*
+ * NVIDIA Tegra SPI-SLINK controller
+ *
+ * Copyright 2010-2013 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_SLINK_H_
+#define _TEGRA_SLINK_H_
+
+#include asm/types.h
+
+struct slink_tegra {
+ u32 command;/* SLINK_COMMAND_0 register */
+ u32 command2; /* SLINK_COMMAND2_0 reg */
+ u32 status; /* SLINK_STATUS_0 register */
+ u32 reserved; /* Reserved offset 0C */
+ u32 mas_data; /* SLINK_MAS_DATA_0 reg */
+ u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
+ u32 dma_ctl;/* SLINK_DMA_CTL_0 register */
+ u32 status2;/* SLINK_STATUS2_0 reg */
+ u32 rsvd[56]; /* 0x20 to 0xFF reserved */
+ u32 tx_fifo;/* SLINK_TX_FIFO_0 reg off 100h */
+ u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
+ u32 rx_fifo;/* SLINK_RX_FIFO_0 reg off 180h */
+};
+
+/* COMMAND */
+#define SLINK_CMD_ENB (1 31)
+#define SLINK_CMD_GO (1 30)
+#define SLINK_CMD_M_S (1 28)
+#define SLINK_CMD_CK_SDA (1 21)
+#define SLINK_CMD_CS_POL (1 13)
+#define SLINK_CMD_CS_VAL (1 12)
+#define SLINK_CMD_CS_SOFT (1 11)
+#define SLINK_CMD_BIT_LENGTH (1 4)
+#define SLINK_CMD_BIT_LENGTH_MASK 0x001F
+/* COMMAND2 */
+#define SLINK_CMD2_TXEN(1 30)
+#define SLINK_CMD2_RXEN(1 31)
+#define SLINK_CMD2_SS_EN (1 18)
+#define SLINK_CMD2_SS_EN_SHIFT 18
+#define SLINK_CMD2_SS_EN_MASK 0x000C
+#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 17)
+/* STATUS */
+#define SLINK_STAT_BSY (1 31)
+#define SLINK_STAT_RDY (1 30)
+#define SLINK_STAT_ERR (1 29)
+#define SLINK_STAT_RXF_FLUSH (1 27)
+#define SLINK_STAT_TXF_FLUSH (1 26)
+#define SLINK_STAT_RXF_OVF (1 25)
+#define SLINK_STAT_TXF_UNR (1 24)
+#define SLINK_STAT_RXF_EMPTY (1 23)
+#define SLINK_STAT_RXF_FULL(1 22)
+#define SLINK_STAT_TXF_EMPTY (1 21)
+#define SLINK_STAT_TXF_FULL(1 20)
+#define SLINK_STAT_TXF_OVF (1 19)
+#define SLINK_STAT_RXF_UNR (1 18)
+#define SLINK_STAT_CUR_BLKCNT (1 15)
+/* STATUS2 */
+#define SLINK_STAT2_RXF_FULL_CNT (1 16)
+#define SLINK_STAT2_TXF_FULL_CNT (1 0)
+
+#define SPI_TIMEOUT1000
+#define TEGRA_SPI_MAX_FREQ 5200
+
+#endif /* _TEGRA_SLINK_H_ */
diff
[U-Boot] [PATCH v4 4/7] tegra30: fdt: add SPI SLINK nodes
Add tegra30 SPI SLINK nodes to fdt.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Simon Glass s...@chromium.org
---
arch/arm/dts/tegra30.dtsi | 72 +++
board/nvidia/dts/tegra30-cardhu.dts |5 +++
2 files changed, 77 insertions(+)
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index aa7e7ae..7b8126f 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -90,4 +90,76 @@
/* PERIPH_ID_I2C_DVC, CLK_M */
clocks = tegra_car 47;
};
+
+ spi@7000d400 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000d400 0x200;
+ interrupts = 0 59 0x04;
+ nvidia,dma-request-selector = apbdma 15;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC1, PLLP_OUT0 */
+ clocks = tegra_car 41;
+ };
+
+ spi@7000d600 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000d600 0x200;
+ interrupts = 0 82 0x04;
+ nvidia,dma-request-selector = apbdma 16;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC2, PLLP_OUT0 */
+ clocks = tegra_car 44;
+ };
+
+ spi@7000d800 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000d480 0x200;
+ interrupts = 0 83 0x04;
+ nvidia,dma-request-selector = apbdma 17;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC3, PLLP_OUT0 */
+ clocks = tegra_car 46;
+ };
+
+ spi@7000da00 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000da00 0x200;
+ interrupts = 0 93 0x04;
+ nvidia,dma-request-selector = apbdma 18;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC4, PLLP_OUT0 */
+ clocks = tegra_car 68;
+ };
+
+ spi@7000dc00 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000dc00 0x200;
+ interrupts = 0 94 0x04;
+ nvidia,dma-request-selector = apbdma 27;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC5, PLLP_OUT0 */
+ clocks = tegra_car 104;
+ };
+
+ spi@7000de00 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000de00 0x200;
+ interrupts = 0 79 0x04;
+ nvidia,dma-request-selector = apbdma 28;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC6, PLLP_OUT0 */
+ clocks = tegra_car 105;
+ };
};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts
b/board/nvidia/dts/tegra30-cardhu.dts
index 3223ed4..f9f80c5 100644
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -39,4 +39,9 @@
i2c@7000d000 {
clock-frequency = 10;
};
+
+ spi@7000da00 {
+ status = okay;
+ spi-max-frequency = 2500;
+ };
};
--
1.7.10.4
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Re: [U-Boot] [PATCH v4 0/7] tegra: SPI drivers
On Tue, Jan 29, 2013 at 03:51:22PM -0800, Allen Martin wrote: This series updates the tegra20 SPI driver to add fdt support and adds a new tegra30 SPI driver. Testing was done on trimslice (tegra20) and cardhu (tegra30). Tom, this series applies cleanly on top of your T114 series. Changes in v4: -Added support for fdt aliases to slink driver -Check status field of fdt node to make sure node is enabled Changes in v3: -Dropped some fdt patches from the series that were picked up in u-boot-tegra/next already -Removed SPI node from seaboard, added to trimslice -Incorporated feedback from Simon Glass and Stephen Warren to slink driver Changes in v2: -Added new patch to sort dts files prior to adding new nodes -Moved max-spi-frequency out to board dts files -Moved tegra20 SFLASH fdt changes out to separate patch -Added valid flag to slink driver controller structure Allen Martin (7): tegra20: fdt: add SPI SFLASH node tegra: spi: add fdt support to tegra SPI SFLASH driver tegra30: add SBC1 to periph id mapping table tegra30: fdt: add SPI SLINK nodes tegra: add addresses of SPI SLINK controllers tegra: add SPI SLINK driver tegra: cardhu: config: enable SPI arch/arm/cpu/tegra30-common/clock.c |2 +- arch/arm/dts/tegra20.dtsi | 12 + arch/arm/dts/tegra30.dtsi | 72 ++ arch/arm/include/asm/arch-tegra/tegra.h |6 + arch/arm/include/asm/arch-tegra/tegra_slink.h | 84 ++ board/compulab/dts/tegra20-trimslice.dts |5 + board/nvidia/common/board.c |3 +- board/nvidia/dts/tegra30-cardhu.dts |5 + drivers/spi/Makefile |1 + drivers/spi/tegra_slink.c | 343 + drivers/spi/tegra_spi.c | 45 +++- include/configs/cardhu.h | 11 + include/fdtdec.h |2 + lib/fdtdec.c |2 + 14 files changed, 589 insertions(+), 4 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h create mode 100644 drivers/spi/tegra_slink.c -- 1.7.10.4 -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] MAKEALL: add support for per architecture toolchains
Add support for per architecture CROSS_COMPILE toolchain definitions
via CROSS_COMPILE_ARCH where ARCH is any of the supported u-boot
architectures. This allows building every supported u-boot board in a
single pass of MAKEALL.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Simon Glass s...@chromium.org
---
v2: Changed CROSS_COMPILE_ARM to CROSS_COMPILE_ARCH in help text
---
MAKEALL | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 5b06c54..397adef 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -35,6 +35,9 @@ usage()
Environment variables:
BUILD_NCPUS number of parallel make jobs (default: auto)
CROSS_COMPILEcross-compiler toolchain prefix (default: )
+ CROSS_COMPILE_ARCH cross-compiler toolchain prefix for
+ architecture ARCH. Substitute ARCH for any
+ supported architecture (default: )
MAKEALL_LOGDIR output all logs to here (default: ./LOG/)
BUILD_DIRoutput build directory (default: ./)
BUILD_NBUILDSnumber of parallel targets (default: 1)
@@ -180,13 +183,6 @@ else
JOBS=
fi
-
-if [ ${CROSS_COMPILE} ] ; then
- MAKE=make CROSS_COMPILE=${CROSS_COMPILE}
-else
- MAKE=make
-fi
-
if [ ${MAKEALL_LOGDIR} ] ; then
LOG_DIR=${MAKEALL_LOGDIR}
else
@@ -585,6 +581,18 @@ get_target_maintainers() {
echo $mail
}
+get_target_arch() {
+ local target=$1
+
+ # Automatic mode
+ local line=`egrep -i ^[[:space:]]*${target}[[:space:]] boards.cfg`
+
+ if [ -z ${line} ] ; then echo ; return ; fi
+
+ set ${line}
+ echo $2
+}
+
list_target() {
if [ $PRINT_MAINTS != 'y' ] ; then
echo $1
@@ -655,6 +663,16 @@ build_target() {
export BUILD_DIR=${output_dir}
+ target_arch=$(get_target_arch ${target})
+ eval cross_toolchain=\$CROSS_COMPILE_${target_arch^^}
+ if [ ${cross_toolchain} ] ; then
+ MAKE=make CROSS_COMPILE=${cross_toolchain}
+ elif [ ${CROSS_COMPILE} ] ; then
+ MAKE=make CROSS_COMPILE=${CROSS_COMPILE}
+ else
+ MAKE=make
+ fi
+
${MAKE} distclean /dev/null
${MAKE} -s ${target}_config
--
1.7.10.4
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[U-Boot] CONFIG_DELAY_ENVIRONMENT usage
Simon, I had a question about your CONFIG_DELAY_ENVIRONMENT patch. In
the commit description it says:
When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a
run-time way of enabling loading of the environment. Add this to the
fdt as /config/delay-environment.
In the code, it's actually reading /config/load-environment, and it
defaults to prevent loading environment regardless if
CONFIG_DELAY_ENVIRONMENT is set or not:
static int should_load_env(void)
{
#ifdef CONFIG_OF_CONTROL
return fdtdec_get_config_int(gd-fdt_blob, load-environment, 0);
#elif defined CONFIG_DELAY_ENVIRONMENT
return 0;
#else
return 1;
#endif
}
The problem I'm seeing is that this regressed environment loading on
all boards that use fdt, because none of them have
/config/load-environment defined. If I read the commit message
correctly, I think the actual intention is:
static int should_load_env(void)
{
#ifdef CONFIG_DELAY_ENVIRONMENT
#ifdef CONFIG_OF_CONTROL
return fdtdec_get_config_int(gd-fdt_blob, load-environment,
0);
#else
return 0;
#endif
#else
return 1;
#endif
}
Is my understanding correct?
-Allen
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Re: [U-Boot] [PATCH] tegra: fdt: add back missing host1x node
Have you got the right Tom? This is for the Tegra tree (u-boot-tegra), not TI, Tom Warren, not Tom Rini. My PR *has* been taken into the ARM/master branch, AFAICT, and I never release PRs with warnings or errors that aren't already pre-existing in other ARM builds (VCMA9 and smdk2410, for instance). Allen's fix is for a Tegra DT file, not for any TI board/SoC/etc. My bad -- I've indeed mixed up Toms here. No worries, so would it be ok to take this patch in through the arm tree so the regression doesn't make it up into Wolfgang's tree? -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] tegra: fdt: add back missing host1x node
Add back host1x node to seaboard dts file. This got dropped during
the tegra fdt sort.
Signed-off-by: Allen Martin amar...@nvidia.com
---
board/nvidia/dts/tegra20-seaboard.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/board/nvidia/dts/tegra20-seaboard.dts
b/board/nvidia/dts/tegra20-seaboard.dts
index 9cb9b5b..527a296 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -27,6 +27,17 @@
reg = 0x 0x4000 ;
};
+ host1x {
+ status = okay;
+ dc@5420 {
+ status = okay;
+ rgb {
+ status = okay;
+ nvidia,panel = lcd_panel;
+ };
+ };
+ };
+
/* This is not used in U-Boot, but is expected to be in kernel .dts */
i2c@7000d000 {
clock-frequency = 10;
--
1.7.10.4
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Re: [U-Boot] [PATCH] tegra: fdt: add back missing host1x node
On Fri, Jan 25, 2013 at 10:46:47AM -0800, Allen Martin wrote:
Add back host1x node to seaboard dts file. This got dropped during
the tegra fdt sort.
Signed-off-by: Allen Martin amar...@nvidia.com
---
Hi Albert, would it be possible for you to apply this directly to your
u-boot-arm repository? It fixes a regression introduced by my
previous patch:
b7723f3 tegra: fdt: sort dts files
So I wanted to make sure it gets applied before that previous patch
makes it to u-boot/master, and Tom's not ready to do another tegra
pull request yet.
-Allen
board/nvidia/dts/tegra20-seaboard.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/board/nvidia/dts/tegra20-seaboard.dts
b/board/nvidia/dts/tegra20-seaboard.dts
index 9cb9b5b..527a296 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -27,6 +27,17 @@
reg = 0x 0x4000 ;
};
+ host1x {
+ status = okay;
+ dc@5420 {
+ status = okay;
+ rgb {
+ status = okay;
+ nvidia,panel = lcd_panel;
+ };
+ };
+ };
+
/* This is not used in U-Boot, but is expected to be in kernel .dts */
i2c@7000d000 {
clock-frequency = 10;
--
1.7.10.4
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Re: [U-Boot] [Patch v3] Consolidate bool type
On Wed, Jan 23, 2013 at 02:05:26PM -0800, York Sun wrote:
On 01/23/2013 02:02 PM, Scott Wood wrote:
On 01/23/2013 04:01:49 PM, York Sun wrote:
On 01/23/2013 01:52 PM, Scott Wood wrote:
On 01/23/2013 03:46:04 PM, York Sun wrote:
On 01/23/2013 01:41 PM, York Sun wrote:
I should put RFC in the subject as I am not able to compile all ARCH
myself.
So how do you see this patch becoming non-RFC? I think most people
don't have every single toolchain. You should at least get a toolchain
for a couple major architectures such as ARM. Usually RFC is for when
you know the patch has issues, and don't want it applied yet even if
nobody else finds fault with it.
I know this version has problem. I am hoping more people get involved
and test what they can. I tried the arm toolchain you pointed to me. I
couldn't run MAKEALL for arm.
Even before your patch, using USE_PRIVATE_LIBGCC? How many boards failed?
I don't know. Wolfgang brought it. Allen kindly offered help to verify
on tegra which uses USE_PRIVATE_LIBGCC.
Built and tested on tegra, no problems. I'm still seeing a lot of
references to TRUE/FALSE even after this patch though:
$ git grep -e FALSE -e TRUE | awk 'BEGIN {FS = :} {print $1}' | sort | uniq
arch/arm/cpu/arm926ejs/spear/spear600.c
arch/arm/cpu/arm926ejs/spear/spl_boot.c
arch/m68k/lib/interrupts.c
arch/nds32/lib/interrupts.c
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
Binary file tools/easylogo/linux_logo.tga matches
board/amcc/bamboo/bamboo.c
board/amcc/yucca/yucca.h
board/bf533-ezkit/flash.c
board/bf537-stamp/ide-cf.c
board/esd/common/lcd.c
board/esd/dasa_sim/cmd_dasa_sim.c
board/esd/pmc440/fpga.c
board/evb64260/eth_addrtbl.c
board/gen860t/fpga.c
board/matrix_vision/mvblx/mvblx.c
board/mousse/flash.c
board/mpl/common/isa.c
board/mpl/mip405/mip405.c
board/mpl/pip405/pip405.c
board/sacsng/clkinit.c
board/spear/x600/fpga.c
board/teejet/mt_ventoux/mt_ventoux.c
board/xilinx/common/xbasic_types.c
board/xilinx/common/xdma_channel.c
board/xilinx/common/xdma_channel_sg.c
board/xilinx/common/xipif_v1_23_b.h
board/xilinx/common/xpacket_fifo_v1_00_b.h
board/xilinx/common/xversion.c
common/bedbug.c
common/cmd_bedbug.c
common/cmd_fdc.c
common/cmd_scsi.c
drivers/bios_emulator/x86emu/debug.c
drivers/block/ahci.c
drivers/block/sata_dwc.c
drivers/block/sym53c8xx.c
drivers/dma/MCD_dmaApi.c
drivers/fpga/ACEX1K.c
drivers/fpga/altera.c
drivers/fpga/cyclon2.c
drivers/fpga/lattice.c
drivers/fpga/spartan2.c
drivers/fpga/spartan3.c
drivers/fpga/virtex2.c
drivers/fpga/xilinx.c
drivers/net/armada100_fec.c
drivers/net/e1000.c
drivers/net/e1000.h
drivers/net/e1000_spi.c
drivers/net/npe/include/IxAtmdAccCtrl.h
drivers/net/npe/include/IxEthAcc_p.h
drivers/net/npe/include/IxEthDB.h
drivers/net/npe/include/IxEthDB_p.h
drivers/net/npe/include/IxEthMii.h
drivers/net/npe/include/IxFeatureCtrl.h
drivers/net/npe/include/IxHssAcc.h
drivers/net/npe/include/IxNpeDl.h
drivers/net/npe/include/IxNpeDlNpeMgr_p.h
drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h
drivers/net/npe/include/IxNpeMhConfig_p.h
drivers/net/npe/include/IxOsal.h
drivers/net/npe/include/IxOsalTypes.h
drivers/net/npe/include/IxPerfProfAcc.h
drivers/net/npe/include/IxQMgrAqmIf_p.h
drivers/net/npe/include/IxTimeSyncAcc.h
drivers/net/npe/IxEthAcc.c
drivers/net/npe/IxEthAccCommon.c
drivers/net/npe/IxEthAccDataPlane.c
drivers/net/npe/IxEthAccMac.c
drivers/net/npe/IxEthDBAPI.c
drivers/net/npe/IxEthDBAPISupport.c
drivers/net/npe/IxEthDBCore.c
drivers/net/npe/IxEthDBEvents.c
drivers/net/npe/IxEthDBFeatures.c
drivers/net/npe/IxEthDBFirewall.c
drivers/net/npe/IxEthDBLearning.c
drivers/net/npe/IxEthDBNPEAdaptor.c
drivers/net/npe/IxEthDBPortUpdate.c
drivers/net/npe/IxEthDBReports.c
drivers/net/npe/IxEthDBSearch.c
drivers/net/npe/IxEthDBSpanningTree.c
drivers/net/npe/IxEthDBUtil.c
drivers/net/npe/IxEthDBVlan.c
drivers/net/npe/IxEthMii.c
drivers/net/npe/IxFeatureCtrl.c
drivers/net/npe/IxNpeDl.c
drivers/net/npe/IxNpeDlImageMgr.c
drivers/net/npe/IxNpeDlNpeMgr.c
drivers/net/npe/IxNpeMh.c
drivers/net/npe/IxNpeMhConfig.c
drivers/net/npe/IxNpeMhSend.c
drivers/net/npe/IxOsalOsSemaphore.c
drivers/net/npe/IxQMgrDispatcher.c
drivers/net/npe/IxQMgrInit.c
drivers/net/npe/IxQMgrQCfg.c
drivers/net/npe/npe.c
drivers/rtc/ds1374.c
drivers/serial/usbtty.c
drivers/video/da8xx-fb.c
drivers/video/mxc_ipuv3_fb.c
fs/ext4/ext4_journal.c
include/configs/bf537-stamp.h
include/dp83848.h
include/linux/fb.h
include/linux/mtd/nand.h
include/linux/types.h
include/MCD_dma.h
include/pcmcia/ti113x.h
include/radeon.h
include/sym53c8xx.h
include/usb_cdc_acm.h
include/usbdevice.h
README
tools/bddb/defs.php
-Allen
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Re: [U-Boot] [Patch v3] Consolidate bool type
On Thu, Jan 24, 2013 at 10:14:37AM -0800, Scott Wood wrote:
On 01/24/2013 12:03:49 PM, York Sun wrote:
On 01/24/2013 09:54 AM, York Sun wrote:
On 01/24/2013 09:34 AM, Allen Martin wrote:
On Wed, Jan 23, 2013 at 02:05:26PM -0800, York Sun wrote:
On 01/23/2013 02:02 PM, Scott Wood wrote:
On 01/23/2013 04:01:49 PM, York Sun wrote:
On 01/23/2013 01:52 PM, Scott Wood wrote:
On 01/23/2013 03:46:04 PM, York Sun wrote:
On 01/23/2013 01:41 PM, York Sun wrote:
I should put RFC in the subject as I am not able to compile
all ARCH
myself.
So how do you see this patch becoming non-RFC? I think most
people
don't have every single toolchain. You should at least get a
toolchain
for a couple major architectures such as ARM. Usually RFC is
for when
you know the patch has issues, and don't want it applied yet
even if
nobody else finds fault with it.
I know this version has problem. I am hoping more people get
involved
and test what they can. I tried the arm toolchain you pointed
to me. I
couldn't run MAKEALL for arm.
Even before your patch, using USE_PRIVATE_LIBGCC? How many
boards failed?
I don't know. Wolfgang brought it. Allen kindly offered help to
verify
on tegra which uses USE_PRIVATE_LIBGCC.
Built and tested on tegra, no problems. I'm still seeing a lot of
references to TRUE/FALSE even after this patch though:
$ git grep -e FALSE -e TRUE | awk 'BEGIN {FS = :} {print $1}' |
sort | uniq
Thanks, Allen. A long way to go.
I thought I have replaced all #define, enum, typedef. I have left
alone
those FALSE, False, false but add define like this
+#include stdbool.h
+#define TRUE true
+#define FALSE false
+#define True true
+#define False false
Isn't that enough?
It's enough to make it build, but it would be better to fix the users.
For code consistency I think it would be better to force everything to
use the lower case true/false. Otherwise this patch does nothing to
force new code to use the standardized version.
There may be some exception we want to make for unmodified 3rd party
libraries that are checked in, like lib/bzlib which uses True/False,
otherwise it makes it hard to take new code drops of those things.
-Allen
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Re: [U-Boot] [Patch v3] Consolidate bool type
On Thu, Jan 24, 2013 at 10:23:21AM -0800, York Sun wrote: On 01/24/2013 10:14 AM, Scott Wood wrote: I thought I have replaced all #define, enum, typedef. I have left alone those FALSE, False, false but add define like this +#include stdbool.h +#define TRUE true +#define FALSE false +#define True true +#define False false Isn't that enough? It's enough to make it build, but it would be better to fix the users. Let me try to run a script to replace all of them to false and true. York Try this: $ find . -type f -name \*.h -print | xargs perl -pi -e 's/(\b)FALSE(\b)/$1false$2/g' $ find . -type f -name \*.h -print | xargs perl -pi -e 's/(\b)TRUE(\b)/$1true$2/g' $ find . -type f -name \*.c -print | xargs perl -pi -e 's/(\b)FALSE(\b)/$1false$2/g' $ find . -type f -name \*.c -print | xargs perl -pi -e 's/(\b)TRUE(\b)/$1true$2/g' $ find . -type f -name \*.h -print | xargs perl -pi -e 's/(\b)False(\b)/$1false$2/g' $ find . -type f -name \*.h -print | xargs perl -pi -e 's/(\b)True(\b)/$1true$2/g' $ find . -type f -name \*.c -print | xargs perl -pi -e 's/(\b)False(\b)/$1false$2/g' $ find . -type f -name \*.c -print | xargs perl -pi -e 's/(\b)True(\b)/$1true$2/g' -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MAKEALL: add support for per architecture toolchains
Add support for per architecture CROSS_COMPILE toolchain definitions
via CROSS_COMPILE_ARCH where ARCH is any of the supported u-boot
architectures. This allows building every supported u-boot board in a
single pass of MAKEALL.
Signed-off-by: Allen Martin amar...@nvidia.com
---
MAKEALL | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 5b06c54..18b4e4d 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -35,6 +35,9 @@ usage()
Environment variables:
BUILD_NCPUS number of parallel make jobs (default: auto)
CROSS_COMPILEcross-compiler toolchain prefix (default: )
+ CROSS_COMPILE_ARM cross-compiler toolchain prefix for
+ architecture ARM. Substitute ARM for any
+ supported architecture (default: )
MAKEALL_LOGDIR output all logs to here (default: ./LOG/)
BUILD_DIRoutput build directory (default: ./)
BUILD_NBUILDSnumber of parallel targets (default: 1)
@@ -180,13 +183,6 @@ else
JOBS=
fi
-
-if [ ${CROSS_COMPILE} ] ; then
- MAKE=make CROSS_COMPILE=${CROSS_COMPILE}
-else
- MAKE=make
-fi
-
if [ ${MAKEALL_LOGDIR} ] ; then
LOG_DIR=${MAKEALL_LOGDIR}
else
@@ -585,6 +581,18 @@ get_target_maintainers() {
echo $mail
}
+get_target_arch() {
+ local target=$1
+
+ # Automatic mode
+ local line=`egrep -i ^[[:space:]]*${target}[[:space:]] boards.cfg`
+
+ if [ -z ${line} ] ; then echo ; return ; fi
+
+ set ${line}
+ echo $2
+}
+
list_target() {
if [ $PRINT_MAINTS != 'y' ] ; then
echo $1
@@ -655,6 +663,16 @@ build_target() {
export BUILD_DIR=${output_dir}
+ target_arch=$(get_target_arch ${target})
+ eval cross_toolchain=\$CROSS_COMPILE_${target_arch^^}
+ if [ ${cross_toolchain} ] ; then
+ MAKE=make CROSS_COMPILE=${cross_toolchain}
+ elif [ ${CROSS_COMPILE} ] ; then
+ MAKE=make CROSS_COMPILE=${CROSS_COMPILE}
+ else
+ MAKE=make
+ fi
+
${MAKE} distclean /dev/null
${MAKE} -s ${target}_config
--
1.7.10.4
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Re: [U-Boot] [RFC Patch v5] Consolidate bool type
On Thu, Jan 24, 2013 at 11:13:27AM -0800, York Sun wrote: On 01/24/2013 11:09 AM, Scott Wood wrote: On 01/24/2013 12:47:10 PM, York Sun wrote: diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py index d831087..28b3240 100644 --- a/tools/patman/checkpatch.py +++ b/tools/patman/checkpatch.py @@ -48,12 +48,12 @@ def FindCheckPatch(): print 'Could not find checkpatch.pl' return None -def CheckPatch(fname, verbose=False): +def CheckPatch(fname, verbose=false): Run checkpatch.pl on a file. Returns: 4-tuple containing: -result: False=failure, True=ok +result: false=failure, true=ok problems: List of problems, each a dict: 'type'; error or warning 'msg': text message You should probably limit the change to C code. :-) Nice catch. I forgot Python use True and False. Will fix. Omit tools/bddb/defs.php as well. I'm still not clear what the policy should be regarding 3rd party libraries that are checked into u-boot, but my opinion is they should stay as close to the original source as much as possible, so we should exclude them from this cleanup: lib/bzlib.c| 76 +- lib/bzlib_decompress.c | 20 +-- lib/bzlib_huffman.c|8 +- lib/bzlib_private.h|3 - lib/lzma/LzmaDec.c |2 +- lib/lzma/Types.h |3 - -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] tegra: fdt: sort dts files
Sort nodes in dts files according the the following rules:
1) Any nodes that already exist in any /include/d file, in the order
they appear in the /include/d file.
2) Any nodes with a reg property, in order of their address.
3) Any nodes without a reg property, alphabetically by node name.
Signed-off-by: Allen Martin amar...@nvidia.com
Signed-off-by: Tom Warren twar...@nvidia.com
---
v2: Added back host1x node that got dropped from seaboard by mistake.
As an added precaution I verified each file touched by this patch by
running it through sort before and after the patch and confirmed they
are identical minus blank lines that were fixed up.
v1: split this out from SPI driver series
---
arch/arm/dts/tegra20.dtsi| 377 +++---
board/avionic-design/dts/tegra20-tec.dts | 22 +-
board/compal/dts/tegra20-paz00.dts | 22 +-
board/nvidia/dts/tegra20-harmony.dts | 20 +-
board/nvidia/dts/tegra20-seaboard.dts| 119 +-
5 files changed, 279 insertions(+), 281 deletions(-)
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index cc086b1..46e3785 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -4,10 +4,102 @@
compatible = nvidia,tegra20;
interrupt-parent = intc;
- tegra_car: clock@60006000 {
- compatible = nvidia,tegra20-car;
- reg = 0x60006000 0x1000;
- #clock-cells = 1;
+ host1x {
+ compatible = nvidia,tegra20-host1x, simple-bus;
+ reg = 0x5000 0x00024000;
+ interrupts = 0 65 0x04 /* mpcore syncpt */
+ 0 67 0x04; /* mpcore general */
+ status = disabled;
+
+ #address-cells = 1;
+ #size-cells = 1;
+
+ ranges = 0x5400 0x5400 0x0400;
+
+ /* video-encoding/decoding */
+ mpe {
+ reg = 0x5404 0x0004;
+ interrupts = 0 68 0x04;
+ status = disabled;
+ };
+
+ /* video input */
+ vi {
+ reg = 0x5408 0x0004;
+ interrupts = 0 69 0x04;
+ status = disabled;
+ };
+
+ /* EPP */
+ epp {
+ reg = 0x540c 0x0004;
+ interrupts = 0 70 0x04;
+ status = disabled;
+ };
+
+ /* ISP */
+ isp {
+ reg = 0x5410 0x0004;
+ interrupts = 0 71 0x04;
+ status = disabled;
+ };
+
+ /* 2D engine */
+ gr2d {
+ reg = 0x5414 0x0004;
+ interrupts = 0 72 0x04;
+ status = disabled;
+ };
+
+ /* 3D engine */
+ gr3d {
+ reg = 0x5418 0x0004;
+ status = disabled;
+ };
+
+ /* display controllers */
+ dc@5420 {
+ compatible = nvidia,tegra20-dc;
+ reg = 0x5420 0x0004;
+ interrupts = 0 73 0x04;
+ status = disabled;
+
+ rgb {
+ status = disabled;
+ };
+ };
+
+ dc@5424 {
+ compatible = nvidia,tegra20-dc;
+ reg = 0x5424 0x0004;
+ interrupts = 0 74 0x04;
+ status = disabled;
+
+ rgb {
+ status = disabled;
+ };
+ };
+
+ /* outputs */
+ hdmi {
+ compatible = nvidia,tegra20-hdmi;
+ reg = 0x5428 0x0004;
+ interrupts = 0 75 0x04;
+ status = disabled;
+ };
+
+ tvo {
+ compatible = nvidia,tegra20-tvo;
+ reg = 0x542c 0x0004;
+ interrupts = 0 76 0x04;
+ status = disabled;
+ };
+
+ dsi {
+ compatible = nvidia,tegra20-dsi;
+ reg = 0x5430 0x0004;
+ status = disabled;
+ };
};
intc: interrupt-controller@50041000 {
@@ -18,44 +110,33 @@
0x50040100 0x0100 ;
};
- i2c@7000c000 {
- #address-cells = 1;
- #size-cells = 0;
- compatible = nvidia,tegra20-i2c;
- reg = 0x7000C000 0x100;
- interrupts = 70
Re: [U-Boot] [RFC Patch v6] Consolidate bool type
On Thu, Jan 24, 2013 at 03:12:17PM -0800, York Sun wrote: 'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun york...@freescale.com --- Change since v1: Move 'false' and 'true' to the common header file. Change since v2: Use stdbool.h Consolidate all TRUE, FALSE, True, False, true, false Change since v3: Fix boolean_t which was missed in v2. Change since v4: Replace FALSE, False with false. Replace TRUE, True with true. Change since v5: Revert changes for *.py, *.php, lib/* files. Revert change to type conversions. Revert comment-only changes. (Not sure about if we should replace the comments). Fix many coding style issues but left drivers/net/npe alone (way too many issues). This patch doesn't address the white space issue where TRUE/FALSE is repalced. Need help to test on all ARCHs with differnt toolchains as well as USE_PRIVATE_LIBGCC. I think you can drop the RFC from your patch at this point. Built on all tegra20 and tegra30 devices with USE_PRIVATE_LIBGCC. Tested on seaboard (tegra20). I've also submitted your patch to my build regression script which will build all 1100+ boards against your patch and tell if there are any build regressions. I'll let you know the results tomorrow. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] sandbox: fix compiler warning
On Tue, Jan 22, 2013 at 10:46:03PM -0800, Albert ARIBAUD wrote:
Hi Allen,
On Tue, 22 Jan 2013 15:11:21 -0800, Allen Martin amar...@nvidia.com
wrote:
Add back return statement to fix compiler warning about control flow
reaching end of non void function that was introduced with:
e05e5de arm: move C runtime setup code in crt0.S
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Simon Glass s...@chromium.org
---
arch/sandbox/cpu/start.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 7603bf9..5287fd5 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -122,4 +122,7 @@ int main(int argc, char *argv[])
* never return.
*/
board_init_f(0);
+
+ /* NOTREACHED - board_init_f() does not return */
+ return 0;
}
Shouldn't the function be given '__attribute__((noreturn))' rather than
adding a non-executed 'return 0' to it?
The function in question is sandbox main(), and it can return if there
was an error prior to calling board_init_f(). Here's the whole
function for context:
int main(int argc, char *argv[])
{
struct sandbox_state *state;
int err;
err = state_init();
if (err)
return err;
state = state_get_current();
if (os_parse_args(state, argc, argv))
return 1;
/*
* Do pre- and post-relocation init, then start up
U-Boot. This will
* never return.
*/
board_init_f(0);
/* NOTREACHED - board_init_f() does not return */
return 0;
}
-Allen
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Re: [U-Boot] [Patch v3] Consolidate bool type
On Wed, Jan 23, 2013 at 02:05:26PM -0800, York Sun wrote: On 01/23/2013 02:02 PM, Scott Wood wrote: On 01/23/2013 04:01:49 PM, York Sun wrote: On 01/23/2013 01:52 PM, Scott Wood wrote: On 01/23/2013 03:46:04 PM, York Sun wrote: On 01/23/2013 01:41 PM, York Sun wrote: I should put RFC in the subject as I am not able to compile all ARCH myself. So how do you see this patch becoming non-RFC? I think most people don't have every single toolchain. You should at least get a toolchain for a couple major architectures such as ARM. Usually RFC is for when you know the patch has issues, and don't want it applied yet even if nobody else finds fault with it. I know this version has problem. I am hoping more people get involved and test what they can. I tried the arm toolchain you pointed to me. I couldn't run MAKEALL for arm. Even before your patch, using USE_PRIVATE_LIBGCC? How many boards failed? I don't know. Wolfgang brought it. Allen kindly offered help to verify on tegra which uses USE_PRIVATE_LIBGCC. I actually have a script to build all 1000+ boards in every architecture, but I think a few of my toolchains are broken (openrisc and blackfin come to mind). I've been thinking about incorporating that functionality into MAKEALL as a set of patches. In the meantime I can build and test on tegra, which as York says uses USE_PRIVATE_LIBGCC. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sandbox: fix compiler warning
Fix compiler warning about control flow reaching end of non void function. Signed-off-by: Allen Martin amar...@nvidia.com --- arch/sandbox/cpu/start.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 7603bf9..5287fd5 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -122,4 +122,7 @@ int main(int argc, char *argv[]) * never return. */ board_init_f(0); + + /* NOTREACHED - board_init_f() does not return */ + return 0; } -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sandbox: fix compiler warning
On Tue, Jan 22, 2013 at 01:56:23PM -0800, Simon Glass wrote: On Tue, Jan 22, 2013 at 1:42 PM, Allen Martin amar...@nvidia.com wrote: Fix compiler warning about control flow reaching end of non void function. Signed-off-by: Allen Martin amar...@nvidia.com Should perhaps mention the commit that adding this warning (e05e5de7 I think) Acked-by: Simon Glass s...@chromium.org It was this commit: commit fec79acc864bed049b6beae719ccbf2bbec5403a Author: Mike Frysinger vap...@gentoo.org Date: Wed Oct 26 00:22:14 2011 + sandbox: drop unused return Signed-off-by: Mike Frysinger vap...@gentoo.org Acked-by: Simon Glass s...@chromium.org I'll change the commit messagen and repost and cc Mike as well. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] sandbox: fix compiler warning
Add back return statement to fix compiler warning about control flow reaching end of non void function that was introduced with: fec79ac sandbox: drop unused return Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Simon Glass s...@chromium.org --- arch/sandbox/cpu/start.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 7603bf9..5287fd5 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -122,4 +122,7 @@ int main(int argc, char *argv[]) * never return. */ board_init_f(0); + + /* NOTREACHED - board_init_f() does not return */ + return 0; } -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sandbox: fix compiler warning
On Tue, Jan 22, 2013 at 02:58:58PM -0800, Simon Glass wrote: Hi Allen, On Tue, Jan 22, 2013 at 2:48 PM, Allen Martin amar...@nvidia.com wrote: On Tue, Jan 22, 2013 at 01:56:23PM -0800, Simon Glass wrote: On Tue, Jan 22, 2013 at 1:42 PM, Allen Martin amar...@nvidia.com wrote: Fix compiler warning about control flow reaching end of non void function. Signed-off-by: Allen Martin amar...@nvidia.com Should perhaps mention the commit that adding this warning (e05e5de7 I think) Acked-by: Simon Glass s...@chromium.org It was this commit: commit fec79acc864bed049b6beae719ccbf2bbec5403a Author: Mike Frysinger vap...@gentoo.org Date: Wed Oct 26 00:22:14 2011 + sandbox: drop unused return Signed-off-by: Mike Frysinger vap...@gentoo.org Acked-by: Simon Glass s...@chromium.org I'll change the commit messagen and repost and cc Mike as well. Actually I think that Mike's commit was correct at the time, and it was Albert's which changed the no-return behaviour of the function signature in common.h? Oh I see, you're right. I'll resend. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] sandbox: fix compiler warning
Add back return statement to fix compiler warning about control flow reaching end of non void function that was introduced with: e05e5de arm: move C runtime setup code in crt0.S Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Simon Glass s...@chromium.org --- arch/sandbox/cpu/start.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 7603bf9..5287fd5 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -122,4 +122,7 @@ int main(int argc, char *argv[]) * never return. */ board_init_f(0); + + /* NOTREACHED - board_init_f() does not return */ + return 0; } -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BIT
On Tue, Jan 22, 2013 at 02:27:30PM -0800, Lucas Stach wrote: Am Dienstag, den 22.01.2013, 09:24 -0700 schrieb Stephen Warren: On 01/21/2013 05:20 PM, Lucas Stach wrote: Even the 8bit case needs KBCB configured, as pin D7 is located in this pingroup. Also pingroup ATC seems to come out of reset with config set to NAND, so we need to explictly configure some other function to this group in order to avoid clashing settings. diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c @@ -266,17 +266,25 @@ int funcmux_select(enum periph_id id, int config) break; case FUNCMUX_NDFLASH_KBC_8_BIT: ... + /* + * configure pingroup ATC to something unrelated to + * avoid ATC overriding KBC + */ + pinmux_set_func(PINGRP_ATC, PMUX_FUNC_GMI); + This gets a bit dangerous; what if pingroup ATC was already configured for some function other than NAND or GMI? This code will then break that setting. I would suggest one of the following alternatives: 1) Use the new pinmux_avoid_func() function implemented in the patch that I just sent. 2) Move Tegra20 over to the new board-wide pinmux style that Tegra30 uses, where the entire pinmux is initialized in one shot. This will completely avoid any kind of uninitialized pinmux settings, and to some extent is the only sensible thing to do on a device like Tegra which has the potential for conflicts like this patch tries to avoid. I'll take a look on how much work it is to implement option #2. If it isn't too much and I find some time in this U-Boot release cycle, I'm very much inclined to do this the ultimately right way. I think #2 really is the only way to do it. The reset state is full of conflicts and unless everything is initialized at once you end up chasing your tail where you fix conflict A, but that leads to new conflict B, and fixing that leads to C, etc. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v2] Introduce a global bool type
On Mon, Jan 07, 2013 at 03:55:48PM -0800, York Sun wrote: 'bool' is defined in random places. This patch consolidates them into a single typedef, using _Bool introduced in C99. Signed-off-by: York Sun york...@freescale.com --- Change since v1: Move 'false' and 'true' to the common header file. Need help from other arch maintainers to test it. I could only test powerpc. Thank you for taking this on, it's definately in need of cleanup. There are also many duplicate definitions of the upper case variants (BOOL/TRUE/FALSE). Those should get fixed too. +typedef _Bool bool; +#define false 0 +#define true 1 + Linux defines true/false as an enum type in stddef.h, since u-boot already has a copy of this Linux header, shouldn't it go in there? -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v2] Introduce a global bool type
On Mon, Jan 07, 2013 at 10:29:28PM -0800, Wolfgang Denk wrote: Dear York Sun, In message 1357602948-16848-1-git-send-email-york...@freescale.com you wrote: 'bool' is defined in random places. This patch consolidates them into a single typedef, using _Bool introduced in C99. Signed-off-by: York Sun york...@freescale.com --- Change since v1: Move 'false' and 'true' to the common header file. Please see Måns Rullgård's comment about using stdbool.h instead. Isn't stdbool.h more for backward compatability for user space programs, so only newer C99 aware programs can opt-in to the new data type? Linux for example doesn't use stdbool.h, it puts the definition of bool in types.h, and true/false in stddef.h. Since, like Linux, u-boot is a single codebase, all the data types can go in a common place and not have to worry about breaking old programs with new types. Then please make sure that a sufficient number of tool chains as well as configurations using USE_PRIVATE_LIBGCC continue to work, i. e. in a first step verify that these are still compile-clean. If you cc me on newer versions of the patch I can help verify on tegra, which uses USE_PRIVATE_LIBGCC. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/7] tegra30: add SBC1 to periph id mapping table
SBC1 is SPI controller 1 on tegra30
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Simon Glass s...@chromium.org
---
arch/arm/cpu/tegra30-common/clock.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/tegra30-common/clock.c
b/arch/arm/cpu/tegra30-common/clock.c
index c67a2e1..db5ac1e 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -318,7 +318,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
/* 40 */
NONE(KFUSE),
- NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
+ PERIPHC_SBC1,
PERIPHC_NOR,
NONE(RESERVED43),
PERIPHC_SBC2,
--
1.7.10.4
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[U-Boot] [PATCH v3 4/7] tegra30: fdt: add SPI SLINK nodes
Add tegra30 SPI SLINK nodes to fdt.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Simon Glass s...@chromium.org
---
arch/arm/dts/tegra30.dtsi | 72 +++
board/nvidia/dts/tegra30-cardhu.dts |4 ++
2 files changed, 76 insertions(+)
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index aa7e7ae..7b8126f 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -90,4 +90,76 @@
/* PERIPH_ID_I2C_DVC, CLK_M */
clocks = tegra_car 47;
};
+
+ spi@7000d400 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000d400 0x200;
+ interrupts = 0 59 0x04;
+ nvidia,dma-request-selector = apbdma 15;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC1, PLLP_OUT0 */
+ clocks = tegra_car 41;
+ };
+
+ spi@7000d600 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000d600 0x200;
+ interrupts = 0 82 0x04;
+ nvidia,dma-request-selector = apbdma 16;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC2, PLLP_OUT0 */
+ clocks = tegra_car 44;
+ };
+
+ spi@7000d800 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000d480 0x200;
+ interrupts = 0 83 0x04;
+ nvidia,dma-request-selector = apbdma 17;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC3, PLLP_OUT0 */
+ clocks = tegra_car 46;
+ };
+
+ spi@7000da00 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000da00 0x200;
+ interrupts = 0 93 0x04;
+ nvidia,dma-request-selector = apbdma 18;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC4, PLLP_OUT0 */
+ clocks = tegra_car 68;
+ };
+
+ spi@7000dc00 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000dc00 0x200;
+ interrupts = 0 94 0x04;
+ nvidia,dma-request-selector = apbdma 27;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC5, PLLP_OUT0 */
+ clocks = tegra_car 104;
+ };
+
+ spi@7000de00 {
+ compatible = nvidia,tegra30-slink, nvidia,tegra20-slink;
+ reg = 0x7000de00 0x200;
+ interrupts = 0 79 0x04;
+ nvidia,dma-request-selector = apbdma 28;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SBC6, PLLP_OUT0 */
+ clocks = tegra_car 105;
+ };
};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts
b/board/nvidia/dts/tegra30-cardhu.dts
index 3223ed4..79a7c4f 100644
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -39,4 +39,8 @@
i2c@7000d000 {
clock-frequency = 10;
};
+
+ spi@7000da00 {
+ spi-max-frequency = 2500;
+ };
};
--
1.7.10.4
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[U-Boot] [PATCH v3 0/7] tegra: SPI drivers
This series updates the tegra20 SPI driver to add fdt support and adds a new tegra30 SPI driver. Testing was done on trimslice (tegra20) and cardhu (tegra30). Changes in v3: -Dropped some fdt patches from the series that were picked up in u-boot-tegra/next already -Removed SPI node from seaboard, added to trimslice -Incorporated feedback from Simon Glass and Stephen Warren to slink driver Changes in v2: -Added new patch to sort dts files prior to adding new nodes -Moved max-spi-frequency out to board dts files -Moved tegra20 SFLASH fdt changes out to separate patch -Added valid flag to slink driver controller structure Allen Martin (7): tegra20: fdt: add SPI SFLASH node tegra: spi: add fdt support to tegra SPI SFLASH driver tegra30: add SBC1 to periph id mapping table tegra30: fdt: add SPI SLINK nodes tegra: add addresses of SPI SLINK controllers tegra: add SPI SLINK driver tegra: cardhu: config: enable SPI arch/arm/cpu/tegra30-common/clock.c |2 +- arch/arm/dts/tegra20.dtsi | 12 + arch/arm/dts/tegra30.dtsi | 72 ++ arch/arm/include/asm/arch-tegra/tegra.h |6 + arch/arm/include/asm/arch-tegra/tegra_slink.h | 84 +++ board/compulab/dts/tegra20-trimslice.dts |4 + board/nvidia/common/board.c |3 +- board/nvidia/dts/tegra30-cardhu.dts |4 + drivers/spi/Makefile |1 + drivers/spi/tegra_slink.c | 332 + drivers/spi/tegra_spi.c | 42 +++- include/configs/cardhu.h | 11 + include/fdtdec.h |2 + lib/fdtdec.c |2 + 14 files changed, 574 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h create mode 100644 drivers/spi/tegra_slink.c -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/7] tegra20: fdt: add SPI SFLASH node
Add node for tegra20 SPI SFLASH controller to fdt.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/dts/tegra20.dtsi| 12
board/compulab/dts/tegra20-trimslice.dts |4
2 files changed, 16 insertions(+)
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 12049fd..9a89685 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -236,6 +236,18 @@
clocks = tegra_car 12, tegra_car 124;
};
+ spi@7000c380 {
+ compatible = nvidia,tegra20-sflash;
+ reg = 0x7000c380 0x80;
+ interrupts = 0 39 0x04;
+ nvidia,dma-request-selector = apbdma 11;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ /* PERIPH_ID_SPI1, PLLP_OUT0 */
+ clocks = tegra_car 43;
+ };
+
i2c@7000c400 {
#address-cells = 1;
#size-cells = 0;
diff --git a/board/compulab/dts/tegra20-trimslice.dts
b/board/compulab/dts/tegra20-trimslice.dts
index c8a4dd4..eb66be5 100644
--- a/board/compulab/dts/tegra20-trimslice.dts
+++ b/board/compulab/dts/tegra20-trimslice.dts
@@ -23,6 +23,10 @@
status = disabled;
};
+ spi@7000c380 {
+ spi-max-frequency = 2500;
+ };
+
i2c@7000c400 {
status = disabled;
};
--
1.7.10.4
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[U-Boot] [PATCH v3 7/7] tegra: cardhu: config: enable SPI
Turn on SPI in cardhu config file Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Simon Glass s...@chromium.org --- include/configs/cardhu.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index aa725ba..1616b39 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -49,6 +49,17 @@ #define CONFIG_ENV_IS_NOWHERE +/* SPI */ +#define CONFIG_TEGRA_SLINK +#define CONFIG_TEGRA_SLINK_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED2400 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 20) + #include tegra-common-post.h #endif /* __CONFIG_H */ -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 2/7] tegra: spi: add fdt support to tegra SPI SFLASH driver
Add support for configuring tegra SPI driver from devicetree.
Support is keyed off CONFIG_OF_CONTROL. Add entry in seaboard dts
file for spi controller to describe seaboard spi.
Signed-off-by: Allen Martin amar...@nvidia.com
---
drivers/spi/tegra_spi.c | 42 +-
include/fdtdec.h|1 +
lib/fdtdec.c|1 +
3 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c
index 9bb34e2..36b0cd0 100644
--- a/drivers/spi/tegra_spi.c
+++ b/drivers/spi/tegra_spi.c
@@ -32,6 +32,11 @@
#include asm/arch-tegra/clk_rst.h
#include asm/arch-tegra/tegra_spi.h
#include spi.h
+#ifdef CONFIG_OF_CONTROL
+#include fdtdec.h
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPI_CORRUPTS_UART)
#define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
@@ -44,6 +49,7 @@ struct tegra_spi_slave {
struct spi_tegra *regs;
unsigned int freq;
unsigned int mode;
+ int periph_id;
};
static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
@@ -85,7 +91,41 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
spi-slave.bus = bus;
spi-slave.cs = cs;
spi-freq = max_hz;
+#ifdef CONFIG_OF_CONTROL
+ int node = fdtdec_next_compatible(gd-fdt_blob, 0,
+ COMPAT_NVIDIA_TEGRA20_SFLASH);
+ if (node 0) {
+ debug(%s: cannot locate sflash node\n, __func__);
+ return NULL;
+ }
+ spi-regs = (struct spi_tegra *)fdtdec_get_addr(gd-fdt_blob,
+ node, reg);
+ if ((fdt_addr_t)spi-regs == FDT_ADDR_T_NONE) {
+ debug(%s: no sflash register found\n, __func__);
+ return NULL;
+ }
+ spi-freq = fdtdec_get_int(gd-fdt_blob, node, spi-max-frequency, 0);
+ if (!spi-freq) {
+ debug(%s: no sflash max frequency found\n, __func__);
+ return NULL;
+ }
+ spi-periph_id = clock_decode_periph_id(gd-fdt_blob, node);
+ if (spi-periph_id == PERIPH_ID_NONE) {
+ debug(%s: could not decode periph id\n, __func__);
+ return NULL;
+ }
+#else
spi-regs = (struct spi_tegra *)NV_PA_SPI_BASE;
+ spi-freq = TEGRA_SPI_MAX_FREQ;
+ spi-periph_id = PERIPH_ID_SPI1;
+#endif
+ if (max_hz spi-freq) {
+ debug(%s: limiting frequency from %u to %u\n, __func__,
+ spi-freq, max_hz);
+ spi-freq = max_hz;
+ }
+ debug(%s: controller initialized at %p, freq = %u, periph_id = %d\n,
+ __func__, spi-regs, spi-freq, spi-periph_id);
spi-mode = mode;
return spi-slave;
@@ -110,7 +150,7 @@ int spi_claim_bus(struct spi_slave *slave)
u32 reg;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi-freq);
+ clock_start_periph_pll(spi-periph_id, CLOCK_ID_PERIPH, spi-freq);
/* Clear stale status here */
reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
diff --git a/include/fdtdec.h b/include/fdtdec.h
index f77d195..5b67a77 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -70,6 +70,7 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
+ COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */
COMPAT_SMSC_LAN9215,/* SMSC 10/100 Ethernet LAN9215 */
COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 16921e1..385e0e5 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -45,6 +45,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA20_NAND, nvidia,tegra20-nand),
COMPAT(NVIDIA_TEGRA20_PWM, nvidia,tegra20-pwm),
COMPAT(NVIDIA_TEGRA20_DC, nvidia,tegra20-dc),
+ COMPAT(NVIDIA_TEGRA20_SFLASH, nvidia,tegra20-sflash),
COMPAT(SMSC_LAN9215, smsc,lan9215),
COMPAT(SAMSUNG_EXYNOS5_SROMC, samsung,exynos-sromc),
COMPAT(SAMSUNG_S3C2440_I2C, samsung,s3c2440-i2c),
--
1.7.10.4
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[U-Boot] [PATCH v3 5/7] tegra: add addresses of SPI SLINK controllers
Add I/O addresses of SPI SLINK controllers 1-6 Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Simon Glass s...@chromium.org --- arch/arm/include/asm/arch-tegra/tegra.h |6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 953936c..5606b63 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -40,6 +40,12 @@ #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) #define NV_PA_NAND_BASE(NV_PA_APB_MISC_BASE + 0x8000) #define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) +#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400) +#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600) +#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800) +#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00) +#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) +#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) #define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) #define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 6/7] tegra: add SPI SLINK driver
Add driver for tegra SPI SLINK style driver. This controller is
similar to the tegra20 SPI SFLASH controller. The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices. In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH. Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.
This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.
To enable this driver, use CONFIG_TEGRA_SLINK
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/tegra_slink.h | 84 +++
board/nvidia/common/board.c |3 +-
drivers/spi/Makefile |1 +
drivers/spi/tegra_slink.c | 332 +
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
6 files changed, 421 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-tegra/tegra_slink.h
create mode 100644 drivers/spi/tegra_slink.c
diff --git a/arch/arm/include/asm/arch-tegra/tegra_slink.h
b/arch/arm/include/asm/arch-tegra/tegra_slink.h
new file mode 100644
index 000..74804b5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/tegra_slink.h
@@ -0,0 +1,84 @@
+/*
+ * NVIDIA Tegra SPI-SLINK controller
+ *
+ * Copyright 2010-2013 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_SLINK_H_
+#define _TEGRA_SLINK_H_
+
+#include asm/types.h
+
+struct slink_tegra {
+ u32 command;/* SLINK_COMMAND_0 register */
+ u32 command2; /* SLINK_COMMAND2_0 reg */
+ u32 status; /* SLINK_STATUS_0 register */
+ u32 reserved; /* Reserved offset 0C */
+ u32 mas_data; /* SLINK_MAS_DATA_0 reg */
+ u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
+ u32 dma_ctl;/* SLINK_DMA_CTL_0 register */
+ u32 status2;/* SLINK_STATUS2_0 reg */
+ u32 rsvd[56]; /* 0x20 to 0xFF reserved */
+ u32 tx_fifo;/* SLINK_TX_FIFO_0 reg off 100h */
+ u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
+ u32 rx_fifo;/* SLINK_RX_FIFO_0 reg off 180h */
+};
+
+/* COMMAND */
+#define SLINK_CMD_ENB (1 31)
+#define SLINK_CMD_GO (1 30)
+#define SLINK_CMD_M_S (1 28)
+#define SLINK_CMD_CK_SDA (1 21)
+#define SLINK_CMD_CS_POL (1 13)
+#define SLINK_CMD_CS_VAL (1 12)
+#define SLINK_CMD_CS_SOFT (1 11)
+#define SLINK_CMD_BIT_LENGTH (1 4)
+#define SLINK_CMD_BIT_LENGTH_MASK 0x001F
+/* COMMAND2 */
+#define SLINK_CMD2_TXEN(1 30)
+#define SLINK_CMD2_RXEN(1 31)
+#define SLINK_CMD2_SS_EN (1 18)
+#define SLINK_CMD2_SS_EN_SHIFT 18
+#define SLINK_CMD2_SS_EN_MASK 0x000C
+#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 17)
+/* STATUS */
+#define SLINK_STAT_BSY (1 31)
+#define SLINK_STAT_RDY (1 30)
+#define SLINK_STAT_ERR (1 29)
+#define SLINK_STAT_RXF_FLUSH (1 27)
+#define SLINK_STAT_TXF_FLUSH (1 26)
+#define SLINK_STAT_RXF_OVF (1 25)
+#define SLINK_STAT_TXF_UNR (1 24)
+#define SLINK_STAT_RXF_EMPTY (1 23)
+#define SLINK_STAT_RXF_FULL(1 22)
+#define SLINK_STAT_TXF_EMPTY (1 21)
+#define SLINK_STAT_TXF_FULL(1 20)
+#define SLINK_STAT_TXF_OVF (1 19)
+#define SLINK_STAT_RXF_UNR (1 18)
+#define SLINK_STAT_CUR_BLKCNT (1 15)
+/* STATUS2 */
+#define SLINK_STAT2_RXF_FULL_CNT (1 16)
+#define SLINK_STAT2_TXF_FULL_CNT (1 0)
+
+#define SPI_TIMEOUT1000
+#define TEGRA_SPI_MAX_FREQ 5200
+
+#endif /* _TEGRA_SLINK_H_ */
diff
Re: [U-Boot] [PATCH 1/7] Tegra114: Add arch-tegra114 include files
On Wed, Jan 16, 2013 at 01:14:02PM -0800, Tom Warren wrote:
Common Tegra files are in arch-tegra, shared between T20/T30/T114.
Tegra114-specific headers are in arch-tegra114. Note that some of
these will be filled in as more T114 support is added (drivers,
WB/LP0 support, etc.).
Signed-off-by: Tom Warren twar...@nvidia.com
---
+#if defined(CONFIG_TEGRA20)
#define OSC_FREQ_SHIFT 30
#define OSC_FREQ_MASK (3U OSC_FREQ_SHIFT)
+#else /* Tegra30, Tegra114 */
+#define OSC_FREQ_SHIFT 28
+#define OSC_FREQ_MASK (0xF OSC_FREQ_SHIFT)
+#endif
Can this be a new define instead of a #ifdef? That makes it easier in
the future to make a single u-boot to boot on all tegras.
index 953936c..670745f 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -73,6 +73,7 @@ enum {
SKU_ID_AP25E= 0x1b,
SKU_ID_T25E = 0x1c,
SKU_ID_T30 = 0x81, /* Cardhu value */
+ SKU_ID_T114 = 0x00, /* Dalmore value */
};
Is that really the proper SKU id? Or is it just unprogrammed on the
early chips?
diff --git a/arch/arm/include/asm/arch-tegra114/clock.h
b/arch/arm/include/asm/arch-tegra114/clock.h
new file mode 100644
index 000..9e56f57
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/clock.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
2013, here and all new files
-Allen
--
nvpublic
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Re: [U-Boot] [PATCH 2/7] Tegra114: Add AVP (arm720t) files
On Wed, Jan 16, 2013 at 01:14:03PM -0800, Tom Warren wrote:
This provides SPL support for T114 boards - AVP early init, plus
CPU (A15) init/jump to main U-Boot.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/cpu/arm720t/tegra-common/cpu.c | 23 ++-
arch/arm/cpu/arm720t/tegra-common/cpu.h | 13 +-
arch/arm/cpu/arm720t/tegra114/Makefile | 42
arch/arm/cpu/arm720t/tegra114/config.mk | 19 ++
arch/arm/cpu/arm720t/tegra114/cpu.c | 328
+++
5 files changed, 411 insertions(+), 14 deletions(-)
create mode 100644 arch/arm/cpu/arm720t/tegra114/Makefile
create mode 100644 arch/arm/cpu/arm720t/tegra114/config.mk
create mode 100644 arch/arm/cpu/arm720t/tegra114/cpu.c
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c
b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 693d584..846163c 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -40,7 +40,7 @@ enum tegra_family_t get_family(void)
chip_id = reg 8;
chip_id = 0xff;
debug( tegra_get_family: chip_id = %x\n, chip_id);
- if (chip_id == 0x30)
+ if (chip_id = 0x30)
Should this be CHIPID_TEGRA30? And it would probably be better to do:
if (chipid == CHIPID_TEGRA30 || chipid == CHIPID_TEGRA114)
return TEGRA_FAMILY_T3x;
else if (chipid == CHIPID_TEGRA20)
return TEGRA_FAMILY_T2x;
else
fail;
That forces the person doing the support for the next tegra chip to
have to make a conscious decision about what to do here.
return TEGRA_FAMILY_T3x;
else
return TEGRA_FAMILY_T2x;
@@ -56,6 +56,7 @@ int get_num_cpus(void)
*/
struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT]
= {
/* T20: 1 GHz */
+ /* n, m, p, cpcon */
{{ 1000, 13, 0, 12},/* OSC 13M */
{ 625, 12, 0, 8}, /* OSC 19.2M */
{ 1000, 12, 0, 12},/* OSC 12M */
@@ -76,11 +77,11 @@ struct clk_pll_table
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ 700, 13, 0, 8},
},
- /* TEGRA_SOC2_SLOW: 312 MHz */
- {{ 312, 13, 0, 12}, /* OSC 13M */
-{ 260, 16, 0, 8}, /* OSC 19.2M */
-{ 312, 12, 0, 12}, /* OSC 12M */
-{ 312, 26, 0, 12}, /* OSC 26M */
Removing TEGRA_SOC2_SLOW should probably be a separate patch, since it
doesn't hae anything to do with t114.
+ /* T114: 1.4 GHz */
+ {{ 862, 8, 0, 8},
+{ 583, 8, 0, 4},
+{ 696, 12, 0, 8},
+{ 700, 13, 0, 8},
},
};
@@ -166,8 +167,8 @@ void init_pllx(void)
sel = tegra_pll_x_table[chip_type][osc];
pllx_set_rate(pll, sel-n, sel-m, sel-p, sel-cpcon);
- /* adjust PLLP_out1-4 on T30 */
- if (chip_type == TEGRA_SOC_T30) {
+ /* adjust PLLP_out1-4 on T30/T114 */
+ if (chip_type = TEGRA_SOC_T30) {
same comment here about = T30
debug( init_pllx: adjusting PLLP out freqs\n);
adjust_pllp_out_freqs();
}
@@ -203,7 +204,7 @@ void enable_cpu_clock(int enable)
*/
clk = readl(clkrst-crc_clk_cpu_cmplx);
clk |= 1 CPU1_CLK_STP_SHIFT;
-#if defined(CONFIG_TEGRA30)
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
Can this be runtime instead of #ifdef?
clk |= 1 CPU2_CLK_STP_SHIFT;
clk |= 1 CPU3_CLK_STP_SHIFT;
#endif
@@ -308,7 +309,7 @@ void clock_enable_coresight(int enable)
* Clock divider request for 204MHz would setup CSITE clock as
* 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz
*/
- if (tegra_get_chip_type() == TEGRA_SOC_T30)
+ if (tegra_get_chip_type() = TEGRA_SOC_T30)
same comment here about = T30
src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
else
src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
@@ -318,7 +319,7 @@ void clock_enable_coresight(int enable)
rst = CORESIGHT_UNLOCK;
writel(rst, CSITE_CPU_DBG0_LAR);
writel(rst, CSITE_CPU_DBG1_LAR);
-#if defined(CONFIG_TEGRA30)
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
same comment here about runtime vs ifdef
writel(rst, CSITE_CPU_DBG2_LAR);
writel(rst, CSITE_CPU_DBG3_LAR);
#endif
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h
b/arch/arm/cpu/arm720t/tegra-common/cpu.h
index 3e2ea3a..45b346d 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h
@@ -22,14 +22,21 @@
*/
#include asm/types.h
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
u-boot seems a little inconsistent here, but it looks like most of
u-boot uses C99 true and false
/* Stabilization delays, in usec */
[U-Boot] [PATCH v2] tegra: fdt: remove clocks nodes
These nodes are unused.
Signed-off-by: Allen Martin amar...@nvidia.com
---
v2: remove clock as well as clocks nodes
remove from non nvidia tegra boards as well
v1: original submission
---
arch/arm/dts/tegra20.dtsi| 10 --
arch/arm/dts/tegra30.dtsi| 10 --
board/avionic-design/dts/tegra20-medcom-wide.dts | 14 --
board/avionic-design/dts/tegra20-plutux.dts | 14 --
board/avionic-design/dts/tegra20-tec.dts | 14 --
board/compal/dts/tegra20-paz00.dts | 13 -
board/compulab/dts/tegra20-trimslice.dts | 13 -
board/nvidia/dts/tegra20-harmony.dts | 13 -
board/nvidia/dts/tegra20-seaboard.dts| 10 --
board/nvidia/dts/tegra20-ventana.dts | 13 -
board/nvidia/dts/tegra20-whistler.dts| 10 --
board/nvidia/dts/tegra30-cardhu.dts | 13 -
12 files changed, 147 deletions(-)
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 636ec2c..cc086b1 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -10,16 +10,6 @@
#clock-cells = 1;
};
- clocks {
- #address-cells = 1;
- #size-cells = 0;
-
- osc: clock {
- compatible = fixed-clock;
- #clock-cells = 0;
- };
- };
-
intc: interrupt-controller@50041000 {
compatible = nvidia,tegra20-gic;
interrupt-controller;
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index 664c397..09bdb36 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -9,16 +9,6 @@
#clock-cells = 1;
};
- clocks {
- #address-cells = 1;
- #size-cells = 0;
-
- osc: clock {
- compatible = fixed-clock;
- #clock-cells = 0;
- };
- };
-
i2c@7000c000 {
#address-cells = 1;
#size-cells = 0;
diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts
b/board/avionic-design/dts/tegra20-medcom-wide.dts
index 70587a6..e46afbe 100644
--- a/board/avionic-design/dts/tegra20-medcom-wide.dts
+++ b/board/avionic-design/dts/tegra20-medcom-wide.dts
@@ -14,16 +14,6 @@
reg = 0x 0x2000;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = 32000;
- };
-
- osc {
- clock-frequency = 1200;
- };
- };
-
host1x {
status = okay;
@@ -37,10 +27,6 @@
};
};
- clock@60006000 {
- clocks = clk_32k osc;
- };
-
serial@70006300 {
clock-frequency = 21600;
};
diff --git a/board/avionic-design/dts/tegra20-plutux.dts
b/board/avionic-design/dts/tegra20-plutux.dts
index 78c394f..3e6cce0 100644
--- a/board/avionic-design/dts/tegra20-plutux.dts
+++ b/board/avionic-design/dts/tegra20-plutux.dts
@@ -14,20 +14,6 @@
reg = 0x 0x2000;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = 32000;
- };
-
- osc {
- clock-frequency = 1200;
- };
- };
-
- clock@60006000 {
- clocks = clk_32k osc;
- };
-
serial@70006300 {
clock-frequency = 21600;
};
diff --git a/board/avionic-design/dts/tegra20-tec.dts
b/board/avionic-design/dts/tegra20-tec.dts
index cdb7527..8135eeb 100644
--- a/board/avionic-design/dts/tegra20-tec.dts
+++ b/board/avionic-design/dts/tegra20-tec.dts
@@ -14,16 +14,6 @@
reg = 0x 0x2000;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = 32000;
- };
-
- osc {
- clock-frequency = 1200;
- };
- };
-
host1x {
status = okay;
@@ -37,10 +27,6 @@
};
};
- clock@60006000 {
- clocks = clk_32k osc;
- };
-
serial@70006300 {
clock-frequency = 21600;
};
diff --git a/board/compal/dts/tegra20-paz00.dts
b/board/compal/dts/tegra20-paz00.dts
index afebbe5..0fef713 100644
--- a/board/compal/dts/tegra20-paz00.dts
+++ b/board/compal/dts/tegra20-paz00.dts
@@ -14,19 +14,6 @@
reg = 0x 0x2000;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = 32000;
- };
- osc {
- clock-frequency
[U-Boot] [PATCH] tegra: fdt: sort dts files
Sort nodes in dts files according the the following rules:
1) Any nodes that already exist in any /include/d file, in the order
they appear in the /include/d file.
2) Any nodes with a reg property, in order of their address.
3) Any nodes without a reg property, alphabetically by node name.
Signed-off-by: Allen Martin amar...@nvidia.com
---
v1: split this out from SPI driver series
---
arch/arm/dts/tegra20.dtsi| 377 +++---
board/avionic-design/dts/tegra20-tec.dts | 22 +-
board/compal/dts/tegra20-paz00.dts | 22 +-
board/nvidia/dts/tegra20-harmony.dts | 20 +-
board/nvidia/dts/tegra20-seaboard.dts| 108 -
5 files changed, 268 insertions(+), 281 deletions(-)
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index cc086b1..46e3785 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -4,10 +4,102 @@
compatible = nvidia,tegra20;
interrupt-parent = intc;
- tegra_car: clock@60006000 {
- compatible = nvidia,tegra20-car;
- reg = 0x60006000 0x1000;
- #clock-cells = 1;
+ host1x {
+ compatible = nvidia,tegra20-host1x, simple-bus;
+ reg = 0x5000 0x00024000;
+ interrupts = 0 65 0x04 /* mpcore syncpt */
+ 0 67 0x04; /* mpcore general */
+ status = disabled;
+
+ #address-cells = 1;
+ #size-cells = 1;
+
+ ranges = 0x5400 0x5400 0x0400;
+
+ /* video-encoding/decoding */
+ mpe {
+ reg = 0x5404 0x0004;
+ interrupts = 0 68 0x04;
+ status = disabled;
+ };
+
+ /* video input */
+ vi {
+ reg = 0x5408 0x0004;
+ interrupts = 0 69 0x04;
+ status = disabled;
+ };
+
+ /* EPP */
+ epp {
+ reg = 0x540c 0x0004;
+ interrupts = 0 70 0x04;
+ status = disabled;
+ };
+
+ /* ISP */
+ isp {
+ reg = 0x5410 0x0004;
+ interrupts = 0 71 0x04;
+ status = disabled;
+ };
+
+ /* 2D engine */
+ gr2d {
+ reg = 0x5414 0x0004;
+ interrupts = 0 72 0x04;
+ status = disabled;
+ };
+
+ /* 3D engine */
+ gr3d {
+ reg = 0x5418 0x0004;
+ status = disabled;
+ };
+
+ /* display controllers */
+ dc@5420 {
+ compatible = nvidia,tegra20-dc;
+ reg = 0x5420 0x0004;
+ interrupts = 0 73 0x04;
+ status = disabled;
+
+ rgb {
+ status = disabled;
+ };
+ };
+
+ dc@5424 {
+ compatible = nvidia,tegra20-dc;
+ reg = 0x5424 0x0004;
+ interrupts = 0 74 0x04;
+ status = disabled;
+
+ rgb {
+ status = disabled;
+ };
+ };
+
+ /* outputs */
+ hdmi {
+ compatible = nvidia,tegra20-hdmi;
+ reg = 0x5428 0x0004;
+ interrupts = 0 75 0x04;
+ status = disabled;
+ };
+
+ tvo {
+ compatible = nvidia,tegra20-tvo;
+ reg = 0x542c 0x0004;
+ interrupts = 0 76 0x04;
+ status = disabled;
+ };
+
+ dsi {
+ compatible = nvidia,tegra20-dsi;
+ reg = 0x5430 0x0004;
+ status = disabled;
+ };
};
intc: interrupt-controller@50041000 {
@@ -18,44 +110,33 @@
0x50040100 0x0100 ;
};
- i2c@7000c000 {
- #address-cells = 1;
- #size-cells = 0;
- compatible = nvidia,tegra20-i2c;
- reg = 0x7000C000 0x100;
- interrupts = 70 ;
- /* PERIPH_ID_I2C1, PLL_P_OUT3 */
- clocks = tegra_car 12, tegra_car 124;
+ tegra_car: clock@60006000 {
+ compatible = nvidia,tegra20-car;
+ reg = 0x60006000 0x1000;
+ #clock-cells = 1;
};
- i2c@7000c400 {
- #address
[U-Boot] [PATCH] tegra: fdt: remove clocks nodes
These nodes are unused.
Signed-off-by: Allen Martin amar...@nvidia.com
---
arch/arm/dts/tegra20.dtsi| 10 --
arch/arm/dts/tegra30.dtsi| 10 --
board/compulab/dts/tegra20-trimslice.dts |9 -
board/nvidia/dts/tegra20-harmony.dts |9 -
board/nvidia/dts/tegra20-seaboard.dts|6 --
board/nvidia/dts/tegra20-ventana.dts |9 -
board/nvidia/dts/tegra20-whistler.dts|6 --
board/nvidia/dts/tegra30-cardhu.dts |9 -
8 files changed, 68 deletions(-)
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 636ec2c..cc086b1 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -10,16 +10,6 @@
#clock-cells = 1;
};
- clocks {
- #address-cells = 1;
- #size-cells = 0;
-
- osc: clock {
- compatible = fixed-clock;
- #clock-cells = 0;
- };
- };
-
intc: interrupt-controller@50041000 {
compatible = nvidia,tegra20-gic;
interrupt-controller;
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index 664c397..09bdb36 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -9,16 +9,6 @@
#clock-cells = 1;
};
- clocks {
- #address-cells = 1;
- #size-cells = 0;
-
- osc: clock {
- compatible = fixed-clock;
- #clock-cells = 0;
- };
- };
-
i2c@7000c000 {
#address-cells = 1;
#size-cells = 0;
diff --git a/board/compulab/dts/tegra20-trimslice.dts
b/board/compulab/dts/tegra20-trimslice.dts
index 4450674..92e3e0f 100644
--- a/board/compulab/dts/tegra20-trimslice.dts
+++ b/board/compulab/dts/tegra20-trimslice.dts
@@ -15,15 +15,6 @@
reg = 0x 0x4000;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = 32000;
- };
- osc {
- clock-frequency = 1200;
- };
- };
-
clock@60006000 {
clocks = clk_32k osc;
};
diff --git a/board/nvidia/dts/tegra20-harmony.dts
b/board/nvidia/dts/tegra20-harmony.dts
index 5645a8d..332ace1 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -15,15 +15,6 @@
reg = 0x 0x4000;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = 32000;
- };
- osc {
- clock-frequency = 1200;
- };
- };
-
clock@60006000 {
clocks = clk_32k osc;
};
diff --git a/board/nvidia/dts/tegra20-seaboard.dts
b/board/nvidia/dts/tegra20-seaboard.dts
index dd98ca4..2d834da 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -45,12 +45,6 @@
};
};
- clocks {
- osc {
- clock-frequency = 1200;
- };
- };
-
clock@60006000 {
clocks = clk_32k osc;
};
diff --git a/board/nvidia/dts/tegra20-ventana.dts
b/board/nvidia/dts/tegra20-ventana.dts
index 38b7b13..bbb4480 100644
--- a/board/nvidia/dts/tegra20-ventana.dts
+++ b/board/nvidia/dts/tegra20-ventana.dts
@@ -14,15 +14,6 @@
reg = 0x 0x4000;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = 32000;
- };
- osc {
- clock-frequency = 1200;
- };
- };
-
clock@60006000 {
clocks = clk_32k osc;
};
diff --git a/board/nvidia/dts/tegra20-whistler.dts
b/board/nvidia/dts/tegra20-whistler.dts
index f830cf3..3c575e6 100644
--- a/board/nvidia/dts/tegra20-whistler.dts
+++ b/board/nvidia/dts/tegra20-whistler.dts
@@ -16,12 +16,6 @@
reg = 0x 0x2000 ;
};
- clocks {
- osc {
- clock-frequency = 1200;
- };
- };
-
clock@60006000 {
clocks = clk_32k osc;
};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts
b/board/nvidia/dts/tegra30-cardhu.dts
index 60b91b4..00388fa 100644
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -20,15 +20,6 @@
reg = 0x8000 0x4000;
};
- clocks {
- clk_32k: clk_32K {
- clock-frequency = 32768;
- };
- osc {
- clock-frequency = 1200;
- };
- };
-
clock@60006000
Re: [U-Boot] [PATCH v2 8/9] tegra: add SPI SLINK driver
On Sat, Jan 12, 2013 at 08:56:23AM -0800, Simon Glass wrote:
Hi,
On Sat, Jan 12, 2013 at 1:07 AM, Allen Martin amar...@nvidia.com wrote:
Add driver for tegra SPI SLINK style driver. This controller is
similar to the tegra20 SPI SFLASH controller. The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices. In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH. Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.
This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.
To enable this driver, use CONFIG_TEGRA_SLINK
A few comments - note I am on holiday next week so please don't wait
for my response on the next version.
...
+#include spi.h
+#ifdef CONFIG_OF_CONTROL
You probably don't need this ifdef
ok
+
+ spi = malloc(sizeof(struct tegra_spi_slave));
Please also look at my SPI series where I added an allocate function for this.
http://patchwork.ozlabs.org/patch/208226/
http://patchwork.ozlabs.org/patch/208229/
Nice, thanks. I propose I should wait for that to land in
u-boot/master and trick back down to u-boot-arm and u-boot-tegra, and
then add it in a separate patch. That way I don't have to add a
cross repo dependency.
+{
+ int node = 0, i;
+ struct tegra_spi_ctrl *ctrl;
blank line here
ok
+ for (i = 0; i CONFIG_TEGRA_SLINK_CTRLS; i++) {
+ ctrl = spi_ctrls[i];
+#ifdef CONFIG_OF_CONTROL
+ node = fdtdec_next_compatible(gd-fdt_blob, node,
+ COMPAT_NVIDIA_TEGRA20_SLINK);
+ if (!node)
+ break;
I think you should be using fdtdec_find_aliases_for_id() so that aliases work.
I'll reply in Stephen's follow-up on this.
+ (slave-cs SLINK_CMD2_SS_EN_SHIFT);
+ writel(reg, regs-command2);
Could use clrsetbits_le32() if you like
Ok
+ bytes = (num_bytes 4) ? 4 : num_bytes;
+
+ if (dout != NULL) {
+ for (i = 0; i bytes; ++i)
+ tmpdout = (tmpdout 8) | dout[i];
dout += bytes here...
+ }
+
+ num_bytes -= bytes;
+ if (dout)
+ dout += bytes;
instead of here?
ok
+
+ clrsetbits_le32(regs-command, SLINK_CMD_BIT_LENGTH_MASK,
+ bytes * 8 - 1);
+ writel(tmpdout, regs-tx_fifo);
+ setbits_le32(regs-command, SLINK_CMD_GO);
+
+ /*
+* Wait for SPI transmit FIFO to empty, or to time out.
+* The RX FIFO status will be read and cleared last
+*/
+ for (tm = 0, is_read = 0; tm SPI_TIMEOUT; ++tm) {
+ u32 status;
+
This says timeout but doesn't seem to actually check get_timer(). Also
is it possible to separate the code that waits for completion from the
code below?
You're right about get_timer(), I'll fix that.
I pulled this loop directly from the tegra20 tegra_spi driver, so I'm
not the original author, but I believe the reason it's written this
way is so there's a single timeout loop around the wait for STAT_BSY
to drop, RXF_EMPTY to drop, and TXF_EMPTY to go high. It *should* be
ok to move the TXF_EMPTY wait to a separate wait loop, but I'm a
little hesitant to touch the code since it's beeen well tested in the
tegra20 driver, and this part of the driver is identical.
+ status = readl(regs-status);
+
+ /* We can exit when we've had both RX and TX
activity */
+ if (is_read (status SLINK_STAT_TXF_EMPTY))
+ break;
+
+ if ((status (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
+ SLINK_STAT_RDY)
+ tm++;
+
+ else if (!(status SLINK_STAT_RXF_EMPTY)) {
+ tmpdin = readl(regs-rx_fifo);
+ is_read = 1;
+
+ /* swap bytes read in */
+ if (din != NULL) {
+ for (i = bytes - 1; i = 0; --i) {
+ din[i] = tmpdin 0xff;
+ tmpdin = 8
