[...]
diff --git a/include/mmc.h b/include/mmc.h
index 4b8327f1f93b..7243bd761202 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -381,6 +381,21 @@ enum mmc_voltage {
#define MMC_TIMING_MMC_HS200 9
#define MMC_TIMING_MMC_HS400 10
+/* emmc hardware partition values */
+enum
On 4/26/24 7:36 PM, Tim Harvey wrote:
On Fri, Apr 26, 2024 at 10:25 AM Marek Vasut wrote:
On 4/26/24 7:12 PM, Tim Harvey wrote:
eMMC devices have hardware partitions such as user, boot0, and boot1.
Allow these names to be displayed when reading the mmc PARTITION_CONFIG
field via 'mmc
On 4/26/24 4:39 PM, Heinrich Schuchardt wrote:
On 26.04.24 06:03, Marek Vasut wrote:
On 4/26/24 2:16 AM, Tim Harvey wrote:
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index 7a2543e16cc..4fbce519a0b 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl
On 4/26/24 7:12 PM, Tim Harvey wrote:
eMMC devices have hardware partitions such as user, boot0, and boot1.
Allow these names to be displayed when reading the mmc PARTITION_CONFIG
field via 'mmc partconf'. Additionally allow a name to be specified when
setting the PARTITION_CONFIG.
Before:
On 4/26/24 6:00 PM, Tom Rini wrote:
On Fri, Apr 26, 2024 at 08:56:29AM -0700, Tim Harvey wrote:
On Fri, Apr 26, 2024 at 8:51 AM Tom Rini wrote:
On Fri, Apr 26, 2024 at 08:30:23AM -0700, Tim Harvey wrote:
On Thu, Apr 25, 2024 at 4:07 PM Marek Vasut wrote:
Update documentation and use
On 4/26/24 5:14 PM, Tim Harvey wrote:
On Thu, Apr 25, 2024 at 9:07 PM Marek Vasut wrote:
On 4/26/24 2:14 AM, Tim Harvey wrote:
eMMC devices have hardware partitions such as user, boot0, and boot1.
Allow these names to be displayed when reading the mmc PARTITION_CONFIG
field via 'mmc partconf
On 4/26/24 8:27 AM, Jaehoon Chung wrote:
Dear Marek,
-Original Message-
From: Marek Vasut
Sent: Wednesday, April 24, 2024 8:18 AM
To: u-boot@lists.denx.de; Jaehoon Chung
Cc: Peng Fan ; Simon Glass
Subject: Re: [PATCH v4] mmc: Poll CD in case cyclic framework is enabled
On 3/16/24 9
On 4/26/24 9:49 AM, Patrice CHOTARD wrote:
On 4/22/24 01:16, Marek Vasut wrote:
Add another mux option for ADC pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc
On 4/26/24 2:14 AM, Tim Harvey wrote:
eMMC devices have hardware partitions such as user, boot0, and boot1.
Allow these names to be displayed when reading the mmc PARTITION_CONFIG
field via 'mmc partconf'. Additionally allow a name to be specified when
setting the PARTITION_CONFIG.
Before:
On 4/26/24 2:16 AM, Tim Harvey wrote:
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index 7a2543e16cc..4fbce519a0b 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -6,6 +6,6 @@ obj-y += sec.o
obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o
On 4/25/24 10:34 PM, Tim Harvey wrote:
On Tue, Apr 23, 2024 at 11:33 AM Marek Vasut wrote:
Rework the flash.bin image generation such that it uses the new binman
nxp_imx8mimage etype. This way, the flash.bin is assembled in correct
order using plain binman, without any workarounds or sections
Update documentation and use nxp_imx8mcst binman etype for signing
of flash.bin instead of previous horrible shell scripting.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
ge etype superclass */
+
fit {
description = "Configuration to load ATF before
U-Boot";
#ifndef CONFIG_IMX_HAB
@@ -191,5 +205,6 @@
};
};
};
+ };
};
Differentiate between "Enable Random Number Generator support" and
"Enable Random Number Generator support" in Kconfig entry, mark the
first as CAAM and the second as DCP, otherwise users cannot easily
decide which of the options is which and enable the correct one.
Signed
Add SPL variant of SPL_FSL_CAAM_RNG so that the SPL_FSL_CAAM_RNG can
be disabled in SPL if necessary. This may be necessary due to e.g.
size constraints of the SPL.
Signed-off-by: Marek Vasut
---
Cc: Angelo Dureghello
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Gaurav Jain
Cc: Heinrich
Add SPL variant of DM_RNG so that the DM_RNG can be disabled in SPL
if necessary. This may be necessary due to e.g. size constraints of
the SPL.
Signed-off-by: Marek Vasut
---
Cc: Angelo Dureghello
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Gaurav Jain
Cc: Heinrich Schuchardt
Cc: Marek
# imx8mm_venice
Tested-by: Fabio Estevam # imx8mm-evk and imx8mn-evk
Signed-off-by: Marek Vasut
---
WARNING: This is very likely to break corner case uses, so please do
test this on your platform.
NOTE: This also opens the implementation for proper CST signing etype,
the CST signing would
Include imx8mq-u-boot.dtsi in the board -u-boot.dtsi to pull in binman
configuration instead of duplicating it in the board -u-boot.dtsi again.
Drop the duplicate binman configuration.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
C
it a/tools/binman/etype/nxp_imx8mimage.py
b/tools/binman/etype/nxp_imx8mimage.py
new file mode 100644
index 000..3585120b79b
--- /dev/null
+++ b/tools/binman/etype/nxp_imx8mimage.py
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023-2024 Marek Vasut
+# Written with
Fix a typo, no functional change.
Signed-off-by: Marek Vasut
---
Cc: Alper Nebi Yasak
Cc: Simon Glass
Cc: Tom Rini
Cc: u-boot@lists.denx.de
---
tools/binman/btool/mkimage.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/binman/btool/mkimage.py b/tools/binman/btool
s bit") in the
upstream kernel is taken as reference.
Signed-off-by: Aswath Govindraju
Signed-off-by: Ravi Gunasekaran
Reviewed-by: Roger Quadros
Reviewed-by: Marek Vasut
---
Changes since v2:
* Updated the commit description with reference to upstream kernel commit
*
On 4/19/24 5:24 PM, Tim Harvey wrote:
On Thu, Apr 18, 2024 at 11:42 AM Marek Vasut wrote:
On 4/18/24 8:02 PM, Fabio Estevam wrote:
Hi Tim,
On Thu, Apr 18, 2024 at 2:54 PM Tim Harvey wrote:
Fabio, if you enable CONFIG_DM_RNG on an imx8m{m,p}_evk do you get the
following in the SPL
On 4/23/24 9:09 AM, Mattijs Korpershoek wrote:
Hi Greg,
On ven., avril 19, 2024 at 15:21, Greg Malysa wrote:
Hi Mattijs,
Please avoid top-posting when replying, it makes following the
discussion more difficult:
On 3/16/24 9:13 PM, Marek Vasut wrote:
In case the cyclic framework is enabled, poll the card detect of already
initialized cards and deinitialize them in case they are removed. Since
the card initialization is a longer process and card initialization is
done on first access to an uninitialized
on, it is possible to supplant the generator
functionality by fixed-clock.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Fabio Estevam
Cc: Simon Glass
Cc: Stefano Babic
Cc: Tom Rini
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
arch/arm/dts/imx8mp-dhcom-pdk3-u-boot
Rework the flash.bin image generation such that it uses the new binman
nxp_imx8mimage etype. This way, the flash.bin is assembled in correct
order using plain binman, without any workarounds or sections assembled
in special DT node order.
Signed-off-by: Marek Vasut
---
WARNING: This is very
Include imx8mq-u-boot.dtsi in the board -u-boot.dtsi to pull in binman
configuration instead of duplicating it in the board -u-boot.dtsi again.
Drop the duplicate binman configuration.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
C
nman/etype/nxp_imx8mimage.py
b/tools/binman/etype/nxp_imx8mimage.py
new file mode 100644
index 000..5a106e0a76e
--- /dev/null
+++ b/tools/binman/etype/nxp_imx8mimage.py
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023-2024 Marek Vasut
+# Written with much help from Simon Glass
+
On 4/23/24 3:35 PM, Detlev Casanova wrote:
On Monday, April 22, 2024 3:47:21 P.M. EDT Marek Vasut wrote:
On 4/22/24 3:56 PM, Detlev Casanova wrote:
On some boards, a MAC address is set based on the CPU ID or other
information. This is usually done in the misc_init_r() function.
This becomes
the commit message.
With that fixed:
Reviewed-by: Marek Vasut
Thanks !
On 4/23/24 10:51 AM, Philip Oberfichtner wrote:
Bevor this commit, only clause 22 access was possible. After this commit,
clause 45 direct access will available as well.
Note that there is a slight change of behavior: Before this commit, the
C45E bit was set to whatever value was left in the
On 4/22/24 12:53 PM, Caleb Connolly wrote:
On 21/04/2024 22:38, Marek Vasut wrote:
On 4/11/24 6:05 PM, Caleb Connolly wrote:
The revision is different for these, add the additional check as in
xhci-dwc3 core_init code.
Signed-off-by: Caleb Connolly
Is there a matching Linux kernel patch
On 4/22/24 7:31 AM, Kongyang Liu wrote:
[...]
@@ -167,9 +168,20 @@ static void dwc_otg_core_reset(struct udevice *dev,
dev_info(dev, "%s: Timeout!\n", __func__);
/* Core Soft Reset */
+ snpsid = readl(>gsnpsid);
writel(DWC2_GRSTCTL_CSFTRST, >grstctl);
-
On 4/22/24 3:56 PM, Detlev Casanova wrote:
---
configs/rock5b-rk3588_defconfig | 1 +
1 file changed, 1 insertion(+)
This patch seems to be missing commit message and SoB line
On 4/22/24 3:56 PM, Detlev Casanova wrote:
On some boards, a MAC address is set based on the CPU ID or other
information. This is usually done in the misc_init_r() function.
This becomes a problem for net devices that are probed after the call to
misc_init_r(), for example, when the ethernet is
contains the following peripherals:
- Two RGMII Ethernet ports
- USB-A Host port, USB-C peripheral port, USB-C power supply plug
- Expansion connector
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
Add another mux option for UART7 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 41
Add another mux option for UART4 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 30
Add another mux option for USART2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 41
Add another mux option for USART1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 30
Add another mux option for SPI3 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 23
Add another mux option for SPI2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 23
Add another mux option for SDMMC2 D4..D7 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13
Add another mux option for SAI1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 32
Add another mux option for QSPI pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 51
Add another mux option for PWM13 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 15
Add another mux option for PWM5 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 15
Add another mux option for MCAN2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 20
Add another mux option for MCAN1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 20
Add another mux option for I2C5 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 17
Add another mux option for ETH2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 45
Add another mux option for ETH1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 46
Add another mux option for ADC CC pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 7
Add another mux option for ADC pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 6
From: Christophe Roullier
Add both ethernet MACs based on GMAC SNPS IP on stm32mp13.
Signed-off-by: Christophe Roullier
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
Cc: u-b...@dh-electronics.com
Cc:
On 3/28/24 2:14 PM, Kongyang Liu wrote:
[...]
@@ -464,12 +464,26 @@ static void reconfig_usbd(struct dwc2_udc *dev)
{
/* 2. Soft-reset OTG Core and then unreset again. */
int i;
- unsigned int uTemp = writel(CORE_SOFT_RESET, >grstctl);
+ unsigned int uTemp;
On 4/11/24 6:05 PM, Caleb Connolly wrote:
The revision is different for these, add the additional check as in
xhci-dwc3 core_init code.
Signed-off-by: Caleb Connolly
Is there a matching Linux kernel patch , or does Linux do some other check ?
On 3/19/24 3:45 AM, Marek Vasut wrote:
This patch adds STM32 PWR regulators DT support on stm32mp131.
This requires TFA to clear RCC_SECCFGR, is disabled by default
and can only be enabled on board DT level.
Signed-off-by: Marek Vasut
It seems these patches have been missed from the recent
. In case either of the IWDG is
enabled, ping it first and then return to the OS.
Signed-off-by: Marek Vasut
---
Cc: Igor Opaniuk
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Simon Glass
Cc: Tom Rini
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/mach-stm32mp
On 4/19/24 5:29 PM, Tim Harvey wrote:
Add support for PCIe clocks required to enable PCIe support on
iMX8MM SoC.
Signed-off-by: Tim Harvey
Reviewed-by: Marek Vasut
On 4/18/24 8:24 PM, Patrick DELAUNAY wrote:
Hi,
Hi,
[...]
@@ -136,6 +140,18 @@ static void security_init(void)
*/
writel(0x0, TAMP_CR1);
+ /*
+ * TAMP: Configure non-zero secure protection settings. This is
+ * checked by BootROM function 35ac on OTP-CLOSED device
until it reaches handoff to the TAMP BKPxR 5
branch address.
This fixes CPU core 1 release using U-Boot PSCI implementation on an
OTP-CLOSED system, i.e. system with fuse 0 bit 6 set.
Reviewed-by: Patrick Delaunay
Signed-off-by: Marek Vasut
---
Cc: Igor Opaniuk
Cc: Patrice Chotard
Cc: Patrick
On 4/18/24 8:02 PM, Fabio Estevam wrote:
Hi Tim,
On Thu, Apr 18, 2024 at 2:54 PM Tim Harvey wrote:
Fabio, if you enable CONFIG_DM_RNG on an imx8m{m,p}_evk do you get the
following in the SPL?
Couldn't bind rng driver (-96)
SEC0: RNG instantiated
sec_init failed!
Yes, if I add
On 4/18/24 8:24 PM, Tim Harvey wrote:
On Thu, Apr 18, 2024 at 11:14 AM Marek Vasut wrote:
On 4/18/24 7:56 PM, Tim Harvey wrote:
Add support for PCIe clocks required to enable PCIe support on
iMX8MM SoC.
Signed-off-by: Tim Harvey
---
v2: no changes
---
drivers/clk/imx/clk-imx8mm.c | 21
On 4/18/24 7:56 PM, Tim Harvey wrote:
Add support for PCIe clocks required to enable PCIe support on
iMX8MM SoC.
Signed-off-by: Tim Harvey
---
v2: no changes
---
drivers/clk/imx/clk-imx8mm.c | 21 +
1 file changed, 21 insertions(+)
diff --git
On 4/18/24 7:56 PM, Tim Harvey wrote:
Add support for the IMX8MM SoC by adding driver data with the compatible
string of the GPR controller.
Signed-off-by: Tim Harvey
Reviewed-by: Marek Vasut
On 4/18/24 6:21 PM, Tim Harvey wrote:
On Fri, Jan 19, 2024 at 4:36 PM Marek Vasut wrote:
Linux 6.6.y with KASLR enabled would print the following message on boot:
"
KASLR disabled due to lack of seed
"
Enable the 'kaslrseed' command so a random number seed can be pulled
from CAAM an
On 4/18/24 1:36 PM, Patrice CHOTARD wrote:
On 4/17/24 18:47, Marek Vasut wrote:
On 3/26/24 1:07 PM, Marek Vasut wrote:
Split off STM32 glue code from the DWMAC driver into separate
file, similar to what other SoCs already do, to avoid mixing
the ST specifics with generic DWMAC core code
master-fdt
for you to fetch changes up to aad511a488c40393728156333d983c31001aac32:
ARM: dts: renesas: Switch to using upstream DT (2024-04-18 05:21:26 +0200)
--------
Marek Vasut (4):
ARM: dts: renesas: Stop using the -u-boot DTs
On 4/17/24 10:09 PM, Tim Harvey wrote:
Add support for the IMX8MM SoC by adding driver data with the compatible
string of the GPR controller.
Signed-off-by: Tim Harvey
---
drivers/pci/pcie_dw_imx.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git
On 3/26/24 1:07 PM, Marek Vasut wrote:
Split off STM32 glue code from the DWMAC driver into separate
file, similar to what other SoCs already do, to avoid mixing
the ST specifics with generic DWMAC core code.
Clean the STM32 DWMAC board code which is currently duplicated
in multiple board files
On 4/17/24 10:41 AM, Nicole Battenfeld wrote:
Subject: [PATCH] dwc_eth_qos: Revert regression handling fixed phy
In imx8mp operation on eqos with fixed phy I get without that patch:
ERROR: no/invalid
Which commit is being reverted here ?
On 4/15/24 11:48 AM, Patrice CHOTARD wrote:
On 4/14/24 20:39, Marek Vasut wrote:
In case of an OTP-CLOSED STM32MP15xx system, the CPU core 1 cannot be
released from endless loop in BootROM only by populating TAMP BKPxR 4
and 5 with magic and branch address and sending SGI0 interrupt from
core
until it reaches handoff to the TAMP BKPxR 5
branch address.
This fixes CPU core 1 release using U-Boot PSCI implementation on an
OTP-CLOSED system, i.e. system with fuse 0 bit 6 set.
Signed-off-by: Marek Vasut
---
Cc: Igor Opaniuk
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Simon Glass
Cc
On 4/14/24 11:28 PM, Laurent Pinchart wrote:
On Sun, Apr 14, 2024 at 11:25:06PM +0200, Marek Vasut wrote:
On 4/14/24 9:29 PM, Laurent Pinchart wrote:
Hi Marek,
Thank you for the patch.
On Sun, Apr 14, 2024 at 08:37:20PM +0200, Marek Vasut wrote:
In case of systems where DRAM bank ends
On 4/14/24 9:29 PM, Laurent Pinchart wrote:
Hi Marek,
Thank you for the patch.
On Sun, Apr 14, 2024 at 08:37:20PM +0200, Marek Vasut wrote:
In case of systems where DRAM bank ends at the edge of 32bit boundary,
start + size calculations would overflow. This happens on STM32MP15xx
with 1 DRAM
The following changes since commit cdfcc37428e06f4730ab9a17cc084eeb7676ea1a:
Merge tag 'u-boot-dfu-next-20240402' of
https://source.denx.de/u-boot/custodians/u-boot-dfu (2024-04-02 22:37:23 -0400)
are available in the Git repository at:
git://source.denx.de/u-boot-usb.git master
for you
until it reaches handoff to the TAMP BKPxR 5
branch address.
This fixes CPU core 1 release using U-Boot PSCI implementation on an
OTP-CLOSED system, i.e. system with fuse 0 bit 6 set.
Signed-off-by: Marek Vasut
---
Cc: Igor Opaniuk
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Simon Glass
Cc
as this might open a brief window for timing attacks.
Instead, report that this system is OTP-CLOSED and do not
report any SoC revision to avoid confusing users. Use an
SEC/C abbreviation to avoid growing SOC_NAME_SIZE .
Signed-off-by: Marek Vasut
---
Cc: Igor Opaniuk
Cc: Patrice Chotard
Cc: Patrick
The source file is in arch/arm/mach-stm32mp/ecdsa_romapi.c and not
in arch/arm/mach-stm32mp/stm32mp1/ecdsa_romapi.c . There are two
Makefile entries in each subdirectory. Drop the bogus one and keep
only the correct one, the one in arch/arm/mach-stm32mp/Makefile .
Signed-off-by: Marek Vasut
calculations using u64 types. This also covers a case where
a 32bit PAE system might be able to address up to 36bits of DRAM.
Fixes: a4df06e41fa2 ("boot: fdt: Change type of env_get_bootm_low() to
phys_addr_t")
Signed-off-by: Marek Vasut
---
Cc: Laurent Pinchart
Cc: Matthias Schiffer
Cc: S
On 4/12/24 8:37 PM, Tom Rini wrote:
On Fri, Apr 12, 2024 at 08:26:18PM +0200, Marek Vasut wrote:
On 4/12/24 2:53 PM, Marek Vasut wrote:
Hi,
Seems to work here with a broken imx8 config from the CI. Is it ok to
rely on dead code elimination? Apparently it is, build with KCFLAGS=-O0
has
On 4/12/24 2:53 PM, Marek Vasut wrote:
Hi,
Seems to work here with a broken imx8 config from the CI. Is it ok to
rely on dead code elimination? Apparently it is, build with KCFLAGS=-O0
has already several other missing symbols.
See attached fixup
Thanks, squashed, let's see how CI likes
On 12/31/23 9:38 PM, Aren Moynihan wrote:
Add support for building the sunxi-musb driver with DM_USB_GADGET
including adding a separate IRQ handling function and registering the
driver with the musb system differently.
The implementation of usb_gadget_register_driver from
musb-new/musb_uboot.c
On 4/8/24 9:46 AM, Janne Grunau wrote:
On Sun, Apr 07, 2024 at 03:05:59AM +0200, Marek Vasut wrote:
On 4/6/24 10:04 PM, Janne Grunau wrote:
On Sat, Apr 06, 2024 at 08:52:17PM +0200, Marek Vasut wrote:
On 4/5/24 9:05 PM, Janne Grunau wrote:
On Fri, Apr 05, 2024 at 04:52:32PM +0200, Marek
stored on stack
with 'ep' value in case of a successful resume, which is really in
every case unless some catastrophic failure occurred during suspend.
Without this change, Linux counts every resume as failed in
/sys/power/suspend_stats/fail
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc
On 4/6/24 10:04 PM, Janne Grunau wrote:
On Sat, Apr 06, 2024 at 08:52:17PM +0200, Marek Vasut wrote:
On 4/5/24 9:05 PM, Janne Grunau wrote:
On Fri, Apr 05, 2024 at 04:52:32PM +0200, Marek Vasut wrote:
On 4/4/24 8:25 AM, Janne Grunau via B4 Relay wrote:
Apple USB Keyboards from 2021 need
On 4/5/24 9:05 PM, Janne Grunau wrote:
On Fri, Apr 05, 2024 at 04:52:32PM +0200, Marek Vasut wrote:
On 4/4/24 8:25 AM, Janne Grunau via B4 Relay wrote:
Apple USB Keyboards from 2021 need quirks to be useable. The boot HID
keyboard protocol is unfortunately not described in the first interface
On 4/5/24 4:56 PM, Christophe ROULLIER wrote:
On 3/9/24 03:11, Marek Vasut wrote:
From: Christophe Roullier
Add compatible "st,stm32mp13-dwmac" to manage STM32MP13 boards.
Signed-off-by: Christophe Roullier
Signed-off-by: Marek Vasut # Rebase, reshuffle, squash
code
---
Cc:
On 4/4/24 8:25 AM, Janne Grunau via B4 Relay wrote:
Apple USB Keyboards from 2021 need quirks to be useable. The boot HID
keyboard protocol is unfortunately not described in the first interface
descriptor but the second. This needs several changes. The USB keyboard
driver has to look at all (2)
stored on stack
with 'ep' value in case of a successful resume, which is really in
every case unless some catastrophic failure occurred during suspend.
Without this change, Linux counts every resume as failed in
/sys/power/suspend_stats/fail
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc
On 3/28/24 4:08 PM, Tom Rini wrote:
On Mon, Feb 05, 2024 at 04:13:23PM +0800, Jacky Chou wrote:
From the ethernet header is not on aligned, because the length
of the ethernet header is 14 bytes.
Therefore, unaligned access must be done here.
Signed-off-by: Jacky Chou
Applied to
On 3/28/24 10:20 AM, Lukasz Majewski wrote:
Dear Community,
I'd like to share with you some thoughts about growth of u-boot's
binary size for SPL and u-boot proper.
Board: XEA
SoC : imx287 (still in active production)
Problem: SPL size constrained to ~55 KiB (This cannot be exceeded).
On 3/20/24 10:00 PM, Laurent Pinchart wrote:
On Wed, Mar 20, 2024 at 09:52:34PM +0100, Marek Vasut wrote:
On 3/18/24 5:18 PM, Laurent Pinchart wrote:
@@ -142,7 +140,7 @@ phys_size_t env_get_bootm_size(void)
s = env_get("bootm_low");
if (s)
- tmp = (p
Move the variable below comment which explains what the variable means.
Update the comment. No functional change.
Reviewed-by: Laurent Pinchart
Suggested-by: Laurent Pinchart
Signed-off-by: Marek Vasut
---
Cc: Heinrich Schuchardt
Cc: Kuninori Morimoto
Cc: Laurent Pinchart
Cc: Simon Glass
The lmb_alloc_base() returns phys_addr_t , map_sysmem() accepts
phys_addr_t as first parameter. Declare 'addr' as phys_addr_t and
get rid of the casts.
Reviewed-by: Laurent Pinchart
Reported-by: Laurent Pinchart
Signed-off-by: Marek Vasut
---
Cc: Heinrich Schuchardt
Cc: Kuninori Morimoto
Cc
Reduce tmp variable use and remove unnecessary type cast in
env_get_bootm_mapsize(). This aligns the env variable parsing
with env_get_bootm_low(). No functional change.
Signed-off-by: Marek Vasut
---
Cc: Heinrich Schuchardt
Cc: Kuninori Morimoto
Cc: Laurent Pinchart
Cc: Simon Glass
Cc: Tom
Change type of 'tmp' variable from phys_size_t to phys_addr_t and
rename it to 'low' to better describe what the variable represents,
which is either the bootm_low address from environment or start of
DRAM address.
Signed-off-by: Marek Vasut
---
Cc: Heinrich Schuchardt
Cc: Kuninori Morimoto
Cc
Reduce tmp variable use and remove unnecessary type cast in
env_get_bootm_size(). This aligns the env variable parsing
with env_get_bootm_low(). No functional change.
Signed-off-by: Marek Vasut
---
Cc: Heinrich Schuchardt
Cc: Kuninori Morimoto
Cc: Laurent Pinchart
Cc: Simon Glass
Cc: Tom
the content
of "bootm_low" environment variable. Fix it by using phys_addr_t, similar to
what env_get_bootm_size() does, which returns phys_size_t .
Reviewed-by: Laurent Pinchart
Reported-by: Laurent Pinchart
Signed-off-by: Marek Vasut
---
Cc: Heinrich Schuchardt
Cc: Kuninori Morimoto
C
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