Re: [PATCH v1 7/7] MAINTAINERS: Update Starfive visionfive2 maintain files.
On 5/4/24 5:03 PM, Minda Chen wrote: Add USB related files to Starfive visionfive2 MAINTAINERS. Signed-off-by: Minda Chen --- board/starfive/visionfive2/MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS index d7f638f9b4..1faf83f581 100644 --- a/board/starfive/visionfive2/MAINTAINERS +++ b/board/starfive/visionfive2/MAINTAINERS @@ -6,3 +6,5 @@ F: board/starfive/visionfive2/ F:include/configs/starfive-visionfive2.h F:configs/starfive_visionfive2_defconfig F:drivers/pci/pcie_starfive_jh7110.c +F: drivers/phy/starfive/ +F: drivers/usb/cdns3/cdns3-starfive.c Thanks ! Reviewed-by: Marek Vasut
Re: [PATCH v1 4/7] usb: cdns: starfive: Add cdns USB driver
On 5/4/24 5:03 PM, Minda Chen wrote:
[...]
+static void cdns_mode_init(struct cdns_starfive *data, enum usb_dr_mode mode)
+{
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_MISC_CFG_MASK,
+ USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
+
+ switch (mode) {
+ case USB_DR_MODE_HOST:
+ regmap_update_bits(data->stg_syscon,
+ data->stg_usb_mode,
+ USB_STRAP_MASK,
+ USB_STRAP_HOST);
+ regmap_update_bits(data->stg_syscon,
+ data->stg_usb_mode,
+ USB_SUSPENDM_MASK,
+ USB_SUSPENDM_HOST);
Can you deduplicate thse regmap_update_bits at the end of this function
? Set a variable to USB_STRAP_HOST and another to USB_SUSPENDM_HOST
here, set the same variables to USB_STRAP_DEVICE/0 below, and then call
regmap_update_bits() with these variables at the end of this function once.
+ break;
+
+ case USB_DR_MODE_PERIPHERAL:
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_STRAP_MASK, USB_STRAP_DEVICE);
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_SUSPENDM_MASK, 0);
+ break;
+ default:
+ break;
+ }
+}
[...]
Re: [PATCH v1 3/7] phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
On 5/4/24 5:03 PM, Minda Chen wrote:
Fix up the copyrights to year 2024 globally please.
[...]
+static int phy_usb3_mode_set(struct jh7110_pcie_phy *data)
+{
Can this phy_usb3_mode_set and phy_pcie_mode_set be unified into single
function with parameter to select usb3/pcie mode instead ?
+ if (!data->stg_syscon || !data->sys_syscon) {
+ dev_err(data->phy->dev, "doesn't support usb3 mode\n");
+ return -EINVAL;
+ }
+
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
+ PCIE_PHY_MODE_MASK, PCIE_PHY_MODE);
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+ PCIE_USB3_BUS_WIDTH_MASK, 0);
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+ PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE);
+
+ /* Connect usb 3.0 phy mode */
+ regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
+ USB_PDRSTN_SPLIT, 0);
+
+ /* Configuare spread-spectrum mode: down-spread-spectrum */
+ writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
+
+ return 0;
+}
[...]
+int jh7110_pcie_phy_probe(struct udevice *dev)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ int rc;
+
+ phy->regs = dev_read_addr_ptr(dev);
+
Drop extra newline here.
+ if (!phy->regs)
+ return -EINVAL;
[...]
Re: [PATCH v1 2/7] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
On 5/4/24 5:03 PM, Minda Chen wrote:
[...]
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
new file mode 100644
index 00..a405a75e34
--- /dev/null
+++ b/drivers/phy/starfive/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Starfive
2024 instead of 2023, please fix globally.
+#
+
+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c
b/drivers/phy/starfive/phy-jh7110-usb2.c
new file mode 100644
index 00..ffbd96d721
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb2.c
[...]
+static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set)
+{
+ unsigned int val;
+
+ /* Host mode enable the LS speed keep-alive signal */
+ val = readl(phy->regs + USB_LS_KEEPALIVE_OFF);
+ if (set)
+ val |= USB_LS_KEEPALIVE_ENABLE;
+ else
+ val &= ~USB_LS_KEEPALIVE_ENABLE;
+
+ writel(val, phy->regs + USB_LS_KEEPALIVE_OFF);
This is clrsetbits_le32(), use it.
+}
+
+static int usb2_phy_set_mode(struct phy *_phy,
+enum phy_mode mode, int submode)
+{
+ struct udevice *dev = _phy->dev;
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (mode != phy->mode) {
Reduce indent this way:
if (mode == phy->mode)
return 0;
... do mode switch stuff ...
return 0;
+ dev_dbg(dev, "Changing phy to %d\n", mode);
+ phy->mode = mode;
+ usb2_set_ls_keepalive(phy, (mode != PHY_MODE_USB_DEVICE));
+ }
+
+ return 0;
+}
+
+static int jh7110_usb2_phy_init(struct phy *_phy)
+{
+ struct udevice *dev = _phy->dev;
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_prepare_enable(phy->app_125m);
return clk_prepare_...(); is just fine
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int jh7110_usb2_phy_exit(struct phy *_phy)
+{
+ struct udevice *dev = _phy->dev;
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+ clk_disable_unprepare(phy->app_125m);
+
+ return 0;
+}
+
+struct phy_ops jh7110_usb2_phy_ops = {
+ .init = jh7110_usb2_phy_init,
+ .exit = jh7110_usb2_phy_exit,
+ .set_mode = usb2_phy_set_mode,
+};
+
+int jh7110_usb2_phy_probe(struct udevice *dev)
+{
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+ phy->regs = dev_read_addr_ptr(dev);
+
Drop extra newline.
+ if (!phy->regs)
+ return -EINVAL;
[...]
Re: [PATCH v1 1/7] usb: cdns3: Set USB PHY mode in cdns3_probe()
On 5/4/24 5:03 PM, Minda Chen wrote:
USB PHY maybe need to set PHY mode in different USB
dr mode. So translate to generic PHY mode and call
generic_phy_set_mode().
Signed-off-by: Minda Chen
---
drivers/usb/cdns3/core.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c
index 12a741c6ea..c1a61471f9 100644
--- a/drivers/usb/cdns3/core.c
+++ b/drivers/usb/cdns3/core.c
@@ -321,6 +321,7 @@ static int cdns3_probe(struct cdns3 *cdns)
{
struct udevice *dev = cdns->dev;
int ret;
+ int mode = PHY_MODE_INVALID;
Please swap ret and mode to keep this list sorted.
cdns->xhci_regs = dev_remap_addr_name(dev, "xhci");
if (!cdns->xhci_regs)
@@ -372,6 +373,22 @@ static int cdns3_probe(struct cdns3 *cdns)
if (ret)
return ret;
+ if (cdns->dr_mode == USB_DR_MODE_HOST)
+ mode = PHY_MODE_USB_HOST;
+ else if (cdns->dr_mode == USB_DR_MODE_PERIPHERAL)
+ mode = PHY_MODE_USB_DEVICE;
+ else if (cdns->dr_mode == USB_DR_MODE_OTG)
+ mode = PHY_MODE_USB_OTG;
+
+ if (mode != PHY_MODE_INVALID) {
Better invert the condition this way to reduce indent:
if (mode == PHY_MODE_INVALID) {
dev_err(...report the error...);
return ret;
}
ret = generic_phy_set...
+ ret = generic_phy_set_mode(>usb2_phy, mode, 0);
+ if (ret)
+ return ret;
+ ret = generic_phy_set_mode(>usb3_phy, mode, 0);
+ if (ret)
+ return ret;
+ }
+
dev_dbg(dev, "Cadence USB3 core: probe succeed\n");
return 0;
Re: [PATCH v2 1/1] net: dwc_eth_qos: mdio: Implement clause 45
On 5/7/24 11:42 AM, Philip Oberfichtner wrote: Bevor this commit, only clause 22 access was possible. After this commit, clause 45 direct access will available as well. Note that there is a slight change of behavior: Before this commit, the C45E bit was set to whatever value was left in the register from the previous access. After this commit, we adopt the common practice of discerning C45 from C22 using the devad argument. Signed-off-by: Philip Oberfichtner --- Notes: Attention: There is a slight change of behavior introduced by this commit (see commit message). Please test and review if this works for everybody. My implementation is tested on an Intel Elkhart lake SOC, patch submitted here: https://patchwork.ozlabs.org/project/uboot/list/?series=405358 Changes in V2: - Use FIELD_PREP() instead of manual '<<' shifting - Fix whitespace errors Reviewed-by: Marek Vasut
Re: [PATCH] imx: hab: add documentation about the required keys/certs
On 5/7/24 3:06 PM, Claudius Heine wrote:
For CST to find the certificates and keys for signing, some keys and
certs need to be copied into the u-boot build directory.
Make sure to CC "NXP i.MX U-Boot Team" , else NXP is not informed. Use
scripts/get_maintainer to get the full list or just reuse the CC list
from patches in this thread.
diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
index ce1de659d8..42214df21a 100644
--- a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
+++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
@@ -144,6 +144,22 @@ The signing is activated by wrapping SPL and fitImage
sections into nxp-imx8mcst
etype, which is done automatically in arch/arm/dts/imx8m{m,n,p,q}-u-boot.dtsi
in case CONFIG_IMX_HAB Kconfig symbol is enabled.
+Per default the HAB keys and certificates need to be located in the build
+directory, this means copying the following files from the HAB keys directory
+flat (e.g. removing the `keys` and `cert` subdirectory) into the u-boot build
+directory for the CST Code Signing Tool to locate them:
Do symlink(s) work too ?
+- `crts/SRK_1_2_3_4_table.bin`
+- `crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem`
+- `keys/CSF1_1_sha256_4096_65537_v3_usr_key.pem`
+- `crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem`
+- `keys/IMG1_1_sha256_4096_65537_v3_usr_key.pem`
+- `keys/key_pass.txt`
+
+The paths to the SRK table and the certificates can be modified via changes to
+the nxp_imx8mcst device tree node
"nodes", plural, there are two, one for SPL and one for fitImage.
It would be good to mention the DT properties which govern the crypto
material paths -- nxp,srk-table, nxp,csf-crt, nxp,img-crt -- somewhere
around this sentence.
Re: [PATCH v2 1/4] binman: Add nxp_imx8mcst etype for i.MX8M flash.bin signing
On 5/6/24 1:52 PM, Francesco Dolcini wrote: Hello Marek, On Fri, May 03, 2024 at 03:05:09AM +0200, Marek Vasut wrote: Add new binman etype which allows signing both the SPL and fitImage sections of i.MX8M flash.bin using CST. There are multiple DT properties which govern the signing process, nxp,loader-address is the only mandatory one which sets the SPL signature start address without the imx8mimage header, this should be SPL text base. The key material can be configured using optional DT properties nxp,srk-table, nxp,csf-crt, nxp,img-crt, all of which default the key material names generated by CST tool scripts. The nxp,unlock property can be used to unlock CAAM access in SPL section. Signed-off-by: Marek Vasut I was not able to test or really look into your series [1], however I can relate with a comment from Tim Harvey. I think is important to keep in mind that that signing cannot be done with key material that is in-tree, because well, that's private, and I think we should not force people to branch to properly sign the binaries. I think that it would be valuable to share how do you foresee this used in a real environment. I am open to discussion, really. Currently the most basic approach is implemented -- plug in key material either by copying it into build directory, or creating a symlink, or adjusting the DT to specify full path to key material. I am sure this can be expanded to cover other use cases ?
[PATCH v2 4/4] imx: hab: Use nxp_imx8mcst etype for i.MX8M flash.bin signing
Update documentation and use nxp_imx8mcst binman etype for signing
of flash.bin instead of previous horrible shell scripting.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
V2: Document the automatic signing in case CONFIG_IMX_HAB is enabled
---
doc/imx/habv4/csf_examples/mx8m/csf.sh| 92
doc/imx/habv4/csf_examples/mx8m/csf_fit.txt | 30 --
doc/imx/habv4/csf_examples/mx8m/csf_spl.txt | 33 --
doc/imx/habv4/guides/mx8m_spl_secure_boot.txt | 100 +++---
4 files changed, 14 insertions(+), 241 deletions(-)
delete mode 100644 doc/imx/habv4/csf_examples/mx8m/csf.sh
delete mode 100644 doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
delete mode 100644 doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh
b/doc/imx/habv4/csf_examples/mx8m/csf.sh
deleted file mode 100644
index cd3b2614a2f..000
--- a/doc/imx/habv4/csf_examples/mx8m/csf.sh
+++ /dev/null
@@ -1,92 +0,0 @@
-#!/bin/sh
-
-# 0) Generate keys
-#
-# WARNING: ECDSA keys are only supported by HAB 4.5 and newer (i.e. i.MX8M
Plus)
-#
-# cd /path/to/cst-3.3.1/keys/
-#./hab4_pki_tree.sh -existing-ca n -use-ecc n -kl 4096 -duration 10
-num-srk 4 -srk-ca y
-# cd /path/to/cst-3.3.1/crts/
-# ../linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e
SRK_1_2_3_4_fuse.bin -d sha256 -c
./SRK1_sha256_4096_65537_v3_ca_crt.pem,./SRK2_sha256_4096_65537_v3_ca_crt.pem,./SRK3_sha256_4096_65537_v3_ca_crt.pem,./SRK4_sha256_4096_65537_v3_ca_crt.pem
-f 1
-
-# 1) Build U-Boot (e.g. for i.MX8MM)
-#
-# cp -Lv /path/to/arm-trusted-firmware/build/imx8mm/release/bl31.bin .
-# cp -Lv /path/to/firmware-imx-8.14/firmware/ddr/synopsys/ddr3* .
-# make -j imx8mm_board_defconfig
-# make -j`nproc` flash.bin
-
-# 2) Sign SPL and DRAM blobs
-
-cp doc/imx/habv4/csf_examples/mx8m/csf_spl.txt csf_spl.tmp
-cp doc/imx/habv4/csf_examples/mx8m/csf_fit.txt csf_fit.tmp
-
-# update File Paths from env vars
-if ! [ -r $CSF_KEY ]; then
- echo "Error: \$CSF_KEY not found"
- exit 1
-fi
-if ! [ -r $IMG_KEY ]; then
- echo "Error: \$IMG_KEY not found"
- exit 1
-fi
-if ! [ -r $SRK_TABLE ]; then
- echo "Error: \$SRK_TABLE not found"
- exit 1
-fi
-sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_spl.tmp
-sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_spl.tmp
-sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_spl.tmp
-sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_fit.tmp
-sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_fit.tmp
-sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_fit.tmp
-
-# update SPL Blocks
-spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p"
.config) - 0x40)) )
-spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin))
-sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size
\"flash.bin\"@" csf_spl.tmp
-
-# Generate CSF blob
-cst -i csf_spl.tmp -o csf_spl.bin
-
-# Patch CSF blob into flash.bin
-spl_csf_offset=$(xxd -s 24 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_bin_offset=$(xxd -s 4 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_dd_offset=$((${spl_csf_offset} - ${spl_bin_offset} + 0x40))
-dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
-
-# 3) Sign u-boot.itb
-
-# fitImage
-fit_block_base=$(printf "0x%x" $(sed -n "/CONFIG_SPL_LOAD_FIT_ADDRESS=/
s@.*=@@p" .config) )
-fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb
/binman/imx-boot/uboot offset))
-fit_block_size=$(printf "0x%x" $(( ( ( $(stat -tc %s u-boot.itb) + 0x1000 -
0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
-sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset
$fit_block_size \"flash.bin\"@" csf_fit.tmp
-
-# IVT
-ivt_ptr_base=$(printf "%08x" ${fit_block_base} | sed
"s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} -
0x20 )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) |
sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20))
-csf_block_offset=$((${ivt_block_offset} + 0x20))
-
-echo "0xd1002041 ${ivt_block_base} 0x 0x 0x
${ivt_block_base} ${csf_block_base} 0x" | xxd -r -p > ivt.bin
-dd if=ivt.bin of=flash.bin bs=1 seek=${iv
[PATCH v2 3/4] ARM: dts: imx: Wrap i.MX8M binman SPL and FIT nodes in CST node if IMX_HAB enabled
In case CONFIG_IMX_HAB is enabled, extend the binman image description for
all of i.MX8M{Q,M,N,P} with CST wrapper node. This way, if CONFIG_IMX_HAB
is enabled, binman will be automatically used to sign SPL and fitImage.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
V2: New patch
---
arch/arm/dts/imx8mm-u-boot.dtsi | 195 -
arch/arm/dts/imx8mn-u-boot.dtsi | 209 ++--
arch/arm/dts/imx8mp-u-boot.dtsi | 172 ++
arch/arm/dts/imx8mq-u-boot.dtsi | 182 ++-
4 files changed, 424 insertions(+), 334 deletions(-)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index b9b1193823a..c02e11def5f 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -54,126 +54,151 @@
};
#endif
- binman_imx_spl: nxp-imx8mimage {
- filename = "u-boot-spl-mkimage.bin";
- nxp,boot-from = "sd";
- nxp,rom-version = <1>;
+#ifdef CONFIG_IMX_HAB
+ nxp-imx8mcst@0 {
+ filename = "u-boot-spl-mkimage.signed.bin";
nxp,loader-address = ;
+ nxp,unlock;
args; /* Needed by mkimage etype superclass */
+#endif
- section {
- align = <4>;
- align-size = <4>;
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
-
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
+ binman_imx_spl: nxp-imx8mimage {
+ filename = "u-boot-spl-mkimage.bin";
+ nxp,boot-from = "sd";
+ nxp,rom-version = <1>;
+ nxp,loader-address = ;
+ args; /* Needed by mkimage etype superclass */
+
+ section {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
- ddr-1d-imem-fw {
- filename =
"lpddr4_pmu_train_1d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-1d-imem-fw {
+ filename =
"lpddr4_pmu_train_1d_imem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-1d-dmem-fw {
- filename =
"lpddr4_pmu_train_1d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-1d-dmem-fw {
+ filename =
"lpddr4_pmu_train_1d_dmem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- ddr-2d-imem-fw {
- filename =
"lpddr4_pmu_train_2d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ ddr-2d-imem-fw {
+
[PATCH v2 2/4] ARM: dts: imx: Introduce SPL and FIT labels to i.MX8M DTs binman nodes
Add binman_imx_spl and binman_imx_fit labels to nxp-imx8mimage {} and fit {}
nodes respectively, so they can be referened in board DTs no matter how deep
in the top level binman image description they are. Update current board DTs
to use those labels.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
V2: New patch
---
arch/arm/dts/imx8mm-u-boot.dtsi | 4 +-
.../dts/imx8mm-verdin-wifi-dev-u-boot.dtsi| 8 +-
arch/arm/dts/imx8mn-u-boot.dtsi | 4 +-
arch/arm/dts/imx8mp-dhcom-u-boot.dtsi | 124 +-
arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi| 26 ++--
arch/arm/dts/imx8mp-u-boot.dtsi | 4 +-
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi| 10 +-
arch/arm/dts/imx8mq-u-boot.dtsi | 4 +-
8 files changed, 84 insertions(+), 100 deletions(-)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 6ab8f66256e..b9b1193823a 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -54,7 +54,7 @@
};
#endif
- nxp-imx8mimage {
+ binman_imx_spl: nxp-imx8mimage {
filename = "u-boot-spl-mkimage.bin";
nxp,boot-from = "sd";
nxp,rom-version = <1>;
@@ -98,7 +98,7 @@
};
};
- fit {
+ binman_imx_fit: fit {
description = "Configuration to load ATF before U-Boot";
#ifndef CONFIG_IMX_HAB
fit,external-offset = ;
diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
index 90183aff8bc..183de46f66a 100644
--- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
@@ -35,12 +35,8 @@
bootph-pre-ram;
};
- {
- section {
- fit {
- offset = <0x5fc00>;
- };
- };
+_imx_fit {
+ offset = <0x5fc00>;
};
{
diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi
index ba9967dbe4a..c9fb33cfb73 100644
--- a/arch/arm/dts/imx8mn-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-u-boot.dtsi
@@ -103,7 +103,7 @@
};
#endif
- nxp-imx8mimage {
+ binman_imx_spl: nxp-imx8mimage {
filename = "u-boot-spl-mkimage.bin";
nxp,boot-from = "sd";
nxp,rom-version = <2>;
@@ -169,7 +169,7 @@
};
};
- fit {
+ binman_imx_fit: fit {
description = "Configuration to load ATF before U-Boot";
#ifndef CONFIG_IMX_HAB
fit,external-offset = ;
diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
index cb37e28f28f..c065fb82994 100644
--- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
@@ -135,73 +135,69 @@
bootph-pre-ram;
};
- {
- section {
- fit {
- images {
- fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast {
- description =
"imx8mp-dhcom-som-overlay-eth1xfast";
- type = "flat_dt";
- compression = "none";
-
- blob-ext {
- filename =
"imx8mp-dhcom-som-overlay-eth1xfast.dtbo";
- };
- };
-
- fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast {
- description =
"imx8mp-dhcom-som-overlay-eth2xfast";
- type = "flat_dt";
- compression = "none";
-
- blob-ext {
- filename =
"imx8mp-dhcom-som-overlay-eth2xfast.dtbo";
- };
- };
-
- fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast {
- description =
"imx8mp-dhcom-pdk-overlay-eth2xfast";
- type
[PATCH v2 1/4] binman: Add nxp_imx8mcst etype for i.MX8M flash.bin signing
Add new binman etype which allows signing both the SPL and fitImage sections
of i.MX8M flash.bin using CST. There are multiple DT properties which govern
the signing process, nxp,loader-address is the only mandatory one which sets
the SPL signature start address without the imx8mimage header, this should be
SPL text base. The key material can be configured using optional DT properties
nxp,srk-table, nxp,csf-crt, nxp,img-crt, all of which default the key material
names generated by CST tool scripts. The nxp,unlock property can be used to
unlock CAAM access in SPL section.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
V2: - Use configparser module for generating the configuration INI file
- Use config template as an input, parse it, modify only keys of interest
- Pull magic values into top level variables
- Rename nxp,csf-key and nxp,img-key to nxp,csf-crt and nxp,img-crt
- Return unmodified data if signing unrecognized (non-SPL/non-FIT) section
---
tools/binman/btool/cst.py | 48 +
tools/binman/etype/nxp_imx8mcst.py | 163 +
2 files changed, 211 insertions(+)
create mode 100644 tools/binman/btool/cst.py
create mode 100644 tools/binman/etype/nxp_imx8mcst.py
diff --git a/tools/binman/btool/cst.py b/tools/binman/btool/cst.py
new file mode 100644
index 000..30e78bdbbd9
--- /dev/null
+++ b/tools/binman/btool/cst.py
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2024 Marek Vasut
+#
+"""Bintool implementation for cst"""
+
+import re
+
+from binman import bintool
+
+class Bintoolcst(bintool.Bintool):
+"""Image generation for U-Boot
+
+This bintool supports running `cst` with some basic parameters as
+needed by binman.
+"""
+def __init__(self, name):
+super().__init__(name, 'Sign NXP i.MX image')
+
+# pylint: disable=R0913
+def run(self, output_fname=None):
+"""Run cst
+
+Args:
+output_fname: Output filename to write to
+"""
+args = []
+if output_fname:
+args += ['-o', output_fname]
+return self.run_cmd(*args)
+
+def fetch(self, method):
+"""Fetch handler for cst
+
+This installs cst using the apt utility.
+
+Args:
+method (FETCH_...): Method to use
+
+Returns:
+True if the file was fetched and now installed, None if a method
+other than FETCH_BIN was requested
+
+Raises:
+Valuerror: Fetching could not be completed
+"""
+if method != bintool.FETCH_BIN:
+return None
+return self.apt_install('imx-code-signing-tool')
diff --git a/tools/binman/etype/nxp_imx8mcst.py
b/tools/binman/etype/nxp_imx8mcst.py
new file mode 100644
index 000..132127ad482
--- /dev/null
+++ b/tools/binman/etype/nxp_imx8mcst.py
@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023-2024 Marek Vasut
+# Written with much help from Simon Glass
+#
+# Entry-type module for generating the i.MX8M code signing tool
+# input configuration file and invocation of cst on generated
+# input configuration file and input data to be signed.
+#
+
+import configparser
+import struct
+
+from collections import OrderedDict
+
+from binman.entry import Entry
+from binman.etype.mkimage import Entry_mkimage
+from binman.etype.section import Entry_section
+from binman import elf
+from dtoc import fdt_util
+from u_boot_pylib import tools
+
+MAGIC_NXP_IMX_IVT = 0x412000d1
+MAGIC_FITIMAGE= 0xedfe0dd0
+
+csf_config_template = """
+[Header]
+ Version = 4.3
+ Hash Algorithm = sha256
+ Engine = CAAM
+ Engine Configuration = 0
+ Certificate Format = X509
+ Signature Format = CMS
+
+[Install SRK]
+ File = "SRK_1_2_3_4_table.bin"
+ Source index = 0
+
+[Install CSFK]
+ File = "CSF1_1_sha256_4096_65537_v3_usr_crt.pem"
+
+[Authenticate CSF]
+
+[Unlock]
+ Engine = CAAM
+ Features = MID
+
+[Install Key]
+ Verification index = 0
+ Target Index = 2
+ File = "IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
+
+[Authenticate Data]
+ Verification index = 2
+ Blocks = 0x1234 0x78 0xabcd "data.bin"
+"""
+
+class Entry_nxp_imx8mcst(Entry_mkimage):
+"""NXP i.MX8M CST .cfg file generator and cst invoker
+
+Properties / Entry arguments:
+- nxp,loader-address - loader address (SPL text base)
+"""
+
+def __init__(self, s
Re: [PATCH] ARM: imx: Enable kaslrseed command on DH i.MX8M Plus DHCOM
On 4/29/24 10:52 PM, Tim Harvey wrote:
On Mon, Apr 29, 2024 at 1:51 PM Marek Vasut wrote:
On 4/29/24 9:10 PM, Tim Harvey wrote:
On Tue, Apr 23, 2024 at 4:18 PM Marek Vasut wrote:
On 4/19/24 5:24 PM, Tim Harvey wrote:
On Thu, Apr 18, 2024 at 11:42 AM Marek Vasut wrote:
On 4/18/24 8:02 PM, Fabio Estevam wrote:
Hi Tim,
On Thu, Apr 18, 2024 at 2:54 PM Tim Harvey wrote:
Fabio, if you enable CONFIG_DM_RNG on an imx8m{m,p}_evk do you get the
following in the SPL?
Couldn't bind rng driver (-96)
SEC0: RNG instantiated
sec_init failed!
Yes, if I add CONFIG_DM_RNG=y to imx8mm_evk_defconfig I get:
U-Boot SPL 2024.04-00793-g3434b88d2c2f-dirty (Apr 18 2024 - 14:58:57 -0300)
No pmic
Couldn't bind rng driver (-96)
SEC0: RNG instantiated
sec_init failed!
Interesting. Which TFA blob version do you use ? I used the mainline
2.10 for my tests.
Marek,
Were you able to reproduce this as well with the board you enabled
DM_RNG for? If it does work fine what dtb were you using... perhaps
there is something in its u-boot.dtsi that we need?
This one arch/arm/dts/imx8mp-dhcom-pdk3.dts , see log below. The build
has a few extra patches in it, but nothing which affects the KASLR:
$ export SOURCE_DATE_EPOCH=1672531200 ; echo tst > .scmversion
$ make imx8mp_dhcom_pdk3_defconfig ; make
U-Boot SPL 2024.07-rc1tst (Jan 01 2023 - 00:00:00 +)
DDR: 4096 MiB [0x5]
DDR: Inline ECC enabled
WDT: Started watchdog@3028 with servicing every 1000ms (60s timeout)
Trying to boot from BOOTROM
Boot Stage: Primary boot
image offset 0x1000, pagesize 0x1, ivt offset 0x0
NOTICE: Do not release JR0 to NS as it can be used by HAB
NOTICE: BL31: v2.10.0 (release):v2.10.0-5-gfb51ca229
NOTICE: BL31: Built : 20:30:36, Apr 23 2024
U-Boot 2024.07-rc1tst (Jan 01 2023 - 00:00:00 +)
CPU: Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 70C
Reset cause: POR
Model: DH electronics i.MX8M Plus DHCOM Premium Developer Kit (3)
DRAM: 3.5 GiB
Core: 183 devices, 34 uclasses, devicetree: separate
WDT: Started watchdog@3028 with servicing every 1000ms (60s timeout)
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from SPIFlash... SF: Detected w25q128jw with page
size 256 Bytes, erase size 4 KiB, total 16 MiB
OK
In:serial
Out: serial
Err: serial
SEC0: RNG instantiated
Net: eth1: ethernet@30be, eth0: ethernet@30bf
...
The error -EPFNOSUPPORT is interesting and helps point to the only
place it can be where the comment says the strange errno is to make
this easier to find:
https://elixir.bootlin.com/u-boot/latest/source/drivers/core/uclass.c#L70:
if (!uc_drv) {
debug("Cannot find uclass for id %d: please add the
UCLASS_DRIVER() declaration for this UCLASS_... id\n",
id);
/*
* Use a strange error to make this case easier to find. When
* a uclass is not available it can prevent driver model from
* starting up and this failure is otherwise hard to debug.
*/
return -EPFNOSUPPORT;
}
I'm not very familiar with the dm driver binding - does the
U-BOOT_DRIVER usage in drivers/crypto/fsl/rng.c need to be refactored
to use UCLASS_DRIVER for it to be usable in both SPL and U-Boot?
I don't think you need the CAAM RNG in SPL in the first place, or do you ?
Honestly I don't know why we need DM_RNG in SPL anyway and we could
just add support for disabling it there to avoid unwanted bloat.
I think you can disable it , yes.
Marek,
Would it be advantageous for the kaslr-seed to be added automatically
from image_setup_libfdt?
Yes, can you prepare a patch ? (I wanted to do this, just haven't had
the time)
I notice arch/arm/cpu/armv8/fsl-layerscape/fdt.c:ft_cpu_setup does
this and board/raspberrypi/rpi/rpi.c looks like it copies kaslr-seed
from the control fdt which I assume was added by an earlier layer for
that target.
Right, exactly, this .
I'm not clear if there is a disadvantage to automatically adding this
node if DM_RNG is enabled.
I would say, add it.
Yes, I'll submit something this week.
Thank you, much appreciated.
Re: [PATCH v4] mmc: Poll CD in case cyclic framework is enabled
On 4/30/24 12:36 AM, Jaehoon Chung wrote: -Original Message- From: Marek Vasut Sent: Friday, April 26, 2024 8:41 PM To: Jaehoon Chung ; u-boot@lists.denx.de Cc: 'Peng Fan' ; 'Simon Glass' Subject: Re: [PATCH v4] mmc: Poll CD in case cyclic framework is enabled On 4/26/24 8:27 AM, Jaehoon Chung wrote: Dear Marek, -Original Message- From: Marek Vasut Sent: Wednesday, April 24, 2024 8:18 AM To: u-boot@lists.denx.de; Jaehoon Chung Cc: Peng Fan ; Simon Glass Subject: Re: [PATCH v4] mmc: Poll CD in case cyclic framework is enabled On 3/16/24 9:13 PM, Marek Vasut wrote: In case the cyclic framework is enabled, poll the card detect of already initialized cards and deinitialize them in case they are removed. Since the card initialization is a longer process and card initialization is done on first access to an uninitialized card anyway, avoid initializing newly detected uninitialized cards in the cyclic callback. Any input on this ? When I have applied your patch from patchwork, it didn't apply directly. If you're ok, I will apply after touch your patch. Is it ok? Sure. After touching your patch, I will inform again to you. btw. what is the problem with the patch ?
Re: [PATCH v3] mmc: allow use of hardware partition names for mmc partconf
On 4/29/24 6:48 PM, Tim Harvey wrote:
On Sat, Apr 27, 2024 at 4:20 PM Marek Vasut wrote:
On 4/27/24 2:11 AM, Tim Harvey wrote:
[...]
diff --git a/include/mmc.h b/include/mmc.h
index 4b8327f1f93b..7243bd761202 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -381,6 +381,21 @@ enum mmc_voltage {
#define MMC_TIMING_MMC_HS2009
#define MMC_TIMING_MMC_HS40010
+/* emmc hardware partition values */
+enum emmc_hwpart {
+ EMMC_HWPART_DEFAULT = 0,
One more thing ... eMMC hardware partition 0 and 7 are both referring to
USER HW partition. Have a look at the git log, there have been patches
which handled this case in the MMC subsystem from about a year ago.
Hi Marek,
I can't find what you are referring to. I assume you are talking about
calling the first name something other than 'user' as technically it's
not (but it gets treated as user).
Can you find the commit or discussion you are thinking about?
It seems this whole thing is much older:
7dbe63bc950b ("SPL: Add CONFIG_SUPPORT_EMMC_BOOT support to
CONFIG_SPL_FRAMEWORK")
+* We need to check what the partition is configured to.
+* 1 and 2 match up to boot0 / boot1 and 7 is user data
+* which is the first physical partition (0).
+*/
+ int part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
+
+ if (part == 7)
+ part = 0;
Re: [PATCH] ARM: imx: Enable kaslrseed command on DH i.MX8M Plus DHCOM
On 4/29/24 9:10 PM, Tim Harvey wrote:
On Tue, Apr 23, 2024 at 4:18 PM Marek Vasut wrote:
On 4/19/24 5:24 PM, Tim Harvey wrote:
On Thu, Apr 18, 2024 at 11:42 AM Marek Vasut wrote:
On 4/18/24 8:02 PM, Fabio Estevam wrote:
Hi Tim,
On Thu, Apr 18, 2024 at 2:54 PM Tim Harvey wrote:
Fabio, if you enable CONFIG_DM_RNG on an imx8m{m,p}_evk do you get the
following in the SPL?
Couldn't bind rng driver (-96)
SEC0: RNG instantiated
sec_init failed!
Yes, if I add CONFIG_DM_RNG=y to imx8mm_evk_defconfig I get:
U-Boot SPL 2024.04-00793-g3434b88d2c2f-dirty (Apr 18 2024 - 14:58:57 -0300)
No pmic
Couldn't bind rng driver (-96)
SEC0: RNG instantiated
sec_init failed!
Interesting. Which TFA blob version do you use ? I used the mainline
2.10 for my tests.
Marek,
Were you able to reproduce this as well with the board you enabled
DM_RNG for? If it does work fine what dtb were you using... perhaps
there is something in its u-boot.dtsi that we need?
This one arch/arm/dts/imx8mp-dhcom-pdk3.dts , see log below. The build
has a few extra patches in it, but nothing which affects the KASLR:
$ export SOURCE_DATE_EPOCH=1672531200 ; echo tst > .scmversion
$ make imx8mp_dhcom_pdk3_defconfig ; make
U-Boot SPL 2024.07-rc1tst (Jan 01 2023 - 00:00:00 +)
DDR: 4096 MiB [0x5]
DDR: Inline ECC enabled
WDT: Started watchdog@3028 with servicing every 1000ms (60s timeout)
Trying to boot from BOOTROM
Boot Stage: Primary boot
image offset 0x1000, pagesize 0x1, ivt offset 0x0
NOTICE: Do not release JR0 to NS as it can be used by HAB
NOTICE: BL31: v2.10.0 (release):v2.10.0-5-gfb51ca229
NOTICE: BL31: Built : 20:30:36, Apr 23 2024
U-Boot 2024.07-rc1tst (Jan 01 2023 - 00:00:00 +)
CPU: Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 70C
Reset cause: POR
Model: DH electronics i.MX8M Plus DHCOM Premium Developer Kit (3)
DRAM: 3.5 GiB
Core: 183 devices, 34 uclasses, devicetree: separate
WDT: Started watchdog@3028 with servicing every 1000ms (60s timeout)
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from SPIFlash... SF: Detected w25q128jw with page
size 256 Bytes, erase size 4 KiB, total 16 MiB
OK
In:serial
Out: serial
Err: serial
SEC0: RNG instantiated
Net: eth1: ethernet@30be, eth0: ethernet@30bf
...
The error -EPFNOSUPPORT is interesting and helps point to the only
place it can be where the comment says the strange errno is to make
this easier to find:
https://elixir.bootlin.com/u-boot/latest/source/drivers/core/uclass.c#L70:
if (!uc_drv) {
debug("Cannot find uclass for id %d: please add the
UCLASS_DRIVER() declaration for this UCLASS_... id\n",
id);
/*
* Use a strange error to make this case easier to find. When
* a uclass is not available it can prevent driver model from
* starting up and this failure is otherwise hard to debug.
*/
return -EPFNOSUPPORT;
}
I'm not very familiar with the dm driver binding - does the
U-BOOT_DRIVER usage in drivers/crypto/fsl/rng.c need to be refactored
to use UCLASS_DRIVER for it to be usable in both SPL and U-Boot?
I don't think you need the CAAM RNG in SPL in the first place, or do you ?
Honestly I don't know why we need DM_RNG in SPL anyway and we could
just add support for disabling it there to avoid unwanted bloat.
I think you can disable it , yes.
Marek,
Would it be advantageous for the kaslr-seed to be added automatically
from image_setup_libfdt?
Yes, can you prepare a patch ? (I wanted to do this, just haven't had
the time)
I notice arch/arm/cpu/armv8/fsl-layerscape/fdt.c:ft_cpu_setup does
this and board/raspberrypi/rpi/rpi.c looks like it copies kaslr-seed
from the control fdt which I assume was added by an earlier layer for
that target.
Right, exactly, this .
I'm not clear if there is a disadvantage to automatically adding this
node if DM_RNG is enabled.
I would say, add it.
Re: [EXT] Re: [PATCH 2/3] crypto/fsl: Introduce SPL_FSL_CAAM_RNG
On 4/29/24 11:02 AM, Gaurav Jain wrote: Hi, diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index 7a2543e16cc..4fbce519a0b 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -6,6 +6,6 @@ obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o obj-$(CONFIG_CMD_BLOB)$(CONFIG_IMX_CAAM_DEK_ENCAP) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o -obj-$(CONFIG_FSL_CAAM_RNG) += rng.o +obj-$(CONFIG_$(SPL_TPL_)FSL_CAAM_RNG) += rng.o obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o -- 2.43.0 Marek, Hi, Thanks - this series does solve the issue I am seeing in the SPL when enabling DM_RNG. Is this going to cause an issue for people who expect it to be currently enabled and now have to manually enable it? That's a good question. If I do '$ git grep FSL_CAAM_RNG' , there seem to be no users, so I don't think we need to worry here, right ? With SPL_DM_RNG i.e. 1/3 I am a bit more concerned. But, looking at the users that enable DM_RNG, I am not seeing any obvious ones that would require SPL_DM_RNG too. What do you think ? FSL_CAAM_RNG is enabled based on DM_RNG. This patch will disable the build of drivers/crypto/fsl/rng.c in SPL. Is that actually a problem for any supported platform ? (that is what is being discussed in this thread already)
Re: [PATCH v3] mmc: allow use of hardware partition names for mmc partconf
On 4/27/24 2:11 AM, Tim Harvey wrote:
[...]
diff --git a/include/mmc.h b/include/mmc.h
index 4b8327f1f93b..7243bd761202 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -381,6 +381,21 @@ enum mmc_voltage {
#define MMC_TIMING_MMC_HS200 9
#define MMC_TIMING_MMC_HS400 10
+/* emmc hardware partition values */
+enum emmc_hwpart {
+ EMMC_HWPART_DEFAULT = 0,
One more thing ... eMMC hardware partition 0 and 7 are both referring to
USER HW partition. Have a look at the git log, there have been patches
which handled this case in the MMC subsystem from about a year ago.
+ EMMC_HWPART_BOOT0 = 1,
+ EMMC_HWPART_BOOT1 = 2,
+ EMMC_HWPART_GP1 = 3,
+ EMMC_HWPART_GP2 = 4,
+ EMMC_HWPART_GP3 = 5,
+ EMMC_HWPART_GP4 = 6,
+ EMMC_HWPART_USER = 7,
[...]
Re: [PATCH v3] mmc: allow use of hardware partition names for mmc partconf
On 4/27/24 2:06 PM, E Shattow wrote:
On Sat, Apr 27, 2024 at 3:22 AM Marek Vasut wrote:
On 4/27/24 3:29 AM, E Shattow wrote:
Hi Marek,
On Fri, Apr 26, 2024 at 5:49 PM Marek Vasut wrote:
[...]
diff --git a/include/mmc.h b/include/mmc.h
index 4b8327f1f93b..7243bd761202 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -381,6 +381,21 @@ enum mmc_voltage {
#define MMC_TIMING_MMC_HS2009
#define MMC_TIMING_MMC_HS40010
+/* emmc hardware partition values */
+enum emmc_hwpart {
+ EMMC_HWPART_DEFAULT = 0,
+ EMMC_HWPART_BOOT0 = 1,
+ EMMC_HWPART_BOOT1 = 2,
+ EMMC_HWPART_GP1 = 3,
+ EMMC_HWPART_GP2 = 4,
+ EMMC_HWPART_GP3 = 5,
+ EMMC_HWPART_GP4 = 6,
+ EMMC_HWPART_USER = 7,
+};
+
+/* emmc hardware partition names */
+extern const char *emmc_hwpart_names[];
Maybe the array should have fixed size here, i.e. 8 ?
Is there an ABI reason to do so? Can you explain further why it would
be needed to do that?
It has nothing to do with ABI, it is only to let the compiler validate
that nobody would index the array with index > 7 by accident.
At least GCC knows this without doing its work again ourselves. How
about a const for the upper limit, where currently EMMC_HWPART_USER
substitutes for expressing an upper limit? You may as well be writing
EMMC_HWPART_MAX = 8 in the enum and using that for the initializer
also any iterators with a less-than condition to make it more
expressive.
You could use ARRAY_SIZE(emmc_hwpart_names) in iterators, no extra
symbols should be necessary.
$ gcc -o testobj test.c -Wall -Wextra -O2
test.c: In function ‘main’:
test.c:16:5: warning: array subscript 8 is above array bounds of
‘const char *[8]’ [-Warray-bounds=]
16 | printf(emmc_hwpart_names[8]);
| ^~~~
test.c:3:13: note: while referencing ‘emmc_hwpart_names’
3 | const char *emmc_hwpart_names[] = {
| ^
#include
const char *emmc_hwpart_names[] = {
"user",
"boot0",
"boot1",
"gp1",
"gp2",
"gp3",
"gp4",
"user",
};
int main(int argc, char** argv) {
(void) argc; (void) argv;
printf(emmc_hwpart_names[8]);
return 0;
}
In case of this patched code here, the example is more like this:
a.c:
#include
#include "h.h"
int main(void)
{
printf("%d\n", arr[8]); // This code contains a bug here
return 0;
}
b.c:
int arr[2] = { 1, 2 };
h.h:
extern int arr[];
Compile:
$ gcc -O2 -Wall -c -o a.o a.c
$ gcc -O2 -Wall -c -o b.o b.c
$ gcc -O2 -Wall -o out a.o b.o
You won't get warning when compiling a.c , because gcc does not know the
size of the array until the linking step. You will get a warning if you
change the header like this:
h.h:
-extern int arr[];
+extern int arr[2];
[PATCH v2 2/2] ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board
This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on
STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC
carrier board.
The SoM contains the following peripherals:
- STPMIC (power delivery)
- 512MB DDR3L memory
- eMMC and SDIO WiFi module
The DHSBC carrier board contains the following peripherals:
- Two RGMII Ethernet ports
- USB-A Host port, USB-C peripheral port, USB-C power supply plug
- Expansion connector
Reviewed-by: Patrice Chotard
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
V2: Add RB from Patrice
---
arch/arm/dts/Makefile | 1 +
.../dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi | 25 ++
arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts | 383 ++
arch/arm/dts/stm32mp13xx-dhcor-som.dtsi | 308 ++
arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi| 55 +++
configs/stm32mp13_dhcor_defconfig | 148 +++
6 files changed, 920 insertions(+)
create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
create mode 100644 configs/stm32mp13_dhcor_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0c6f0221b77..6d4972827c8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1285,6 +1285,7 @@ dtb-$(CONFIG_ASPEED_AST2600) += \
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP13X) += \
+ stm32mp135f-dhcor-dhsbc.dtb \
stm32mp135f-dk.dtb
dtb-$(CONFIG_STM32MP15X) += \
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
new file mode 100644
index 000..d718aae16ca
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut
+ */
+
+#include "stm32mp13xx-dhcor-u-boot.dtsi"
+
+ {
+ bootph-all;
+};
+
+_pins_b {
+ bootph-all;
+
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
+ {
+ bootph-all;
+};
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
new file mode 100644
index 000..fc1c48ad56d
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut
+ *
+ * DHCOR STM32MP13 variant:
+ * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
+ * DHCOR PCB number: 718-100 or newer
+ * DHSBC PCB number: 719-100 or newer
+ */
+
+/dts-v1/;
+
+#include
+#include "stm32mp135.dtsi"
+#include "stm32mp13xf.dtsi"
+#include "stm32mp13xx-dhcor-som.dtsi"
+
+/ {
+ model = "DH electronics STM32MP135F DHCOR DHSBC";
+ compatible = "dh,stm32mp135f-dhcor-dhsbc",
+"dh,stm32mp135f-dhcor-som",
+"st,stm32mp135";
+
+ aliases {
+ ethernet0 =
+ ethernet1 =
+ serial2 =
+ serial3 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_a _usb_cc_pins_b>;
+ vdda-supply = <_adc>;
+ vref-supply = <_adc>;
+ status = "okay";
+
+ adc1: adc@0 {
+ status = "okay";
+
+ /*
+* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
+* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+* 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+* Use arbitrary margin here (e.g. 5us).
+*
+* The pinmux pins must be set as ANALOG, use datasheet
+* DS13483 Table 7. STM32MP135C/F ball definitions to
+* find out which 'pin name' maps to which 'additional
+* functions', which lists the mapping between pin and
+* ADC channel. In this case, PA5 maps to ADC1_INP2 and
+* PF13 maps to ADC1_INP11 .
+*/
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ channel@11 {
+ reg = <11>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ /* Expansion connector: INP12:pin29 */
+ channel@12 {
+ reg = <12>;
+ st,min-sample-time-ns = <50
[PATCH v2 1/2] ARM: dts: stm32: Add pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board
Add new pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board.
The following pinmux nodes are added:
- ADC pins
- ADC CC pins
- ETH1 pins
- ETH2 pins
- I2C5 pins
- MCAN1 pins
- MCAN2 pins
- PWM13 pins
- PWM5 pins
- QSPI pins
- SAI1 pins
- SDMMC2 D4..D7 pins
- SPI2 pins
- SPI3 pins
- UART4 pins
- UART7 pins
- USART1 pins
- USART2 pins
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
V2: Squash the pinmux patches into one megapatch
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 483
1 file changed, 483 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 27e0c382678..c01d39f03ea 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -6,6 +6,12 @@
#include
{
+ adc1_pins_a: adc1-pins-0 {
+ pins {
+ pinmux = ; /* ADC1 in12 */
+ };
+ };
+
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
pins {
pinmux = , /* ADC1 in6 */
@@ -13,6 +19,104 @@
};
};
+ adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
+ pins {
+ pinmux = , /* ADC1_INP2 */
+; /* ADC1_INP11
*/
+ };
+ };
+
+ eth1_rgmii_pins_a: eth1-rgmii-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+, /* ETH_MDIO */
+; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = , /*
ETH_RGMII_RXD0 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD2 */
+, /*
ETH_RGMII_RXD3 */
+, /*
ETH_RGMII_RX_CTL */
+; /*
ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+
+ };
+
+ eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+, /* ETH_MDIO */
+, /* ETH_MDC */
+, /*
ETH_RGMII_RXD0 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RX_CTL */
+; /*
ETH_RGMII_RX_CLK */
+ };
+ };
+
+ eth2_rgmii_pins_a: eth2-rgmii-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+, /* ETH_MDIO */
+; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = , /*
ETH_RGMII_RXD0 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD2 */
+, /*
ETH_RGMII_RXD3 */
+, /*
ETH_RGMII_RX_CTL */
+; /*
ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+ };
+
+ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+,
Re: [PATCH v3] mmc: allow use of hardware partition names for mmc partconf
On 4/27/24 3:29 AM, E Shattow wrote:
Hi Marek,
On Fri, Apr 26, 2024 at 5:49 PM Marek Vasut wrote:
[...]
diff --git a/include/mmc.h b/include/mmc.h
index 4b8327f1f93b..7243bd761202 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -381,6 +381,21 @@ enum mmc_voltage {
#define MMC_TIMING_MMC_HS2009
#define MMC_TIMING_MMC_HS40010
+/* emmc hardware partition values */
+enum emmc_hwpart {
+ EMMC_HWPART_DEFAULT = 0,
+ EMMC_HWPART_BOOT0 = 1,
+ EMMC_HWPART_BOOT1 = 2,
+ EMMC_HWPART_GP1 = 3,
+ EMMC_HWPART_GP2 = 4,
+ EMMC_HWPART_GP3 = 5,
+ EMMC_HWPART_GP4 = 6,
+ EMMC_HWPART_USER = 7,
+};
+
+/* emmc hardware partition names */
+extern const char *emmc_hwpart_names[];
Maybe the array should have fixed size here, i.e. 8 ?
Is there an ABI reason to do so? Can you explain further why it would
be needed to do that?
It has nothing to do with ABI, it is only to let the compiler validate
that nobody would index the array with index > 7 by accident.
Re: [PATCH v3] mmc: allow use of hardware partition names for mmc partconf
[...]
diff --git a/include/mmc.h b/include/mmc.h
index 4b8327f1f93b..7243bd761202 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -381,6 +381,21 @@ enum mmc_voltage {
#define MMC_TIMING_MMC_HS200 9
#define MMC_TIMING_MMC_HS400 10
+/* emmc hardware partition values */
+enum emmc_hwpart {
+ EMMC_HWPART_DEFAULT = 0,
+ EMMC_HWPART_BOOT0 = 1,
+ EMMC_HWPART_BOOT1 = 2,
+ EMMC_HWPART_GP1 = 3,
+ EMMC_HWPART_GP2 = 4,
+ EMMC_HWPART_GP3 = 5,
+ EMMC_HWPART_GP4 = 6,
+ EMMC_HWPART_USER = 7,
+};
+
+/* emmc hardware partition names */
+extern const char *emmc_hwpart_names[];
Maybe the array should have fixed size here, i.e. 8 ?
Re: [PATCH v2] cmd: mmc: allow use of hardware partition names for mmc partconf
On 4/26/24 7:36 PM, Tim Harvey wrote:
On Fri, Apr 26, 2024 at 10:25 AM Marek Vasut wrote:
On 4/26/24 7:12 PM, Tim Harvey wrote:
eMMC devices have hardware partitions such as user, boot0, and boot1.
Allow these names to be displayed when reading the mmc PARTITION_CONFIG
field via 'mmc partconf'. Additionally allow a name to be specified when
setting the PARTITION_CONFIG.
Before:
u-boot=> mmc partconf 2 1 1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x2
PARTITION_ACCESS: 0x0
After:
u-boot=> mmc partconf 2 1 1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x1 (boot0)
PARTITION_ACCESS: 0x0
u-boot=> mmc partconf 2 1 boot1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x2 (boot1)
PARTITION_ACCESS: 0x0
Signed-off-by: Tim Harvey
---
v2:
- fix typo in subject
- add names for gp1..gp4
---
cmd/mmc.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 2d5430a53079..af9a66cc6df4 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -14,6 +14,18 @@
#include
#include
#include
+#include
+
+static const char *mmc_partnames[] = {
+ "user",
+ "boot0",
+ "boot1",
+ "gp1",
+ "gp2",
+ "gp3",
+ "gp4",
Uh, maybe gp%d are indexed from zero too ?
(sorry for the confusion)
but 'mmc hwpartition' does not list them 0 based:
u-boot=> mmc hwpartition
switch to partitions #0, OK
mmc2(part 0) is current device
Partition configuration:
No enhanced user data area
No GP1 partition
No GP2 partition
No GP3 partition
No GP4 partition
I'm ok with either, I'm just not sure what is more understandable and standard.
Then 1-based counting is OK, thanks for checking !
Re: [PATCH 2/3] crypto/fsl: Introduce SPL_FSL_CAAM_RNG
On 4/26/24 4:39 PM, Heinrich Schuchardt wrote: On 26.04.24 06:03, Marek Vasut wrote: On 4/26/24 2:16 AM, Tim Harvey wrote: diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index 7a2543e16cc..4fbce519a0b 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -6,6 +6,6 @@ obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o obj-$(CONFIG_CMD_BLOB)$(CONFIG_IMX_CAAM_DEK_ENCAP) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o -obj-$(CONFIG_FSL_CAAM_RNG) += rng.o +obj-$(CONFIG_$(SPL_TPL_)FSL_CAAM_RNG) += rng.o obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o -- 2.43.0 Marek, Hi, Thanks - this series does solve the issue I am seeing in the SPL when enabling DM_RNG. Is this going to cause an issue for people who expect it to be currently enabled and now have to manually enable it? That's a good question. If I do '$ git grep FSL_CAAM_RNG' , there seem to be no users, so I don't think we need to worry here, right ? With SPL_DM_RNG i.e. 1/3 I am a bit more concerned. But, looking at the users that enable DM_RNG, I am not seeing any obvious ones that would require SPL_DM_RNG too. What do you think ? Grepping for UCLASS_RNG should find usages. The only possible SPL usage seems to be in net/net_rand.h. Here a fallback to the mac address as seed exists. So this may need to be tested on AM335x with SPL ethernet boot ? +CC Nishanth ?
Re: [PATCH v2] cmd: mmc: allow use of hardware partition names for mmc partconf
On 4/26/24 7:12 PM, Tim Harvey wrote:
eMMC devices have hardware partitions such as user, boot0, and boot1.
Allow these names to be displayed when reading the mmc PARTITION_CONFIG
field via 'mmc partconf'. Additionally allow a name to be specified when
setting the PARTITION_CONFIG.
Before:
u-boot=> mmc partconf 2 1 1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x2
PARTITION_ACCESS: 0x0
After:
u-boot=> mmc partconf 2 1 1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x1 (boot0)
PARTITION_ACCESS: 0x0
u-boot=> mmc partconf 2 1 boot1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x2 (boot1)
PARTITION_ACCESS: 0x0
Signed-off-by: Tim Harvey
---
v2:
- fix typo in subject
- add names for gp1..gp4
---
cmd/mmc.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 2d5430a53079..af9a66cc6df4 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -14,6 +14,18 @@
#include
#include
#include
+#include
+
+static const char *mmc_partnames[] = {
+ "user",
+ "boot0",
+ "boot1",
+ "gp1",
+ "gp2",
+ "gp3",
+ "gp4",
Uh, maybe gp%d are indexed from zero too ?
(sorry for the confusion)
Re: [PATCH 2/2] imx: hab: Use nxp_imx8mcst etype for i.MX8M flash.bin signing
On 4/26/24 6:00 PM, Tom Rini wrote: On Fri, Apr 26, 2024 at 08:56:29AM -0700, Tim Harvey wrote: On Fri, Apr 26, 2024 at 8:51 AM Tom Rini wrote: On Fri, Apr 26, 2024 at 08:30:23AM -0700, Tim Harvey wrote: On Thu, Apr 25, 2024 at 4:07 PM Marek Vasut wrote: Update documentation and use nxp_imx8mcst binman etype for signing of flash.bin instead of previous horrible shell scripting. Hi Marek, To be completely fair we are just replacing a shell script and template file with a python script (tools/binman/etype/nxp_imx8mcst.py) which also creates the template file. I could care less about shell vs python but do put huge value in the idea of making signing easier and doing so without modification of U-Boot code. The current implementation requires a couple of things to be enabled in defconfig which can be done with a seperate 'out-of-tree' defconfig but this new proposed implementation requires changing a u-boot.dtsi which is a tracked file. A counter-point is that with using binman for signing we start eliminating differences between different semiconductors on how to get something signed. Hi Tom, I agree... I'm a huge fan of binman. I just don't want to replace current constructs that use env and/or config items on a clean code directory with replacements that require code diffs to do the same. I'm simply wanting to wrap binman sections with Kconfig items. Is there a way to use environment variables within binman sections (ie to wrap sections or override filenames)? I'm honestly not sure if everyone is happy just yet with how integration and support for production use cases of signing features is integrated with binman just yet. I am sort-of on the fence with the Kconfig option, I did consider it before sending this patch, because we already have #ifdef ...IMX_HAB in that .dtsi file, but we would need new Kconfig option for this and the binman node is starting to be cluttered with ifdeffery. The other option would be to add a wrapper section around both the SPL and FIT nodes, and for signing the type= of the section could be overridden to nxp_mx8mcst , that would work too, but that impact all the non-signing users. So ... thoughts ?
Re: [PATCH] cmd: mmc: allow use of hardware parittion names for mmc partconf
On 4/26/24 5:14 PM, Tim Harvey wrote:
On Thu, Apr 25, 2024 at 9:07 PM Marek Vasut wrote:
On 4/26/24 2:14 AM, Tim Harvey wrote:
eMMC devices have hardware partitions such as user, boot0, and boot1.
Allow these names to be displayed when reading the mmc PARTITION_CONFIG
field via 'mmc partconf'. Additionally allow a name to be specified when
setting the PARTITION_CONFIG.
Before:
u-boot=> mmc partconf 2 1 1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x2
PARTITION_ACCESS: 0x0
After:
u-boot=> mmc partconf 2 1 1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x1 (boot0)
PARTITION_ACCESS: 0x0
u-boot=> mmc partconf 2 1 boot1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x2 (boot1)
PARTITION_ACCESS: 0x0
Signed-off-by: Tim Harvey
---
cmd/mmc.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 2d5430a53079..26692a8e349b 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -14,6 +14,18 @@
#include
#include
#include
+#include
+
+static const char *mmc_partnames[] = {
+ "user",
+ "boot0",
+ "boot1",
+ "",
Shouldn't these be 'gp' partitions here ?
He Marek,
Do you mean that 3-6 should be named 'gp1', 'gp2' etc? I couldn't find
if those values were possible or have meaning.
Yes, General Purpose eMMC hardware partitions.
Re: [PATCH v4] mmc: Poll CD in case cyclic framework is enabled
On 4/26/24 8:27 AM, Jaehoon Chung wrote: Dear Marek, -Original Message- From: Marek Vasut Sent: Wednesday, April 24, 2024 8:18 AM To: u-boot@lists.denx.de; Jaehoon Chung Cc: Peng Fan ; Simon Glass Subject: Re: [PATCH v4] mmc: Poll CD in case cyclic framework is enabled On 3/16/24 9:13 PM, Marek Vasut wrote: In case the cyclic framework is enabled, poll the card detect of already initialized cards and deinitialize them in case they are removed. Since the card initialization is a longer process and card initialization is done on first access to an uninitialized card anyway, avoid initializing newly detected uninitialized cards in the cyclic callback. Any input on this ? When I have applied your patch from patchwork, it didn't apply directly. If you're ok, I will apply after touch your patch. Is it ok? Sure.
Re: [PATCH 01/19] ARM: dts: stm32: Add alternate pinmux for MP13 ADC pins
On 4/26/24 9:49 AM, Patrice CHOTARD wrote:
On 4/22/24 01:16, Marek Vasut wrote:
Add another mux option for ADC pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 27e0c382678..03ded415390 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -6,6 +6,12 @@
#include
{
+ adc1_pins_a: adc1-pins-0 {
+ pins {
+ pinmux = ; /* ADC1 in12 */
+ };
+ };
+
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
pins {
pinmux = , /* ADC1 in6 */
Reviewed-by: Patrice Chotard
I'll be sending a V2 with all the pinmux patches squashed into single patch.
Re: [PATCH] cmd: mmc: allow use of hardware parittion names for mmc partconf
On 4/26/24 2:14 AM, Tim Harvey wrote:
eMMC devices have hardware partitions such as user, boot0, and boot1.
Allow these names to be displayed when reading the mmc PARTITION_CONFIG
field via 'mmc partconf'. Additionally allow a name to be specified when
setting the PARTITION_CONFIG.
Before:
u-boot=> mmc partconf 2 1 1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x2
PARTITION_ACCESS: 0x0
After:
u-boot=> mmc partconf 2 1 1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x1 (boot0)
PARTITION_ACCESS: 0x0
u-boot=> mmc partconf 2 1 boot1 0 && mmc partconf 2
EXT_CSD[179], PARTITION_CONFIG:
BOOT_ACK: 0x1
BOOT_PARTITION_ENABLE: 0x2 (boot1)
PARTITION_ACCESS: 0x0
Signed-off-by: Tim Harvey
---
cmd/mmc.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 2d5430a53079..26692a8e349b 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -14,6 +14,18 @@
#include
#include
#include
+#include
+
+static const char *mmc_partnames[] = {
+ "user",
+ "boot0",
+ "boot1",
+ "",
Shouldn't these be 'gp' partitions here ?
[...]
Re: [PATCH 2/3] crypto/fsl: Introduce SPL_FSL_CAAM_RNG
On 4/26/24 2:16 AM, Tim Harvey wrote: diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index 7a2543e16cc..4fbce519a0b 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -6,6 +6,6 @@ obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o obj-$(CONFIG_CMD_BLOB)$(CONFIG_IMX_CAAM_DEK_ENCAP) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o -obj-$(CONFIG_FSL_CAAM_RNG) += rng.o +obj-$(CONFIG_$(SPL_TPL_)FSL_CAAM_RNG) += rng.o obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o -- 2.43.0 Marek, Hi, Thanks - this series does solve the issue I am seeing in the SPL when enabling DM_RNG. Is this going to cause an issue for people who expect it to be currently enabled and now have to manually enable it? That's a good question. If I do '$ git grep FSL_CAAM_RNG' , there seem to be no users, so I don't think we need to worry here, right ? With SPL_DM_RNG i.e. 1/3 I am a bit more concerned. But, looking at the users that enable DM_RNG, I am not seeing any obvious ones that would require SPL_DM_RNG too. What do you think ?
Re: [PATCH 3/3] ARM: dts: imx: Convert i.MX8M flash.bin image generation to binman
On 4/25/24 10:34 PM, Tim Harvey wrote:
On Tue, Apr 23, 2024 at 11:33 AM Marek Vasut wrote:
Rework the flash.bin image generation such that it uses the new binman
nxp_imx8mimage etype. This way, the flash.bin is assembled in correct
order using plain binman, without any workarounds or sections assembled
in special DT node order.
Signed-off-by: Marek Vasut
---
WARNING: This is very likely to break corner case uses, so please do
test this on your platform.
NOTE: This also opens the implementation for proper CST signing etype,
the CST signing would look similar to nxp-imx8mimage section, and
it would likely wrap the whole topmost section {} in the binman
node.
Marek,
Thanks - this is neat and I look forward to seeing a CST signing etype!
The whole collected batch of patches is here:
https://source.denx.de/u-boot/custodians/u-boot-usb/-/commits/test-cst?ref_type=heads
I believe this will need tweaking, we will probably need more DT
properties to configure the content of the CST config file more
precisely. But this could be a start.
[PATCH 2/2] imx: hab: Use nxp_imx8mcst etype for i.MX8M flash.bin signing
Update documentation and use nxp_imx8mcst binman etype for signing
of flash.bin instead of previous horrible shell scripting.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
doc/imx/habv4/csf_examples/mx8m/csf.sh| 92
doc/imx/habv4/csf_examples/mx8m/csf_fit.txt | 30
doc/imx/habv4/csf_examples/mx8m/csf_spl.txt | 33
doc/imx/habv4/guides/mx8m_spl_secure_boot.txt | 141 +++---
4 files changed, 55 insertions(+), 241 deletions(-)
delete mode 100644 doc/imx/habv4/csf_examples/mx8m/csf.sh
delete mode 100644 doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
delete mode 100644 doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh
b/doc/imx/habv4/csf_examples/mx8m/csf.sh
deleted file mode 100644
index cd3b2614a2f..000
--- a/doc/imx/habv4/csf_examples/mx8m/csf.sh
+++ /dev/null
@@ -1,92 +0,0 @@
-#!/bin/sh
-
-# 0) Generate keys
-#
-# WARNING: ECDSA keys are only supported by HAB 4.5 and newer (i.e. i.MX8M
Plus)
-#
-# cd /path/to/cst-3.3.1/keys/
-#./hab4_pki_tree.sh -existing-ca n -use-ecc n -kl 4096 -duration 10
-num-srk 4 -srk-ca y
-# cd /path/to/cst-3.3.1/crts/
-# ../linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e
SRK_1_2_3_4_fuse.bin -d sha256 -c
./SRK1_sha256_4096_65537_v3_ca_crt.pem,./SRK2_sha256_4096_65537_v3_ca_crt.pem,./SRK3_sha256_4096_65537_v3_ca_crt.pem,./SRK4_sha256_4096_65537_v3_ca_crt.pem
-f 1
-
-# 1) Build U-Boot (e.g. for i.MX8MM)
-#
-# cp -Lv /path/to/arm-trusted-firmware/build/imx8mm/release/bl31.bin .
-# cp -Lv /path/to/firmware-imx-8.14/firmware/ddr/synopsys/ddr3* .
-# make -j imx8mm_board_defconfig
-# make -j`nproc` flash.bin
-
-# 2) Sign SPL and DRAM blobs
-
-cp doc/imx/habv4/csf_examples/mx8m/csf_spl.txt csf_spl.tmp
-cp doc/imx/habv4/csf_examples/mx8m/csf_fit.txt csf_fit.tmp
-
-# update File Paths from env vars
-if ! [ -r $CSF_KEY ]; then
- echo "Error: \$CSF_KEY not found"
- exit 1
-fi
-if ! [ -r $IMG_KEY ]; then
- echo "Error: \$IMG_KEY not found"
- exit 1
-fi
-if ! [ -r $SRK_TABLE ]; then
- echo "Error: \$SRK_TABLE not found"
- exit 1
-fi
-sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_spl.tmp
-sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_spl.tmp
-sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_spl.tmp
-sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_fit.tmp
-sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_fit.tmp
-sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_fit.tmp
-
-# update SPL Blocks
-spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p"
.config) - 0x40)) )
-spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin))
-sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size
\"flash.bin\"@" csf_spl.tmp
-
-# Generate CSF blob
-cst -i csf_spl.tmp -o csf_spl.bin
-
-# Patch CSF blob into flash.bin
-spl_csf_offset=$(xxd -s 24 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_bin_offset=$(xxd -s 4 -l 4 -e flash.bin | cut -d " " -f 2 | sed "s@^@0x@")
-spl_dd_offset=$((${spl_csf_offset} - ${spl_bin_offset} + 0x40))
-dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
-
-# 3) Sign u-boot.itb
-
-# fitImage
-fit_block_base=$(printf "0x%x" $(sed -n "/CONFIG_SPL_LOAD_FIT_ADDRESS=/
s@.*=@@p" .config) )
-fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb
/binman/imx-boot/uboot offset))
-fit_block_size=$(printf "0x%x" $(( ( ( $(stat -tc %s u-boot.itb) + 0x1000 -
0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
-sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset
$fit_block_size \"flash.bin\"@" csf_fit.tmp
-
-# IVT
-ivt_ptr_base=$(printf "%08x" ${fit_block_base} | sed
"s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} -
0x20 )) | sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-csf_block_base=$(printf "%08x" $(( ${fit_block_base} + ${fit_block_size} )) |
sed "s@\(..\)\(..\)\(..\)\(..\)@0x\4\3\2\1@")
-ivt_block_offset=$((${fit_block_offset} + ${fit_block_size} - 0x20))
-csf_block_offset=$((${ivt_block_offset} + 0x20))
-
-echo "0xd1002041 ${ivt_block_base} 0x 0x 0x
${ivt_block_base} ${csf_block_base} 0x" | xxd -r -p > ivt.bin
-dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc
-
-# Generate CSF blob
-cst -i csf_fit.tmp -o cs
[PATCH 1/2] binman: Add nxp_imx8mcst etype for i.MX8M flash.bin signing
Add new binman etype which allows signing both the SPL and fitImage sections
of i.MX8M flash.bin using CST. There are multiple DT properties which govern
the signing process, nxp,loader-address is the only mandatory one which sets
the SPL signature start address without the imx8mimage header, this should be
SPL text base. The key material can be configured using optional DT properties
nxp,srk-table, nxp,csf-key, nxp,img-key, all of which default the key material
names generated by CST tool scripts. The nxp,unlock property can be used to
unlock CAAM access in SPL section.
Minimal signing description example:
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi
b/arch/arm/dts/imx8mp-u-boot.dtsi
index c4c1a177102..ccd44bf9d0b 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -86,6 +86,12 @@
section {
pad-byte = <0x00>;
+ nxp-imx8mcst@0 {
+ filename = "u-boot-spl-mkimage.signed.bin";
+ nxp,loader-address = ;
+ nxp,unlock;
+ args; /* Needed by mkimage etype superclass */
+
nxp-imx8mimage {
filename = "u-boot-spl-mkimage.bin";
nxp,boot-from = "sd";
@@ -129,6 +135,14 @@
};
};
+ };
+
+ nxp-imx8mcst@1 {
+ filename = "u-boot-fit.signed.bin";
+ nxp,loader-address = ;
+ offset = <0x58000>;
+ args; /* Needed by mkimage etype superclass */
+
fit {
description = "Configuration to load ATF before
U-Boot";
#ifndef CONFIG_IMX_HAB
@@ -191,5 +205,6 @@
};
};
};
+ };
};
};
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
tools/binman/btool/cst.py | 48 +++
tools/binman/etype/nxp_imx8mcst.py | 133 +
2 files changed, 181 insertions(+)
create mode 100644 tools/binman/btool/cst.py
create mode 100644 tools/binman/etype/nxp_imx8mcst.py
diff --git a/tools/binman/btool/cst.py b/tools/binman/btool/cst.py
new file mode 100644
index 000..30e78bdbbd9
--- /dev/null
+++ b/tools/binman/btool/cst.py
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2024 Marek Vasut
+#
+"""Bintool implementation for cst"""
+
+import re
+
+from binman import bintool
+
+class Bintoolcst(bintool.Bintool):
+"""Image generation for U-Boot
+
+This bintool supports running `cst` with some basic parameters as
+needed by binman.
+"""
+def __init__(self, name):
+super().__init__(name, 'Sign NXP i.MX image')
+
+# pylint: disable=R0913
+def run(self, output_fname=None):
+"""Run cst
+
+Args:
+output_fname: Output filename to write to
+"""
+args = []
+if output_fname:
+args += ['-o', output_fname]
+return self.run_cmd(*args)
+
+def fetch(self, method):
+"""Fetch handler for cst
+
+This installs cst using the apt utility.
+
+Args:
+method (FETCH_...): Method to use
+
+Returns:
+True if the file was fetched and now installed, None if a method
+other than FETCH_BIN was requested
+
+Raises:
+Valuerror: Fetching could not be completed
+"""
+if method != bintool.FETCH_BIN:
+return None
+return self.apt_install('imx-code-signing-tool')
diff --git a/tools/binman/etype/nxp_imx8mcst.py
b/tools/binman/etype/nxp_imx8mcst.py
new file mode 100644
index 000..fb1c3415ca1
--- /dev/null
+++ b/tools/binman/etype/nxp_imx8mcst.py
@@ -0,0 +1,133 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023-2024 Marek Vasut
+# Written with much help from Simon Glass
+#
+# Entry-type module for generating the i.MX8M code signing tool
+# input configuration file and invocation of cst on generated
+# input configuration file and input data to be signed.
+#
+
+import struct
+
+from collections import OrderedDict
+
+from binman.entry import Entry
+from binman.etype.mkimage i
[PATCH 3/3] crypto/fsl: Differentiate between CAAM and DCP in Kconfig entry
Differentiate between "Enable Random Number Generator support" and "Enable Random Number Generator support" in Kconfig entry, mark the first as CAAM and the second as DCP, otherwise users cannot easily decide which of the options is which and enable the correct one. Signed-off-by: Marek Vasut --- Cc: Angelo Dureghello Cc: Emanuele Ghidoli Cc: Fabio Estevam Cc: Gaurav Jain Cc: Heinrich Schuchardt Cc: Marek Vasut Cc: Michal Simek Cc: Simon Glass Cc: Stefan Roese Cc: Sughosh Ganu Cc: Svyatoslav Ryhel Cc: Tim Harvey Cc: Tom Rini Cc: u-boot@lists.denx.de --- drivers/crypto/fsl/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 9f58731bb67..9ed56632fcd 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -69,7 +69,7 @@ config FSL_CAAM_JR_NTZ_ACCESS driver is used. config FSL_CAAM_RNG - bool "Enable Random Number Generator support" + bool "Enable CAAM Random Number Generator support" depends on DM_RNG default y help @@ -88,7 +88,7 @@ config SPL_FSL_CAAM_RNG endif config FSL_DCP_RNG - bool "Enable Random Number Generator support" + bool "Enable DCP Random Number Generator support" depends on DM_RNG help Enable support for the hardware based random number generator -- 2.43.0
[PATCH 2/3] crypto/fsl: Introduce SPL_FSL_CAAM_RNG
Add SPL variant of SPL_FSL_CAAM_RNG so that the SPL_FSL_CAAM_RNG can be disabled in SPL if necessary. This may be necessary due to e.g. size constraints of the SPL. Signed-off-by: Marek Vasut --- Cc: Angelo Dureghello Cc: Emanuele Ghidoli Cc: Fabio Estevam Cc: Gaurav Jain Cc: Heinrich Schuchardt Cc: Marek Vasut Cc: Michal Simek Cc: Simon Glass Cc: Stefan Roese Cc: Sughosh Ganu Cc: Svyatoslav Ryhel Cc: Tim Harvey Cc: Tom Rini Cc: u-boot@lists.denx.de --- drivers/crypto/fsl/Kconfig | 7 +++ drivers/crypto/fsl/Makefile | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 294e1c8a44e..9f58731bb67 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -78,6 +78,13 @@ config FSL_CAAM_RNG using the prediction resistance flag which means the DRGB is reseeded from the TRNG every time random data is generated. +config SPL_FSL_CAAM_RNG + bool "Enable CAAM Random Number Generator support in SPL" + depends on SPL_DM_RNG + help + This option is an SPL-variant of the FSL_CAAM_RNG option. + See the help of FSL_CAAM_RNG for details. + endif config FSL_DCP_RNG diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index 7a2543e16cc..4fbce519a0b 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -6,6 +6,6 @@ obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o obj-$(CONFIG_CMD_BLOB)$(CONFIG_IMX_CAAM_DEK_ENCAP) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o -obj-$(CONFIG_FSL_CAAM_RNG) += rng.o +obj-$(CONFIG_$(SPL_TPL_)FSL_CAAM_RNG) += rng.o obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o -- 2.43.0
[PATCH 1/3] rng: Introduce SPL_DM_RNG
Add SPL variant of DM_RNG so that the DM_RNG can be disabled in SPL
if necessary. This may be necessary due to e.g. size constraints of
the SPL.
Signed-off-by: Marek Vasut
---
Cc: Angelo Dureghello
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Gaurav Jain
Cc: Heinrich Schuchardt
Cc: Marek Vasut
Cc: Michal Simek
Cc: Simon Glass
Cc: Stefan Roese
Cc: Sughosh Ganu
Cc: Svyatoslav Ryhel
Cc: Tim Harvey
Cc: Tom Rini
Cc: u-boot@lists.denx.de
---
boot/pxe_utils.c| 4 +---
boot/vbe_request.c | 2 +-
drivers/Makefile| 2 +-
drivers/crypto/fsl/jr.c | 4 ++--
drivers/rng/Kconfig | 7 +++
drivers/rng/Makefile| 2 +-
lib/uuid.c | 2 +-
net/net_rand.h | 2 +-
test/dm/Makefile| 2 +-
9 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
index 96205626750..5c1c962ff4c 100644
--- a/boot/pxe_utils.c
+++ b/boot/pxe_utils.c
@@ -21,9 +21,7 @@
#include
#include
-#ifdef CONFIG_DM_RNG
#include
-#endif
#include
#include
@@ -323,7 +321,7 @@ static int label_localboot(struct pxe_label *label)
static void label_boot_kaslrseed(void)
{
-#ifdef CONFIG_DM_RNG
+#if CONFIG_IS_ENABLED(DM_RNG)
ulong fdt_addr;
struct fdt_header *working_fdt;
size_t n = 0x8;
diff --git a/boot/vbe_request.c b/boot/vbe_request.c
index 917251afa1c..0293ac6c869 100644
--- a/boot/vbe_request.c
+++ b/boot/vbe_request.c
@@ -36,7 +36,7 @@ static int handle_random_req(ofnode node, int default_size,
u32 size;
int ret;
- if (!IS_ENABLED(CONFIG_DM_RNG))
+ if (!CONFIG_IS_ENABLED(DM_RNG))
return -ENOTSUPP;
if (ofnode_read_u32(node, "vbe,size", )) {
diff --git a/drivers/Makefile b/drivers/Makefile
index bf73b7718ce..9195dafd37e 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -126,7 +126,7 @@ obj-$(CONFIG_W1_EEPROM) += w1-eeprom/
obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
obj-$(CONFIG_FUZZ) += fuzz/
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/
-obj-$(CONFIG_DM_RNG) += rng/
+obj-$(CONFIG_$(SPL_TPL_)DM_RNG) += rng/
endif
obj-y += soc/
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 203f1625215..8ae5c434bdb 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -787,7 +787,7 @@ init:
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
if (ofnode_valid(scu_node)) {
- if (IS_ENABLED(CONFIG_DM_RNG)) {
+ if (CONFIG_IS_ENABLED(DM_RNG)) {
ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
NULL);
if (ret)
printf("Couldn't bind rng driver (%d)\n", ret);
@@ -810,7 +810,7 @@ init:
return -1;
}
- if (IS_ENABLED(CONFIG_DM_RNG)) {
+ if (CONFIG_IS_ENABLED(DM_RNG)) {
ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
NULL);
if (ret)
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index cd72852a479..5758ae192a6 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -6,6 +6,13 @@ config DM_RNG
This interface is used to initialise the rng device and to
read the random seed from the device.
+config SPL_DM_RNG
+ bool "Driver support for Random Number Generator devices in SPL"
+ depends on SPL_DM
+ help
+ This option is an SPL-variant of the DM_RNG option.
+ See the help of DM_RNG for details.
+
if DM_RNG
config RNG_MESON
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index ecae1a3da33..c1f1c616e00 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -3,7 +3,7 @@
# Copyright (c) 2019, Linaro Limited
#
-obj-$(CONFIG_DM_RNG) += rng-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)DM_RNG) += rng-uclass.o
obj-$(CONFIG_RNG_MESON) += meson-rng.o
obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
obj-$(CONFIG_RNG_MSM) += msm_rng.o
diff --git a/lib/uuid.c b/lib/uuid.c
index 2d7d99535e7..dfa2320ba26 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -378,7 +378,7 @@ void gen_rand_uuid(unsigned char *uuid_bin)
struct udevice *devp;
u32 randv = 0;
- if (IS_ENABLED(CONFIG_DM_RNG)) {
+ if (CONFIG_IS_ENABLED(DM_RNG)) {
ret = uclass_get_device(UCLASS_RNG, 0, );
if (!ret) {
ret = dm_rng_read(devp, , sizeof(randv));
diff --git a/net/net_rand.h b/net/net_rand.h
index d3c5559adfd..686e85f2b53 100644
--- a/net/net_rand.h
+++ b/net/net_rand.h
@@ -42,7 +42,7 @@ static inline void srand_mac(void)
struct udevice *devp;
u32 randv = 0;
- if (IS_ENABLED(CONFIG_DM_RNG)) {
+ if (CONFIG_IS_ENABLED(DM_RNG)) {
ret = uclass_get_device(UCLASS_RNG, 0, );
if (ret) {
ret = dm_rn
[PATCH v2 3/3] ARM: dts: imx: Convert i.MX8M flash.bin image generation to binman
Rework the flash.bin image generation such that it uses the new binman
nxp_imx8mimage etype. This way, the flash.bin is assembled in correct
order using plain binman, without any workarounds or sections assembled
in special DT node order.
Reviewed-By: Tim Harvey
Tested-By: Tim Harvey # imx8mm_venice
Tested-by: Fabio Estevam # imx8mm-evk and imx8mn-evk
Signed-off-by: Marek Vasut
---
WARNING: This is very likely to break corner case uses, so please do
test this on your platform.
NOTE: This also opens the implementation for proper CST signing etype,
the CST signing would look similar to nxp-imx8mimage section, and
it would likely wrap the whole topmost section {} in the binman
node.
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
V2: Add TB from Fabio/Tim and RB from Tim
---
arch/arm/dts/imx8mm-u-boot.dtsi | 126 ++-
.../dts/imx8mm-verdin-wifi-dev-u-boot.dtsi| 8 +-
arch/arm/dts/imx8mn-u-boot.dtsi | 147 +++---
arch/arm/dts/imx8mp-dhcom-u-boot.dtsi | 2 +-
arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi| 2 +-
arch/arm/dts/imx8mp-u-boot.dtsi | 96 +---
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi| 15 +-
arch/arm/dts/imx8mq-u-boot.dtsi | 109 +
8 files changed, 203 insertions(+), 302 deletions(-)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 06f2f73a03f..6ab8f66256e 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -5,7 +5,6 @@
/ {
binman: binman {
- multiple-images;
};
#ifdef CONFIG_OPTEE
@@ -43,56 +42,61 @@
};
{
- u-boot-spl-ddr {
- align = <4>;
- align-size = <4>;
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
-
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
+ filename = "flash.bin";
+ section {
+ pad-byte = <0x00>;
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem.bin";
- align-end = <4>;
+#ifdef CONFIG_FSPI_CONF_HEADER
+ fspi_conf_block {
+ filename = CONFIG_FSPI_CONF_FILE;
type = "blob-ext";
+ size = <0x1000>;
};
+#endif
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ nxp-imx8mimage {
+ filename = "u-boot-spl-mkimage.bin";
+ nxp,boot-from = "sd";
+ nxp,rom-version = <1>;
+ nxp,loader-address = ;
+ args; /* Needed by mkimage etype superclass */
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ section {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
- };
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
- spl {
- filename = "spl.bin";
+ ddr-1d-imem-fw {
+ filename =
"lpddr4_pmu_train_1d_imem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x7e1000";
+
[PATCH v2 2/3] ARM: dts: imx: Switch Ronetix iMX8MQ-CM to imx8mq-u-boot.dtsi
Include imx8mq-u-boot.dtsi in the board -u-boot.dtsi to pull in binman
configuration instead of duplicating it in the board -u-boot.dtsi again.
Drop the duplicate binman configuration.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
V2: No change
---
arch/arm/dts/imx8mq-cm-u-boot.dtsi | 111 +
1 file changed, 1 insertion(+), 110 deletions(-)
diff --git a/arch/arm/dts/imx8mq-cm-u-boot.dtsi
b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
index e23998f5aba..819501337e9 100644
--- a/arch/arm/dts/imx8mq-cm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
@@ -3,11 +3,7 @@
* Copyright 2019 NXP
*/
-/ {
- binman: binman {
- multiple-images;
- };
-};
+#include "imx8mq-u-boot.dtsi"
_uart1 {
bootph-pre-ram;
@@ -16,108 +12,3 @@
{
bootph-pre-ram;
};
-
- {
-u-boot-spl-ddr {
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
-
- u-boot-spl {
- align-end = <4>;
- };
-
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
- };
-
- flash {
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x7e1000";
-
- blob {
- filename = "u-boot-spl-ddr.bin";
- };
- };
- };
-
- itb {
- filename = "u-boot.itb";
-
- fit {
- description = "Configuration to load ATF before U-Boot";
- #address-cells = <1>;
- fit,external-offset = ;
-
- images {
- uboot {
- description = "U-Boot (64-bit)";
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = ;
-
- uboot_blob: blob-ext {
- filename = "u-boot-nodtb.bin";
- };
- };
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x91>;
- entry = <0x91>;
-
- atf_blob: blob-ext {
- filename = "bl31.bin";
- };
- };
-
- fdt {
- description = "NAME";
- type = "flat_dt";
- compression = "none";
-
- uboot_fdt_blob: blob-ext {
- filename = "u-boot.dtb";
- };
- };
- };
-
-
[PATCH v2 1/3] binman: Add nxp_imx8mimage etype
Add new binman etype derived from mkimage etype which generates configuration
input file for mkimage -T imx8mimage, and runs the mkimage on input data. The
mkimage -T imx8mimage is used to generate combined image with SPL and DDR PHY
blobs which is bootable on i.MX8M.
The configuration file generated here is equivalent of imx8mimage.cfg, which
is the file passed to '$ mkimage -T imx8mimage -n imx8mimage.cfg ...' . The
settings generated into the imx8mimage.cfg file are configured via supported
binman DT properties, nxp,boot-from, nxp,loader-address, nxp,rom-version.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
V2: Fix pylint errors
---
tools/binman/etype/nxp_imx8mimage.py | 74
1 file changed, 74 insertions(+)
create mode 100644 tools/binman/etype/nxp_imx8mimage.py
diff --git a/tools/binman/etype/nxp_imx8mimage.py
b/tools/binman/etype/nxp_imx8mimage.py
new file mode 100644
index 000..3585120b79b
--- /dev/null
+++ b/tools/binman/etype/nxp_imx8mimage.py
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023-2024 Marek Vasut
+# Written with much help from Simon Glass
+#
+# Entry-type module for generating the i.MX8M mkimage -T imx8mimage
+# configuration file and invocation of mkimage -T imx8mimage on the
+# configuration file and input data.
+#
+
+from collections import OrderedDict
+
+from binman.entry import Entry
+from binman.etype.mkimage import Entry_mkimage
+from binman.etype.section import Entry_section
+from binman import elf
+from dtoc import fdt_util
+from u_boot_pylib import tools
+
+class Entry_nxp_imx8mimage(Entry_mkimage):
+"""NXP i.MX8M imx8mimage .cfg file generator and mkimage invoker
+
+Properties / Entry arguments:
+- nxp,boot-from - device to boot from (e.g. 'sd')
+- nxp,loader-address - loader address (SPL text base)
+- nxp,rom-version - BootROM version ('2' for i.MX8M Nano and Plus)
+"""
+
+def __init__(self, section, etype, node):
+super().__init__(section, etype, node)
+self.required_props = ['nxp,boot-from', 'nxp,rom-version',
'nxp,loader-address']
+
+def ReadNode(self):
+super().ReadNode()
+self.boot_from = fdt_util.GetString(self._node, 'nxp,boot-from')
+self.loader_address = fdt_util.GetInt(self._node, 'nxp,loader-address')
+self.rom_version = fdt_util.GetInt(self._node, 'nxp,rom-version')
+self.ReadEntries()
+
+def BuildSectionData(self, required):
+data, input_fname, uniq = self.collect_contents_to_file(
+self._entries.values(), 'input')
+# Generate mkimage configuration file similar to imx8mimage.cfg
+# and pass it to mkimage to generate SPL image for us here.
+cfg_fname = tools.get_output_filename('nxp.imx8mimage.cfg.%s' % uniq)
+with open(cfg_fname, 'w') as outf:
+print('ROM_VERSION v%d' % self.rom_version, file=outf)
+print('BOOT_FROM %s' % self.boot_from, file=outf)
+print('LOADER %s %#x' % (input_fname, self.loader_address),
file=outf)
+
+output_fname = tools.get_output_filename(f'cfg-out.{uniq}')
+args = ['-d', input_fname, '-n', cfg_fname, '-T', 'imx8mimage',
+output_fname]
+if self.mkimage.run_cmd(*args) is not None:
+return tools.read_file(output_fname)
+else:
+# Bintool is missing; just use the input data as the output
+self.record_missing_bintool(self.mkimage)
+return data
+
+def SetImagePos(self, image_pos):
+# Customized SoC specific SetImagePos which skips the mkimage etype
+# implementation and removes the 0x48 offset introduced there. That
+# offset is only used for uImage/fitImage, which is not the case in
+# here.
+upto = 0x00
+for entry in super().GetEntries().values():
+entry.SetOffsetSize(upto, None)
+
+# Give up if any entries lack a size
+if entry.size is None:
+return
+upto += entry.size
+
+Entry_section.SetImagePos(self, image_pos)
--
2.43.0
[PATCH] binman: Fix typo in mkimage etype description
Fix a typo, no functional change. Signed-off-by: Marek Vasut --- Cc: Alper Nebi Yasak Cc: Simon Glass Cc: Tom Rini Cc: u-boot@lists.denx.de --- tools/binman/btool/mkimage.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/binman/btool/mkimage.py b/tools/binman/btool/mkimage.py index d5b407c5547..39a4c8c1432 100644 --- a/tools/binman/btool/mkimage.py +++ b/tools/binman/btool/mkimage.py @@ -11,7 +11,7 @@ class Bintoolmkimage(bintool.Bintool): """Image generation for U-Boot This bintool supports running `mkimage` with some basic parameters as -neeed by binman. +needed by binman. Normally binman uses the mkimage built by U-Boot. But when run outside the U-Boot build system, binman can use the version installed in your system. -- 2.43.0
Re: [PATCH v3] usb: cdns3: gadget.c: Set fast access bit
On 4/24/24 9:39 AM, Ravi Gunasekaran wrote:
From: Aswath Govindraju
When the device port is in a low power state [U3/L2/Not Connected],
accesses to usb device registers may take a long time. This could lead to
potential core hang when the controller registers are accessed after the
port is disabled by setting DEVDS field. Setting the fast register access
bit ensures that the PHY clock is keeping up in active state.
Therefore, set fast access bit to ensure the accesses to device registers
are quick even in low power states.
commit b5148d946f45 ("usb: cdns3: gadget: set fast access bit") in the
upstream kernel is taken as reference.
Signed-off-by: Aswath Govindraju
Signed-off-by: Ravi Gunasekaran
Reviewed-by: Roger Quadros
Reviewed-by: Marek Vasut
---
Changes since v2:
* Updated the commit description with reference to upstream kernel commit
* Picked up Marek's Reviewed-by tag from v2
Changes since v1:
-
* Rebased to tip of -next
* Added Reviewed-by tag
v2: https://lore.kernel.org/all/20240423082420.32336-1-r-gunaseka...@ti.com/
v1: https://lore.kernel.org/u-boot/20230505121353.23486-1-r-gunaseka...@ti.com/
drivers/usb/cdns3/gadget.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index 7aa0c6b2be..d11175dc5b 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -2325,6 +2325,9 @@ static void cdns3_gadget_config(struct cdns3_device
*priv_dev)
writel(USB_IEN_INIT, >usb_ien);
writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, >usb_conf);
+ /* Set the Fast access bit */
+ writel(PUSB_PWR_FST_REG_ACCESS, _dev->regs->usb_pwr);
+
cdns3_configure_dmult(priv_dev, NULL);
cdns3_gadget_pullup(_dev->gadget, 1);
@@ -2383,6 +2386,7 @@ static int cdns3_gadget_udc_stop(struct usb_gadget
*gadget)
/* disable interrupt for device */
writel(0, _dev->regs->usb_ien);
+ writel(0, _dev->regs->usb_pwr);
writel(USB_CONF_DEVDS, _dev->regs->usb_conf);
return ret;
base-commit: bc39e06778168a34bb4e0a34fbee4edbde4414d8
Since this is gadget stuff, +CC Mattijs , that should go through their tree.
Thanks!
Re: [PATCH] ARM: imx: Enable kaslrseed command on DH i.MX8M Plus DHCOM
On 4/19/24 5:24 PM, Tim Harvey wrote:
On Thu, Apr 18, 2024 at 11:42 AM Marek Vasut wrote:
On 4/18/24 8:02 PM, Fabio Estevam wrote:
Hi Tim,
On Thu, Apr 18, 2024 at 2:54 PM Tim Harvey wrote:
Fabio, if you enable CONFIG_DM_RNG on an imx8m{m,p}_evk do you get the
following in the SPL?
Couldn't bind rng driver (-96)
SEC0: RNG instantiated
sec_init failed!
Yes, if I add CONFIG_DM_RNG=y to imx8mm_evk_defconfig I get:
U-Boot SPL 2024.04-00793-g3434b88d2c2f-dirty (Apr 18 2024 - 14:58:57 -0300)
No pmic
Couldn't bind rng driver (-96)
SEC0: RNG instantiated
sec_init failed!
Interesting. Which TFA blob version do you use ? I used the mainline
2.10 for my tests.
Marek,
Were you able to reproduce this as well with the board you enabled
DM_RNG for? If it does work fine what dtb were you using... perhaps
there is something in its u-boot.dtsi that we need?
This one arch/arm/dts/imx8mp-dhcom-pdk3.dts , see log below. The build
has a few extra patches in it, but nothing which affects the KASLR:
$ export SOURCE_DATE_EPOCH=1672531200 ; echo tst > .scmversion
$ make imx8mp_dhcom_pdk3_defconfig ; make
U-Boot SPL 2024.07-rc1tst (Jan 01 2023 - 00:00:00 +)
DDR: 4096 MiB [0x5]
DDR: Inline ECC enabled
WDT: Started watchdog@3028 with servicing every 1000ms (60s timeout)
Trying to boot from BOOTROM
Boot Stage: Primary boot
image offset 0x1000, pagesize 0x1, ivt offset 0x0
NOTICE: Do not release JR0 to NS as it can be used by HAB
NOTICE: BL31: v2.10.0 (release):v2.10.0-5-gfb51ca229
NOTICE: BL31: Built : 20:30:36, Apr 23 2024
U-Boot 2024.07-rc1tst (Jan 01 2023 - 00:00:00 +)
CPU: Freescale i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 70C
Reset cause: POR
Model: DH electronics i.MX8M Plus DHCOM Premium Developer Kit (3)
DRAM: 3.5 GiB
Core: 183 devices, 34 uclasses, devicetree: separate
WDT: Started watchdog@3028 with servicing every 1000ms (60s timeout)
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from SPIFlash... SF: Detected w25q128jw with page
size 256 Bytes, erase size 4 KiB, total 16 MiB
OK
In:serial
Out: serial
Err: serial
SEC0: RNG instantiated
Net: eth1: ethernet@30be, eth0: ethernet@30bf
...
The error -EPFNOSUPPORT is interesting and helps point to the only
place it can be where the comment says the strange errno is to make
this easier to find:
https://elixir.bootlin.com/u-boot/latest/source/drivers/core/uclass.c#L70:
if (!uc_drv) {
debug("Cannot find uclass for id %d: please add the
UCLASS_DRIVER() declaration for this UCLASS_... id\n",
id);
/*
* Use a strange error to make this case easier to find. When
* a uclass is not available it can prevent driver model from
* starting up and this failure is otherwise hard to debug.
*/
return -EPFNOSUPPORT;
}
I'm not very familiar with the dm driver binding - does the
U-BOOT_DRIVER usage in drivers/crypto/fsl/rng.c need to be refactored
to use UCLASS_DRIVER for it to be usable in both SPL and U-Boot?
I don't think you need the CAAM RNG in SPL in the first place, or do you ?
Honestly I don't know why we need DM_RNG in SPL anyway and we could
just add support for disabling it there to avoid unwanted bloat.
I think you can disable it , yes.
Re: [PATCH] usb: dwc2: Add in version 4xx compatibility
On 4/23/24 9:09 AM, Mattijs Korpershoek wrote: Hi Greg, On ven., avril 19, 2024 at 15:21, Greg Malysa wrote: Hi Mattijs, Please avoid top-posting when replying, it makes following the discussion more difficult: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#use-trimmed-interleaved-replies-in-email-discussions Will do. Sorry about that; I'm still learning about this approach to email. No worries. There are quite some things to learn and we probably all did this wrong when starting. Thank you for taking the time to learn and to contribute! Looking at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=65dc2e725286106f99c6f6b78e3d9c52c15f3a9c we can see that the following is added: #define DWC2_CORE_REV_MASK 0x This makes me believe that the versioning follows a well known pattern. I can submit a v2 next week to bring it in line with the kernel's approach. To me, it's fine as is. Note that this change is also part of: https://lore.kernel.org/all/20240328131811.94559-1-seashell11234...@gmail.com/ Or if you prefer I can also drop our patch and we can pursue this linked patch with both 4xx compatibility and the 420a reset handling. I think the patch you submitted is fine by itself, but I'd let Marek decide since he is the maintainer for this part. If you have access to the hardware that has a 4.20a dwc2 controller, maybe you can help testing the patch above patch as well? +CC Liu on this thread, maybe it is best if the two of you figure out the best common approach that works for you both ?
Re: [PATCH v4] mmc: Poll CD in case cyclic framework is enabled
On 3/16/24 9:13 PM, Marek Vasut wrote: In case the cyclic framework is enabled, poll the card detect of already initialized cards and deinitialize them in case they are removed. Since the card initialization is a longer process and card initialization is done on first access to an uninitialized card anyway, avoid initializing newly detected uninitialized cards in the cyclic callback. Any input on this ?
[PATCH] ARM: dts: imx: Enable PCIe and NVMe on DH i.MX8M Plus DHCOM PDK3
Enable PCIe/NVMe support on DH i.MX8M Plus DHCOM PDK3. Except for
the configuration options which are enabled, add slight adjustment
to board u-boot.dtsi, which is necessary as there is currently no
driver for the I2C PCIe clock generator. Since the generator is
strapped to be always on, it is possible to supplant the generator
functionality by fixed-clock.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Fabio Estevam
Cc: Simon Glass
Cc: Stefano Babic
Cc: Tom Rini
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi | 12
configs/imx8mp_dhcom_pdk3_defconfig| 5 +
2 files changed, 17 insertions(+)
diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi
b/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi
index 040f333c52d..b0b99d51856 100644
--- a/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi
@@ -4,3 +4,15 @@
*/
#include "imx8mp-dhcom-u-boot.dtsi"
+
+/ {
+ clk_pcie100: clk-pcie100 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+};
+
+_phy {
+ clocks = <_pcie100>;
+};
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig
b/configs/imx8mp_dhcom_pdk3_defconfig
index a42dc27aff8..019595edda8 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -31,6 +31,7 @@ CONFIG_ENV_OFFSET_REDUND=0xFF
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800
CONFIG_SYS_LOAD_ADDR=0x5000
+CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
@@ -104,6 +105,7 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_BKOPS_ENABLE=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
@@ -218,7 +220,10 @@ CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_IMX=y
CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PHY_IMX8M_PCIE=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
--
2.43.0
[PATCH 3/3] ARM: dts: imx: Convert i.MX8M flash.bin image generation to binman
Rework the flash.bin image generation such that it uses the new binman
nxp_imx8mimage etype. This way, the flash.bin is assembled in correct
order using plain binman, without any workarounds or sections assembled
in special DT node order.
Signed-off-by: Marek Vasut
---
WARNING: This is very likely to break corner case uses, so please do
test this on your platform.
NOTE: This also opens the implementation for proper CST signing etype,
the CST signing would look similar to nxp-imx8mimage section, and
it would likely wrap the whole topmost section {} in the binman
node.
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
arch/arm/dts/imx8mm-u-boot.dtsi | 126 ++-
.../dts/imx8mm-verdin-wifi-dev-u-boot.dtsi| 8 +-
arch/arm/dts/imx8mn-u-boot.dtsi | 147 +++---
arch/arm/dts/imx8mp-dhcom-u-boot.dtsi | 2 +-
arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi| 2 +-
arch/arm/dts/imx8mp-u-boot.dtsi | 96 +---
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi| 15 +-
arch/arm/dts/imx8mq-u-boot.dtsi | 109 +
8 files changed, 203 insertions(+), 302 deletions(-)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 06f2f73a03f..6ab8f66256e 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -5,7 +5,6 @@
/ {
binman: binman {
- multiple-images;
};
#ifdef CONFIG_OPTEE
@@ -43,56 +42,61 @@
};
{
- u-boot-spl-ddr {
- align = <4>;
- align-size = <4>;
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
-
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
+ filename = "flash.bin";
+ section {
+ pad-byte = <0x00>;
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem.bin";
- align-end = <4>;
+#ifdef CONFIG_FSPI_CONF_HEADER
+ fspi_conf_block {
+ filename = CONFIG_FSPI_CONF_FILE;
type = "blob-ext";
+ size = <0x1000>;
};
+#endif
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ nxp-imx8mimage {
+ filename = "u-boot-spl-mkimage.bin";
+ nxp,boot-from = "sd";
+ nxp,rom-version = <1>;
+ nxp,loader-address = ;
+ args; /* Needed by mkimage etype superclass */
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
+ section {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
- };
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
- spl {
- filename = "spl.bin";
+ ddr-1d-imem-fw {
+ filename =
"lpddr4_pmu_train_1d_imem.bin";
+ align-end = <4>;
+ type = "blob-ext";
+ };
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x7e1000";
+ ddr-1d-dmem-fw {
+ filename =
"lpddr4_pmu_train_1d_dmem.bin";
+
[PATCH 2/3] ARM: dts: imx: Switch Ronetix iMX8MQ-CM to imx8mq-u-boot.dtsi
Include imx8mq-u-boot.dtsi in the board -u-boot.dtsi to pull in binman
configuration instead of duplicating it in the board -u-boot.dtsi again.
Drop the duplicate binman configuration.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
arch/arm/dts/imx8mq-cm-u-boot.dtsi | 111 +
1 file changed, 1 insertion(+), 110 deletions(-)
diff --git a/arch/arm/dts/imx8mq-cm-u-boot.dtsi
b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
index e23998f5aba..819501337e9 100644
--- a/arch/arm/dts/imx8mq-cm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
@@ -3,11 +3,7 @@
* Copyright 2019 NXP
*/
-/ {
- binman: binman {
- multiple-images;
- };
-};
+#include "imx8mq-u-boot.dtsi"
_uart1 {
bootph-pre-ram;
@@ -16,108 +12,3 @@
{
bootph-pre-ram;
};
-
- {
-u-boot-spl-ddr {
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
-
- u-boot-spl {
- align-end = <4>;
- };
-
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
- };
-
- flash {
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x7e1000";
-
- blob {
- filename = "u-boot-spl-ddr.bin";
- };
- };
- };
-
- itb {
- filename = "u-boot.itb";
-
- fit {
- description = "Configuration to load ATF before U-Boot";
- #address-cells = <1>;
- fit,external-offset = ;
-
- images {
- uboot {
- description = "U-Boot (64-bit)";
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = ;
-
- uboot_blob: blob-ext {
- filename = "u-boot-nodtb.bin";
- };
- };
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x91>;
- entry = <0x91>;
-
- atf_blob: blob-ext {
- filename = "bl31.bin";
- };
- };
-
- fdt {
- description = "NAME";
- type = "flat_dt";
- compression = "none";
-
- uboot_fdt_blob: blob-ext {
- filename = "u-boot.dtb";
- };
- };
- };
-
- configurations {
- default = "conf";
-
- conf {
- description = "NAME";
- firmware = "uboot";
- loadables = "atf";
- fdt = "fdt";
- };
- };
- };
- };
-};
--
2.43.0
[PATCH 1/3] binman: Add nxp_imx8mimage etype
Add new binman etype derived from mkimage etype which generates configuration
input file for mkimage -T imx8mimage, and runs the mkimage on input data. The
mkimage -T imx8mimage is used to generate combined image with SPL and DDR PHY
blobs which is bootable on i.MX8M.
The configuration file generated here is equivalent of imx8mimage.cfg, which
is the file passed to '$ mkimage -T imx8mimage -n imx8mimage.cfg ...' . The
settings generated into the imx8mimage.cfg file are configured via supported
binman DT properties, nxp,boot-from, nxp,loader-address, nxp,rom-version.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Francesco Dolcini
Cc: Marcel Ziswiler
Cc: Rasmus Villemoes
Cc: Simon Glass
Cc: Stefan Eichenberger
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tom Rini
Cc: ker...@puri.sm
Cc: u-b...@dh-electronics.com
Cc: u-boot@lists.denx.de
---
tools/binman/etype/nxp_imx8mimage.py | 73
1 file changed, 73 insertions(+)
create mode 100644 tools/binman/etype/nxp_imx8mimage.py
diff --git a/tools/binman/etype/nxp_imx8mimage.py
b/tools/binman/etype/nxp_imx8mimage.py
new file mode 100644
index 000..5a106e0a76e
--- /dev/null
+++ b/tools/binman/etype/nxp_imx8mimage.py
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2023-2024 Marek Vasut
+# Written with much help from Simon Glass
+#
+# Entry-type module for generating the i.MX8M mkimage -T imx8mimage
+# configuration file and invocation of mkimage -T imx8mimage on the
+# configuration file and input data.
+#
+
+from collections import OrderedDict
+
+from binman.entry import Entry
+from binman.etype.mkimage import Entry_mkimage
+from binman import elf
+from dtoc import fdt_util
+from u_boot_pylib import tools
+
+class Entry_nxp_imx8mimage(Entry_mkimage):
+"""NXP i.MX8M imx8mimage .cfg file generator and mkimage invoker
+
+Properties / Entry arguments:
+- nxp,boot-from - device to boot from (e.g. 'sd')
+- nxp,loader-address - loader address (SPL text base)
+- nxp,rom-version - BootROM version ('2' for i.MX8M Nano and Plus)
+"""
+
+def __init__(self, section, etype, node):
+super().__init__(section, etype, node)
+self.required_props = ['nxp,boot-from', 'nxp,rom-version',
'nxp,loader-address']
+
+def ReadNode(self):
+super().ReadNode()
+self.boot_from = fdt_util.GetString(self._node, 'nxp,boot-from')
+self.loader_address = fdt_util.GetInt(self._node, 'nxp,loader-address')
+self.rom_version = fdt_util.GetInt(self._node, 'nxp,rom-version')
+self.ReadEntries()
+
+def BuildSectionData(self, required):
+_, input_fname, uniq = self.collect_contents_to_file(
+self._entries.values(), 'input')
+# Generate mkimage configuration file similar to imx8mimage.cfg
+# and pass it to mkimage to generate SPL image for us here.
+cfg_fname = tools.get_output_filename('nxp.imx8mimage.cfg.%s' % uniq)
+with open(cfg_fname, 'w') as outf:
+print('ROM_VERSION v%d' % self.rom_version, file=outf)
+print('BOOT_FROM %s' % self.boot_from, file=outf)
+print('LOADER %s %#x' % (input_fname, self.loader_address),
file=outf)
+
+output_fname = tools.get_output_filename(f'cfg-out.{uniq}')
+args = ['-d', input_fname, '-n', cfg_fname, '-T', 'imx8mimage',
+output_fname]
+if self.mkimage.run_cmd(*args) is not None:
+return tools.read_file(output_fname)
+else:
+# Bintool is missing; just use the input data as the output
+self.record_missing_bintool(self.mkimage)
+return data
+
+def SetImagePos(self, image_pos):
+# Customized SoC specific SetImagePos which skips the mkimage etype
+# implementation and removes the 0x48 offset introduced there. That
+# offset is only used for uImage/fitImage, which is not the case in
+# here.
+upto = 0x00
+for entry in super().GetEntries().values():
+entry.SetOffsetSize(upto, None)
+
+# Give up if any entries lack a size
+if entry.size is None:
+return
+upto += entry.size
+
+super(Entry_mkimage, self).SetImagePos(image_pos)
--
2.43.0
Re: [PATCH v2 1/3] net: eth-uclass: Introduce NET_PREFER_ROM_MAC_ADDR
On 4/23/24 3:35 PM, Detlev Casanova wrote: On Monday, April 22, 2024 3:47:21 P.M. EDT Marek Vasut wrote: On 4/22/24 3:56 PM, Detlev Casanova wrote: On some boards, a MAC address is set based on the CPU ID or other information. This is usually done in the misc_init_r() function. This becomes a problem for net devices that are probed after the call to misc_init_r(), for example, when the ethernet is on a PCI port, which needs to be enumerated. In this case, misc_init_r() will set the ethaddr variable, then, when the ethernet device is probed, if it has a ROM address, u-boot will warn about a MAC address mismatch and use the misc_init_r() address instead of the one in ROM. The operating system later will most likely use the ROM MAC address, which can be confusing. To avoid that, this commit introduces NET_PREFER_ROM_MAC_ADDR that can be set for boards that have such an interface. Signed-off-by: Detlev Casanova Won't the system pick ROM MAC if $ethaddr is not set ? Yes, and in the case of rockchip, misc_init_r() will set an $ethaddr based on the cpuid, which makes the eth driver use that instead of the ROM one. Shouldn't the rockchip misc_init_r be fixed then ?
Re: [PATCH v2] usb: cdns3: gadget.c: Set fast access bit
On 4/23/24 10:24 AM, Ravi Gunasekaran wrote:
From: Aswath Govindraju
When the device port is in a low power state [U3/L2/Not Connected],
accesses to usb device registers may take a long time. This could lead to
potential core hang when the controller registers are accessed after the
port is disabled by setting DEVDS field. Setting the fast register access
bit ensures that the PHY clock is keeping up in active state.
Therefore, set fast access bit to ensure the accesses to device registers
are quick even in low power states.
Signed-off-by: Aswath Govindraju
Signed-off-by: Ravi Gunasekaran
Reviewed-by: Roger Quadros
---
v1 was posted and was reviewed as well. But it did not get merged.
This change is present in upstream linux kernel as well.
Upstream Linux kernel commit: b5148d946f45 ("usb: cdns3: gadget: set fast access
bit")
This commit ^ should be mentioned in the commit message.
With that fixed:
Reviewed-by: Marek Vasut
Thanks !
Re: [RFC PATCH 1/1] net: dwc_eth_qos: mdio: Implement clause 45
On 4/23/24 10:51 AM, Philip Oberfichtner wrote: Bevor this commit, only clause 22 access was possible. After this commit, clause 45 direct access will available as well. Note that there is a slight change of behavior: Before this commit, the C45E bit was set to whatever value was left in the register from the previous access. After this commit, we adopt the common practice of discerning C45 from C22 using the devad argument. Signed-off-by: Philip Oberfichtner --- Notes: This patch is labeled RFC as there is a slight change of behavior (see commit message). I'm not sure in fact if this solution works for everybody - this is up for discussion! My implementation is tested on an Intel Elkhart lake SOC. Driver code for dwc_eth_qos_intel coming soon in a separate patch series. drivers/net/dwc_eth_qos.c | 66 ++- drivers/net/dwc_eth_qos.h | 1 + 2 files changed, 45 insertions(+), 22 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 86d989e244..64a9bff6bb 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -162,6 +162,25 @@ static int eqos_mdio_wait_idle(struct eqos_priv *eqos) 100, true); } +/* Bitmask common for mdio_read and mdio_write */ +#define EQOS_MDIO_BITFIELD(pa, rda, cr) \ + (pa << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | \ Parenthesis around (pa) are missing, DTTO for the rest of this. However, better use FIELD_GET/FIELD_PREP macros instead. [...]
Re: [PATCH] usb: dwc3: support USB 3.1 controllers
On 4/22/24 12:53 PM, Caleb Connolly wrote:
On 21/04/2024 22:38, Marek Vasut wrote:
On 4/11/24 6:05 PM, Caleb Connolly wrote:
The revision is different for these, add the additional check as in
xhci-dwc3 core_init code.
Signed-off-by: Caleb Connolly
Is there a matching Linux kernel patch , or does Linux do some other
check ?
I just took this change from the xhci-dwc3 driver tbh... But I did some
archeology and it seems the associated Linux patch would be 690fb3718a70
("usb: dwc3: Support Synopsys USB 3.1 IP").
Can you please mention it in the commit message, and send a V2 with my:
Reviewed-by: Marek Vasut
Thanks
Re: [PATCH] usb: dwc2: update reset method for host and device mode
On 4/22/24 7:31 AM, Kongyang Liu wrote:
[...]
@@ -167,9 +168,20 @@ static void dwc_otg_core_reset(struct udevice *dev,
dev_info(dev, "%s: Timeout!\n", __func__);
/* Core Soft Reset */
+ snpsid = readl(>gsnpsid);
writel(DWC2_GRSTCTL_CSFTRST, >grstctl);
- ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
- false, 1000, false);
+ if ((snpsid & DWC2_SNPSID_VER_MASK) < (DWC2_SNPSID_DEVID_VER_420a &
DWC2_SNPSID_VER_MASK)) {
+ ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
+ false, 1000, false);
+ } else {
+ ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_GSFTRST_DONE,
+ true, 1000, false);
+ greset = readl(>grstctl);
+ greset &= ~DWC2_GRSTCTL_CSFTRST;
+ greset |= DWC2_GRSTCTL_GSFTRST_DONE;
+ writel(greset, >grstctl);
Same comments as above.
Maybe this should be pulled into dedicated function to avoid duplication?
For U-Boot, the dwc2 USB driver is split into two modules: host and gadget.
Each has its own register definitions and definitions for register bits,
which makes it difficult to extract a single function. Moreover, deciding
where to place this function is also an issue.
There is drivers/usb/common/ for such code. The register macros can
probably be unified into a single header too.
Re: [PATCH v2 2/3] configs/rock5b: Set NET_PREFER_ROM_MAC_ADDR to y
On 4/22/24 3:56 PM, Detlev Casanova wrote: --- configs/rock5b-rk3588_defconfig | 1 + 1 file changed, 1 insertion(+) This patch seems to be missing commit message and SoB line
Re: [PATCH v2 1/3] net: eth-uclass: Introduce NET_PREFER_ROM_MAC_ADDR
On 4/22/24 3:56 PM, Detlev Casanova wrote: On some boards, a MAC address is set based on the CPU ID or other information. This is usually done in the misc_init_r() function. This becomes a problem for net devices that are probed after the call to misc_init_r(), for example, when the ethernet is on a PCI port, which needs to be enumerated. In this case, misc_init_r() will set the ethaddr variable, then, when the ethernet device is probed, if it has a ROM address, u-boot will warn about a MAC address mismatch and use the misc_init_r() address instead of the one in ROM. The operating system later will most likely use the ROM MAC address, which can be confusing. To avoid that, this commit introduces NET_PREFER_ROM_MAC_ADDR that can be set for boards that have such an interface. Signed-off-by: Detlev Casanova Won't the system pick ROM MAC if $ethaddr is not set ?
[PATCH 19/19] ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board
This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on
STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC
carrier board.
The SoM contains the following peripherals:
- STPMIC (power delivery)
- 512MB DDR3L memory
- eMMC and SDIO WiFi module
The DHSBC carrier board contains the following peripherals:
- Two RGMII Ethernet ports
- USB-A Host port, USB-C peripheral port, USB-C power supply plug
- Expansion connector
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/Makefile | 1 +
.../dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi | 25 ++
arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts | 383 ++
arch/arm/dts/stm32mp13xx-dhcor-som.dtsi | 308 ++
arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi| 55 +++
configs/stm32mp13_dhcor_defconfig | 148 +++
6 files changed, 920 insertions(+)
create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-som.dtsi
create mode 100644 arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
create mode 100644 configs/stm32mp13_dhcor_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c9c6222e5..ca1e3bf3fc8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1290,6 +1290,7 @@ dtb-$(CONFIG_ASPEED_AST2600) += \
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP13X) += \
+ stm32mp135f-dhcor-dhsbc.dtb \
stm32mp135f-dk.dtb
dtb-$(CONFIG_STM32MP15X) += \
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
new file mode 100644
index 000..d718aae16ca
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut
+ */
+
+#include "stm32mp13xx-dhcor-u-boot.dtsi"
+
+ {
+ bootph-all;
+};
+
+_pins_b {
+ bootph-all;
+
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
+ {
+ bootph-all;
+};
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
new file mode 100644
index 000..fc1c48ad56d
--- /dev/null
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut
+ *
+ * DHCOR STM32MP13 variant:
+ * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
+ * DHCOR PCB number: 718-100 or newer
+ * DHSBC PCB number: 719-100 or newer
+ */
+
+/dts-v1/;
+
+#include
+#include "stm32mp135.dtsi"
+#include "stm32mp13xf.dtsi"
+#include "stm32mp13xx-dhcor-som.dtsi"
+
+/ {
+ model = "DH electronics STM32MP135F DHCOR DHSBC";
+ compatible = "dh,stm32mp135f-dhcor-dhsbc",
+"dh,stm32mp135f-dhcor-som",
+"st,stm32mp135";
+
+ aliases {
+ ethernet0 =
+ ethernet1 =
+ serial2 =
+ serial3 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_a _usb_cc_pins_b>;
+ vdda-supply = <_adc>;
+ vref-supply = <_adc>;
+ status = "okay";
+
+ adc1: adc@0 {
+ status = "okay";
+
+ /*
+* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
+* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+* 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+* Use arbitrary margin here (e.g. 5us).
+*
+* The pinmux pins must be set as ANALOG, use datasheet
+* DS13483 Table 7. STM32MP135C/F ball definitions to
+* find out which 'pin name' maps to which 'additional
+* functions', which lists the mapping between pin and
+* ADC channel. In this case, PA5 maps to ADC1_INP2 and
+* PF13 maps to ADC1_INP11 .
+*/
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ channel@11 {
+ reg = <11>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ /* Expansion connector: INP12:pin29 */
+ channel@12 {
+ reg = <12>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+};
+
+ {
+ statu
[PATCH 18/19] ARM: dts: stm32: Add alternate pinmux for MP13 UART7 pins
Add another mux option for UART7 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 41 +
1 file changed, 41 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 7014c7a6d23..c01d39f03ea 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -647,6 +647,47 @@
};
};
+ uart7_pins_a: uart7-0 {
+ pins1 {
+ pinmux = , /* UART7_TX */
+; /* UART7_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = , /* UART7_RX */
+; /* UART7_CTS_NSS
*/
+ bias-disable;
+ };
+ };
+
+ uart7_idle_pins_a: uart7-idle-0 {
+ pins1 {
+ pinmux = , /* UART7_TX */
+; /*
UART7_CTS_NSS */
+ };
+ pins2 {
+ pinmux = ; /* UART7_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = ; /* UART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_sleep_pins_a: uart7-sleep-0 {
+ pins {
+ pinmux = , /* UART7_TX */
+, /* UART7_RTS
*/
+, /* UART7_RX */
+; /*
UART7_CTS_NSS */
+ };
+ };
+
uart8_pins_a: uart8-0 {
pins1 {
pinmux = ; /* UART8_TX */
--
2.43.0
[PATCH 17/19] ARM: dts: stm32: Add alternate pinmux for MP13 UART4 pins
Add another mux option for UART4 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 30 +
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 65f91265a4d..7014c7a6d23 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -617,6 +617,36 @@
};
};
+ uart4_pins_b: uart4-1 {
+ pins1 {
+ pinmux = ; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = ; /* UART4_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart4_idle_pins_b: uart4-idle-1 {
+ pins1 {
+ pinmux = ; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = ; /* UART4_RX */
+ bias-pull-up;
+ };
+ };
+
+ uart4_sleep_pins_b: uart4-sleep-1 {
+ pins {
+ pinmux = , /* UART4_TX */
+; /* UART4_RX */
+ };
+ };
+
uart8_pins_a: uart8-0 {
pins1 {
pinmux = ; /* UART8_TX */
--
2.43.0
[PATCH 16/19] ARM: dts: stm32: Add alternate pinmux for MP13 USART2 pins
Add another mux option for USART2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 41 +
1 file changed, 41 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index dae015a0ddf..65f91265a4d 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -758,4 +758,45 @@
; /*
USART2_CTS_NSS */
};
};
+
+ usart2_pins_b: usart2-0 {
+ pins1 {
+ pinmux = , /* USART2_TX */
+; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = , /* USART2_RX */
+; /*
USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_b: usart2-idle-0 {
+ pins1 {
+ pinmux = , /* USART2_TX
*/
+; /*
USART2_CTS_NSS */
+ };
+ pins2 {
+ pinmux = ; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = ; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_b: usart2-sleep-0 {
+ pins {
+ pinmux = , /* USART2_TX
*/
+, /* USART2_RTS
*/
+, /* USART2_RX
*/
+; /*
USART2_CTS_NSS */
+ };
+ };
};
--
2.43.0
[PATCH 15/19] ARM: dts: stm32: Add alternate pinmux for MP13 USART1 pins
Add another mux option for USART1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 30 +
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 7abd227e69f..dae015a0ddf 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -688,6 +688,36 @@
};
};
+ usart1_pins_b: usart1-1 {
+ pins1 {
+ pinmux = ; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = ; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_idle_pins_b: usart1-idle-1 {
+ pins1 {
+ pinmux = ; /* USART1_TX */
+ };
+ pins2 {
+ pinmux = ; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart1_sleep_pins_b: usart1-sleep-1 {
+ pins {
+ pinmux = , /* USART1_TX */
+; /* USART1_RX
*/
+ };
+ };
+
usart2_pins_a: usart2-0 {
pins1 {
pinmux = , /* USART2_TX */
--
2.43.0
[PATCH 14/19] ARM: dts: stm32: Add alternate pinmux for MP13 SPI3 pins
Add another mux option for SPI3 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 17acd2850d3..7abd227e69f 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -534,6 +534,29 @@
};
};
+ spi3_pins_a: spi3-0 {
+ pins1 {
+ pinmux = , /* SPI3_SCK */
+; /* SPI3_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = ; /* SPI3_MISO */
+ bias-disable;
+ };
+ };
+
+ spi3_sleep_pins_a: spi3-sleep-0 {
+ pins {
+ pinmux = , /* SPI3_SCK */
+, /* SPI3_MISO */
+; /* SPI3_MOSI */
+ };
+ };
+
spi5_pins_a: spi5-0 {
pins1 {
pinmux = , /* SPI5_SCK */
--
2.43.0
[PATCH 13/19] ARM: dts: stm32: Add alternate pinmux for MP13 SPI2 pins
Add another mux option for SPI2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index c6967e82b5d..17acd2850d3 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -511,6 +511,29 @@
};
};
+ spi2_pins_a: spi2-0 {
+ pins1 {
+ pinmux = , /* SPI2_SCK */
+; /* SPI2_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = ; /* SPI2_MISO */
+ bias-disable;
+ };
+ };
+
+ spi2_sleep_pins_a: spi2-sleep-0 {
+ pins {
+ pinmux = , /* SPI2_SCK */
+, /* SPI2_MISO */
+; /* SPI2_MOSI
*/
+ };
+ };
+
spi5_pins_a: spi5-0 {
pins1 {
pinmux = , /* SPI5_SCK */
--
2.43.0
[PATCH 12/19] ARM: dts: stm32: Add alternate pinmux for MP13 SDMMC2 D4..D7 pins
Add another mux option for SDMMC2 D4..D7 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index f2b41104a58..c6967e82b5d 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -490,6 +490,27 @@
};
};
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
+ pins {
+ pinmux = , /* SDMMC2_D4 */
+, /* SDMMC2_D5 */
+, /* SDMMC2_D6 */
+; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
+ pins {
+ pinmux = , /* SDMMC2_D4 */
+, /* SDMMC2_D5 */
+, /* SDMMC2_D6 */
+; /* SDMMC2_D7 */
+ };
+ };
+
spi5_pins_a: spi5-0 {
pins1 {
pinmux = , /* SPI5_SCK */
--
2.43.0
[PATCH 11/19] ARM: dts: stm32: Add alternate pinmux for MP13 SAI1 pins
Add another mux option for SAI1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 32 +
1 file changed, 32 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 77a222903de..f2b41104a58 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -356,6 +356,38 @@
};
};
+ sai1a_pins_a: sai1a-0 {
+ pins {
+ pinmux = , /* SAI1_SCK_A */
+, /* SAI1_SD_A */
+; /* SAI1_FS_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai1a_sleep_pins_a: sai1a-sleep-0 {
+ pins {
+ pinmux = , /* SAI1_SCK_A
*/
+, /* SAI1_SD_A */
+; /* SAI1_FS_A
*/
+ };
+ };
+
+ sai1b_pins_a: sai1b-0 {
+ pins {
+ pinmux = ; /* SAI1_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai1b_sleep_pins_a: sai1b-sleep-0 {
+ pins {
+ pinmux = ; /* SAI1_SD_B */
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = , /* SDMMC1_D0 */
--
2.43.0
[PATCH 10/19] ARM: dts: stm32: Add alternate pinmux for MP13 QSPI pins
Add another mux option for QSPI pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 51 +
1 file changed, 51 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index cf070fbd7f7..77a222903de 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -305,6 +305,57 @@
};
};
+ qspi_clk_pins_a: qspi-clk-0 {
+ pins {
+ pinmux = ; /* QSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = ; /* QSPI_CLK */
+ };
+ };
+
+ qspi_bk1_pins_a: qspi-bk1-0 {
+ pins {
+ pinmux = , /* QSPI_BK1_IO0
*/
+, /* QSPI_BK1_IO1
*/
+, /* QSPI_BK1_IO2
*/
+; /* QSPI_BK1_IO3
*/
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+ pins {
+ pinmux = , /*
QSPI_BK1_IO0 */
+, /*
QSPI_BK1_IO1 */
+, /*
QSPI_BK1_IO2 */
+; /*
QSPI_BK1_IO3 */
+ };
+ };
+
+ qspi_cs1_pins_a: qspi-cs1-0 {
+ pins {
+ pinmux = ; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
+ pins {
+ pinmux = ; /*
QSPI_BK1_NCS */
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = , /* SDMMC1_D0 */
--
2.43.0
[PATCH 09/19] ARM: dts: stm32: Add alternate pinmux for MP13 PWM13 pins
Add another mux option for PWM13 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index d19408f19f9..cf070fbd7f7 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -275,6 +275,21 @@
};
};
+ pwm13_pins_a: pwm13-0 {
+ pins {
+ pinmux = ; /* TIM13_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm13_sleep_pins_a: pwm13-sleep-0 {
+ pins {
+ pinmux = ; /* TIM13_CH1 */
+ };
+ };
+
pwm14_pins_a: pwm14-0 {
pins {
pinmux = ; /* TIM14_CH1 */
--
2.43.0
[PATCH 08/19] ARM: dts: stm32: Add alternate pinmux for MP13 PWM5 pins
Add another mux option for PWM5 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index b58bf6c0024..d19408f19f9 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -245,6 +245,21 @@
};
};
+ pwm5_pins_a: pwm5-0 {
+ pins {
+ pinmux = ; /* TIM5_CH3 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm5_sleep_pins_a: pwm5-sleep-0 {
+ pins {
+ pinmux = ; /* TIM5_CH3 */
+ };
+ };
+
pwm8_pins_a: pwm8-0 {
pins {
pinmux = ; /* TIM8_CH3 */
--
2.43.0
[PATCH 07/19] ARM: dts: stm32: Add alternate pinmux for MP13 MCAN2 pins
Add another mux option for MCAN2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index b38174504ff..b58bf6c0024 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -188,6 +188,26 @@
};
};
+ m_can2_pins_a: m-can2-0 {
+ pins1 {
+ pinmux = ; /* CAN2_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = ; /* CAN2_RX */
+ bias-disable;
+ };
+ };
+
+ m_can2_sleep_pins_a: m_can2-sleep-0 {
+ pins {
+ pinmux = , /* CAN2_TX */
+; /* CAN2_RX */
+ };
+ };
+
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = ;
--
2.43.0
[PATCH 06/19] ARM: dts: stm32: Add alternate pinmux for MP13 MCAN1 pins
Add another mux option for MCAN1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index cfbae71efc7..b38174504ff 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -168,6 +168,26 @@
};
};
+ m_can1_pins_a: m-can1-0 {
+ pins1 {
+ pinmux = ; /* CAN1_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = ; /* CAN1_RX */
+ bias-disable;
+ };
+ };
+
+ m_can1_sleep_pins_a: m_can1-sleep-0 {
+ pins {
+ pinmux = , /* CAN1_TX */
+; /* CAN1_RX */
+ };
+ };
+
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = ;
--
2.43.0
[PATCH 05/19] ARM: dts: stm32: Add alternate pinmux for MP13 I2C5 pins
Add another mux option for I2C5 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 899f0f98e1a..cfbae71efc7 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -151,6 +151,23 @@
};
};
+ i2c5_pins_b: i2c5-1 {
+ pins {
+ pinmux = , /* I2C5_SCL */
+; /* I2C5_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_sleep_pins_b: i2c5-sleep-1 {
+ pins {
+ pinmux = , /* I2C5_SCL */
+; /* I2C5_SDA */
+ };
+ };
+
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = ;
--
2.43.0
[PATCH 04/19] ARM: dts: stm32: Add alternate pinmux for MP13 ETH2 pins
Add another mux option for ETH2 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 45 +
1 file changed, 45 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index c709d64edcc..899f0f98e1a 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -72,6 +72,51 @@
};
};
+ eth2_rgmii_pins_a: eth2-rgmii-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+, /* ETH_MDIO */
+; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = , /*
ETH_RGMII_RXD0 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD2 */
+, /*
ETH_RGMII_RXD3 */
+, /*
ETH_RGMII_RX_CTL */
+; /*
ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+ };
+
+ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+, /* ETH_MDIO */
+, /* ETH_MDC */
+, /*
ETH_RGMII_RXD0 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD2 */
+, /*
ETH_RGMII_RXD3 */
+, /*
ETH_RGMII_RX_CTL */
+; /*
ETH_RGMII_RX_CLK */
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = , /* I2C1_SCL */
--
2.43.0
[PATCH 03/19] ARM: dts: stm32: Add alternate pinmux for MP13 ETH1 pins
Add another mux option for ETH1 pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 46 +
1 file changed, 46 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 396fb6eee84..c709d64edcc 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -26,6 +26,52 @@
};
};
+ eth1_rgmii_pins_a: eth1-rgmii-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+, /* ETH_MDIO */
+; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = , /*
ETH_RGMII_RXD0 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD2 */
+, /*
ETH_RGMII_RXD3 */
+, /*
ETH_RGMII_RX_CTL */
+; /*
ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+
+ };
+
+ eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
+ pins1 {
+ pinmux = , /*
ETH_RGMII_TXD0 */
+, /*
ETH_RGMII_TXD1 */
+, /*
ETH_RGMII_TXD2 */
+, /*
ETH_RGMII_TXD3 */
+, /*
ETH_RGMII_TX_CTL */
+, /*
ETH_RGMII_GTX_CLK */
+, /* ETH_MDIO */
+, /* ETH_MDC */
+, /*
ETH_RGMII_RXD0 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RXD1 */
+, /*
ETH_RGMII_RX_CTL */
+; /*
ETH_RGMII_RX_CLK */
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = , /* I2C1_SCL */
--
2.43.0
[PATCH 02/19] ARM: dts: stm32: Add alternate pinmux for MP13 ADC CC pins
Add another mux option for ADC CC pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 03ded415390..396fb6eee84 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -19,6 +19,13 @@
};
};
+ adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
+ pins {
+ pinmux = , /* ADC1_INP2 */
+; /* ADC1_INP11
*/
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = , /* I2C1_SCL */
--
2.43.0
[PATCH 01/19] ARM: dts: stm32: Add alternate pinmux for MP13 ADC pins
Add another mux option for ADC pins, this is used on
DH electronics STM32MP13xx DHCOR DHSBC board.
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi
b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index 27e0c382678..03ded415390 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -6,6 +6,12 @@
#include
{
+ adc1_pins_a: adc1-pins-0 {
+ pins {
+ pinmux = ; /* ADC1 in12 */
+ };
+ };
+
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
pins {
pinmux = , /* ADC1 in6 */
--
2.43.0
[PATCH] ARM: dts: stm32: add eth1 and eth2 support on stm32mp13
From: Christophe Roullier
Add both ethernet MACs based on GMAC SNPS IP on stm32mp13.
Signed-off-by: Christophe Roullier
---
Cc: Christophe Roullier
Cc: Joe Hershberger
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Ramon Fried
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/dts/stm32mp131.dtsi | 37
arch/arm/dts/stm32mp133.dtsi | 30 +
2 files changed, 67 insertions(+)
diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
index 159ba8f8c9c..ad331b73d18 100644
--- a/arch/arm/dts/stm32mp131.dtsi
+++ b/arch/arm/dts/stm32mp131.dtsi
@@ -1328,6 +1328,37 @@
status = "disabled";
};
+ eth1: eth1@5800a000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800a000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = < GIC_SPI 62
IRQ_TYPE_LEVEL_HIGH>,
+ < 68 1>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = < ETH1MAC>,
+< ETH1TX>,
+< ETH1RX>,
+< ETH1STP>,
+< ETH1CK_K>;
+ st,syscon = < 0x4 0xff>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <_axi_config_1>;
+ snps,tso;
+ status = "disabled";
+
+ stmmac_axi_config_1: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+ };
+
usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
@@ -1404,6 +1435,12 @@
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
+ ethernet_mac1_address: mac1@e4 {
+ reg = <0xe4 0x6>;
+ };
+ ethernet_mac2_address: mac2@ea {
+ reg = <0xea 0x6>;
+ };
};
/*
diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi
index df451c3c2a2..5cd5bde9535 100644
--- a/arch/arm/dts/stm32mp133.dtsi
+++ b/arch/arm/dts/stm32mp133.dtsi
@@ -64,5 +64,35 @@
};
};
};
+
+ eth2: eth2@5800e000 {
+ compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
+ reg = <0x5800e000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = < GIC_SPI 97
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = < ETH2MAC>,
+< ETH2TX>,
+< ETH2RX>,
+< ETH2STP>,
+< ETH2CK_K>;
+ st,syscon = < 0x4 0xff00>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <_axi_config_2>;
+ snps,tso;
+ status = "disabled";
+
+ stmmac_axi_config_2: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+ };
};
};
--
2.43.0
Re: [PATCH] usb: dwc2: update reset method for host and device mode
On 3/28/24 2:14 PM, Kongyang Liu wrote:
[...]
@@ -464,12 +464,26 @@ static void reconfig_usbd(struct dwc2_udc *dev)
{
/* 2. Soft-reset OTG Core and then unreset again. */
int i;
- unsigned int uTemp = writel(CORE_SOFT_RESET, >grstctl);
+ unsigned int uTemp;
uint32_t dflt_gusbcfg;
uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
u32 max_hw_ep;
int pdata_hw_ep;
Drop this newline
+ u32 snpsid, greset;
+
+ snpsid = readl(>gsnpsid);
+ writel(CORE_SOFT_RESET, >grstctl);
+ if ((snpsid & SNPSID_VER_MASK) < (SNPSID_VER_420a & SNPSID_VER_MASK)) {
Can you use FIELD_GET()/FIELD_PREP() for this ?
+ wait_for_bit_le32(>grstctl, CORE_SOFT_RESET, false, 1000,
false);
+ } else {
+ wait_for_bit_le32(>grstctl, CORE_SOFT_RESET_DONE, true,
1000, false);
+ greset = readl(>grstctl);
+ greset &= ~CORE_SOFT_RESET;
+ greset |= CORE_SOFT_RESET_DONE;
+ writel(greset, >grstctl);
clrsetbits_le32()
[...]
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 637eb2dd06..1baeff96ee 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -159,6 +159,7 @@ static void dwc_otg_core_reset(struct udevice *dev,
struct dwc2_core_regs *regs)
{
int ret;
+ u32 snpsid, greset;
/* Wait for AHB master IDLE state. */
ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_AHBIDLE,
@@ -167,9 +168,20 @@ static void dwc_otg_core_reset(struct udevice *dev,
dev_info(dev, "%s: Timeout!\n", __func__);
/* Core Soft Reset */
+ snpsid = readl(>gsnpsid);
writel(DWC2_GRSTCTL_CSFTRST, >grstctl);
- ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
- false, 1000, false);
+ if ((snpsid & DWC2_SNPSID_VER_MASK) < (DWC2_SNPSID_DEVID_VER_420a &
DWC2_SNPSID_VER_MASK)) {
+ ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
+ false, 1000, false);
+ } else {
+ ret = wait_for_bit_le32(>grstctl,
DWC2_GRSTCTL_GSFTRST_DONE,
+ true, 1000, false);
+ greset = readl(>grstctl);
+ greset &= ~DWC2_GRSTCTL_CSFTRST;
+ greset |= DWC2_GRSTCTL_GSFTRST_DONE;
+ writel(greset, >grstctl);
Same comments as above.
Maybe this should be pulled into dedicated function to avoid duplication?
+ }
+
if (ret)
dev_info(dev, "%s: Timeout!\n", __func__);
@@ -1180,7 +1192,8 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
snpsid >> 12 & 0xf, snpsid & 0xfff);
if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
- (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
+ (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx
&&
+ (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_4xx) {
Try FIELD_GET/FIELD_PREP
Re: [PATCH] usb: dwc3: support USB 3.1 controllers
On 4/11/24 6:05 PM, Caleb Connolly wrote: The revision is different for these, add the additional check as in xhci-dwc3 core_init code. Signed-off-by: Caleb Connolly Is there a matching Linux kernel patch , or does Linux do some other check ?
Re: [PATCH 1/2] ARM: dts: stm32: add PWR regulators support on stm32mp131
On 3/19/24 3:45 AM, Marek Vasut wrote: This patch adds STM32 PWR regulators DT support on stm32mp131. This requires TFA to clear RCC_SECCFGR, is disabled by default and can only be enabled on board DT level. Signed-off-by: Marek Vasut It seems these patches have been missed from the recent PR ? Is there any feedback on those patches ?
[PATCH] ARM: stm32: Ping IWDG on exit from PSCI suspend code
Make sure the OS would not get any spurious IWDG pretimeout IRQ
right after the system wakes up. This may happen in case the SoC
got woken up by another source than the IWDG pretimeout and the
pretimeout IRQ arrived immediately afterward, but too late to be
handled by the suspend main loop. In case either of the IWDG is
enabled, ping it first and then return to the OS.
Signed-off-by: Marek Vasut
---
Cc: Igor Opaniuk
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Simon Glass
Cc: Tom Rini
Cc: u-b...@dh-electronics.com
Cc: uboot-st...@st-md-mailman.stormreply.com
---
arch/arm/mach-stm32mp/stm32mp1/psci.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c
b/arch/arm/mach-stm32mp/stm32mp1/psci.c
index 4f2379df45f..e99103910d9 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/psci.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c
@@ -808,6 +808,27 @@ void __secure psci_system_suspend(u32 __always_unused
function_id,
writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+ /*
+* Make sure the OS would not get any spurious IWDG pretimeout IRQ
+* right after the system wakes up. This may happen in case the SoC
+* got woken up by another source than the IWDG pretimeout and the
+* pretimeout IRQ arrived immediately afterward, but too late to be
+* handled by the main loop above. In case either of the IWDG is
+* enabled, ping it first and then return to the OS.
+*/
+
+ /* Ping IWDG1 and ACK pretimer IRQ */
+ if (gic_enabled[4] & BIT(22)) {
+ writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR);
+ writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR);
+ }
+
+ /* Ping IWDG2 and ACK pretimer IRQ */
+ if (gic_enabled[4] & BIT(23)) {
+ writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
+ writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
+ }
+
/*
* The system has resumed successfully. Rewrite LR register stored
* on stack with 'ep' value, so that on return from this PSCI call,
--
2.43.0
Re: [PATCH v3 1/3] clk: imx8mm: Add support for PCIe clocks
On 4/19/24 5:29 PM, Tim Harvey wrote: Add support for PCIe clocks required to enable PCIe support on iMX8MM SoC. Signed-off-by: Tim Harvey Reviewed-by: Marek Vasut
Re: [PATCH v2] ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx
On 4/18/24 8:24 PM, Patrick DELAUNAY wrote:
Hi,
Hi,
[...]
@@ -136,6 +140,18 @@ static void security_init(void)
*/
writel(0x0, TAMP_CR1);
+ /*
+ * TAMP: Configure non-zero secure protection settings. This is
+ * checked by BootROM function 35ac on OTP-CLOSED device during
+ * CPU core 1 release from endless loop. If secure protection
+ * fields are zero, the core 1 is not released from endless
+ * loop on second SGI0.
+ */
+ clrsetbits_le32(TAMP_SMCR,
+ TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT,
+ FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x10) |
+ FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x10));
+
/* GPIOZ: deactivate the security */
writel(BIT(0), RCC_MP_AHB5ENSETR);
writel(0x0, GPIOZ_SECCFGR);
The recommended mapping (the mapping done in OP-TEE for OpenSTLinux) is
described in Wiki page
- 10 backup register secure
- 4 backup register secure write / non secure read
- 17 backup register Non-secure
It is done in
https://github.com/STMicroelectronics/optee_os/blob/3.19.0-stm32mp/core/arch/arm/plat-stm32mp1/main.c
with
static TEE_Result stm32_configure_tamp(void)
{
TEE_Result res __maybe_unused = TEE_SUCCESS;
struct stm32_bkpregs_conf bkpregs_conf = {
.nb_zone1_regs = 10, /* 10 registers in zone 1 */
.nb_zone2_regs = 5 /* 5 registers in zone 2 */
/* Zone3 all remaining */
};
/* Enable BKP Register protection */
if (stm32_tamp_set_secure_bkpregs(_conf))
panic();
But when you are booting with SPL U-boot, all the boot chain and the
Linux kernel
is running in secure world
So you have no reason to manage any limit for the access to backup
register,
you can allocate all the backup registers (the 32 one) to secure world
See "Figure 552. Backup registers secure protections" in reference mnauel
Protection zone 1 => x = 31 with BKPRWDPROT = 31
Protection zone 2 & 3 => empty
+ clrsetbits_le32(TAMP_SMCR,
+ TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT,
+ FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) |
+ FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20));
Sorry for the delay, I need also to check on my side
But anyway your proposal is functional,
So with or without the previous remark
Thank you for the detailed explanation and for checking this.
V3 is coming now.
[PATCH v3] ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx
In case of an OTP-CLOSED STM32MP15xx system, the CPU core 1 cannot be released from endless loop in BootROM only by populating TAMP BKPxR 4 and 5 with magic and branch address and sending SGI0 interrupt from core 0 to core 1 twice. TAMP_SMCR BKP..PROT fields must be initialized as well to release the core 1 from endless loop during the second SGI0 handling on core 1. Initialize TAMP_SMCR to protect the first 32 backup registers, the ones which contain the core 1 magic, branch address and boot information. This requirement seems to be undocumented, therefore it was necessary to trace and analyze the STM32MP15xx BootROM using OpenOCD and objdump. Ultimately, it turns out that a certain BootROM function reads out the TAMP_SMCR register and tests whether the BKP..PROT fields are non-zero. If they are zero, the BootROM code again waits for SGI0 using WFI, else the execution moves forward until it reaches handoff to the TAMP BKPxR 5 branch address. This fixes CPU core 1 release using U-Boot PSCI implementation on an OTP-CLOSED system, i.e. system with fuse 0 bit 6 set. Reviewed-by: Patrick Delaunay Signed-off-by: Marek Vasut --- Cc: Igor Opaniuk Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Tom Rini Cc: u-b...@dh-electronics.com Cc: uboot-st...@st-md-mailman.stormreply.com --- V2: Fix up the BKPRWD/BKPWD mask typo V3: - Update the allocation to 0x20/0x20 - Update commit message - Add RB from Patrick --- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index dd99150fbc2..d75ec99d6a1 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -14,6 +14,7 @@ #include #include #include +#include /* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -41,6 +42,9 @@ #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROTGENMASK(23, 16) #define PWR_CR1(STM32_PWR_BASE + 0x00) #define PWR_MCUCR (STM32_PWR_BASE + 0x14) @@ -136,6 +140,18 @@ static void security_init(void) */ writel(0x0, TAMP_CR1); + /* +* TAMP: Configure non-zero secure protection settings. This is +* checked by BootROM function 35ac on OTP-CLOSED device during +* CPU core 1 release from endless loop. If secure protection +* fields are zero, the core 1 is not released from endless +* loop on second SGI0. +*/ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT, + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20)); + /* GPIOZ: deactivate the security */ writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); -- 2.43.0
Re: [PATCH] ARM: imx: Enable kaslrseed command on DH i.MX8M Plus DHCOM
On 4/18/24 8:02 PM, Fabio Estevam wrote:
Hi Tim,
On Thu, Apr 18, 2024 at 2:54 PM Tim Harvey wrote:
Fabio, if you enable CONFIG_DM_RNG on an imx8m{m,p}_evk do you get the
following in the SPL?
Couldn't bind rng driver (-96)
SEC0: RNG instantiated
sec_init failed!
Yes, if I add CONFIG_DM_RNG=y to imx8mm_evk_defconfig I get:
U-Boot SPL 2024.04-00793-g3434b88d2c2f-dirty (Apr 18 2024 - 14:58:57 -0300)
No pmic
Couldn't bind rng driver (-96)
SEC0: RNG instantiated
sec_init failed!
Interesting. Which TFA blob version do you use ? I used the mainline
2.10 for my tests.
btw. 'no pmic' ? Is that expected ?
Re: [PATCH v2 1/3] clk: imx8mm: Add support for PCIe clocks
On 4/18/24 8:24 PM, Tim Harvey wrote:
On Thu, Apr 18, 2024 at 11:14 AM Marek Vasut wrote:
On 4/18/24 7:56 PM, Tim Harvey wrote:
Add support for PCIe clocks required to enable PCIe support on
iMX8MM SoC.
Signed-off-by: Tim Harvey
---
v2: no changes
---
drivers/clk/imx/clk-imx8mm.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index b5c253e49663..c2f01b385201 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -66,6 +66,15 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_
static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out",
"sys_pll1_133m", };
+static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m",
"sys_pll2_200m", "sys_pll1_266m",
+"sys_pll1_800m", "sys_pll2_500m",
"sys_pll2_333m", "sys_pll3_out", };
+
+static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m",
"clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4",
"sys_pll1_400m", };
+
+static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m",
"sys_pll2_50m", "sys_pll3_out",
+ "sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_160m", "sys_pll1_200m", };
+
#ifndef CONFIG_SPL_BUILD
static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
"sys_pll3_out", "clk_ext1", "sys_pll1_80m",
"video_pll1_out", };
@@ -256,6 +265,15 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base +
0x8b80));
/* IP */
+ clk_dm(IMX8MM_CLK_PCIE1_CTRL,
+imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
+base + 0xa300));
+ clk_dm(IMX8MM_CLK_PCIE1_PHY,
+imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
+base + 0xa380));
+ clk_dm(IMX8MM_CLK_PCIE1_AUX,
+imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
+base + 0xa400));
Maybe this should be behind IS_ENABLED() like the SPI clock to avoid
growth of SPL ?
Makes sense... I'll add that in a v3. Thanks for the review!
Of course, glad I could help.
Re: [PATCH v2 1/3] clk: imx8mm: Add support for PCIe clocks
On 4/18/24 7:56 PM, Tim Harvey wrote:
Add support for PCIe clocks required to enable PCIe support on
iMX8MM SoC.
Signed-off-by: Tim Harvey
---
v2: no changes
---
drivers/clk/imx/clk-imx8mm.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index b5c253e49663..c2f01b385201 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -66,6 +66,15 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m",
"sys_pll1_160m", "sys_
static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out",
"sys_pll1_133m", };
+static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
+ "sys_pll1_800m", "sys_pll2_500m",
"sys_pll2_333m", "sys_pll3_out", };
+
+static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m",
"clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4",
"sys_pll1_400m", };
+
+static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m",
"sys_pll2_50m", "sys_pll3_out",
+ "sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_160m", "sys_pll1_200m", };
+
#ifndef CONFIG_SPL_BUILD
static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m",
"sys_pll1_160m", "sys_pll1_40m",
"sys_pll3_out", "clk_ext1", "sys_pll1_80m",
"video_pll1_out", };
@@ -256,6 +265,15 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base +
0x8b80));
/* IP */
+ clk_dm(IMX8MM_CLK_PCIE1_CTRL,
+ imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
+ base + 0xa300));
+ clk_dm(IMX8MM_CLK_PCIE1_PHY,
+ imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
+ base + 0xa380));
+ clk_dm(IMX8MM_CLK_PCIE1_AUX,
+ imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
+ base + 0xa400));
Maybe this should be behind IS_ENABLED() like the SPI clock to avoid
growth of SPL ?
Re: [PATCH v2 2/3] pci: dw_imx: add support for IMX8MM
On 4/18/24 7:56 PM, Tim Harvey wrote: Add support for the IMX8MM SoC by adding driver data with the compatible string of the GPR controller. Signed-off-by: Tim Harvey Reviewed-by: Marek Vasut
Re: [PATCH] ARM: imx: Enable kaslrseed command on DH i.MX8M Plus DHCOM
On 4/18/24 6:21 PM, Tim Harvey wrote:
On Fri, Jan 19, 2024 at 4:36 PM Marek Vasut wrote:
Linux 6.6.y with KASLR enabled would print the following message on boot:
"
KASLR disabled due to lack of seed
"
Enable the 'kaslrseed' command so a random number seed can be pulled
from CAAM and inserted into the /chosen node 'kaslr-seed' property of
Linux kernel DT before boot, thus letting KASLR work properly.
Signed-off-by: Marek Vasut
---
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: u-b...@dh-electronics.com
---
configs/imx8mp_dhcom_pdk2_defconfig | 2 ++
configs/imx8mp_dhcom_pdk3_defconfig | 2 ++
2 files changed, 4 insertions(+)
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig
b/configs/imx8mp_dhcom_pdk2_defconfig
index 4f907ce00d0..23fb6272ad5 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -117,6 +117,7 @@ CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
+CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
@@ -223,6 +224,7 @@ CONFIG_DM_REGULATOR_PCA9450=y
CONFIG_SPL_DM_REGULATOR_PCA9450=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RNG=y
CONFIG_DM_RTC=y
CONFIG_RTC_M41T62=y
CONFIG_CONS_INDEX=2
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig
b/configs/imx8mp_dhcom_pdk3_defconfig
index 9972e2d96b6..0d47c12b1f9 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -119,6 +119,7 @@ CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
+CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
@@ -228,6 +229,7 @@ CONFIG_DM_REGULATOR_PCA9450=y
CONFIG_SPL_DM_REGULATOR_PCA9450=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RNG=y
CONFIG_DM_RTC=y
CONFIG_RTC_M41T62=y
CONFIG_CONS_INDEX=2
--
2.43.0
Hi Marek,
Sorry to respond to an old thread but I ran across this when enabling
KALSR on my boards.
I have noticed when you enable DM_RNG on IMX8M that SPL fails to bind
the driver:
Couldn't bind rng driver (-96)
SEC0: RNG instantiated
sec_init failed!
Did you enable CAAM and ARCH_MISC_INIT on your machine, to initialize
CAAM in SPL ?
Didn't you encounter this as well? It seems to me that we may need to
add the ability to disable DM_RNG in the SPL unless I'm missing
something.
No, but see above, I suspect that might be it, see also
1f908b1898bd ("ARM: imx8m: Deduplicate CAAM init with arch_misc_init()
call")
Re: [PATCH v2 00/11] net: dwc_eth_qos: Clean up STM32 glue code and add STM32MP13xx support
On 4/18/24 1:36 PM, Patrice CHOTARD wrote: On 4/17/24 18:47, Marek Vasut wrote: On 3/26/24 1:07 PM, Marek Vasut wrote: Split off STM32 glue code from the DWMAC driver into separate file, similar to what other SoCs already do, to avoid mixing the ST specifics with generic DWMAC core code. Clean the STM32 DWMAC board code which is currently duplicated in multiple board files, move it into the newly separated glue code, since the code is not board specific, it is only generic DT parsing and generic register programming. Add STM32MP13xx support based on ST downstream patches on top, although that part is mostly rewritten from scratch. Can either of you, Patrice/Patrick, pick this series via ST tree and create a MR for Tom (possibly including the other long outstanding patches too) ? Thanks Hi Marek STM32 pull request will be done tomorrow. Thank you
[PULL] u-boot-sh/master-fdt
The following changes since commit a712a54dc427708195e6405af4b072d869d0dd8f:
Merge patch series "configs: ti: Enable basic settings for SystemReady ACS"
(2024-04-17 13:16:12 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-sh.git master-fdt
for you to fetch changes up to aad511a488c40393728156333d983c31001aac32:
ARM: dts: renesas: Switch to using upstream DT (2024-04-18 05:21:26 +0200)
--------
Marek Vasut (4):
ARM: dts: renesas: Stop using the -u-boot DTs for build
ARM: dts: renesas: Replace R8A77950 with R8A77951
ARM: dts: renesas: Switch to using upstream DT on 64bit Renesas SoCs
ARM: dts: renesas: Switch to using upstream DT
arch/arm/Kconfig | 1 +
arch/arm/dts/Makefile | 58 +++---
...ch-u-boot.dts => r7s72100-gr-peach-u-boot.dtsi} | 1 -
...-boot.dts => r8a774a1-hihope-rzg2m-u-boot.dtsi} | 1 -
...-boot.dts => r8a774b1-hihope-rzg2n-u-boot.dtsi} | 1 -
...ek874-u-boot.dts => r8a774c0-ek874-u-boot.dtsi} | 1 -
...-boot.dts => r8a774e1-hihope-rzg2h-u-boot.dtsi} | 1 -
...-lager-u-boot.dts => r8a7790-lager-u-boot.dtsi} | 1 -
...-stout-u-boot.dts => r8a7790-stout-u-boot.dtsi} | 1 -
...lsch-u-boot.dts => r8a7791-koelsch-u-boot.dtsi} | 1 -
...orter-u-boot.dts => r8a7791-porter-u-boot.dtsi} | 1 -
...nche-u-boot.dts => r8a7792-blanche-u-boot.dtsi} | 1 -
...93-gose-u-boot.dts => r8a7793-gose-u-boot.dtsi} | 1 -
...7794-alt-u-boot.dts => r8a7794-alt-u-boot.dtsi} | 1 -
...94-silk-u-boot.dts => r8a7794-silk-u-boot.dtsi} | 1 -
...-u-boot.dts => r8a77951-salvator-x-u-boot.dtsi} | 3 +-
.../{r8a77950-u-boot.dtsi => r8a77951-u-boot.dtsi} | 6 ---
...0-ulcb-u-boot.dts => r8a77951-ulcb-u-boot.dtsi} | 3 +-
...-u-boot.dts => r8a77960-salvator-x-u-boot.dtsi} | 1 -
...0-ulcb-u-boot.dts => r8a77960-ulcb-u-boot.dtsi} | 1 -
...-u-boot.dts => r8a77965-salvator-x-u-boot.dtsi} | 1 -
...5-ulcb-u-boot.dts => r8a77965-ulcb-u-boot.dtsi} | 1 -
...eagle-u-boot.dts => r8a77970-eagle-u-boot.dtsi} | 1 -
...v3msk-u-boot.dts => r8a77970-v3msk-u-boot.dtsi} | 1 -
...ndor-u-boot.dts => r8a77980-condor-u-boot.dtsi} | 1 -
...v3hsk-u-boot.dts => r8a77980-v3hsk-u-boot.dtsi} | 1 -
...ebisu-u-boot.dts => r8a77990-ebisu-u-boot.dtsi} | 1 -
...draak-u-boot.dts => r8a77995-draak-u-boot.dtsi} | 1 -
...lcon-u-boot.dts => r8a779a0-falcon-u-boot.dtsi} | 1 -
...ider-u-boot.dts => r8a779f0-spider-u-boot.dtsi} | 1 -
...-u-boot.dts => r8a779g0-white-hawk-u-boot.dtsi} | 1 -
...k-u-boot.dts => r8a779h0-gray-hawk-u-boot.dtsi} | 1 -
arch/arm/mach-renesas/Kconfig | 1 +
board/renesas/salvator-x/salvator-x.c | 6 +--
board/renesas/ulcb/ulcb.c | 6 +--
configs/alt_defconfig | 2 +-
configs/blanche_defconfig | 2 +-
configs/gose_defconfig | 2 +-
configs/grpeach_defconfig | 2 +-
configs/hihope_rzg2_defconfig | 4 +-
configs/koelsch_defconfig | 2 +-
configs/lager_defconfig| 2 +-
configs/porter_defconfig | 2 +-
configs/r8a77970_eagle_defconfig | 2 +-
configs/r8a77970_v3msk_defconfig | 2 +-
configs/r8a77980_condor_defconfig | 2 +-
configs/r8a77980_v3hsk_defconfig | 2 +-
configs/r8a77990_ebisu_defconfig | 2 +-
configs/r8a77995_draak_defconfig | 2 +-
configs/r8a779a0_falcon_defconfig | 2 +-
configs/r8a779f0_spider_defconfig | 2 +-
configs/r8a779g0_whitehawk_defconfig | 2 +-
configs/r8a779h0_grayhawk_defconfig| 3 +-
configs/rcar3_salvator-x_defconfig | 8 +--
configs/rcar3_ulcb_defconfig | 8 +--
configs/renesas_rzg2l_smarc_defconfig | 2 +-
configs/rzg2_beacon_defconfig | 4 +-
configs/rzn1_snarc_defconfig | 1 +
configs/silinux_ek874_defconfig| 2 +-
configs/silk_defconfig | 2 +-
configs/stout_defconfig| 2 +-
61 files changed, 74 insertions(+), 105 deletions(-)
rename arch/arm/dts/{r7s72100-gr-peach-u-boot.dts =>
r7s72100-gr-peach-u-boot.dtsi} (97%)
rename arch/arm/dts/{r8a774a1-hihope-rzg2m-u-boot.dts =>
r8a774a1-hihope-rzg2m-u-boot.dtsi} (91%)
rename arch/arm/dts/{r8a774b1-hihope-rzg2n-u-boot.dts =>
r8a774b1-hihope-rzg2n-u-boot.dtsi} (91%)
rename arch/arm/dts/{r8a774c0-ek874-u-boot.dts => r8a774c0-ek874-u-boot.dtsi}
(95%)
rename arch/arm/
Re: [PATCH 2/3] pci: dw_imx: add support for IMX8MM
On 4/17/24 10:09 PM, Tim Harvey wrote:
Add support for the IMX8MM SoC by adding driver data with the compatible
string of the GPR controller.
Signed-off-by: Tim Harvey
---
drivers/pci/pcie_dw_imx.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c
index a2ee228224b5..10d926c30645 100644
--- a/drivers/pci/pcie_dw_imx.c
+++ b/drivers/pci/pcie_dw_imx.c
@@ -45,6 +45,10 @@
#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_ENBIT(10)
#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
+struct pcie_chip_info {
+ const char *gpr;
+};
+
struct pcie_dw_imx {
/* Must be first member of the struct */
struct pcie_dw dw;
@@ -54,6 +58,15 @@ struct pcie_dw_imx {
struct reset_ctlapps_reset;
struct phy phy;
struct udevice *vpcie;
+ struct pcie_chip_info *info;
+};
+
+static const struct pcie_chip_info imx8mm_chip_info = {
+ .gpr = "fsl,imx8mm-iomuxc-gpr",
+};
+
+static const struct pcie_chip_info imx8mp_chip_info = {
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
};
static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
@@ -246,6 +259,8 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
ofnode gpr;
int ret;
+ priv->info = (void *)dev_get_driver_data(dev);
+
Does this really have to be cached in priv ?
The priv->info seems used only in this function.
[...]
Re: [PATCH v2 00/11] net: dwc_eth_qos: Clean up STM32 glue code and add STM32MP13xx support
On 3/26/24 1:07 PM, Marek Vasut wrote: Split off STM32 glue code from the DWMAC driver into separate file, similar to what other SoCs already do, to avoid mixing the ST specifics with generic DWMAC core code. Clean the STM32 DWMAC board code which is currently duplicated in multiple board files, move it into the newly separated glue code, since the code is not board specific, it is only generic DT parsing and generic register programming. Add STM32MP13xx support based on ST downstream patches on top, although that part is mostly rewritten from scratch. Can either of you, Patrice/Patrick, pick this series via ST tree and create a MR for Tom (possibly including the other long outstanding patches too) ? Thanks
Re: [Patch] dwc_eth_qos: Revert regression handling fixed phy
On 4/17/24 10:41 AM, Nicole Battenfeld wrote: Subject: [PATCH] dwc_eth_qos: Revert regression handling fixed phy In imx8mp operation on eqos with fixed phy I get without that patch: ERROR: no/invalid Which commit is being reverted here ?
Re: [PATCH] ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx
On 4/15/24 11:48 AM, Patrice CHOTARD wrote: On 4/14/24 20:39, Marek Vasut wrote: In case of an OTP-CLOSED STM32MP15xx system, the CPU core 1 cannot be released from endless loop in BootROM only by populating TAMP BKPxR 4 and 5 with magic and branch address and sending SGI0 interrupt from core 0 to core 1 twice. TAMP_SMCR BKP..PROT fields must be initialized as well to release the core 1 from endless loop during the second SGI0 handling on core 1. Initialize TAMP_SMCR to protect the first 16 backup registers, the ones which contain the core 1 magic, branch address and boot information. This requirement seems to be undocumented, therefore it was necessary to trace and analyze the STM32MP15xx BootROM using OpenOCD and objdump. Ultimately, it turns out that a certain BootROM function reads out the TAMP_SMCR register and tests whether the BKP..PROT fields are non-zero. If they are zero, the BootROM code again waits for SGI0 using WFI, else the execution moves forward until it reaches handoff to the TAMP BKPxR 5 branch address. This fixes CPU core 1 release using U-Boot PSCI implementation on an OTP-CLOSED system, i.e. system with fuse 0 bit 6 set. Signed-off-by: Marek Vasut --- Cc: Igor Opaniuk Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Tom Rini Cc: u-b...@dh-electronics.com Cc: uboot-st...@st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index dd99150fbc2..138a6d6b614 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -14,6 +14,7 @@ #include #include #include +#include /* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -41,6 +42,9 @@ #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROTGENMASK(23, 16) #define PWR_CR1 (STM32_PWR_BASE + 0x00) #define PWR_MCUCR (STM32_PWR_BASE + 0x14) @@ -136,6 +140,18 @@ static void security_init(void) */ writel(0x0, TAMP_CR1); + /* +* TAMP: Configure non-zero secure protection settings. This is +* checked by BootROM function 35ac on OTP-CLOSED device during +* CPU core 1 release from endless loop. If secure protection +* fields are zero, the core 1 is not released from endless +* loop on second SGI0. +*/ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPRWDPROT, Hi Marek there is a typo, you used twice TAMP_SMCR_BKPRWDPROT : TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPRWDPROT => TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT ^ Fixed in V2, thanks. btw are there any other such undocumented surprises in the BootROM ?
[PATCH v2] ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx
In case of an OTP-CLOSED STM32MP15xx system, the CPU core 1 cannot be released from endless loop in BootROM only by populating TAMP BKPxR 4 and 5 with magic and branch address and sending SGI0 interrupt from core 0 to core 1 twice. TAMP_SMCR BKP..PROT fields must be initialized as well to release the core 1 from endless loop during the second SGI0 handling on core 1. Initialize TAMP_SMCR to protect the first 16 backup registers, the ones which contain the core 1 magic, branch address and boot information. This requirement seems to be undocumented, therefore it was necessary to trace and analyze the STM32MP15xx BootROM using OpenOCD and objdump. Ultimately, it turns out that a certain BootROM function reads out the TAMP_SMCR register and tests whether the BKP..PROT fields are non-zero. If they are zero, the BootROM code again waits for SGI0 using WFI, else the execution moves forward until it reaches handoff to the TAMP BKPxR 5 branch address. This fixes CPU core 1 release using U-Boot PSCI implementation on an OTP-CLOSED system, i.e. system with fuse 0 bit 6 set. Signed-off-by: Marek Vasut --- Cc: Igor Opaniuk Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Tom Rini Cc: u-b...@dh-electronics.com Cc: uboot-st...@st-md-mailman.stormreply.com --- V2: Fix up the BKPRWD/BKPWD mask typo --- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index dd99150fbc2..a2496361e01 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -14,6 +14,7 @@ #include #include #include +#include /* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -41,6 +42,9 @@ #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROTGENMASK(23, 16) #define PWR_CR1(STM32_PWR_BASE + 0x00) #define PWR_MCUCR (STM32_PWR_BASE + 0x14) @@ -136,6 +140,18 @@ static void security_init(void) */ writel(0x0, TAMP_CR1); + /* +* TAMP: Configure non-zero secure protection settings. This is +* checked by BootROM function 35ac on OTP-CLOSED device during +* CPU core 1 release from endless loop. If secure protection +* fields are zero, the core 1 is not released from endless +* loop on second SGI0. +*/ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT, + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x10) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x10)); + /* GPIOZ: deactivate the security */ writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); -- 2.43.0
Re: [PATCH] boot: fdt: Turn all addresses and sizes into u64
On 4/14/24 11:28 PM, Laurent Pinchart wrote: On Sun, Apr 14, 2024 at 11:25:06PM +0200, Marek Vasut wrote: On 4/14/24 9:29 PM, Laurent Pinchart wrote: Hi Marek, Thank you for the patch. On Sun, Apr 14, 2024 at 08:37:20PM +0200, Marek Vasut wrote: In case of systems where DRAM bank ends at the edge of 32bit boundary, start + size calculations would overflow. This happens on STM32MP15xx with 1 DRAM bank starting at 0xc000 and 1 GiB of DRAM. This is a usual 32bit system DRAM size overflow, fix it by doing all DRAM size and offset calculations using u64 types. I'm not sure I like this much, as it removes a useful indication regarding what the variables store. That's what the variable name is for, not variable type. Wouldn't it be better if the code's logic could be modified to avoid those overflows ? I'd prefer to keep the code simple and blanket avoid the overflows for a very long time, rather than play whack-a-mole with various odd corner cases here. Up to you. Note that this is a fix for a previous series which changed from u64/ulong to phys_addr/size_t , which clearly was incorrect . This also covers a case where a 32bit PAE system might be able to address up to 36bits of DRAM. Shouldn't phys_addr_t be a 64-bit type on PAE systems ? That depends on CONFIG_PHYS_64BIT , on am57xx this is not set for example, so there phys_addr_t is 32bit . The system won't be able to address more than 32 bits of memory in that case, would it ? It might do so through some memory window, like PCIe, but I never used the am57xx so I cannot tell what it really does.
Re: [PATCH] boot: fdt: Turn all addresses and sizes into u64
On 4/14/24 9:29 PM, Laurent Pinchart wrote: Hi Marek, Thank you for the patch. On Sun, Apr 14, 2024 at 08:37:20PM +0200, Marek Vasut wrote: In case of systems where DRAM bank ends at the edge of 32bit boundary, start + size calculations would overflow. This happens on STM32MP15xx with 1 DRAM bank starting at 0xc000 and 1 GiB of DRAM. This is a usual 32bit system DRAM size overflow, fix it by doing all DRAM size and offset calculations using u64 types. I'm not sure I like this much, as it removes a useful indication regarding what the variables store. That's what the variable name is for, not variable type. Wouldn't it be better if the code's logic could be modified to avoid those overflows ? I'd prefer to keep the code simple and blanket avoid the overflows for a very long time, rather than play whack-a-mole with various odd corner cases here. Note that this is a fix for a previous series which changed from u64/ulong to phys_addr/size_t , which clearly was incorrect . This also covers a case where a 32bit PAE system might be able to address up to 36bits of DRAM. Shouldn't phys_addr_t be a 64-bit type on PAE systems ? That depends on CONFIG_PHYS_64BIT , on am57xx this is not set for example, so there phys_addr_t is 32bit .
[PULL] u-boot-usb/master
The following changes since commit cdfcc37428e06f4730ab9a17cc084eeb7676ea1a: Merge tag 'u-boot-dfu-next-20240402' of https://source.denx.de/u-boot/custodians/u-boot-dfu (2024-04-02 22:37:23 -0400) are available in the Git repository at: git://source.denx.de/u-boot-usb.git master for you to fetch changes up to 63f6a449bffe46beca89580d3efa48e5d041025c: usb: kbd: Add probe quirk for Apple and Keychron keyboards (2024-04-12 14:53:13 +0200) Janne Grunau (6): usb: xhci: refactor xhci_set_configuration usb: xhci: Set up endpoints for the first 2 interfaces usb: xhci: Abort transfers with unallocated rings usb: Add environment based device ignorelist usb: kbd: support Apple Magic Keyboards (2021) usb: kbd: Add probe quirk for Apple and Keychron keyboards common/usb.c | 70 common/usb_kbd.c | 59 ++-- doc/usage/environment.rst| 13 + drivers/usb/host/xhci-ring.c | 5 ++ drivers/usb/host/xhci.c | 126 +++ include/env_default.h| 11 include/usb.h| 6 +++ 7 files changed, 241 insertions(+), 49 deletions(-)
[PATCH] ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx
In case of an OTP-CLOSED STM32MP15xx system, the CPU core 1 cannot be released from endless loop in BootROM only by populating TAMP BKPxR 4 and 5 with magic and branch address and sending SGI0 interrupt from core 0 to core 1 twice. TAMP_SMCR BKP..PROT fields must be initialized as well to release the core 1 from endless loop during the second SGI0 handling on core 1. Initialize TAMP_SMCR to protect the first 16 backup registers, the ones which contain the core 1 magic, branch address and boot information. This requirement seems to be undocumented, therefore it was necessary to trace and analyze the STM32MP15xx BootROM using OpenOCD and objdump. Ultimately, it turns out that a certain BootROM function reads out the TAMP_SMCR register and tests whether the BKP..PROT fields are non-zero. If they are zero, the BootROM code again waits for SGI0 using WFI, else the execution moves forward until it reaches handoff to the TAMP BKPxR 5 branch address. This fixes CPU core 1 release using U-Boot PSCI implementation on an OTP-CLOSED system, i.e. system with fuse 0 bit 6 set. Signed-off-by: Marek Vasut --- Cc: Igor Opaniuk Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Tom Rini Cc: u-b...@dh-electronics.com Cc: uboot-st...@st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index dd99150fbc2..138a6d6b614 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -14,6 +14,7 @@ #include #include #include +#include /* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -41,6 +42,9 @@ #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROTGENMASK(23, 16) #define PWR_CR1(STM32_PWR_BASE + 0x00) #define PWR_MCUCR (STM32_PWR_BASE + 0x14) @@ -136,6 +140,18 @@ static void security_init(void) */ writel(0x0, TAMP_CR1); + /* +* TAMP: Configure non-zero secure protection settings. This is +* checked by BootROM function 35ac on OTP-CLOSED device during +* CPU core 1 release from endless loop. If secure protection +* fields are zero, the core 1 is not released from endless +* loop on second SGI0. +*/ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPRWDPROT, + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x10) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x10)); + /* GPIOZ: deactivate the security */ writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); -- 2.43.0
