Re: [PATCH v4 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
Hi Kever, On 4/26/24 09:41, Kever Yang wrote: Hi Quentin, On 2024/4/25 18:46, Quentin Schulz wrote: From: Quentin Schulz Allow RK3568 and RK3588 based boards to get the RAM bank configuration from the ROCKCHIP_TPL stage instead of the current logic. This fixes both an issue where 256MB of RAM is blocked for devices with >= 4GB of RAM and where memory holes need to be defined for devices with more than 16GB of RAM. In the event that neither SoC is used or the ROCKCHIP_TPL stage is not used, fall back to existing logic. The logic handles creating memory holes from reserved memory areas defined in mem_map data struct in SoC C files, but only if the DRAM area overlaps with one reserved memory area. Since mem_map data struct is used, it should be rather straightforward to add support for other SoCs if needed. The logic is taken from Rockchip's U-Boot tag linux-5.10-gen-rkr4.1 (e08e32143dd). Note that Rockchip's U-Boot/TF-A/OP-TEE modify the ATAGS at runtime as well, but the DDR_MEM tag seems to be pretty much stable (though BL31 seems to be reserving only 1MB for itself at the moment). u32 for ATAGS is used because it simplifies the pointer arithmetic and it's expected that ATAGS are always below the 4GB limit allowed by u32. Co-developed-by: Chris Morgan Signed-off-by: Chris Morgan Signed-off-by: Quentin Schulz This breaks rv1126 build which is non ARM64 platform, I can fix it and apply it directly. Thanks! Cheers, Quentin
[PATCH v4 11/11] rockchip: rk356x: use DRAM banks from ATAGS
From: Quentin Schulz RK356x-based devices now support creating DRAM banks with proper holes by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism instead. The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for reading banks from ATAGS, so let's use the default value instead. Co-developed-by: Chris Morgan Signed-off-by: Chris Morgan Signed-off-by: Quentin Schulz --- configs/anbernic-rgxx3-rk3566_defconfig | 1 - configs/bpi-r2-pro-rk3568_defconfig | 1 - configs/evb-rk3568_defconfig | 1 - configs/generic-rk3568_defconfig | 1 - configs/lubancat-2-rk3568_defconfig | 1 - configs/nanopi-r5c-rk3568_defconfig | 1 - configs/nanopi-r5s-rk3568_defconfig | 1 - configs/odroid-m1-rk3568_defconfig| 1 - configs/pinetab2-rk3566_defconfig | 1 - configs/quartz64-a-rk3566_defconfig | 1 - configs/quartz64-b-rk3566_defconfig | 1 - configs/radxa-cm3-io-rk3566_defconfig | 1 - configs/radxa-e25-rk3568_defconfig| 1 - configs/rock-3a-rk3568_defconfig | 1 - configs/soquartz-blade-rk3566_defconfig | 1 - configs/soquartz-cm4-rk3566_defconfig | 1 - configs/soquartz-model-a-rk3566_defconfig | 1 - 17 files changed, 17 deletions(-) diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig index c8c9238f96f..aa3809e00c1 100644 --- a/configs/anbernic-rgxx3-rk3566_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig index 5cc95241ba4..0f85dc63c55 100644 --- a/configs/bpi-r2-pro-rk3568_defconfig +++ b/configs/bpi-r2-pro-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index 6e8061f5f48..f2f429d33c4 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index e7d5e55bbfd..8f4a6259a27 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig index 1c50a0ccbe6..ea67b6a7286 100644 --- a/configs/lubancat-2-rk3568_defconfig +++ b/configs/lubancat-2-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig index 0f1a9461a0c..00743b7f926 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 4ebf0cc9ee8..91e3a19dea6 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig index b5ed9e4bc98..e749f9af9d2 100644 --- a/configs/odroid-m1-rk3568_defconfig +++ b/configs/odroid-m1-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=2400 CONFIG_SF_DEFAULT_MODE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1" diff --git a/configs/
[PATCH v4 10/11] rockchip: rk3588: use DRAM banks from ATAGS
From: Quentin Schulz RK3588-based devices now support creating DRAM banks with proper holes by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism instead. The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for reading banks from ATAGS, so let's use the default value instead. Co-developed-by: Chris Morgan Signed-off-by: Chris Morgan Signed-off-by: Quentin Schulz --- configs/jaguar-rk3588_defconfig | 1 - configs/neu6a-io-rk3588_defconfig | 1 - configs/neu6b-io-rk3588_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 3233b75cee9..f29505ea150 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=2400 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_ENV_SIZE=0x1f000 diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index 307a540f424..2b939e6795f 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig index 9ef2bb21fff..d0fa0dca7ac 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y -- 2.44.0
[PATCH v4 09/11] rockchip: turing-rk1-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the turing-rk1-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/turing/turing-rk1-rk3588/Makefile| 6
board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c | 39 --
configs/turing-rk1-rk3588_defconfig| 2 --
3 files changed, 47 deletions(-)
diff --git a/board/turing/turing-rk1-rk3588/Makefile
b/board/turing/turing-rk1-rk3588/Makefile
deleted file mode 100644
index a979d8023aa..000
--- a/board/turing/turing-rk1-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += turing-rk1-rk3588.o
diff --git a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
b/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
deleted file mode 100644
index e2338a2a35a..000
--- a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int turing_rk1_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return turing_rk1_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/turing-rk1-rk3588_defconfig
b/configs/turing-rk1-rk3588_defconfig
index e18ced72178..49d62410ca0 100644
--- a/configs/turing-rk1-rk3588_defconfig
+++ b/configs/turing-rk1-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1"
@@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v4 08/11] rockchip: toybrick_rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the toybrick_rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/rockchip/toybrick_rk3588/Makefile | 6
board/rockchip/toybrick_rk3588/toybrick-rk3588.c | 39
configs/toybrick-rk3588_defconfig| 2 --
3 files changed, 47 deletions(-)
diff --git a/board/rockchip/toybrick_rk3588/Makefile
b/board/rockchip/toybrick_rk3588/Makefile
deleted file mode 100644
index 75d4d9438f7..000
--- a/board/rockchip/toybrick_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += toybrick-rk3588.o
diff --git a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
deleted file mode 100644
index e3217f70b50..000
--- a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/toybrick-rk3588_defconfig
b/configs/toybrick-rk3588_defconfig
index 6ee92e94313..675e7d89e12 100644
--- a/configs/toybrick-rk3588_defconfig
+++ b/configs/toybrick-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v4 07/11] rockchip: evb_rk3588 et al.: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the evb_rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
All defconfigs using the CONFIG_TARGET_EVB_RK3588 are updated at once
since they are impacted by this change.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/rockchip/evb_rk3588/Makefile | 6 -
board/rockchip/evb_rk3588/evb-rk3588.c | 39
configs/coolpi-4b-rk3588s_defconfig | 2 --
configs/coolpi-cm5-evb-rk3588_defconfig | 2 --
configs/evb-rk3588_defconfig | 2 --
configs/generic-rk3588_defconfig | 2 --
configs/orangepi-5-plus-rk3588_defconfig | 2 --
configs/orangepi-5-rk3588s_defconfig | 2 --
8 files changed, 57 deletions(-)
diff --git a/board/rockchip/evb_rk3588/Makefile
b/board/rockchip/evb_rk3588/Makefile
deleted file mode 100644
index 240d2ec597e..000
--- a/board/rockchip/evb_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += evb-rk3588.o
diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c
b/board/rockchip/evb_rk3588/evb-rk3588.c
deleted file mode 100644
index caf94d8d29c..000
--- a/board/rockchip/evb_rk3588/evb-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/coolpi-4b-rk3588s_defconfig
b/configs/coolpi-4b-rk3588s_defconfig
index a0fe3708344..2608bb67679 100644
--- a/configs/coolpi-4b-rk3588s_defconfig
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig
b/configs/coolpi-cm5-evb-rk3588_defconfig
index fc17660da2a..c5bb7a42957 100644
--- a/configs/coolpi-cm5-evb-rk3588_defconfig
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index c8db04c076e..187cf26a5c9 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FI
[PATCH v4 06/11] rockchip: rock5b-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the rock5b-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/radxa/rock5b-rk3588/Makefile| 6 -
board/radxa/rock5b-rk3588/rock5b-rk3588.c | 39 ---
configs/rock5b-rk3588_defconfig | 2 --
3 files changed, 47 deletions(-)
diff --git a/board/radxa/rock5b-rk3588/Makefile
b/board/radxa/rock5b-rk3588/Makefile
deleted file mode 100644
index 95d813596da..000
--- a/board/radxa/rock5b-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2022 Collabora Ltd.
-#
-
-obj-y += rock5b-rk3588.o
diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
deleted file mode 100644
index 5c3b52b9489..000
--- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5b_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rock5b_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index ac4f1ebb4c1..ea8e3593572 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
@@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v4 05/11] rockchip: rock5a-rk3588s: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the rock5a-rk3588s.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/radxa/rock5a-rk3588s/Makefile | 6 -
board/radxa/rock5a-rk3588s/rock5a-rk3588s.c | 39 -
configs/rock5a-rk3588s_defconfig| 2 --
3 files changed, 47 deletions(-)
diff --git a/board/radxa/rock5a-rk3588s/Makefile
b/board/radxa/rock5a-rk3588s/Makefile
deleted file mode 100644
index 48dd5124550..000
--- a/board/radxa/rock5a-rk3588s/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Collabora Ltd.
-#
-
-obj-y += rock5a-rk3588s.o
diff --git a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
deleted file mode 100644
index 2d7a8c07dc5..000
--- a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5a_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rock5a_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index ebe2d4a2d81..01df911d9dc 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v4 04/11] rockchip: quartzpro64-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the quartzpro64-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/pine64/quartzpro64-rk3588/Makefile | 3 --
.../pine64/quartzpro64-rk3588/quartzpro64-rk3588.c | 39 --
configs/quartzpro64-rk3588_defconfig | 2 --
3 files changed, 44 deletions(-)
diff --git a/board/pine64/quartzpro64-rk3588/Makefile
b/board/pine64/quartzpro64-rk3588/Makefile
deleted file mode 100644
index 47819d9be93..000
--- a/board/pine64/quartzpro64-rk3588/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += quartzpro64-rk3588.o
diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
deleted file mode 100644
index bda804a89e2..000
--- a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2023 Google, Inc
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return quartzpro64_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/quartzpro64-rk3588_defconfig
b/configs/quartzpro64-rk3588_defconfig
index b2a66d3f2db..e398c7c2c0e 100644
--- a/configs/quartzpro64-rk3588_defconfig
+++ b/configs/quartzpro64-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -19,7 +18,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v4 03/11] rockchip: nanopc-t6-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the nanopc-t6-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/friendlyelec/nanopc-t6-rk3588/Makefile | 6
.../nanopc-t6-rk3588/nanopc-t6-rk3588.c| 39 --
configs/nanopc-t6-rk3588_defconfig | 2 --
3 files changed, 47 deletions(-)
diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile
b/board/friendlyelec/nanopc-t6-rk3588/Makefile
deleted file mode 100644
index c1c49b19708..000
--- a/board/friendlyelec/nanopc-t6-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += nanopc-t6-rk3588.o
diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
deleted file mode 100644
index 99bbef964e0..000
--- a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int nanopc_t6_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return nanopc_t6_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/nanopc-t6-rk3588_defconfig
b/configs/nanopc-t6-rk3588_defconfig
index 5c7bc0b7196..738dda026b0 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v4 02/11] rockchip: NR_DRAM_BANKS now defaults to 10 when Rockchip TPL blob is used
From: Quentin Schulz When Rockchip TPL blob is used, the memory areas that can be used for DRAM is gotten from ATAGS passed through the DRAM at a specific address. The DDR_MEM tag contains at most 10 areas, so we should default to 10 if Rockchip TPL blob is used. Note that it is technically possible we need more if one of those 10 areas overlaps with reserved memory area, forcing us to split it in two. But a default doesn't need to handle all cases, only most. Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 4f22d9bde9f..644f7997a29 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -574,6 +574,9 @@ config ROCKCHIP_COMMON_STACK_ADDR imply TPL_SYS_MALLOC_F if TPL imply TPL_SYS_MALLOC_SIMPLE if TPL +config NR_DRAM_BANKS + default 10 if ROCKCHIP_EXTERNAL_TPL + source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3066/Kconfig" -- 2.44.0
[PATCH v4 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
From: Quentin Schulz
Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with
more than 16GB of RAM. In the event that neither SoC is used or the
ROCKCHIP_TPL stage is not used, fall back to existing logic.
The logic handles creating memory holes from reserved memory areas
defined in mem_map data struct in SoC C files, but only if the DRAM area
overlaps with one reserved memory area.
Since mem_map data struct is used, it should be rather straightforward
to add support for other SoCs if needed.
The logic is taken from Rockchip's U-Boot tag linux-5.10-gen-rkr4.1
(e08e32143dd).
Note that Rockchip's U-Boot/TF-A/OP-TEE modify the ATAGS at runtime as
well, but the DDR_MEM tag seems to be pretty much stable (though BL31
seems to be reserving only 1MB for itself at the moment).
u32 for ATAGS is used because it simplifies the pointer arithmetic and
it's expected that ATAGS are always below the 4GB limit allowed by u32.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
arch/arm/mach-rockchip/sdram.c | 258 +
1 file changed, 258 insertions(+)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0aef6f5..405a998cb84 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -35,12 +36,269 @@ struct tos_parameter_t {
s64 reserve[8];
};
+/* Tag size and offset */
+#define ATAGS_SIZE SZ_8K
+#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE)
+#define ATAGS_PHYS_BASE(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+#define ATAGS_PHYS_END (ATAGS_PHYS_BASE + ATAGS_SIZE)
+
+/* ATAGS memory structures */
+
+enum tag_magic {
+ ATAG_NONE,
+ ATAG_CORE = 0x54410001,
+ ATAG_SERIAL = 0x54410050,
+ ATAG_DDR_MEM = 0x54410052,
+ ATAG_MAX = 0x544100ff,
+};
+
+/*
+ * An ATAG contains the following data:
+ * - header
+ *u32 size // sizeof(header + tag data) / sizeof(u32)
+ *u32 magic
+ * - tag data
+ */
+
+struct tag_header {
+ u32 size;
+ u32 magic;
+} __packed;
+
+/*
+ * DDR_MEM tag bank is storing data this way:
+ * - address0
+ * - address1
+ * - [...]
+ * - addressX
+ * - size0
+ * - size1
+ * - [...]
+ * - sizeX
+ *
+ * with X being tag_ddr_mem.count - 1.
+ */
+struct tag_ddr_mem {
+ u32 count;
+ u32 version;
+ u64 bank[20];
+ u32 flags;
+ u32 data[2];
+ u32 hash;
+} __packed;
+
+static u32 js_hash(const void *buf, u32 len)
+{
+ u32 i, hash = 0x47C6A7E6;
+
+ if (!buf || !len)
+ return hash;
+
+ for (i = 0; i < len; i++)
+ hash ^= ((hash << 5) + ((const char *)buf)[i] + (hash >> 2));
+
+ return hash;
+}
+
+static int rockchip_dram_init_banksize(void)
+{
+ const struct tag_header *tag_h = NULL;
+ u32 *addr = (void *)ATAGS_PHYS_BASE;
+ struct tag_ddr_mem *ddr_info;
+ u32 calc_hash;
+ u8 i, j;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ return -ENOTSUPP;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
+ return -ENOTSUPP;
+
+ /* Find DDR_MEM tag */
+ while (addr < (u32 *)ATAGS_PHYS_END) {
+ tag_h = (const struct tag_header *)addr;
+
+ if (!tag_h->size) {
+ debug("End of ATAGS (0-size tag), no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ if (tag_h->magic == ATAG_DDR_MEM)
+ break;
+
+ switch (tag_h->magic) {
+ case ATAG_NONE:
+ case ATAG_CORE:
+ case ATAG_SERIAL ... ATAG_MAX:
+ addr += tag_h->size;
+ continue;
+ default:
+ debug("Invalid magic (0x%08x) for ATAG at 0x%p\n",
+ tag_h->magic, addr);
+ return -EINVAL;
+ }
+ }
+
+ if (addr >= (u32 *)ATAGS_PHYS_END ||
+ (tag_h && (addr + tag_h->size > (u32 *)ATAGS_PHYS_END))) {
+ debug("End of ATAGS, no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ /* Data is right after the magic member of the tag_header struct */
+ ddr_info = (struct tag_ddr_mem *)(_h->magic + 1);
+ if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS) {
+ debug("Too many ATAG banks, got (%d) but max allowed (%d)\n",
+
[PATCH v4 00/11] rockchip: Support getting DRAM banks from TPL for rk3568 and rk3588
x0004fdf882ff - 0x0004fdf88300 pattern [0.00] 0x0004fdf8832f - 0x0004fdf88330 pattern [0.00] 0x0004fdf8835f - 0x0004fdf88360 pattern [0.00] 0x0004fdf8838f - 0x0004fdf88390 pattern [0.00] 0x0004fdf883bf - 0x0004fdf883c0 pattern [0.00] 0x0004fdf883ef - 0x0004fdf883f0 pattern [0.00] 0x0004fdf8841c - 0x0004fdf88420 pattern [0.00] 0x0004fdf8844c - 0x0004fdf88450 pattern [0.00] 0x0004fdf8847c - 0x0004fdf88480 pattern [0.00] 0x0004fdf884ac - 0x0004fdf884b0 pattern [0.00] 0x0004fdf884dc - 0x0004fdf884e0 pattern [0.00] 0x0004fdf8850c - 0x0004fdf88510 pattern [0.00] 0x0004fdf8853c - 0x0004fdf88540 pattern [0.00] 0x0004fdf8856c - 0x0004fdf88570 pattern [0.00] 0x0004fdf8859c - 0x0004fdf885a0 pattern [0.00] 0x0004fdf885cd - 0x0004fdf885d0 pattern [0.00] 0x0004fdf885fd - 0x0004fdf88600 pattern [0.00] 0x0004fdf8862d - 0x0004fdf88630 pattern [0.00] 0x0004fdf8865d - 0x0004fdf88660 pattern [0.00] 0x0004fdf8868d - 0x0004fdf88690 pattern $ lsmem --output SIZE --bytes --json | jq '[.memory[].size] | add / 1024 / 1024 / 1024' 16 """ I tested on Rock5B 16GB that without the memory holes and without using this new logic, the kernel fails this memtest, so this test seems valid. This has NOT been tested on RK356x as I don't own any. Note that the logic for excluding DRAM memory areas from the memory areas to consider for putting holes in DRAM banks based on mem_map struct may conflict with SDRAM, ROM or flashes if we ever add those to the SoC's mem_map... Something we can tackle the day we do it, it's good enough for now. Co-Developed-by: Chris Morgan Signed-off-by: Quentin Schulz --- Changes in v4: - fix infinite while loop if there's no hole to create by incrementing the pointer in the no-match path, - fix identification of non-DRAM memory areas in mem_map by checking for PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE instead of looking for ! PTE_BLOCK_NON_SHARE since PTE_BLOCK_NON_SHARE is 0 so using it as a mask always makes the result the same value, regardless of the other operand, - Link to v3: https://lore.kernel.org/r/20240415-rk35xx-dram-atags-v3-0-5bc5475b3...@theobroma-systems.com Changes in v3: - Split board migration to new DRAM ATAGS mechanism into separate commits, - Use mem_map instead of hardcoded values for reserved memory area for MMIO, - Add tag hash check to match Rockchip's downstream implementation, - Bail from while loop as soon as a tag with no size is encountered to match Rockchip's downstream implementation, - Use enum instead of constants for ATAG magic, - Add debug messages and comments, - Fix atags traversal by using tag size instead of checking every 16B, - Migrate Jaguar to new mechanism, - Default NR_DRAM_BANKS to 10 when ROCKCHIP_EXTERNAL_TPL is used so the default allows to use this new logic, - Define tag_header data struct to parse the first two bytes of a tag more easily, - Do not stop at CORE magic, directly look for DDR_MEM, - Bail from while loop as soon as an unknown tag is used to match Rockchip's downstream implementation, - Use phys_size_t and phys_addr_t wherever possible, Link to v2: https://lore.kernel.org/u-boot/20240401181435.553351-1-macroalph...@gmail.com/ Link to v1: https://lore.kernel.org/u-boot/20240330050515.470025-1-macroalph...@gmail.com/ --- Quentin Schulz (11): rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588 rockchip: NR_DRAM_BANKS now defaults to 10 when Rockchip TPL blob is used rockchip: nanopc-t6-rk3588: use DRAM banks from ATAGS rockchip: quartzpro64-rk3588: use DRAM banks from ATAGS rockchip: rock5a-rk3588s: use DRAM banks from ATAGS rockchip: rock5b-rk3588: use DRAM banks from ATAGS rockchip: evb_rk3588 et al.: use DRAM banks from ATAGS rockchip: toybrick_rk3588: use DRAM banks from ATAGS rockchip: turing-rk1-rk3588: use DRAM banks from ATAGS rockchip: rk3588: use DRAM banks from ATAGS rockchip: rk356x: use DRAM banks from ATAGS arch/arm/mach-rockchip/Kconfig | 3 + arch/arm/mach-rockchip/sdram.c | 258 + board/friendlyelec/nanopc-t6-rk3588/Makefile | 6 - .../nanopc-t6-rk3588/nanopc-t6-rk3588.c| 39 board/pine64/quartzpro64-rk3588/Mak
Re: [PATCH 2/2] armv8: generic_timer: Use event stream for udelay
Hi Peter, Andre,
On 4/24/24 12:29, Andre Przywara wrote:
On Tue, 23 Apr 2024 12:55:55 +0200
Quentin Schulz wrote:
Hi Peter,
On 4/23/24 10:10, Peter Hoyes wrote:
From: Peter Hoyes
Polling cntpct_el0 in a tight loop for delays is inefficient.
This is particularly apparent on Arm FVPs, which do not simulate
real time, meaning that a 1s sleep can take a couple of orders
of magnitude longer to execute in wall time.
If running at EL2 or above (where CNTHCTL_EL2 is available), enable
the cntpct_el0 event stream temporarily and use wfe to implement
the delay more efficiently. The event period is chosen as a
trade-off between efficiency and the fact that Arm FVPs do not
typically simulate real time.
This is only implemented for Armv8 boards, where an architectural
timer exists.
Some mach-socfpga AArch64 boards already override __udelay to make
it always inline, so guard the functionality with a new
ARMV8_UDELAY_EVENT_STREAM Kconfig, enabled by default.
Signed-off-by: Peter Hoyes
---
arch/arm/cpu/armv8/Kconfig | 8
arch/arm/cpu/armv8/generic_timer.c | 27 +++
arch/arm/include/asm/system.h | 6 --
3 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 9f0fb369f7..544c5e2d74 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -191,6 +191,14 @@ config ARMV8_EA_EL3_FIRST
Exception handling at all exception levels for External Abort and
SError interrupt exception are taken in EL3.
+config ARMV8_UDELAY_EVENT_STREAM
+ bool "Use the event stream for udelay"
+ default y if !ARCH_SOCFPGA
+ help
+ Use the event stream provided by the AArch64 architectural timer for
+ delays. This is more efficient than the default polling
+ implementation.
+
menuconfig ARMV8_CRYPTO
bool "ARM64 Accelerated Cryptographic Algorithms"
diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
index 8f83372cbc..e18b5c8187 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -115,3 +115,30 @@ ulong timer_get_boot_us(void)
return val / get_tbclk();
}
+
+#if CONFIG_IS_ENABLED(ARMV8_UDELAY_EVENT_STREAM)
+void __udelay(unsigned long usec)
+{
+ u64 target = get_ticks() + usec_to_tick(usec);
+
This can theoretically overflow, do we have any guarantee this cannot
happen in real life, like... we would need U-Boot to be running for 100
years without being powered-down/reset or something like that? Can we
document this assumption? Does this make sense?
The Arm ARM guarantees a "Roll-over time of not less than 40 years."
(Armv8 ARM 0487K.a D12.1.2 "The system counter").
So that's not the 100 years you are asking for, but I guess still good
enough?
I guess it is, since it is also stored in a u64 and is reset to 0 upon
start-up according to the ARM. I also assume nobody is going to add a
udelay of years in their code :) (and if they do, they would probably
figure out something's wrong before it reaches the final products :) ).
Thanks all for the pointers to reference manuals and current
implementations.
Cheers,
Quentin
Re: [PATCH v3 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
Hi Jonas,
On 4/24/24 00:40, Jonas Karlman wrote:
Hi Quentin,
On 2024-04-15 16:16, Quentin Schulz wrote:
From: Quentin Schulz
[...]
+ if (!(tmp_mem_map->attrs & PTE_BLOCK_NON_SHARE)) {
This check does not seem to work because PTE_BLOCK_NON_SHARE evaluates
to 0. Because of this the logic to split the 0-8 GiB bank reported on
rk3568 is never split in two.
Oof, that's a bit oversight, thanks for the catch.
Can you test the following please?
"""
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 5b1ff1e5495..0492f9b9f41 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -196,7 +196,23 @@ static int rockchip_dram_init_banksize(void)
const phys_size_t rsrv_size = tmp_mem_map->size;
const phys_addr_t rsrv_end = rsrv_start + rsrv_size;
- if (!(tmp_mem_map->attrs & PTE_BLOCK_NON_SHARE)) {
+ /*
+* DRAM memories are expected by Arm to be marked as
+* Normal Write-back cacheable, Inner shareable[1], so
+* let's filter on that to put holes in non-DRAM areas.
+*
+ * [1]
https://developer.arm.com/documentation/102376/0200/Cacheability-and-shareability-attributes
+*/
+ const u64 dram_attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ /*
+* (AttrIndx | SH) in Lower Attributes of Block
+* Descriptor[2].
+ * [2]
https://developer.arm.com/documentation/102376/0200/Describing-memory-in-AArch64
+*/
+ const u64 attrs_mask = PMD_ATTRINDX_MASK | GENMASK(9,
8);
+
+ if ((tmp_mem_map->attrs & attrs_mask) == dram_attrs) {
tmp_mem_map++;
continue;
}
"""
The DRAM mem_map entry for Rockchip devices seems to have those
attributes and no other non-DRAM entry seems to have
PTE_BLOCK_MEMTYPE(MT_NORMAL).
We may have an issue in the future if we also want to mark SRAM, ROM or
flash
(https://developer.arm.com/documentation/102376/0200/Normal-memory)
because it's likely those would also match the same attributes but we
would need to put holes for those so that they aren't thought to be
DRAM, but I guess we can tackle this the day this happens :)
Thanks again for the catch, let me know if this helps and makes sense
and I'll send a v4 for it.
Cheers,
Quentin
Re: [PATCH 2/2] armv8: generic_timer: Use event stream for udelay
Hi Peter,
On 4/23/24 10:10, Peter Hoyes wrote:
From: Peter Hoyes
Polling cntpct_el0 in a tight loop for delays is inefficient.
This is particularly apparent on Arm FVPs, which do not simulate
real time, meaning that a 1s sleep can take a couple of orders
of magnitude longer to execute in wall time.
If running at EL2 or above (where CNTHCTL_EL2 is available), enable
the cntpct_el0 event stream temporarily and use wfe to implement
the delay more efficiently. The event period is chosen as a
trade-off between efficiency and the fact that Arm FVPs do not
typically simulate real time.
This is only implemented for Armv8 boards, where an architectural
timer exists.
Some mach-socfpga AArch64 boards already override __udelay to make
it always inline, so guard the functionality with a new
ARMV8_UDELAY_EVENT_STREAM Kconfig, enabled by default.
Signed-off-by: Peter Hoyes
---
arch/arm/cpu/armv8/Kconfig | 8
arch/arm/cpu/armv8/generic_timer.c | 27 +++
arch/arm/include/asm/system.h | 6 --
3 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 9f0fb369f7..544c5e2d74 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -191,6 +191,14 @@ config ARMV8_EA_EL3_FIRST
Exception handling at all exception levels for External Abort and
SError interrupt exception are taken in EL3.
+config ARMV8_UDELAY_EVENT_STREAM
+ bool "Use the event stream for udelay"
+ default y if !ARCH_SOCFPGA
+ help
+ Use the event stream provided by the AArch64 architectural timer for
+ delays. This is more efficient than the default polling
+ implementation.
+
menuconfig ARMV8_CRYPTO
bool "ARM64 Accelerated Cryptographic Algorithms"
diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
index 8f83372cbc..e18b5c8187 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -115,3 +115,30 @@ ulong timer_get_boot_us(void)
return val / get_tbclk();
}
+
+#if CONFIG_IS_ENABLED(ARMV8_UDELAY_EVENT_STREAM)
+void __udelay(unsigned long usec)
+{
+ u64 target = get_ticks() + usec_to_tick(usec);
+
This can theoretically overflow, do we have any guarantee this cannot
happen in real life, like... we would need U-Boot to be running for 100
years without being powered-down/reset or something like that? Can we
document this assumption? Does this make sense?
+ /* At EL2 or above, use the event stream to avoid polling CNTPCT_EL0 so
often */
+ if (current_el() >= 2) {
+ u32 cnthctl_val;
+ const u8 event_period = 0x7;
+
+ asm volatile("mrs %0, cnthctl_el2" : "=r" (cnthctl_val));
+ asm volatile("msr cnthctl_el2, %0" : : "r"
+ (cnthctl_val | CNTHCTL_EL2_EVNT_EN |
CNTHCTL_EL2_EVNT_I(event_period)));
+
+ while (get_ticks() + (1ULL << event_period) <= target)
This could be an overflow as well.
+ wfe();
+
+ /* Reset the event stream */
+ asm volatile("msr cnthctl_el2, %0" : : "r" (cnthctl_val));
+ }
+
+ /* Fall back to polling CNTPCT_EL0 */
+ while (get_ticks() <= target)
get_ticks() could wrap around here maybe?
Cheers,
Quentin
[PATCH v2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module
From: Quentin Schulz
The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3588.
It provides the following feature set:
* up to 16GB LPDDR4x
* on-module eMMC
* SD card (on a baseboard) via edge connector
* Gigabit Ethernet with on-module GbE PHY
* HDMI/eDP
* MIPI-DSI
* 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
* HDMI input over FPC connector
* CAN
* USB
- 1x USB 3.0 dual-role (direct connection)
- 2x USB 3.0 host + 1x USB 2.0 host
* PCIe
- 1x PCIe 2.1 Gen3, 4 lanes
- 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
* on-module ATtiny816 companion controller, implementing:
- low-power RTC functionality (ISL1208 emulation)
- fan controller (AMC6821 emulation)
* on-module Secure Element with Global Platform 2.2.1 compliant
JavaCard environment
The support is added for Tiger on Haikou devkit, similarly to RK3399
Puma and PX30 Ringneck.
The DTS and DTSI are taken from upstream Linux kernel v6.9-rc4.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
This has a light dependency on
https://lore.kernel.org/u-boot/20240415-rk35xx-dram-atags-v3-0-5bc5475b3...@theobroma-systems.com/
(the Tiger defconfig can be updated to remove the dependency if required)
To: Tom Rini
To: Klaus Goger
To: Heiko Stuebner
To: Simon Glass
To: Philipp Tomsich
To: Kever Yang
Cc: u-boot@lists.denx.de
Signed-off-by: Quentin Schulz
Changes in v2:
- removed uart controller muxing patch as not necessary until we get
open-source DRAM init,
- disabled DEBUG_UART_BOARD_INIT as it's only used for muxing the UART
controller and it's not necessary since DDR bin does this for us
already,
- added missing uart2 mux bootph in U-Boot dtsi (though not required
yet),
- switched to USB_DWC3_GENERIC from USB_XHCI_DWC3 as requested by Jonas,
- Link to v1:
https://lore.kernel.org/r/20240422-tiger-v1-0-8816b070d...@theobroma-systems.com
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi | 59 ++
arch/arm/dts/rk3588-tiger-haikou.dts | 266
arch/arm/dts/rk3588-tiger.dtsi | 690 +
arch/arm/mach-rockchip/rk3588/Kconfig | 31 +
board/theobroma-systems/tiger_rk3588/Kconfig | 16 +
board/theobroma-systems/tiger_rk3588/MAINTAINERS | 13 +
board/theobroma-systems/tiger_rk3588/Makefile | 10 +
.../theobroma-systems/tiger_rk3588/tiger_rk3588.c | 53 ++
configs/tiger-rk3588_defconfig | 114
doc/board/rockchip/rockchip.rst| 1 +
doc/board/theobroma-systems/index.rst | 1 +
doc/board/theobroma-systems/tiger_rk3588.rst | 102 +++
include/configs/tiger_rk3588.h | 15 +
14 files changed, 1372 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c9c6222e5..ef901642a0a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -180,6 +180,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb \
+ rk3588-tiger-haikou.dtb \
rk3588-turing-rk1.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
new file mode 100644
index 000..bfcefe256b0
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+_pwrseq {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+_reset {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+ {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+ {
+ /* U-Boot currently cannot handle anything below HS200 for eMMC on
RK3588 */
+ /delete-property/ mmc-ddr-1_8v;
+ /delete-property/ cap-mmc-highspeed;
+};
+
+/* Q7 USB P0 */
+ {
+ status = "okay";
+};
+
+_otg {
+ status = "okay";
+};
+
+_xfer {
+ bootph-all;
+};
+
+/* Q7 USB P0 */
+_phy1 {
+ status = "okay";
+};
+
+_phy1_u3 {
+ status = "okay";
+};
+
+_host1_xhci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-tiger-haikou.dts
b/arch/arm/dts/rk3588-tiger-haikou.dts
new file mode 100644
index 000..d672198c6b6
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou.dts
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include
+#include "rk3588-tiger.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3588-Q7 SoM on Haikou devkit";
+ compati
Re: [PATCH 2/2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module
Hi Jonas,
On 4/22/24 19:54, Jonas Karlman wrote:
Hi Quentin,
On 2024-04-22 18:41, Quentin Schulz wrote:
From: Quentin Schulz
[...]
diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
new file mode 100644
index 000..4259399193a
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
[...]
Following should be added to possible fix uart2 pinctrl in SPL:
_xfer {
bootph-all;
};
Would only be useful once we get rid of DDR bin, but will do it now
because I have a feeling I would forget otherwise :)
Thanks for catching this though.
[...]
[snip]
diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig
new file mode 100644
index 000..6545445bba1
--- /dev/null
+++ b/configs/tiger-rk3588_defconfig
[...]
+CONFIG_USB_XHCI_DWC3=y
Please use USB_DWC3_GENERIC instead of USB_XHCI_DWC3.
Dang, I thought I was using "the correct one".
It's very difficult to know which one to pick right now, would it be
possible to update the help message to guide the users a bit more in
their choice? I don't really have a clue why one is "better" than the
other so wouldn't be able to suggest something.
Cheers,
Quentin
Re: [PATCH 1/2] rockchip: rk3588: add support for UART2 M1 and M2 in SPL
Hi Kever, On 4/23/24 03:09, Kever Yang wrote: Hi Quentin, On 2024/4/23 00:41, Quentin Schulz wrote: From: Quentin Schulz UART2 controller is the controller in the reference design for debug console. The default mux is M0 in that reference design. Until now, all boards seemed to be using UART2M0 but RK3588 Tiger for example will be using UART2M2 instead. This feature already been supported, please use CONFIG_DEBUG_UART_BASE and CONFIG_ROCKCHIP_UART_MUX_SEL_M to select your output channel. CONFIG_ROCKCHIP_UART_MUX_SEL_M is only available in Rockchip's downstream U-Boot. git log -p -S ROCKCHIP_UART_MUX_SEL_M returns nothing upstream, neither does git grep. I used the same mechanism as for PX30. This patch will be removed though as it's not needed until we have an open-source DRAM init. Until then we have to rely on the DDR bin to setup the UART. Cheers, Quentin
Re: [PATCH 1/2] rockchip: rk3588: add support for UART2 M1 and M2 in SPL
Hi Jonas, On 4/22/24 19:41, Jonas Karlman wrote: Hi Quentin, On 2024-04-22 18:41, Quentin Schulz wrote: From: Quentin Schulz UART2 controller is the controller in the reference design for debug console. The default mux is M0 in that reference design. Until now, all boards seemed to be using UART2M0 but RK3588 Tiger for example will be using UART2M2 instead. Therefore, let's add support for UART2M1 and M2 as possible muxes for the UART2 controller used as debug console. UART2M1 support was not tested. The default value is M0 to match the one used currently by all devices and the reference design. Is this really necessary? Use of board_debug_uart_init() should typically only be needed in TPL on Rockchip platform, and with ROCKCHIP_TPL being used it should be enough to use rkbin/ddrbin_tool to change uart config and just ensure correct pinctrl is used for uart node, and that the uart node is included in SPL for correct serial console use. ddrbin_tool is a blob that Rockchip refuses to provide sources of. Running a blob on the target is one thing, requiring our users to run a blob on their build machine is another thing (though I document it in the rST). However... I don't think we have another way around because I just remembered that if you have two muxes selected for the same UART controller, RX won't work. So while we would have UART output for U-Boot if Rockchip's TPL is one mux (e.g. m0, the default) and upstream U-Boot another one, we wouldn't be able to interact with it. It'll be necessary the day we have an open-source DRAM init though (I had to do this for PX30 for example). The issue is that since ddrbin_tool is a blob, it's not possible to use it in Yocto for automatically generating the appropriate ddr bin blob based on uart controller, mux and baudrate. So that will be my cross to bear. May I suggest you try adding following to defconfig and drop this patch? # CONFIG_DEBUG_UART_BOARD_INIT is not set I would expect that should result in same/working behavior without having to add any new code. It does work, thanks for the suggestion, will send a v2. Cheers, Quentin
[PATCH 2/2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module
From: Quentin Schulz
The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3588.
It provides the following feature set:
* up to 16GB LPDDR4x
* on-module eMMC
* SD card (on a baseboard) via edge connector
* Gigabit Ethernet with on-module GbE PHY
* HDMI/eDP
* MIPI-DSI
* 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
* HDMI input over FPC connector
* CAN
* USB
- 1x USB 3.0 dual-role (direct connection)
- 2x USB 3.0 host + 1x USB 2.0 host
* PCIe
- 1x PCIe 2.1 Gen3, 4 lanes
- 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
* on-module ATtiny816 companion controller, implementing:
- low-power RTC functionality (ISL1208 emulation)
- fan controller (AMC6821 emulation)
* on-module Secure Element with Global Platform 2.2.1 compliant
JavaCard environment
The support is added for Tiger on Haikou devkit, similarly to RK3399
Puma and PX30 Ringneck.
The DTS and DTSI are taken from upstream Linux kernel v6.9-rc4.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi | 54 ++
arch/arm/dts/rk3588-tiger-haikou.dts | 266
arch/arm/dts/rk3588-tiger.dtsi | 690 +
arch/arm/mach-rockchip/rk3588/Kconfig | 31 +
board/theobroma-systems/tiger_rk3588/Kconfig | 16 +
board/theobroma-systems/tiger_rk3588/MAINTAINERS | 13 +
board/theobroma-systems/tiger_rk3588/Makefile | 10 +
.../theobroma-systems/tiger_rk3588/tiger_rk3588.c | 53 ++
configs/tiger-rk3588_defconfig | 114
doc/board/rockchip/rockchip.rst| 1 +
doc/board/theobroma-systems/index.rst | 1 +
doc/board/theobroma-systems/tiger_rk3588.rst | 102 +++
include/configs/tiger_rk3588.h | 15 +
14 files changed, 1367 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c9c6222e5..ef901642a0a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -180,6 +180,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb \
+ rk3588-tiger-haikou.dtb \
rk3588-turing-rk1.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
new file mode 100644
index 000..4259399193a
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+_pwrseq {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+_reset {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+ {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+ {
+ /* U-Boot currently cannot handle anything below HS200 for eMMC on
RK3588 */
+ /delete-property/ mmc-ddr-1_8v;
+ /delete-property/ cap-mmc-highspeed;
+};
+
+/* Q7 USB P0 */
+ {
+ status = "okay";
+};
+
+_otg {
+ status = "okay";
+};
+
+_phy1 {
+ status = "okay";
+};
+
+_phy1_u3 {
+ status = "okay";
+};
+
+_host1_xhci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-tiger-haikou.dts
b/arch/arm/dts/rk3588-tiger-haikou.dts
new file mode 100644
index 000..d672198c6b6
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou.dts
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include
+#include "rk3588-tiger.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3588-Q7 SoM on Haikou devkit";
+ compatible = "tsd,rk3588-tiger-haikou", "tsd,rk3588-tiger",
"rockchip,rk3588";
+
+ aliases {
+ ethernet0 =
+ mmc1 =
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <_keys_pin>;
+
+ button-batlow-n {
+ label = "BATLOW#";
+ linux,code
[PATCH 1/2] rockchip: rk3588: add support for UART2 M1 and M2 in SPL
From: Quentin Schulz
UART2 controller is the controller in the reference design for debug
console. The default mux is M0 in that reference design. Until now, all
boards seemed to be using UART2M0 but RK3588 Tiger for example will be
using UART2M2 instead.
Therefore, let's add support for UART2M1 and M2 as possible muxes for
the UART2 controller used as debug console. UART2M1 support was not
tested.
The default value is M0 to match the one used currently by all devices
and the reference design.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/mach-rockchip/rk3588/Kconfig | 10 ++
arch/arm/mach-rockchip/rk3588/rk3588.c | 36 ++
2 files changed, 46 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index d7e4af31f24..cacdb0459c9 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -221,6 +221,16 @@ config ROCKCHIP_COMMON_STACK_ADDR
config TEXT_BASE
default 0x00a0
+config DEBUG_UART_CHANNEL
+ int "Mux channel to use for debug UART2"
+ depends on DEBUG_UART_BOARD_INIT
+ default 0
+ range 0 2
+ help
+ UART2 can use three different set of pins to route the output.
+ For using the UART for early debugging the route to use needs
+ to be declared (0, 1 or 2).
+
source board/edgeble/neural-compute-module-6/Kconfig
source board/friendlyelec/nanopc-t6-rk3588/Kconfig
source board/pine64/quartzpro64-rk3588/Kconfig
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index eb65dafe3a2..e330ad6a697 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -94,9 +94,32 @@ enum {
GPIO0B6_UART2_RX_M0 = 10,
};
+/* GPIO3B_IOMUX_SEL_L */
+enum {
+ GPIO3B1_SHIFT = 4,
+ GPIO3B1_MASK= GENMASK(7, 4),
+ GPIO3B1_UART2_TX_M2 = 10,
+
+ GPIO3B2_SHIFT = 8,
+ GPIO3B2_MASK= GENMASK(11, 8),
+ GPIO3B2_UART2_RX_M2 = 10,
+};
+
+/* GPIO4D_IOMUX_SEL_L */
+enum {
+ GPIO4D0_SHIFT = 0,
+ GPIO4D0_MASK= GENMASK(3, 0),
+ GPIO4D0_UART2_TX_M1 = 10,
+
+ GPIO4D1_SHIFT = 4,
+ GPIO4D1_MASK= GENMASK(7, 4),
+ GPIO4D1_UART2_RX_M1 = 10,
+};
+
void board_debug_uart_init(void)
{
__maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void
*)BUS_IOC_BASE;
+#if (CONFIG_DEBUG_UART_CHANNEL == 0)
static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
/* Refer to BUS_IOC */
@@ -110,6 +133,19 @@ void board_debug_uart_init(void)
GPIO0B6_MASK | GPIO0B5_MASK,
GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
+#elif (CONFIG_DEBUG_UART_CHANNEL == 1)
+ /* UART2_M1 Switch iomux */
+ rk_clrsetreg(_ioc->gpio4d_iomux_sel_l,
+GPIO4D0_MASK | GPIO4D1_MASK,
+GPIO4D0_UART2_TX_M1 << GPIO4D0_UART2_TX_M1 |
+GPIO4D1_UART2_RX_M1 << GPIO4D1_SHIFT);
+#else
+ /* UART2_M2 Switch iomux */
+ rk_clrsetreg(_ioc->gpio3b_iomux_sel_l,
+GPIO3B1_MASK | GPIO3B2_MASK,
+GPIO3B1_UART2_TX_M2 << GPIO3B1_SHIFT |
+GPIO3B2_UART2_RX_M2 << GPIO3B2_SHIFT);
+#endif /* CONFIG_DEBUG_UART_CHANNEL */
}
#ifdef CONFIG_SPL_BUILD
--
2.44.0
[PATCH 0/2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module
The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3588. It provides the following feature set: * up to 16GB LPDDR4x * on-module eMMC * SD card (on a baseboard) via edge connector * Gigabit Ethernet with on-module GbE PHY * HDMI/eDP * MIPI-DSI * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7) * HDMI input over FPC connector * CAN * USB - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 host * PCIe - 1x PCIe 2.1 Gen3, 4 lanes - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes * on-module ATtiny816 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) * on-module Secure Element with Global Platform 2.2.1 compliant JavaCard environment The support is added for Tiger on Haikou devkit, similarly to RK3399 Puma and PX30 Ringneck. The DTS and DTSI are taken from upstream Linux kernel v6.9-rc4. Because Tiger doesn't use the same mux for the debug console as all other RK3588 devices currently supported in U-Boot, an additional patch is required to be able to interact with the device properly. This has a light dependency on https://lore.kernel.org/u-boot/20240415-rk35xx-dram-atags-v3-0-5bc5475b3...@theobroma-systems.com/ (the Tiger defconfig can be updated to remove the dependency if required) Signed-off-by: Quentin Schulz --- Quentin Schulz (2): rockchip: rk3588: add support for UART2 M1 and M2 in SPL rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi | 54 ++ arch/arm/dts/rk3588-tiger-haikou.dts | 266 arch/arm/dts/rk3588-tiger.dtsi | 690 + arch/arm/mach-rockchip/rk3588/Kconfig | 41 ++ arch/arm/mach-rockchip/rk3588/rk3588.c | 36 ++ board/theobroma-systems/tiger_rk3588/Kconfig | 16 + board/theobroma-systems/tiger_rk3588/MAINTAINERS | 13 + board/theobroma-systems/tiger_rk3588/Makefile | 10 + .../theobroma-systems/tiger_rk3588/tiger_rk3588.c | 53 ++ configs/tiger-rk3588_defconfig | 114 doc/board/rockchip/rockchip.rst| 1 + doc/board/theobroma-systems/index.rst | 1 + doc/board/theobroma-systems/tiger_rk3588.rst | 102 +++ include/configs/tiger_rk3588.h | 15 + 15 files changed, 1413 insertions(+) --- base-commit: 5fb840ed8339cae3915ea1528a4bfa3e587540e6 change-id: 20240418-tiger-d1531308c9a0 Best regards, -- Quentin Schulz
Re: [PATCH 1/1] Makefile: don't add -Wno-maybe-uninitialized twice
Hi Heinrich,
On 4/16/24 09:35, Heinrich Schuchardt wrote:
Avoid adding the same flag to KBUILD_CFLAGS twice.
Fixes: 8602d97ca2cf ("Makefile: avoid false positive -Wmaybe-uninitialized")
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Quentin Schulz
Thanks,
Quentin
Re: [PATCH] ram: rockchip: px30: Replace misleading log message
BTW, On 4/17/24 13:16, lukasz.czechow...@thaumatec.com wrote: From: Lukasz Czechowski There is a typo in your mail address. I assume your git config user.email may be wrong, because your signed-off-by is correct. Cheers, Quentin
Re: [PATCH] ram: rockchip: px30: Replace misleading log message
Hi Lukasz,
On 4/17/24 13:16, lukasz.czechow...@thaumatec.com wrote:
From: Lukasz Czechowski
Remove the log message "out" from sdram_init function which
pollutes the console. It brings no meaningful information and
might be unwanted in case silencing the console is required.
Instead, add a debug log with a more meaningful message, printed
only if DEBUG is set. The same convention is used for other
boards, i.e. rk3399.
Signed-off-by: Lukasz Czechowski
---
drivers/ram/rockchip/sdram_px30.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_px30.c
b/drivers/ram/rockchip/sdram_px30.c
index 21498e8957..3b429973cd 100644
--- a/drivers/ram/rockchip/sdram_px30.c
+++ b/drivers/ram/rockchip/sdram_px30.c
@@ -712,7 +712,7 @@ int sdram_init(void)
sdram_print_ddr_info(_params->ch.cap_info, _params->base, 0);
- printascii("out\n");
+ debug("Finish SDRAM initialization...\n");
Mmmm I don't think this is appropriate. debug() is essentially replaced
with printf() whenever the selected log level permits. The issue is that
printf() != printascii() and I have a feeling we use printascii
explicitly because it is a much smaller way to print data than printf.
Additionally, we're extremely size constrained in TPL on PX30, so
increasing the string size to print may also not be wise. If we are not
enable to even build the TPL by defining DEBUG, this is basically dead
code and it's as good to us as removing it entirely.
So... questions:
1) does it actually build if you set #define DEBUG 1 or whatever is
needed for having the debug message printed? If yes, does it boot?
2) What's the size of the TPL with this change and with this
change+DEBUG set?
What I can suggest instead is to guard all printascii (or at least the
ones only useful for debugging) with the appropriate symbol, e.g. could
be CONFIG_RAM_ROCKCHIP_DEBUG.
I have not tested it (only build tested on Ringneck PX30 without
CONFIG_RAM_ROCKCHIP_DEBUG nor CONFIG_TPL_SERIAL), but here's a quick
attempt:
"""
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index b7a6f100d41..17656e99a2f 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -11,7 +11,7 @@ config ROCKCHIP_PX30
select TPL_NEEDS_SEPARATE_STACK if TPL
imply SPL_SEPARATE_BSS
select SPL_SERIAL
- select TPL_SERIAL
+ imply TPL_SERIAL
select DEBUG_UART_BOARD_INIT
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c
b/arch/arm/mach-rockchip/px30-board-tpl.c
index 637a5e1b18b..8f56147ca7a 100644
--- a/arch/arm/mach-rockchip/px30-board-tpl.c
+++ b/arch/arm/mach-rockchip/px30-board-tpl.c
@@ -36,7 +36,7 @@ void board_init_f(ulong dummy)
{
int ret;
-#ifdef CONFIG_DEBUG_UART
+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
debug_uart_init();
/*
* Debug UART can be used from here if required:
@@ -51,8 +51,10 @@ void board_init_f(ulong dummy)
secure_timer_init();
ret = sdram_init();
+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
if (ret)
printascii("sdram_init failed\n");
+#endif
/* return to maskrom */
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
index 67c63ecba04..cb59bcf0414 100644
--- a/drivers/ram/rockchip/Kconfig
+++ b/drivers/ram/rockchip/Kconfig
@@ -16,6 +16,8 @@ if RAM_ROCKCHIP
config RAM_ROCKCHIP_DEBUG
bool "Rockchip ram drivers debugging"
default y
+ depends on TPL_SERIAL if TPL_RAM
+ depends on SPL_SERIAL if SPL_RAM
help
This enables debugging ram driver API's for the platforms
based on Rockchip SoCs.
diff --git a/drivers/ram/rockchip/sdram_common.c
b/drivers/ram/rockchip/sdram_common.c
index 60fc90d0a5c..8076cfa9aad 100644
--- a/drivers/ram/rockchip/sdram_common.c
+++ b/drivers/ram/rockchip/sdram_common.c
@@ -231,7 +231,9 @@ int sdram_detect_col(struct sdram_cap_info *cap_info,
break;
}
if (col == 8) {
+#ifdef CONFIG_RAM_ROCKCHIP_DEBUG
printascii("col error\n");
+#endif
return -1;
}
@@ -348,7 +350,9 @@ int sdram_detect_row(struct sdram_cap_info *cap_info,
break;
}
if (row == 12) {
+#ifdef CONFIG_RAM_ROCKCHIP_DEBUG
printascii("row error");
+#endif
return -1;
}
diff --git a/drivers/ram/rockchip/sdram_px30.c
b/drivers/ram/rockchip/sdram_px30.c
index 21498e89570..607d97c268e 100644
--- a/drivers/ram/rockchip/sdram_px30.c
+++ b/drivers/ram/rockchip/sdram_px30.c
@@ -231,8 +231,10 @@ static unsigned int calculate_ddrconfig(struct
px30_sdram_params *sdram_params)
ddrconf = i;
break;
Re: [PATCH v3] rockchip: px30-board-tpl: Sync ifdef guards with full TPL
Hi Lukasz, On 4/17/24 13:21, lukasz.czechow...@thaumatec.com wrote: From: Lukasz Czechowski Display TPL init information message only when TPL_BANNER_PRINT configuration entry is set. This allows to disable information message in case logs on UART are unwanted. Update parent ifdef condition to check also CONFIG_TPL_SERIAL to match logic of the non-PX30 TPL implementation. Signed-off-by: Lukasz Czechowski When someone gives a tag (Acked-by, Reviewed-by, Tested-by, ...) on a version and you send a new one, it's best to include this in the commit log now (above your Signed-off-by if I remember correctly) if and only if the content only changed a bit (like no big logic change or rewrite). So here, my Reviewed-by would have been nice since I gave it in the v2 :) (please do not send a v4 for this :) ) b4 does this with `b4 trailers -u` automatically by the way :) Reviewed-by: Quentin Schulz Thanks, Quentin
Re: [PATCH v2] rockchip: px30-board-tpl: Use CONFIG_TPL_BANNER_PRINT flag
Hi Lukasz,
I would have renamed the commit title to be something like
rockchip: px30-board-tpl: sync ifdef guards with full TPL
because CONFIG_TPL_BANNER_PRINT isn't really a flag but a Kconfig symbol
and the effect of this patch is to not print the banner when the symbol
is not selected.
Another option could have been (only for the v1, since you do more now):
rockchip: px30-board-tpl: print banner only if CONFIG_TPL_BANNER_PRINT
On 4/17/24 11:35, lukasz.czechow...@thaumatec.com wrote:
From: Lukasz Czechowski
Display TPL init information message only when TPL_BANNER_PRINT
configuration entry is set. This allows to disable information
message in case logs on UART are unwanted.
Update parent ifdef condition to check also CONFIG_TPL_SERIAL
to match logic of the non-PX30 TPL implementation.
Signed-off-by: Lukasz Czechowski
Cc: Tom Rini
Cc: Simon Glass
Cc: Philipp Tomsich
Cc: Kever Yang
Small nitpick, the Cc would make it to the git history, which isn't
really necessary. I believe you could have those below the --- and
git-send-email still find them.
Additionally, git send-email allows you to provide --cc and --to manually.
---
Changes for v2:
- Updated parent ifdef condition
---
arch/arm/mach-rockchip/px30-board-tpl.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c
b/arch/arm/mach-rockchip/px30-board-tpl.c
index 637a5e1b18..db368a7b8c 100644
--- a/arch/arm/mach-rockchip/px30-board-tpl.c
+++ b/arch/arm/mach-rockchip/px30-board-tpl.c
@@ -36,7 +36,7 @@ void board_init_f(ulong dummy)
{
int ret;
-#ifdef CONFIG_DEBUG_UART
+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
Quite interestingly, CONFIG_TPL_SERIAL cannot be disabled on PX30, maybe
we should change arch/arm/mach-rockchip/Kconfig to use an `imply`
instead of `select`.
Anyway, no change required on my side. Only, if there's a v3 (for the Cc
and commit title, the Kconfig change would be a separate patch anyway).
Reviewed-by: Quentin Schulz
Thanks,
Quentin
Re: [PATCH] rockchip: px30-board-tpl: Use CONFIG_TPL_BANNER_PRINT flag
Hi Lukasz,
Please use scripts/get_maintainer.pl to set the Cc and To recipients of
your mail to make sure it reaches the appropriate people explicitly.
$ scripts/get_maintainer.pl arch/arm/mach-rockchip/px30-board-tpl.c
Tom Rini (maintainer:ARM)
Simon Glass (maintainer:ARM ROCKCHIP)
Philipp Tomsich (maintainer:ARM ROCKCHIP)
Kever Yang (maintainer:ARM ROCKCHIP)
u-boot@lists.denx.de (open list)
(one can use scripts/get_maintainer.pl on patches instead of files, and
it'll return whatever is needed).
Plugging `b4` here as well, because it's a pretty nice tool to use:
https://git.kernel.org/pub/scm/utils/b4/b4.git/ One can install it with
pip. I use it for Linux kernel and U-Boot contributions for a couple of
years now and I'm not going back to manual workflow :)
b4 prep --auto-to-cc would set everything up properly for you.
On 4/16/24 14:47, Lukasz Czechowski wrote:
Display TPL init information message only when TPL_BANNER_PRINT
configuration entry is set. This allows to disable information
message in case logs on UART are unwanted.
Signed-off-by: Lukasz Czechowski
This matches Rockchip's non-PX30 TPL, so:
Reviewed-by: Quentin Schulz
---
arch/arm/mach-rockchip/px30-board-tpl.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c
b/arch/arm/mach-rockchip/px30-board-tpl.c
index 637a5e1b18..a660816db0 100644
--- a/arch/arm/mach-rockchip/px30-board-tpl.c
+++ b/arch/arm/mach-rockchip/px30-board-tpl.c
@@ -46,7 +46,9 @@ void board_init_f(ulong dummy)
* printhex8(0x1234);
* printascii("string");
*/
+#if CONFIG_TPL_BANNER_PRINT
printascii("U-Boot TPL board init\n");
+#endif
I'm wondering if we shouldn't have the parent ifdef also match the logic
of the non-PX30 TPL?
#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
instead of
#if defined(CONFIG_DEBUG_UART)
?
Thanks,
Quentin
[PATCH v3 11/11] rockchip: rk356x: use DRAM banks from ATAGS
From: Quentin Schulz RK356x-based devices now support creating DRAM banks with proper holes by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism instead. The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for reading banks from ATAGS, so let's use the default value instead. Co-developed-by: Chris Morgan Signed-off-by: Chris Morgan Signed-off-by: Quentin Schulz --- configs/anbernic-rgxx3-rk3566_defconfig | 1 - configs/bpi-r2-pro-rk3568_defconfig | 1 - configs/evb-rk3568_defconfig | 1 - configs/generic-rk3568_defconfig | 1 - configs/lubancat-2-rk3568_defconfig | 1 - configs/nanopi-r5c-rk3568_defconfig | 1 - configs/nanopi-r5s-rk3568_defconfig | 1 - configs/odroid-m1-rk3568_defconfig| 1 - configs/pinetab2-rk3566_defconfig | 1 - configs/quartz64-a-rk3566_defconfig | 1 - configs/quartz64-b-rk3566_defconfig | 1 - configs/radxa-cm3-io-rk3566_defconfig | 1 - configs/radxa-e25-rk3568_defconfig| 1 - configs/rock-3a-rk3568_defconfig | 1 - configs/soquartz-blade-rk3566_defconfig | 1 - configs/soquartz-cm4-rk3566_defconfig | 1 - configs/soquartz-model-a-rk3566_defconfig | 1 - 17 files changed, 17 deletions(-) diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig index c8c9238f96f..aa3809e00c1 100644 --- a/configs/anbernic-rgxx3-rk3566_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig index 5cc95241ba4..0f85dc63c55 100644 --- a/configs/bpi-r2-pro-rk3568_defconfig +++ b/configs/bpi-r2-pro-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index 6e8061f5f48..f2f429d33c4 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index e7d5e55bbfd..8f4a6259a27 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig index 1c50a0ccbe6..ea67b6a7286 100644 --- a/configs/lubancat-2-rk3568_defconfig +++ b/configs/lubancat-2-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig index 0f1a9461a0c..00743b7f926 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 4ebf0cc9ee8..91e3a19dea6 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig index b5ed9e4bc98..e749f9af9d2 100644 --- a/configs/odroid-m1-rk3568_defconfig +++ b/configs/odroid-m1-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=2400 CONFIG_SF_DEFAULT_MODE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1" diff --git a/configs/
[PATCH v3 10/11] rockchip: rk3588: use DRAM banks from ATAGS
From: Quentin Schulz RK3588-based devices now support creating DRAM banks with proper holes by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism instead. The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for reading banks from ATAGS, so let's use the default value instead. Co-developed-by: Chris Morgan Signed-off-by: Chris Morgan Signed-off-by: Quentin Schulz --- configs/jaguar-rk3588_defconfig | 1 - configs/neu6a-io-rk3588_defconfig | 1 - configs/neu6b-io-rk3588_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 3233b75cee9..f29505ea150 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=2400 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_ENV_SIZE=0x1f000 diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index 307a540f424..2b939e6795f 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig index 9ef2bb21fff..d0fa0dca7ac 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y -- 2.44.0
[PATCH v3 09/11] rockchip: turing-rk1-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the turing-rk1-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/turing/turing-rk1-rk3588/Makefile| 6
board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c | 39 --
configs/turing-rk1-rk3588_defconfig| 2 --
3 files changed, 47 deletions(-)
diff --git a/board/turing/turing-rk1-rk3588/Makefile
b/board/turing/turing-rk1-rk3588/Makefile
deleted file mode 100644
index a979d8023aa..000
--- a/board/turing/turing-rk1-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += turing-rk1-rk3588.o
diff --git a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
b/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
deleted file mode 100644
index e2338a2a35a..000
--- a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int turing_rk1_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return turing_rk1_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/turing-rk1-rk3588_defconfig
b/configs/turing-rk1-rk3588_defconfig
index 07f7b848529..2195b03d57a 100644
--- a/configs/turing-rk1-rk3588_defconfig
+++ b/configs/turing-rk1-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1"
@@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 08/11] rockchip: toybrick_rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the toybrick_rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/rockchip/toybrick_rk3588/Makefile | 6
board/rockchip/toybrick_rk3588/toybrick-rk3588.c | 39
configs/toybrick-rk3588_defconfig| 2 --
3 files changed, 47 deletions(-)
diff --git a/board/rockchip/toybrick_rk3588/Makefile
b/board/rockchip/toybrick_rk3588/Makefile
deleted file mode 100644
index 75d4d9438f7..000
--- a/board/rockchip/toybrick_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += toybrick-rk3588.o
diff --git a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
deleted file mode 100644
index e3217f70b50..000
--- a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/toybrick-rk3588_defconfig
b/configs/toybrick-rk3588_defconfig
index 6ee92e94313..675e7d89e12 100644
--- a/configs/toybrick-rk3588_defconfig
+++ b/configs/toybrick-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 06/11] rockchip: rock5b-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the rock5b-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/radxa/rock5b-rk3588/Makefile| 6 -
board/radxa/rock5b-rk3588/rock5b-rk3588.c | 39 ---
configs/rock5b-rk3588_defconfig | 2 --
3 files changed, 47 deletions(-)
diff --git a/board/radxa/rock5b-rk3588/Makefile
b/board/radxa/rock5b-rk3588/Makefile
deleted file mode 100644
index 95d813596da..000
--- a/board/radxa/rock5b-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2022 Collabora Ltd.
-#
-
-obj-y += rock5b-rk3588.o
diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
deleted file mode 100644
index 5c3b52b9489..000
--- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5b_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rock5b_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 58c7c44fb4f..3603e175a0b 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
@@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 07/11] rockchip: evb_rk3588 et al.: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the evb_rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
All defconfigs using the CONFIG_TARGET_EVB_RK3588 are updated at once
since they are impacted by this change.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/rockchip/evb_rk3588/Makefile | 6 -
board/rockchip/evb_rk3588/evb-rk3588.c | 39
configs/coolpi-4b-rk3588s_defconfig | 2 --
configs/coolpi-cm5-evb-rk3588_defconfig | 2 --
configs/evb-rk3588_defconfig | 2 --
configs/generic-rk3588_defconfig | 2 --
configs/orangepi-5-plus-rk3588_defconfig | 2 --
configs/orangepi-5-rk3588s_defconfig | 2 --
8 files changed, 57 deletions(-)
diff --git a/board/rockchip/evb_rk3588/Makefile
b/board/rockchip/evb_rk3588/Makefile
deleted file mode 100644
index 240d2ec597e..000
--- a/board/rockchip/evb_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += evb-rk3588.o
diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c
b/board/rockchip/evb_rk3588/evb-rk3588.c
deleted file mode 100644
index caf94d8d29c..000
--- a/board/rockchip/evb_rk3588/evb-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/coolpi-4b-rk3588s_defconfig
b/configs/coolpi-4b-rk3588s_defconfig
index a0fe3708344..2608bb67679 100644
--- a/configs/coolpi-4b-rk3588s_defconfig
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig
b/configs/coolpi-cm5-evb-rk3588_defconfig
index fc17660da2a..c5bb7a42957 100644
--- a/configs/coolpi-cm5-evb-rk3588_defconfig
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index c8db04c076e..187cf26a5c9 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FI
[PATCH v3 05/11] rockchip: rock5a-rk3588s: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the rock5a-rk3588s.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/radxa/rock5a-rk3588s/Makefile | 6 -
board/radxa/rock5a-rk3588s/rock5a-rk3588s.c | 39 -
configs/rock5a-rk3588s_defconfig| 2 --
3 files changed, 47 deletions(-)
diff --git a/board/radxa/rock5a-rk3588s/Makefile
b/board/radxa/rock5a-rk3588s/Makefile
deleted file mode 100644
index 48dd5124550..000
--- a/board/radxa/rock5a-rk3588s/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Collabora Ltd.
-#
-
-obj-y += rock5a-rk3588s.o
diff --git a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
b/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
deleted file mode 100644
index 2d7a8c07dc5..000
--- a/board/radxa/rock5a-rk3588s/rock5a-rk3588s.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5a_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rock5a_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index ebe2d4a2d81..01df911d9dc 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 04/11] rockchip: quartzpro64-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the quartzpro64-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/pine64/quartzpro64-rk3588/Makefile | 3 --
.../pine64/quartzpro64-rk3588/quartzpro64-rk3588.c | 39 --
configs/quartzpro64-rk3588_defconfig | 2 --
3 files changed, 44 deletions(-)
diff --git a/board/pine64/quartzpro64-rk3588/Makefile
b/board/pine64/quartzpro64-rk3588/Makefile
deleted file mode 100644
index 47819d9be93..000
--- a/board/pine64/quartzpro64-rk3588/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += quartzpro64-rk3588.o
diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
deleted file mode 100644
index bda804a89e2..000
--- a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2023 Google, Inc
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return quartzpro64_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/quartzpro64-rk3588_defconfig
b/configs/quartzpro64-rk3588_defconfig
index b2a66d3f2db..e398c7c2c0e 100644
--- a/configs/quartzpro64-rk3588_defconfig
+++ b/configs/quartzpro64-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -19,7 +18,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 03/11] rockchip: nanopc-t6-rk3588: use DRAM banks from ATAGS
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the nanopc-t6-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
board/friendlyelec/nanopc-t6-rk3588/Makefile | 6
.../nanopc-t6-rk3588/nanopc-t6-rk3588.c| 39 --
configs/nanopc-t6-rk3588_defconfig | 2 --
3 files changed, 47 deletions(-)
diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile
b/board/friendlyelec/nanopc-t6-rk3588/Makefile
deleted file mode 100644
index c1c49b19708..000
--- a/board/friendlyelec/nanopc-t6-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += nanopc-t6-rk3588.o
diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
deleted file mode 100644
index 99bbef964e0..000
--- a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int nanopc_t6_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return nanopc_t6_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/nanopc-t6-rk3588_defconfig
b/configs/nanopc-t6-rk3588_defconfig
index 5c7bc0b7196..738dda026b0 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
--
2.44.0
[PATCH v3 02/11] rockchip: NR_DRAM_BANKS now defaults to 10 when Rockchip TPL blob is used
From: Quentin Schulz When Rockchip TPL blob is used, the memory areas that can be used for DRAM is gotten from ATAGS passed through the DRAM at a specific address. The DDR_MEM tag contains at most 10 areas, so we should default to 10 if Rockchip TPL blob is used. Note that it is technically possible we need more if one of those 10 areas overlaps with reserved memory area, forcing us to split it in two. But a default doesn't need to handle all cases, only most. Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f68a0a48949..b7a6f100d41 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -573,6 +573,9 @@ config ROCKCHIP_COMMON_STACK_ADDR imply TPL_SYS_MALLOC_F if TPL imply TPL_SYS_MALLOC_SIMPLE if TPL +config NR_DRAM_BANKS + default 10 if ROCKCHIP_EXTERNAL_TPL + source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3066/Kconfig" -- 2.44.0
[PATCH v3 01/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
From: Quentin Schulz
Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with
more than 16GB of RAM. In the event that neither SoC is used or the
ROCKCHIP_TPL stage is not used, fall back to existing logic.
The logic handles creating memory holes from reserved memory areas
defined in mem_map data struct in SoC C files, but only if the DRAM area
overlaps with one reserved memory area.
Since mem_map data struct is used, it should be rather straightforward
to add support for other SoCs if needed.
The logic is taken from Rockchip's U-Boot tag linux-5.10-gen-rkr4.1
(e08e32143dd).
Note that Rockchip's U-Boot/TF-A/OP-TEE modify the ATAGS at runtime as
well, but the DDR_MEM tag seems to be pretty much stable (though BL31
seems to be reserving only 1MB for itself at the moment).
u32 for ATAGS is used because it simplifies the pointer arithmetic and
it's expected that ATAGS are always below the 4GB limit allowed by u32.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
---
arch/arm/mach-rockchip/sdram.c | 240 +
1 file changed, 240 insertions(+)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0aef6f5..5b1ff1e5495 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -35,12 +36,251 @@ struct tos_parameter_t {
s64 reserve[8];
};
+/* Tag size and offset */
+#define ATAGS_SIZE SZ_8K
+#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE)
+#define ATAGS_PHYS_BASE(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+#define ATAGS_PHYS_END (ATAGS_PHYS_BASE + ATAGS_SIZE)
+
+/* ATAGS memory structures */
+
+enum tag_magic {
+ ATAG_NONE,
+ ATAG_CORE = 0x54410001,
+ ATAG_SERIAL = 0x54410050,
+ ATAG_DDR_MEM = 0x54410052,
+ ATAG_MAX = 0x544100ff,
+};
+
+/*
+ * An ATAG contains the following data:
+ * - header
+ *u32 size // sizeof(header + tag data) / sizeof(u32)
+ *u32 magic
+ * - tag data
+ */
+
+struct tag_header {
+ u32 size;
+ u32 magic;
+} __packed;
+
+/*
+ * DDR_MEM tag bank is storing data this way:
+ * - address0
+ * - address1
+ * - [...]
+ * - addressX
+ * - size0
+ * - size1
+ * - [...]
+ * - sizeX
+ *
+ * with X being tag_ddr_mem.count - 1.
+ */
+struct tag_ddr_mem {
+ u32 count;
+ u32 version;
+ u64 bank[20];
+ u32 flags;
+ u32 data[2];
+ u32 hash;
+} __packed;
+
+static u32 js_hash(const void *buf, u32 len)
+{
+ u32 i, hash = 0x47C6A7E6;
+
+ if (!buf || !len)
+ return hash;
+
+ for (i = 0; i < len; i++)
+ hash ^= ((hash << 5) + ((const char *)buf)[i] + (hash >> 2));
+
+ return hash;
+}
+
+static int rockchip_dram_init_banksize(void)
+{
+ const struct tag_header *tag_h = NULL;
+ u32 *addr = (void *)ATAGS_PHYS_BASE;
+ struct tag_ddr_mem *ddr_info;
+ u32 calc_hash;
+ u8 i, j;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ return -ENOTSUPP;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
+ return -ENOTSUPP;
+
+ /* Find DDR_MEM tag */
+ while (addr < (u32 *)ATAGS_PHYS_END) {
+ tag_h = (const struct tag_header *)addr;
+
+ if (!tag_h->size) {
+ debug("End of ATAGS (0-size tag), no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ if (tag_h->magic == ATAG_DDR_MEM)
+ break;
+
+ switch (tag_h->magic) {
+ case ATAG_NONE:
+ case ATAG_CORE:
+ case ATAG_SERIAL ... ATAG_MAX:
+ addr += tag_h->size;
+ continue;
+ default:
+ debug("Invalid magic (0x%08x) for ATAG at 0x%p\n",
+ tag_h->magic, addr);
+ return -EINVAL;
+ }
+ }
+
+ if (addr >= (u32 *)ATAGS_PHYS_END ||
+ (tag_h && (addr + tag_h->size > (u32 *)ATAGS_PHYS_END))) {
+ debug("End of ATAGS, no DDR_MEM found\n");
+ return -ENODATA;
+ }
+
+ /* Data is right after the magic member of the tag_header struct */
+ ddr_info = (struct tag_ddr_mem *)(_h->magic + 1);
+ if (!ddr_info->count || ddr_info->count > CONFIG_NR_DRAM_BANKS) {
+ debug("Too many ATAG banks, got (%d) but max allowed (%d)\n",
+
[PATCH v3 00/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
x0004fdf882ff - 0x0004fdf88300 pattern [0.00] 0x0004fdf8832f - 0x0004fdf88330 pattern [0.00] 0x0004fdf8835f - 0x0004fdf88360 pattern [0.00] 0x0004fdf8838f - 0x0004fdf88390 pattern [0.00] 0x0004fdf883bf - 0x0004fdf883c0 pattern [0.00] 0x0004fdf883ef - 0x0004fdf883f0 pattern [0.00] 0x0004fdf8841c - 0x0004fdf88420 pattern [0.00] 0x0004fdf8844c - 0x0004fdf88450 pattern [0.00] 0x0004fdf8847c - 0x0004fdf88480 pattern [0.00] 0x0004fdf884ac - 0x0004fdf884b0 pattern [0.00] 0x0004fdf884dc - 0x0004fdf884e0 pattern [0.00] 0x0004fdf8850c - 0x0004fdf88510 pattern [0.00] 0x0004fdf8853c - 0x0004fdf88540 pattern [0.00] 0x0004fdf8856c - 0x0004fdf88570 pattern [0.00] 0x0004fdf8859c - 0x0004fdf885a0 pattern [0.00] 0x0004fdf885cd - 0x0004fdf885d0 pattern [0.00] 0x0004fdf885fd - 0x0004fdf88600 pattern [0.00] 0x0004fdf8862d - 0x0004fdf88630 pattern [0.00] 0x0004fdf8865d - 0x0004fdf88660 pattern [0.00] 0x0004fdf8868d - 0x0004fdf88690 pattern $ lsmem --output SIZE --bytes --json | jq '[.memory[].size] | add / 1024 / 1024 / 1024' 16 """ I tested on Rock5B 16GB that without the memory holes and without using this new logic, the kernel fails this memtest, so this test seems valid. This has NOT been tested on RK356x as I don't own any. Changes in v3: - Split board migration to new DRAM ATAGS mechanism into separate commits, - Use mem_map instead of hardcoded values for reserved memory area for MMIO, - Add tag hash check to match Rockchip's downstream implementation, - Bail from while loop as soon as a tag with no size is encountered to match Rockchip's downstream implementation, - Use enum instead of constants for ATAG magic, - Add debug messages and comments, - Fix atags traversal by using tag size instead of checking every 16B, - Migrate Jaguar to new mechanism, - Default NR_DRAM_BANKS to 10 when ROCKCHIP_EXTERNAL_TPL is used so the default allows to use this new logic, - Define tag_header data struct to parse the first two bytes of a tag more easily, - Do not stop at CORE magic, directly look for DDR_MEM, - Bail from while loop as soon as an unknown tag is used to match Rockchip's downstream implementation, - Use phys_size_t and phys_addr_t wherever possible, Link to v2: https://lore.kernel.org/u-boot/20240401181435.553351-1-macroalph...@gmail.com/ Link to v1: https://lore.kernel.org/u-boot/20240330050515.470025-1-macroalph...@gmail.com/ Co-Developed-by: Chris Morgan Signed-off-by: Quentin Schulz --- Quentin Schulz (11): rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588 rockchip: NR_DRAM_BANKS now defaults to 10 when Rockchip TPL blob is used rockchip: nanopc-t6-rk3588: use DRAM banks from ATAGS rockchip: quartzpro64-rk3588: use DRAM banks from ATAGS rockchip: rock5a-rk3588s: use DRAM banks from ATAGS rockchip: rock5b-rk3588: use DRAM banks from ATAGS rockchip: evb_rk3588 et al.: use DRAM banks from ATAGS rockchip: toybrick_rk3588: use DRAM banks from ATAGS rockchip: turing-rk1-rk3588: use DRAM banks from ATAGS rockchip: rk3588: use DRAM banks from ATAGS rockchip: rk356x: use DRAM banks from ATAGS arch/arm/mach-rockchip/Kconfig | 3 + arch/arm/mach-rockchip/sdram.c | 240 + board/friendlyelec/nanopc-t6-rk3588/Makefile | 6 - .../nanopc-t6-rk3588/nanopc-t6-rk3588.c| 39 board/pine64/quartzpro64-rk3588/Makefile | 3 - .../pine64/quartzpro64-rk3588/quartzpro64-rk3588.c | 39 board/radxa/rock5a-rk3588s/Makefile| 6 - board/radxa/rock5a-rk3588s/rock5a-rk3588s.c| 39 board/radxa/rock5b-rk3588/Makefile | 6 - board/radxa/rock5b-rk3588/rock5b-rk3588.c | 39 board/rockchip/evb_rk3588/Makefile | 6 - board/rockchip/evb_rk3588/evb-rk3588.c | 39 board/rockchip/toybrick_rk3588/Makefile| 6 - board/rockchip/toybrick_rk3588/toybrick-rk3588.c | 39 board/turing/turing-rk1-rk3588/Makefile| 6 - board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c | 39 configs/anbernic-rgxx3-rk3566_defconfig| 1 - configs/bpi-r2-pro-rk3568_defconfig| 1 - config
[PATCH] env: mmc: print MMC device being read
From: Quentin Schulz
This prints the MMC device being read similar to how we print the MMC
device we write to when e.g. calling saveenv.
One of the side effects is that the boot log now shows from which MMC
device the env was loaded:
Loading Environment from MMC... Reading from MMC(1)... OK
This is useful to identify which MMC device the environment was loaded
from for boards where there are more than one (e.g. eMMC and SD card)
without adding some debug messages manually.
Sadly, there's no way to know which of the default or redundant
environment is being read from env_mmc_load before env_import_redund is
called so it is printing a bit later (and possibly after error/warning
messages).
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
env/mmc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/env/mmc.c b/env/mmc.c
index da84cddd74f..7afb733e890 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -436,6 +436,7 @@ static int env_mmc_load(void)
ret = env_import_redund((char *)tmp_env1, read1_fail, (char *)tmp_env2,
read2_fail, H_EXTERNAL);
+ printf("Reading from %sMMC(%d)... ", gd->env_valid == ENV_REDUND ?
"redundant " : "", dev);
fini:
fini_mmc_for_env(mmc);
@@ -475,6 +476,8 @@ static int env_mmc_load(void)
goto fini;
}
+ printf("Reading from MMC(%d)... ", dev);
+
ret = env_import(buf, 1, H_EXTERNAL);
if (!ret) {
ep = (env_t *)buf;
---
base-commit: b03b49046af5dfca599d2ce8f0aafed89b97aa91
change-id: 20240415-mmc-loadenv-dev-ced678171e98
Best regards,
--
Quentin Schulz
Re: [PATCH v2 15/23] rockchip: rk3588-toybrick: Add missing Kconfig options
Hi Dragan, On 4/15/24 11:04, Dragan Simic wrote: On 2024-04-15 10:58, Quentin Schulz wrote: On 4/13/24 20:13, Jonas Karlman wrote: Add .dtb-file entry to Makefile and enable Kconfig options required to configure pinctrl in SPL. Also add missing PHY_ROCKCHIP_NANENG_COMBOPHY. Separate commits please. Perhaps the Makefile changes from a couple of different patches could be put together into another, separate patch. Those are all related changes, and it would result in one less patch in the v3 of this series. That would be fine with me. But always better have too many patches than too few, it's easier to later squash than separate them :) Cheers, Quentin
Re: [PATCH v2 23/23] rockchip: rk3588: Enable use of eMMC HS200 mode on a few missed boards
Hi Jonas, On 4/13/24 20:13, Jonas Karlman wrote: A few RK3588 boards are missing a mmc-hs200 prop to signal that HS200 mode is supported in addition to HS400, this lead to bad performance reading FIT in SPL and broken MMC write. Add cap-mmc-highspeed and mmc-hs200-1_8v to affected boards to enable use of eMMC HS200 mode. Signed-off-by: Jonas Karlman --- v2: New patch All these mmc-hs200 prop overrides may not be needed if the patch "mmc: Imply HS200 cap with mmc-hs400 prop to match linux" [1] gets applied, until such time this matches what has been done for all other RK35xx boards. [1] https://patchwork.ozlabs.org/patch/1921039/ I think this is an acceptable change until we agree on what to do with that other patch :) I'll abstain from giving my Rb here though as I do not own any of those boards and therefore cannot check this is actually valid. Cheers, Quentin
Re: [PATCH v2 15/23] rockchip: rk3588-toybrick: Add missing Kconfig options
Hi Jonas, On 4/13/24 20:13, Jonas Karlman wrote: Add .dtb-file entry to Makefile and enable Kconfig options required to configure pinctrl in SPL. Also add missing PHY_ROCKCHIP_NANENG_COMBOPHY. Separate commits please. Sum of changes is fine though (but a bit more verbose commit log would be welcome, why SPL_DM_SEQ_ALIAS for example). Cheers, Quentin
Re: [PATCH v2 14/23] rockchip: rk3588-coolpi: Add boards to documentation
Hi Jonas, On 4/13/24 20:13, Jonas Karlman wrote: Add the CoolPi 4 Model B and CoolPi CM5 EVB board to the documentation. Also fix .dtb-file entries in Makefile. When one needs to use a list or say "also", "moreover", etc... it usually is a tell the commit should be split. Here the changes are not related, so please have two separate patches. The sum of changes is fine though, thanks. Cheers, Quentin
Re: [PATCH v2 12/23] rockchip: rk3588: Update bootph props
Hi Jonas,
On 4/13/24 20:13, Jonas Karlman wrote:
After the commit aca95282c1b7 ("Makefile: Use the fdtgrep -u flag")
bootph props is propagating to parent nodes.
Update bootph props to ensure eMMC, SD-card and SPI flash is available
in SPL and U-Boot proper pre-reloc phase also remove unneeded bootph
props that automatically is propagated to parent nodes.
Also adjust pinctrl nodes to only be included in boot phases where they
are needed and add any missing pinctrl node needed in SPL.
Signed-off-by: Jonas Karlman
---
v2: Add bootph-some-ram props and follow kernel sort order
Following bootph props have been applied:
CRU, GRF and UART nodes:
- bootph-all - needed at all or most stages
SD-card regulator related nodes:
- bootph-pre-ram (SPL) - regulator pinctrl may be needed to read FIT
from SD-card on some boards
eMMC/SD-card/SPI flash related nodes:
- bootph-pre-ram (SPL)
- bootph-some-ram (U-Boot proper pre-reloc)
---
.../arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi | 8 +--
arch/arm/dts/rk3588-generic.dts | 1 +
arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi | 12 ++---
.../dts/rk3588-orangepi-5-plus-u-boot.dtsi| 7 ++-
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 8 +--
arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi| 6 ++-
arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi| 8 +--
arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi | 9 ++--
arch/arm/dts/rk3588s-u-boot.dtsi | 50 ++-
configs/evb-rk3588_defconfig | 4 +-
10 files changed, 71 insertions(+), 42 deletions(-)
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
index ed15b14ea0ee..f0ef0164664e 100644
--- a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
@@ -3,7 +3,8 @@
#include "rk3588-u-boot.dtsi"
_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
{
@@ -12,16 +13,15 @@
};
{
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "okay";
flash@0 {
- bootph-pre-ram;
compatible = "jedec,spi-nor";
reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
spi-max-frequency = <2400>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts
index e4721d97a87d..baafe7463f1b 100644
--- a/arch/arm/dts/rk3588-generic.dts
+++ b/arch/arm/dts/rk3588-generic.dts
@@ -40,5 +40,6 @@
};
{
+ pinctrl-0 = <_xfer>;
I think this should be its own patch.
[...]
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 68ecbc54b807..610a8d740fbb 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -33,7 +33,8 @@ CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent
assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -52,6 +53,7 @@ CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
I have a feeling the changes to the defconfig aren't entirely related to
this patch? Specifically, I think at least CONFIG_SPL_DM_SEQ_ALIAS isn't
related?
Otherwise,
Reviewed-by: Quentin Schulz
Thanks,
Quentin
Re: [PATCH v2 10/23] rockchip: rk35xx: Sort soc u-boot.dtsi alphabetically
Hi Jonas,
On 4/13/24 20:13, Jonas Karlman wrote:
Sort nodes and props in RK356x/RK3588 u-boot.dtsi alphabetically, nodes
is sorted by reg addr then by alphabetical order.
This has no intended change beside sorting existing nodes and removing
a duplicated usbdpphy0_grf node.
Signed-off-by: Jonas Karlman
---
v2: Follow kernel sort order (Quentin)
[1]
https://www.kernel.org/doc/html/latest/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
---
arch/arm/dts/rk356x-u-boot.dtsi | 98
arch/arm/dts/rk3588s-u-boot.dtsi | 69 +++---
2 files changed, 81 insertions(+), 86 deletions(-)
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 05367216e118..1ecf719202e9 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -38,46 +38,10 @@
[...]
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
{
simple-bin-spi {
We could also alphabetically sort the binman node if we wanted.
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 233eb79d9ba2..543327954b1a 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -41,6 +41,17 @@
status = "disabled";
};
+ vo0_grf: syscon@fd5a6000 {
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
+ clocks = < PCLK_VO0GRF>;
+ };
+
+ usb_grf: syscon@fd5ac000 {
+ compatible = "rockchip,rk3588-usb-grf", "syscon";
+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
+ };
+
usbdpphy0_grf: syscon@fd5c8000 {
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
reg = <0x0 0xfd5c8000 0x0 0x4000>;
@@ -72,22 +83,6 @@
};
};
- vo0_grf: syscon@fd5a6000 {
- compatible = "rockchip,rk3588-vo-grf", "syscon";
- reg = <0x0 0xfd5a6000 0x0 0x2000>;
- clocks = < PCLK_VO0GRF>;
- };
-
- usb_grf: syscon@fd5ac000 {
- compatible = "rockchip,rk3588-usb-grf", "syscon";
- reg = <0x0 0xfd5ac000 0x0 0x4000>;
- };
-
- usbdpphy0_grf: syscon@fd5c8000 {
- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
- reg = <0x0 0xfd5c8000 0x0 0x4000>;
- };
-
Would have been nice to at least mention this node is removed because it
is duplicated (or have it removed in a different commit to make it more
explicit).
[...]
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
What's below this git context is , which we could also
alphabetically sort if we wanted.
Did the change manually and it matches, so:
Reviewed-by: Quentin Schulz
Thanks!
Quentin
Re: [PATCH v3] cmd: bootm: add ELF file support
Hi Maxim,
On 4/11/24 10:32, Maxim Moskalets wrote:
From: Maxim Moskalets
Some operating systems (e.g. seL4) and embedded applications are ELF
images. It is convenient to use FIT-images to implement trusted boot.
Added "elf" image type for booting using bootm command.
Signed-off-by: Maxim Moskalets
---
boot/bootm_os.c | 24
boot/image-fit.c | 3 ++-
boot/image.c | 3 +++
include/image.h | 1 +
4 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/boot/bootm_os.c b/boot/bootm_os.c
index ccde72d22c..1c92b8149c 100644
--- a/boot/bootm_os.c
+++ b/boot/bootm_os.c
@@ -395,6 +395,27 @@ static int do_bootm_qnxelf(int flag, struct bootm_info
*bmi)
}
#endif
+#if defined(CONFIG_CMD_ELF)
+static int do_bootm_elf(int flag, struct bootm_info *bmi)
+{
+ struct bootm_headers *images = bmi->images;
+ char *local_args[2] = {NULL};
+ char str[19] = ""; /* "0x" + 16 digits + "\0" */
+
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+ snprintf(str, sizeof str, "0x%lx", images->ep); /* write entry-point
into string */
While sizeof str does return the same as the number of elements in the
array, it's only because it's a char array and thus its elements are all
1B, any other type would have returned something incorrect.
I recommend using ARRAY_SIZE(str) instead, which is the way to know the
number of elements in the array (dividing the size of the array by the
size of an element in the array).
Cheers,
Quentin
Re: [PATCH] cmd: bootm: add ELF file support
Hi Maxim,
On 4/10/24 23:21, Maxim Moskalets wrote:
From: Maxim Moskalets
Some operating systems (e.g. seL4) and embedded applications are ELF
images. It is convenient to use FIT-images to implement trusted boot.
Added "elf" image type for booting using bootm command.
Signed-off-by: Maxim Moskalets
---
boot/bootm_os.c | 24
boot/image-fit.c | 3 ++-
boot/image.c | 3 +++
include/image.h | 1 +
4 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/boot/bootm_os.c b/boot/bootm_os.c
index ccde72d22c..1c92b8149c 100644
--- a/boot/bootm_os.c
+++ b/boot/bootm_os.c
@@ -395,6 +395,27 @@ static int do_bootm_qnxelf(int flag, struct bootm_info
*bmi)
}
#endif
+#if defined(CONFIG_CMD_ELF)
+static int do_bootm_elf(int flag, struct bootm_info *bmi)
+{
+ struct bootm_headers *images = bmi->images;
+ char *local_args[2] = {NULL};
+ char str[19] = ""; /* "0x" + 16 digits + "\0" */
+
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+ sprintf(str, "0x%lx", images->ep); /* write entry-point into string */
+ str[18] = '\0';
This does seem like snprintf would be useful here?
"""
snprintf(str, 19, "0x%lx", images-ep);
"""
safest and also merges the two instructions in one.
Also, have another question, do we want to 0-left-pad the value so that
it's always a 16 hex-digit number?
e.g. 0x%016lx
Cheers,
Quentin
Re: [PATCH] gpio: pca953x_gpio: support optional reset-gpios property
Hi Rasmus,
On 4/10/24 14:59, Rasmus Villemoes wrote:
On 10/04/2024 14.24, Quentin Schulz wrote:
Hi Rasmus,
@@ -321,6 +322,13 @@ static int pca953x_probe(struct udevice *dev)
  driver_data = dev_get_driver_data(dev);
 +   /* If a reset-gpios property is present, take the device out of
reset. */
+Â Â Â ret = gpio_request_by_name(dev, "reset-gpios", 0, ,
GPIOD_IS_OUT);
+Â Â Â if (ret && ret != -ENOENT) {
This seems to differ from the implementation we have for optionally
getting gpios by index, c.f.
https://elixir.bootlin.com/u-boot/latest/source/drivers/gpio/gpio-uclass.c#L1498
"""
struct gpio_desc *devm_gpiod_get_index(struct udevice *dev, const char *id,
  unsigned int index, int flags)
{
[...]
rc = gpio_request_by_name(dev, propname, index, desc, flags);
end:
[...]
if (rc)
   return ERR_PTR(rc);
[...]
return desc;
}
struct gpio_desc *devm_gpiod_get_index_optional(struct udevice *dev,
   const char *id,
   unsigned int index,
   int flags)
Well, that doesn't seem to have a lot of users outside tests? We really
have way too many APIs for doing the same thing.
It is actually used outside of tests as well:
#define devm_gpiod_get_optional(dev, id, flags) \
devm_gpiod_get_index_optional(dev, id, 0, flags)
Then:
"""
$ git grep devm_gpiod_get_optional
drivers/phy/ti/phy-j721e-wiz.c:wiz->gpio_typec_dir =
devm_gpiod_get_optional(dev, "typec-dir",
drivers/power/pmic/pca9450.c:priv->sd_vsel_gpio =
devm_gpiod_get_optional(dev, "sd-vsel",
drivers/usb/dwc3/dwc3-generic.c:priv->ulpi_reset =
devm_gpiod_get_optional(dev->parent, "reset",
"""
It's not THAT many but at least there are a few *real* users :)
Also, I think you actually want to use devm_gpiod_get_optional since
it's basically just wrapping
"""
gpio_request_by_name(dev, "reset-gpios", 0, , GPIOD_IS_OUT);
"""
with devres?
-ENOENT seems to happen (at least) if the property reset-gpios isn't
found, which very much would be the case if it's optional. Now it seems
-EINVAL could also be returned in some cases...
https://elixir.bootlin.com/u-boot/latest/source/drivers/core/of_access.c#L669
Now... reading what the kernel does:
https://elixir.bootlin.com/linux/latest/source/drivers/gpio/gpiolib-devres.c#L186
checks the return value with
https://elixir.bootlin.com/linux/latest/source/drivers/gpio/gpiolib.h#L189
S... it seems they are doing what you're doing.
So, what I suggest is the following:
1) fix devm_gpiod_get_index_optional
to return desc (which may be a pointer or an ERR_PTR, so users should do
an IS_ERR(desc) check after call) ONLY when NOT IS_ERR(desc) &&
PTR_ERR(desc) == -ENOENT.
So:
"""
struct gpio_desc *devm_gpiod_get_index_optional(struct udevice *dev,
const char *id,
unsigned int index,
int flags)
{
struct gpio_desc *desc = devm_gpiod_get_index(dev, id, index, flags);
if (IS_ERR(desc) && PTR_ERR(desc) == -ENOENT)
return NULL;
return desc;
}
"""
Maybe some adding some new test also for this new part of the if check?
2) use devm_gpiod_get_optional in your driver
What do you think?
Cheers,
Quentin
Re: [PATCH] gpio: pca953x_gpio: support optional reset-gpios property
Hi Rasmus,
On 4/10/24 13:11, Rasmus Villemoes wrote:
The DT bindings for the pca953x family has an optional reset-gpios
property. If present, ensure that the device is taken out of reset
before attempting to read from it.
Signed-off-by: Rasmus Villemoes
---
drivers/gpio/pca953x_gpio.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index b0c66d18317..24b0732f89a 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -306,6 +306,7 @@ static int pca953x_probe(struct udevice *dev)
struct pca953x_info *info = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
char name[32], label[8], *str;
+ struct gpio_desc reset;
int addr;
ulong driver_data;
int ret;
@@ -321,6 +322,13 @@ static int pca953x_probe(struct udevice *dev)
driver_data = dev_get_driver_data(dev);
+ /* If a reset-gpios property is present, take the device out of reset. */
+ ret = gpio_request_by_name(dev, "reset-gpios", 0, , GPIOD_IS_OUT);
+ if (ret && ret != -ENOENT) {
This seems to differ from the implementation we have for optionally
getting gpios by index, c.f.
https://elixir.bootlin.com/u-boot/latest/source/drivers/gpio/gpio-uclass.c#L1498
"""
struct gpio_desc *devm_gpiod_get_index(struct udevice *dev, const char *id,
unsigned int index, int flags)
{
[...]
rc = gpio_request_by_name(dev, propname, index, desc, flags);
end:
[...]
if (rc)
return ERR_PTR(rc);
[...]
return desc;
}
struct gpio_desc *devm_gpiod_get_index_optional(struct udevice *dev,
const char *id,
unsigned int index,
int flags)
{
struct gpio_desc *desc = devm_gpiod_get_index(dev, id, index, flags);
if (IS_ERR(desc))
return NULL;
return desc;
}
"""
It seems we only need to check whether rc is non-zero, but it doesn't
check that it's not ENOENT. I think we would benefit from having the
same logic here.
Also, maybe we need a devm_gpio_get_by_name_optional implementation in
the subsystem so we don't have to reimplement it in drivers that want to
use this?
Cheers,
Quentin
Re: [PATCH v4 1/1] fastboot: introduce 'oem board' subcommand
Hi Alexey, On 4/10/24 12:58, Alexey Romanov wrote: Currently, fastboot protocol in U-Boot has no opportunity to execute vendor custom code with verifed boot. This patch introduce new fastboot subcommand fastboot oem board:, which allow to run custom oem_board function. Default implementation is __weak. Vendor must redefine it in board/ folder with his own logic. For example, some vendors have their custom nand/emmc partition flashing or erasing. Here some typical command for such use cases: - flashing: $ fastboot stage bootloader.img $ fastboot oem board:write_bootloader - erasing: $ fastboot oem board:erase_env Signed-off-by: Alexey Romanov Reviewed-by: Mattijs Korpershoek --- doc/android/fastboot.rst | 18 ++ drivers/fastboot/Kconfig | 7 +++ drivers/fastboot/fb_command.c | 30 ++ include/fastboot.h| 1 + 4 files changed, 56 insertions(+) diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst index 1ad8a897c8..2a627f9890 100644 --- a/doc/android/fastboot.rst +++ b/doc/android/fastboot.rst @@ -29,6 +29,7 @@ The following OEM commands are supported (if enabled): with = boot_ack boot_partition - ``oem bootbus`` - this executes ``mmc bootbus %x %s`` to configure eMMC - ``oem run`` - this executes an arbitrary U-Boot command +- ``oem board`` - this executes a custom board function which is defined by the vendor Support for both eMMC and NAND devices is included. @@ -245,6 +246,23 @@ including multiple commands (using e.g. ``;`` or ``&&``) and control structures (``if``, ``while``, etc.). The exit code of ``fastboot`` will reflect the exit code of the command you ran. +Running Custom Vendor Code +^^ + +U-Boot allows you to execute custom fastboot logic, which can be defined +in board/ files. It can still be used for production devices with verified +boot, because the vendor define logic at compile time by implementing I think it should be "defines" here? Reviewed-by: Quentin Schulz Thanks, Quentin
Re: [PATCH 1/2] mmc: Imply HS200 cap with mmc-hs400 prop to match linux
Hi Dragan, On 4/9/24 21:28, Dragan Simic wrote: [...] Let's keep in mind that the troublesome DT properties describe the capabilities of the MMC controller and the board, not the capabilities of the MMC storage device. As we know, eMMC devices provide automatic detection capabilities, to allow the host to determine its supported modes, and match them with the ones the host is configured to support. It's all described in the JEDEC standards. So why do we have those properties specified in board DTSes instead of in the SoC DTSI? Logic would want us to have this defined in one place only. I assume the issue is that even if the eMMC chip itself says it supports HS400 but the HW routing or some other issue make it impossible to use, we need a way to disable it from the DT for that board? Having that in mind, I find the approach in the Linux kernel rather reasonable, because I highly doubt that some MMC controllers support, for example, HS400 without supporting DDR52, or HS400 without supporting DDR52. A reasonable approach for an MMC IP block is to make it capable of supporting all the speeds below its highest supported speed, to make itself capable of supporting more, if not all, MMC storage devices. That's true for the IP block which is self-contained in the SoC, but it's forgetting about the other part, the eMMC chip/card. It depends on the HW routing, where mistakes/limitations can happen. And I don't think we have a mechanism today to disable the modes set in the MMC controller for a given MMC card from DT (aside from /delete-property/ in board files). In fact, I'll probably go ahead and submit a Linux kernel patch that updates the descriptions in the binding, to hopefully eliminate any ambiguities like these. I hope you agree. I for sure do not have enough knowledge in MMC to argue more than I just did, so having people with more experience/knowledge have a look at this would make sense, let's see what they have to say :) Cheers, Quentin
Re: [PATCH 1/2] mmc: Imply HS200 cap with mmc-hs400 prop to match linux
Hi Dragan, On 4/9/24 21:30, Dragan Simic wrote: Hello Jonas, On 2024-04-09 18:30, Jonas Karlman wrote: On 2024-04-09 18:02, Quentin Schulz wrote: On 4/9/24 17:58, Jonas Karlman wrote: On 2024-04-09 17:27, Quentin Schulz wrote: On 4/8/24 23:06, Jonas Karlman wrote: eMMC nodes in linux device tree files typically only contain a mmc-hs400 prop to signal support for both HS400 and HS200. However, U-Boot require an explicit mmc-hs200 prop to signal support for the HS200 mode.  > Fix this by follow linux and imply HS200 cap when HS400 cap is signaled using a mmc-hs400 prop. Technically speaking, the DT binding should be the one and only source of truth and should be implementation-agnostic. There it says: """    mmc-hs400-1_2v:  $ref: /schemas/types.yaml#/definitions/flag  description:    eMMC HS400 mode (1.2V I/O) is supported.    mmc-hs400-1_8v:  $ref: /schemas/types.yaml#/definitions/flag  description:    eMMC HS400 mode (1.8V I/O) is supported. """ So I'd say, the DTs should be fixed to add mmc-hs200 as well wherever it makes sense. The point of the DT/DT binding is to be system-agnostic and representative of the **HW** implementation. At least that's what the DT people want it to be. If the eMMC standard doesn't allow to have HS400 without HS200, then I think this change is acceptable as is, because it is the reality of the HW standard. Couldn't find this implied in the standard though (but I just skimmed through). It's also quite surprising, as it's not because the eMMC works with HS400 that it necessarily does with HS200 or that it's desired (EMI, signal integrity/stability, etc...)? Now, it wouldn't be the first time U-Boot follows whatever is done in Linux, so... up to you/the maintainers :) Agree that implying HS200 does not fully make sense, however it was part of the original Linux binding when HS400 was added in v3.16-rc1 [1] so I think that this is the expected behavior and changing it may be an ABI breakage. I'm not advocating undoing the kernel "hack", but rather make it so that we add hs200 to DTs where it's actually supported instead of doing the same hack the kernel does. In that case, we wouldn't need the hack anymore. I will add a patch that adds the missing mmc-hs200 props to affected rk3588 boards, nanopc-t4 and quartzpro64 in v2 of the "rockchip: rk35xx: Miscellaneous fixes and updates" series. Also turns out the issue with those boards was because of my other "mmc: rockchip_sdhci: Revert 4 blocks PIO mode read limit for RK35xx" patch, so will need to rework that revert some more before posting a v2 of that patch. For this patch it is fully up to the maintainers if U-Boot wants to mimic Linux kernel or not. I think that the logic used in the Linux kernel should be followed, because one of the goals should be to add as few "touches" to the upstream DT files in U-Boot as possible. I was suggesting to fix the upstream DT files as well. Cheers, Quentin
Re: [PATCH v2 05/14] rockchip: rk3308: Enable random generator
Hi Jonas,
On 4/9/24 18:21, Jonas Karlman wrote:
Hi Quentin,
On 2024-04-09 17:45, Quentin Schulz wrote:
Hi Jonas,
On 4/8/24 20:14, Jonas Karlman wrote:
The RK3308 SoC contain a crypto engine block that can generate random
numbers.
Add rng node to soc u-boot.dtsi and enable Kconfig options to take
advantage of the random generator.
Signed-off-by: Jonas Karlman
---
v2: No change
---
arch/arm/dts/rk3308-u-boot.dtsi | 5 +
arch/arm/mach-rockchip/Kconfig | 2 ++
2 files changed, 7 insertions(+)
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index 436f66d1b87d..fa31c838d34d 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -26,6 +26,11 @@
reg = <0x07 0x10>;
};
};
+
+ rng: rng@ff2f {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xff2f 0x0 0x4000>;
Downstream says something different:
https://github.com/rockchip-linux/kernel/blob/develop-5.10/arch/arm64/boot/dts/rockchip/rk3308.dtsi#L1007-L1020
I couldn't quickly find the TRM for the RK3308 so cannot check myself :/
RK3308TRM Part1 mention following under address mapping:
ff2f CRYPTO 64K
And RK3308TRM Part2 mention following under crypto regs:
CRYPTO_CLK_CTL 0x W 0x0001 Clock Control Register
[...]
CRYPTO_RNG_CTL 0x0400 W 0x000c RNG Control Register
[...]
CRYPTO_SRAM_ADDR 0x1000 W 0x SRAM Base Address
And the U-Boot driver:
/* start of CRYPTO V2 register define */
#define CRYPTO_V2_RNG_CTL 0x0400
So 0xff2f should be correct for the crypto block on RK3308. And the
rng cmd also gives me proper random numbers on my Rock Pi S board.
Could verify with the TRM Dragan shared, thanks.
Also seems to be missing clocks and resets?
Yeah, this is just a minimal node to get the rng driver in U-Boot
working and like most other clocks they are enabled and running at an
acceptable rate by default.
Considering that the clocks and resets all seem to be crypto block
specific and that the kernel doesn't seem to be doing runtime PM on
Rockchip clocks, I guess this is good enough for now?
Reviewed-by: Quentin Schulz
Thanks,
Quentin
Re: [PATCH 1/2] mmc: Imply HS200 cap with mmc-hs400 prop to match linux
Hi Jonas, On 4/9/24 17:58, Jonas Karlman wrote: Hi Quentin, On 2024-04-09 17:27, Quentin Schulz wrote: Hi Jonas, On 4/8/24 23:06, Jonas Karlman wrote: eMMC nodes in linux device tree files typically only contain a mmc-hs400 prop to signal support for both HS400 and HS200. However, U-Boot require an explicit mmc-hs200 prop to signal support for the HS200 mode. > Fix this by follow linux and imply HS200 cap when HS400 cap is signaled using a mmc-hs400 prop. Technically speaking, the DT binding should be the one and only source of truth and should be implementation-agnostic. There it says: """ mmc-hs400-1_2v: $ref: /schemas/types.yaml#/definitions/flag description: eMMC HS400 mode (1.2V I/O) is supported. mmc-hs400-1_8v: $ref: /schemas/types.yaml#/definitions/flag description: eMMC HS400 mode (1.8V I/O) is supported. """ So I'd say, the DTs should be fixed to add mmc-hs200 as well wherever it makes sense. The point of the DT/DT binding is to be system-agnostic and representative of the **HW** implementation. At least that's what the DT people want it to be. If the eMMC standard doesn't allow to have HS400 without HS200, then I think this change is acceptable as is, because it is the reality of the HW standard. Couldn't find this implied in the standard though (but I just skimmed through). It's also quite surprising, as it's not because the eMMC works with HS400 that it necessarily does with HS200 or that it's desired (EMI, signal integrity/stability, etc...)? Now, it wouldn't be the first time U-Boot follows whatever is done in Linux, so... up to you/the maintainers :) Agree that implying HS200 does not fully make sense, however it was part of the original Linux binding when HS400 was added in v3.16-rc1 [1] so I think that this is the expected behavior and changing it may be an ABI breakage. I'm not advocating undoing the kernel "hack", but rather make it so that we add hs200 to DTs where it's actually supported instead of doing the same hack the kernel does. In that case, we wouldn't need the hack anymore. (well maybe it isn't a hack per-se, but for lack of more info on that, I call the kernel implementation this :) ) Cheers, Quentin
Re: [PATCH v2 05/14] rockchip: rk3308: Enable random generator
Hi Jonas,
On 4/8/24 20:14, Jonas Karlman wrote:
The RK3308 SoC contain a crypto engine block that can generate random
numbers.
Add rng node to soc u-boot.dtsi and enable Kconfig options to take
advantage of the random generator.
Signed-off-by: Jonas Karlman
---
v2: No change
---
arch/arm/dts/rk3308-u-boot.dtsi | 5 +
arch/arm/mach-rockchip/Kconfig | 2 ++
2 files changed, 7 insertions(+)
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index 436f66d1b87d..fa31c838d34d 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -26,6 +26,11 @@
reg = <0x07 0x10>;
};
};
+
+ rng: rng@ff2f {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xff2f 0x0 0x4000>;
Downstream says something different:
https://github.com/rockchip-linux/kernel/blob/develop-5.10/arch/arm64/boot/dts/rockchip/rk3308.dtsi#L1007-L1020
I couldn't quickly find the TRM for the RK3308 so cannot check myself :/
Also seems to be missing clocks and resets?
Cheers,
Quentin
Re: [PATCH v2 04/14] rockchip: rk3308: Generate ethaddr based on cpu id
Hi Jonas,
On 4/8/24 20:14, Jonas Karlman wrote:
Like other Rockchip SoCs the RK3308 has cpu id programmed into OTP
memory. The rockchip_otp driver already support the RK3308 variant.
However, the device tree is missing a node to enable use of OTP.
Add the missing otp node to soc u-boot.dtsi, enable the rockchip_otp
driver and enable use of misc_init_r() to set ethaddr based on cpu id.
Signed-off-by: Jonas Karlman
---
v2: Add clocks and resets props
---
arch/arm/dts/rk3308-u-boot.dtsi | 16
arch/arm/mach-rockchip/Kconfig | 3 +++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index db2c20a7055e..436f66d1b87d 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -10,6 +10,22 @@
mmc0 =
mmc1 =
};
+
+ otp: nvmem@ff21 {
+ compatible = "rockchip,rk3308-otp";
+ reg = <0x0 0xff21 0x0 0x4000>;
+ clocks = < SCLK_OTP_USR>, < PCLK_OTP_NS>,
+< PCLK_OTP_PHY>;
+ clock-names = "otp", "apb_pclk", "phy";
+ resets = < SRST_OTP_PHY>;
+ reset-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+ };
Any plan upstreaming this to the Linux kernel so we can avoid
maintaining it in U-Boot?
It seems supported (the compatible is matched by a driver and there's a
DT binding already).
Reviewed-by: Quentin Schulz
Cheers,
Quentin
Re: [PATCH 1/2] mmc: Imply HS200 cap with mmc-hs400 prop to match linux
Hi Jonas, On 4/8/24 23:06, Jonas Karlman wrote: eMMC nodes in linux device tree files typically only contain a mmc-hs400 prop to signal support for both HS400 and HS200. However, U-Boot require an explicit mmc-hs200 prop to signal support for the HS200 mode. > Fix this by follow linux and imply HS200 cap when HS400 cap is signaled using a mmc-hs400 prop. Technically speaking, the DT binding should be the one and only source of truth and should be implementation-agnostic. There it says: """ mmc-hs400-1_2v: $ref: /schemas/types.yaml#/definitions/flag description: eMMC HS400 mode (1.2V I/O) is supported. mmc-hs400-1_8v: $ref: /schemas/types.yaml#/definitions/flag description: eMMC HS400 mode (1.8V I/O) is supported. """ So I'd say, the DTs should be fixed to add mmc-hs200 as well wherever it makes sense. The point of the DT/DT binding is to be system-agnostic and representative of the **HW** implementation. At least that's what the DT people want it to be. If the eMMC standard doesn't allow to have HS400 without HS200, then I think this change is acceptable as is, because it is the reality of the HW standard. Couldn't find this implied in the standard though (but I just skimmed through). It's also quite surprising, as it's not because the eMMC works with HS400 that it necessarily does with HS200 or that it's desired (EMI, signal integrity/stability, etc...)? Now, it wouldn't be the first time U-Boot follows whatever is done in Linux, so... up to you/the maintainers :) Reviewed-by: Quentin Schulz Cheers, Quentin
Re: [PATCH v3 1/1] fastboot: introduce 'oem board' subcommand
Hi Alexey, On 4/8/24 12:15, Alexey Romanov wrote: Currently, fastboot protocol in U-Boot has no opportunity to execute vendor custom code with verifed boot. This patch introduce new fastboot subcommand fastboot oem board:, which allow to run custom oem_board function. Default implementation is __weak. Vendor must redefine it in board/ folder with his own logic. For example, some vendors have their custom nand/emmc partition flashing or erasing. Here some typical command for such use cases: - flashing: $ fastboot stage bootloader.img $ fastboot oem board:write_bootloader - erasing: $ fastboot oem board:erase_env Signed-off-by: Alexey Romanov --- doc/android/fastboot.rst | 18 ++ drivers/fastboot/Kconfig | 7 +++ drivers/fastboot/fb_command.c | 30 ++ include/fastboot.h| 1 + 4 files changed, 56 insertions(+) diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst index 05d8f77759..2020590657 100644 --- a/doc/android/fastboot.rst +++ b/doc/android/fastboot.rst @@ -30,6 +30,7 @@ The following OEM commands are supported (if enabled): - ``oem bootbus`` - this executes ``mmc bootbus %x %s`` to configure eMMC - ``oem run`` - this executes an arbitrary U-Boot command - ``oem console`` - this dumps U-Boot console record buffer +- ``oem board`` - this executes an custom board function which is defined by vendor s/an/a/ +the vendor? (missing "the") Support for both eMMC and NAND devices is included. @@ -246,6 +247,23 @@ including multiple commands (using e.g. ``;`` or ``&&``) and control structures (``if``, ``while``, etc.). The exit code of ``fastboot`` will reflect the exit code of the command you ran. +Running Custom Vendor Code +^^ + +U-Boot allows you to execute custom fastboot logic, which can be defined +in board/ files. It can still be used for production devices with verified +boot, because vendor define logic at compile time by overriding weak s/vendor define/the vendor defines/ Suggestion: Replace "by overriding weak implementation of fastboot_oem_board()" with "by implementing fastboot_oem_board()", the weak symbol is an implementation detail I don't think we need to keep in the documentation? +implementation of fastboot_oem_board() function. The attacker will +not able to execute his commands / code. For example, this can be useful +be able (missing be) s/his/custom/ or s/his/their/ +for custom flashing or erasing protocols:: + +$ fastboot stage bootloader.img +$ fastboot oem board:write_bootloader + +In this case, ``cmd_parameter`` argument of the function ``fastboot_oem_board()`` +will contain string "write_bootloader" and ``data`` argument is a pointer to +fastboot input buffer, which containing the contents of bootloader.img file. + Either -which (remove "which") s/which containing/which contains/ Cheers, Quentin
Re: [V1 PATCH 1/2] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
Hi Chris,
On 4/4/24 23:33, Chris Morgan wrote:
On Tue, Apr 02, 2024 at 06:38:59PM +0200, Quentin Schulz wrote:
Hi Chris,
On 4/1/24 20:14, Chris Morgan wrote:
From: Chris Morgan
Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with
= 16GB of RAM. In the event that neither SOC is used and the
ROCKCHIP_TPL stage is not used, fall back to existing logic.
Signed-off-by: Chris Morgan
---
arch/arm/mach-rockchip/sdram.c | 100 +
1 file changed, 100 insertions(+)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0aef6f..e02fb03c5f 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -35,11 +36,110 @@ struct tos_parameter_t {
s64 reserve[8];
};
+/* Tag magic */
+#define ATAGS_CORE_MAGIC 0x54410001
+#define ATAGS_DDR_MEM_MAGIC0x54410052
+
+/* Tag size and offset */
+#define ATAGS_SIZE SZ_8K
+#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE)
+#define ATAGS_PHYS_BASE(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+
+/* ATAGS memory structure. */
+struct tag_ddr_mem {
+ u32 count;
+ u32 version;
+ u64 bank[20];
+ u32 flags;
+ u32 data[2];
+ u32 hash;
+} __packed;
+
+/**
+ * rockchip_dram_init_banksize() - Get RAM banks from Rockchip TPL
+ *
+ * Iterate through the defined ATAGS memory location to first find a
+ * valid core header, then find a valid ddr_info header. Sanity check
+ * the number of banks found. Then, iterate through the data to add
+ * each individual memory bank. Perform fixups on memory banks that
+ * overlap with a reserved space. If an error condition is received,
+ * it is expected that memory bank setup will fall back on existing
+ * logic. If ROCKCHIP_EXTERNAL_TPL is false then immediately return,
+ * and if neither ROCKCHIP_RK3588 or ROCKCHIP_RK3568 is enabled
+ * immediately return.
+ *
+ * Return number of banks found on success or negative on error.
+ */
+__weak int rockchip_dram_init_banksize(void)
+{
+ struct tag_ddr_mem *ddr_info;
+ size_t val;
+ size_t addr = ATAGS_PHYS_BASE;
I think this should be phys_addr_t instead of size_t?
size_t is an unsigned long on aarch64 and phys_addr_t is an unsigned long
long so 4B vs 8B.
This however would likely prevent us from reusing this code on aarch32
machines, but maybe it's a problem for the people who'll look into
supporting this :) (also, aarch32 and >= 3.75GiB may be a bit optimistic :)
).
Could I just specify a size and not worry about it? A u32 should be more
than enough to hold the maximum RAM address of an RK3588 board (32GB).
That would allow this to work on both 32 and 64 right? Otherwise I could
further restrict this code to the AARCH64 ifdef.
There's even a bigger issue here as phys_t is an 8B structure (on
Aarch64) while the atags are actually 4B aligned, so that would
unnecessarily increase the complexity for arithmetic on those addresses.
So u32 would probably be fine then.
+ int i;
+
u8 is plenty enough here :)
I use it as a return value where there are negative numbers (though
obviously this should never be negative since it's an increment
counter). Does that matter?
You could return i still and let the compiler do the conversion.
No, it's not a blocker, but that may unnecessarily increase the size of
the TPL.
[...]
+ break;
+ addr += 4;
This is an incorrect step size, addr is 4B, so this will result in 16B
increments, which may be too much. Additionally, we shouldn't read every 4B
as the tag is only ever guaranteed to be 4B aligned, not that we would have
a tag every 4B. This also means that it's possible somehow the content of a
tag at a 4B-aligned offset has the CORE_MAGIC for some reason, but we
shouldn't match on it.
I'm not quite sure I follow. Are you saying I need to increment every
4 * the value of size in the tag_header? The value I show is 0x5 in
my header meaning increment every 0x14?
What we have in memory is (each 4B) (correct me if I misread Rockchip's
code)
tag1.size = 6
tag1.magic
data1[0]
data1[1]
data1[2]
data1[3]
tag2.size = 4
tag2.magic
data2[0]
data2[1]
...
You start with addr =
when you do addr +4, you now have addr= [2]
By casting data1[2] into a tag struct, you would have
tagX.size = data1[2]
tagX.magic = data1[3]
If somehow data1[3] matches the magic, you'll detect tag data as a tag
header, and that's no good. Also, you may be missing a tag by checking
every 16B, which isn't guaranteed by Rockchip's ATAGS (only guaranteed
to be 4B aligned)
tag1.size is the size of the tag1 in multiples of 4
Re: [PATCH] board: rockchip: Add Indiedroid Nova
Hi Chris,
On 4/1/24 20:17, Chris Morgan wrote:
From: Chris Morgan
The Indiedroid Nova is a Rockchip RK3588S based SBC from Indiedroid.
Specifications:
Rockchip RK3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
Optional eMMC
2x USB 2.0, 2x USB 3.0, 1x USB 3.0 C port with DP Alt
1x MIPI-CSI Port (4-lane or 2x 2-lane)
1x MIPI-DSI 4-lane connector
1x Micro HDMI 2.1 output, 1x DP 1.4 output
Gigabit Ethernet
Realtek RTL8821CS WiFi
4 pin debug UART connector
40 pin GPIO header
Size: 85mm x 56mm (Raspberry Pi Form Factor)
Kernel commit:
3900160e164b ("arm64: dts: rockchip: Add Indiedroid Nova board")
Signed-off-by: Chris Morgan
---
arch/arm/dts/Makefile | 1 +
.../dts/rk3588s-indiedroid-nova-u-boot.dtsi | 11 +
arch/arm/dts/rk3588s-indiedroid-nova.dts | 853 ++
arch/arm/mach-rockchip/rk3588/Kconfig | 7 +
board/indiedroid/nova/Kconfig | 15 +
board/indiedroid/nova/MAINTAINERS | 8 +
configs/indiedroid-nova-rk3588s_defconfig | 106 +++
include/configs/indiedroid-nova.h | 15 +
8 files changed, 1016 insertions(+)
create mode 100644 arch/arm/dts/rk3588s-indiedroid-nova-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3588s-indiedroid-nova.dts
create mode 100644 board/indiedroid/nova/Kconfig
create mode 100644 board/indiedroid/nova/MAINTAINERS
create mode 100644 configs/indiedroid-nova-rk3588s_defconfig
create mode 100644 include/configs/indiedroid-nova.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b102ffb5f6..0af2986610 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -194,6 +194,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
+ rk3588s-indiedroid-nova.dtb \
rk3588-nanopc-t6.dtb \
rk3588s-orangepi-5.dtb \
rk3588-orangepi-5-plus.dtb \
diff --git a/arch/arm/dts/rk3588s-indiedroid-nova-u-boot.dtsi
b/arch/arm/dts/rk3588s-indiedroid-nova-u-boot.dtsi
new file mode 100644
index 00..16ded31fa5
--- /dev/null
+++ b/arch/arm/dts/rk3588s-indiedroid-nova-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
+#include
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588s-indiedroid-nova.dts
b/arch/arm/dts/rk3588s-indiedroid-nova.dts
new file mode 100644
index 00..253f163960
--- /dev/null
+++ b/arch/arm/dts/rk3588s-indiedroid-nova.dts
@@ -0,0 +1,853 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include
+#include
+#include
+#include
+#include "rk3588s.dtsi"
+
+/ {
+ model = "Indiedroid Nova";
+ compatible = "indiedroid,nova", "rockchip,rk3588s";
+
+ adc-keys-0 {
+ compatible = "adc-keys";
+ io-channel-names = "buttons";
+ io-channels = < 0>;
+ keyup-threshold-microvolt = <180>;
+ poll-interval = <100>;
+
+ button-boot {
+ label = "boot";
+ linux,code = ;
+ press-threshold-microvolt = <18000>;
+ };
+ };
+
+ adc-keys-1 {
+ compatible = "adc-keys";
+ io-channel-names = "buttons";
+ io-channels = < 1>;
+ keyup-threshold-microvolt = <180>;
+ poll-interval = <100>;
+
+ button-recovery {
+ label = "recovery";
+ linux,code = ;
+ press-threshold-microvolt = <18000>;
+ };
+ };
+
+ aliases {
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ };
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clock-names = "ext_clock";
+ clocks = <_hym8563>;
+ pinctrl-0 = <_enable_h>;
+ pinctrl-names = "default";
+ post-power-on-delay-ms = <200>;
+ reset-gpios = < RK_PC7 GPIO_ACTIVE_LOW>;
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "rockchip,es8388-codec";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ routing = "LINPUT2", "Mic Jack",
+ "Headphones", "LOUT1",
+ "Headphones", "ROUT1";
+ dais = <_8ch_p0>;
+ };
+
+ vbus5v0_typec: vbus5v0-typec-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PA5 GPIO_ACTIVE_HIGH>;
+
Re: [V2 PATCH 2/2] rockchip: Switch RK3568 and RK3588 to new RAM bank logic
Hi Chris, On 4/1/24 20:14, Chris Morgan wrote: From: Chris Morgan Switch all RK3568 and RK3588 boards to use the ATAGS based RAM bank logic. This allows us to access all RAM when >= 4GB of RAM is available while also automatically creating the memory holes when >= 16GB of RAM is available. Remove the board specific logic that previously created the memory holes, and update the CONFIG_NR_DRAM_BANKS to 10 which is the maximum supported number of banks using the ATAGS method. Only the number of banks found by the RAM init code will get added. Signed-off-by: Chris Morgan Could you please rebase on top of next to have all new boards as well? I don't see my Jaguar in there and it feels sad being left on the side :( You may want to have your Indiedroid Nova patch based on that series as well? Half wondering if we shouldn't have CONFIG_NR_DRAM_BANKS=10 forcibly set when ROCKCHIP_EXTERNAL_TPL is used? --- board/friendlyelec/nanopc-t6-rk3588/Makefile | 6 --- .../nanopc-t6-rk3588/nanopc-t6-rk3588.c | 39 --- board/pine64/quartzpro64-rk3588/Makefile | 3 -- .../quartzpro64-rk3588/quartzpro64-rk3588.c | 39 --- board/radxa/rock5a-rk3588s/Makefile | 6 --- board/radxa/rock5a-rk3588s/rock5a-rk3588s.c | 39 --- board/radxa/rock5b-rk3588/Makefile| 6 --- board/radxa/rock5b-rk3588/rock5b-rk3588.c | 39 --- board/rockchip/evb_rk3588/Makefile| 6 --- board/rockchip/evb_rk3588/evb-rk3588.c| 39 --- board/turing/turing-rk1-rk3588/Makefile | 6 --- .../turing-rk1-rk3588/turing-rk1-rk3588.c | 39 --- configs/anbernic-rgxx3-rk3566_defconfig | 2 +- configs/bpi-r2-pro-rk3568_defconfig | 2 +- configs/evb-rk3568_defconfig | 2 +- configs/evb-rk3588_defconfig | 3 +- configs/generic-rk3568_defconfig | 2 +- configs/lubancat-2-rk3568_defconfig | 2 +- configs/nanopc-t6-rk3588_defconfig| 3 +- configs/nanopi-r5c-rk3568_defconfig | 2 +- configs/nanopi-r5s-rk3568_defconfig | 2 +- configs/neu6a-io-rk3588_defconfig | 2 +- configs/neu6b-io-rk3588_defconfig | 2 +- configs/odroid-m1-rk3568_defconfig| 2 +- configs/orangepi-5-plus-rk3588_defconfig | 3 +- configs/orangepi-5-rk3588s_defconfig | 3 +- configs/quartz64-a-rk3566_defconfig | 2 +- configs/quartz64-b-rk3566_defconfig | 2 +- configs/quartzpro64-rk3588_defconfig | 3 +- configs/radxa-cm3-io-rk3566_defconfig | 2 +- configs/radxa-e25-rk3568_defconfig| 2 +- configs/rock-3a-rk3568_defconfig | 2 +- configs/rock5a-rk3588s_defconfig | 3 +- configs/rock5b-rk3588_defconfig | 3 +- configs/soquartz-blade-rk3566_defconfig | 2 +- configs/soquartz-cm4-rk3566_defconfig | 2 +- configs/soquartz-model-a-rk3566_defconfig | 2 +- configs/turing-rk1-rk3588_defconfig | 3 +- 38 files changed, 26 insertions(+), 301 deletions(-) delete mode 100644 board/friendlyelec/nanopc-t6-rk3588/Makefile delete mode 100644 board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c delete mode 100644 board/pine64/quartzpro64-rk3588/Makefile delete mode 100644 board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c delete mode 100644 board/radxa/rock5a-rk3588s/Makefile delete mode 100644 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c delete mode 100644 board/radxa/rock5b-rk3588/Makefile delete mode 100644 board/radxa/rock5b-rk3588/rock5b-rk3588.c delete mode 100644 board/rockchip/evb_rk3588/Makefile delete mode 100644 board/rockchip/evb_rk3588/evb-rk3588.c delete mode 100644 board/turing/turing-rk1-rk3588/Makefile delete mode 100644 board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile b/board/friendlyelec/nanopc-t6-rk3588/Makefile deleted file mode 100644 index c1c49b1970..00 --- a/board/friendlyelec/nanopc-t6-rk3588/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2023 Rockchip Electronics Co,. Ltd. -# - -obj-y += nanopc-t6-rk3588.o diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c deleted file mode 100644 index 99bbef964e..00 --- a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2023 Rockchip Electronics Co,. Ltd. - */ - -#include -#include - -#ifdef CONFIG_OF_BOARD_SETUP I think it may now be possible to remove this symbol from the appropriate defconfigs? Not sure though. Cheers, Quentin
Re: [V1 PATCH 1/2] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
Hi Chris,
On 4/1/24 20:14, Chris Morgan wrote:
From: Chris Morgan
Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with
= 16GB of RAM. In the event that neither SOC is used and the
ROCKCHIP_TPL stage is not used, fall back to existing logic.
Signed-off-by: Chris Morgan
---
arch/arm/mach-rockchip/sdram.c | 100 +
1 file changed, 100 insertions(+)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0aef6f..e02fb03c5f 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -35,11 +36,110 @@ struct tos_parameter_t {
s64 reserve[8];
};
+/* Tag magic */
+#define ATAGS_CORE_MAGIC 0x54410001
+#define ATAGS_DDR_MEM_MAGIC0x54410052
+
+/* Tag size and offset */
+#define ATAGS_SIZE SZ_8K
+#define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE)
+#define ATAGS_PHYS_BASE(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+
+/* ATAGS memory structure. */
+struct tag_ddr_mem {
+ u32 count;
+ u32 version;
+ u64 bank[20];
+ u32 flags;
+ u32 data[2];
+ u32 hash;
+} __packed;
+
+/**
+ * rockchip_dram_init_banksize() - Get RAM banks from Rockchip TPL
+ *
+ * Iterate through the defined ATAGS memory location to first find a
+ * valid core header, then find a valid ddr_info header. Sanity check
+ * the number of banks found. Then, iterate through the data to add
+ * each individual memory bank. Perform fixups on memory banks that
+ * overlap with a reserved space. If an error condition is received,
+ * it is expected that memory bank setup will fall back on existing
+ * logic. If ROCKCHIP_EXTERNAL_TPL is false then immediately return,
+ * and if neither ROCKCHIP_RK3588 or ROCKCHIP_RK3568 is enabled
+ * immediately return.
+ *
+ * Return number of banks found on success or negative on error.
+ */
+__weak int rockchip_dram_init_banksize(void)
+{
+ struct tag_ddr_mem *ddr_info;
+ size_t val;
+ size_t addr = ATAGS_PHYS_BASE;
I think this should be phys_addr_t instead of size_t?
size_t is an unsigned long on aarch64 and phys_addr_t is an unsigned
long long so 4B vs 8B.
This however would likely prevent us from reusing this code on aarch32
machines, but maybe it's a problem for the people who'll look into
supporting this :) (also, aarch32 and >= 3.75GiB may be a bit optimistic
:) ).
+ int i;
+
u8 is plenty enough here :)
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
+ return 0;
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ return 0;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
+ return -EPERM;
+
I think testing once is enough :)
Also, you probably want to use -ENOTSUPP instead?
+ while (addr < (ATAGS_PHYS_BASE + ATAGS_SIZE)) {
+ val = readl(addr);
+ if (val == ATAGS_CORE_MAGIC)
Save a variable by not saving the result of readl and just check against
ATAGS_CORE_MAGIC.
+ break;
+ addr += 4;
This is an incorrect step size, addr is 4B, so this will result in 16B
increments, which may be too much. Additionally, we shouldn't read every
4B as the tag is only ever guaranteed to be 4B aligned, not that we
would have a tag every 4B. This also means that it's possible somehow
the content of a tag at a 4B-aligned offset has the CORE_MAGIC for some
reason, but we shouldn't match on it.
I recommend to follow what Rockchip does downstream:
"""
struct tag_header {
u32 size; /* size in units of 4B */
u32 magic;
};
"""
if magic != CORE_MAGIC, then we should increment addr by size * 4B and
check again.
+ }
+ if (addr >= (ATAGS_PHYS_BASE + ATAGS_SIZE))
+ return -ENODATA;
I think it'd be nice to have debug messages here and there :)
+
+ while (addr < (ATAGS_PHYS_BASE + ATAGS_SIZE)) {
+ val = readl(addr);
+ if (val == ATAGS_DDR_MEM_MAGIC)
+ break;
+ addr += 4;
Same remarks here.
+ }
+ if (addr >= (ATAGS_PHYS_BASE + ATAGS_SIZE))
+ return -ENODATA;
+
+ ddr_info = (void *)addr + 4;
It seems that arithmetic operations on void pointers is illegal in the C
standard. This also quite obfuscate what you want to do here.
Considering that in this patch you're iterating for each 4B until you
get the MAGIC, the next 4B are data for that header of that magic.
If you go for the tag_header I suggested above, I would recommend to do
the following instead:
"""
ddr_info = (u8*)addr +
Re: [PATCH 00/31] rockchip: rk3399: Sync DT with linux v6.8 and update defconfigs
Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails. After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag. I have runtime tested this series on following devices: - 96boards Rock960 - Khadas Edge Captain - Pine64 PineBook Pro - Pine64 RockPro64 - Radxa ROCK 4C+ - Radxa ROCK 4SE - Radxa ROCK Pi 4A - Radxa ROCK Pi 4B+ This series depends on the following series: - Enable booting from SPI flash on ROCK Pi 4 [1] - rockchip: spl: Cache boot source id for later use [2] A copy of this series and all its depends can be found at [3] [1] https://patchwork.ozlabs.org/cover/1912469/ [2] https://patchwork.ozlabs.org/cover/1915071/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1 That's a patch series I warmly welcome, we've been long overdue an update of Rockchip's DTs in U-Boot. Here's to hope we can migrate to use OF_UPSTREAM sooner rather than later and this is a very big step in that direction, so thank you. Cheers, Quentin
Re: [PATCH 17/31] rockchip: rk3399-puma: Sync DT from linux v6.8
compatible = "linux,extcon-usb-gpio";
- id-gpio = < RK_PC2 GPIO_ACTIVE_HIGH>;
+ id-gpios = < RK_PC2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <_id>;
};
@@ -119,6 +120,20 @@
drive-impedance-ohm = <33>;
};
+ {
+ /*
+* The BIOS_DISABLE hog is a feedback pin for the actual status of the
+* signal. This usually represents the state of a switch on the
baseboard.
+* The pin has a 10k pull-up resistor connected, so no pull-up setting
is needed.
+*/
+ bios-disable-hog {
+ gpios = ;
+ gpio-hog;
+ input;
+ line-name = "bios_disable";
+ };
+};
+
{
assigned-clocks = < SCLK_RMII_SRC>;
assigned-clock-parents = <_gmac>;
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index cc3d2cf3755d..26d524cabb06 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -27,7 +27,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x38000
Those are unrelated changes, please in a different commit (but thanks
for catching my mistakes :) ).
Reviewed-by: Quentin Schulz
Thanks,
Quentin
Re: [PATCH 15/31] rockchip: rk3399: Sync soc device tree from linux v6.8
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
Sync RK3399 SoC common .dtsi-files from linux v6.8.
The ethernet0 alias is removed from rk3399.dtsi in this patch, it will
be restored in board specific .dts-files. There is no other intended
Please add ethernet0 alias to rk3399-u-boot.dtsi and remove it in the
patch that moves it to board-specific dts files so that this is not a
breaking change and we can bisect through this patch if we need to :)
change with this patch.
Could you please mention that rng node is named crypto1 in Linux DT? The
diff here was a bit surprising since rng node is entirely removed.
Signed-off-by: Jonas Karlman
---
arch/arm/dts/rk3399-op1-opp.dtsi | 31 +-
arch/arm/dts/rk3399-opp.dtsi | 6 +-
arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 4 -
arch/arm/dts/rk3399-u-boot.dtsi | 52 ++--
arch/arm/dts/rk3399.dtsi | 289 --
5 files changed, 308 insertions(+), 74 deletions(-)
diff --git a/arch/arm/dts/rk3399-op1-opp.dtsi b/arch/arm/dts/rk3399-op1-opp.dtsi
index 69cc9b05baa5..783120e9cebe 100644
--- a/arch/arm/dts/rk3399-op1-opp.dtsi
+++ b/arch/arm/dts/rk3399-op1-opp.dtsi
@@ -4,7 +4,7 @@
*/
/ {
- cluster0_opp: opp-table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -39,7 +39,7 @@
};
};
- cluster1_opp: opp-table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
@@ -82,7 +82,7 @@
};
};
- gpu_opp_table: opp-table2 {
+ gpu_opp_table: opp-table-2 {
compatible = "operating-points-v2";
opp00 {
@@ -110,6 +110,27 @@
opp-microvolt = <1075000>;
};
};
+
+ dmc_opp_table: opp-table-3 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <90>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <66600>;
+ opp-microvolt = <90>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <90>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <92800>;
+ opp-microvolt = <925000>;
+ };
+ };
};
_l0 {
@@ -136,6 +157,10 @@
operating-points-v2 = <_opp>;
};
+ {
+ operating-points-v2 = <_opp_table>;
+};
+
{
operating-points-v2 = <_opp_table>;
};
diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi
index da41cd81ebb7..fee5e7111279 100644
--- a/arch/arm/dts/rk3399-opp.dtsi
+++ b/arch/arm/dts/rk3399-opp.dtsi
@@ -4,7 +4,7 @@
*/
/ {
- cluster0_opp: opp-table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -35,7 +35,7 @@
};
};
- cluster1_opp: opp-table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
@@ -74,7 +74,7 @@
};
};
- gpu_opp_table: opp-table2 {
+ gpu_opp_table: opp-table-2 {
compatible = "operating-points-v2";
opp00 {
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
index b8f95b86d86b..dcfcec4f3072 100644
--- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
@@ -6,10 +6,6 @@
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
- {
- status = "okay";
-};
-
{
max-frequency = <2500>;
};
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index adb64d17e040..d2648abd0a44 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -2,8 +2,6 @@
/*
* Copyright (C) 2019 Jagan Teki
*/
-#define USB_CLASS_HUB 9
-
#include "rockchip-u-boot.dtsi"
/ {
@@ -24,44 +22,11 @@
reg = <0x0 0xff62 0x0 0x100>;
};
- dfi: dfi@ff63 {
- bootph-all;
- reg = <0x00 0xff63 0x00 0x4000>;
- compatible = "rockchip,rk3399-dfi";
- rockchip,pmu = <>;
- clocks = < PCLK_DDR_MON>;
- clock-names = "pclk_ddr_mon";
- };
-
- rng: rng@ff8b8000 {
- compatible = "rockchip,rk3399-crypto";
- reg = <0x0 0xff8b8000 0x0 0x1000>;
- status = "okay";
- };
-
- dmc: dmc {
- bootph-all;
- compatible = "rockchip,rk3399-dmc";
-
Re: [PATCH 14/31] clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support
Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: The SCLK_USB3OTGx_REF clocks is used as reference clock for USB3 block. Add simple support to get rate of SCLK_USB3OTGx_REF clocks to fix reference clock period configuration. Also replace use of 2400 with the OSC_HZ constant. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Thanks, Quentin
Re: [PATCH 13/31] clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock
Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock. The existing enable/disable ops for SCLK_PCIEPHY_REF already handles setting correct parent once the clock gets enabled. And 100 MHz is the default rate used for this clock. I'm not sure that's true? If I read the TRM correctly, clk_pciephy_ref_sel can come either from clk_pcie_ref24m (the default) or clk_pcie_ref100m. enable/disable is actually only ever writing 0 to that bit (bit 10 in CRU_CLKSEL_CON18) and not even enabling the clock. Assuming clk_pcie_ref24m is the 24MHz base clock (which seems to be the case according to the Linux kernel CRU driver), there shouldn't be a way to disable that clock. However, if clk_pcie_ref100m is selected, one needs to enable/disable it via CRU_CLKGATE_CON12 bit 6 (enabled by default). set_parent should be properly implemented to handle this parenting and enable/disable fixed to use the proper register. Cheers, Quentin
Re: [PATCH 10/31] rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC
Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: When RK3399 boards run SPL from eMMC and fail to load FIT from eMMC due to it being missing or checksum validation fails there can be a fallback to read FIT from SD-card. However, without proper pinctrl configuration reading FIT from SD-card may fail: U-Boot SPL 2024.04-rc4 (Mar 17 2024 - 22:54:45 +) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC1 Card did not respond to voltage select! : -110 mmc_init: -95, time 12 spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices (err=-6) ### ERROR ### Please RESET the board ### Fix this by tagging related sdhci and sdmmc pinctrl nodes with bootph props. Also sort and move common nodes shared by all boards to the SoC u-boot.dtsi. Finally imply the SPL_DM_SEQ_ALIAS Kconfig option to enable it on all RK3399 boards. Signed-off-by: Jonas Karlman Review may be easier if we added all missing nodes in one commit, and then another commit to move the common nodes into rk3399-u-boot.dtsi. For Puma, Reviewed-by: Quentin Schulz Thanks, Quentin
Re: [PATCH 08/31] rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options
Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: The TPL and/or SPL control FDT on RK3399 boards does not contain any node with a compatible that is supported by driver/misc/ drivers. Remove use of xPL_MISC_DRIVERS options to stop including e.g an unused efuse driver in TPL and/or SPL. This also makes each board maintainer responsible for enabling CrOS EC (Embedded Controller on Chromebooks) and/or IO domain if they need it in TPL/SPL. But considering Gru Bob and Kevin don't seem to be enabling EC support in TPL/SPL and that IO domain isn't enabled for any board in TPL/SPL, Reviewed-by: Quentin Schulz Thanks, Quentin
Re: [PATCH 09/31] rockchip: rk3399: Add a default spl-boot-order prop
Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: A lot of RK3399 boards use a u-boot,spl-boot-order of "same-as-spl", and Move this to rk3399-u-boot.dtsi and make this default for boards currently missing a u-boot,spl-boot-order prop. The _flash reference has been dropped from spl-boot-order now that boot source id is cached and "same-as-spl" can be resolved into the SPI flash node. This is not really the same thing. This prevents from having U-Boot proper in SPI and TPL+SPL on eMMC/SD card. Is this a real usecase? I don't know, we do support it on Puma (though I know you haven't changed it in this commit). I guess we could still have the devices with SPI flashes have their own u-boot,spl-boot-order if they want. So, in short, I would at the very least document this new limitation in the commit log but have nothing against the change (my board not being impacted by it :) ). Cheers, Quentin
Re: [PATCH 07/31] rockchip: rk3399: Enable DT overlay support on all boards
Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: Imply OF_LIBFDT_OVERLAY Kconfig options to add device tree overlay support on all RK3399 boards. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Thanks, Quentin
Re: [PATCH 06/31] rockchip: rk3399: Imply support for GbE PHY
Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: Imply support for GbE PHY status parsing and configuration when support for onboard ethernet is enabled. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Thanks, Quentin
Re: [PATCH 05/31] rockchip: rk3399: Enable random generator on all boards
Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: The RK3399 SoC contain a crypto engine block that can generate random numbers. Imply DM_RNG and RNG_ROCKCHIP Kconfig options to take advantage of the random generator on all RK3399 boards. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Thanks, Quentin
Re: [PATCH 12/19] rockchip: rk3588: Update bootph props
Hi Jonas,
On 4/2/24 15:36, Jonas Karlman wrote:
Hi Quentin,
On 2024-04-02 13:20, Quentin Schulz wrote:
Hi Jonas,
On 3/29/24 20:01, Jonas Karlman wrote:
[...]
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index e4171bd24d2a..a502a82fae6a 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -121,31 +121,35 @@
};
{
- bootph-pre-ram;
+ bootph-all;
};
_bus8 {
- bootph-all;
+ bootph-pre-ram;
};
_clk {
- bootph-all;
+ bootph-pre-ram;
};
_cmd {
- bootph-all;
+ bootph-pre-ram;
};
_data_strobe {
- bootph-all;
+ bootph-pre-ram;
};
_rstnout {
- bootph-all;
+ bootph-pre-ram;
};
{
- bootph-pre-ram;
+ bootph-all;
+};
+
+_pull_down {
+ bootph-all;
};
_pull_none {
@@ -157,6 +161,10 @@
};
_pull_up_drv_level_2 {
+ bootph-pre-ram;
+};
+
+_grf {
bootph-all;
};
@@ -189,19 +197,23 @@
};
_bus4 {
- bootph-all;
+ bootph-pre-ram;
};
_clk {
- bootph-all;
+ bootph-pre-ram;
};
_cmd {
- bootph-all;
+ bootph-pre-ram;
};
_det {
- bootph-all;
+ bootph-pre-ram;
+};
+
Please add bootph-some-ram to all nodes related to eMMC/SD card
otherwise I assume some boards won't work anymore (e.g. the ones that
need to find MMC devices through DT in arch_env_get_location, e.g.
Theobroma's Jaguar (and soon Tiger)).
Sure I will add them in a v2.
When I tested your arch_env_get_location() it did not seem to require
any pinctrl nodes at pre-reloc stage.
Mm... I assume it is because the device checked in
arch_env_get_location() in U-Boot proper pre-reloc is necessarily the
same as the one used to load U-Boot proper from SPL, which means the SPL
will have set the mux correctly (because of bootph-pre-ram). I don't
think U-Boot proper pre-reloc has a separate DTB from U-Boot proper, so
I think it checks only for boopth-some-ram property in the MMC
controller node, and maybe not for pinctrl nodes?
Ideally we should be able to skip use of DM, env and serial at pre-reloc
stage for Rockchip. Serial and pinctrl already gets configured in SPL, and
use of DM slows down boot by 200-700ms, but that is for another series ;-)
Agreed :)
c.f.
https://source.denx.de/u-boot/u-boot/-/commit/70f9212d61fe79c605b805c6eb0764b29f8ae3b6
It was not easy to have this merged, so I'd prefer to avoid having to go
through it again to fix my board(s) :)
It'd be nice to split this into multiple commits so we can have some
individual justification of why such a change is made, so that we know
if we need to revert/update it in the future.
Will try to split this in v2.
In summary some pinctrl or nodes referenced was not enabled for SPL
stage, and some was enabled for TPL that should never be needed in TPL,
if U-Boot TPL will be used in future.
TPL: uart node + dmc/ram and any node required/referenced
SPL: TPL + sdmmc/sdhci/spi-flash nodes and related pinctrl
For the -u-boot.dtsi, I guess this is good enough, we may need more
though for some boards (e.g. emmc-reset, gpios, etc...).
pre-reloc: TPL + sdmmc/sdhci/spi-flash nodes
I created a python script [1] that can check the built tpl/spl/proper
dtb for missing nodes and some config options for all soc targets.
[1] https://gist.github.com/Kwiboo/34c099fb42eb6ae5ed515a04275a7ed7
Ooh this seems really neat. I'm always very careful when adding
support for a new board and I'm always afraid to miss a few nodes, I'll
try to not forget to have a look at this for adding support for Tiger
RK3588 :)
Do you have any plan of submitting this on the ML? I think this could be
beneficial to the project!
Cheers,
Quentin
Re: [PATCH 08/19] rockchip: rk35xx: Imply support for GbE PHY
Hi Jonas, On 4/2/24 14:54, Jonas Karlman wrote: Hi Quentin, On 2024-04-02 13:11, Quentin Schulz wrote: Hi Jonas, On 3/29/24 20:01, Jonas Karlman wrote: Imply support for GbE PHY status parsing and configuration when support for onboard ethernet is enabled. Signed-off-by: Jonas Karlman --- arch/arm/mach-rockchip/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d518913f8a37..d85b59a92da2 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -316,6 +316,7 @@ config ROCKCHIP_RK3568 imply MISC_INIT_R imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP imply OF_LIBFDT_OVERLAY + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP Is this really something we expect most devices to use? We have two products based on RK3588, none use it. If I'm not mistaken, Rock5B doesn't as well as Orange Pi 5 Plus, RK3588 EVB, Rock5A, (likely not the Edgeble as well since they have 2.5Gbps connectors), NanoPC T6, IndieDroid Nova, Cool Pi 4B, Cool Pi CM5 EVB, NanoPi R6S, Rockchip Toybrick TB-RK3588X. So, I'm not sure it's worth it making it the default? (Even though we could remove it from the defconfig manually). Wouldn't this make more sense in your generic defconfigs? The PHY_GIGE option is only used to control if miiphy_speed() and miiphy_duplex() should use MII_STAT1000 reg to determine speed/duplex. This patch only imply this option if a board use on-board gmac and have DWC_ETH_QOS_ROCKCHIP enabled. Mostly this only help the "mii info" command to show 1000baseT instead of max 100baseT. I can drop this if you think it will cause an issue for any board? No no, this is fine thanks for the correction. I don't know what happened for my brain to read this as "enable support for integrated PHY by default" (c.f. the list of boards I listed not having integrated PHYs). Sorry for the noise, Reviewed-by: Quentin Schulz Thanks, Quentin
Re: [PATCH 18/19] rockchip: rk356x-generic: Add support for SPI flash and USB OTG
Hi Jonas,
On 4/2/24 14:37, Jonas Karlman wrote:
Hi Quentin,
On 2024-04-02 12:38, Quentin Schulz wrote:
Hi Jonas,
On 3/29/24 20:01, Jonas Karlman wrote:
Extend the Generic RK3566/RK3568 target to also include support for SPI
flash, USB OTG, RockUSB and UMS.
Also fix sdmmc alias, include missing pinctrl and add broken-cd prop to
fix use of SD-card in linux.
I think we would have benefit with more and smaller commits there, but
since you're the one mainly maintaining those generic devices, up to you.
I can try to split it in a v2.
[...]
{
+ broken-cd;
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
no-mmc;
no-sdio;
pinctrl-names = "default";
- pinctrl-0 = <_bus4 _clk _cmd>;
+ pinctrl-0 = <_bus4 _clk _cmd _det>;
This is... surprising.
`broken-cd` but we still mux the SDMMC_DET pin in the SD card detect
function?
According to the dt binding, if broken-cd is provided, we should do
polling. If neither cd-gpios nor broken-cd is passed, host native card
detect will be used (which I assume means the SD card controller handles
this internally).
c.f.
https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/mmc/mmc-controller.yaml#L33
What are we supposed to do there actually, because this seems to be
contradicting itself?
The generic DTs is intended to be able to be use as control FDT in
U-Boot with any board that mostly follows reference hw dedign as close
as possible.
broken-cd was added to fool U-Boot (and possible Linux) into thinking a
card is present. And the sdmmc0_det pinctrl was added to satisfy the
controller logic and auto jtag.
You shouldn't need to fool auto jtag anymore on RK3588 since
https://source.denx.de/u-boot/u-boot/-/commit/5d710738bb1e0ff2bb93ce7baf4c9691ce919b53
since it would be disabled except if you enable it by hand via the symbol.
I assume you need a similar patch for RK3568.
Linux disables auto jtag automatically for RK3588 since
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/soc/rockchip/grf.c?id=6f6878ec6faf16a5f36761c93da6ea9cf09adb33.
I guess you need a similar patch for RK3568?
When I tried to boot into linux with the control FDT prior to this, only
eMMC was detected and working, after these changes SD-card was working.
Will re-try without broken-cd for v2.
I think it'd make sense to properly patch this by disabling autojtag
feature instead :)
status = "okay";
};
+ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <2400>;
Random thought, but shouldn't we update common/spl/spl_spi.c to read
this value instead of using CONFIG_SF_DEFAULT_SPEED? (Nothing to do in
this patch series though :) ).
For U-Boot proper the value from this prop is used, SF_DEFAULT_SPEED is
only used in SPL.
Yup, but I assume we have DM support for SPI flashes in SPL, so we could
do this instead of having to rely on a defconfig symbol :)
[...]
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index e7d5e55bbfd8..b458080cd539 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -3,17 +3,22 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic"
CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE66
CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+# CONFIG_BOOTMETH_VBE is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
@@ -21,32 +26,58 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x4
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
This seems surprising, do you really want to get rid of network support
for the generic board defconfig?
My intention with the generic tar
Re: [PATCH 04/31] rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation
Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: The RK3399 SoC support the ARMv8 Cryptography Extensions, use of ARMv8 crypto can speed up FIT checksum validation in SPL. Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto extensions for SHA256 when validating checksum of FIT images. Imply SPL_FIT_SIGNATURE and LEGACY_IMAGE_FORMAT to enable FIT checksum validation to almost all RK3399 boards. The following boards have been excluded: - chromebook_bob: SPL max size limitation of 120 KiB - chromebook_kevin: SPL max size limitation of 120 KiB - puma-rk3399: SPL stack in SRAM and TPL+SPL combined max size limitation of 224 KiB I think we should move the SPL stack out of SRAM, thanks for hinting at this. This is clearly something I missed when migrating Puma to TPL+SPL as all other devices were migrated way earlier than this board, c.f. https://source.denx.de/u-boot/u-boot/-/commit/f113d7d3034672de7d074506a05a7055f1f0dcae for the default address. Considering that SPL_MAX_SIZE is set to 0x2e000 (184K) right now, we should fail if we reach that size. But I couldn't with applying the same changes as in this patch, is there something I'm missing that prevents this from happening on Puma? Just trying to figure out what we need to do to not stay too far from most RK3399 devices :) """ diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2aa02ec74b..f3d23fa3f11 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -21,8 +21,12 @@ CONFIG_DEBUG_UART_BASE=0xFF18 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_ARMV8_SET_SMPEN=y +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y @@ -115,4 +119,5 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y +# CONFIG_RSA is not set CONFIG_ERRNO_STR=y """ (not booted). Additionally, I think I should be able to bump SPL_MAX_SIZE to 0x3 (224K offset for U-Boot proper on MMC - 32K offset for TPL+SPL on MMC), don't you think? Backward compatibility is a PITA :) Cheers, Quentin
Re: [PATCH 02/31] rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr
Hi Jonas, On 3/31/24 22:28, Jonas Karlman wrote: The rk3399-ficus board is only using SPL and not TPL+SPL like all other RK3399 boards, chromebook bob/kevin excluded. It does not seem to be any technical reason why this board was left using only SPL. Switch to use TPL+SPL and use common bss and stack addresses to allow for more options to be enabled in a future patch. Also add the missing DEFAULT_FDT_FILE option. Signed-off-by: Jonas Karlman --- configs/ficus-rk3399_defconfig | 14 ++ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 4859042d6b56..3bcd0fd66b91 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -2,32 +2,22 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x0020 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30 CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" -CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y -CONFIG_SPL_STACK=0xff8e CONFIG_DEBUG_UART_BASE=0xFF1A CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e -CONFIG_SPL_BSS_MAX_SIZE=0x1 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y I think we want to move CONFIG_SPL_STACK to match other RK3399 devices as well? Indeed, it is currently set to 0xff8e which matches the default value for when TPL was NOT enabled. 0x40 is used for devices with TPL support. c.f. https://source.denx.de/u-boot/u-boot/-/commit/f113d7d3034672de7d074506a05a7055f1f0dcae Cheers, Quentin
Re: [PATCH] clk: rockchip: rk3399: Add SCLK_UART4_PMU support
Hi, On 4/2/24 12:01, xiaofengvskuye wrote: [You don't often get email from xiaofengvsk...@hotmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] The SCLK_UART4_PMU clocks is used as reference clock for UART4 block. Add simple support to get rate of SCLK_UART4_PMU clocks to fix reference clock period configuration. Signed-off-by: xiaofengvskuye --- drivers/clk/rockchip/clk_rk3399.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index c37e8a53a2..a9114c4b02 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1563,6 +1563,8 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk) case SCLK_I2C8_PMU: rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); break; +case SCLK_UART4_PMU: + return 2400; Please be mindful about the indentation. Additionally, UART4 can be at a different rate than 24MHz, it depends on the value of uart4_clk_sel (which defaults to 24MHz source clock, indeed). I would suggest to do this support entirely and handle all three clock sources and return the current rate. Cheers, Quentin
Re: [PATCH 1/1] net: dw_eth_qos: Add missing \n in error messages.
Hi Heinrich,
On 4/2/24 10:39, Heinrich Schuchardt wrote:
Missing line-feeds in error messages lead to output like:
phy_startup() failed: -110FAILED: -110=>
Output like the following is much easier to read:
phy_startup() failed: -110
FAILED: -110
=>
Signed-off-by: Heinrich Schuchardt
---
drivers/net/dwc_eth_qos.c | 108 +++---
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9b3bce1dc87..1b4d0eda887 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -159,7 +159,7 @@ static int eqos_mdio_read(struct mii_dev *bus, int
mdio_addr, int mdio_devad,
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
- pr_err("MDIO not idle at entry");
+ pr_err("MDIO not idle at entry\n");
What about using this as an opportunity to migrate to dev_err?
(considering there are two GMAC controllers on RK3588(s), this would
help identify which has an issue :) ).
Cheers,
Quentin
Re: [PATCH 12/19] rockchip: rk3588: Update bootph props
Hi Jonas,
On 3/29/24 20:01, Jonas Karlman wrote:
[...]
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index e4171bd24d2a..a502a82fae6a 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -121,31 +121,35 @@
};
{
- bootph-pre-ram;
+ bootph-all;
};
_bus8 {
- bootph-all;
+ bootph-pre-ram;
};
_clk {
- bootph-all;
+ bootph-pre-ram;
};
_cmd {
- bootph-all;
+ bootph-pre-ram;
};
_data_strobe {
- bootph-all;
+ bootph-pre-ram;
};
_rstnout {
- bootph-all;
+ bootph-pre-ram;
};
{
- bootph-pre-ram;
+ bootph-all;
+};
+
+_pull_down {
+ bootph-all;
};
_pull_none {
@@ -157,6 +161,10 @@
};
_pull_up_drv_level_2 {
+ bootph-pre-ram;
+};
+
+_grf {
bootph-all;
};
@@ -189,19 +197,23 @@
};
_bus4 {
- bootph-all;
+ bootph-pre-ram;
};
_clk {
- bootph-all;
+ bootph-pre-ram;
};
_cmd {
- bootph-all;
+ bootph-pre-ram;
};
_det {
- bootph-all;
+ bootph-pre-ram;
+};
+
Please add bootph-some-ram to all nodes related to eMMC/SD card
otherwise I assume some boards won't work anymore (e.g. the ones that
need to find MMC devices through DT in arch_env_get_location, e.g.
Theobroma's Jaguar (and soon Tiger)).
c.f.
https://source.denx.de/u-boot/u-boot/-/commit/70f9212d61fe79c605b805c6eb0764b29f8ae3b6
It was not easy to have this merged, so I'd prefer to avoid having to go
through it again to fix my board(s) :)
It'd be nice to split this into multiple commits so we can have some
individual justification of why such a change is made, so that we know
if we need to revert/update it in the future.
Cheers,
Quentin
Re: [PATCH 08/19] rockchip: rk35xx: Imply support for GbE PHY
Hi Jonas, On 3/29/24 20:01, Jonas Karlman wrote: Imply support for GbE PHY status parsing and configuration when support for onboard ethernet is enabled. Signed-off-by: Jonas Karlman --- arch/arm/mach-rockchip/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d518913f8a37..d85b59a92da2 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -316,6 +316,7 @@ config ROCKCHIP_RK3568 imply MISC_INIT_R imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP imply OF_LIBFDT_OVERLAY + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP Is this really something we expect most devices to use? We have two products based on RK3588, none use it. If I'm not mistaken, Rock5B doesn't as well as Orange Pi 5 Plus, RK3588 EVB, Rock5A, (likely not the Edgeble as well since they have 2.5Gbps connectors), NanoPC T6, IndieDroid Nova, Cool Pi 4B, Cool Pi CM5 EVB, NanoPi R6S, Rockchip Toybrick TB-RK3588X. So, I'm not sure it's worth it making it the default? (Even though we could remove it from the defconfig manually). Wouldn't this make more sense in your generic defconfigs? Cheers, Quentin
Re: [PATCH 02/19] clk: rockchip: rk3588: Add REF_CLK_USB3OTGx support
Hi Jonas, On 3/29/24 20:01, Jonas Karlman wrote: The REF_CLK_USB3OTGx clocks is used as reference clock for USB3 block. Add simple support to get rate of REF_CLK_USB3OTGx clocks to fix reference clock period configuration. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Thanks, Quentin
Re: [PATCH 18/19] rockchip: rk356x-generic: Add support for SPI flash and USB OTG
Hi Jonas,
On 3/29/24 20:01, Jonas Karlman wrote:
Extend the Generic RK3566/RK3568 target to also include support for SPI
flash, USB OTG, RockUSB and UMS.
Also fix sdmmc alias, include missing pinctrl and add broken-cd prop to
fix use of SD-card in linux.
I think we would have benefit with more and smaller commits there, but
since you're the one mainly maintaining those generic devices, up to you.
[...]
{
+ broken-cd;
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
no-mmc;
no-sdio;
pinctrl-names = "default";
- pinctrl-0 = <_bus4 _clk _cmd>;
+ pinctrl-0 = <_bus4 _clk _cmd _det>;
This is... surprising.
`broken-cd` but we still mux the SDMMC_DET pin in the SD card detect
function?
According to the dt binding, if broken-cd is provided, we should do
polling. If neither cd-gpios nor broken-cd is passed, host native card
detect will be used (which I assume means the SD card controller handles
this internally).
c.f.
https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/mmc/mmc-controller.yaml#L33
What are we supposed to do there actually, because this seems to be
contradicting itself?
status = "okay";
};
+ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <2400>;
Random thought, but shouldn't we update common/spl/spl_spi.c to read
this value instead of using CONFIG_SF_DEFAULT_SPEED? (Nothing to do in
this patch series though :) ).
[...]
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index e7d5e55bbfd8..b458080cd539 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -3,17 +3,22 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic"
CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE66
CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+# CONFIG_BOOTMETH_VBE is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
@@ -21,32 +26,58 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x4
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
This seems surprising, do you really want to get rid of network support
for the generic board defconfig?
Cheers,
Quentin
Re: [PATCH 15/19] rockchip: rk3588-toybrick: Add missing Kconfig options
Hi Jonas,
On 3/29/24 20:01, Jonas Karlman wrote:
Add .dtb-file entry to Makefile and enable Kconfig options required to
configure pinctrl in SPL. Also add missing PHY_ROCKCHIP_NANENG_COMBOPHY.
Fixes: 9fdd9a546986 ("board: rockchip: add Rockchip Toybrick TB-RK3588X board")
Signed-off-by: Jonas Karlman
---
arch/arm/dts/Makefile | 1 +
configs/toybrick-rk3588_defconfig | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f49b7e5d251f..3e0bad8306b5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -207,6 +207,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb \
+ rk3588-toybrick-x0.dts \
Should be .dtb here I guess :)
Cheers,
Quentin
Re: [PATCH 10/19] rockchip: rk35xx: Sort soc u-boot.dtsi alphabetically
Hi Jonas,
On 3/29/24 20:01, Jonas Karlman wrote:
Sort nodes and props in RK356x/RK3588 u-boot.dtsi alphabetically, nodes
is sorted by reg addr then by alphabetical order.
This has no intended change beside sorting existing nodes and removing
a duplicated usbdpphy0_grf node.
Signed-off-by: Jonas Karlman
---
arch/arm/dts/rk356x-u-boot.dtsi | 100 +++
arch/arm/dts/rk3588s-u-boot.dtsi | 71 ++
2 files changed, 83 insertions(+), 88 deletions(-)
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 05367216e118..a0c630326217 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -17,8 +17,8 @@
};
dmc: dmc {
- compatible = "rockchip,rk3568-dmc";
bootph-all;
+ compatible = "rockchip,rk3568-dmc";
This doesn't follow the kernel's DT coding style:
https://www.kernel.org/doc/html/latest/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
[...]
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 233eb79d9ba2..e4171bd24d2a 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -15,8 +15,8 @@
};
dmc {
- compatible = "rockchip,rk3588-dmc";
bootph-all;
+ compatible = "rockchip,rk3588-dmc";
Ditto.
Cheers,
Quentin
Re: [PATCH 2/2] rockchip: rk3588: Add Support for RAM Defines from ATAGs
Hi Chris,
On 3/26/24 21:49, Chris Morgan wrote:
From: Chris Morgan
Add support for defining the usable RAM from ATAGs provided by the
Rockchip binary TPL loader. This allows us to automatically account
for necessary memory holes on RK3588 devices with 16GB of RAM or
more, as well as ensure we can use the full amount of RAM available.
In the event we can't cleanly read the ATAG values from RAM or are
not running an RK3588 board, simply fall back to the old method of
detecting the RAM.
Tested on Indiedroid Nova with 4GB and 16GB of RAM.
Signed-off-by: Chris Morgan
---
arch/arm/mach-rockchip/sdram.c | 58 ++
1 file changed, 58 insertions(+)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0d9a0aef6f..58b78466b0 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
@@ -35,12 +36,69 @@ struct tos_parameter_t {
s64 reserve[8];
};
+/*
+ * Read the ATAGs to identify all the memory banks. If we can't do it
+ * cleanly return 1 to note an unsuccessful attempt, otherwise return
+ * 0 for a successful attempt.
Return a valid error code instead? Negative if possible?
+ */
+int rockchip_atag_ram_banks(void)
+{
+ struct tag *t;
+ int bank_cnt;
+ size_t tmp;
+
+ if (!CONFIG_IS_ENABLED(ARM64) && !CONFIG_IS_ENABLED(ROCKCHIP_RK3588))
+ return 1;
+
+ t = atags_get_tag(ATAG_DDR_MEM);
I believe this will not compile for non RK3588 because this function is
not defined.
There are a few ways to handle this:
- always compile atags.c but have ifdefs there with inline functions
returning -ENOTSUPP or something like that.
+ if (!t)
+ return 1;
+
-ENOENT? -ENOXIO?
+ bank_cnt = t->u.ddr_mem.count;
+
+ /*
+* Check to make sure the first bank ends at 0xf000, if it
Explain what 0xf000 represents here.
+* does not fall back to the other methods of RAM bank
+* detection.
Do we really need the first bank to ends exactly at 0xf000? Or
should we rather make sure that it doesn't go into that space? (so
anything below that would be fine?). I assume this is the result of some
experiments, what did you learn from those boards?
+*/
+ if (t->u.ddr_mem.bank[t->u.ddr_mem.count] != 0xf000)
+ return 1;
+
-EINVAL?
+ /*
+* Iterate over the RAM banks. If the start address of bank 0
+* is less than or equal to 0x20, set it to 0x20 to
+* reserve room for A-TF. Make sure the size of bank 0 doesn't
+* bleed into the address space for hardware (starting at
+* 0xf000). Banks 1 and on can be defined as-is.
+*/
+ for (int i = 0; i < (t->u.ddr_mem.count); i++) {
This may result in out-of-bounds access. Indeed gd->bd->bi_dram is a
build-time allocated array of size CONFIG_NR_DRAM_BANKS.
So I would recommend printing an error message if t->u.ddr_mem.count is
bigger than CONFIG_NR_DRAM_BANKS. I assume we may want to still boot but
with less RAM in that case? If we do, then only loop for the min between
t->u.ddr_mem.count and CONFIG_NR_DRAM_BANKS.
+ if (i == 0) {
+ if (t->u.ddr_mem.bank[i] <= 0x20)
+ gd->bd->bi_dram[i].start = 0x20;
+ else
+ gd->bd->bi_dram[i].start = t->u.ddr_mem.bank[i];
+ tmp = gd->bd->bi_dram[i].start +
t->u.ddr_mem.bank[(bank_cnt + i)];
This is incorrect, it may be offsetting up to 0x20. If it's offset,
you need to remove it from the address size.
"""
if (t->u.ddr_mem.bank[i] <= 0x20)
tmp -= 0x20;
"""
+ if (tmp > 0xf000)
+ gd->bd->bi_dram[i].size = 0xf000 -
gd->bd->bi_dram[i].start;
Shouldn't we do this check for all declared address spaces, not only the
first one?
+ else
+ gd->bd->bi_dram[i].size =
t->u.ddr_mem.bank[(bank_cnt + i)];
You may need to remove the 0x20 offset here as well, e.g. with
"""
if (tmp > 0xf000)
tmp = 0xf000;
gd->bd->bi_dram[i].size = tmp - gd->bd->bi_dram[i].start;
"""
Renaming tmp into end would probably also help figure out what it's
supposed to contain.
+ } else {
+ gd->bd->bi_dram[i].start = t->u.ddr_mem.bank[i];
+ gd->bd->bi_dram[i].size = t->u.ddr_mem.bank[(bank_cnt +
i)];
+ }
+ };
+
You can make this for-loop logic a bit more readable (well, to me :) ) with:
"""
/* Iterate over the RAM banks. */
/* If the start address of bank 0
* is less than or equal to 0x20, set it to 0x20 to
* reserve room for A-TF. Make sure the size of bank 0 doesn't
* bleed
Re: [PATCH 1/2] rockchip: rk3588: Add support for ATAG parsing
Hi Chris,
On 3/26/24 21:49, Chris Morgan wrote:
From: Chris Morgan
Add support for parsing the ATAGs created by the Rockchip binary
RAM init. This ATAG parsing code was taken from the Rockchip BSP
U-Boot source and tested only on parsing the RAM specific ATAGs
for the RK3588.
Can you tell us from which commit (and maybe branch/tag in the event
they rename/rebase/delete branches) exactly so we can check if they fix
stuff downstream every now and then?
Signed-off-by: Chris Morgan
---
arch/arm/include/asm/arch-rockchip/atags.h | 222 +
arch/arm/mach-rockchip/Makefile| 1 +
arch/arm/mach-rockchip/atags.c | 99 +
3 files changed, 322 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/atags.h
create mode 100644 arch/arm/mach-rockchip/atags.c
diff --git a/arch/arm/include/asm/arch-rockchip/atags.h
b/arch/arm/include/asm/arch-rockchip/atags.h
new file mode 100644
index 00..9bae66d7f8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/atags.h
@@ -0,0 +1,222 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd
+ *
+ */
+
+#ifndef __RK_ATAGS_H_
+#define __RK_ATAGS_H_
+
+/* Tag magic */
+#define ATAG_CORE 0x54410001
+#define ATAG_NONE 0x
+
+#define ATAG_SERIAL0x54410050
+#define ATAG_BOOTDEV 0x54410051
+#define ATAG_DDR_MEM 0x54410052
+#define ATAG_TOS_MEM 0x54410053
+#define ATAG_RAM_PARTITION 0x54410054
+#define ATAG_ATF_MEM 0x54410055
+#define ATAG_PUB_KEY 0x54410056
+#define ATAG_SOC_INFO 0x54410057
+#define ATAG_BOOT1_PARAM 0x54410058
+#define ATAG_PSTORE0x54410059
+#define ATAG_FWVER 0x5441005a
+#define ATAG_MAX 0x544100ff
+
+/* Tag size and offset */
+#define ATAGS_SIZE (0x2000)/* 8K */
+#define ATAGS_OFFSET (0x20 - ATAGS_SIZE)/* [2M-8K, 2M] */
+#define ATAGS_PHYS_BASE(CFG_SYS_SDRAM_BASE + ATAGS_OFFSET)
+
+/* tag_fwver.ver[fwid][] */
+#define FWVER_LEN 36
+
+enum fwid {
+ FW_DDR,
+ FW_SPL,
+ FW_ATF,
+ FW_TEE,
+ FW_MAX,
+};
+
+struct tag_serial {
+ u32 version;
+ u32 enable;
+ u64 addr;
+ u32 baudrate;
+ u32 m_mode;
+ u32 id;
+ u32 reserved[2];
+ u32 hash;
+} __packed;
+
+struct tag_bootdev {
+ u32 version;
+ u32 devtype;
+ u32 devnum;
+ u32 mode;
+ u32 sdupdate;
+ u32 reserved[6];
+ u32 hash;
+} __packed;
+
+struct tag_ddr_mem {
+ u32 count;
+ u32 version;
+ u64 bank[20];
+ u32 flags;
+ u32 data[2];
+ u32 hash;
+} __packed;
+
+struct tag_tos_mem {
+ u32 version;
+ struct {
+ char name[8];
+ u64 phy_addr;
+ u32 size;
+ u32 flags;
+ } tee_mem;
+
+ struct {
+ char name[8];
+ u64 phy_addr;
+ u32 size;
+ u32 flags;
+ } drm_mem;
+
+ u64 reserved[7];
+ u32 reserved1;
+ u32 hash;
+} __packed;
+
+struct tag_atf_mem {
+ u32 version;
+ u64 phy_addr;
+ u32 size;
+ u32 flags;
+ u32 reserved[2];
+ u32 hash;
+} __packed;
+
+struct tag_pub_key {
+ u32 version;
+ u32 len;
+ u8 data[768]; /* u32 rsa_n[64], rsa_e[64], rsa_c[64] */
+ u32 flag;
+ u32 reserved[5];
+ u32 hash;
+} __packed;
+
+struct tag_ram_partition {
+ u32 version;
+ u32 count;
+ u32 reserved[4];
+
+ struct {
+ char name[16];
+ u64 start;
+ u64 size;
+ } part[6];
+
+ u32 reserved1[3];
+ u32 hash;
+} __packed;
+
+struct tag_soc_info {
+ u32 version;
+ u32 name; /* Hex: 0x3288, 0x3399... */
+ u32 flags;
+ u32 reserved[6];
+ u32 hash;
+} __packed;
+
+struct tag_boot1p {
+ u32 version;
+ u32 param[8];
+ u32 reserved[4];
+ u32 hash;
+} __packed;
+
+struct tag_pstore {
+ u32 version;
+ struct {
+ u32 addr;
+ u32 size;
+ } buf[16];
+ u32 hash;
+} __packed;
+
+struct tag_fwver {
+ u32 version;
+ char ver[8][FWVER_LEN];
+ u32 hash;
+} __packed;
+
+struct tag_core {
+ u32 flags;
+ u32 pagesize;
+ u32 rootdev;
+} __packed;
+
+struct tag_header {
+ u32 size; /* bytes = size * 4 */
+ u32 magic;
+} __packed;
+
+/* Must be 4 bytes align */
+struct tag {
+ struct tag_header hdr;
+ union {
+ struct tag_core core;
+ struct tag_serial serial;
+ struct tag_bootdev bootdev;
+ struct tag_ddr_mem ddr_mem;
+ struct tag_tos_mem tos_mem;
+ struct tag_ram_partition
Re: [PATCH] mmc: rockchip_sdhci: Revert 4 blocks PIO mode read limit for RK35xx
Hi Jonas,
On 3/27/24 00:35, Jonas Karlman wrote:
The commit 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks
read in a single command") introduced a limit of number of blocks to
read to fix a Data End Bit Error on RK3568 and RK3588. This had a side
affect of significant slowing down reading FIT from eMMC.
After the commit 6de9d7b2f13c ("rockchip: rk35xx: Enable eMMC HS200 mode
by default") the limit of number of blocks to read workaround is no
longer necessary and a Data End Bit Error is no longer happening using
PIO mode.
Revert this limitation to allow reading more than 4 blocks with a single
CMD18 command in PIO mode and speed up reading FIT from eMMC.
Should we instead keep this code but surround it with
#if !IS_ENABLED(MMC_HS200_SUPPORT)
?
After all, HS200 is only implied for RK35xx boards, so one could disable it.
Also wondering whether we should do this dynamically based on the MMC
mode that could be negotiated with the chip? E.g. I think it's not
guaranteed that with hs200 support built and enabled in DT that it'll be
negotiated as HS200?
Cheers,
Quentin
Re: [PATCH] rockchip: ringneck-px30: put STM32_RST line in input mode instead of output
Hi Kever, On 2/19/24 10:50, Quentin Schulz wrote: Hi Kever, On 2/18/24 02:14, Kever Yang wrote: Hi Quentin, On 2024/2/9 21:18, Quentin Schulz wrote: From: Quentin Schulz The STM32_RST line is routed to the ATtiny microcontroller PA0/RESET/UPDI pin. By driving the PX30 SoC pin as GPIO output high, we prevent external UPDI to be used for flashing without first putting this pin as GPIO input, an extra step we could avoid in userspace. A little confuse here, this GPIO is an output for PX30, right?So the config is: 1. the PX30 SPL init STM32_RST as input, with hardware pull-up the keep STM32 work; The pin needs to be high for STM32, and high **but not driven** for ATtiny in order to allow flashing scripts to work. 2. when need UPDI for flashing, need to set STM32_RST to output and trigger the reset in userspace? For STM32, STM32_RST needs to be driven low, then STM32_BOOT needs to be driven high, then STM32_RST needs to be high to deassert reset. For ATtiny, STM32_RST needs to be NOT driven so that UPDI lines can be used to interact with the MCU. Note that we also have the ability to do bitbang UPDI on that STM32_RST pin but that's another topic (just explaining why it is routed while seemingly useless for ATtiny). All the above is for entering the flashing mode. However, in U-Boot we do NOT want to enter flashing mode, we want to exit it, c.f. https://lore.kernel.org/u-boot/20231103-ringneck-stm32-reset-v2-1-a0e5559f8...@theobroma-systems.com/ An external HW pull-up is required because of glitches on the line when powering up/down. However, this is only done on newer versions of the PCB, so we need to tackle old versions. The old versions do not have this external HW pull-up and the glitch may cause the MCU to enter its flashing mode. Therefore, we force it to exit the flashing mode by always hard resetting it into the normal runtime mode. This is what spl_board_init() does. STM32_RST and STM32_BOOT are controlled by our flashing script for the STM32 variant for the MCU, so the default state when entering the Linux kernel doesn't matter. For the ATtiny MCU variant, we do not handle those GPIOs as part of the flashing script, therefore the default state when entering the Linux kernel should be the expected value for which we can use UPDI to flash the ATtiny. For ATtiny, the reset line is shared between STM32_RST that goes to the SoC and the UPDI lines exposed over the Q7 header. If STM32_RST is driven by the SoC, the UPDI lines won't be able to interact with the MCU. Therefore it needs to be put into input mode, whether in U-Boot or in Linux userspace. Can we have this in the next merge request for next please? Or maybe there's something I need to change here? Cheers, Quentin
Re: [PATCH] rockchip: spl: Cache boot source id for later use
Hi Jonas,
On 3/15/24 18:34, Jonas Karlman wrote:
Rockchip BROM write a boot source id at CFG_IRAM_BASE + 0x10, the id
indicate from what storage media TPL/SPL was loaded from.
SPL use this value to determine what device "same-as-spl" represent when
determining from where FIT should be loaded. This works as long as the
boot_devices array contain a matching id <-> node path entry.
However, SPL typically load a small part of TF-A into SRAM and on RK3399
this overwrites the CFG_IRAM_BASE + 0x10 addr used for boot source id.
Here boot source id is 3 before FIT images is loaded, and 0 after:
U-Boot SPL 2024.04-rc4 (Mar 15 2024 - 17:26:19 +)
board_spl_was_booted_from: brom_bootdevice_id 3 maps to
'/spi@ff1d/flash@0'
Trying to boot from SPI
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256+ OK
## Checking hash(es) for Image u-boot ... sha256+ OK
## Checking hash(es) for Image fdt-1 ... sha256+ OK
## Checking hash(es) for Image atf-2 ... sha256+ OK
## Checking hash(es) for Image atf-3 ... sha256+ OK
board_spl_was_booted_from: failed to resolve brom_bootdevice_id 0
spl_decode_boot_device: could not find udevice for /mmc@fe33
spl_decode_boot_device: could not find udevice for /mmc@fe32
spl_perform_fixups: could not map boot_device to ofpath: -19
Use a static bootdevice_brom_id to cache the boot source id after an
initial read from SRAM to fix this, this allow spl_perform_fixups() to
resolve correct boot source path for "same-as-spl" after SPL have loaded
TF-A related FIT images into memory.
With this the spl-boot-device prop can correctly be resolved to the
SPI flash node in the control FDT:
=> fdt addr ${fdtcontroladdr}
Working FDT set to f1ee6710
=> fdt list /chosen
chosen {
u-boot,spl-boot-device = "/spi@ff1d/flash@0";
stdout-path = "serial2:150n8";
u-boot,spl-boot-order = "same-as-spl", "/mmc@fe33", "/mmc@fe32";
};
I'm perplexed. We make use of this spl-boot-device DT property on Puma
(RK3399) and Ringneck (PX30) and I am pretty sure I tested it does what
it's supposed to do. So that is a bit surprising this seems to not work
anymore. Is this related to the BSS/stack memory address location
changes you made recently by any chance? Or did I manage to be very
lucky for a very long time for our boards?
"""
U-Boot SPL 2024.04-rc4-00026-g6ec096a7116-dirty (Mar 19 2024 - 10:50:03
+0100)
board_spl_was_booted_from: brom_bootdevice_id 5 maps to '/mmc@fe32'
Trying to boot from MMC2
load_simple_fit: Skip load 'atf-5': image size is 0!
NOTICE: BL31: v2.9(release):v2.9.0
NOTICE: BL31: Built : 17:47:58, Jun 21 2023
U-Boot 2024.04-rc4-00026-g6ec096a7116-dirty (Mar 19 2024 - 10:50:03 +0100)
[...]
=> fdt addr ${fdtcontroladdr}
Working FDT set to f1f13d10
=> fdt list /chosen
chosen {
u-boot,spl-boot-device = "/mmc@fe32";
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = "same-as-spl", "/spi@ff1d/flash@0",
"/mmc@fe33", "/mmc@fe32";
};
"""
for Puma when booting from SD card... I don't see
board_spl_was_booted_from being called a second time after BL31 is loaded?
mmm
Very interestingly, when booting from SPI-NOR flash:
"""
U-Boot SPL 2024.04-rc4-00026-g6ec096a7116-dirty (Mar 19 2024 - 10:50:03
+0100)
board_spl_was_booted_from: brom_bootdevice_id 3 maps to
'/spi@ff1d/flash@0'
Trying to boot from SPI
load_simple_fit: Skip load 'atf-5': image size is 0!
board_spl_was_booted_from: failed to resolve brom_bootdevice_id 0
NOTICE: BL31: v2.9(release):v2.9.0
NOTICE: BL31: Built : 17:47:58, Jun 21 2023
U-Boot 2024.04-rc4-00026-g6ec096a7116-dirty (Mar 19 2024 - 10:50:03 +0100)
[...]
=> fdt addr ${fdtcontroladdr}
Working FDT set to f1f13d10
=> fdt list /chosen
chosen {
u-boot,spl-boot-device = "/spi@ff1d/flash@0";
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = "same-as-spl", "/spi@ff1d/flash@0",
"/mmc@fe33", "/mmc@fe32";
};
"""
but the DT is properly written...
Ahah! This is because of one of my commits where I added support for
SPI-NOR flashes to spl_perform_fixups. So I think this worked for me
because the SPI-NOR flash is explicitly listed in spl-boot-order for
Puma, so when same-as-spl fails to resolve, the device is still found in
spl-boot-order DT property which means spl_perform_fixup will still be
able to write that spl-boot-device DT property. So basically, the issue
is related to SPI-NOR flash NOT being explicitly listed in
spl-boot-order or/and that the order isn't actually respected because
same-as-spl is basically skipped right now (but it works for Puma
because the next medium in the list is SPI, so skipping same-as-spl for
SPI, would result in checking SPI again :) ).
Can you please add:
Fixes: d57e16c7e712 ("rockchip: find U-boot proper boot device by
inverting the logic that sets it")
to the commit log regardless of the
Re: [PATCH v2 2/2] rockchip: spl-boot-order: show DT path for missing device
Hi Christopher, On 3/14/24 12:57, Christopher Obbard wrote: When debugging the SPL boot order, the node ID of a device which hasn't been found is printed but it can be quite hard to relate that to the specific devicetree node. To aid debugging, print the node path instead of the cryptic node ID. Original debug message: board_boot_order: could not map node @73c to a boot-device With this patch applied this becomes e.g: board_boot_order: could not map node /spi@ff1d/flash@0 to a boot-device Reviewed-by: Dragan Simic Signed-off-by: Christopher Obbard Reviewed-by: Quentin Schulz Thanks, Quentin
[PATCH v4 16/16] rockchip: boot_mode: fix rockchip_dnl_key_pressed requiring ADC support
From: Quentin Schulz
ADC support is implied by the Rockchip arch Kconfig but that means it
should be possible to disable ADC support and still be able to build.
However the weak implementation of rockchip_dnl_key_pressed() currently
blindly use functions from the ADC subsystem which do not exist when ADC
is not enabled, failing the build.
Therefore, let's encapsulate this logic with a check on the ADC symbol
being selected.
Cc: Quentin Schulz
Reviewed-by: Kever Yang
Signed-off-by: Quentin Schulz
---
arch/arm/mach-rockchip/boot_mode.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-rockchip/boot_mode.c
b/arch/arm/mach-rockchip/boot_mode.c
index eb8f65ae4e9..f9be396aa55 100644
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -40,6 +40,7 @@ void set_back_to_bootrom_dnl_flag(void)
__weak int rockchip_dnl_key_pressed(void)
{
+#if CONFIG_IS_ENABLED(ADC)
unsigned int val;
struct udevice *dev;
struct uclass *uc;
@@ -69,6 +70,9 @@ __weak int rockchip_dnl_key_pressed(void)
return true;
else
return false;
+#else
+ return false;
+#endif
}
void rockchip_dnl_mode_check(void)
--
2.44.0
[PATCH v4 15/16] button: add missing ADC dependency for BUTTON_ADC
From: Quentin Schulz The BUTTON_ADC symbol guards the compilation of button-adc driver whose name very well makes it explicit that it requires ADC support to be enabled. Fix build issue of button-adc driver when ADC support isn't enabled by making sure it cannot be built without ADC support. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/button/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig index 097b05f822e..3918b05ae03 100644 --- a/drivers/button/Kconfig +++ b/drivers/button/Kconfig @@ -12,6 +12,7 @@ config BUTTON config BUTTON_ADC bool "Button adc" depends on BUTTON + depends on ADC help Enable support for buttons which are connected to Analog to Digital Converter device. The ADC driver must use driver model. Buttons are -- 2.44.0
[PATCH v4 14/16] adc: add missing depends on ADC for controller drivers
From: Quentin Schulz The ADC controller drivers are obviously all depending on ADC symbol being selected. While they don't seem to fail to build without, they won't be useful without that symbol selected, so let's make sure the options aren't shown in menuconfig when ADC isn't selected. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/adc/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index a01d73846b7..c9cdbe6942d 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -13,6 +13,7 @@ config ADC config ADC_EXYNOS bool "Enable Exynos 54xx ADC driver" + depends on ADC help This enables basic driver for Exynos ADC compatible with Exynos54xx. It provides: @@ -22,6 +23,7 @@ config ADC_EXYNOS config ADC_SANDBOX bool "Enable Sandbox ADC test driver" + depends on ADC help This enables driver for Sandbox ADC device emulation. It provides: @@ -31,6 +33,7 @@ config ADC_SANDBOX config SARADC_MESON bool "Enable Amlogic Meson SARADC driver" + depends on ADC imply REGMAP help This enables driver for Amlogic Meson SARADC. @@ -41,6 +44,7 @@ config SARADC_MESON config SARADC_ROCKCHIP bool "Enable Rockchip SARADC driver" + depends on ADC help This enables driver for Rockchip SARADC. It provides: -- 2.44.0
[PATCH v4 13/16] rockchip: jaguar-rk3588: enable SARADC and derivatives
From: Quentin Schulz The SARADC is used on Jaguar for multiple things: - channel 0 is used (at runtime) as a BIOS button, - channel 2 is exposed on the Mezzanine connector for customer specific logic, - channel 5 and 6 are used for identification, Since the SARADC requires a vref-supply provided by the RK806 PMIC, its support and the support for its regulators are also enabled. The button, adc, pmic and regulator commands are also enabled for CLI use in U-Boot for debugging and scripting purposes. The RK806 PMIC on Jaguar being routed on the SPI bus, let's enable Rockchip SPI controller driver. Finally, the SARADC channel 1 on Jaguar is hardwired so will never change in the lifetime of a unit, for that reason, disable the Rockchip Download Mode check by setting ROCKCHIP_BOOT_MODE_REG symbol to 0. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- configs/jaguar-rk3588_defconfig | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index f55bfb1c82b..275d70ae008 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -15,6 +15,7 @@ CONFIG_ENV_SIZE=0x1f000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-jaguar" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x60 CONFIG_TARGET_JAGUAR_RK3588=y @@ -47,6 +48,7 @@ CONFIG_SPL_ATF=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ADC=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -59,6 +61,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_MII is not set # CONFIG_CMD_BLOCK_CACHE is not set # CONFIG_CMD_EFICONFIG is not set +CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EROFS=y CONFIG_CMD_SQUASHFS=y @@ -73,7 +76,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y -# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y CONFIG_SPL_CLK=y CONFIG_CLK_GPIO=y CONFIG_ROCKCHIP_GPIO=y @@ -101,10 +105,14 @@ CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y CONFIG_SPL_RAM=y CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -- 2.44.0
[PATCH v4 12/16] power: pmic: rk8xx: fix duplicate prompt
From: Quentin Schulz SPL_PMIC_RK8XX and PMIC_RK8XX both share the same prompt making it difficult to know at first glance in menuconfig what's for what, let's fix this by adding "in SPL" at the end of the prompt for the SPL symbol. Cc: Quentin Schulz Reviewed-by: Kever Yang Signed-off-by: Quentin Schulz --- drivers/power/pmic/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 9b61b18e11f..562c1a3b122 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -250,7 +250,7 @@ config PMIC_RK8XX This driver implements register read/write operations. config SPL_PMIC_RK8XX - bool "Enable support for Rockchip PMIC RK8XX" + bool "Enable support for Rockchip PMIC RK8XX in SPL" depends on SPL_DM_PMIC ---help--- The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, -- 2.44.0
