Re: [U-Boot] [PATCH] usb: dwc3: Handle case where setup_phy is not needed
Hi, > -Original Message- > From: Siva Durga Prasad Paladugu > Sent: Tuesday, May 28, 2019 3:36 PM > To: Michal Simek ; Lukasz Majewski > > Cc: u-boot@lists.denx.de; ma...@denx.de; jjhib...@ti.com; > s...@chromium.org; patrick.delau...@st.com > Subject: RE: [PATCH] usb: dwc3: Handle case where setup_phy is not needed > > Hi, > > > -Original Message- > > From: Michal Simek [mailto:michal.si...@xilinx.com] > > Sent: Monday, April 1, 2019 4:10 PM > > To: Siva Durga Prasad Paladugu ; Lukasz Majewski > > > > Cc: u-boot@lists.denx.de; ma...@denx.de; jjhib...@ti.com; > > s...@chromium.org; patrick.delau...@st.com > > Subject: Re: [PATCH] usb: dwc3: Handle case where setup_phy is not > > needed > > > > On 01. 04. 19 12:38, Siva Durga Prasad Paladugu wrote: > > > Hi Lukasz, > > > > > >> -Original Message----- > > >> From: Lukasz Majewski [mailto:lu...@denx.de] > > >> Sent: Monday, April 01, 2019 4:04 PM > > >> To: Siva Durga Prasad Paladugu > > >> Cc: u-boot@lists.denx.de; ma...@denx.de; jjhib...@ti.com; > > >> s...@chromium.org; patrick.delau...@st.com; Michal Simek > > >> > > >> Subject: Re: [PATCH] usb: dwc3: Handle case where setup_phy is not > > >> needed > > >> > > >> On Mon, 1 Apr 2019 10:23:42 + > > >> Siva Durga Prasad Paladugu wrote: > > >> > > >>> Hi Lukasz, > > >>> > > >>>> -Original Message- > > >>>> From: Lukasz Majewski [mailto:lu...@denx.de] > > >>>> Sent: Monday, April 01, 2019 1:03 PM > > >>>> To: Siva Durga Prasad Paladugu > > >>>> Cc: u-boot@lists.denx.de; ma...@denx.de; jjhib...@ti.com; > > >>>> s...@chromium.org; patrick.delau...@st.com; Michal Simek > > >>>> > > >>>> Subject: Re: [PATCH] usb: dwc3: Handle case where setup_phy is > > >>>> not needed > > >>>> > > >>>> Hi Siva Durga Prasad Paladugu, > > >>>> > > >>>>> If CONFIG_PHY is not enabled then the dwc3_setup_phy() returns > > >>>>> ENOTSUPP which can be still valid and intentional > > >>>> ^^^ - > > >>>> could you elaborate on this a bit more? > > >>>> > > >>>> What is the use case when -ENOTSUPP is valid and intentional ? > > >>> > > >>> In the cases where phy will be setup by First stage boot loader > > >>> itself and don't want to do it again at u-boot. > > >> > > >> I think that I saw some time ago similar patch for uart - on IMX > > >> IIRC (it was also setup by BootROM on SoC). > > >> > > >> Maybe we would need some kind of switch in Kconfig to indicate this > > >> use case? > > >> > > >> Another option would be to mark this in DTS as TI specific property? > > >> > > >> My point is that we shall not proceed with the flow when we do > > >> receive - ENOTSUPP > > > > > > TBH, I feel we should not call dwc3_setup_phy() if CONFIG_PHY is not > > > enabled. If we look at dwc3_setup_phy() definition, it is under > > CONFIG_PHY. > > > > +1 on this. > > Any update on this patch? This is how its already being handled in drivers/usb/host/xhci-dwc3.c at line 127 in routine xhci_dwc3_probe() (snippet below) ret = dwc3_setup_phy(dev, >usb_phys, >num_phys); if (ret && (ret != -ENOTSUPP)) return ret; We have two options either treat -ENOTSUPP as valid as above patch which I sent or don’t invoke dwc3_setup_phy() if CONFIG_PHY is not enabled. Thanks, Siva > > Thanks, > Siva > > > > > M ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] usb: dwc3: Handle case where setup_phy is not needed
Hi, > -Original Message- > From: Michal Simek [mailto:michal.si...@xilinx.com] > Sent: Monday, April 1, 2019 4:10 PM > To: Siva Durga Prasad Paladugu ; Lukasz Majewski > > Cc: u-boot@lists.denx.de; ma...@denx.de; jjhib...@ti.com; > s...@chromium.org; patrick.delau...@st.com > Subject: Re: [PATCH] usb: dwc3: Handle case where setup_phy is not needed > > On 01. 04. 19 12:38, Siva Durga Prasad Paladugu wrote: > > Hi Lukasz, > > > >> -Original Message- > >> From: Lukasz Majewski [mailto:lu...@denx.de] > >> Sent: Monday, April 01, 2019 4:04 PM > >> To: Siva Durga Prasad Paladugu > >> Cc: u-boot@lists.denx.de; ma...@denx.de; jjhib...@ti.com; > >> s...@chromium.org; patrick.delau...@st.com; Michal Simek > >> > >> Subject: Re: [PATCH] usb: dwc3: Handle case where setup_phy is not > >> needed > >> > >> On Mon, 1 Apr 2019 10:23:42 + > >> Siva Durga Prasad Paladugu wrote: > >> > >>> Hi Lukasz, > >>> > >>>> -Original Message- > >>>> From: Lukasz Majewski [mailto:lu...@denx.de] > >>>> Sent: Monday, April 01, 2019 1:03 PM > >>>> To: Siva Durga Prasad Paladugu > >>>> Cc: u-boot@lists.denx.de; ma...@denx.de; jjhib...@ti.com; > >>>> s...@chromium.org; patrick.delau...@st.com; Michal Simek > >>>> > >>>> Subject: Re: [PATCH] usb: dwc3: Handle case where setup_phy is not > >>>> needed > >>>> > >>>> Hi Siva Durga Prasad Paladugu, > >>>> > >>>>> If CONFIG_PHY is not enabled then the dwc3_setup_phy() returns > >>>>> ENOTSUPP which can be still valid and intentional > >>>> ^^^ - could > >>>> you elaborate on this a bit more? > >>>> > >>>> What is the use case when -ENOTSUPP is valid and intentional ? > >>> > >>> In the cases where phy will be setup by First stage boot loader > >>> itself and don't want to do it again at u-boot. > >> > >> I think that I saw some time ago similar patch for uart - on IMX IIRC > >> (it was also setup by BootROM on SoC). > >> > >> Maybe we would need some kind of switch in Kconfig to indicate this > >> use case? > >> > >> Another option would be to mark this in DTS as TI specific property? > >> > >> My point is that we shall not proceed with the flow when we do > >> receive - ENOTSUPP > > > > TBH, I feel we should not call dwc3_setup_phy() if CONFIG_PHY is not > > enabled. If we look at dwc3_setup_phy() definition, it is under > CONFIG_PHY. > > +1 on this. Any update on this patch? Thanks, Siva > > M ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/18] Improvement for the DWC3 USB generic driver and fixes for the K2 platforms
Hi Lukasz, > -Original Message- > From: Lukasz Majewski [mailto:lu...@denx.de] > Sent: Tuesday, May 21, 2019 5:52 PM > To: Siva Durga Prasad Paladugu > Cc: Jean-Jacques Hiblot ; ma...@denx.de; Marcel Ziswiler > ; u-boot@lists.denx.de; Miquel Raynal > ; Stefan Roese ; Tom Rini > ; Ryder Lee ; Heinrich > Schuchardt ; Michal Simek ; > Krzysztof Kozlowski ; Maxime Ripard > ; Sven Schwermer ; > Ramon Fried ; Eugeniu Rosca > ; Vitaly Andrianov ; Joe > Hershberger ; Tom Warren > Subject: Re: [U-Boot] [PATCH v2 00/18] Improvement for the DWC3 USB generic > driver and fixes for the K2 platforms > > On Tue, 21 May 2019 11:36:57 + > Siva Durga Prasad Paladugu wrote: > > > Hi, > > > > Tested the series with one out of tree > > patch(https://marc.info/?l=u-boot=155409909828219 ) on Xilinx ZynqMP > > and it looks fine. We may need to finalize on > > https://marc.info/?l=u-boot=155409909828219 as well. > > Could you also provide proper Tested-by tag to this patch set? In that way it > would automatically be added to patchwork, and your tag would be applied to > the patches. > > Thanks in advance. I cant provide Tested-by as I tested this with one out of tree patch(https://marc.info/?l=u-boot=155409909828219). If it goes in, then I can provide Tested-by. Thanks, Siva > > > > > U-Boot 2019.04-rc4-00065-g5063fa3-dirty (May 21 2019 - 16:58:34 +0530) > > > > Model: ZynqMP ZCU102 Rev1.0 > > Board: Xilinx ZynqMP > > DRAM: 4 GiB > > EL Level: EL2 > > Chip ID:zu9eg > > MMC: mmc@ff17: 0 > > Loading Environment from FAT... *** Warning - bad CRC, using default > > environment > > > > In:serial@ff00 > > Out: serial@ff00 > > Err: serial@ff00 > > Bootmode: JTAG_MODE > > Reset reason: EXTERNAL > > Net: ZYNQ GEM: ff0e, phyaddr c, interface rgmii-id > > > > Warning: ethernet@ff0e (eth0) using random MAC address - > > 32:98:cb:f1:92:33 eth0: ethernet@ff0e Hit any key to stop > > autoboot: 0 > > ZynqMP> usb start > > starting USB... > > USB0: Register 2000440 NbrPorts 2 > > Starting the controller > > USB XHCI 1.00 > > scanning bus 0 for devices... 2 USB Device(s) found > >scanning usb for storage devices... 1 Storage Device(s) found > > ZynqMP> ls usb 0 > > 5242880 dummy.bin > > 133849600 Image > > > > 2 file(s), 0 dir(s) > > > > ZynqMP> load usb 0 10 Image > > 133849600 bytes read in 1056 ms (120.9 MiB/s) > > ZynqMP> > > > > Thanks, > > Siva > > > > -Original Message- > > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of > > Jean-Jacques Hiblot Sent: Monday, May 13, 2019 8:00 PM > > To: lu...@denx.de; ma...@denx.de > > Cc: Marcel Ziswiler ; > > u-boot@lists.denx.de; Miquel Raynal ; > > Stefan Roese ; Tom Rini ; Ryder Lee > > ; Heinrich Schuchardt ; > > Michal Simek ; Krzysztof Kozlowski > > ; Maxime Ripard ; Sven > > Schwermer ; Ramon Fried > > ; Eugeniu Rosca ; > > Vitaly Andrianov ; Joe Hershberger > > ; Tom Warren Subject: > > [U-Boot] [PATCH v2 00/18] Improvement for the DWC3 USB generic driver > > and fixes for the K2 platforms > > > > The K2 platforms have shown boot issues after switching to the DWC3 > > generic driver. Those are due to the fact that the USB domains are not > > turned off before booting linux and the phy were not properly > > initialized. Fixing it by improving the DWC3-generic driver and > > handling the USB power domain in the PHY driver. At the same time this > > series introduce a new uclass (UCLASS_NOP) to replace usage of > > UCLASS_MISC in the USB wrapper because the MISC class now > > automatically binds all the child devices. > > > > Improvements to the DWC3 generic driver are: > > - Fix it by switching to UCLASS_NOP > > - core: read quirks properties from DT and apply the fixes. > > - add a new host driver that uses the DWC3 core (more generic than > > xhci-dwc3). This should enable most platforms to drop their own > > version of the xhci-driver to use the generic one instead. > > > > This series also removes the now unused xhci-zynqmp driver and tries > > to better manage the Kconfig options related to DWC3 gadget/host mode > > selection. > > > > This has been tested with K2 and DRA7 platforms (host and device > > modes). Travis build: > > https://travis-ci.org/jjhiblot/u-boot/builds/515282720 > > > > Changes in v2: > > - Add a test for the NOP ucla
Re: [U-Boot] [PATCH v2 00/18] Improvement for the DWC3 USB generic driver and fixes for the K2 platforms
Hi, -Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Tuesday, May 21, 2019 6:14 PM To: Siva Durga Prasad Paladugu ; Jean-Jacques Hiblot ; lu...@denx.de Cc: Marcel Ziswiler ; u-boot@lists.denx.de; Miquel Raynal ; Stefan Roese ; Tom Rini ; Ryder Lee ; Heinrich Schuchardt ; Michal Simek ; Krzysztof Kozlowski ; Maxime Ripard ; Sven Schwermer ; Ramon Fried ; Eugeniu Rosca ; Vitaly Andrianov ; Joe Hershberger ; Tom Warren Subject: Re: [U-Boot] [PATCH v2 00/18] Improvement for the DWC3 USB generic driver and fixes for the K2 platforms On 5/21/19 1:36 PM, Siva Durga Prasad Paladugu wrote: > Hi, Hi, > Tested the series with one out of tree > patch(https://marc.info/?l=u-boot=155409909828219 ) on Xilinx ZynqMP and it > looks fine. > We may need to finalize on https://marc.info/?l=u-boot=155409909828219 as > well. > > U-Boot 2019.04-rc4-00065-g5063fa3-dirty (May 21 2019 - 16:58:34 +0530) Does it still work on current master (2019.07-rc) ? Testing a patch on top of rc version of previous release is not really helpful. [...] Its same with latest too. U-Boot 2019.07-rc2-00182-g29792e4-dirty (May 22 2019 - 11:21:25 +0530) Model: ZynqMP ZCU102 Rev1.0 Board: Xilinx ZynqMP DRAM: 4 GiB EL Level: EL2 Chip ID:zu9eg MMC: mmc@ff17: 0 Loading Environment from FAT... *** Warning - bad CRC, using default environment In:serial@ff00 Out: serial@ff00 Err: serial@ff00 Bootmode: JTAG_MODE Reset reason: EXTERNAL Net: ZYNQ GEM: ff0e, phyaddr c, interface rgmii-id Warning: ethernet@ff0e (eth0) using random MAC address - ca:f4:c2:4a:b8:df eth0: ethernet@ff0e Hit any key to stop autoboot: 0 ZynqMP> usb start starting USB... Bus dwc3@fe20: Register 2000440 NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus dwc3@fe20 for devices... 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found ZynqMP> ls ubs 0 ZynqMP> ls usb 0 5242880 dummy.bin 133849600 Image 2 file(s), 0 dir(s) ZynqMP> load usb 0 10 dummy.bin 5242880 bytes read in 55 ms (90.9 MiB/s) ZynqMP> Thanks, Siva -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/18] Improvement for the DWC3 USB generic driver and fixes for the K2 platforms
Hi, Tested the series with one out of tree patch(https://marc.info/?l=u-boot=155409909828219 ) on Xilinx ZynqMP and it looks fine. We may need to finalize on https://marc.info/?l=u-boot=155409909828219 as well. U-Boot 2019.04-rc4-00065-g5063fa3-dirty (May 21 2019 - 16:58:34 +0530) Model: ZynqMP ZCU102 Rev1.0 Board: Xilinx ZynqMP DRAM: 4 GiB EL Level: EL2 Chip ID:zu9eg MMC: mmc@ff17: 0 Loading Environment from FAT... *** Warning - bad CRC, using default environment In:serial@ff00 Out: serial@ff00 Err: serial@ff00 Bootmode: JTAG_MODE Reset reason: EXTERNAL Net: ZYNQ GEM: ff0e, phyaddr c, interface rgmii-id Warning: ethernet@ff0e (eth0) using random MAC address - 32:98:cb:f1:92:33 eth0: ethernet@ff0e Hit any key to stop autoboot: 0 ZynqMP> usb start starting USB... USB0: Register 2000440 NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found ZynqMP> ls usb 0 5242880 dummy.bin 133849600 Image 2 file(s), 0 dir(s) ZynqMP> load usb 0 10 Image 133849600 bytes read in 1056 ms (120.9 MiB/s) ZynqMP> Thanks, Siva -Original Message- From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Jean-Jacques Hiblot Sent: Monday, May 13, 2019 8:00 PM To: lu...@denx.de; ma...@denx.de Cc: Marcel Ziswiler ; u-boot@lists.denx.de; Miquel Raynal ; Stefan Roese ; Tom Rini ; Ryder Lee ; Heinrich Schuchardt ; Michal Simek ; Krzysztof Kozlowski ; Maxime Ripard ; Sven Schwermer ; Ramon Fried ; Eugeniu Rosca ; Vitaly Andrianov ; Joe Hershberger ; Tom Warren Subject: [U-Boot] [PATCH v2 00/18] Improvement for the DWC3 USB generic driver and fixes for the K2 platforms The K2 platforms have shown boot issues after switching to the DWC3 generic driver. Those are due to the fact that the USB domains are not turned off before booting linux and the phy were not properly initialized. Fixing it by improving the DWC3-generic driver and handling the USB power domain in the PHY driver. At the same time this series introduce a new uclass (UCLASS_NOP) to replace usage of UCLASS_MISC in the USB wrapper because the MISC class now automatically binds all the child devices. Improvements to the DWC3 generic driver are: - Fix it by switching to UCLASS_NOP - core: read quirks properties from DT and apply the fixes. - add a new host driver that uses the DWC3 core (more generic than xhci-dwc3). This should enable most platforms to drop their own version of the xhci-driver to use the generic one instead. This series also removes the now unused xhci-zynqmp driver and tries to better manage the Kconfig options related to DWC3 gadget/host mode selection. This has been tested with K2 and DRA7 platforms (host and device modes). Travis build: https://travis-ci.org/jjhiblot/u-boot/builds/515282720 Changes in v2: - Add a test for the NOP uclass - Update commit logs - Select USB_GADGET_DUALSPEED if USB_DWC3_GADGET is selected Jean-Jacques Hiblot (18): usb: dwc3-generic: remove dm_scan_fdt_dev() from the remove() callback usb: host: remove the xhci-zynqmp driver dm: Add a No-op uclass usb: dwc3: Use UCLASS_NOP instead of UCLASS_MISC for the DWC3 generic glue usb: dwc3: switch to peripheral mode when exiting usb: xhci: move xhci.h to include usb usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit usb: dwc3-generic: use platdata usb: dwc3-generic: factorize code usb: dwc3-generic: add a new host driver that uses the dwc3 core usb: dwc3-generic: if no max speed is specified in DT, assume super speed usb: dwc3: Add dwc3_of_parse() to get quirks information from DT usb: dwc3: Kconfig: get rid of obsolete mode selection ARM: keystone: increase PSC timeout ARM: keystone: Do not enable the USB power domains at the board level phy: keystone-usb: handle the transition of the USB power domain configs: k2g_evm_defconfig: disable XHCI_DWC3 and enable KEYSTONE_USB_PHY ARM: DTS: keystone: complete the description of the USB PHY devices MAINTAINERS | 1 + arch/arm/dts/keystone-k2e-evm-u-boot.dtsi | 32 arch/arm/dts/keystone-k2g-evm-u-boot.dtsi | 28 arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi| 14 ++ arch/arm/dts/keystone-k2l-evm-u-boot.dtsi | 18 +++ .../arm/mach-keystone/include/mach/psc_defs.h | 2 +- arch/sandbox/dts/test.dts | 12 ++ board/ti/ks2_evm/board.c | 13 -- configs/avnet_ultra96_rev1_defconfig | 1 - configs/evb-rk3328_defconfig | 1 + configs/k2g_evm_defconfig | 3 +- .../xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 -
Re: [U-Boot] [PATCH] usb: dwc3: Handle case where setup_phy is not needed
Hi Lukasz, > -Original Message- > From: Lukasz Majewski [mailto:lu...@denx.de] > Sent: Monday, April 01, 2019 4:04 PM > To: Siva Durga Prasad Paladugu > Cc: u-boot@lists.denx.de; ma...@denx.de; jjhib...@ti.com; > s...@chromium.org; patrick.delau...@st.com; Michal Simek > > Subject: Re: [PATCH] usb: dwc3: Handle case where setup_phy is not > needed > > On Mon, 1 Apr 2019 10:23:42 + > Siva Durga Prasad Paladugu wrote: > > > Hi Lukasz, > > > > > -Original Message- > > > From: Lukasz Majewski [mailto:lu...@denx.de] > > > Sent: Monday, April 01, 2019 1:03 PM > > > To: Siva Durga Prasad Paladugu > > > Cc: u-boot@lists.denx.de; ma...@denx.de; jjhib...@ti.com; > > > s...@chromium.org; patrick.delau...@st.com; Michal Simek > > > > > > Subject: Re: [PATCH] usb: dwc3: Handle case where setup_phy is not > > > needed > > > > > > Hi Siva Durga Prasad Paladugu, > > > > > > > If CONFIG_PHY is not enabled then the dwc3_setup_phy() returns > > > > ENOTSUPP which can be still valid and intentional > > > ^^^ - could > > > you elaborate on this a bit more? > > > > > > What is the use case when -ENOTSUPP is valid and intentional ? > > > > In the cases where phy will be setup by First stage boot loader itself > > and don't want to do it again at u-boot. > > I think that I saw some time ago similar patch for uart - on IMX IIRC (it was > also setup by BootROM on SoC). > > Maybe we would need some kind of switch in Kconfig to indicate this use > case? > > Another option would be to mark this in DTS as TI specific property? > > My point is that we shall not proceed with the flow when we do receive - > ENOTSUPP TBH, I feel we should not call dwc3_setup_phy() if CONFIG_PHY is not enabled. If we look at dwc3_setup_phy() definition, it is under CONFIG_PHY. Thanks, Siva > > > > > Thanks, > > Siva > > > > > > > > > so modify error check to handle this -ENOTSUPP. > > > > > > > > Signed-off-by: Siva Durga Prasad Paladugu > > > > --- > > > > drivers/usb/dwc3/dwc3-generic.c | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/usb/dwc3/dwc3-generic.c > > > > b/drivers/usb/dwc3/dwc3-generic.c index 3e6c494..a261d8d 100644 > > > > --- a/drivers/usb/dwc3/dwc3-generic.c > > > > +++ b/drivers/usb/dwc3/dwc3-generic.c > > > > @@ -47,7 +47,7 @@ static int dwc3_generic_peripheral_probe(struct > > > > udevice *dev) struct dwc3 *dwc3 = >dwc3; > > > > > > > > rc = dwc3_setup_phy(dev, >phys, >num_phys); > > > > - if (rc) > > > > + if (rc && rc != -ENOTSUPP) > > > > return rc; > > > > > > > > dwc3->regs = map_physmem(priv->base, DWC3_OTG_REGS_END, > > > > MAP_NOCACHE); > > > > > > > > > > > > > > > Best regards, > > > > > > Lukasz Majewski > > > > > > -- > > > > > > DENX Software Engineering GmbH, Managing Director: Wolfgang > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, > > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 > Email: > > > lu...@denx.de > > > > > Best regards, > > Lukasz Majewski > > -- > > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: > lu...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] usb: dwc3: Handle case where setup_phy is not needed
Hi Lukasz, > -Original Message- > From: Lukasz Majewski [mailto:lu...@denx.de] > Sent: Monday, April 01, 2019 1:03 PM > To: Siva Durga Prasad Paladugu > Cc: u-boot@lists.denx.de; ma...@denx.de; jjhib...@ti.com; > s...@chromium.org; patrick.delau...@st.com; Michal Simek > > Subject: Re: [PATCH] usb: dwc3: Handle case where setup_phy is not > needed > > Hi Siva Durga Prasad Paladugu, > > > If CONFIG_PHY is not enabled then the dwc3_setup_phy() returns > > ENOTSUPP which can be still valid and intentional > ^^^ - could you > elaborate on this a bit more? > > What is the use case when -ENOTSUPP is valid and intentional ? In the cases where phy will be setup by First stage boot loader itself and don't want to do it again at u-boot. Thanks, Siva > > > so modify error check to handle this -ENOTSUPP. > > > > Signed-off-by: Siva Durga Prasad Paladugu > > --- drivers/usb/dwc3/dwc3-generic.c > > | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/usb/dwc3/dwc3-generic.c > > b/drivers/usb/dwc3/dwc3-generic.c index 3e6c494..a261d8d 100644 > > --- a/drivers/usb/dwc3/dwc3-generic.c > > +++ b/drivers/usb/dwc3/dwc3-generic.c > > @@ -47,7 +47,7 @@ static int dwc3_generic_peripheral_probe(struct > > udevice *dev) struct dwc3 *dwc3 = >dwc3; > > > > rc = dwc3_setup_phy(dev, >phys, >num_phys); > > - if (rc) > > + if (rc && rc != -ENOTSUPP) > > return rc; > > > > dwc3->regs = map_physmem(priv->base, DWC3_OTG_REGS_END, > > MAP_NOCACHE); > > > > > Best regards, > > Lukasz Majewski > > -- > > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: > lu...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] usb: dwc3: Handle case where setup_phy is not needed
If CONFIG_PHY is not enabled then the dwc3_setup_phy() returns ENOTSUPP which can be still valid and intentional so modify error check to handle this -ENOTSUPP. Signed-off-by: Siva Durga Prasad Paladugu --- drivers/usb/dwc3/dwc3-generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 3e6c494..a261d8d 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -47,7 +47,7 @@ static int dwc3_generic_peripheral_probe(struct udevice *dev) struct dwc3 *dwc3 = >dwc3; rc = dwc3_setup_phy(dev, >phys, >num_phys); - if (rc) + if (rc && rc != -ENOTSUPP) return rc; dwc3->regs = map_physmem(priv->base, DWC3_OTG_REGS_END, MAP_NOCACHE); -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] usb: composite: Fix max packet size for USB3.0
For USB3.0, the max packetsize for GET_DESCRIPTOR should be
sent as exponent value for 2. This means for 512, max packet
size should be filled with 9(2^9=512). Also, fill the USB
version field with 3.0 if speed is negotiated to Superspeed.
This fixes the issue of DFU gadget download failure with
superspeed. Without this patch, the max packet size is
overflowed to zero as the bMaxPacketsize is of u8 and hence
host is not able to detect this device.
Signed-off-by: Siva Durga Prasad Paladugu
Reviewed-by: Bin Meng
---
Changes from RFC:
- Fixed typo in description as per comment.
---
drivers/usb/gadget/composite.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 5106cc5..c7e7623 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -735,8 +735,21 @@ composite_setup(struct usb_gadget *gadget, const struct
usb_ctrlrequest *ctrl)
case USB_DT_DEVICE:
cdev->desc.bNumConfigurations =
count_configs(cdev, USB_DT_DEVICE);
- cdev->desc.bMaxPacketSize0 =
- cdev->gadget->ep0->maxpacket;
+
+ /*
+* If the speed is Super speed, then the supported
+* max packet size is 512 and it should be sent as
+* exponent of 2. So, 9(2^9=512) should be filled in
+* bMaxPacketSize0. Also fill USB version as 3.0
+* if speed is Super speed.
+*/
+ if (cdev->gadget->speed == USB_SPEED_SUPER) {
+ cdev->desc.bMaxPacketSize0 = 9;
+ cdev->desc.bcdUSB = cpu_to_le16(0x0300);
+ } else {
+ cdev->desc.bMaxPacketSize0 =
+ cdev->gadget->ep0->maxpacket;
+ }
value = min(w_length, (u16) sizeof cdev->desc);
memcpy(req->buf, >desc, value);
break;
--
2.7.4
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[U-Boot] [RFC PATCH] usb: composite: Fix max packet size for USB3.0
For USB3.0 the max packetsize for GET_DESCRIPTOR should be
sent as exponent value for 2. This means for 512, max packet
size should be filled with 9(2^9=512). Also, fill the USB
version field with 3.0 if speed is negotiated to Superspeed.
This fixes the issue of DFU gadget download failure with
superspeed. With out this patch, the max packet size is
overflowed to zero as the bMaxPacketsize is of u8 and hence
host is not able to detect this device.
Signed-off-by: Siva Durga Prasad Paladugu
---
drivers/usb/gadget/composite.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 5106cc5..c7e7623 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -735,8 +735,21 @@ composite_setup(struct usb_gadget *gadget, const struct
usb_ctrlrequest *ctrl)
case USB_DT_DEVICE:
cdev->desc.bNumConfigurations =
count_configs(cdev, USB_DT_DEVICE);
- cdev->desc.bMaxPacketSize0 =
- cdev->gadget->ep0->maxpacket;
+
+ /*
+* If the speed is Super speed, then the supported
+* max packet size is 512 and it should be sent as
+* exponent of 2. So, 9(2^9=512) should be filled in
+* bMaxPacketSize0. Also fill USB version as 3.0
+* if speed is Super speed.
+*/
+ if (cdev->gadget->speed == USB_SPEED_SUPER) {
+ cdev->desc.bMaxPacketSize0 = 9;
+ cdev->desc.bcdUSB = cpu_to_le16(0x0300);
+ } else {
+ cdev->desc.bMaxPacketSize0 =
+ cdev->gadget->ep0->maxpacket;
+ }
value = min(w_length, (u16) sizeof cdev->desc);
memcpy(req->buf, >desc, value);
break;
--
2.7.4
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[U-Boot] [RFC PATCH] mmc: sdhci: zynqmp: Added support to read tap delay values from DT
From: Vipul Kumar
This patch added support to read ITAP and OTAP delay values from
the device tree. If the DT does not contain tap delay values, the
predefined values will be used for the same.
Signed-off-by: Vipul Kumar
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
- These bindings were sent to mainline but not accepted yet.
---
board/xilinx/zynqmp/tap_delays.c | 195 ++-
drivers/mmc/zynq_sdhci.c | 217 ++-
include/zynqmp_tap_delay.h | 5 +-
3 files changed, 249 insertions(+), 168 deletions(-)
diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c
index c3ae357..3788d67 100644
--- a/board/xilinx/zynqmp/tap_delays.c
+++ b/board/xilinx/zynqmp/tap_delays.c
@@ -24,43 +24,12 @@
#define SD1_ITAPDLYENA_MASK0x0100
#define SD1_ITAPDLYENA 0x0100
#define SD0_ITAPDLYSEL_MASK0x00FF
-#define SD0_ITAPDLYSEL_HSD 0x0015
-#define SD0_ITAPDLYSEL_SD_DDR500x003D
-#define SD0_ITAPDLYSEL_MMC_DDR50 0x0012
#define SD1_ITAPDLYSEL_MASK0x00FF
-#define SD1_ITAPDLYSEL_HSD 0x0015
-#define SD1_ITAPDLYSEL_SD_DDR500x003D
-#define SD1_ITAPDLYSEL_MMC_DDR50 0x0012
#define SD0_OTAPDLYSEL_MASK0x003F
-#define SD0_OTAPDLYSEL_MMC_HSD 0x0006
-#define SD0_OTAPDLYSEL_SD_HSD 0x0005
-#define SD0_OTAPDLYSEL_SDR50 0x0003
-#define SD0_OTAPDLYSEL_SDR104_B0 0x0003
-#define SD0_OTAPDLYSEL_SDR104_B2 0x0002
-#define SD0_OTAPDLYSEL_SD_DDR500x0004
-#define SD0_OTAPDLYSEL_MMC_DDR50 0x0006
#define SD1_OTAPDLYSEL_MASK0x003F
-#define SD1_OTAPDLYSEL_MMC_HSD 0x0006
-#define SD1_OTAPDLYSEL_SD_HSD 0x0005
-#define SD1_OTAPDLYSEL_SDR50 0x0003
-#define SD1_OTAPDLYSEL_SDR104_B0 0x0003
-#define SD1_OTAPDLYSEL_SDR104_B2 0x0002
-#define SD1_OTAPDLYSEL_SD_DDR500x0004
-#define SD1_OTAPDLYSEL_MMC_DDR50 0x0006
-
-#define MMC_BANK2 0x2
-
-#define MMC_TIMING_UHS_SDR25 1
-#define MMC_TIMING_UHS_SDR50 2
-#define MMC_TIMING_UHS_SDR104 3
-#define MMC_TIMING_UHS_DDR50 4
-#define MMC_TIMING_MMC_HS200 5
-#define MMC_TIMING_SD_HS 6
-#define MMC_TIMING_MMC_DDR52 7
-#define MMC_TIMING_MMC_HS 8
void zynqmp_dll_reset(u8 deviceid)
{
@@ -81,149 +50,49 @@ void zynqmp_dll_reset(u8 deviceid)
zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
}
-static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank)
-{
- if (deviceid == 0) {
- /* Program OTAP */
- if (bank == MMC_BANK2)
- zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
- SD0_OTAPDLYSEL_SDR104_B2);
- else
- zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
- SD0_OTAPDLYSEL_SDR104_B0);
- } else {
- /* Program OTAP */
- if (bank == MMC_BANK2)
- zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
- SD1_OTAPDLYSEL_SDR104_B2);
- else
- zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
- SD1_OTAPDLYSEL_SDR104_B0);
- }
-}
-
-static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank)
-{
- if (deviceid == 0) {
- /* Program ITAP */
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
- SD0_ITAPCHGWIN);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
- SD0_ITAPDLYENA);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
- SD0_ITAPDLYSEL_HSD);
- zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
- /* Program OTAP */
- if (timing == MMC_TIMING_MMC_HS)
- zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
- SD0_OTAPDLYSEL_MMC_HSD);
- else
- zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
- SD0_OTAPDLYSEL_SD_HSD);
- } else {
- /* Program ITAP */
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
- SD1_ITAPCHGWIN);
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
- SD1_ITAPDLYENA);
- zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK
[U-Boot] [PATCH 2/2] net: phy: Add gmiitorgmii converter support
This patch adds support for gmiitorgmii converter.
This converter sits between the MAC and the external phy
MAC <==> GMII2RGMII <==> RGMII_PHY.
The ethernet driver probes this bridge and this bridge driver
probes real phy driver and invokes the real phy functionalities
as requested. This bridge just needs to be configured based on
real phy negotiated speed and duplex.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
drivers/net/phy/Kconfig | 7 +++
drivers/net/phy/Makefile| 1 +
drivers/net/phy/phy.c | 41 ++
drivers/net/phy/xilinx_gmii2rgmii.c | 103
include/phy.h | 6 +++
5 files changed, 158 insertions(+)
create mode 100644 drivers/net/phy/xilinx_gmii2rgmii.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 3dc0822..a68e167 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -217,6 +217,13 @@ config PHY_VITESSE
config PHY_XILINX
bool "Xilinx Ethernet PHYs support"
+config PHY_XILINX_GMII2RGMII
+ bool "Xilinx GMII to RGMII Ethernet PHYs support"
+ help
+ This adds support for Xilinx GMII to RGMII IP core. This IP acts
+ as bridge between MAC connected over GMII and external phy that
+ is connected over RGMII interface.
+
config PHY_FIXED
bool "Fixed-Link PHY"
depends on DM_ETH
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 555da83..76b6197 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
obj-$(CONFIG_PHY_TI) += ti.o
obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o
+obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
obj-$(CONFIG_PHY_VITESSE) += vitesse.o
obj-$(CONFIG_PHY_MSCC) += mscc.o
obj-$(CONFIG_PHY_FIXED) += fixed.o
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 3cb2785..d02c4d8 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -528,6 +528,9 @@ int phy_init(void)
#ifdef CONFIG_PHY_FIXED
phy_fixed_init();
#endif
+#ifdef CONFIG_PHY_XILINX_GMII2RGMII
+ phy_xilinx_gmii2rgmii_init();
+#endif
return 0;
}
@@ -875,6 +878,41 @@ void phy_connect_dev(struct phy_device *phydev, struct
eth_device *dev)
debug("%s connected to %s\n", dev->name, phydev->drv->name);
}
+#ifdef CONFIG_PHY_XILINX_GMII2RGMII
+#ifdef CONFIG_DM_ETH
+static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
+struct udevice *dev,
+phy_interface_t interface)
+#else
+static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
+struct eth_device *dev,
+phy_interface_t interface)
+#endif
+{
+ struct phy_device *phydev = NULL;
+ int sn = dev_of_offset(dev);
+ int off;
+
+ while (sn > 0) {
+ off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
+ "xlnx,gmii-to-rgmii-1.0");
+ if (off > 0) {
+ phydev = phy_device_create(bus,
+ off, PHY_GMII2RGMII_ID,
+ interface);
+ break;
+ }
+ if (off == -FDT_ERR_NOTFOUND)
+ sn = fdt_first_subnode(gd->fdt_blob, sn);
+ else
+ printf("%s: Error finding compat string:%d\n",
+ __func__, off);
+ }
+
+ return phydev;
+}
+#endif
+
#ifdef CONFIG_PHY_FIXED
#ifdef CONFIG_DM_ETH
static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
@@ -920,6 +958,9 @@ struct phy_device *phy_connect(struct mii_dev *bus, int
addr,
#ifdef CONFIG_PHY_FIXED
phydev = phy_connect_fixed(bus, dev, interface);
#endif
+#ifdef CONFIG_PHY_XILINX_GMII2RGMII
+ phydev = phy_connect_gmii2rgmii(bus, dev, interface);
+#endif
if (!phydev)
phydev = phy_find_by_mask(bus, 1 << addr, interface);
diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c
b/drivers/net/phy/xilinx_gmii2rgmii.c
new file mode 100644
index 000..aa4ce86
--- /dev/null
+++ b/drivers/net/phy/xilinx_gmii2rgmii.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx GMII2RGMII phy driver
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ZYNQ_GMII2RGMII_REG0x10
+#define ZYNQ_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100)
+
+static int xilinxgmiitorgmii_config(struct phy_device
[U-Boot] [PATCH 1/2] net: phy: Move fixed link code to separate routine
This patch moves fixed-link functionality code to a separate
routine inorder to make it more modular and cleaner.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
drivers/net/phy/phy.c | 34 +++---
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index e837eb7..3cb2785 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -875,18 +875,18 @@ void phy_connect_dev(struct phy_device *phydev, struct
eth_device *dev)
debug("%s connected to %s\n", dev->name, phydev->drv->name);
}
+#ifdef CONFIG_PHY_FIXED
#ifdef CONFIG_DM_ETH
-struct phy_device *phy_connect(struct mii_dev *bus, int addr,
- struct udevice *dev,
- phy_interface_t interface)
+static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
+ struct udevice *dev,
+ phy_interface_t interface)
#else
-struct phy_device *phy_connect(struct mii_dev *bus, int addr,
- struct eth_device *dev,
- phy_interface_t interface)
+static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
+ struct eth_device *dev,
+ phy_interface_t interface)
#endif
{
struct phy_device *phydev = NULL;
-#ifdef CONFIG_PHY_FIXED
int sn;
const char *name;
@@ -900,7 +900,27 @@ struct phy_device *phy_connect(struct mii_dev *bus, int
addr,
}
sn = fdt_next_subnode(gd->fdt_blob, sn);
}
+
+ return phydev;
+}
#endif
+
+#ifdef CONFIG_DM_ETH
+struct phy_device *phy_connect(struct mii_dev *bus, int addr,
+ struct udevice *dev,
+ phy_interface_t interface)
+#else
+struct phy_device *phy_connect(struct mii_dev *bus, int addr,
+ struct eth_device *dev,
+ phy_interface_t interface)
+#endif
+{
+ struct phy_device *phydev = NULL;
+
+#ifdef CONFIG_PHY_FIXED
+ phydev = phy_connect_fixed(bus, dev, interface);
+#endif
+
if (!phydev)
phydev = phy_find_by_mask(bus, 1 << addr, interface);
--
2.7.4
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[U-Boot] [PATCH 2/2] net: zynq_gem: Add check for 64-bit dma support by hardware
This patch throws an error if 64-bit support is expected
but DMA hardware is not capable of 64-bit support. It also
prints a debug message if DMA is capable of 64-bit but not
using it.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
drivers/net/zynq_gem.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index ee528db..9bd79b1 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -102,6 +102,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
+#define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
+
/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG 1
@@ -150,7 +152,9 @@ struct zynq_gem_regs {
u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
u32 reserved9[20];
u32 pcscntrl;
- u32 reserved7[143];
+ u32 rserved12[36];
+ u32 dcfg6; /* 0x294 Design config reg6 */
+ u32 reserved7[106];
u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
u32 reserved8[15];
u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
@@ -198,6 +202,7 @@ struct zynq_gem_priv {
struct clk clk;
u32 max_speed;
bool int_pcs;
+ bool dma_64bit;
};
static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@@ -378,6 +383,23 @@ static int zynq_gem_init(struct udevice *dev)
struct emac_bd *dummy_tx_bd = >tx_bd[TX_FREE_DESC];
struct emac_bd *dummy_rx_bd = >tx_bd[TX_FREE_DESC + 2];
+ if (readl(>dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
+ priv->dma_64bit = true;
+ else
+ priv->dma_64bit = false;
+
+#if defined(CONFIG_PHYS_64BIT)
+ if (!priv->dma_64bit) {
+ printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
+ __func__);
+ return -EINVAL;
+ }
+#else
+ if (priv->dma_64bit)
+ debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
+ __func__);
+#endif
+
if (!priv->init) {
/* Disable all interrupts */
writel(0x, >idr);
--
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[U-Boot] [PATCH 1/2] net: zynq_gem: Added 64-bit addressing support
From: Vipul Kumar
This patch adds 64-bit addressing support for zynq gem.
This means it can perform send and receive operations on
64-bit address buffers.
Signed-off-by: Vipul Kumar
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
drivers/net/zynq_gem.c | 63 ++
1 file changed, 54 insertions(+), 9 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index bc33126..ee528db 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -86,10 +86,17 @@ DECLARE_GLOBAL_DATA_PTR;
/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
#define ZYNQ_GEM_DMACR_RXBUF 0x0018
+#if defined(CONFIG_PHYS_64BIT)
+# define ZYNQ_GEM_DMA_BUS_WIDTHBIT(30) /* 64 bit bus */
+#else
+# define ZYNQ_GEM_DMA_BUS_WIDTH(0 << 30) /* 32 bit bus */
+#endif
+
#define ZYNQ_GEM_DMACR_INIT(ZYNQ_GEM_DMACR_BLENGTH | \
ZYNQ_GEM_DMACR_RXSIZE | \
ZYNQ_GEM_DMACR_TXSIZE | \
- ZYNQ_GEM_DMACR_RXBUF)
+ ZYNQ_GEM_DMACR_RXBUF | \
+ ZYNQ_GEM_DMA_BUS_WIDTH)
#define ZYNQ_GEM_TSR_DONE 0x0020 /* Tx done mask */
@@ -147,12 +154,20 @@ struct zynq_gem_regs {
u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
u32 reserved8[15];
u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
+ u32 reserved10[17];
+ u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
+ u32 reserved11[2];
+ u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
};
/* BD descriptors */
struct emac_bd {
u32 addr; /* Next descriptor pointer */
u32 status;
+#if defined(CONFIG_PHYS_64BIT)
+ u32 addr_hi;
+ u32 reserved;
+#endif
};
#define RX_BUF 32
@@ -390,13 +405,21 @@ static int zynq_gem_init(struct udevice *dev)
for (i = 0; i < RX_BUF; i++) {
priv->rx_bd[i].status = 0xF000;
priv->rx_bd[i].addr =
- ((ulong)(priv->rxbuffers) +
- (i * PKTSIZE_ALIGN));
- }
+ (lower_32_bits((ulong)(priv->rxbuffers)
+ + (i * PKTSIZE_ALIGN)));
+#if defined(CONFIG_PHYS_64BIT)
+ priv->rx_bd[i].addr_hi =
+ (upper_32_bits((ulong)(priv->rxbuffers)
+ + (i * PKTSIZE_ALIGN)));
+#endif
+ }
/* WRAP bit to last BD */
priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
/* Write RxBDs to IP */
- writel((ulong)priv->rx_bd, >rxqbase);
+ writel(lower_32_bits((ulong)priv->rx_bd), >rxqbase);
+#if defined(CONFIG_PHYS_64BIT)
+ writel(upper_32_bits((ulong)priv->rx_bd), >upper_rxqbase);
+#endif
/* Setup for DMA Configuration register */
writel(ZYNQ_GEM_DMACR_INIT, >dmacr);
@@ -406,12 +429,18 @@ static int zynq_gem_init(struct udevice *dev)
/* Disable the second priority queue */
dummy_tx_bd->addr = 0;
+#if defined(CONFIG_PHYS_64BIT)
+ dummy_tx_bd->addr_hi = 0;
+#endif
dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
ZYNQ_GEM_TXBUF_LAST_MASK|
ZYNQ_GEM_TXBUF_USED_MASK;
dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
ZYNQ_GEM_RXBUF_NEW_MASK;
+#if defined(CONFIG_PHYS_64BIT)
+ dummy_rx_bd->addr_hi = 0;
+#endif
dummy_rx_bd->status = 0;
writel((ulong)dummy_tx_bd, >transmit_q1_ptr);
@@ -485,7 +514,8 @@ static int zynq_gem_init(struct udevice *dev)
static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
{
- u32 addr, size;
+ dma_addr_t addr;
+ u32 size;
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct zynq_gem_regs *regs = priv->iobase;
struct emac_bd *current_bd = >tx_bd[1];
@@ -493,17 +523,26 @@ static int zynq_gem_send(struct udevice *dev, void *ptr,
int len)
/* Setup Tx BD */
memset(priv->tx_bd, 0, sizeof(struct emac_bd));
- priv->tx_bd->addr = (ulong)ptr;
+ priv->tx_bd->addr = lower_32_bits((ulong)ptr);
+#if defined(CONFIG_PHYS_64BIT)
+ priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
+#endif
priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
ZYNQ_GEM_TXBUF_LAST_M
Re: [U-Boot] [PATCH v3] usb: dwc3: convert to livetree
Hi Marek/Michal,
Can you please review and let me know if any comments otherwise, please take it
up.
Thanks,
Siva
> -Original Message-
> From: Siva Durga Prasad Paladugu [mailto:siva.durga.palad...@xilinx.com]
> Sent: Friday, September 07, 2018 4:27 PM
> To: u-boot@lists.denx.de
> Cc: Michal Simek ; ma...@denx.de;
> bmeng...@gmail.com; s...@chromium.org;
> yamada.masah...@socionext.com; Vipul Kumar ; Siva
> Durga Prasad Paladugu
> Subject: [PATCH v3] usb: dwc3: convert to livetree
>
> From: Vipul Kumar
>
> Update the DWC3 USB driver to support a live tree.
>
> Signed-off-by: Vipul Kumar
> Signed-off-by: Siva Durga Prasad Paladugu
>
> Tested-by: Michal Simek
> ---
> Changes in v3:
> - Used ofnode_valid() to check for node validity
> This fixes the below compilation failure
> for stih410-b2260_defconfig
> LD cmd/built-in.o
> drivers/usb/host/dwc3-sti-glue.c: In function ‘sti_dwc3_glue_bind’:
> drivers/usb/host/dwc3-sti-glue.c:160:16: error: invalid operands to binary
> <= (have ‘ofnode {aka union ofnode_union}’ and ‘int’)
> if (dwc3_node <= 0) {
> ^~
> make[1]: *** [drivers/usb/host/dwc3-sti-glue.o] Error 1
>
> Changes in v2:
> - compilation failures for am335x_hs_evm_uart platform during travis ci as
> v1 didn’t made corresponding changes to drivers/usb/musb-new/ti-
> musb.c
> as per live tree conversion.
> Now it is fixed in v2 by moving this driver to support live tree.
> Also fixed dwc3-sti-glue.c to support live tree.
> ---
> drivers/usb/common/common.c | 11 +--
> drivers/usb/dwc3/dwc3-generic.c | 17 +++--
> drivers/usb/host/dwc3-sti-glue.c | 9 -
> drivers/usb/host/xhci-dwc3.c | 3 ++-
> drivers/usb/host/xhci-zynqmp.c | 3 +--
> drivers/usb/musb-new/ti-musb.c | 11 ---
> include/linux/usb/otg.h | 6 --
> 7 files changed, 27 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/usb/common/common.c
> b/drivers/usb/common/common.c index a55def5..3dea79b 100644
> --- a/drivers/usb/common/common.c
> +++ b/drivers/usb/common/common.c
> @@ -10,6 +10,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -20,13 +21,12 @@ static const char *const usb_dr_modes[] = {
> [USB_DR_MODE_OTG] = "otg",
> };
>
> -enum usb_dr_mode usb_get_dr_mode(int node)
> +enum usb_dr_mode usb_get_dr_mode(ofnode node)
> {
> - const void *fdt = gd->fdt_blob;
> const char *dr_mode;
> int i;
>
> - dr_mode = fdt_getprop(fdt, node, "dr_mode", NULL);
> + dr_mode = ofnode_get_property(node, "dr_mode", NULL);
> if (!dr_mode) {
> pr_err("usb dr_mode not found\n");
> return USB_DR_MODE_UNKNOWN;
> @@ -48,13 +48,12 @@ static const char *const speed_names[] = {
> [USB_SPEED_SUPER] = "super-speed",
> };
>
> -enum usb_device_speed usb_get_maximum_speed(int node)
> +enum usb_device_speed usb_get_maximum_speed(ofnode node)
> {
> - const void *fdt = gd->fdt_blob;
> const char *max_speed;
> int i;
>
> - max_speed = fdt_getprop(fdt, node, "maximum-speed", NULL);
> + max_speed = ofnode_get_property(node, "maximum-speed",
> NULL);
> if (!max_speed) {
> pr_err("usb maximum-speed not found\n");
> return USB_SPEED_UNKNOWN;
> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-
> generic.c index ca63eac..ef72c8c 100644
> --- a/drivers/usb/dwc3/dwc3-generic.c
> +++ b/drivers/usb/dwc3/dwc3-generic.c
> @@ -61,18 +61,17 @@ static int dwc3_generic_peripheral_remove(struct
> udevice *dev) static int
> dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev) {
> struct dwc3 *priv = dev_get_priv(dev);
> - int node = dev_of_offset(dev);
>
> - priv->regs = (void *)devfdt_get_addr(dev);
> + priv->regs = (void *)dev_read_addr(dev);
> priv->regs += DWC3_GLOBALS_REGS_START;
>
> - priv->maximum_speed = usb_get_maximum_speed(node);
> + priv->maximum_speed = usb_get_maximum_speed(dev->node);
> if (priv->maximum_speed == USB_SPEED_UNKNOWN) {
> pr_err("Invalid usb maximum speed\n");
> return -ENODEV;
> }
>
> - priv->dr_mode = usb_get_dr_mode(node);
> + priv->dr_mode = usb_get_dr_mode(dev->node);
> if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
> pr_err("Invalid usb mode setup\n");
> return -ENODEV;
> @@ -100,13 +99,11 @@ U
Re: [U-Boot] QSPI driver for Zynq and ZynqMP
Hi Jagan, Could you please take some time to look into this mail and let me now your comments. Thanks, Siva > -Original Message- > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Siva > Durga Prasad Paladugu > Sent: Wednesday, September 12, 2018 2:47 PM > To: u-boot@lists.denx.de > Cc: Michal Simek ; Jagan Teki > > Subject: Re: [U-Boot] QSPI driver for Zynq and ZynqMP > > Ping! > > Thanks, > Siva > > From: Siva Durga Prasad Paladugu > Sent: Friday, September 07, 2018 12:59 PM > To: 'u-boot@lists.denx.de' > Cc: Jagan Teki ; Michal Simek > > Subject: QSPI driver for Zynq and ZynqMP > > Hi Jagan, > > We would like to upstream quad and dual modes(parallel and stacked) > support for qspi drivers of Zynq and ZynqMP. Can we send patches based > on existing framework(drivers/spi , this is what we are using on Xilinx tree) > or you want us to use any other? > I know we had discussion sometime back on this and we completed > upstreaming driver without dual modes support as a first step. Please let > me know on how to proceed further on adding quad and dual modes > support. Any inputs are welcome. > > Thanks, > Siva > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] QSPI driver for Zynq and ZynqMP
Ping! Thanks, Siva From: Siva Durga Prasad Paladugu Sent: Friday, September 07, 2018 12:59 PM To: 'u-boot@lists.denx.de' Cc: Jagan Teki ; Michal Simek Subject: QSPI driver for Zynq and ZynqMP Hi Jagan, We would like to upstream quad and dual modes(parallel and stacked) support for qspi drivers of Zynq and ZynqMP. Can we send patches based on existing framework(drivers/spi , this is what we are using on Xilinx tree) or you want us to use any other? I know we had discussion sometime back on this and we completed upstreaming driver without dual modes support as a first step. Please let me know on how to proceed further on adding quad and dual modes support. Any inputs are welcome. Thanks, Siva ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3] usb: dwc3: convert to livetree
From: Vipul Kumar
Update the DWC3 USB driver to support a live tree.
Signed-off-by: Vipul Kumar
Signed-off-by: Siva Durga Prasad Paladugu
Tested-by: Michal Simek
---
Changes in v3:
- Used ofnode_valid() to check for node validity
This fixes the below compilation failure
for stih410-b2260_defconfig
LD cmd/built-in.o
drivers/usb/host/dwc3-sti-glue.c: In function ‘sti_dwc3_glue_bind’:
drivers/usb/host/dwc3-sti-glue.c:160:16: error: invalid operands to binary <=
(have ‘ofnode {aka union ofnode_union}’ and ‘int’)
if (dwc3_node <= 0) {
^~
make[1]: *** [drivers/usb/host/dwc3-sti-glue.o] Error 1
Changes in v2:
- compilation failures for am335x_hs_evm_uart platform during travis ci as
v1 didn’t made corresponding changes to drivers/usb/musb-new/ti-musb.c
as per live tree conversion.
Now it is fixed in v2 by moving this driver to support live tree.
Also fixed dwc3-sti-glue.c to support live tree.
---
drivers/usb/common/common.c | 11 +--
drivers/usb/dwc3/dwc3-generic.c | 17 +++--
drivers/usb/host/dwc3-sti-glue.c | 9 -
drivers/usb/host/xhci-dwc3.c | 3 ++-
drivers/usb/host/xhci-zynqmp.c | 3 +--
drivers/usb/musb-new/ti-musb.c | 11 ---
include/linux/usb/otg.h | 6 --
7 files changed, 27 insertions(+), 33 deletions(-)
diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
index a55def5..3dea79b 100644
--- a/drivers/usb/common/common.c
+++ b/drivers/usb/common/common.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -20,13 +21,12 @@ static const char *const usb_dr_modes[] = {
[USB_DR_MODE_OTG] = "otg",
};
-enum usb_dr_mode usb_get_dr_mode(int node)
+enum usb_dr_mode usb_get_dr_mode(ofnode node)
{
- const void *fdt = gd->fdt_blob;
const char *dr_mode;
int i;
- dr_mode = fdt_getprop(fdt, node, "dr_mode", NULL);
+ dr_mode = ofnode_get_property(node, "dr_mode", NULL);
if (!dr_mode) {
pr_err("usb dr_mode not found\n");
return USB_DR_MODE_UNKNOWN;
@@ -48,13 +48,12 @@ static const char *const speed_names[] = {
[USB_SPEED_SUPER] = "super-speed",
};
-enum usb_device_speed usb_get_maximum_speed(int node)
+enum usb_device_speed usb_get_maximum_speed(ofnode node)
{
- const void *fdt = gd->fdt_blob;
const char *max_speed;
int i;
- max_speed = fdt_getprop(fdt, node, "maximum-speed", NULL);
+ max_speed = ofnode_get_property(node, "maximum-speed", NULL);
if (!max_speed) {
pr_err("usb maximum-speed not found\n");
return USB_SPEED_UNKNOWN;
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index ca63eac..ef72c8c 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -61,18 +61,17 @@ static int dwc3_generic_peripheral_remove(struct udevice
*dev)
static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
{
struct dwc3 *priv = dev_get_priv(dev);
- int node = dev_of_offset(dev);
- priv->regs = (void *)devfdt_get_addr(dev);
+ priv->regs = (void *)dev_read_addr(dev);
priv->regs += DWC3_GLOBALS_REGS_START;
- priv->maximum_speed = usb_get_maximum_speed(node);
+ priv->maximum_speed = usb_get_maximum_speed(dev->node);
if (priv->maximum_speed == USB_SPEED_UNKNOWN) {
pr_err("Invalid usb maximum speed\n");
return -ENODEV;
}
- priv->dr_mode = usb_get_dr_mode(node);
+ priv->dr_mode = usb_get_dr_mode(dev->node);
if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
pr_err("Invalid usb mode setup\n");
return -ENODEV;
@@ -100,13 +99,11 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
static int dwc3_generic_bind(struct udevice *parent)
{
- const void *fdt = gd->fdt_blob;
- int node;
+ ofnode node;
int ret;
- for (node = fdt_first_subnode(fdt, dev_of_offset(parent)); node > 0;
-node = fdt_next_subnode(fdt, node)) {
- const char *name = fdt_get_name(fdt, node, NULL);
+ dev_for_each_subnode(node, parent) {
+ const char *name = (char *)ofnode_get_name(node);
enum usb_dr_mode dr_mode;
struct udevice *dev;
const char *driver;
@@ -133,7 +130,7 @@ static int dwc3_generic_bind(struct udevice *parent)
};
ret = device_bind_driver_to_node(parent, driver, name,
-offset_to_ofnode(node), );
+node, );
if (ret) {
debug("%s: not able to bind
[U-Boot] QSPI driver for Zynq and ZynqMP
Hi Jagan, We would like to upstream quad and dual modes(parallel and stacked) support for qspi drivers of Zynq and ZynqMP. Can we send patches based on existing framework(drivers/spi , this is what we are using on Xilinx tree) or you want us to use any other? I know we had discussion sometime back on this and we completed upstreaming driver without dual modes support as a first step. Please let me know on how to proceed further on adding quad and dual modes support. Any inputs are welcome. Thanks, Siva ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] usb: dwc3: convert to livetree
Hi,
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Thursday, September 06, 2018 7:36 PM
> To: Siva Durga Prasad Paladugu ; u-
> b...@lists.denx.de
> Cc: Michal Simek ; ma...@denx.de;
> bmeng...@gmail.com; s...@chromium.org;
> yamada.masah...@socionext.com; Vipul Kumar
> Subject: Re: [PATCH v2] usb: dwc3: convert to livetree
>
> On 6.9.2018 12:39, Siva Durga Prasad Paladugu wrote:
> > From: Vipul Kumar
> >
> > Update the DWC3 USB driver to support a live tree.
> >
> > Signed-off-by: Siva Durga Prasad Paladugu
> >
> > Signed-off-by: Vipul Kumar
> > Tested-by: Michal Simek
> > ---
> > Changes in v2:
> > - Fixed travis build issues with some platforms.
> > ---
> > drivers/usb/common/common.c | 11 +--
> > drivers/usb/dwc3/dwc3-generic.c | 17 +++--
> > drivers/usb/host/dwc3-sti-glue.c | 7 +++
> > drivers/usb/host/xhci-dwc3.c | 3 ++-
> > drivers/usb/host/xhci-zynqmp.c | 3 +--
> > drivers/usb/musb-new/ti-musb.c | 11 ---
> > include/linux/usb/otg.h | 6 --
> > 7 files changed, 26 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/usb/common/common.c
> b/drivers/usb/common/common.c
> > index a55def5..3dea79b 100644
> > --- a/drivers/usb/common/common.c
> > +++ b/drivers/usb/common/common.c
> > @@ -10,6 +10,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -20,13 +21,12 @@ static const char *const usb_dr_modes[] = {
> > [USB_DR_MODE_OTG] = "otg",
> > };
> >
> > -enum usb_dr_mode usb_get_dr_mode(int node)
> > +enum usb_dr_mode usb_get_dr_mode(ofnode node)
> > {
> > - const void *fdt = gd->fdt_blob;
> > const char *dr_mode;
> > int i;
> >
> > - dr_mode = fdt_getprop(fdt, node, "dr_mode", NULL);
> > + dr_mode = ofnode_get_property(node, "dr_mode", NULL);
> > if (!dr_mode) {
> > pr_err("usb dr_mode not found\n");
> > return USB_DR_MODE_UNKNOWN;
> > @@ -48,13 +48,12 @@ static const char *const speed_names[] = {
> > [USB_SPEED_SUPER] = "super-speed",
> > };
> >
> > -enum usb_device_speed usb_get_maximum_speed(int node)
> > +enum usb_device_speed usb_get_maximum_speed(ofnode node)
> > {
> > - const void *fdt = gd->fdt_blob;
> > const char *max_speed;
> > int i;
> >
> > - max_speed = fdt_getprop(fdt, node, "maximum-speed", NULL);
> > + max_speed = ofnode_get_property(node, "maximum-speed",
> NULL);
> > if (!max_speed) {
> > pr_err("usb maximum-speed not found\n");
> > return USB_SPEED_UNKNOWN;
> > diff --git a/drivers/usb/dwc3/dwc3-generic.c
> > b/drivers/usb/dwc3/dwc3-generic.c index ca63eac..ef72c8c 100644
> > --- a/drivers/usb/dwc3/dwc3-generic.c
> > +++ b/drivers/usb/dwc3/dwc3-generic.c
> > @@ -61,18 +61,17 @@ static int
> dwc3_generic_peripheral_remove(struct
> > udevice *dev) static int
> > dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev) {
> > struct dwc3 *priv = dev_get_priv(dev);
> > - int node = dev_of_offset(dev);
> >
> > - priv->regs = (void *)devfdt_get_addr(dev);
> > + priv->regs = (void *)dev_read_addr(dev);
> > priv->regs += DWC3_GLOBALS_REGS_START;
> >
> > - priv->maximum_speed = usb_get_maximum_speed(node);
> > + priv->maximum_speed = usb_get_maximum_speed(dev->node);
> > if (priv->maximum_speed == USB_SPEED_UNKNOWN) {
> > pr_err("Invalid usb maximum speed\n");
> > return -ENODEV;
> > }
> >
> > - priv->dr_mode = usb_get_dr_mode(node);
> > + priv->dr_mode = usb_get_dr_mode(dev->node);
> > if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
> > pr_err("Invalid usb mode setup\n");
> > return -ENODEV;
> > @@ -100,13 +99,11 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
> >
> > static int dwc3_generic_bind(struct udevice *parent) {
> > - const void *fdt = gd->fdt_blob;
> > - int node;
> > + ofnode node;
> > int ret;
> >
> > - for (node = fdt_first_subnode(fdt, dev_of_offset(parent)); node > 0;
> > -node = fdt_next_subnode(fdt, node)) {
> > - const char *name = fdt_get_name(fdt, node, NULL);
> > + dev_fo
Re: [U-Boot] [PATCH v2] usb: dwc3: convert to livetree
Hi,
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Thursday, September 06, 2018 4:28 PM
> To: Siva Durga Prasad Paladugu ; u-
> b...@lists.denx.de
> Cc: Michal Simek ; bmeng...@gmail.com;
> s...@chromium.org; yamada.masah...@socionext.com; Vipul Kumar
>
> Subject: Re: [PATCH v2] usb: dwc3: convert to livetree
>
> On 09/06/2018 12:39 PM, Siva Durga Prasad Paladugu wrote:
> > From: Vipul Kumar
> >
> > Update the DWC3 USB driver to support a live tree.
> >
> > Signed-off-by: Siva Durga Prasad Paladugu
> >
> > Signed-off-by: Vipul Kumar
> > Tested-by: Michal Simek
> > ---
> > Changes in v2:
> > - Fixed travis build issues with some platforms.
>
> Cool, what exactly changed ?
Earlier we got compilation failures for am335x_hs_evm_uart platform during
travis ci
as we didn’t made corresponding changes to drivers/usb/musb-new/ti-musb.c as
per
live tree conversion. Now it is fixed by moving this driver to support live
tree.
Also fixed dwc3-sti-glue.c to support live tree.
Thanks,
Siva
>
> > ---
> > drivers/usb/common/common.c | 11 +--
> > drivers/usb/dwc3/dwc3-generic.c | 17 +++--
> > drivers/usb/host/dwc3-sti-glue.c | 7 +++
> > drivers/usb/host/xhci-dwc3.c | 3 ++-
> > drivers/usb/host/xhci-zynqmp.c | 3 +--
> > drivers/usb/musb-new/ti-musb.c | 11 ---
> > include/linux/usb/otg.h | 6 --
> > 7 files changed, 26 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/usb/common/common.c
> b/drivers/usb/common/common.c
> > index a55def5..3dea79b 100644
> > --- a/drivers/usb/common/common.c
> > +++ b/drivers/usb/common/common.c
> > @@ -10,6 +10,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -20,13 +21,12 @@ static const char *const usb_dr_modes[] = {
> > [USB_DR_MODE_OTG] = "otg",
> > };
> >
> > -enum usb_dr_mode usb_get_dr_mode(int node)
> > +enum usb_dr_mode usb_get_dr_mode(ofnode node)
> > {
> > - const void *fdt = gd->fdt_blob;
> > const char *dr_mode;
> > int i;
> >
> > - dr_mode = fdt_getprop(fdt, node, "dr_mode", NULL);
> > + dr_mode = ofnode_get_property(node, "dr_mode", NULL);
> > if (!dr_mode) {
> > pr_err("usb dr_mode not found\n");
> > return USB_DR_MODE_UNKNOWN;
> > @@ -48,13 +48,12 @@ static const char *const speed_names[] = {
> > [USB_SPEED_SUPER] = "super-speed",
> > };
> >
> > -enum usb_device_speed usb_get_maximum_speed(int node)
> > +enum usb_device_speed usb_get_maximum_speed(ofnode node)
> > {
> > - const void *fdt = gd->fdt_blob;
> > const char *max_speed;
> > int i;
> >
> > - max_speed = fdt_getprop(fdt, node, "maximum-speed", NULL);
> > + max_speed = ofnode_get_property(node, "maximum-speed",
> NULL);
> > if (!max_speed) {
> > pr_err("usb maximum-speed not found\n");
> > return USB_SPEED_UNKNOWN;
> > diff --git a/drivers/usb/dwc3/dwc3-generic.c
> > b/drivers/usb/dwc3/dwc3-generic.c index ca63eac..ef72c8c 100644
> > --- a/drivers/usb/dwc3/dwc3-generic.c
> > +++ b/drivers/usb/dwc3/dwc3-generic.c
> > @@ -61,18 +61,17 @@ static int
> dwc3_generic_peripheral_remove(struct
> > udevice *dev) static int
> > dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev) {
> > struct dwc3 *priv = dev_get_priv(dev);
> > - int node = dev_of_offset(dev);
> >
> > - priv->regs = (void *)devfdt_get_addr(dev);
> > + priv->regs = (void *)dev_read_addr(dev);
> > priv->regs += DWC3_GLOBALS_REGS_START;
> >
> > - priv->maximum_speed = usb_get_maximum_speed(node);
> > + priv->maximum_speed = usb_get_maximum_speed(dev->node);
> > if (priv->maximum_speed == USB_SPEED_UNKNOWN) {
> > pr_err("Invalid usb maximum speed\n");
> > return -ENODEV;
> > }
> >
> > - priv->dr_mode = usb_get_dr_mode(node);
> > + priv->dr_mode = usb_get_dr_mode(dev->node);
> > if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
> > pr_err("Invalid usb mode setup\n");
> > return -ENODEV;
> > @@ -100,13 +99,11 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
> >
> > static int dwc3_generic_bind(struct udevice *parent) {
> >
[U-Boot] [PATCH v2] usb: dwc3: convert to livetree
From: Vipul Kumar
Update the DWC3 USB driver to support a live tree.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Vipul Kumar
Tested-by: Michal Simek
---
Changes in v2:
- Fixed travis build issues with some platforms.
---
drivers/usb/common/common.c | 11 +--
drivers/usb/dwc3/dwc3-generic.c | 17 +++--
drivers/usb/host/dwc3-sti-glue.c | 7 +++
drivers/usb/host/xhci-dwc3.c | 3 ++-
drivers/usb/host/xhci-zynqmp.c | 3 +--
drivers/usb/musb-new/ti-musb.c | 11 ---
include/linux/usb/otg.h | 6 --
7 files changed, 26 insertions(+), 32 deletions(-)
diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
index a55def5..3dea79b 100644
--- a/drivers/usb/common/common.c
+++ b/drivers/usb/common/common.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -20,13 +21,12 @@ static const char *const usb_dr_modes[] = {
[USB_DR_MODE_OTG] = "otg",
};
-enum usb_dr_mode usb_get_dr_mode(int node)
+enum usb_dr_mode usb_get_dr_mode(ofnode node)
{
- const void *fdt = gd->fdt_blob;
const char *dr_mode;
int i;
- dr_mode = fdt_getprop(fdt, node, "dr_mode", NULL);
+ dr_mode = ofnode_get_property(node, "dr_mode", NULL);
if (!dr_mode) {
pr_err("usb dr_mode not found\n");
return USB_DR_MODE_UNKNOWN;
@@ -48,13 +48,12 @@ static const char *const speed_names[] = {
[USB_SPEED_SUPER] = "super-speed",
};
-enum usb_device_speed usb_get_maximum_speed(int node)
+enum usb_device_speed usb_get_maximum_speed(ofnode node)
{
- const void *fdt = gd->fdt_blob;
const char *max_speed;
int i;
- max_speed = fdt_getprop(fdt, node, "maximum-speed", NULL);
+ max_speed = ofnode_get_property(node, "maximum-speed", NULL);
if (!max_speed) {
pr_err("usb maximum-speed not found\n");
return USB_SPEED_UNKNOWN;
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index ca63eac..ef72c8c 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -61,18 +61,17 @@ static int dwc3_generic_peripheral_remove(struct udevice
*dev)
static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
{
struct dwc3 *priv = dev_get_priv(dev);
- int node = dev_of_offset(dev);
- priv->regs = (void *)devfdt_get_addr(dev);
+ priv->regs = (void *)dev_read_addr(dev);
priv->regs += DWC3_GLOBALS_REGS_START;
- priv->maximum_speed = usb_get_maximum_speed(node);
+ priv->maximum_speed = usb_get_maximum_speed(dev->node);
if (priv->maximum_speed == USB_SPEED_UNKNOWN) {
pr_err("Invalid usb maximum speed\n");
return -ENODEV;
}
- priv->dr_mode = usb_get_dr_mode(node);
+ priv->dr_mode = usb_get_dr_mode(dev->node);
if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
pr_err("Invalid usb mode setup\n");
return -ENODEV;
@@ -100,13 +99,11 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
static int dwc3_generic_bind(struct udevice *parent)
{
- const void *fdt = gd->fdt_blob;
- int node;
+ ofnode node;
int ret;
- for (node = fdt_first_subnode(fdt, dev_of_offset(parent)); node > 0;
-node = fdt_next_subnode(fdt, node)) {
- const char *name = fdt_get_name(fdt, node, NULL);
+ dev_for_each_subnode(node, parent) {
+ const char *name = (char *)ofnode_get_name(node);
enum usb_dr_mode dr_mode;
struct udevice *dev;
const char *driver;
@@ -133,7 +130,7 @@ static int dwc3_generic_bind(struct udevice *parent)
};
ret = device_bind_driver_to_node(parent, driver, name,
-offset_to_ofnode(node), );
+node, );
if (ret) {
debug("%s: not able to bind usb device mode\n",
__func__);
diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c
index ad7cf6e..de423ee 100644
--- a/drivers/usb/host/dwc3-sti-glue.c
+++ b/drivers/usb/host/dwc3-sti-glue.c
@@ -153,18 +153,17 @@ static int sti_dwc3_glue_ofdata_to_platdata(struct
udevice *dev)
static int sti_dwc3_glue_bind(struct udevice *dev)
{
struct sti_dwc3_glue_platdata *plat = dev_get_platdata(dev);
- int dwc3_node;
+ ofnode dwc3_node;
/* check if one subnode is present */
- dwc3_node = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
+ dwc3_node = dev_read_first_subnode(dev);
if (dwc3_node <= 0)
[U-Boot] [PATCH] net: zynq_gem: Fix reading of max-speed property
max-speed property is part of phynode and it has to be
read using ofnode_read_u32_default(). This fixes the issue
of incorrect max-speed read from DT.
Signed-off-by: Siva Durga Prasad Paladugu
---
drivers/net/zynq_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 68d1c2f..d5c3fbe 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -716,7 +716,8 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
}
priv->interface = pdata->phy_interface;
- priv->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
+ priv->max_speed = ofnode_read_u32_default(phandle_args.node,
+ "max-speed", SPEED_1000);
priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
--
2.7.4
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[U-Boot] Query on FAT file system
Hi, I have below queries on FAT filesystem support in uboot. It would be really helpful if someone can provide some insight into these. 1. fatwrite command is not able to write into subdirectories, but able to perform same ops on to root directory, its treating / as part of file name while trying to write into subdirs. Is there any otherway to write into subdirectories instead of using slashes or Is it a limitation/feature not supported in u-boot for writes to subdirectories in fat filesystem? 2. Does fatwrite command support overwriting a file in root directory. For example if there is a file with name abc.bin in SD card and I perform fatwrite to SD with same filename as( fatwrite mmc 0 1 abc.bin size). 3. The FAT16 support in uboot was broken https://lists.denx.de/pipermail/u-boot/2018-July/335292.html Is it fixed now or any update on this would really be helpful. Thanks, Siva ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [UBOOT PATCH v2] net: zynq_gem: convert to use livetree
Hi Joe/Michal,
Can you please take it up if it is fine.
Thanks,
Siva
> -Original Message-
> From: Siva Durga Prasad Paladugu [mailto:siva.durga.palad...@xilinx.com]
> Sent: Monday, July 16, 2018 6:26 PM
> To: u-boot@lists.denx.de
> Cc: Michal Simek ; joe.hershber...@ni.com;
> grygorii.stras...@ti.com; Siva Durga Prasad Paladugu
> ; Vipul Kumar
> Subject: [UBOOT PATCH v2] net: zynq_gem: convert to use livetree
>
> This patch updates the zynq gem driver to support livetree.
>
> Signed-off-by: Siva Durga Prasad Paladugu
>
> Signed-off-by: Vipul Kumar
> ---
> Changes for v2:
> - Note that this patch is based on below two series.
> https://patchwork.ozlabs.org/cover/936370/
> and
> https://patchwork.ozlabs.org/cover/936380/
> ---
> drivers/net/zynq_gem.c | 30 ++
> 1 file changed, 14 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index
> 0f56cda..68d1c2f 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -178,7 +178,7 @@ struct zynq_gem_priv {
> struct zynq_gem_regs *iobase;
> phy_interface_t interface;
> struct phy_device *phydev;
> - int phy_of_handle;
> + ofnode phy_of_node;
> struct mii_dev *bus;
> struct clk clk;
> u32 max_speed;
> @@ -348,9 +348,7 @@ static int zynq_phy_init(struct udevice *dev)
> }
>
> priv->phydev->advertising = priv->phydev->supported;
> -
> - if (priv->phy_of_handle > 0)
> - priv->phydev->node = offset_to_ofnode(priv-
> >phy_of_handle);
> + priv->phydev->node = priv->phy_of_node;
>
> return phy_config(priv->phydev);
> }
> @@ -693,21 +691,23 @@ static int zynq_gem_ofdata_to_platdata(struct
> udevice *dev) {
> struct eth_pdata *pdata = dev_get_platdata(dev);
> struct zynq_gem_priv *priv = dev_get_priv(dev);
> - int node = dev_of_offset(dev);
> + struct ofnode_phandle_args phandle_args;
> const char *phy_mode;
>
> - pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
> + pdata->iobase = (phys_addr_t)dev_read_addr(dev);
> priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
> /* Hardcode for now */
> priv->phyaddr = -1;
>
> - priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
> - "phy-handle");
> - if (priv->phy_of_handle > 0)
> - priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
> - priv->phy_of_handle, "reg", -1);
> + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> +_args)) {
> + debug("phy-handle does not exist %s\n", dev->name);
> + return -ENOENT;
> + }
>
> - phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
> + priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
> "reg", -1);
> + priv->phy_of_node = phandle_args.node;
> + phy_mode = dev_read_prop(dev, "phy-mode", NULL);
> if (phy_mode)
> pdata->phy_interface =
> phy_get_interface_by_name(phy_mode);
> if (pdata->phy_interface == -1) {
> @@ -716,10 +716,8 @@ static int zynq_gem_ofdata_to_platdata(struct
> udevice *dev)
> }
> priv->interface = pdata->phy_interface;
>
> - priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv-
> >phy_of_handle,
> - "max-speed", SPEED_1000);
> - priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
> - "is-internal-pcspma");
> + priv->max_speed = dev_read_u32_default(dev, "max-speed",
> SPEED_1000);
> + priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
>
> printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv-
> >iobase,
> priv->phyaddr, phy_string_for_interface(priv->interface));
> --
> 2.7.4
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Re: [U-Boot] Issue with fat16 format
Hi Heinrich/Rob, Do we have any update on this issue. Thanks, Siva > -Original Message- > From: Vipul Kumar > Sent: Monday, June 18, 2018 10:35 AM > To: Heinrich Schuchardt ; u-boot@lists.denx.de > Cc: Michal Simek ; Siva Durga Prasad Paladugu > ; Rob Clark ; Łukasz Majewski > ; Simon Glass > Subject: RE: [U-Boot] Issue with fat16 format > > Hi Heinrich, > > > -Original Message- > > From: Heinrich Schuchardt [mailto:xypron.deb...@gmx.de] > > Sent: Sunday, June 17, 2018 1:07 AM > > To: Vipul Kumar ; u-boot@lists.denx.de > > Cc: Michal Simek ; Siva Durga Prasad Paladugu > > ; Rob Clark ; Łukasz > Majewski > > ; Simon Glass > > Subject: Re: [U-Boot] Issue with fat16 format > > > > On 06/15/2018 08:37 AM, Vipul Kumar wrote: > > > Hi, > > > > > > After formatting SD card in fat16 format in windows, we are facing > > > issue. I > > used git bisect and came to know that this issue is due to > > 8eafae209c35932d9a6560809c55ee4641534236 commit. > > > > > > When we use "gparted" utility for formatting SD card in fat16 in > > > linux, it > > works fine. > > > > > > Please give your comments on this issue and point out what's causing > > > this > > issue. > > > > > > Regards, > > > Vipul Kumar > > > > > > > > > > Hello Vipul, > > > > >> we are facing issue > > could you, please, indicate what issue you face. Please, also tell > > which configuration file you are using. > > Configuration file: zynq_zc702_defconfig > > Issue: We are using BOOT.BIN and fit image (Kernel image + dtb + rootfs) to > boot the board. Board is booting till u-boot successfully but when it goes to > read image.ub for further booting, it gives below message: > > ERROR: > Hit any key to stop autoboot: 0 > Copying FIT from SD to RAM... > ** Unable to read file image.ub ** > > After this, I run the fatls command and it seems that it removed both > BOOT.BIN and image.ub files. > > Zynq> mmc info > Device: sdhci@e010 > Manufacturer ID: 27 > OEM: 5048 > Name: SD04G > Bus Speed: 5000 > Mode : SD High Speed (50MHz) > Rd Block Len: 512 > SD version 3.0 > High Capacity: Yes > Capacity: 3.7 GiB > Bus Width: 4-bit > Erase Group Size: 512 Bytes > > Zynq> fatls mmc 0:1 > > 0 file(s), 0 dir(s) > > Zynq> > > > Regards, > Vipul > > > > As you are complaining about Rob's patch I put him and the reviewers > > of the patch on CC. > > > > Best regards > > > > Heinrich ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2] arm64: zynqmp: Add QSPI flash mini u-boot configuration
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint of internal memory. This
configuration has only required qspi flash support and it
uses DCC as serial.
Signed-off-by: Siva Durga Prasad Paladugu
---
Chnages for v2:
- Fixed copyright year
- Fixed memory node
- Removed partitions in flash node
- Moved CONFIG_MP to kconfig
This patch is based on
https://lists.denx.de/pipermail/u-boot/2018-July/335126.html
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-mini-qspi.dts | 79 +++
configs/xilinx_zynqmp_mini_qspi_defconfig | 61
include/configs/xilinx_zynqmp_mini_qspi.h | 21
4 files changed, 162 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-mini-qspi.dts
create mode 100644 configs/xilinx_zynqmp_mini_qspi_defconfig
create mode 100644 include/configs/xilinx_zynqmp_mini_qspi.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6785fef..6bbe2a3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -152,6 +152,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb\
+ zynqmp-mini-qspi.dtb\
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts
b/arch/arm/dts/zynqmp-mini-qspi.dts
new file mode 100644
index 000..c235a5f
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad
+ * Michal Simek
+ */
+
+/dts-v1/;
+
+/ {
+ model = "ZynqMP MINI QSPI";
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 =
+ spi0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@fffc {
+ device_type = "memory";
+ reg = <0x0 0xfffc 0x4>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ qspi: spi@ff0f {
+ compatible = "xlnx,zynqmp-qspi-1.0";
+ status = "disabled";
+ clock-names = "ref_clk", "pclk";
+ clocks = <_clk _clk>;
+ num-cs = <1>;
+ reg = <0x0 0xff0f 0x1000 0x0 0xc000 0x800>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ misc_clk: misc_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12500>;
+ };
+ };
+};
+
+ {
+ status = "okay";
+ flash@0 {
+ compatible = "n25q512a11";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <1000>;
+ };
+};
+
+ {
+ status = "okay";
+};
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig
b/configs/xilinx_zynqmp_mini_qspi_defconfig
new file mode 100644
index 000..8b32829
--- /dev/null
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -0,0 +1,61 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0xFFFC
+CONFIG_SYS_MEM_RSVD_FOR_MMU=y
+CONFIG_ZYNQMP_NO_DDR=y
+# CONFIG_CMD_ZYNQMP is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi"
+# CONFIG_IMAGE_FORMAT_LEGACY is not set
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_CMDLINE_EDITING is not set
+# CONFIG_AUTO_COMPLETE is not set
+# CONFIG_SYS_LONGHELP is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
[U-Boot] [PATCH] arm64: zynqmp: Add QSPI flash mini u-boot configuration
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint of internal memory. This
configuration has only required qspi flash support and it
uses DCC as serial.
Signed-off-by: Siva Durga Prasad Paladugu
---
This patch is based on series
"[PATCH v6 0/5] Add support for reading memory configuration from
DT at run-time"
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynqmp-mini-qspi.dts | 95 +++
configs/xilinx_zynqmp_mini_qspi_defconfig | 61
include/configs/xilinx_zynqmp_mini_qspi.h | 22 +++
4 files changed, 179 insertions(+)
create mode 100644 arch/arm/dts/zynqmp-mini-qspi.dts
create mode 100644 configs/xilinx_zynqmp_mini_qspi_defconfig
create mode 100644 include/configs/xilinx_zynqmp_mini_qspi.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9607239..b62670b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -150,6 +150,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb\
+ zynqmp-mini-qspi.dtb\
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts
b/arch/arm/dts/zynqmp-mini-qspi.dts
new file mode 100644
index 000..3267021
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad
+ * Michal Simek
+ */
+
+/dts-v1/;
+
+/ {
+ model = "ZynqMP MINI QSPI";
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 =
+ spi0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0xfffc 0x4>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ qspi: spi@ff0f {
+ compatible = "xlnx,zynqmp-qspi-1.0";
+ status = "disabled";
+ clock-names = "ref_clk", "pclk";
+ clocks = <_clk _clk>;
+ num-cs = <1>;
+ reg = <0x0 0xff0f 0x1000 0x0 0xc000 0x800>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ misc_clk: misc_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12500>;
+ };
+ };
+};
+
+ {
+ status = "okay";
+ flash@0 {
+ compatible = "n25q512a11";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <1000>;
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x10>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x10 0x50>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x60 0x2>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x62 0x5E>;
+ };
+ };
+};
+
+ {
+ status = "okay";
+};
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig
b/configs/xilinx_zynqmp_mini_qspi_defconfig
new file mode 100644
index 000..745a550
--- /dev/null
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -0,0 +1,61 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0xF
[U-Boot] [UBOOT PATCH v2] net: zynq_gem: convert to use livetree
This patch updates the zynq gem driver to support livetree.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Vipul Kumar
---
Changes for v2:
- Note that this patch is based on below two series.
https://patchwork.ozlabs.org/cover/936370/
and
https://patchwork.ozlabs.org/cover/936380/
---
drivers/net/zynq_gem.c | 30 ++
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 0f56cda..68d1c2f 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -178,7 +178,7 @@ struct zynq_gem_priv {
struct zynq_gem_regs *iobase;
phy_interface_t interface;
struct phy_device *phydev;
- int phy_of_handle;
+ ofnode phy_of_node;
struct mii_dev *bus;
struct clk clk;
u32 max_speed;
@@ -348,9 +348,7 @@ static int zynq_phy_init(struct udevice *dev)
}
priv->phydev->advertising = priv->phydev->supported;
-
- if (priv->phy_of_handle > 0)
- priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
+ priv->phydev->node = priv->phy_of_node;
return phy_config(priv->phydev);
}
@@ -693,21 +691,23 @@ static int zynq_gem_ofdata_to_platdata(struct udevice
*dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
- int node = dev_of_offset(dev);
+ struct ofnode_phandle_args phandle_args;
const char *phy_mode;
- pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
+ pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->phyaddr = -1;
- priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
- "phy-handle");
- if (priv->phy_of_handle > 0)
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
- priv->phy_of_handle, "reg", -1);
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ _args)) {
+ debug("phy-handle does not exist %s\n", dev->name);
+ return -ENOENT;
+ }
- phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
+ priv->phyaddr = ofnode_read_u32_default(phandle_args.node, "reg", -1);
+ priv->phy_of_node = phandle_args.node;
+ phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
@@ -716,10 +716,8 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
}
priv->interface = pdata->phy_interface;
- priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv->phy_of_handle,
- "max-speed", SPEED_1000);
- priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
- "is-internal-pcspma");
+ priv->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
+ priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] net: zynq_gem: convert to use livetree
HI Joe,
> -Original Message-
> From: Siva Durga Prasad Paladugu
> Sent: Monday, July 16, 2018 2:32 PM
> To: 'joe.hershber...@ni.com' ; Grygorii Strashko
>
> Cc: u-boot ; Michal Simek ;
> Vipul Kumar
> Subject: RE: [U-Boot] [PATCH 3/3] net: zynq_gem: convert to use livetree
>
> Hi Joe,
>
> > -Original Message-
> > From: Joe Hershberger [mailto:joe.hershber...@ni.com]
> > Sent: Thursday, July 12, 2018 12:26 AM
> > To: Siva Durga Prasad Paladugu ; Grygorii Strashko
> >
> > Cc: u-boot ; Joe Hershberger
> > ; Michal Simek ; Vipul
> > Kumar
> > Subject: Re: [U-Boot] [PATCH 3/3] net: zynq_gem: convert to use
> > livetree
> >
> > Hi Siva,
> >
> > On Fri, Jul 6, 2018 at 5:10 AM, Siva Durga Prasad Paladugu
> > wrote:
> > > This patch updates the zynq gem driver to support livetree.
> > >
> > > Signed-off-by: Siva Durga Prasad Paladugu
> > >
> > > Signed-off-by: Vipul Kumar
> > > ---
> > > drivers/net/zynq_gem.c | 29 ++---
> > > 1 file changed, 14 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index
> > > a817f2e..b9858e4 100644
> > > --- a/drivers/net/zynq_gem.c
> > > +++ b/drivers/net/zynq_gem.c
> > > @@ -178,7 +178,7 @@ struct zynq_gem_priv {
> > > struct zynq_gem_regs *iobase;
> > > phy_interface_t interface;
> > > struct phy_device *phydev;
> > > - int phy_of_handle;
> > > + ofnode phy_of_node;
> > > struct mii_dev *bus;
> > > struct clk clk;
> > > u32 max_speed;
> > > @@ -349,8 +349,7 @@ static int zynq_phy_init(struct udevice *dev)
> > >
> > > priv->phydev->advertising = priv->phydev->supported;
> > >
> > > - if (priv->phy_of_handle > 0)
> > > - dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
> > > + priv->phydev->dev->node = priv->phy_of_node;
> > >
> > > return phy_config(priv->phydev); } @@ -693,21 +692,23 @@
> > > static int zynq_gem_ofdata_to_platdata(struct udevice *dev) {
> > > struct eth_pdata *pdata = dev_get_platdata(dev);
> > > struct zynq_gem_priv *priv = dev_get_priv(dev);
> > > - int node = dev_of_offset(dev);
> > > + struct ofnode_phandle_args phandle_args;
> > > const char *phy_mode;
> > >
> > > - pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
> > > + pdata->iobase = (phys_addr_t)dev_read_addr(dev);
> > > priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
> > > /* Hardcode for now */
> > > priv->phyaddr = -1;
> > >
> > > - priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob,
> node,
> > > - "phy-handle");
> > > - if (priv->phy_of_handle > 0)
> > > - priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
> > > - priv->phy_of_handle, "reg", -1);
> > > + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> > > + _args)) {
> > > + debug("phy-handle does not exist %s\n", dev->name);
> > > + return -ENOENT;
> > > + }
> > >
> > > - phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
> > > + priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
> > "reg", -1);
> > > + priv->phy_of_node = phandle_args.node;
> > > + phy_mode = dev_read_prop(dev, "phy-mode", NULL);
> >
> > I want to make sure we are in sync here. I plan to take Grygorii's series.
> >
> > Thanks!
>
> Thanks for informing. No problem, I will make changes as per Grygorii's
> series and will test it sometime this week.
I tested by applying both series on ZynqMP zcu102 board(it has ti phy) and its
working fine.
I also tested by modifying the zynq_gem to support live tree for which I will
be sending patch soon.
Grygorii,
You can add my tested-by to TI phy and zynq_gem patches in your series.
Tested-by: Siva Durga Prasad Paladugu
Thanks,
Siva
>
> Thanks,
> Siva
>
> >
> > > if (phy_mode)
> > > pdata->
[U-Boot] [UBOOT PATCH v4 5/5] arm: zynq: Add parallel NOR flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint OCM memory. This configuration
only has required parallel nor flash support.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v3:
- None, rebased on latest master
Changes from v2:
- None
Changes from v1:
- None
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-cse-nor.dts | 88 ++
configs/zynq_cse_nor_defconfig | 50
3 files changed, 139 insertions(+)
create mode 100644 arch/arm/dts/zynq-cse-nor.dts
create mode 100644 configs/zynq_cse_nor_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 834a19b..6785fef 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
zynq-cse-nand.dtb \
+ zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
zynq-minized.dtb \
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
new file mode 100644
index 000..ba6f9a1
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NOR board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NOR Board";
+ compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@fffc {
+ device_type = "memory";
+ reg = <0xFFFC 0x4>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+ ranges;
+
+ intc: interrupt-controller@f8f01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xF8F01000 0x1000>,
+ <0xF8F00100 0x100>;
+ };
+
+ slcr: slcr@f800 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF800 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ fclk-enable = <0xf>;
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", &q
[U-Boot] [UBOOT PATCH v4 3/5] arm: zynq: Dont define SDRAM_BASE and SDRAM_SIZE in .h
Remove the SDRAM_BASE nad SDRAM_SIZE as it can now get these details from DT. Signed-off-by: Siva Durga Prasad Paladugu --- Changes from v3: - None Changes from v2: - None Changes from v1: - Removed commit reference from description as per comment --- include/configs/zynq_cse.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index 2f5843f..adc02f0 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -41,7 +41,4 @@ #undef CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_MALLOC_LEN 0x1000 -#define CONFIG_SYS_SDRAM_BASE 0xfffc -#define CONFIG_SYS_SDRAM_SIZE 0x4 - #endif /* __CONFIG_ZYNQ_CSE_H */ -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [UBOOT PATCH v4 4/5] arm: zynq: Add Nand flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint of memory. This configuration
has only required nand flash support.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v3:
- Rebased on latest master
Changes from v2:
- None
Changes from v1:
- Update memory node as per comment
- Removed intc and fclk as per comment
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-cse-nand.dts | 80 +
configs/zynq_cse_nand_defconfig | 50 ++
3 files changed, 131 insertions(+)
create mode 100644 arch/arm/dts/zynq-cse-nand.dts
create mode 100644 configs/zynq_cse_nand_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9460230..834a19b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
+ zynq-cse-nand.dtb \
zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
zynq-minized.dtb \
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
new file mode 100644
index 000..9b1dd19
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NAND board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NAND Board";
+ compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ slcr: slcr@f800 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF800 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper",
+ "swdt", "dbg_trc", "dbg_apb";
+ reg = <0x100 0x100>;
+ };
+ };
+ };
+
+};
+
+ {
+ status = "okay";
+};
diff --git a/configs/zynq_cse_nand_defcon
[U-Boot] [UBOOT PATCH v4 2/5] lib: fdtdec: Rename routine fdtdec_setup_memory_size()
This patch renames the routine fdtdec_setup_memory_size()
to fdtdec_setup_mem_size_base() as it now fills the
mem base as well along with size.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v3:
- Separted the rename patch
---
arch/arm/mach-mvebu/arm64-common.c | 2 +-
board/emulation/qemu-arm/qemu-arm.c | 2 +-
board/renesas/alt/alt.c | 2 +-
board/renesas/blanche/blanche.c | 2 +-
board/renesas/draak/draak.c | 2 +-
board/renesas/eagle/eagle.c | 2 +-
board/renesas/gose/gose.c| 2 +-
board/renesas/koelsch/koelsch.c | 2 +-
board/renesas/lager/lager.c | 2 +-
board/renesas/porter/porter.c| 2 +-
board/renesas/salvator-x/salvator-x.c| 2 +-
board/renesas/silk/silk.c| 2 +-
board/renesas/stout/stout.c | 2 +-
board/renesas/ulcb/ulcb.c| 2 +-
board/st/stm32f429-discovery/stm32f429-discovery.c | 2 +-
board/st/stm32f429-evaluation/stm32f429-evaluation.c | 2 +-
board/st/stm32f469-discovery/stm32f469-discovery.c | 2 +-
board/st/stm32h743-disco/stm32h743-disco.c | 2 +-
board/st/stm32h743-eval/stm32h743-eval.c | 2 +-
board/xilinx/zynq/board.c| 2 +-
board/xilinx/zynqmp/zynqmp.c | 2 +-
board/xilinx/zynqmp_r5/board.c | 2 +-
include/fdtdec.h | 16 +---
lib/fdtdec.c | 2 +-
tools/patman/func_test.py| 2 +-
tools/patman/test/-cover-letter.patch| 2 +-
...orrect-cast-for-sandbox-in-fdtdec_setup_memory_.patch | 4 ++--
tools/patman/test/test01.txt | 2 +-
28 files changed, 37 insertions(+), 35 deletions(-)
diff --git a/arch/arm/mach-mvebu/arm64-common.c
b/arch/arm/mach-mvebu/arm64-common.c
index d3ea9e6..f47273f 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -54,7 +54,7 @@ int dram_init_banksize(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
diff --git a/board/emulation/qemu-arm/qemu-arm.c
b/board/emulation/qemu-arm/qemu-arm.c
index 085cbbe..1f5a33d 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -47,7 +47,7 @@ int board_init(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 86e9d24..b18ab7c 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -78,7 +78,7 @@ int board_init(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index 7d48d0f..f5ada6e 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c
@@ -339,7 +339,7 @@ int board_eth_init(bd_t *bis)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index f804fae..852fdda 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -96,7 +96,7 @@ int board_init(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c
index 7b89c10..9317410 100644
--- a/board/renesas/eagle/eagle.c
+++ b/board/renesas/eagle/eagle.c
@@ -74,7 +74,7 @@ int board_init(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index 96ac29d..282381e 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c
@@ -83,7 +83,7 @@ int board_init(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index b6688a2..52f37c9 100644
--- a/board
[U-Boot] [UBOOT PATCH v4 1/5] lib: fdtdec: Update ram_base to store ram start adddress
This patch updates the ram_base to store the start address of
the first bank DRAM and the use this ram_base to calculate ram_top
properly. This patch fixes the erroneous calculation of ram_top
incase of non zero ram start address.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
Changes from v3:
- Rebased on latest master and used
available ram_base
Changes from v2:
- Used new varibale ram_start
- Rename fdtdec_setup_memory_size
Changes from v1:
- None
---
common/board_f.c | 4 ++--
lib/fdtdec.c | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index e943347..88d7700 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -281,9 +281,9 @@ static int setup_dest_addr(void)
gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
#endif
#ifdef CONFIG_SYS_SDRAM_BASE
- gd->ram_top = CONFIG_SYS_SDRAM_BASE;
+ gd->ram_base = CONFIG_SYS_SDRAM_BASE;
#endif
- gd->ram_top += get_effective_memsize();
+ gd->ram_top = gd->ram_base + get_effective_memsize();
gd->ram_top = board_get_usable_ram_top(gd->mon_len);
gd->relocaddr = gd->ram_top;
debug("Ram top: %08lX\n", (ulong)gd->ram_top);
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 1b0c430..66dff0f 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1173,6 +1173,7 @@ int fdtdec_setup_memory_size(void)
}
gd->ram_size = (phys_size_t)(res.end - res.start + 1);
+ gd->ram_base = (unsigned long)res.start;
debug("%s: Initial DRAM size %llx\n", __func__,
(unsigned long long)gd->ram_size);
--
2.7.4
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Re: [U-Boot] [PATCH 3/3] net: zynq_gem: convert to use livetree
Hi Joe,
> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@ni.com]
> Sent: Thursday, July 12, 2018 12:26 AM
> To: Siva Durga Prasad Paladugu ; Grygorii Strashko
>
> Cc: u-boot ; Joe Hershberger
> ; Michal Simek ; Vipul
> Kumar
> Subject: Re: [U-Boot] [PATCH 3/3] net: zynq_gem: convert to use livetree
>
> Hi Siva,
>
> On Fri, Jul 6, 2018 at 5:10 AM, Siva Durga Prasad Paladugu
> wrote:
> > This patch updates the zynq gem driver to support livetree.
> >
> > Signed-off-by: Siva Durga Prasad Paladugu
> >
> > Signed-off-by: Vipul Kumar
> > ---
> > drivers/net/zynq_gem.c | 29 ++---
> > 1 file changed, 14 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index
> > a817f2e..b9858e4 100644
> > --- a/drivers/net/zynq_gem.c
> > +++ b/drivers/net/zynq_gem.c
> > @@ -178,7 +178,7 @@ struct zynq_gem_priv {
> > struct zynq_gem_regs *iobase;
> > phy_interface_t interface;
> > struct phy_device *phydev;
> > - int phy_of_handle;
> > + ofnode phy_of_node;
> > struct mii_dev *bus;
> > struct clk clk;
> > u32 max_speed;
> > @@ -349,8 +349,7 @@ static int zynq_phy_init(struct udevice *dev)
> >
> > priv->phydev->advertising = priv->phydev->supported;
> >
> > - if (priv->phy_of_handle > 0)
> > - dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
> > + priv->phydev->dev->node = priv->phy_of_node;
> >
> > return phy_config(priv->phydev); } @@ -693,21 +692,23 @@
> > static int zynq_gem_ofdata_to_platdata(struct udevice *dev) {
> > struct eth_pdata *pdata = dev_get_platdata(dev);
> > struct zynq_gem_priv *priv = dev_get_priv(dev);
> > - int node = dev_of_offset(dev);
> > + struct ofnode_phandle_args phandle_args;
> > const char *phy_mode;
> >
> > - pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
> > + pdata->iobase = (phys_addr_t)dev_read_addr(dev);
> > priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
> > /* Hardcode for now */
> > priv->phyaddr = -1;
> >
> > - priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
> > - "phy-handle");
> > - if (priv->phy_of_handle > 0)
> > - priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
> > - priv->phy_of_handle, "reg", -1);
> > + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> > + _args)) {
> > + debug("phy-handle does not exist %s\n", dev->name);
> > + return -ENOENT;
> > + }
> >
> > - phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
> > + priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
> "reg", -1);
> > + priv->phy_of_node = phandle_args.node;
> > + phy_mode = dev_read_prop(dev, "phy-mode", NULL);
>
> I want to make sure we are in sync here. I plan to take Grygorii's series.
>
> Thanks!
Thanks for informing. No problem, I will make changes as per Grygorii's series
and will test it sometime this week.
Thanks,
Siva
>
> > if (phy_mode)
> > pdata->phy_interface =
> phy_get_interface_by_name(phy_mode);
> > if (pdata->phy_interface == -1) { @@ -716,10 +717,8 @@ static
> > int zynq_gem_ofdata_to_platdata(struct udevice *dev)
> > }
> > priv->interface = pdata->phy_interface;
> >
> > - priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv-
> >phy_of_handle,
> > - "max-speed", SPEED_1000);
> > - priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
> > - "is-internal-pcspma");
> > + priv->max_speed = dev_read_u32_default(dev, "max-speed",
> SPEED_1000);
> > + priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
> >
> > printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv-
> >iobase,
> >priv->phyaddr,
> > phy_string_for_interface(priv->interface));
> > --
> > 2.7.4
> >
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > https://lists.denx.de/listinfo/u-boot
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Re: [U-Boot] [PATCH v7 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
Hi Jagan, > -Original Message- > From: Jagan Teki [mailto:jagannadh.t...@gmail.com] > Sent: Monday, July 16, 2018 2:00 PM > To: Siva Durga Prasad Paladugu > Cc: U-Boot Mailing List ; Michal Simek > > Subject: Re: [U-Boot] [PATCH v7 1/2] spi: zynqmp_gqspi: Add support for > ZynqMP qspi driver > > On Wed, Jul 4, 2018 at 5:31 PM, Siva Durga Prasad Paladugu > wrote: > > This patch adds qspi driver support for ZynqMP SoC. This driver is > > responsible for communicating with qspi flash devices. > > > > Signed-off-by: Siva Durga Prasad Paladugu > > > > --- > > Changes for v7: > > - Removed reading of mode, clock phase and polarity from > ofdata_to_platdata > > as drivercan get from spi-uclass if required > > Thanks for your efforts. > > > > > Changes for v6: > > - Removed spi_flash.h inclusion and other unused macros > > - Fixed coding style comments > > - Removed tx_rx_mode in plat and removed preprobe routine. > > - Used proper error codes > > > > Changed for v5: > > - Removed zynqm_gqspi.h file which was added > > by mistake. > > > > Changes for v4: > > - Moved macro definitions back to .c > > - Removed last_cmd and flash command checks in driver > > - Used macros and GENMASK as per comments > > - Removed debugs wherever commented. > > - Modified set_mode routine as per comment > > > > Changes for v3: > > - Renamed all macros, functions, files and configs as per comment > > - Used wait_for_bit wherever required > > - Removed unnecessary header inclusion > > > > Changes for v2: > > - Rebased on top of latest master > > - Moved macro definitions to .h file as per comment > > - Fixed magic values with macros as per comment > > --- > > drivers/spi/Kconfig| 7 + > > drivers/spi/Makefile | 1 + > > drivers/spi/zynqmp_gqspi.c | 734 > > + > > 3 files changed, 742 insertions(+) > > create mode 100644 drivers/spi/zynqmp_gqspi.c > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index > > 3532c2a..c3c424e 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -223,6 +223,13 @@ config ZYNQ_QSPI > > Zynq QSPI IP core. This IP is used to connect the flash in > > 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. > > > > +config ZYNQMP_GQSPI > > + bool "Configure ZynqMP Generic QSPI" > > + depends on ARCH_ZYNQMP > > + help > > + This option is used to enable ZynqMP QSPI controller driver which > > + is used to communicate with qspi flash devices. > > + > > endif # if DM_SPI > > > > config SOFT_SPI > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > > 5a2c00e..2187633 100644 > > --- a/drivers/spi/Makefile > > +++ b/drivers/spi/Makefile > > @@ -51,3 +51,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o > > obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o > > obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o > > obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o > > +obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o > > diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c > > new file mode 100644 index 000..665f98e > > --- /dev/null > > +++ b/drivers/spi/zynqmp_gqspi.c > > @@ -0,0 +1,734 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * (C) Copyright 2018 Xilinx > > + * > > + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode > > +only) */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) > > +#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) > > +#define GQSPI_CONFIG_DMA_MODE (2 << 30) > > +#define GQSPI_CONFIG_CPHA_MASK BIT(2) > > +#define GQSPI_CONFIG_CPOL_MASK BIT(1) > > + > > +/* QSPI MIO's count for different connection topologies */ > > +#define GQSPI_MIO_NUM_QSPI06 > > +#define GQSPI_MIO_NUM_QSPI15 > > +#define GQSPI_MIO_NUM_QSPI1_CS 1 > > These were not related to spi driver, let me know if you OK to remove while > applying? Yes, please remove these (GQSPI_MIO_NUM_*) if you can , they don’t need any more. Thanks, DP > > All fine to me except the above, so > > Reviewed-by: Jagan Teki ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] net: phy: ti: Modify to support livetree
Hi,
> -Original Message-
> From: Siva Durga Prasad Paladugu
> Sent: Tuesday, July 10, 2018 9:32 AM
> To: Grygorii Strashko ; u-boot@lists.denx.de
> Cc: joe.hershber...@ni.com; Michal Simek
> Subject: RE: [U-Boot] [PATCH 1/3] net: phy: ti: Modify to support livetree
>
> Hi,
>
> > -Original Message-
> > From: Grygorii Strashko [mailto:grygorii.stras...@ti.com]
> > Sent: Monday, July 09, 2018 10:51 PM
> > To: Siva Durga Prasad Paladugu ; u-
> > b...@lists.denx.de
> > Cc: joe.hershber...@ni.com; Michal Simek
> > Subject: Re: [U-Boot] [PATCH 1/3] net: phy: ti: Modify to support
> > livetree
> >
> >
> >
> > On 07/06/2018 05:10 AM, Siva Durga Prasad Paladugu wrote:
> > > This patch adds support for livetree by using dev_.. calls instead
> > > of fdtdec_..
> > >
> > > Signed-off-by: Siva Durga Prasad Paladugu
> > >
> > > ---
> > > drivers/net/phy/ti.c | 16 +++-
> > > 1 file changed, 7 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index
> > > 8f3ed8a..945d9e9 100644
> > > --- a/drivers/net/phy/ti.c
> > > +++ b/drivers/net/phy/ti.c
> > > @@ -173,24 +173,22 @@ static int dp83867_of_init(struct phy_device
> > *phydev)
> > > {
> > > struct dp83867_private *dp83867 = phydev->priv;
> > > struct udevice *dev = phydev->dev;
> > > - int node = dev_of_offset(dev);
> > > const void *fdt = gd->fdt_blob;
> > >
> > > - if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
> > > + if (dev_read_bool(dev, "ti,max-output-impedance"))
> > > dp83867->io_impedance =
> > DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
> > > - else if (fdtdec_get_bool(fdt, node, "ti,min-output-impedance"))
> > > + else if (dev_read_bool(dev, "ti,min-output-impedance"))
> > > dp83867->io_impedance =
> > DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
> > > else
> > > dp83867->io_impedance = -EINVAL;
> > >
> > > - dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob,
> > dev_of_offset(dev),
> > > - "ti,rx-internal-delay", -1);
> > > + dp83867->rx_id_delay = dev_read_u32_default(dev, "ti,rx-internal-
> > delay",
> > > + -1);
> > >
> > > - dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob,
> > dev_of_offset(dev),
> > > - "ti,tx-internal-delay", -1);
> > > + dp83867->tx_id_delay = dev_read_u32_default(dev, "ti,tx-internal-
> > delay",
> > > + -1);
> > >
> > > - dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob,
> > dev_of_offset(dev),
> > > - "ti,fifo-depth", -1);
> > > + dp83867->fifo_depth = dev_read_u32_default(dev, "ti,fifo-depth",
> > > +-1);
> > >
> > > return 0;
> > > }
> > >
> >
> > NACK. Pls, check
> > https://patchwork.ozlabs.org/cover/936370/
> > and
> > https://patchwork.ozlabs.org/cover/936380/
> >
> > any comments, tested-by are very welcome.
>
> Do you mean to say that this patch has to be rebased and tested on the top
> of your patch.
Oops, I missed your second thread(936380) and replied.
Please ignore my last mail.
I will review, test with your series and let you know if any.
Thanks,
Siva
>
> Thanks,
> Siva
>
> >
> > --
> > regards,
> > -grygorii
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Re: [U-Boot] [PATCH 1/3] net: phy: ti: Modify to support livetree
Hi,
> -Original Message-
> From: Grygorii Strashko [mailto:grygorii.stras...@ti.com]
> Sent: Monday, July 09, 2018 10:51 PM
> To: Siva Durga Prasad Paladugu ; u-
> b...@lists.denx.de
> Cc: joe.hershber...@ni.com; Michal Simek
> Subject: Re: [U-Boot] [PATCH 1/3] net: phy: ti: Modify to support livetree
>
>
>
> On 07/06/2018 05:10 AM, Siva Durga Prasad Paladugu wrote:
> > This patch adds support for livetree by using dev_.. calls instead of
> > fdtdec_..
> >
> > Signed-off-by: Siva Durga Prasad Paladugu
> >
> > ---
> > drivers/net/phy/ti.c | 16 +++-
> > 1 file changed, 7 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index
> > 8f3ed8a..945d9e9 100644
> > --- a/drivers/net/phy/ti.c
> > +++ b/drivers/net/phy/ti.c
> > @@ -173,24 +173,22 @@ static int dp83867_of_init(struct phy_device
> *phydev)
> > {
> > struct dp83867_private *dp83867 = phydev->priv;
> > struct udevice *dev = phydev->dev;
> > - int node = dev_of_offset(dev);
> > const void *fdt = gd->fdt_blob;
> >
> > - if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
> > + if (dev_read_bool(dev, "ti,max-output-impedance"))
> > dp83867->io_impedance =
> DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
> > - else if (fdtdec_get_bool(fdt, node, "ti,min-output-impedance"))
> > + else if (dev_read_bool(dev, "ti,min-output-impedance"))
> > dp83867->io_impedance =
> DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
> > else
> > dp83867->io_impedance = -EINVAL;
> >
> > - dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob,
> dev_of_offset(dev),
> > -"ti,rx-internal-delay", -1);
> > + dp83867->rx_id_delay = dev_read_u32_default(dev, "ti,rx-internal-
> delay",
> > + -1);
> >
> > - dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob,
> dev_of_offset(dev),
> > -"ti,tx-internal-delay", -1);
> > + dp83867->tx_id_delay = dev_read_u32_default(dev, "ti,tx-internal-
> delay",
> > + -1);
> >
> > - dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob,
> dev_of_offset(dev),
> > -"ti,fifo-depth", -1);
> > + dp83867->fifo_depth = dev_read_u32_default(dev, "ti,fifo-depth",
> > +-1);
> >
> > return 0;
> > }
> >
>
> NACK. Pls, check
> https://patchwork.ozlabs.org/cover/936370/
> and
> https://patchwork.ozlabs.org/cover/936380/
>
> any comments, tested-by are very welcome.
Do you mean to say that this patch has to be rebased and tested on the top of
your patch.
Thanks,
Siva
>
> --
> regards,
> -grygorii
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[U-Boot] [PATCH 3/3] net: zynq_gem: convert to use livetree
This patch updates the zynq gem driver to support
livetree.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Vipul Kumar
---
drivers/net/zynq_gem.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index a817f2e..b9858e4 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -178,7 +178,7 @@ struct zynq_gem_priv {
struct zynq_gem_regs *iobase;
phy_interface_t interface;
struct phy_device *phydev;
- int phy_of_handle;
+ ofnode phy_of_node;
struct mii_dev *bus;
struct clk clk;
u32 max_speed;
@@ -349,8 +349,7 @@ static int zynq_phy_init(struct udevice *dev)
priv->phydev->advertising = priv->phydev->supported;
- if (priv->phy_of_handle > 0)
- dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
+ priv->phydev->dev->node = priv->phy_of_node;
return phy_config(priv->phydev);
}
@@ -693,21 +692,23 @@ static int zynq_gem_ofdata_to_platdata(struct udevice
*dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
- int node = dev_of_offset(dev);
+ struct ofnode_phandle_args phandle_args;
const char *phy_mode;
- pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
+ pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->phyaddr = -1;
- priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
- "phy-handle");
- if (priv->phy_of_handle > 0)
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
- priv->phy_of_handle, "reg", -1);
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ _args)) {
+ debug("phy-handle does not exist %s\n", dev->name);
+ return -ENOENT;
+ }
- phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
+ priv->phyaddr = ofnode_read_u32_default(phandle_args.node, "reg", -1);
+ priv->phy_of_node = phandle_args.node;
+ phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
@@ -716,10 +717,8 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
}
priv->interface = pdata->phy_interface;
- priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv->phy_of_handle,
- "max-speed", SPEED_1000);
- priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
- "is-internal-pcspma");
+ priv->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
+ priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
--
2.7.4
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[U-Boot] [PATCH 1/3] net: phy: ti: Modify to support livetree
This patch adds support for livetree by using
dev_.. calls instead of fdtdec_..
Signed-off-by: Siva Durga Prasad Paladugu
---
drivers/net/phy/ti.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 8f3ed8a..945d9e9 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -173,24 +173,22 @@ static int dp83867_of_init(struct phy_device *phydev)
{
struct dp83867_private *dp83867 = phydev->priv;
struct udevice *dev = phydev->dev;
- int node = dev_of_offset(dev);
const void *fdt = gd->fdt_blob;
- if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
+ if (dev_read_bool(dev, "ti,max-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
- else if (fdtdec_get_bool(fdt, node, "ti,min-output-impedance"))
+ else if (dev_read_bool(dev, "ti,min-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
else
dp83867->io_impedance = -EINVAL;
- dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
-"ti,rx-internal-delay", -1);
+ dp83867->rx_id_delay = dev_read_u32_default(dev, "ti,rx-internal-delay",
+ -1);
- dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
-"ti,tx-internal-delay", -1);
+ dp83867->tx_id_delay = dev_read_u32_default(dev, "ti,tx-internal-delay",
+ -1);
- dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
-"ti,fifo-depth", -1);
+ dp83867->fifo_depth = dev_read_u32_default(dev, "ti,fifo-depth", -1);
return 0;
}
--
2.7.4
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[U-Boot] [PATCH 2/3] net: phy: xilinx_phy: Add suuport for livetree
This patch adds support for livetree by using dev_..
calls instead of fdtdec_.. .
Signed-off-by: Siva Durga Prasad Paladugu
---
drivers/net/phy/xilinx_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c
index 004cfcf..2e2a5cd 100644
--- a/drivers/net/phy/xilinx_phy.c
+++ b/drivers/net/phy/xilinx_phy.c
@@ -103,8 +103,8 @@ static int xilinxphy_of_init(struct phy_device *phydev)
u32 phytype;
debug("%s\n", __func__);
- phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev),
-"xlnx,phy-type", -1);
+ phytype = dev_read_u32_default(phydev->dev,
+ "xlnx,phy-type", -1);
if (phytype == XAE_PHY_TYPE_1000BASE_X)
phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
--
2.7.4
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[U-Boot] [PATCH v7 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
This patch adds qspi driver support for ZynqMP SoC. This driver is responsible for communicating with qspi flash devices. Signed-off-by: Siva Durga Prasad Paladugu --- Changes for v7: - Removed reading of mode, clock phase and polarity from ofdata_to_platdata as drivercan get from spi-uclass if required Changes for v6: - Removed spi_flash.h inclusion and other unused macros - Fixed coding style comments - Removed tx_rx_mode in plat and removed preprobe routine. - Used proper error codes Changed for v5: - Removed zynqm_gqspi.h file which was added by mistake. Changes for v4: - Moved macro definitions back to .c - Removed last_cmd and flash command checks in driver - Used macros and GENMASK as per comments - Removed debugs wherever commented. - Modified set_mode routine as per comment Changes for v3: - Renamed all macros, functions, files and configs as per comment - Used wait_for_bit wherever required - Removed unnecessary header inclusion Changes for v2: - Rebased on top of latest master - Moved macro definitions to .h file as per comment - Fixed magic values with macros as per comment --- drivers/spi/Kconfig| 7 + drivers/spi/Makefile | 1 + drivers/spi/zynqmp_gqspi.c | 734 + 3 files changed, 742 insertions(+) create mode 100644 drivers/spi/zynqmp_gqspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3532c2a..c3c424e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -223,6 +223,13 @@ config ZYNQ_QSPI Zynq QSPI IP core. This IP is used to connect the flash in 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. +config ZYNQMP_GQSPI + bool "Configure ZynqMP Generic QSPI" + depends on ARCH_ZYNQMP + help + This option is used to enable ZynqMP QSPI controller driver which + is used to communicate with qspi flash devices. + endif # if DM_SPI config SOFT_SPI diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 5a2c00e..2187633 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o +obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c new file mode 100644 index 000..665f98e --- /dev/null +++ b/drivers/spi/zynqmp_gqspi.c @@ -0,0 +1,734 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 Xilinx + * + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) +#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) +#define GQSPI_CONFIG_DMA_MODE (2 << 30) +#define GQSPI_CONFIG_CPHA_MASK BIT(2) +#define GQSPI_CONFIG_CPOL_MASK BIT(1) + +/* QSPI MIO's count for different connection topologies */ +#define GQSPI_MIO_NUM_QSPI06 +#define GQSPI_MIO_NUM_QSPI15 +#define GQSPI_MIO_NUM_QSPI1_CS 1 + +/* + * QSPI Interrupt Registers bit Masks + * + * All the four interrupt registers (Status/Mask/Enable/Disable) have the same + * bit definitions. + */ +#define GQSPI_IXR_TXNFULL_MASK 0x0004 /* QSPI TX FIFO Overflow */ +#define GQSPI_IXR_TXFULL_MASK 0x0008 /* QSPI TX FIFO is full */ +#define GQSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX FIFO Not Empty */ +#define GQSPI_IXR_GFEMTY_MASK 0x0080 /* QSPI Generic FIFO Empty */ +#define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \ +GQSPI_IXR_RXNEMTY_MASK) + +/* + * QSPI Enable Register bit Masks + * + * This register is used to enable or disable the QSPI controller + */ +#define GQSPI_ENABLE_ENABLE_MASK 0x0001 /* QSPI Enable Bit Mask */ + +#define GQSPI_GFIFO_LOW_BUSBIT(14) +#define GQSPI_GFIFO_CS_LOWER BIT(12) +#define GQSPI_GFIFO_UP_BUS BIT(15) +#define GQSPI_GFIFO_CS_UPPER BIT(13) +#define GQSPI_SPI_MODE_QSPI(3 << 10) +#define GQSPI_SPI_MODE_SPI BIT(10) +#define GQSPI_SPI_MODE_DUAL_SPI(2 << 10) +#define GQSPI_IMD_DATA_CS_ASSERT 5 +#define GQSPI_IMD_DATA_CS_DEASSERT 5 +#define GQSPI_GFIFO_TX BIT(16) +#define GQSPI_GFIFO_RX BIT(17) +#define GQSPI_GFIFO_STRIPE_MASKBIT(18) +#define GQSPI_GFIFO_IMD_MASK 0xFF +#define GQSPI_GFIFO_EXP_MASK BIT(9) +#define GQSPI_GFIFO_DATA_XFR_MASK BIT(8) +#define GQSPI_STRT_GEN_FIFOBIT(28) +#define GQSPI_GEN_FIFO_STRT_MODBIT(29) +#define GQSPI_GFIFO_WP_HOLDBIT(19) +#define GQSPI_BAUD_DIV_MASK(7 << 3) +#def
[U-Boot] [PATCH v7 2/2] zynqmp: zcu102: Add qspi driver support for ZynqMP zcu102 boards
This patch adds qspi driver support for all ZynqMP ZCU102
boards.
Signed-off-by: Siva Durga Prasad Paladugu
Acked-by: Michal Simek
---
Changes for v7:
- Added "spi-flash" to compatible strings.
Changes for v6:
- None
Changes for v5:
- None
Changes for v4:
- None
Changes for v3:
- Changed as per latest changes in 1/2
Changes for v2:
- Rebased on top of latest master and enabled qspi for
all zcu102 boards.
---
arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +-
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 5 +
configs/xilinx_zynqmp_zcu102_revA_defconfig | 5 +
configs/xilinx_zynqmp_zcu102_revB_defconfig | 5 +
4 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index ddc3fba..ac7035f 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -534,7 +534,7 @@
status = "okay";
is-dual = <1>;
flash@0 {
- compatible = "m25p80"; /* 32MB */
+ compatible = "m25p80", "spi-flash"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 49a14d8..da53aa4 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
@@ -69,6 +70,7 @@ CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -90,6 +92,9 @@ CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig
b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index 05dad41..60e1269 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -35,6 +35,7 @@ CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
@@ -66,6 +67,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -87,6 +89,9 @@ CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig
b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index b3711b4..fa2804d 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -35,6 +35,7 @@ CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
@@ -66,6 +67,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -87,6 +89,9 @@ CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
--
2.7.4
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[U-Boot] [PATCH v6 2/2] zynqmp: zcu102: Add qspi driver support for ZynqMP zcu102 boards
This patch adds qspi driver support for all ZynqMP ZCU102 boards. Signed-off-by: Siva Durga Prasad Paladugu Acked-by: Michal Simek --- Changes for v6: - None Changes for v5: - None Changes for v4: - None Changes for v3: - Changed as per latest changes in 1/2 Changes for v2: - Rebased on top of latest master and enabled qspi for all zcu102 boards. --- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 5 + configs/xilinx_zynqmp_zcu102_revA_defconfig | 5 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 5 + 3 files changed, 15 insertions(+) diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 49a14d8..da53aa4 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -69,6 +70,7 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -90,6 +92,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 05dad41..60e1269 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -66,6 +67,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -87,6 +89,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index b3711b4..fa2804d 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -66,6 +67,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -87,6 +89,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
This patch adds qspi driver support for ZynqMP SoC. This driver is responsible for communicating with qspi flash devices. Signed-off-by: Siva Durga Prasad Paladugu --- Changes for v6: - Removed spi_flash.h inclusion and other unused macros - Fixed coding style comments - Removed tx_rx_mode in plat and removed preprobe routine. - Used proper error codes Changed for v5: - Removed zynqm_gqspi.h file which was added by mistake. Changes for v4: - Moved macro definitions back to .c - Removed last_cmd and flash command checks in driver - Used macros and GENMASK as per comments - Removed debugs wherever commented. - Modified set_mode routine as per comment Changes for v3: - Renamed all macros, functions, files and configs as per comment - Used wait_for_bit wherever required - Removed unnecessary header inclusion Changes for v2: - Rebased on top of latest master - Moved macro definitions to .h file as per comment - Fixed magic values with macros as per comment --- drivers/spi/Kconfig| 7 + drivers/spi/Makefile | 1 + drivers/spi/zynqmp_gqspi.c | 774 + 3 files changed, 782 insertions(+) create mode 100644 drivers/spi/zynqmp_gqspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3532c2a..c3c424e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -223,6 +223,13 @@ config ZYNQ_QSPI Zynq QSPI IP core. This IP is used to connect the flash in 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. +config ZYNQMP_GQSPI + bool "Configure ZynqMP Generic QSPI" + depends on ARCH_ZYNQMP + help + This option is used to enable ZynqMP QSPI controller driver which + is used to communicate with qspi flash devices. + endif # if DM_SPI config SOFT_SPI diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 5a2c00e..2187633 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o +obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c new file mode 100644 index 000..c224522 --- /dev/null +++ b/drivers/spi/zynqmp_gqspi.c @@ -0,0 +1,774 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 Xilinx + * + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) +#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) +#define GQSPI_CONFIG_DMA_MODE (2 << 30) +#define GQSPI_CONFIG_CPHA_MASK BIT(2) +#define GQSPI_CONFIG_CPOL_MASK BIT(1) + +/* QSPI MIO's count for different connection topologies */ +#define GQSPI_MIO_NUM_QSPI06 +#define GQSPI_MIO_NUM_QSPI15 +#define GQSPI_MIO_NUM_QSPI1_CS 1 + +/* + * QSPI Interrupt Registers bit Masks + * + * All the four interrupt registers (Status/Mask/Enable/Disable) have the same + * bit definitions. + */ +#define GQSPI_IXR_TXNFULL_MASK 0x0004 /* QSPI TX FIFO Overflow */ +#define GQSPI_IXR_TXFULL_MASK 0x0008 /* QSPI TX FIFO is full */ +#define GQSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX FIFO Not Empty */ +#define GQSPI_IXR_GFEMTY_MASK 0x0080 /* QSPI Generic FIFO Empty */ +#define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \ +GQSPI_IXR_RXNEMTY_MASK) + +/* + * QSPI Enable Register bit Masks + * + * This register is used to enable or disable the QSPI controller + */ +#define GQSPI_ENABLE_ENABLE_MASK 0x0001 /* QSPI Enable Bit Mask */ + +#define GQSPI_GFIFO_LOW_BUSBIT(14) +#define GQSPI_GFIFO_CS_LOWER BIT(12) +#define GQSPI_GFIFO_UP_BUS BIT(15) +#define GQSPI_GFIFO_CS_UPPER BIT(13) +#define GQSPI_SPI_MODE_QSPI(3 << 10) +#define GQSPI_SPI_MODE_SPI BIT(10) +#define GQSPI_SPI_MODE_DUAL_SPI(2 << 10) +#define GQSPI_IMD_DATA_CS_ASSERT 5 +#define GQSPI_IMD_DATA_CS_DEASSERT 5 +#define GQSPI_GFIFO_TX BIT(16) +#define GQSPI_GFIFO_RX BIT(17) +#define GQSPI_GFIFO_STRIPE_MASKBIT(18) +#define GQSPI_GFIFO_IMD_MASK 0xFF +#define GQSPI_GFIFO_EXP_MASK BIT(9) +#define GQSPI_GFIFO_DATA_XFR_MASK BIT(8) +#define GQSPI_STRT_GEN_FIFOBIT(28) +#define GQSPI_GEN_FIFO_STRT_MODBIT(29) +#define GQSPI_GFIFO_WP_HOLDBIT(19) +#define GQSPI_BAUD_DIV_MASK(7 << 3) +#define GQSPI_DFLT_BAUD_RATE_DIV BIT(3) +#define GQSPI_GFIFO_ALL_INT_MASK 0xFBE +#define GQSPI_DMA_DST_I_STS_DONE BIT(1) +#de
Re: [U-Boot] [PATCH v5 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
Hi Jagan, > -Original Message- > From: Jagan Teki [mailto:ja...@amarulasolutions.com] > Sent: Wednesday, June 27, 2018 12:52 PM > To: Siva Durga Prasad Paladugu > Cc: U-Boot-Denx ; Jagan Teki > ; Michal Simek > Subject: Re: [U-Boot] [PATCH v5 1/2] spi: zynqmp_gqspi: Add support for > ZynqMP qspi driver > > On Tue, Jun 26, 2018 at 3:07 PM, Siva Durga Prasad Paladugu > wrote: > > This patch adds qspi driver support for ZynqMP SoC. This driver is > > responsible for communicating with qspi flash devices. > > > > Signed-off-by: Siva Durga Prasad Paladugu > > > > --- > > Changed for v5: > > - Removed zynqm_gqspi.h file which was added > > by mistake. > > > > Changes for v4: > > - Moved macro definitions back to .c > > - Removed last_cmd and flash command checks in driver > > - Used macros and GENMASK as per comments > > - Removed debugs wherever commented. > > - Modified set_mode routine as per comment > > > > Changes for v3: > > - Renamed all macros, functions, files and configs as per comment > > - Used wait_for_bit wherever required > > - Removed unnecessary header inclusion > > > > Changes for v2: > > - Rebased on top of latest master > > - Moved macro definitions to .h file as per comment > > - Fixed magic values with macros as per comment > > --- > > drivers/spi/Kconfig| 7 + > > drivers/spi/Makefile | 1 + > > drivers/spi/zynqmp_gqspi.c | 794 > > + > > 3 files changed, 802 insertions(+) > > create mode 100644 drivers/spi/zynqmp_gqspi.c > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index > > 3532c2a..c3c424e 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -223,6 +223,13 @@ config ZYNQ_QSPI > > Zynq QSPI IP core. This IP is used to connect the flash in > > 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. > > > > +config ZYNQMP_GQSPI > > + bool "Configure ZynqMP Generic QSPI" > > + depends on ARCH_ZYNQMP > > + help > > + This option is used to enable ZynqMP QSPI controller driver which > > + is used to communicate with qspi flash devices. > > + > > endif # if DM_SPI > > > > config SOFT_SPI > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > > 5a2c00e..2187633 100644 > > --- a/drivers/spi/Makefile > > +++ b/drivers/spi/Makefile > > @@ -51,3 +51,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o > > obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o > > obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o > > obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o > > +obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o > > diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c > > new file mode 100644 index 000..9a04839 > > --- /dev/null > > +++ b/drivers/spi/zynqmp_gqspi.c > > @@ -0,0 +1,794 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * (C) Copyright 2018 Xilinx > > + * > > + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode > > +only) */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > remove this header. Yes can be removed now > > > +#include > > +#include > > + > > +#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) > > +#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) > > +#define GQSPI_CONFIG_DMA_MODE (2 << 30) #define > > +GQSPI_CONFIG_CPHA_MASK BIT(2) #define > GQSPI_CONFIG_CPOL_MASK BIT(1) > > + > > +/* QSPI MIO's count for different connection topologies */ > > +#define GQSPI_MIO_NUM_QSPI06 > > +#define GQSPI_MIO_NUM_QSPI15 > > +#define GQSPI_MIO_NUM_QSPI1_CS 1 > > + > > +/* > > + * QSPI Interrupt Registers bit Masks > > + * > > + * All the four interrupt registers (Status/Mask/Enable/Disable) have > > +the same > > + * bit definitions. > > + */ > > +#define GQSPI_IXR_TXNFULL_MASK 0x0004 /* QSPI TX FIFO > Overflow */ > > +#define GQSPI_IXR_TXFULL_MASK 0x0008 /* QSPI TX FIFO is full > */ > > +#define GQSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX FIFO Not > Empty > > +*/ #define GQSPI_IXR_GFEMTY_MASK 0x0080 /* QSPI Generic > FIFO Empty */ > > +#define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \ > > +
[U-Boot] [PATCH v5] xilinx: zynq: Add support to secure images
This patch basically adds two new commands for loadig secure images. 1. zynq rsa adds support to load secure image which can be both authenticated or encrypted or both authenticated and encrypted image in xilinx bootimage(BOOT.bin) format. 2. zynq aes command adds support to decrypt and load encrypted image back to DDR as per destination address. The image has to be encrypted using xilinx bootgen tool and to get only the encrypted image from tool use -split option while invoking bootgen. Signed-off-by: Siva Durga Prasad Paladugu --- Changes from v4: - Moved license to top of file as per comment - Removed unused variable ppkexp - Used void * for buf, added check for buf allocation and freeing buf - Fixed coding style comments and fsbl_len usage Changes from v3: - Removed aesload and aesloadp as encrypted bitstream load is under duscussion and hence removed from this patch. Will work on it as a separate patch once discussion finalized. _ Fixed coding style comments Changes from v2: - Created separate commands for zynq aesload and aesloadp as per comment - Fixed all other coding style comments Changes from v1: - Defined two config synbols for RSA and AES separately and used them wherever required. - Used U_BOOT_CMD_KENT as per comment - Cleared DEVCFG_CTRL_PCAP_RATE_EN_MASK once decryption is done. Changes from RFC: - Moved zynqaes to board/xilinx/zynq/cmds.c and renamed as "zynq aes". - Moved boot image parsing code to a separate file. - Squashed in to a single patch. - Fixed coding style comments. --- arch/arm/Kconfig | 1 + arch/arm/mach-zynq/include/mach/hardware.h | 1 + board/xilinx/zynq/Kconfig | 33 ++ board/xilinx/zynq/Makefile | 5 + board/xilinx/zynq/bootimg.c| 143 board/xilinx/zynq/cmds.c | 513 + drivers/fpga/zynqpl.c | 45 +++ include/u-boot/rsa-mod-exp.h | 4 + include/zynq_bootimg.h | 33 ++ include/zynqpl.h | 4 + lib/rsa/rsa-mod-exp.c | 51 +++ 11 files changed, 833 insertions(+) create mode 100644 board/xilinx/zynq/Kconfig create mode 100644 board/xilinx/zynq/bootimg.c create mode 100644 board/xilinx/zynq/cmds.c create mode 100644 include/zynq_bootimg.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3e05f79..e78e1a4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1428,6 +1428,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" +source "board/xilinx/zynq/Kconfig" source "board/xilinx/zynqmp/Kconfig" source "board/zipitz2/Kconfig" diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h index f69cf00..3ff3c10 100644 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -20,6 +20,7 @@ #define ZYNQ_EFUSE_BASEADDR0xF800D000 #define ZYNQ_USB_BASEADDR0 0xE0002000 #define ZYNQ_USB_BASEADDR1 0xE0003000 +#define ZYNQ_OCM_BASEADDR 0xFFFC /* Bootmode setting values */ #define ZYNQ_BM_MASK 0x7 diff --git a/board/xilinx/zynq/Kconfig b/board/xilinx/zynq/Kconfig new file mode 100644 index 000..196c8e2 --- /dev/null +++ b/board/xilinx/zynq/Kconfig @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2018, Xilinx, Inc. + +if ARCH_ZYNQ + +config CMD_ZYNQ + bool "Enable Zynq specific commands" + default y + help + Enables Zynq specific commands. + +config CMD_ZYNQ_AES + bool "Enable zynq aes command for decryption of encrypted images" + depends on CMD_ZYNQ + depends on FPGA_ZYNQPL + help + Decrypts the encrypted image present in source address + and places the decrypted image at destination address. + +config CMD_ZYNQ_RSA + bool "Enable zynq rsa command for loading secure images" + default y + depends on CMD_ZYNQ + select CMD_ZYNQ_AES + help + Enabling this will support zynq secure image verification. + The secure image is a xilinx specific BOOT.BIN with + either authentication or encryption or both encryption + and authentication feature enabled while generating + BOOT.BIN using Xilinx bootgen tool. + +endif diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 5a76a26..f4996fa 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -18,6 +18,11 @@ $(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custom_hw_platform/)) endif endif +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_CMD_ZYNQ) += cmds.o +obj-$(CONFIG
[U-Boot] [PATCH v5 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
This patch adds qspi driver support for ZynqMP SoC. This driver is responsible for communicating with qspi flash devices. Signed-off-by: Siva Durga Prasad Paladugu --- Changed for v5: - Removed zynqm_gqspi.h file which was added by mistake. Changes for v4: - Moved macro definitions back to .c - Removed last_cmd and flash command checks in driver - Used macros and GENMASK as per comments - Removed debugs wherever commented. - Modified set_mode routine as per comment Changes for v3: - Renamed all macros, functions, files and configs as per comment - Used wait_for_bit wherever required - Removed unnecessary header inclusion Changes for v2: - Rebased on top of latest master - Moved macro definitions to .h file as per comment - Fixed magic values with macros as per comment --- drivers/spi/Kconfig| 7 + drivers/spi/Makefile | 1 + drivers/spi/zynqmp_gqspi.c | 794 + 3 files changed, 802 insertions(+) create mode 100644 drivers/spi/zynqmp_gqspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3532c2a..c3c424e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -223,6 +223,13 @@ config ZYNQ_QSPI Zynq QSPI IP core. This IP is used to connect the flash in 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. +config ZYNQMP_GQSPI + bool "Configure ZynqMP Generic QSPI" + depends on ARCH_ZYNQMP + help + This option is used to enable ZynqMP QSPI controller driver which + is used to communicate with qspi flash devices. + endif # if DM_SPI config SOFT_SPI diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 5a2c00e..2187633 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o +obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c new file mode 100644 index 000..9a04839 --- /dev/null +++ b/drivers/spi/zynqmp_gqspi.c @@ -0,0 +1,794 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 Xilinx + * + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) +#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) +#define GQSPI_CONFIG_DMA_MODE (2 << 30) +#define GQSPI_CONFIG_CPHA_MASK BIT(2) +#define GQSPI_CONFIG_CPOL_MASK BIT(1) + +/* QSPI MIO's count for different connection topologies */ +#define GQSPI_MIO_NUM_QSPI06 +#define GQSPI_MIO_NUM_QSPI15 +#define GQSPI_MIO_NUM_QSPI1_CS 1 + +/* + * QSPI Interrupt Registers bit Masks + * + * All the four interrupt registers (Status/Mask/Enable/Disable) have the same + * bit definitions. + */ +#define GQSPI_IXR_TXNFULL_MASK 0x0004 /* QSPI TX FIFO Overflow */ +#define GQSPI_IXR_TXFULL_MASK 0x0008 /* QSPI TX FIFO is full */ +#define GQSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX FIFO Not Empty */ +#define GQSPI_IXR_GFEMTY_MASK 0x0080 /* QSPI Generic FIFO Empty */ +#define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \ + GQSPI_IXR_RXNEMTY_MASK) + +/* + * QSPI Enable Register bit Masks + * + * This register is used to enable or disable the QSPI controller + */ +#define GQSPI_ENABLE_ENABLE_MASK 0x0001 /* QSPI Enable Bit Mask */ + +#define GQSPI_GFIFO_LOW_BUSBIT(14) +#define GQSPI_GFIFO_CS_LOWER BIT(12) +#define GQSPI_GFIFO_UP_BUS BIT(15) +#define GQSPI_GFIFO_CS_UPPER BIT(13) +#define GQSPI_SPI_MODE_QSPI(3 << 10) +#define GQSPI_SPI_MODE_SPI BIT(10) +#define GQSPI_SPI_MODE_DUAL_SPI(2 << 10) +#define GQSPI_IMD_DATA_CS_ASSERT 5 +#define GQSPI_IMD_DATA_CS_DEASSERT 5 +#define GQSPI_GFIFO_TX BIT(16) +#define GQSPI_GFIFO_RX BIT(17) +#define GQSPI_GFIFO_STRIPE_MASKBIT(18) +#define GQSPI_GFIFO_IMD_MASK 0xFF +#define GQSPI_GFIFO_EXP_MASK BIT(9) +#define GQSPI_GFIFO_DATA_XFR_MASK BIT(8) +#define GQSPI_STRT_GEN_FIFOBIT(28) +#define GQSPI_GEN_FIFO_STRT_MODBIT(29) +#define GQSPI_GFIFO_WP_HOLDBIT(19) +#define GQSPI_BAUD_DIV_MASK(7 << 3) +#define GQSPI_DFLT_BAUD_RATE_DIV BIT(3) +#define GQSPI_GFIFO_ALL_INT_MASK 0xFBE +#define GQSPI_DMA_DST_I_STS_DONE BIT(1) +#define GQSPI_DMA_DST_I_STS_MASK 0xFE +#define MODEBITS 0x6 + +#define QUAD_OUT_READ_CMD 0x6B +#define QUAD_PAGE_PROGRAM_CMD 0x32 +#define DUAL_OUTPUT_FASTRD_CMD 0x3B + +#define GQSPI_GFIFO_SELECT BIT(0) + +#define GQSPI_FIFO_THRESHOLD 1 + +#define SPI_XFER_ON_BOTH 0 +#
[U-Boot] [PATCH v5 2/2] zynqmp: zcu102: Add qspi driver support for ZynqMP zcu102 boards
This patch adds qspi driver support for all ZynqMP ZCU102 boards. Signed-off-by: Siva Durga Prasad Paladugu --- Changes for v5: - None Changes for v4: - None Changes for v3: - Changed as per latest changes in 1/2 Changes for v2: - Rebased on top of latest master and enabled qspi for all zcu102 boards. --- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 5 + configs/xilinx_zynqmp_zcu102_revA_defconfig | 5 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 5 + 3 files changed, 15 insertions(+) diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 49a14d8..da53aa4 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -69,6 +70,7 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -90,6 +92,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 05dad41..60e1269 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -66,6 +67,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -87,6 +89,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index b3711b4..fa2804d 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -66,6 +67,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -87,6 +89,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 2/2] zynqmp: zcu102: Add qspi driver support for ZynqMP zcu102 boards
This patch adds qspi driver support for all ZynqMP ZCU102 boards. Signed-off-by: Siva Durga Prasad Paladugu --- Changes for v4: - None Changes for v3: - Changed as per latest changes in 1/2 Changes for v2: - Rebased on top of latest master and enabled qspi for all zcu102 boards. --- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 5 + configs/xilinx_zynqmp_zcu102_revA_defconfig | 5 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 5 + 3 files changed, 15 insertions(+) diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 49a14d8..da53aa4 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -69,6 +70,7 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -90,6 +92,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 05dad41..60e1269 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -66,6 +67,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -87,6 +89,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index b3711b4..fa2804d 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -66,6 +67,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -87,6 +89,9 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
This patch adds qspi driver support for ZynqMP SoC. This driver is responsible for communicating with qspi flash devices. Signed-off-by: Siva Durga Prasad Paladugu --- Changes for v4: - Moved macro definitions back to .c - Removed last_cmd and flash command checks in driver - Used macros and GENMASK as per comments - Removed debugs wherever commented. - Modified set_mode routine as per comment Changes for v3: - Renamed all macros, functions, files and configs as per comment - Used wait_for_bit wherever required - Removed unnecessary header inclusion Changes for v2: - Rebased on top of latest master - Moved macro definitions to .h file as per comment - Fixed magic values with macros as per comment --- arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h | 154 + drivers/spi/Kconfig | 7 + drivers/spi/Makefile| 1 + drivers/spi/zynqmp_gqspi.c | 794 4 files changed, 956 insertions(+) create mode 100644 arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h create mode 100644 drivers/spi/zynqmp_gqspi.c diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h b/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h new file mode 100644 index 000..4b26d80 --- /dev/null +++ b/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Xilinx + * + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller + * driver (master mode only) + */ + +#ifndef _ASM_ARCH_ZYNQMP_GQSPI_H_ +#define _ASM_ARCH_ZYNQMP_GQSPI_H_ + +#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) +#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) +#define GQSPI_CONFIG_DMA_MODE (2 << 30) +#define GQSPI_CONFIG_CPHA_MASK BIT(2) +#define GQSPI_CONFIG_CPOL_MASK BIT(1) + +/* QSPI MIO's count for different connection topologies */ +#define GQSPI_MIO_NUM_QSPI06 +#define GQSPI_MIO_NUM_QSPI15 +#define GQSPI_MIO_NUM_QSPI1_CS 1 + +/* + * QSPI Interrupt Registers bit Masks + * + * All the four interrupt registers (Status/Mask/Enable/Disable) have the same + * bit definitions. + */ +#define GQSPI_IXR_TXNFULL_MASK 0x0004 /* QSPI TX FIFO Overflow */ +#define GQSPI_IXR_TXFULL_MASK 0x0008 /* QSPI TX FIFO is full */ +#define GQSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX FIFO Not Empty */ +#define GQSPI_IXR_GFEMTY_MASK 0x0080 /* QSPI Generic FIFO Empty */ +#define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \ + GQSPI_IXR_RXNEMTY_MASK) + +/* + * QSPI Enable Register bit Masks + * + * This register is used to enable or disable the QSPI controller + */ +#define GQSPI_ENABLE_ENABLE_MASK 0x0001 /* QSPI Enable Bit Mask */ + +#define GQSPI_GFIFO_LOW_BUSBIT(14) +#define GQSPI_GFIFO_CS_LOWER BIT(12) +#define GQSPI_GFIFO_UP_BUS BIT(15) +#define GQSPI_GFIFO_CS_UPPER BIT(13) +#define GQSPI_SPI_MODE_QSPI(3 << 10) +#define GQSPI_SPI_MODE_SPI BIT(10) +#define GQSPI_SPI_MODE_DUAL_SPI(2 << 10) +#define GQSPI_IMD_DATA_CS_ASSERT 5 +#define GQSPI_IMD_DATA_CS_DEASSERT 5 +#define GQSPI_GFIFO_TX BIT(16) +#define GQSPI_GFIFO_RX BIT(17) +#define GQSPI_GFIFO_STRIPE_MASKBIT(18) +#define GQSPI_GFIFO_IMD_MASK 0xFF +#define GQSPI_GFIFO_EXP_MASK BIT(9) +#define GQSPI_GFIFO_DATA_XFR_MASK BIT(8) +#define GQSPI_STRT_GEN_FIFOBIT(28) +#define GQSPI_GEN_FIFO_STRT_MODBIT(29) +#define GQSPI_GFIFO_WP_HOLDBIT(19) +#define GQSPI_BAUD_DIV_MASK(7 << 3) +#define GQSPI_DFLT_BAUD_RATE_DIV BIT(3) +#define GQSPI_GFIFO_ALL_INT_MASK 0xFBE +#define GQSPI_DMA_DST_I_STS_DONE BIT(1) +#define GQSPI_DMA_DST_I_STS_MASK 0xFE +#define MODEBITS 0x6 + +#define QUAD_OUT_READ_CMD 0x6B +#define QUAD_PAGE_PROGRAM_CMD 0x32 +#define DUAL_OUTPUT_FASTRD_CMD 0x3B + +#define GQSPI_GFIFO_SELECT BIT(0) + +#define GQSPI_FIFO_THRESHOLD 1 + +#define SPI_XFER_ON_BOTH 0 +#define SPI_XFER_ON_LOWER 1 +#define SPI_XFER_ON_UPPER 2 + +#define GQSPI_DMA_ALIGN0x4 +#define GQSPI_MAX_BAUD_RATE_VAL7 +#define GQSPI_DFLT_BAUD_RATE_VAL 2 + +#define GQSPI_TIMEOUT 1 + +#define GQSPI_BAUD_DIV_SHIFT 2 +#define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 +#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2 +#define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3 +#define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3 +#define GQSPI_USE_DATA_DLY 0x1 +#define GQSPI_USE_DATA_DLY_SHIFT 31 +#define GQSPI_DATA_DLY_ADJ_VALUE 0x2 +#define GQSPI_DATA_DLY_ADJ_SHIFT 28 +#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1 +#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 +#define GQSPI_DATA_DLY_ADJ_OFST0x01F8 +#define IOU_TAPDLY_BYPASS_OFST 0xFF180390 +#define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x
Re: [U-Boot] [RFC PATCH] fpga: zynq: Add encrypted bitstream support with auto detect
Hi Stefan,
> -Original Message-
> From: ste...@herbrechtsmeier.net [mailto:ste...@herbrechtsmeier.net]
> Sent: Friday, June 08, 2018 5:29 PM
> To: Siva Durga Prasad Paladugu
> Cc: Stefan Herbrechtsmeier ;
> u-boot@lists.denx.de; Michal Simek ;
> mon...@monstr.eu
> Subject: [RFC PATCH] fpga: zynq: Add encrypted bitstream support with
> auto detect
>
Patch description here please.
> From: Stefan Herbrechtsmeier
>
>
> Signed-off-by: Stefan Herbrechtsmeier
>
>
> ---
>
> drivers/fpga/zynqpl.c | 73
> ---
> 1 file changed, 57 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index
> fd37d18..6622750 100644
> --- a/drivers/fpga/zynqpl.c
> +++ b/drivers/fpga/zynqpl.c
> @@ -17,6 +17,7 @@
>
> #define DEVCFG_CTRL_PCFG_PROG_B 0x4000
> #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x1000
> +#define DEVCFG_CTRL_PCAP_RATE_EN_MASK0x0200
> #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
> #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
> #define DEVCFG_ISR_RX_FIFO_OV0x0004
> @@ -38,18 +39,16 @@
> #define CONFIG_SYS_FPGA_PROG_TIME(CONFIG_SYS_HZ * 4) /* 4 s
> */
> #endif
>
> +#define NOP_WORD 0x2000
> +#define CTRL0_WORD 0x3000a001
> +#define MASK_WORD0x3000c001
> #define DUMMY_WORD 0x
>
> +#define CTRL0_DEC_MASK BIT(6)
> +
> /* Xilinx binary format header */
> +#define MAX_DUMMY_WORD_COUNT 8
> static const u32 bin_format[] = {
> - DUMMY_WORD, /* Dummy words */
> - DUMMY_WORD,
> - DUMMY_WORD,
> - DUMMY_WORD,
> - DUMMY_WORD,
> - DUMMY_WORD,
> - DUMMY_WORD,
> - DUMMY_WORD,
> 0x00bb, /* Sync word */
> 0x11220044, /* Sync word */
> DUMMY_WORD,
> @@ -85,7 +84,23 @@ static u32 load_word(const void *buf, u32 swap)
> return word;
> }
>
> -static u32 check_header(const void *buf)
> +static void *skip_dummy_words(const void *buf) {
> + u32 *test = (u32 *)buf;
> + u32 i;
> +
> + for (i = 0; i < MAX_DUMMY_WORD_COUNT; i++) {
> + if (load_word([i], SWAP_NO) != DUMMY_WORD) {
> + debug("%s: Found no dummy word at position
> %d/%x\n",
> + __func__, i, (u32)[i]);
> + return [i];
> + }
> + }
> +
> + return [i];
> +}
> +
> +static u32 check_header(const void *buf, bool *encrypted)
> {
> u32 i, pattern;
> int swap = SWAP_NO;
> @@ -93,6 +108,8 @@ static u32 check_header(const void *buf)
>
> debug("%s: Let's check bitstream header\n", __func__);
>
> + test = (u32 *)skip_dummy_words(buf);
> +
> /* Checking that passing bin is not a bitstream */
> for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
> pattern = load_word([i], swap);
> @@ -112,18 +129,34 @@ static u32 check_header(const void *buf)
>
> debug("%s: %d/%x: pattern %x/%x bin_format\n",
> __func__, i,
> (u32)[i], pattern, bin_format[i]);
> +
> if (pattern != bin_format[i]) {
> debug("%s: Bitstream is not recognized\n",
> __func__);
> return 0;
> }
> }
> - debug("%s: Found bitstream header at %x %s swapinng\n",
> __func__,
> - (u32)buf, swap == SWAP_NO ? "without" : "with");
> +
> + test = [i];
> +
> + /* Checking if passing bin is an encrypted bitstream */
> + if ((load_word([0], swap) == NOP_WORD) &&
> + (load_word([1], swap) == MASK_WORD) &&
> + (load_word([2], swap) & CTRL0_DEC_MASK) &&
> + (load_word([3], swap) == CTRL0_WORD) &&
> + (load_word([4], swap) & CTRL0_DEC_MASK) &&
> + (load_word([5], swap) == NOP_WORD))
> + *encrypted = true;
> + else
> + *encrypted = false;
> +
> + debug("%s: Found %sencrypted bitstream header at %x %s
> swapping\n",
> + __func__, *encrypted ? "" : "un", (u32)buf,
> + swap == SWAP_NO ? "without" : "with");
>
> return swap;
> }
>
> -static void *check_data(u8 *buf, size_t bsize, u32 *swap)
> +static void *check_data(u8 *buf, size_t bsize, u32 *swap, bool
> +*encrypted)
> {
> u32 word, p = 0; /* possition */
>
> @@ -136,7 +169,7 @@ static void *check_data(u8 *buf, size_t bsize, u32
> *swap)
> if
Re: [U-Boot] [RFC PATCH] fpga: zynq: Add encrypted bitstream support with auto detect
Hi Stefan,
Yes, I checked and it looks fine functionally, I even tested it. Otherthan
this, I have few comments on this which I am going to reply to your RFC patch
mail.
Thanks,
Siva
> -Original Message-
> From: Siva Durga Prasad Paladugu
> Sent: Tuesday, June 12, 2018 9:18 AM
> To: stefan.herbrechtsme...@weidmueller.com;
> ste...@herbrechtsmeier.net
> Cc: u-boot@lists.denx.de; michal.si...@xilinx.com; mon...@monstr.eu
> Subject: RE: [RFC PATCH] fpga: zynq: Add encrypted bitstream support with
> auto detect
>
> Hi Stefan,
>
> > -Original Message-
> > From: stefan.herbrechtsme...@weidmueller.com
> > [mailto:stefan.herbrechtsme...@weidmueller.com]
> > Sent: Monday, June 11, 2018 9:33 PM
> > To: Siva Durga Prasad Paladugu ;
> > ste...@herbrechtsmeier.net
> > Cc: u-boot@lists.denx.de; michal.si...@xilinx.com; mon...@monstr.eu
> > Subject: AW: [RFC PATCH] fpga: zynq: Add encrypted bitstream support
> > with auto detect
> >
> > Hi Siva,
> >
> > > -Ursprüngliche Nachricht-
> > > Von: Siva Durga Prasad Paladugu [mailto:siva...@xilinx.com]
> > > Gesendet: Montag, 11. Juni 2018 13:40
> > > An: ste...@herbrechtsmeier.net
> > > Cc: Herbrechtsmeier Dr.-Ing. , Stefan
> > > ; u-boot@lists.denx.de;
> > Michal
> > > Simek ; mon...@monstr.eu
> > > Betreff: RE: [RFC PATCH] fpga: zynq: Add encrypted bitstream support
> > > with auto detect
> > >
> > > Interesting, I got your point. First of all, Could you please let
> > > me know on how do you created the encrypted bitstream?
> >
> > I use bootgen with the split option and the following bif file:
> >
> > bootgen -image u-boot-spl-aes.bif -o i u-boot-spl-aes.bin -w on
> > -encrypt efuse -split bin
> >
> > image:
> > {
> > [aeskeyfile]efuse.nky
> > [pskfile]psk.pem
> > [sskfile]ssk.pem
> > [bootloader, encryption=aes, authentication=rsa]u-boot-spl.elf
> > [encryption=aes]fpga.bit
> > }
> >
> > > I hope this is not the Xilinx bootgen flow(may be through other
> > > Xilinx
> > > flow)
> >
> > To my knowledge you could only use bootgen because Xilinx doesn't
> > documented the encryption even if I would like to integrate the
> > encryption into mkimage.
> >
> > > because, I don't think bootgen will update these fields while
> > > creating encrypted bitstream( need to re confirm on this) and my
> > > flow targets the Xilinx bootgen flow.
> >
> > This fields are part of the encrypted binary bitstream and are needed
> > for the fpga configuration via the pcap. They are documented inside
> > the 'ug470_7Series_Config.pdf'.
> >
> > > Please let know your comments on this, based on which, will try to
> > > review and test your patch.
> >
> > Let me know if you need more information or help.
>
> Thanks for the clarity, let me check on it and come back.
> Let me also look in to modify secure patch if required as per this.
>
> Thanks,
> Siva
>
> >
> > Regards
> >
> > Stefan Herbrechtsmeier
> > Software Developer Embedded Systems
> >
> > Weidmüller - Your partner in Industrial Connectivity We look forward
> > to sharing ideas with you - Let's connect.
> >
> > Weidmueller Interface GmbH & Co. KG
> > Klingenbergstraße 16, 32758 Detmold, Germany
> > Email: stefan.herbrechtsme...@weidmueller.com - Web:
> > www.weidmueller.com
> >
> >
> >
> > Kommanditgesellschaft - Sitz: Detmold - Amtsgericht Lemgo HRA 2790 -
> > Komplementärin: Weidmüller Interface Führungsgesellschaft mbH -
> > Sitz: Detmold - Amtsgericht Lemgo HRB 3924;
> > Geschäftsführer: José Carlos Álvarez Tobar, Elke Eckstein, Jörg
> > Timmermann; USt-ID-Nr. DE124599660
___
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[U-Boot] [PATCH v4] xilinx: zynq: Add support to secure images
This patch basically adds two new commands for loadig secure images. 1. zynq rsa adds support to load secure image which can be both authenticated or encrypted or both authenticated and encrypted image in xilinx bootimage(BOOT.bin) format. 2. zynq aes command adds support to decrypt and load encrypted image back to DDR as per destination address. The image has to be encrypted using xilinx bootgen tool and to get only the encrypted image from tool use -split option while invoking bootgen. Signed-off-by: Siva Durga Prasad Paladugu --- Changes from v3: - Removed aesload and aesloadp as encrypted bitstream load is under duscussion and hence removed from this patch. Will work on it as a separate patch once discussion finalized. _ Fixed coding style comments Changes from v2: - Created separate commands for zynq aesload and aesloadp as per comment - Fixed all other coding style comments Changes from v1: - Defined two config synbols for RSA and AES separately and used them wherever required. - Used U_BOOT_CMD_KENT as per comment - Cleared DEVCFG_CTRL_PCAP_RATE_EN_MASK once decryption is done. Changes from RFC: - Moved zynqaes to board/xilinx/zynq/cmds.c and renamed as "zynq aes". - Moved boot image parsing code to a separate file. - Squashed in to a single patch. - Fixed coding style comments. --- arch/arm/Kconfig | 1 + arch/arm/mach-zynq/include/mach/hardware.h | 1 + board/xilinx/zynq/Kconfig | 33 ++ board/xilinx/zynq/Makefile | 5 + board/xilinx/zynq/bootimg.c| 143 board/xilinx/zynq/cmds.c | 509 + drivers/fpga/zynqpl.c | 47 +++ include/u-boot/rsa-mod-exp.h | 4 + include/zynq_bootimg.h | 33 ++ include/zynqpl.h | 4 + lib/rsa/rsa-mod-exp.c | 51 +++ 11 files changed, 831 insertions(+) create mode 100644 board/xilinx/zynq/Kconfig create mode 100644 board/xilinx/zynq/bootimg.c create mode 100644 board/xilinx/zynq/cmds.c create mode 100644 include/zynq_bootimg.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3e05f79..e78e1a4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1428,6 +1428,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" +source "board/xilinx/zynq/Kconfig" source "board/xilinx/zynqmp/Kconfig" source "board/zipitz2/Kconfig" diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h index f69cf00..3ff3c10 100644 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -20,6 +20,7 @@ #define ZYNQ_EFUSE_BASEADDR0xF800D000 #define ZYNQ_USB_BASEADDR0 0xE0002000 #define ZYNQ_USB_BASEADDR1 0xE0003000 +#define ZYNQ_OCM_BASEADDR 0xFFFC /* Bootmode setting values */ #define ZYNQ_BM_MASK 0x7 diff --git a/board/xilinx/zynq/Kconfig b/board/xilinx/zynq/Kconfig new file mode 100644 index 000..3b91e13 --- /dev/null +++ b/board/xilinx/zynq/Kconfig @@ -0,0 +1,33 @@ +# Copyright (c) 2018, Xilinx, Inc. +# +# SPDX-License-Identifier: GPL-2.0 + +if ARCH_ZYNQ + +config CMD_ZYNQ + bool "Enable Zynq specific commands" + default y + help + Enables Zynq specific commands. + +config CMD_ZYNQ_AES + bool "Enable zynq aes command for decryption of encrypted images" + depends on CMD_ZYNQ + depends on FPGA_ZYNQPL + help + Decrypts the encrypted image present in source address + and places the decrypted image at destination address. + +config CMD_ZYNQ_RSA + bool "Enable zynq rsa command for loading secure images" + default y + depends on CMD_ZYNQ + select CMD_ZYNQ_AES + help + Enabling this will support zynq secure image verification. + The secure image is a xilinx specific BOOT.BIN with + either authentication or encryption or both encryption + and authentication feature enabled while generating + BOOT.BIN using Xilinx bootgen tool. + +endif diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 5a76a26..f4996fa 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -18,6 +18,11 @@ $(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custom_hw_platform/)) endif endif +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_CMD_ZYNQ) += cmds.o +obj-$(CONFIG_CMD_ZYNQ_RSA) += bootimg.o +endif + obj-$(CONFIG_SPL_BUILD) += $(init-objs) # Suppress "warning: function declaration isn't a prototype" diff --git a/board/xilinx/zynq/bootimg.c b/board/xilinx/zynq/bootimg.
[U-Boot] [PATCH v3 4/4] arm: zynq: Add parallel NOR flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint OCM memory. This configuration
only has required parallel nor flash support.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v2:
- None
Changes from v1:
- None
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-cse-nor.dts | 88 ++
configs/zynq_cse_nor_defconfig | 50
3 files changed, 139 insertions(+)
create mode 100644 arch/arm/dts/zynq-cse-nor.dts
create mode 100644 configs/zynq_cse_nor_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 71b7c3a..9e29fe6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
zynq-cse-nand.dtb \
+ zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
new file mode 100644
index 000..ba6f9a1
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NOR board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NOR Board";
+ compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@fffc {
+ device_type = "memory";
+ reg = <0xFFFC 0x4>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+ ranges;
+
+ intc: interrupt-controller@f8f01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xF8F01000 0x1000>,
+ <0xF8F00100 0x100>;
+ };
+
+ slcr: slcr@f800 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF800 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ fclk-enable = <0xf>;
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper",
+
[U-Boot] [PATCH v3 2/4] arm: zynq: Dont define SDRAM_BASE and SDRAM_SIZE in .h
Remove the SDRAM_BASE nad SDRAM_SIZE as it can now get these details from DT. Signed-off-by: Siva Durga Prasad Paladugu --- Changes from v2: - None Changes from v1: - Removed commit reference from description as per comment --- include/configs/zynq_cse.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index 2f5843f..adc02f0 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -41,7 +41,4 @@ #undef CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_MALLOC_LEN 0x1000 -#define CONFIG_SYS_SDRAM_BASE 0xfffc -#define CONFIG_SYS_SDRAM_SIZE 0x4 - #endif /* __CONFIG_ZYNQ_CSE_H */ -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 3/4] arm: zynq: Add Nand flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint of memory. This configuration
has only required nand flash support.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v2:
- None
Changes from v1:
- Update memory node as per comment
- Removed intc and fclk as per comment
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-cse-nand.dts | 80 +
configs/zynq_cse_nand_defconfig | 50 ++
3 files changed, 131 insertions(+)
create mode 100644 arch/arm/dts/zynq-cse-nand.dts
create mode 100644 configs/zynq_cse_nand_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a0349a8..71b7c3a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -128,6 +128,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
+ zynq-cse-nand.dtb \
zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
new file mode 100644
index 000..9b1dd19
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NAND board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NAND Board";
+ compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ slcr: slcr@f800 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF800 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper",
+ "swdt", "dbg_trc", "dbg_apb";
+ reg = <0x100 0x100>;
+ };
+ };
+ };
+
+};
+
+ {
+ status = "okay";
+};
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
new file
[U-Boot] [PATCH v3 1/4] lib: fdtdec: Add new variable ram_start to global data
Added new variable ram_start to global data structure for holding
the start address of first bank of RAM, and then use this ram_start
for calculating ram_top properly. This patch fixes the erroneous
calculation of ram_top incase of non zero ram start address.
This patch also renames fdtdec_setup_memory_size() to
fdtdec_setup_mem_size_start() as this routine now takes care
of memory size and start.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
Changes from v2:
- Used new varibale ram_start
- Rename fdtdec_setup_memory_size
Changes from v1:
- None
---
arch/arm/mach-mvebu/arm64-common.c | 2 +-
board/emulation/qemu-arm/qemu-arm.c | 2 +-
board/renesas/alt/alt.c | 2 +-
board/renesas/blanche/blanche.c | 2 +-
board/renesas/draak/draak.c | 2 +-
board/renesas/eagle/eagle.c | 2 +-
board/renesas/gose/gose.c| 2 +-
board/renesas/koelsch/koelsch.c | 2 +-
board/renesas/lager/lager.c | 2 +-
board/renesas/porter/porter.c| 2 +-
board/renesas/salvator-x/salvator-x.c| 2 +-
board/renesas/silk/silk.c| 2 +-
board/renesas/stout/stout.c | 2 +-
board/renesas/ulcb/ulcb.c| 2 +-
board/st/stm32f429-discovery/stm32f429-discovery.c | 2 +-
board/st/stm32f429-evaluation/stm32f429-evaluation.c | 2 +-
board/st/stm32f469-discovery/stm32f469-discovery.c | 2 +-
board/st/stm32h743-disco/stm32h743-disco.c | 2 +-
board/st/stm32h743-eval/stm32h743-eval.c | 2 +-
board/xilinx/zynq/board.c| 2 +-
board/xilinx/zynqmp/zynqmp.c | 2 +-
board/xilinx/zynqmp_r5/board.c | 2 +-
common/board_f.c | 4 ++--
include/asm-generic/global_data.h| 1 +
include/fdtdec.h | 16 +---
lib/fdtdec.c | 3 ++-
tools/patman/func_test.py| 2 +-
tools/patman/test/-cover-letter.patch| 2 +-
...orrect-cast-for-sandbox-in-fdtdec_setup_memory_.patch | 4 ++--
tools/patman/test/test01.txt | 2 +-
30 files changed, 41 insertions(+), 37 deletions(-)
diff --git a/arch/arm/mach-mvebu/arm64-common.c
b/arch/arm/mach-mvebu/arm64-common.c
index d3ea9e6..c2ab831 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -54,7 +54,7 @@ int dram_init_banksize(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_start() != 0)
return -EINVAL;
return 0;
diff --git a/board/emulation/qemu-arm/qemu-arm.c
b/board/emulation/qemu-arm/qemu-arm.c
index 6ec4200..926bbf2 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -47,7 +47,7 @@ int board_init(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_start() != 0)
return -EINVAL;
return 0;
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 86e9d24..58838ff 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -78,7 +78,7 @@ int board_init(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_start() != 0)
return -EINVAL;
return 0;
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index 7d48d0f..1fd511c 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c
@@ -339,7 +339,7 @@ int board_eth_init(bd_t *bis)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_start() != 0)
return -EINVAL;
return 0;
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index f804fae..b178131 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -96,7 +96,7 @@ int board_init(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_start() != 0)
return -EINVAL;
return 0;
diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c
index 4bf0a20..26deca9 100644
--- a/board/renesas/eagle/eagle.c
+++ b/board/renesas/eagle/eagle.c
@@ -73,7 +73,7 @@ int board_init(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_start() != 0)
return -EINVAL;
return 0
Re: [U-Boot] [PATCH 1/4] lib: fdtdec: Fill initial ram top with DDR start value from dt
Hi Simon,
> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: Saturday, June 09, 2018 3:29 AM
> To: Michal Simek
> Cc: Siva Durga Prasad Paladugu ; U-Boot Mailing List
> ; Tom Rini
> Subject: Re: [PATCH 1/4] lib: fdtdec: Fill initial ram top with DDR start
> value
> from dt
>
> Hi,
>
>
> On 7 June 2018 at 06:18, Michal Simek wrote:
> > Hi,
> >
> > On 5.6.2018 09:20, Siva Durga Prasad Paladugu wrote:
> >> Fill initial ram top with DDR base addr value from DT as not filling
> >> it here always assumes it as zero while calculating relocation offset
> >> and hence lead to failures in somecases. This will assumed as zero if
> >> CONFIG_SYS_SDRAM_BASE is not defined.
> >>
> >> Signed-off-by: Siva Durga Prasad Paladugu
> >>
> >> Signed-off-by: Michal Simek
> >> ---
> >> lib/fdtdec.c | 1 +
> >> 1 file changed, 1 insertion(+)
> >>
> >> diff --git a/lib/fdtdec.c b/lib/fdtdec.c index f4e8dbf..34ef9b8
> >> 100644
> >> --- a/lib/fdtdec.c
> >> +++ b/lib/fdtdec.c
> >> @@ -1172,6 +1172,7 @@ int fdtdec_setup_memory_size(void)
> >> }
> >>
> >> gd->ram_size = (phys_size_t)(res.end - res.start + 1);
> >> + gd->ram_top = (unsigned long)res.start;
> >> debug("%s: Initial DRAM size %llx\n", __func__,
> >> (unsigned long long)gd->ram_size);
> >>
> >>
> >
> > I am curious about ram_top meaning. It is used more as ram_base.
> >
> > I expect we can workaround it by board_get_usable_ram_top() where we
> > decode it exactly the same as patched fdtdec_setup_memory_size() but I
> > don't think it is better solution than this one.
> >
> > Simon/Tom: any comment?
>
> I wonder why it is not set to res.end in this patch?
>
> Comments from global_data.h:
>
> unsigned long ram_top; /* Top address of RAM used by U-Boot */
> phys_size_t ram_size; /* RAM size */
Yes, it holds the ram high address but, initially it should contain start
address then in routine setup_dest_addr() (file common_board_f.c), it will be
updated by getting the
total mem size as below.
gd->ram_top += get_effective_memsize();
Lets consider if start address is non zero then it results in wrong ram_top
without this patch. So, this patch fixes it by initializing it to ram start
address and later in setup_dest_addr(), it will be updated to actual ram high
address.
Otherway of fixing it is, we should add new variable to gd_t to hold ram_start
and then while calculating ram_top in setup_dest_addr(), we should use it as
gd->ram_top = gd->ram_start + get_effective_memsize() as
gd->bd->bi_dram[0].start didn’t get filled by this time during init.
Thanks,
Siva
>
> Regards,
> Simon
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Re: [U-Boot] [PATCH] mmc: sdhci: Fix MMC HS200 tuning command failures
Hi Masahiro,
Not sure why it caused issue now, i used git send-email to sent this patch
and always uses the same to send patches. One more thing is i didn't get
your reply mail on my official mail id, and i don't have any clue on what
caused the issue. I may need to check with our IT on both these.
I will talk to Michal, if he can send this patch on my behalf till my
e-mail issue got resolved
Thanks,
Siva
On Tue, Jun 12, 2018 at 5:57 PM, Masahiro Yamada <
yamada.masah...@socionext.com> wrote:
> 2018-06-12 21:00 GMT+09:00 Siva Durga Prasad Paladugu
> :
> > This patch fixes the mmc tuning command failures
> > when tuning pattern data needs to read back for
> > comparision against the excpected bit pattern.
> >
>
> Typo:
>
> excpected -> expected
>
>
> Reported-by: Masahiro Yamada
>
>
> > Signed-off-by: Siva Durga Prasad Paladugu com>
>
>
> This patch does not apply.
>
> I think all the tabs have been replaced with spaces.
>
> What did you use for sending this patch?
> If you used your mailer, it is a bad idea.
>
> I recommend to use 'git send-email' (or patman).
>
>
>
>
>
>
>
> > ---
> > drivers/mmc/sdhci.c | 8
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> > index 40e28ab..cdeba91 100644
> > --- a/drivers/mmc/sdhci.c
> > +++ b/drivers/mmc/sdhci.c
> > @@ -161,8 +161,8 @@ static int sdhci_send_command(struct mmc *mmc,
> struct mmc_cmd *cmd,
> > /* We shouldn't wait for data inihibit for stop commands, even
> >though they might use busy signaling */
> > if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
> > - cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
> > - cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
> > + ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
> > + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
> > mask &= ~SDHCI_DATA_INHIBIT;
> >
> > while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
> > @@ -184,8 +184,8 @@ static int sdhci_send_command(struct mmc *mmc,
> struct mmc_cmd *cmd,
> > sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
> >
> > mask = SDHCI_INT_RESPONSE;
> > - if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
> > - cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
> > + if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
> > +cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
> > mask = SDHCI_INT_DATA_AVAIL;
> >
> > if (!(cmd->resp_type & MMC_RSP_PRESENT))
> > --
> > 2.7.4
> >
> > This email and any attachments are intended for the sole use of the
> named recipient(s) and contain(s) confidential information that may be
> proprietary, privileged or copyrighted under applicable law. If you are not
> the intended recipient, do not read, copy, or forward this email message or
> any attachments. Delete this email message and any attachments immediately.
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > https://lists.denx.de/listinfo/u-boot
>
>
>
> --
> Best Regards
> Masahiro Yamada
> ___
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[U-Boot] [PATCH] mmc: sdhci: Fix MMC HS200 tuning command failures
This patch fixes the mmc tuning command failures
when tuning pattern data needs to read back for
comparision against the excpected bit pattern.
Signed-off-by: Siva Durga Prasad Paladugu
---
drivers/mmc/sdhci.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 40e28ab..cdeba91 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -161,8 +161,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
mmc_cmd *cmd,
/* We shouldn't wait for data inihibit for stop commands, even
though they might use busy signaling */
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
+ ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
mask &= ~SDHCI_DATA_INHIBIT;
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
@@ -184,8 +184,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
mmc_cmd *cmd,
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_INT_RESPONSE;
- if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
mask = SDHCI_INT_DATA_AVAIL;
if (!(cmd->resp_type & MMC_RSP_PRESENT))
--
2.7.4
This email and any attachments are intended for the sole use of the named
recipient(s) and contain(s) confidential information that may be proprietary,
privileged or copyrighted under applicable law. If you are not the intended
recipient, do not read, copy, or forward this email message or any attachments.
Delete this email message and any attachments immediately.
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Re: [U-Boot] HS200 for SDHCI is broken
Hi Masahiro,
Can you please try with this below change and let me know if it works.
In our case, we don’t want to read tuning pattern, instead it waits for
TUNED_CLK bit to be set in host ctrl2 register. But, in your case, you want to
read back the pattern data and compare it.
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -161,8 +161,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
mmc_cmd *cmd,
/* We shouldn't wait for data inihibit for stop commands, even
though they might use busy signaling */
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
+ ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
mask &= ~SDHCI_DATA_INHIBIT;
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
@@ -184,8 +184,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
mmc_cmd *cmd,
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_INT_RESPONSE;
- if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
mask = SDHCI_INT_DATA_AVAIL;
if (!(cmd->resp_type & MMC_RSP_PRESENT))
Thanks,
Siva
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Tuesday, June 12, 2018 2:34 PM
> To: Masahiro Yamada ; Siva Durga
> Prasad Paladugu ; Michal Simek
> ; U-Boot Mailing List
> Cc: Jaehoon Chung ; Tom Rini
>
> Subject: Re: HS200 for SDHCI is broken
>
> On 12.6.2018 07:31, Masahiro Yamada wrote:
> > 2018-06-12 14:26 GMT+09:00 Masahiro Yamada
> :
> >> Hi Siva, Michal.
> >>
> >>
> >> I noticed drivers/mmc/sdhci-cadence.c not working for my boards.
> >>
> >>
> >> git-bisect points the following commit:
> >>
> >>
> >>
> >> commit 434f9d454eb1a17bb7f5cdb21167ccbe7e41da39
> >> Author: Siva Durga Prasad Paladugu
> >> Date: Tue May 29 20:03:10 2018 +0530
> >>
> >> mmc: sdhci: Update sdhci_send_command() to handle HS200
> >>
> >> This patch updates sdhci_send_command() to handle MMC
> >> HS200 tuning command.
> >>
> >> Signed-off-by: Siva Durga Prasad Paladugu
>
> >> Signed-off-by: Michal Simek
> >>
> >>
> >>
> >>
> >>
> >> By reverting it, I can get the MMC on my boards working again.
> >>
> >> Any idea to fix it?
> >
> >
> >
> > BTW, 'mmc info' looks like follows on the bad commit:
> >
> >
> >
> >
> > U-Boot 2018.05-00471-g434f9d4 (Jun 12 2018 - 14:08:39 +0900)
> >
> > SoC: LD20 (model 1, revision 1)
> > Model: UniPhier LD20 Reference Board
> > DRAM: 3 GiB
> > SC:Micro Support Card (CPLD version 3.6)
> > NAND: 0 MiB
> > MMC: sdhc@5a00: 0
> > In:serial@54006800
> > Out: serial@54006800
> > Err: serial@54006800
> > MODE: NOR Boot (STM: OFF)
> > Net: smc911x-0
> > Warning: smc911x-0 (eth0) using random MAC address -
> fe:7e:f8:eb:45:1d
> >
> > Hit any key to stop autoboot: 0
> > => mmc info
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> > sdhci_send_command: Timeout for status update!
> >
Re: [U-Boot] [RFC PATCH] fpga: zynq: Add encrypted bitstream support with auto detect
Hi Stefan,
> -Original Message-
> From: stefan.herbrechtsme...@weidmueller.com
> [mailto:stefan.herbrechtsme...@weidmueller.com]
> Sent: Monday, June 11, 2018 9:33 PM
> To: Siva Durga Prasad Paladugu ;
> ste...@herbrechtsmeier.net
> Cc: u-boot@lists.denx.de; michal.si...@xilinx.com; mon...@monstr.eu
> Subject: AW: [RFC PATCH] fpga: zynq: Add encrypted bitstream support
> with auto detect
>
> Hi Siva,
>
> > -Ursprüngliche Nachricht-
> > Von: Siva Durga Prasad Paladugu [mailto:siva...@xilinx.com]
> > Gesendet: Montag, 11. Juni 2018 13:40
> > An: ste...@herbrechtsmeier.net
> > Cc: Herbrechtsmeier Dr.-Ing. , Stefan
> > ; u-boot@lists.denx.de;
> Michal
> > Simek ; mon...@monstr.eu
> > Betreff: RE: [RFC PATCH] fpga: zynq: Add encrypted bitstream support
> > with auto detect
> >
> > Interesting, I got your point. First of all, Could you please let me
> > know on how do you created the encrypted bitstream?
>
> I use bootgen with the split option and the following bif file:
>
> bootgen -image u-boot-spl-aes.bif -o i u-boot-spl-aes.bin -w on -encrypt
> efuse -split bin
>
> image:
> {
> [aeskeyfile]efuse.nky
> [pskfile]psk.pem
> [sskfile]ssk.pem
> [bootloader, encryption=aes, authentication=rsa]u-boot-spl.elf
> [encryption=aes]fpga.bit
> }
>
> > I hope this is not the Xilinx bootgen flow(may be through other Xilinx
> > flow)
>
> To my knowledge you could only use bootgen because Xilinx doesn't
> documented the encryption even if I would like to integrate the encryption
> into mkimage.
>
> > because, I don't think bootgen will update these fields while creating
> > encrypted bitstream( need to re confirm on this) and my flow targets
> > the Xilinx bootgen flow.
>
> This fields are part of the encrypted binary bitstream and are needed for the
> fpga configuration via the pcap. They are documented inside the
> 'ug470_7Series_Config.pdf'.
>
> > Please let know your comments on this, based on which, will try to
> > review and test your patch.
>
> Let me know if you need more information or help.
Thanks for the clarity, let me check on it and come back.
Let me also look in to modify secure patch if required as per this.
Thanks,
Siva
>
> Regards
>
> Stefan Herbrechtsmeier
> Software Developer Embedded Systems
>
> Weidmüller - Your partner in Industrial Connectivity We look forward to
> sharing ideas with you - Let's connect.
>
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> www.weidmueller.com
>
>
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[U-Boot] [PATCH v3] xilinx: zynq: Add support to secure images
This patch basically adds two new commands for loadig secure images/bitstreams. 1. zynq rsa adds support to load secure image which can be both authenticated or encrypted or both authenticated and encrypted image in xilinx bootimage(BOOT.bin) format. 2. zynq aes command adds support to decrypted and load encrypted image either back to DDR or it can load an encrypted bitsream to PL directly by decrypting it. The image has to be encrypted using xilinx bootgen tool and to get only the encrypted image from tool use -split option while invoking bootgen. Signed-off-by: Siva Durga Prasad Paladugu --- Changes from v2: - Created separate commands for zynq aesload and aesloadp as per comment - Fixed all other coding style comments Changes from v1: - Defined two config synbols for RSA and AES separately and used them wherever required. - Used U_BOOT_CMD_KENT as per comment - Cleared DEVCFG_CTRL_PCAP_RATE_EN_MASK once decryption is done. Changes from RFC: - Moved zynqaes to board/xilinx/zynq/cmds.c and renamed as "zynq aes". - Moved boot image parsing code to a separate file. - Squashed in to a single patch. - Fixed coding style comments. --- arch/arm/Kconfig | 1 + arch/arm/mach-zynq/include/mach/hardware.h | 1 + board/xilinx/zynq/Kconfig | 32 ++ board/xilinx/zynq/Makefile | 5 + board/xilinx/zynq/bootimg.c| 143 board/xilinx/zynq/cmds.c | 570 + drivers/fpga/zynqpl.c | 67 include/u-boot/rsa-mod-exp.h | 4 + include/zynq_bootimg.h | 33 ++ include/zynqpl.h | 5 + lib/rsa/rsa-mod-exp.c | 51 +++ 11 files changed, 912 insertions(+) create mode 100644 board/xilinx/zynq/Kconfig create mode 100644 board/xilinx/zynq/bootimg.c create mode 100644 board/xilinx/zynq/cmds.c create mode 100644 include/zynq_bootimg.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3e05f79..e78e1a4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1428,6 +1428,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" +source "board/xilinx/zynq/Kconfig" source "board/xilinx/zynqmp/Kconfig" source "board/zipitz2/Kconfig" diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h index f69cf00..3ff3c10 100644 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -20,6 +20,7 @@ #define ZYNQ_EFUSE_BASEADDR0xF800D000 #define ZYNQ_USB_BASEADDR0 0xE0002000 #define ZYNQ_USB_BASEADDR1 0xE0003000 +#define ZYNQ_OCM_BASEADDR 0xFFFC /* Bootmode setting values */ #define ZYNQ_BM_MASK 0x7 diff --git a/board/xilinx/zynq/Kconfig b/board/xilinx/zynq/Kconfig new file mode 100644 index 000..e665c8d --- /dev/null +++ b/board/xilinx/zynq/Kconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2018, Xilinx, Inc. +# +# SPDX-License-Identifier: GPL-2.0 + +if ARCH_ZYNQ + +config CMD_ZYNQ + bool "Enable Zynq specific commands" + default y + help + Enables Zynq specific commands. + +config CMD_ZYNQ_AES + bool "Enable zynq aes command for decryption of encrypted images" + depends on CMD_ZYNQ + help + Decrypts the encrypted image present in source address + and places the decrypted image at destination address. + +config CMD_ZYNQ_RSA + bool "Enable zynq rsa command for loading secure images" + default y + depends on CMD_ZYNQ + select CMD_ZYNQ_AES + help + Enabling this will support zynq secure image verification. + The secure image is a xilinx specific BOOT.BIN with + either authentication or encryption or both encryption + and authentication feature enabled while generating + BOOT.BIN using Xilinx bootgen tool. + +endif diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 5a76a26..f4996fa 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -18,6 +18,11 @@ $(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custom_hw_platform/)) endif endif +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_CMD_ZYNQ) += cmds.o +obj-$(CONFIG_CMD_ZYNQ_RSA) += bootimg.o +endif + obj-$(CONFIG_SPL_BUILD) += $(init-objs) # Suppress "warning: function declaration isn't a prototype" diff --git a/board/xilinx/zynq/bootimg.c b/board/xilinx/zynq/bootimg.c new file mode 100644 index 000..56d69cd --- /dev/null +++ b/board/xilinx/zynq/bootimg.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Xilinx, Inc. + */ + +#inclu
Re: [U-Boot] [RFC PATCH] fpga: zynq: Add encrypted bitstream support with auto detect
Hi Stefan,
Interesting, I got your point. First of all, Could you please let me know on
how do you created the encrypted bitstream?
I hope this is not the Xilinx bootgen flow(may be through other Xilinx flow)
because, I don't think bootgen will update these fields while creating
encrypted bitstream( need to re confirm on this) and my flow targets the Xilinx
bootgen flow.
Please let know your comments on this, based on which, will try to review and
test your patch.
Thanks,
Siva
> -Original Message-
> From: ste...@herbrechtsmeier.net [mailto:ste...@herbrechtsmeier.net]
> Sent: Friday, June 08, 2018 5:29 PM
> To: Siva Durga Prasad Paladugu
> Cc: Stefan Herbrechtsmeier ;
> u-boot@lists.denx.de; Michal Simek ;
> mon...@monstr.eu
> Subject: [RFC PATCH] fpga: zynq: Add encrypted bitstream support with
> auto detect
>
> From: Stefan Herbrechtsmeier
>
>
> Signed-off-by: Stefan Herbrechtsmeier
>
>
> ---
>
> drivers/fpga/zynqpl.c | 73
> ---
> 1 file changed, 57 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index
> fd37d18..6622750 100644
> --- a/drivers/fpga/zynqpl.c
> +++ b/drivers/fpga/zynqpl.c
> @@ -17,6 +17,7 @@
>
> #define DEVCFG_CTRL_PCFG_PROG_B 0x4000
> #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x1000
> +#define DEVCFG_CTRL_PCAP_RATE_EN_MASK0x0200
> #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
> #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
> #define DEVCFG_ISR_RX_FIFO_OV0x0004
> @@ -38,18 +39,16 @@
> #define CONFIG_SYS_FPGA_PROG_TIME(CONFIG_SYS_HZ * 4) /* 4 s
> */
> #endif
>
> +#define NOP_WORD 0x2000
> +#define CTRL0_WORD 0x3000a001
> +#define MASK_WORD0x3000c001
> #define DUMMY_WORD 0x
>
> +#define CTRL0_DEC_MASK BIT(6)
> +
> /* Xilinx binary format header */
> +#define MAX_DUMMY_WORD_COUNT 8
> static const u32 bin_format[] = {
> - DUMMY_WORD, /* Dummy words */
> - DUMMY_WORD,
> - DUMMY_WORD,
> - DUMMY_WORD,
> - DUMMY_WORD,
> - DUMMY_WORD,
> - DUMMY_WORD,
> - DUMMY_WORD,
> 0x00bb, /* Sync word */
> 0x11220044, /* Sync word */
> DUMMY_WORD,
> @@ -85,7 +84,23 @@ static u32 load_word(const void *buf, u32 swap)
> return word;
> }
>
> -static u32 check_header(const void *buf)
> +static void *skip_dummy_words(const void *buf) {
> + u32 *test = (u32 *)buf;
> + u32 i;
> +
> + for (i = 0; i < MAX_DUMMY_WORD_COUNT; i++) {
> + if (load_word([i], SWAP_NO) != DUMMY_WORD) {
> + debug("%s: Found no dummy word at position
> %d/%x\n",
> + __func__, i, (u32)[i]);
> + return [i];
> + }
> + }
> +
> + return [i];
> +}
> +
> +static u32 check_header(const void *buf, bool *encrypted)
> {
> u32 i, pattern;
> int swap = SWAP_NO;
> @@ -93,6 +108,8 @@ static u32 check_header(const void *buf)
>
> debug("%s: Let's check bitstream header\n", __func__);
>
> + test = (u32 *)skip_dummy_words(buf);
> +
> /* Checking that passing bin is not a bitstream */
> for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
> pattern = load_word([i], swap);
> @@ -112,18 +129,34 @@ static u32 check_header(const void *buf)
>
> debug("%s: %d/%x: pattern %x/%x bin_format\n",
> __func__, i,
> (u32)[i], pattern, bin_format[i]);
> +
> if (pattern != bin_format[i]) {
> debug("%s: Bitstream is not recognized\n",
> __func__);
> return 0;
> }
> }
> - debug("%s: Found bitstream header at %x %s swapinng\n",
> __func__,
> - (u32)buf, swap == SWAP_NO ? "without" : "with");
> +
> + test = [i];
> +
> + /* Checking if passing bin is an encrypted bitstream */
> + if ((load_word([0], swap) == NOP_WORD) &&
> + (load_word([1], swap) == MASK_WORD) &&
> + (load_word([2], swap) & CTRL0_DEC_MASK) &&
> + (load_word([3], swap) == CTRL0_WORD) &&
> + (load_word([4], swap) & CTRL0_DEC_MASK) &&
> + (load_word([5], swap) == NOP_WORD))
> + *encrypted = true;
> + else
> + *encrypted = false;
> +
> + debug("%s: Found %sencrypted bitstream header at %x %s
> swapping\n",
> + __func__, *encrypted ? "" : "un", (u32
[U-Boot] [PATCH v2 3/4] arm: zynq: Add Nand flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint of memory. This configuration
has only required nand flash support.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- Update memory node as per comment
- Removed intc and fclk as per comment
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-cse-nand.dts | 80 +
configs/zynq_cse_nand_defconfig | 50 ++
3 files changed, 131 insertions(+)
create mode 100644 arch/arm/dts/zynq-cse-nand.dts
create mode 100644 configs/zynq_cse_nand_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a0349a8..71b7c3a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -128,6 +128,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
+ zynq-cse-nand.dtb \
zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
new file mode 100644
index 000..9b1dd19
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NAND board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NAND Board";
+ compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ slcr: slcr@f800 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF800 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper",
+ "swdt", "dbg_trc", "dbg_apb";
+ reg = <0x100 0x100>;
+ };
+ };
+ };
+
+};
+
+ {
+ status = "okay";
+};
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
new file mode 100644
index 000..7c7
[U-Boot] [PATCH v2 2/4] arm: zynq: Dont define SDRAM_BASE and SDRAM_SIZE in .h
Remove the SDRAM_BASE nad SDRAM_SIZE as it can now get these details from DT. Signed-off-by: Siva Durga Prasad Paladugu --- Changes from v1: - Removed commit reference from description as per comment --- include/configs/zynq_cse.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index 2f5843f..adc02f0 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -41,7 +41,4 @@ #undef CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_MALLOC_LEN 0x1000 -#define CONFIG_SYS_SDRAM_BASE 0xfffc -#define CONFIG_SYS_SDRAM_SIZE 0x4 - #endif /* __CONFIG_ZYNQ_CSE_H */ -- 2.7.4 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] arm: zynq: Add parallel NOR flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint OCM memory. This configuration
only has required parallel nor flash support.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- None
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-cse-nor.dts | 88 ++
configs/zynq_cse_nor_defconfig | 50
3 files changed, 139 insertions(+)
create mode 100644 arch/arm/dts/zynq-cse-nor.dts
create mode 100644 configs/zynq_cse_nor_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 71b7c3a..9e29fe6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
zynq-cse-nand.dtb \
+ zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
new file mode 100644
index 000..ba6f9a1
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NOR board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NOR Board";
+ compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@fffc {
+ device_type = "memory";
+ reg = <0xFFFC 0x4>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+ ranges;
+
+ intc: interrupt-controller@f8f01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xF8F01000 0x1000>,
+ <0xF8F00100 0x100>;
+ };
+
+ slcr: slcr@f800 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF800 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ fclk-enable = <0xf>;
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper",
+ "swdt", "d
[U-Boot] [PATCH v2 1/4] lib: fdtdec: Fill initial ram top with DDR start value from dt
Fill initial ram top with DDR base addr value from DT as not filling
it here always assumes it as zero while calculating relocation
offset and hence lead to failures in somecases. This will assumed
as zero if CONFIG_SYS_SDRAM_BASE is not defined.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
Changes from v1:
- None
---
lib/fdtdec.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index f4e8dbf..34ef9b8 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1172,6 +1172,7 @@ int fdtdec_setup_memory_size(void)
}
gd->ram_size = (phys_size_t)(res.end - res.start + 1);
+ gd->ram_top = (unsigned long)res.start;
debug("%s: Initial DRAM size %llx\n", __func__,
(unsigned long long)gd->ram_size);
--
2.7.4
This email and any attachments are intended for the sole use of the named
recipient(s) and contain(s) confidential information that may be proprietary,
privileged or copyrighted under applicable law. If you are not the intended
recipient, do not read, copy, or forward this email message or any attachments.
Delete this email message and any attachments immediately.
___
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[U-Boot] [PATCH v2] xilinx: zynq: Add support to secure images
This patch basically adds two new commands for loadig secure
images/bitstreams.
1. zynq rsa adds support to load secure image which can be both
authenticated or encrypted or both authenticated and encrypted
image in xilinx bootimage(BOOT.bin) format.
2. zynq aes command adds support to decrypted and load encrypted
image either back to DDR or it can load an encrypted bitsream
to PL directly by decrypting it. The image has to be encrypted
using xilinx bootgen tool and to get only the encrypted
image from tool use -split option while invoking bootgen.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- Defined two config synbols for RSA and AES separately
and used them wherever required.
- Used U_BOOT_CMD_KENT as per comment
- Cleared DEVCFG_CTRL_PCAP_RATE_EN_MASK once decryption is
done.
Changes from RFC:
- Moved zynqaes to board/xilinx/zynq/cmds.c and renamed as
"zynq aes".
- Moved boot image parsing code to a separate file.
- Squashed in to a single patch.
- Fixed coding style comments.
---
arch/arm/Kconfig | 1 +
board/xilinx/zynq/Kconfig| 32 +++
board/xilinx/zynq/Makefile | 5 +
board/xilinx/zynq/bootimg.c | 143 +++
board/xilinx/zynq/cmds.c | 556 +++
drivers/fpga/zynqpl.c| 67 ++
include/u-boot/rsa-mod-exp.h | 4 +
include/zynq_bootimg.h | 33 +++
include/zynqpl.h | 5 +
lib/rsa/rsa-mod-exp.c| 52
10 files changed, 898 insertions(+)
create mode 100644 board/xilinx/zynq/Kconfig
create mode 100644 board/xilinx/zynq/bootimg.c
create mode 100644 board/xilinx/zynq/cmds.c
create mode 100644 include/zynq_bootimg.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3e05f79..e78e1a4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1428,6 +1428,7 @@ source "board/toradex/colibri_pxa270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
+source "board/xilinx/zynq/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
source "board/zipitz2/Kconfig"
diff --git a/board/xilinx/zynq/Kconfig b/board/xilinx/zynq/Kconfig
new file mode 100644
index 000..e665c8d
--- /dev/null
+++ b/board/xilinx/zynq/Kconfig
@@ -0,0 +1,32 @@
+# Copyright (c) 2018, Xilinx, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_ZYNQ
+
+config CMD_ZYNQ
+ bool "Enable Zynq specific commands"
+ default y
+ help
+ Enables Zynq specific commands.
+
+config CMD_ZYNQ_AES
+ bool "Enable zynq aes command for decryption of encrypted images"
+ depends on CMD_ZYNQ
+ help
+ Decrypts the encrypted image present in source address
+ and places the decrypted image at destination address.
+
+config CMD_ZYNQ_RSA
+ bool "Enable zynq rsa command for loading secure images"
+ default y
+ depends on CMD_ZYNQ
+ select CMD_ZYNQ_AES
+ help
+ Enabling this will support zynq secure image verification.
+ The secure image is a xilinx specific BOOT.BIN with
+ either authentication or encryption or both encryption
+ and authentication feature enabled while generating
+ BOOT.BIN using Xilinx bootgen tool.
+
+endif
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index 5a76a26..f4996fa 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -18,6 +18,11 @@ $(warning Put custom ps7_init_gpl.c/h to
board/xilinx/zynq/custom_hw_platform/))
endif
endif
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_ZYNQ) += cmds.o
+obj-$(CONFIG_CMD_ZYNQ_RSA) += bootimg.o
+endif
+
obj-$(CONFIG_SPL_BUILD) += $(init-objs)
# Suppress "warning: function declaration isn't a prototype"
diff --git a/board/xilinx/zynq/bootimg.c b/board/xilinx/zynq/bootimg.c
new file mode 100644
index 000..b069e2b
--- /dev/null
+++ b/board/xilinx/zynq/bootimg.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ZYNQ_IMAGE_PHDR_OFFSET 0x09C
+#define ZYNQ_IMAGE_FSBL_LEN_OFFSET 0x040
+#define ZYNQ_PART_HDR_CHKSUM_WORD_COUNT0x0F
+#define ZYNQ_PART_HDR_WORD_COUNT 0x10
+#define ZYNQ_MAXIMUM_IMAGE_WORD_LEN0x4000
+#define MD5_CHECKSUM_SIZE 16
+
+struct headerarray {
+ u32 fields[16];
+};
+
+/*
+ * Check whether the given partition is last partition or not
+ */
+static int zynq_islastpartition(struct headerarray *head)
+{
+ int index;
+
+ debug("%s\n", __func__);
+ if (head->fields[ZYNQ_PART_HDR_CHKSUM_WORD_COUNT] != 0x)
+ return -1;
+
+ for (index = 0; index < ZYNQ_PART_HDR_WORD_COUNT - 1; index++) {
+ if
[U-Boot] [PATCH] arm64: zynqmp: Split emmc configuration into emmc0 and emmc1
This patch splits the current mini emmc configuration into emmc0
and emmc1 configurations because emmc is probed at boot time and on
systems which have only one interface mini configuration is failing on
unused interface. This patch also adds required clock node in dts and
enables CONFIG_MMC_SDHCI_ZYNQ through defconfig.
Signed-off-by: Siva Durga Prasad Paladugu
---
arch/arm/dts/Makefile | 4 +-
...{zynqmp-mini-emmc.dts => zynqmp-mini-emmc0.dts} | 20 ++-
arch/arm/dts/zynqmp-mini-emmc1.dts | 67 ++
...efconfig => xilinx_zynqmp_mini_emmc0_defconfig} | 3 +-
configs/xilinx_zynqmp_mini_emmc1_defconfig | 49
5 files changed, 127 insertions(+), 16 deletions(-)
rename arch/arm/dts/{zynqmp-mini-emmc.dts => zynqmp-mini-emmc0.dts} (77%)
create mode 100644 arch/arm/dts/zynqmp-mini-emmc1.dts
rename configs/{xilinx_zynqmp_mini_emmc_defconfig =>
xilinx_zynqmp_mini_emmc0_defconfig} (94%)
create mode 100644 configs/xilinx_zynqmp_mini_emmc1_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9e29fe6..6367b2d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -147,7 +147,9 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zturn.dtb \
zynq-zybo.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
- zynqmp-mini-emmc.dtb\
+ zynqmp-mini-emmc0.dtb \
+ zynqmp-mini-emmc1.dtb \
+ zynqmp-mini-nand.dtb\
zynqmp-mini-nand.dtb\
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
diff --git a/arch/arm/dts/zynqmp-mini-emmc.dts
b/arch/arm/dts/zynqmp-mini-emmc0.dts
similarity index 77%
rename from arch/arm/dts/zynqmp-mini-emmc.dts
rename to arch/arm/dts/zynqmp-mini-emmc0.dts
index e5b3c5f..24dd1ab 100644
--- a/arch/arm/dts/zynqmp-mini-emmc.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -18,7 +18,6 @@
aliases {
serial0 =
mmc0 =
- mmc1 =
};
chosen {
@@ -36,6 +35,12 @@
u-boot,dm-pre-reloc;
};
+ clk_xin: clk_xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
@@ -50,15 +55,6 @@
clock-names = "clk_xin", "clk_ahb";
xlnx,device_id = <0>;
};
-
- sdhci1: sdhci@ff17 {
- u-boot,dm-pre-reloc;
- compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
- status = "disabled";
- reg = <0x0 0xff17 0x0 0x1000>;
- clock-names = "clk_xin", "clk_ahb";
- xlnx,device_id = <1>;
- };
};
};
@@ -69,7 +65,3 @@
{
status = "okay";
};
-
- {
- status = "okay";
-};
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts
b/arch/arm/dts/zynqmp-mini-emmc1.dts
new file mode 100644
index 000..d1549b6
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad
+ */
+
+/dts-v1/;
+
+/ {
+ model = "ZynqMP MINI EMMC";
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 =
+ mmc0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x2000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ clk_xin: clk_xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ sdhci1: sdhci@ff17 {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ status = "disabled";
+ reg = <0x0 0xff17 0x0 0x1000>;
+ clock-names
[U-Boot] [PATCH 4/4] arm: zynq: Add parallel NOR flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint OCM memory. This configuration
only has required parallel nor flash support.
Signed-off-by: Siva Durga Prasad Paladugu
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-cse-nor.dts | 88 ++
configs/zynq_cse_nor_defconfig | 50
3 files changed, 139 insertions(+)
create mode 100644 arch/arm/dts/zynq-cse-nor.dts
create mode 100644 configs/zynq_cse_nor_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 71b7c3a..9e29fe6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
zynq-cse-nand.dtb \
+ zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
new file mode 100644
index 000..ba6f9a1
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NOR board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NOR Board";
+ compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@fffc {
+ device_type = "memory";
+ reg = <0xFFFC 0x4>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+ ranges;
+
+ intc: interrupt-controller@f8f01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xF8F01000 0x1000>,
+ <0xF8F00100 0x100>;
+ };
+
+ slcr: slcr@f800 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF800 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ fclk-enable = <0xf>;
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper",
+ "swdt", "dbg_trc", "dbg_apb
[U-Boot] [PATCH 2/4] arm: zynq: Dont define SDRAM_BASE and SDRAM_SIZE in .h
Remove the SDRAM_BASE nad SDRAM_SIZE as it can now get these
details from DT using 'commit 327f66622391
("lib: fdtdec: Fill initial ram top with DDR start value from dt")'
Signed-off-by: Siva Durga Prasad Paladugu
---
include/configs/zynq_cse.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h
index 2f5843f..adc02f0 100644
--- a/include/configs/zynq_cse.h
+++ b/include/configs/zynq_cse.h
@@ -41,7 +41,4 @@
#undef CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_MALLOC_LEN 0x1000
-#define CONFIG_SYS_SDRAM_BASE 0xfffc
-#define CONFIG_SYS_SDRAM_SIZE 0x4
-
#endif /* __CONFIG_ZYNQ_CSE_H */
--
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[U-Boot] [PATCH 3/4] arm: zynq: Add Nand flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint of memory. This configuration
has only required nand flash support.
Signed-off-by: Siva Durga Prasad Paladugu
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-cse-nand.dts | 90 +
configs/zynq_cse_nand_defconfig | 50 +++
3 files changed, 141 insertions(+)
create mode 100644 arch/arm/dts/zynq-cse-nand.dts
create mode 100644 configs/zynq_cse_nand_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a0349a8..71b7c3a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -128,6 +128,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
+ zynq-cse-nand.dtb \
zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
new file mode 100644
index 000..9df5f9a
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NAND board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NAND Board";
+ compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@fffc {
+ device_type = "memory";
+ reg = <0x0 0x40>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+ ranges;
+
+ intc: interrupt-controller@f8f01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xF8F01000 0x1000>,
+ <0xF8F00100 0x100>;
+ };
+
+ slcr: slcr@f800 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF800 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ fclk-enable = <0xf>;
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper",
+
[U-Boot] [PATCH 1/4] lib: fdtdec: Fill initial ram top with DDR start value from dt
Fill initial ram top with DDR base addr value from DT as not filling
it here always assumes it as zero while calculating relocation
offset and hence lead to failures in somecases. This will assumed
as zero if CONFIG_SYS_SDRAM_BASE is not defined.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
lib/fdtdec.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index f4e8dbf..34ef9b8 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1172,6 +1172,7 @@ int fdtdec_setup_memory_size(void)
}
gd->ram_size = (phys_size_t)(res.end - res.start + 1);
+ gd->ram_top = (unsigned long)res.start;
debug("%s: Initial DRAM size %llx\n", __func__,
(unsigned long long)gd->ram_size);
--
2.7.4
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Delete this email message and any attachments immediately.
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Re: [U-Boot] [PATCH] xilinx: zynq: Add support to secure images
Hi Stefan, > -Original Message- > From: Stefan Herbrechtsmeier [mailto:ste...@herbrechtsmeier.net] > Sent: Thursday, May 31, 2018 10:57 PM > To: Siva Durga Prasad Paladugu ; u- > b...@lists.denx.de > Cc: michal.si...@xilinx.com > Subject: Re: [U-Boot] [PATCH] xilinx: zynq: Add support to secure images > > Hi Siva, > > Am 31.05.2018 um 12:37 schrieb Siva Durga Prasad Paladugu: > >> -Original Message- > >> From: Stefan Herbrechtsmeier [mailto:ste...@herbrechtsmeier.net] > >> Sent: Thursday, May 31, 2018 3:43 PM > >> To: Siva Durga Prasad Paladugu ; u- > >> b...@lists.denx.de > >> Cc: michal.si...@xilinx.com > >> Subject: Re: [U-Boot] [PATCH] xilinx: zynq: Add support to secure > >> images > >> > >> Am 31.05.2018 um 11:25 schrieb Siva Durga Prasad Paladugu: > >>> This patch basically adds two new commands for loadig secure > >>> images/bitstreams. > >>> 1. zynq rsa adds support to load secure image which can be both > >>> authenticated or encrypted or both authenticated and encrypted > >>> image in xilinx bootimage(BOOT.bin) format. > >>> 2. zynq aes command adds support to decrypted and load encrypted > >>> image either back to DDR or it can load an encrypted bitsream > >>> to PL directly by decrypting it. The image has to be encrypted > >>> using xilinx bootgen tool and to get only the encrypted > >>> image from tool use -split option while invoking bootgen. > >>> > >>> Signed-off-by: Siva Durga Prasad Paladugu > >>> > >>> --- > >>> Changes from RFC: > >>> - Moved zynqaes to board/xilinx/zynq/cmds.c and renamed as > >>> "zynq aes". > >>> - Moved boot image parsing code to a separate file. > >>> - Squashed in to a single patch. > >>> - Fixed coding style comments. > >>> --- > >>>arch/arm/Kconfig | 1 + > >>>board/xilinx/zynq/Kconfig| 26 +++ > >>>board/xilinx/zynq/Makefile | 5 + > >>>board/xilinx/zynq/bootimg.c | 143 > >>>board/xilinx/zynq/cmds.c | 527 > >> +++ > >>>drivers/fpga/zynqpl.c| 65 ++ > >>>include/u-boot/rsa-mod-exp.h | 4 + > >>>include/zynq_bootimg.h | 33 +++ > >>>include/zynqpl.h | 5 + > >>>lib/rsa/rsa-mod-exp.c| 51 + > >>>10 files changed, 860 insertions(+) > >>>create mode 100644 board/xilinx/zynq/Kconfig > >>>create mode 100644 board/xilinx/zynq/bootimg.c > >>>create mode 100644 board/xilinx/zynq/cmds.c > >>>create mode 100644 include/zynq_bootimg.h > >>> > >> [snip] > >> > >>> diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c new > >>> file mode 100644 index 000..6aebec1 > >>> --- /dev/null > >>> +++ b/board/xilinx/zynq/cmds.c > >>> @@ -0,0 +1,527 @@ > >> [snip] > >> > >>> +#ifdef CONFIG_SYS_LONGHELP > >>> +static char zynq_help_text[] = > >>> + "rsa - Verifies the authenticated and encrypted\n" > >>> + " zynq images and loads them back to load\n" > >>> + " addresses as specified in BOOT > >>> image(BOOT.BIN)\n" > >>> + "aes [operation type]\n" > >>> + "Decrypts the encrypted image present in source address\n" > >>> + "and places the decrypted image at destination address\n" > >>> + "zynqaes operations:\n" > >>> + " zynqaes\n" > >>> + " zynqaes load \n" > >>> + " zynqaes loadp \n" > >>> + "if operation type is load or loadp, it loads the encrypted\n" > >>> + "full or partial bitstream on to PL respectively. If no valid\n" > >>> + "operation type specified then it loads decrypted image back\n" > >>> + "to memory and it doesn't support loading PL bistsream\n"; > >>> +#endif > >>> + > >>> +U_BOOT_CMD(zynq, 6, 0, do_zynq, > >>> + "Zynq specific commands RSA/AES verification ", > >>> +zynq_help_te
Re: [U-Boot] [PATCH] xilinx: zynq: Add support to secure images
Hi Stefan,
> -Original Message-
> From: Stefan Herbrechtsmeier [mailto:ste...@herbrechtsmeier.net]
> Sent: Thursday, May 31, 2018 3:43 PM
> To: Siva Durga Prasad Paladugu ; u-
> b...@lists.denx.de
> Cc: michal.si...@xilinx.com
> Subject: Re: [U-Boot] [PATCH] xilinx: zynq: Add support to secure images
>
> Hi Siva,
>
> Am 31.05.2018 um 11:25 schrieb Siva Durga Prasad Paladugu:
> > This patch basically adds two new commands for loadig secure
> > images/bitstreams.
> > 1. zynq rsa adds support to load secure image which can be both
> > authenticated or encrypted or both authenticated and encrypted
> > image in xilinx bootimage(BOOT.bin) format.
> > 2. zynq aes command adds support to decrypted and load encrypted
> > image either back to DDR or it can load an encrypted bitsream
> > to PL directly by decrypting it. The image has to be encrypted
> > using xilinx bootgen tool and to get only the encrypted
> > image from tool use -split option while invoking bootgen.
> >
> > Signed-off-by: Siva Durga Prasad Paladugu
> >
> > ---
> > Changes from RFC:
> > - Moved zynqaes to board/xilinx/zynq/cmds.c and renamed as
> >"zynq aes".
> > - Moved boot image parsing code to a separate file.
> > - Squashed in to a single patch.
> > - Fixed coding style comments.
> > ---
> > arch/arm/Kconfig | 1 +
> > board/xilinx/zynq/Kconfig| 26 +++
> > board/xilinx/zynq/Makefile | 5 +
> > board/xilinx/zynq/bootimg.c | 143
> > board/xilinx/zynq/cmds.c | 527
> +++
> > drivers/fpga/zynqpl.c| 65 ++
> > include/u-boot/rsa-mod-exp.h | 4 +
> > include/zynq_bootimg.h | 33 +++
> > include/zynqpl.h | 5 +
> > lib/rsa/rsa-mod-exp.c| 51 +
> > 10 files changed, 860 insertions(+)
> > create mode 100644 board/xilinx/zynq/Kconfig
> > create mode 100644 board/xilinx/zynq/bootimg.c
> > create mode 100644 board/xilinx/zynq/cmds.c
> > create mode 100644 include/zynq_bootimg.h
> >
>
> [snip]
>
> > diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c new
> > file mode 100644 index 000..6aebec1
> > --- /dev/null
> > +++ b/board/xilinx/zynq/cmds.c
> > @@ -0,0 +1,527 @@
>
> [snip]
>
> > +#ifdef CONFIG_SYS_LONGHELP
> > +static char zynq_help_text[] =
> > + "rsa - Verifies the authenticated and encrypted\n"
> > + " zynq images and loads them back to load\n"
> > + " addresses as specified in BOOT image(BOOT.BIN)\n"
> > + "aes [operation type]\n"
> > + "Decrypts the encrypted image present in source address\n"
> > + "and places the decrypted image at destination address\n"
> > + "zynqaes operations:\n"
> > + " zynqaes\n"
> > + " zynqaes load \n"
> > + " zynqaes loadp \n"
> > + "if operation type is load or loadp, it loads the encrypted\n"
> > + "full or partial bitstream on to PL respectively. If no valid\n"
> > + "operation type specified then it loads decrypted image back\n"
> > + "to memory and it doesn't support loading PL bistsream\n";
> > +#endif
> > +
> > +U_BOOT_CMD(zynq, 6, 0, do_zynq,
> > + "Zynq specific commands RSA/AES verification ",
> > +zynq_help_text );
>
> Why don't you integrate the encrypted fpga image support into the fpga
> command?
>
> The encrypted fpga image could be detected at run time and the only
> difference is a reduced pcap rate.
Its not just handles encrypted fpga images, indeed it handles all encrypted
Images so, that’s why it is here.
>
> > diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index
> > fd37d18..bdac49e 100644
> > --- a/drivers/fpga/zynqpl.c
> > +++ b/drivers/fpga/zynqpl.c
> > @@ -17,6 +17,7 @@
> >
> > #define DEVCFG_CTRL_PCFG_PROG_B0x4000
> > #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK0x1000
> > +#define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x0200
> > #define DEVCFG_ISR_FATAL_ERROR_MASK0x00740040
> > #define DEVCFG_ISR_ERROR_FLAGS_MASK0x00340840
> > #define DEVCFG_ISR_RX_FIFO_OV 0x0004
> > @@ -497,3 +498,67 @@ struct xilinx_fpga_op zynq_op = {
> > .loadfs = zynq_loadfs,
[U-Boot] [PATCH v2 3/3] fpga: zynqmp: Add secure bitstream loading for ZynqMP
This patch adds support for loading secure bitstreams on ZynqMP
platforms. The secure bitstream images has to be generated using
Xilinx bootgen tool.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes for v2:
- None
---
arch/arm/include/asm/arch-zynqmp/sys_proto.h | 6
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 +
drivers/fpga/xilinx.c | 18 ++
drivers/fpga/zynqmppl.c | 48 +++
include/xilinx.h | 4 +++
include/zynqmppl.h| 3 ++
6 files changed, 80 insertions(+)
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 6056bc6..773b930 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -13,8 +13,14 @@
#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC22D
#define KEY_PTR_LEN32
+#define ZYNQMP_FPGA_BIT_AUTH_DDR 1
+#define ZYNQMP_FPGA_BIT_AUTH_OCM 2
+#define ZYNQMP_FPGA_BIT_ENC_USR_KEY3
+#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY4
#define ZYNQMP_FPGA_BIT_NS 5
+#define ZYNQMP_FPGA_AUTH_DDR 1
+
enum {
IDCODE,
VERSION,
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 4cb3959..1379f14 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -31,6 +31,7 @@ CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index 724304a..f513550 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -171,6 +171,24 @@ int xilinx_loadfs(xilinx_desc *desc, const void *buf,
size_t bsize,
}
#endif
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
+struct fpga_secure_info *fpga_sec_info)
+{
+ if (!xilinx_validate(desc, (char *)__func__)) {
+ printf("%s: Invalid device descriptor\n", __func__);
+ return FPGA_FAIL;
+ }
+
+ if (!desc->operations || !desc->operations->loads) {
+ printf("%s: Missing loads operation\n", __func__);
+ return FPGA_FAIL;
+ }
+
+ return desc->operations->loads(desc, buf, bsize, fpga_sec_info);
+}
+#endif
+
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index b57623b..03ffa8c 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -223,6 +223,51 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf,
size_t bsize,
return ret;
}
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
+static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
+ struct fpga_secure_info *fpga_sec_info)
+{
+ int ret;
+ u32 buf_lo, buf_hi;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ u8 flag = 0;
+
+ flush_dcache_range((ulong)buf, (ulong)buf +
+ ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
+
+ if (!fpga_sec_info->encflag)
+ flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
+
+ if (fpga_sec_info->userkey_addr &&
+ fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
+ flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
+ (ulong)fpga_sec_info->userkey_addr +
+ ALIGN(KEY_PTR_LEN,
+CONFIG_SYS_CACHELINE_SIZE));
+ flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
+ }
+
+ if (!fpga_sec_info->authflag)
+ flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
+
+ if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
+ flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
+
+ buf_lo = lower_32_bits((ulong)buf);
+ buf_hi = upper_32_bits((ulong)buf);
+
+ ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
+(u32)(uintptr_t)fpga_sec_info->userkey_addr,
+flag, ret_payload);
+ if (ret)
+ puts("PL FPGA LOAD fail\n");
+ else
+ puts("Bitstream successfully loaded\n");
+
+ return ret;
+}
+#endif
+
static int zynqmp_pcap_info(xilinx_desc *desc)
{
int ret;
@@ -238,5 +283,8 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
struct xilinx_fpga_op zynqmp_op = {
.load = zynqmp_load,
+#if defined CONFIG_CMD_FPGA_LOAD_SECURE
+ .loads = zynqmp_loads,
+#endif
.info = zynqm
[U-Boot] [PATCH v2 1/3] cmd: fpga: Reorder the arguments parsing code
This patch modifies the arguments parsing code by parsing
based on requested operation for fpga loadfs and then
parses the most common/basic args for other fpga load
commands. This makes it easy for new command extensions
or additions especially the commands with more args.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes for v2:
- Correct the argc check as per comment.
---
cmd/fpga.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/cmd/fpga.c b/cmd/fpga.c
index 14ad4e5..3f09d42 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga.c
@@ -60,15 +60,31 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
if (datastr)
fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
- switch (argc) {
+ if (argc > 9 || argc < 2) {
+ debug("%s: Too many or too few args (%d)\n", __func__, argc);
+ return CMD_RET_USAGE;
+ }
+
+ op = (int)fpga_get_op(argv[1]);
+
+ switch (op) {
#if defined(CONFIG_CMD_FPGA_LOADFS)
- case 9:
+ case FPGA_LOADFS:
+ if (argc < 9)
+ return CMD_RET_USAGE;
fpga_fsinfo.blocksize = (unsigned int)
-simple_strtoul(argv[5], NULL, 16);
+ simple_strtoul(argv[5], NULL, 16);
fpga_fsinfo.interface = argv[6];
fpga_fsinfo.dev_part = argv[7];
fpga_fsinfo.filename = argv[8];
+ argc = 5;
+ break;
#endif
+ default:
+ break;
+ }
+
+ switch (argc) {
case 5: /* fpga */
data_size = simple_strtoul(argv[4], NULL, 16);
@@ -117,15 +133,6 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
__func__, (ulong)fpga_data);
dev = FPGA_INVALID_DEVICE; /* reset device num */
}
-
- case 2: /* fpga */
- op = (int)fpga_get_op(argv[1]);
- break;
-
- default:
- debug("%s: Too many or too few args (%d)\n", __func__, argc);
- op = FPGA_NONE; /* force usage display */
- break;
}
if (dev == FPGA_INVALID_DEVICE) {
--
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[U-Boot] [PATCH v2 2/3] cmd: fpga: Add support to load secure bitstreams
This patch adds support to load secure bitstreams(authenticated or
encrypted or both). As of now, this feature is added and tested only
for xilinx bitstreams and the secure bitstream was generated using
xilinx bootgen tool, but the command is defined in more generic way.
Command example to load authenticated and device key
encrypted bitstream is as follows
"fpga loads 0 10 200 0 1"
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes for v2:
- None
---
cmd/Kconfig | 7 ++
cmd/fpga.c | 62 -
drivers/fpga/fpga.c | 29 +
include/fpga.h | 11 ++
4 files changed, 108 insertions(+), 1 deletion(-)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 38406fc..9b9eb94 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -697,6 +697,13 @@ config CMD_FPGA_LOADP
Supports loading an FPGA device from a bitstream buffer containing
a partial bitstream.
+config CMD_FPGA_LOAD_SECURE
+ bool "fpga loads - loads secure bitstreams (Xilinx only)"
+ depends on CMD_FPGA
+ help
+ Enables the fpga loads command which is used to load secure
+ (authenticated or encrypted or both) bitstreams on to FPGA.
+
config CMD_FPGAD
bool "fpgad - dump FPGA registers"
help
diff --git a/cmd/fpga.c b/cmd/fpga.c
index 3f09d42..74ae80c 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga.c
@@ -27,6 +27,7 @@ enum {
FPGA_LOADP,
FPGA_LOADBP,
FPGA_LOADFS,
+ FPGA_LOADS,
};
/* - */
@@ -54,6 +55,11 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
fpga_fs_info fpga_fsinfo;
fpga_fsinfo.fstype = FS_TYPE_ANY;
#endif
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+ struct fpga_secure_info fpga_sec_info;
+
+ memset(_sec_info, 0, sizeof(fpga_sec_info));
+#endif
if (devstr)
dev = (int) simple_strtoul(devstr, NULL, 16);
@@ -80,6 +86,19 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
argc = 5;
break;
#endif
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+ case FPGA_LOADS:
+ if (argc < 7)
+ return CMD_RET_USAGE;
+ if (argc == 8)
+ fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
+simple_strtoull(argv[7],
+NULL, 16);
+ fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16);
+ fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16);
+ argc = 5;
+ break;
+#endif
default:
break;
}
@@ -150,6 +169,22 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
!fpga_fsinfo.filename)
wrong_parms = 1;
+ break;
+#endif
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+ case FPGA_LOADS:
+ if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
+ fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
+ puts("ERR: use for NonSecure bitstream\n");
+ wrong_parms = 1;
+ }
+
+ if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
+ !fpga_sec_info.userkey_addr) {
+ wrong_parms = 1;
+ puts("ERR:User key not provided\n");
+ }
+ break;
#endif
case FPGA_LOAD:
case FPGA_LOADP:
@@ -206,6 +241,12 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
break;
#endif
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+ case FPGA_LOADS:
+ rc = fpga_loads(dev, fpga_data, data_size, _sec_info);
+ break;
+#endif
+
#if defined(CONFIG_CMD_FPGA_LOADMK)
case FPGA_LOADMK:
switch (genimg_get_format(fpga_data)) {
@@ -339,6 +380,10 @@ static int fpga_get_op(char *opstr)
#endif
else if (!strcmp("dump", opstr))
op = FPGA_DUMP;
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+ else if (!strcmp("loads", opstr))
+ op = FPGA_LOADS;
+#endif
if (op == FPGA_NONE)
printf("Unknown fpga operation \"%s\"\n", opstr);
@@ -346,7 +391,7 @@ static int fpga_get_op(char *opstr)
return op;
}
-#if defined(CONFIG_CMD_FPGA_LOADFS)
+#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
U_BOOT_CMD(fpga, 9, 1, do_fpga,
#else
U_BOOT_CMD(fpga, 6, 1, do_fpga,
@@ -381,4 +426,19 @@ U_BOOT_CMD(fpga, 6, 1, do_fp
[U-Boot] [PATCH] xilinx: zynq: Add support to secure images
This patch basically adds two new commands for loadig secure
images/bitstreams.
1. zynq rsa adds support to load secure image which can be both
authenticated or encrypted or both authenticated and encrypted
image in xilinx bootimage(BOOT.bin) format.
2. zynq aes command adds support to decrypted and load encrypted
image either back to DDR or it can load an encrypted bitsream
to PL directly by decrypting it. The image has to be encrypted
using xilinx bootgen tool and to get only the encrypted
image from tool use -split option while invoking bootgen.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from RFC:
- Moved zynqaes to board/xilinx/zynq/cmds.c and renamed as
"zynq aes".
- Moved boot image parsing code to a separate file.
- Squashed in to a single patch.
- Fixed coding style comments.
---
arch/arm/Kconfig | 1 +
board/xilinx/zynq/Kconfig| 26 +++
board/xilinx/zynq/Makefile | 5 +
board/xilinx/zynq/bootimg.c | 143
board/xilinx/zynq/cmds.c | 527 +++
drivers/fpga/zynqpl.c| 65 ++
include/u-boot/rsa-mod-exp.h | 4 +
include/zynq_bootimg.h | 33 +++
include/zynqpl.h | 5 +
lib/rsa/rsa-mod-exp.c| 51 +
10 files changed, 860 insertions(+)
create mode 100644 board/xilinx/zynq/Kconfig
create mode 100644 board/xilinx/zynq/bootimg.c
create mode 100644 board/xilinx/zynq/cmds.c
create mode 100644 include/zynq_bootimg.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3e05f79..e78e1a4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1428,6 +1428,7 @@ source "board/toradex/colibri_pxa270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
+source "board/xilinx/zynq/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
source "board/zipitz2/Kconfig"
diff --git a/board/xilinx/zynq/Kconfig b/board/xilinx/zynq/Kconfig
new file mode 100644
index 000..54d71dc
--- /dev/null
+++ b/board/xilinx/zynq/Kconfig
@@ -0,0 +1,26 @@
+# Copyright (c) 2018, Xilinx, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_ZYNQ
+
+config CMD_ZYNQ_AES
+ bool "Zynq AES"
+ default y
+ help
+ Decrypts the encrypted image present in source address
+ and places the decrypted image at destination address.
+
+config CMD_ZYNQ
+ bool "Enable ZynqMP specific commands"
+ default y
+ depends on CMD_ZYNQ_AES
+ help
+ Enable Zynq specific commands like "zynq rsa"
+ which is used for zynq secure image verification.
+ The secure image is a xilinx specific BOOT.BIN with
+ either authentication or encryption or both encryption
+ and authentication feature enabled while generating
+ BOOT.BIN using Xilinx bootgen tool.
+
+endif
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index 5a76a26..9b63dd7 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -18,6 +18,11 @@ $(warning Put custom ps7_init_gpl.c/h to
board/xilinx/zynq/custom_hw_platform/))
endif
endif
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_ZYNQ) += cmds.o
+obj-$(CONFIG_CMD_ZYNQ) += bootimg.o
+endif
+
obj-$(CONFIG_SPL_BUILD) += $(init-objs)
# Suppress "warning: function declaration isn't a prototype"
diff --git a/board/xilinx/zynq/bootimg.c b/board/xilinx/zynq/bootimg.c
new file mode 100644
index 000..b069e2b
--- /dev/null
+++ b/board/xilinx/zynq/bootimg.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ZYNQ_IMAGE_PHDR_OFFSET 0x09C
+#define ZYNQ_IMAGE_FSBL_LEN_OFFSET 0x040
+#define ZYNQ_PART_HDR_CHKSUM_WORD_COUNT0x0F
+#define ZYNQ_PART_HDR_WORD_COUNT 0x10
+#define ZYNQ_MAXIMUM_IMAGE_WORD_LEN0x4000
+#define MD5_CHECKSUM_SIZE 16
+
+struct headerarray {
+ u32 fields[16];
+};
+
+/*
+ * Check whether the given partition is last partition or not
+ */
+static int zynq_islastpartition(struct headerarray *head)
+{
+ int index;
+
+ debug("%s\n", __func__);
+ if (head->fields[ZYNQ_PART_HDR_CHKSUM_WORD_COUNT] != 0x)
+ return -1;
+
+ for (index = 0; index < ZYNQ_PART_HDR_WORD_COUNT - 1; index++) {
+ if (head->fields[index] != 0x0)
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Get the partition count from the partition header
+ */
+int zynq_get_part_count(struct partition_hdr *part_hdr_info)
+{
+ u32 count = 0;
+ struct headerarray *hap;
+
+ debug("%s\n", __func__);
+
+ for (count = 0; count < ZYNQ_MAX_PARTITION_NUMBER; cou
Re: [U-Boot] [PATCH 2/3] cmd: fpga: Add support to load secure bitstreams
Hi,
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Thursday, May 31, 2018 11:29 AM
> To: Siva Durga Prasad Paladugu ; u-
> b...@lists.denx.de
> Cc: michal.si...@xilinx.com
> Subject: Re: [PATCH 2/3] cmd: fpga: Add support to load secure bitstreams
>
> On 29.5.2018 16:22, Siva Durga Prasad Paladugu wrote:
> > This patch adds support to load secure bitstreams(authenticated or
> > encrypted or both). As of now, this feature is added and tested only
> > for xilinx bitstreams and the secure bitstream was generated using
> > xilinx bootgen tool, but the command is defined in more generic way.
> >
> > Command example to load authenticated and device key encrypted
> > bitstream is as follows "fpga loads 0 10 200 0 1"
> >
> > Signed-off-by: Siva Durga Prasad Paladugu
> >
> > ---
> > cmd/Kconfig | 7 ++
> > cmd/fpga.c | 62
> -
> > drivers/fpga/fpga.c | 29 +
> > include/fpga.h | 11 ++
> > 4 files changed, 108 insertions(+), 1 deletion(-)
> >
> > diff --git a/cmd/Kconfig b/cmd/Kconfig index 38406fc..9b9eb94 100644
> > --- a/cmd/Kconfig
> > +++ b/cmd/Kconfig
> > @@ -697,6 +697,13 @@ config CMD_FPGA_LOADP
> > Supports loading an FPGA device from a bitstream buffer
> containing
> > a partial bitstream.
> >
> > +config CMD_FPGA_LOAD_SECURE
> > + bool "fpga loads - loads secure bitstreams (Xilinx only)"
> > + depends on CMD_FPGA
> > + help
> > + Enables the fpga loads command which is used to load secure
> > + (authenticated or encrypted or both) bitstreams on to FPGA.
> > +
> > config CMD_FPGAD
> > bool "fpgad - dump FPGA registers"
> > help
> > diff --git a/cmd/fpga.c b/cmd/fpga.c
> > index 0981826..ad716a0 100644
> > --- a/cmd/fpga.c
> > +++ b/cmd/fpga.c
> > @@ -27,6 +27,7 @@ enum {
> > FPGA_LOADP,
> > FPGA_LOADBP,
> > FPGA_LOADFS,
> > + FPGA_LOADS,
> > };
> >
> > /*
> > -
> > */ @@ -54,6 +55,11
> @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
> > fpga_fs_info fpga_fsinfo;
> > fpga_fsinfo.fstype = FS_TYPE_ANY;
> > #endif
> > +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
> > + struct fpga_secure_info fpga_sec_info;
> > +
> > + memset(_sec_info, 0, sizeof(fpga_sec_info)); #endif
> >
> > if (devstr)
> > dev = (int) simple_strtoul(devstr, NULL, 16); @@ -80,6
> +86,19 @@
> > int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
> > argc = 5;
> > break;
> > #endif
> > +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
> > + case FPGA_LOADS:
> > + if (argc < 7)
> > + return CMD_RET_USAGE;
> > + if (argc == 8)
> > + fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
> > +simple_strtoull(argv[7],
> > +NULL, 16);
> > + fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL,
> 16);
> > + fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL,
> 16);
> > + argc = 5;
> > + break;
> > +#endif
> > default:
> > break;
> > }
> > @@ -150,6 +169,22 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc,
> char *const argv[])
> > if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
> > !fpga_fsinfo.filename)
> > wrong_parms = 1;
> > + break;
> > +#endif
> > +#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
> > + case FPGA_LOADS:
> > + if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH
> &&
> > + fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
> > + puts("ERR: use for NonSecure
> bitstream\n");
> > + wrong_parms = 1;
> > + }
> > +
> > + if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
> > + !fpga_sec_info.userkey_addr) {
> > + wrong_parms = 1;
> > + puts("ERR:User key not provided\n");
> > + }
> > + break;
>
> I have created so
Re: [U-Boot] [PATCH 1/3] cmd: fpga: Reorder the arguments parsing code
Hi,
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Wednesday, May 30, 2018 8:37 PM
> To: Siva Durga Prasad Paladugu ; u-
> b...@lists.denx.de
> Cc: michal.si...@xilinx.com
> Subject: Re: [PATCH 1/3] cmd: fpga: Reorder the arguments parsing code
>
> On 29.5.2018 16:22, Siva Durga Prasad Paladugu wrote:
> > This patch modifies the arguments parsing code by parsing based on
> > requested operation for fpga loadfs and then parses the most
> > common/basic args for other fpga load commands. This makes it easy for
> > new command extensions or additions especially the commands with
> more
> > args.
> >
> > Signed-off-by: Siva Durga Prasad Paladugu
> >
> > ---
> > cmd/fpga.c | 31 +++
> > 1 file changed, 19 insertions(+), 12 deletions(-)
> >
> > diff --git a/cmd/fpga.c b/cmd/fpga.c
> > index 14ad4e5..0981826 100644
> > --- a/cmd/fpga.c
> > +++ b/cmd/fpga.c
> > @@ -60,15 +60,31 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc,
> char *const argv[])
> > if (datastr)
> > fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
> >
> > - switch (argc) {
> > + if (argc > 9 && argc < 3) {
>
> && is completely broken here.
> Also there is an option to use fpga and fpgadata variable and 2 args are
> valid too.
:-) Yes, thanks for catching it. Will correct and send next version.
Thanks,
Siva
>
> Thanks,
> Michal
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[U-Boot] [PATCH v2 1/2] mmc: sdhci: Update sdhci_send_command() to handle HS200
This patch updates sdhci_send_command() to handle MMC
HS200 tuning command.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- Fixed spacings as per comment
---
drivers/mmc/sdhci.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 400f87e..40e28ab 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -161,7 +161,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
mmc_cmd *cmd,
/* We shouldn't wait for data inihibit for stop commands, even
though they might use busy signaling */
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
mask &= ~SDHCI_DATA_INHIBIT;
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
@@ -183,7 +184,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
mmc_cmd *cmd,
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_INT_RESPONSE;
- if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
mask = SDHCI_INT_DATA_AVAIL;
if (!(cmd->resp_type & MMC_RSP_PRESENT))
@@ -201,7 +203,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
mmc_cmd *cmd,
flags |= SDHCI_CMD_CRC;
if (cmd->resp_type & MMC_RSP_OPCODE)
flags |= SDHCI_CMD_INDEX;
- if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
flags |= SDHCI_CMD_DATA;
/* Set Transfer mode regarding to data flag */
--
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[U-Boot] [PATCH v2 2/2] mmc: zynqmp: Add HS200 modes support for ZynqMP
This patch adds HS200 suuport for ZynqMP and enables
the same for ZC1751 DC1 board which has eMMC on it.
Signed-off-by: Siva Durga Prasad Paladugu
---
Changes from v1:
- Fixed coding style as per comment
---
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
drivers/mmc/zynq_sdhci.c | 25
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index f5a3334..96abf61 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -54,6 +54,7 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index f99731f..ea5af47 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -32,12 +32,21 @@ struct arasan_sdhci_priv {
};
#if defined(CONFIG_ARCH_ZYNQMP)
+#define MMC_HS200_BUS_SPEED5
+
static const u8 mode2timing[] = {
-[UHS_SDR12] = UHS_SDR12_BUS_SPEED,
-[UHS_SDR25] = UHS_SDR25_BUS_SPEED,
-[UHS_SDR50] = UHS_SDR50_BUS_SPEED,
-[UHS_SDR104] = UHS_SDR104_BUS_SPEED,
-[UHS_DDR50] = UHS_DDR50_BUS_SPEED,
+ [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
+ [SD_LEGACY] = UHS_SDR12_BUS_SPEED,
+ [MMC_HS] = HIGH_SPEED_BUS_SPEED,
+ [SD_HS] = HIGH_SPEED_BUS_SPEED,
+ [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
+ [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
+ [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
+ [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
+ [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
+ [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
+ [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
+ [MMC_HS_200] = MMC_HS200_BUS_SPEED,
};
#define SDHCI_HOST_CTRL2 0x3E
@@ -160,9 +169,6 @@ static void arasan_sdhci_set_tapdelay(struct sdhci_host
*host)
struct mmc *mmc = (struct mmc *)host->mmc;
u8 uhsmode;
- if (!IS_SD(mmc))
- return;
-
uhsmode = mode2timing[mmc->selected_mode];
if (uhsmode >= UHS_SDR25_BUS_SPEED)
@@ -175,6 +181,9 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host
*host)
struct mmc *mmc = (struct mmc *)host->mmc;
u32 reg;
+ if (!IS_SD(mmc))
+ return;
+
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
reg |= SDHCI_18V_SIGNAL;
--
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[U-Boot] [PATCH 3/3] fpga: zynqmp: Add secure bitstream loading for ZynqMP
This patch adds support for loading secure bitstreams on ZynqMP
platforms. The secure bitstream images has to be generated using
Xilinx bootgen tool.
Signed-off-by: Siva Durga Prasad Paladugu
---
arch/arm/include/asm/arch-zynqmp/sys_proto.h | 6
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 +
drivers/fpga/xilinx.c | 18 ++
drivers/fpga/zynqmppl.c | 48 +++
include/xilinx.h | 4 +++
include/zynqmppl.h| 3 ++
6 files changed, 80 insertions(+)
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 6056bc6..773b930 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -13,8 +13,14 @@
#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC22D
#define KEY_PTR_LEN32
+#define ZYNQMP_FPGA_BIT_AUTH_DDR 1
+#define ZYNQMP_FPGA_BIT_AUTH_OCM 2
+#define ZYNQMP_FPGA_BIT_ENC_USR_KEY3
+#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY4
#define ZYNQMP_FPGA_BIT_NS 5
+#define ZYNQMP_FPGA_AUTH_DDR 1
+
enum {
IDCODE,
VERSION,
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index 4cb3959..1379f14 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -31,6 +31,7 @@ CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index 724304a..f513550 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -171,6 +171,24 @@ int xilinx_loadfs(xilinx_desc *desc, const void *buf,
size_t bsize,
}
#endif
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
+struct fpga_secure_info *fpga_sec_info)
+{
+ if (!xilinx_validate(desc, (char *)__func__)) {
+ printf("%s: Invalid device descriptor\n", __func__);
+ return FPGA_FAIL;
+ }
+
+ if (!desc->operations || !desc->operations->loads) {
+ printf("%s: Missing loads operation\n", __func__);
+ return FPGA_FAIL;
+ }
+
+ return desc->operations->loads(desc, buf, bsize, fpga_sec_info);
+}
+#endif
+
int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index b57623b..03ffa8c 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -223,6 +223,51 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf,
size_t bsize,
return ret;
}
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
+static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
+ struct fpga_secure_info *fpga_sec_info)
+{
+ int ret;
+ u32 buf_lo, buf_hi;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ u8 flag = 0;
+
+ flush_dcache_range((ulong)buf, (ulong)buf +
+ ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
+
+ if (!fpga_sec_info->encflag)
+ flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
+
+ if (fpga_sec_info->userkey_addr &&
+ fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
+ flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
+ (ulong)fpga_sec_info->userkey_addr +
+ ALIGN(KEY_PTR_LEN,
+CONFIG_SYS_CACHELINE_SIZE));
+ flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
+ }
+
+ if (!fpga_sec_info->authflag)
+ flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
+
+ if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
+ flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
+
+ buf_lo = lower_32_bits((ulong)buf);
+ buf_hi = upper_32_bits((ulong)buf);
+
+ ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
+(u32)(uintptr_t)fpga_sec_info->userkey_addr,
+flag, ret_payload);
+ if (ret)
+ puts("PL FPGA LOAD fail\n");
+ else
+ puts("Bitstream successfully loaded\n");
+
+ return ret;
+}
+#endif
+
static int zynqmp_pcap_info(xilinx_desc *desc)
{
int ret;
@@ -238,5 +283,8 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
struct xilinx_fpga_op zynqmp_op = {
.load = zynqmp_load,
+#if defined CONFIG_CMD_FPGA_LOAD_SECURE
+ .loads = zynqmp_loads,
+#endif
.info = zynqmp_pcap_info,
};
diff --git a
[U-Boot] [PATCH 2/3] cmd: fpga: Add support to load secure bitstreams
This patch adds support to load secure bitstreams(authenticated or
encrypted or both). As of now, this feature is added and tested only
for xilinx bitstreams and the secure bitstream was generated using
xilinx bootgen tool, but the command is defined in more generic way.
Command example to load authenticated and device key
encrypted bitstream is as follows
"fpga loads 0 10 200 0 1"
Signed-off-by: Siva Durga Prasad Paladugu
---
cmd/Kconfig | 7 ++
cmd/fpga.c | 62 -
drivers/fpga/fpga.c | 29 +
include/fpga.h | 11 ++
4 files changed, 108 insertions(+), 1 deletion(-)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 38406fc..9b9eb94 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -697,6 +697,13 @@ config CMD_FPGA_LOADP
Supports loading an FPGA device from a bitstream buffer containing
a partial bitstream.
+config CMD_FPGA_LOAD_SECURE
+ bool "fpga loads - loads secure bitstreams (Xilinx only)"
+ depends on CMD_FPGA
+ help
+ Enables the fpga loads command which is used to load secure
+ (authenticated or encrypted or both) bitstreams on to FPGA.
+
config CMD_FPGAD
bool "fpgad - dump FPGA registers"
help
diff --git a/cmd/fpga.c b/cmd/fpga.c
index 0981826..ad716a0 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga.c
@@ -27,6 +27,7 @@ enum {
FPGA_LOADP,
FPGA_LOADBP,
FPGA_LOADFS,
+ FPGA_LOADS,
};
/* - */
@@ -54,6 +55,11 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
fpga_fs_info fpga_fsinfo;
fpga_fsinfo.fstype = FS_TYPE_ANY;
#endif
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+ struct fpga_secure_info fpga_sec_info;
+
+ memset(_sec_info, 0, sizeof(fpga_sec_info));
+#endif
if (devstr)
dev = (int) simple_strtoul(devstr, NULL, 16);
@@ -80,6 +86,19 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
argc = 5;
break;
#endif
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+ case FPGA_LOADS:
+ if (argc < 7)
+ return CMD_RET_USAGE;
+ if (argc == 8)
+ fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
+simple_strtoull(argv[7],
+NULL, 16);
+ fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16);
+ fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16);
+ argc = 5;
+ break;
+#endif
default:
break;
}
@@ -150,6 +169,22 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
!fpga_fsinfo.filename)
wrong_parms = 1;
+ break;
+#endif
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+ case FPGA_LOADS:
+ if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
+ fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
+ puts("ERR: use for NonSecure bitstream\n");
+ wrong_parms = 1;
+ }
+
+ if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
+ !fpga_sec_info.userkey_addr) {
+ wrong_parms = 1;
+ puts("ERR:User key not provided\n");
+ }
+ break;
#endif
case FPGA_LOAD:
case FPGA_LOADP:
@@ -206,6 +241,12 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
break;
#endif
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+ case FPGA_LOADS:
+ rc = fpga_loads(dev, fpga_data, data_size, _sec_info);
+ break;
+#endif
+
#if defined(CONFIG_CMD_FPGA_LOADMK)
case FPGA_LOADMK:
switch (genimg_get_format(fpga_data)) {
@@ -339,6 +380,10 @@ static int fpga_get_op(char *opstr)
#endif
else if (!strcmp("dump", opstr))
op = FPGA_DUMP;
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
+ else if (!strcmp("loads", opstr))
+ op = FPGA_LOADS;
+#endif
if (op == FPGA_NONE)
printf("Unknown fpga operation \"%s\"\n", opstr);
@@ -346,7 +391,7 @@ static int fpga_get_op(char *opstr)
return op;
}
-#if defined(CONFIG_CMD_FPGA_LOADFS)
+#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
U_BOOT_CMD(fpga, 9, 1, do_fpga,
#else
U_BOOT_CMD(fpga, 6, 1, do_fpga,
@@ -381,4 +426,19 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga,
"\tsubim
[U-Boot] [PATCH 1/3] cmd: fpga: Reorder the arguments parsing code
This patch modifies the arguments parsing code by parsing
based on requested operation for fpga loadfs and then
parses the most common/basic args for other fpga load
commands. This makes it easy for new command extensions
or additions especially the commands with more args.
Signed-off-by: Siva Durga Prasad Paladugu
---
cmd/fpga.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/cmd/fpga.c b/cmd/fpga.c
index 14ad4e5..0981826 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga.c
@@ -60,15 +60,31 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
if (datastr)
fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
- switch (argc) {
+ if (argc > 9 && argc < 3) {
+ debug("%s: Too many or too few args (%d)\n", __func__, argc);
+ return CMD_RET_USAGE;
+ }
+
+ op = (int)fpga_get_op(argv[1]);
+
+ switch (op) {
#if defined(CONFIG_CMD_FPGA_LOADFS)
- case 9:
+ case FPGA_LOADFS:
+ if (argc < 9)
+ return CMD_RET_USAGE;
fpga_fsinfo.blocksize = (unsigned int)
-simple_strtoul(argv[5], NULL, 16);
+ simple_strtoul(argv[5], NULL, 16);
fpga_fsinfo.interface = argv[6];
fpga_fsinfo.dev_part = argv[7];
fpga_fsinfo.filename = argv[8];
+ argc = 5;
+ break;
#endif
+ default:
+ break;
+ }
+
+ switch (argc) {
case 5: /* fpga */
data_size = simple_strtoul(argv[4], NULL, 16);
@@ -117,15 +133,6 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char
*const argv[])
__func__, (ulong)fpga_data);
dev = FPGA_INVALID_DEVICE; /* reset device num */
}
-
- case 2: /* fpga */
- op = (int)fpga_get_op(argv[1]);
- break;
-
- default:
- debug("%s: Too many or too few args (%d)\n", __func__, argc);
- op = FPGA_NONE; /* force usage display */
- break;
}
if (dev == FPGA_INVALID_DEVICE) {
--
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Re: [U-Boot] [PATCH] sf: Enable FSR polling on N25Q256(A)
Hi,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, May 29, 2018 10:22 AM
> To: Marek Vasut ; Siva Durga Prasad Paladugu
>
> Cc: U-Boot Mailing List ; Tom Rini
>
> Subject: Re: [U-Boot] [PATCH] sf: Enable FSR polling on N25Q256(A)
>
> + Siva
>
> On Fri, May 25, 2018 at 1:28 AM, Marek Vasut wrote:
> > The N25Q256(A) datasheet clearly states that this device does have a
> > Flag Status Register and does update FSR PEC bit 7 during Program and
> > Erase cycles to indicate the cycle is in progress. Enable the FSR PEC
> > bit polling on this device to prevent data corruption.
> >
> > Signed-off-by: Marek Vasut
> > Cc: Jagan Teki
> > Cc: Tom Rini
> > ---
> > drivers/mtd/spi/spi_flash_ids.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mtd/spi/spi_flash_ids.c
> > b/drivers/mtd/spi/spi_flash_ids.c index 3b8f254ca2..fbc1bb6a5e 100644
> > --- a/drivers/mtd/spi/spi_flash_ids.c
> > +++ b/drivers/mtd/spi/spi_flash_ids.c
> > @@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
> > {"n25q64a",INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL |
> WR_QPP | SECT_4K) },
> > {"n25q128",INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL |
> WR_QPP) },
> > {"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL |
> WR_QPP) },
> > - {"n25q256",INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL |
> WR_QPP | SECT_4K) },
> > - {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL |
> WR_QPP | SECT_4K) },
> > + {"n25q256",INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL |
> WR_QPP | E_FSR | SECT_4K) },
> > + {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL |
> WR_QPP | E_FSR | SECT_4K) },
>
> FSR is required to poll flag status instead of read status only from Micron
> n25q512 because 512 is divided into two 256 dies so FSR is used for polling
> each die. In case of n25q256 the flash is single entity (doesn't have die
> concept) so there is no need to poll FSR.
>
> This is what I understood when I add initial FSR support
> 0f6232801cee4f45dbdb0cec45f71172c9b617ca
PEC bit in Flag status register on N25Q256A will apply only for PROGRAM/ERASE
commands but not to WRITE command cycles where as WIP bit in Status register
will be applicable to all(PROGRAM/ERASE and WRITE).
Here is the snippet from N25Q256A datasheet about PEC bit in FSR.
"These program/erase controller settings apply only to PROGRAM or ERASE
command cycles
in progress; they do not apply to a WRITE command cycle in progress."
Regarding PEC bit in FSR of N25Q512(where it has two 256MB dies) here, it is
mostly used to find out whether WRITE command(Write Status and Write Non
volatile config Register) completed successfully for both dies. This is ensured
by reading FSR twice with S# toggled in between and checking the PEC bit to be
1 in both the cases.
Thanks,
Siva
>
>
> Jagan.
>
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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[U-Boot] [PATCH 1/2] mmc: sdhci: Update sdhci_send_command() to handle HS200
This patch updates sdhci_send_command() to handle MMC
HS200 tuning command.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.palad...@xilinx.com>
---
drivers/mmc/sdhci.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 400f87e..1bbcf4b 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -161,7 +161,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
mmc_cmd *cmd,
/* We shouldn't wait for data inihibit for stop commands, even
though they might use busy signaling */
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
mask &= ~SDHCI_DATA_INHIBIT;
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
@@ -183,7 +184,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
mmc_cmd *cmd,
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_INT_RESPONSE;
- if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
mask = SDHCI_INT_DATA_AVAIL;
if (!(cmd->resp_type & MMC_RSP_PRESENT))
@@ -201,7 +203,8 @@ static int sdhci_send_command(struct mmc *mmc, struct
mmc_cmd *cmd,
flags |= SDHCI_CMD_CRC;
if (cmd->resp_type & MMC_RSP_OPCODE)
flags |= SDHCI_CMD_INDEX;
- if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
+ if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
flags |= SDHCI_CMD_DATA;
/* Set Transfer mode regarding to data flag */
--
2.7.4
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[U-Boot] [PATCH 2/2] mmc: zynqmp: Add HS200 modes support for ZynqMP
This patch adds HS200 suuport for ZynqMP and enables
the same for ZC1751 DC1 board which has eMMC on it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.palad...@xilinx.com>
---
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
drivers/mmc/zynq_sdhci.c | 25
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index f5a3334..96abf61 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -54,6 +54,7 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index f99731f..32c2dc6 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -32,12 +32,21 @@ struct arasan_sdhci_priv {
};
#if defined(CONFIG_ARCH_ZYNQMP)
+#define MMC_HS200_BUS_SPEED5
+
static const u8 mode2timing[] = {
-[UHS_SDR12] = UHS_SDR12_BUS_SPEED,
-[UHS_SDR25] = UHS_SDR25_BUS_SPEED,
-[UHS_SDR50] = UHS_SDR50_BUS_SPEED,
-[UHS_SDR104] = UHS_SDR104_BUS_SPEED,
-[UHS_DDR50] = UHS_DDR50_BUS_SPEED,
+ [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
+ [SD_LEGACY] = UHS_SDR12_BUS_SPEED,
+ [MMC_HS] = HIGH_SPEED_BUS_SPEED,
+ [SD_HS] = HIGH_SPEED_BUS_SPEED,
+ [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
+ [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
+ [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
+ [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
+ [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
+ [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
+ [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
+ [MMC_HS_200] = MMC_HS200_BUS_SPEED,
};
#define SDHCI_HOST_CTRL2 0x3E
@@ -160,9 +169,6 @@ static void arasan_sdhci_set_tapdelay(struct sdhci_host
*host)
struct mmc *mmc = (struct mmc *)host->mmc;
u8 uhsmode;
- if (!IS_SD(mmc))
- return;
-
uhsmode = mode2timing[mmc->selected_mode];
if (uhsmode >= UHS_SDR25_BUS_SPEED)
@@ -175,6 +181,9 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host
*host)
struct mmc *mmc = (struct mmc *)host->mmc;
u32 reg;
+ if (!IS_SD(mmc))
+ return;
+
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
reg |= SDHCI_18V_SIGNAL;
--
2.7.4
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Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
Hi, > -Original Message- > From: Jagan Teki [mailto:jagannadh.t...@gmail.com] > Sent: Wednesday, May 09, 2018 4:47 PM > To: Siva Durga Prasad Paladugu <siva...@xilinx.com> > Cc: Jagan Teki <ja...@amarulasolutions.com>; U-Boot-Denx b...@lists.denx.de>; michal.si...@xilinx.com > Subject: Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for > ZynqMP qspi driver > > On Wed, May 9, 2018 at 4:44 PM, Siva Durga Prasad Paladugu > <siva...@xilinx.com> wrote: > > Hi Jagan, > > > >> -Original Message- > >> From: Jagan Teki [mailto:jagannadh.t...@gmail.com] > >> Sent: Wednesday, May 09, 2018 4:18 PM > >> To: Siva Durga Prasad Paladugu <siva...@xilinx.com> > >> Cc: Jagan Teki <ja...@amarulasolutions.com>; U-Boot-Denx >> b...@lists.denx.de>; michal.si...@xilinx.com > >> Subject: Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support > >> for ZynqMP qspi driver > >> > >> On Wed, May 9, 2018 at 4:08 PM, Jagan Teki > <jagannadh.t...@gmail.com> > >> wrote: > >> > On Wed, May 9, 2018 at 1:31 PM, Siva Durga Prasad Paladugu > >> > <siva...@xilinx.com> wrote: > >> >> Hi Jagan, > >> >> > >> >>> -Original Message- > >> >>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com] > >> >>> Sent: Wednesday, May 09, 2018 1:22 PM > >> >>> To: Siva Durga Prasad Paladugu <siva...@xilinx.com> > >> >>> Cc: Jagan Teki <ja...@amarulasolutions.com>; U-Boot-Denx >> >>> b...@lists.denx.de>; michal.si...@xilinx.com > >> >>> Subject: Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add > >> >>> support for ZynqMP qspi driver > >> >>> > >> >>> On Wed, May 9, 2018 at 1:20 PM, Siva Durga Prasad Paladugu > >> >>> <siva...@xilinx.com> wrote: > >> >>> > > >> >>> > Hi, > >> >>> > > >> >>> >> -Original Message- > >> >>> >> From: Jagan Teki [mailto:jagannadh.t...@gmail.com] > >> >>> >> Sent: Wednesday, May 09, 2018 1:12 PM > >> >>> >> To: Siva Durga Prasad Paladugu <siva...@xilinx.com> > >> >>> >> Cc: Jagan Teki <ja...@amarulasolutions.com>; U-Boot-Denx >> >>> >> b...@lists.denx.de>; michal.si...@xilinx.com > >> >>> >> Subject: Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add > >> >>> >> support for ZynqMP qspi driver > >> >>> >> > >> >>> >> On Wed, May 9, 2018 at 12:33 PM, Siva Durga Prasad Paladugu > >> >>> >> <siva...@xilinx.com> wrote: > >> >>> >> > Hi Jagan, > >> >>> >> > > >> >>> >> >> -Original Message- > >> >>> >> >> From: Jagan Teki [mailto:ja...@amarulasolutions.com] > >> >>> >> >> Sent: Wednesday, May 09, 2018 12:01 PM > >> >>> >> >> To: Siva Durga Prasad Paladugu <siva...@xilinx.com> > >> >>> >> >> Cc: U-Boot-Denx <u-boot@lists.denx.de>; > >> >>> >> >> michal.si...@xilinx.com > >> >>> >> >> Subject: Re: [PATCH v3 1/2] spi: zynqmp_gqspi: Add support > >> >>> >> >> for > >> >>> >> ZynqMP > >> >>> >> >> qspi driver > >> >>> >> >> > >> >>> >> >> On Tue, May 8, 2018 at 3:43 PM, Siva Durga Prasad Paladugu > >> >>> >> >> <siva.durga.palad...@xilinx.com> wrote: > >> >>> >> >> > This patch adds qspi driver support for ZynqMP SoC. This > >> >>> >> >> > driver is responsible for communicating with qspi flash > devices. > >> >>> >> >> > > >> >>> >> >> > Signed-off-by: Siva Durga Prasad Paladugu > >> >>> >> >> > <siva.durga.palad...@xilinx.com> > >> >>> >> >> > --- > >> >>> >> >> > Changes for v3: > >> >>> >> >> > - Renamed all macros, functions, files and configs as per > >> >>> >> >> > comment > >> >>> >> >> >
Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
Hi Jagan, > -Original Message- > From: Jagan Teki [mailto:jagannadh.t...@gmail.com] > Sent: Wednesday, May 09, 2018 4:18 PM > To: Siva Durga Prasad Paladugu <siva...@xilinx.com> > Cc: Jagan Teki <ja...@amarulasolutions.com>; U-Boot-Denx b...@lists.denx.de>; michal.si...@xilinx.com > Subject: Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for > ZynqMP qspi driver > > On Wed, May 9, 2018 at 4:08 PM, Jagan Teki <jagannadh.t...@gmail.com> > wrote: > > On Wed, May 9, 2018 at 1:31 PM, Siva Durga Prasad Paladugu > > <siva...@xilinx.com> wrote: > >> Hi Jagan, > >> > >>> -Original Message- > >>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com] > >>> Sent: Wednesday, May 09, 2018 1:22 PM > >>> To: Siva Durga Prasad Paladugu <siva...@xilinx.com> > >>> Cc: Jagan Teki <ja...@amarulasolutions.com>; U-Boot-Denx >>> b...@lists.denx.de>; michal.si...@xilinx.com > >>> Subject: Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support > >>> for ZynqMP qspi driver > >>> > >>> On Wed, May 9, 2018 at 1:20 PM, Siva Durga Prasad Paladugu > >>> <siva...@xilinx.com> wrote: > >>> > > >>> > Hi, > >>> > > >>> >> -Original Message- > >>> >> From: Jagan Teki [mailto:jagannadh.t...@gmail.com] > >>> >> Sent: Wednesday, May 09, 2018 1:12 PM > >>> >> To: Siva Durga Prasad Paladugu <siva...@xilinx.com> > >>> >> Cc: Jagan Teki <ja...@amarulasolutions.com>; U-Boot-Denx >>> >> b...@lists.denx.de>; michal.si...@xilinx.com > >>> >> Subject: Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add > >>> >> support for ZynqMP qspi driver > >>> >> > >>> >> On Wed, May 9, 2018 at 12:33 PM, Siva Durga Prasad Paladugu > >>> >> <siva...@xilinx.com> wrote: > >>> >> > Hi Jagan, > >>> >> > > >>> >> >> -Original Message- > >>> >> >> From: Jagan Teki [mailto:ja...@amarulasolutions.com] > >>> >> >> Sent: Wednesday, May 09, 2018 12:01 PM > >>> >> >> To: Siva Durga Prasad Paladugu <siva...@xilinx.com> > >>> >> >> Cc: U-Boot-Denx <u-boot@lists.denx.de>; > >>> >> >> michal.si...@xilinx.com > >>> >> >> Subject: Re: [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for > >>> >> ZynqMP > >>> >> >> qspi driver > >>> >> >> > >>> >> >> On Tue, May 8, 2018 at 3:43 PM, Siva Durga Prasad Paladugu > >>> >> >> <siva.durga.palad...@xilinx.com> wrote: > >>> >> >> > This patch adds qspi driver support for ZynqMP SoC. This > >>> >> >> > driver is responsible for communicating with qspi flash devices. > >>> >> >> > > >>> >> >> > Signed-off-by: Siva Durga Prasad Paladugu > >>> >> >> > <siva.durga.palad...@xilinx.com> > >>> >> >> > --- > >>> >> >> > Changes for v3: > >>> >> >> > - Renamed all macros, functions, files and configs as per > >>> >> >> > comment > >>> >> >> > - Used wait_for_bit wherever required > >>> >> >> > - Removed unnecessary header inclusion > >>> >> >> > > >>> >> >> > Changes for v2: > >>> >> >> > - Rebased on top of latest master > >>> >> >> > - Moved macro definitions to .h file as per comment > >>> >> >> > - Fixed magic values with macros as per comment > >>> >> >> > --- > >>> >> >> > arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h | 154 > >>> ++ > >>> >> >> > drivers/spi/Kconfig | 7 + > >>> >> >> > drivers/spi/Makefile| 1 + > >>> >> >> > drivers/spi/zynqmp_gqspi.c | 670 > >>> >> >> > >>> >> >> > 4 files changed, 832 insertions(+) create mode 100644 > >>> >> >> > arch/arm/include/asm/arch- > >>> >> >> zyn
Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Wednesday, May 09, 2018 1:22 PM
> To: Siva Durga Prasad Paladugu <siva...@xilinx.com>
> Cc: Jagan Teki <ja...@amarulasolutions.com>; U-Boot-Denx b...@lists.denx.de>; michal.si...@xilinx.com
> Subject: Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for
> ZynqMP qspi driver
>
> On Wed, May 9, 2018 at 1:20 PM, Siva Durga Prasad Paladugu
> <siva...@xilinx.com> wrote:
> >
> > Hi,
> >
> >> -Original Message-
> >> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> >> Sent: Wednesday, May 09, 2018 1:12 PM
> >> To: Siva Durga Prasad Paladugu <siva...@xilinx.com>
> >> Cc: Jagan Teki <ja...@amarulasolutions.com>; U-Boot-Denx >> b...@lists.denx.de>; michal.si...@xilinx.com
> >> Subject: Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support
> >> for ZynqMP qspi driver
> >>
> >> On Wed, May 9, 2018 at 12:33 PM, Siva Durga Prasad Paladugu
> >> <siva...@xilinx.com> wrote:
> >> > Hi Jagan,
> >> >
> >> >> -Original Message-
> >> >> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
> >> >> Sent: Wednesday, May 09, 2018 12:01 PM
> >> >> To: Siva Durga Prasad Paladugu <siva...@xilinx.com>
> >> >> Cc: U-Boot-Denx <u-boot@lists.denx.de>; michal.si...@xilinx.com
> >> >> Subject: Re: [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for
> >> ZynqMP
> >> >> qspi driver
> >> >>
> >> >> On Tue, May 8, 2018 at 3:43 PM, Siva Durga Prasad Paladugu
> >> >> <siva.durga.palad...@xilinx.com> wrote:
> >> >> > This patch adds qspi driver support for ZynqMP SoC. This driver
> >> >> > is responsible for communicating with qspi flash devices.
> >> >> >
> >> >> > Signed-off-by: Siva Durga Prasad Paladugu
> >> >> > <siva.durga.palad...@xilinx.com>
> >> >> > ---
> >> >> > Changes for v3:
> >> >> > - Renamed all macros, functions, files and configs as per
> >> >> > comment
> >> >> > - Used wait_for_bit wherever required
> >> >> > - Removed unnecessary header inclusion
> >> >> >
> >> >> > Changes for v2:
> >> >> > - Rebased on top of latest master
> >> >> > - Moved macro definitions to .h file as per comment
> >> >> > - Fixed magic values with macros as per comment
> >> >> > ---
> >> >> > arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h | 154
> ++
> >> >> > drivers/spi/Kconfig | 7 +
> >> >> > drivers/spi/Makefile| 1 +
> >> >> > drivers/spi/zynqmp_gqspi.c | 670
> >> >>
> >> >> > 4 files changed, 832 insertions(+) create mode 100644
> >> >> > arch/arm/include/asm/arch-
> >> >> zynqmp/zynqmp_gqspi.h
> >> >> > create mode 100644 drivers/spi/zynqmp_gqspi.c
> >> >> >
> >> >> > diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h
> >> >> > b/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h
> >> >>
> >> >> already asked you to move this header code in driver .c file
> >> >
> >> > You might have missed my reply to your earlier comment on this.
> >> > These were moved to .h based on comment from Lukasz in v1.
> >> > I don’t have any issue in having them anywhere. Let me know your
> choice.
> >>
> >> I'm trying to align Linux code, better to move like that and make
> >> sure to use similar macros.
> >>
> >> >
> >
> > [snip]
> >
> >> >> > +static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv
> >> *priv) {
> >> >> > + u8 command = 1;
> >> >> > + u32 gen_fifo_cmd;
> >> >> > + u32 bytecount = 0;
> >> >> > +
> >> >> > + while (priv->len) {
> >> >> > + gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
> >> >> > + gen_fifo_cmd |= GQSPI_GFIFO_TX;
> >> >> > +
> >> >> > + if (comma
Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
Hi,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Wednesday, May 09, 2018 1:12 PM
> To: Siva Durga Prasad Paladugu <siva...@xilinx.com>
> Cc: Jagan Teki <ja...@amarulasolutions.com>; U-Boot-Denx b...@lists.denx.de>; michal.si...@xilinx.com
> Subject: Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for
> ZynqMP qspi driver
>
> On Wed, May 9, 2018 at 12:33 PM, Siva Durga Prasad Paladugu
> <siva...@xilinx.com> wrote:
> > Hi Jagan,
> >
> >> -Original Message-
> >> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
> >> Sent: Wednesday, May 09, 2018 12:01 PM
> >> To: Siva Durga Prasad Paladugu <siva...@xilinx.com>
> >> Cc: U-Boot-Denx <u-boot@lists.denx.de>; michal.si...@xilinx.com
> >> Subject: Re: [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for
> ZynqMP
> >> qspi driver
> >>
> >> On Tue, May 8, 2018 at 3:43 PM, Siva Durga Prasad Paladugu
> >> <siva.durga.palad...@xilinx.com> wrote:
> >> > This patch adds qspi driver support for ZynqMP SoC. This driver is
> >> > responsible for communicating with qspi flash devices.
> >> >
> >> > Signed-off-by: Siva Durga Prasad Paladugu
> >> > <siva.durga.palad...@xilinx.com>
> >> > ---
> >> > Changes for v3:
> >> > - Renamed all macros, functions, files and configs as per comment
> >> > - Used wait_for_bit wherever required
> >> > - Removed unnecessary header inclusion
> >> >
> >> > Changes for v2:
> >> > - Rebased on top of latest master
> >> > - Moved macro definitions to .h file as per comment
> >> > - Fixed magic values with macros as per comment
> >> > ---
> >> > arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h | 154 ++
> >> > drivers/spi/Kconfig | 7 +
> >> > drivers/spi/Makefile| 1 +
> >> > drivers/spi/zynqmp_gqspi.c | 670
> >>
> >> > 4 files changed, 832 insertions(+) create mode 100644
> >> > arch/arm/include/asm/arch-
> >> zynqmp/zynqmp_gqspi.h
> >> > create mode 100644 drivers/spi/zynqmp_gqspi.c
> >> >
> >> > diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h
> >> > b/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h
> >>
> >> already asked you to move this header code in driver .c file
> >
> > You might have missed my reply to your earlier comment on this. These
> > were moved to .h based on comment from Lukasz in v1.
> > I don’t have any issue in having them anywhere. Let me know your choice.
>
> I'm trying to align Linux code, better to move like that and make sure to use
> similar macros.
>
> >
[snip]
> >> > +static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv
> *priv) {
> >> > + u8 command = 1;
> >> > + u32 gen_fifo_cmd;
> >> > + u32 bytecount = 0;
> >> > +
> >> > + while (priv->len) {
> >> > + gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
> >> > + gen_fifo_cmd |= GQSPI_GFIFO_TX;
> >> > +
> >> > + if (command) {
> >> > + command = 0;
> >> > + last_cmd = *(u8 *)priv->tx_buf;
> >> > + }
> >>
> >> don't understand this code can you explain? command assigned 1 it
> >> will not updated anywhere?
> >
> > I want to store last command sent. As the first byte in loop only
> > contains command, it ensures it fills only for one time and next time it
> may contain data to be sent along with command.
> > Command initialized to 1 while declaring it above(u8 command = 1).
>
> Ok the first TX buf has command and reused in tx and rx fifo, how come to
> use use same in rx fifo? why is is last_cmd it is first_cmd?
This holds the command that was sent last to the device before we use in tx/rx
fill, hence used this name.
Thanks,
Siva
>
>
> >
> >>
> >> > +
> >> > + gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
> >> > + gen_fifo_cmd |= *(u8 *)priv->tx_buf;
> >> > + bytecount++;
> >> > + priv->len--;
> >> > + priv->tx_buf = (u8 *)priv->tx_buf + 1;
> >> >
Re: [U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
> Sent: Wednesday, May 09, 2018 12:01 PM
> To: Siva Durga Prasad Paladugu <siva...@xilinx.com>
> Cc: U-Boot-Denx <u-boot@lists.denx.de>; michal.si...@xilinx.com
> Subject: Re: [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for ZynqMP
> qspi driver
>
> On Tue, May 8, 2018 at 3:43 PM, Siva Durga Prasad Paladugu
> <siva.durga.palad...@xilinx.com> wrote:
> > This patch adds qspi driver support for ZynqMP SoC. This driver is
> > responsible for communicating with qspi flash devices.
> >
> > Signed-off-by: Siva Durga Prasad Paladugu
> > <siva.durga.palad...@xilinx.com>
> > ---
> > Changes for v3:
> > - Renamed all macros, functions, files and configs as per comment
> > - Used wait_for_bit wherever required
> > - Removed unnecessary header inclusion
> >
> > Changes for v2:
> > - Rebased on top of latest master
> > - Moved macro definitions to .h file as per comment
> > - Fixed magic values with macros as per comment
> > ---
> > arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h | 154 ++
> > drivers/spi/Kconfig | 7 +
> > drivers/spi/Makefile| 1 +
> > drivers/spi/zynqmp_gqspi.c | 670
>
> > 4 files changed, 832 insertions(+)
> > create mode 100644 arch/arm/include/asm/arch-
> zynqmp/zynqmp_gqspi.h
> > create mode 100644 drivers/spi/zynqmp_gqspi.c
> >
> > diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h
> > b/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h
>
> already asked you to move this header code in driver .c file
You might have missed my reply to your earlier comment on this. These were
moved to .h based on comment
from Lukasz in v1.
I don’t have any issue in having them anywhere. Let me know your choice.
>
> > new file mode 100644
> > index 000..4b26d80
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h
> > @@ -0,0 +1,154 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
>
> [snip]
>
> > + *
> > + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode
> > + only) */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
>
> headers are inorder.
Ok.
>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +struct zynqmp_qspi_platdata {
> > + struct zynqmp_qspi_regs *regs;
> > + struct zynqmp_qspi_dma_regs *dma_regs;
> > + u32 frequency;
> > + u32 speed_hz;
> > + unsigned int tx_rx_mode;
> > +};
> > +
> > +struct zynqmp_qspi_priv {
> > + struct zynqmp_qspi_regs *regs;
> > + struct zynqmp_qspi_dma_regs *dma_regs;
> > + u8 mode;
> > + const void *tx_buf;
> > + void *rx_buf;
> > + unsigned int len;
> > + int bytes_to_transfer;
> > + int bytes_to_receive;
> > + unsigned int is_inst;
> > + unsigned int cs_change:1;
> > +};
> > +
> > +static u8 last_cmd;
> > +
> > +static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus) {
> > + struct zynqmp_qspi_platdata *plat = bus->platdata;
> > + u32 mode = 0;
> > + u32 value;
> > + int ret;
> > + struct clk clk;
> > + unsigned long clock;
> > +
> > + debug("%s\n", __func__);
> > +
> > + plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) +
> > +GQSPI_REG_OFFSET);
> > + plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
> > + (devfdt_get_addr(bus) +
> > + GQSPI_DMA_REG_OFFSET);
> > +
> > + ret = clk_get_by_index(bus, 0, );
> > + if (ret < 0) {
> > + dev_err(dev, "failed to get clock\n");
> > + return ret;
> > + }
> > +
> > + clock = clk_get_rate();
> > + if (IS_ERR_VALUE(clock)) {
> > + dev_err(dev, "failed to get rate\n");
> > + return clock;
> > + }
> > + debug("%s: CLK %ld\n", __func__, clock);
> > +
> > + ret = clk_enable();
> > + if (ret && ret != -ENOS
[U-Boot] [PATCH v3 1/2] spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
This patch adds qspi driver support for ZynqMP SoC. This driver is responsible for communicating with qspi flash devices. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.palad...@xilinx.com> --- Changes for v3: - Renamed all macros, functions, files and configs as per comment - Used wait_for_bit wherever required - Removed unnecessary header inclusion Changes for v2: - Rebased on top of latest master - Moved macro definitions to .h file as per comment - Fixed magic values with macros as per comment --- arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h | 154 ++ drivers/spi/Kconfig | 7 + drivers/spi/Makefile| 1 + drivers/spi/zynqmp_gqspi.c | 670 4 files changed, 832 insertions(+) create mode 100644 arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h create mode 100644 drivers/spi/zynqmp_gqspi.c diff --git a/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h b/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h new file mode 100644 index 000..4b26d80 --- /dev/null +++ b/arch/arm/include/asm/arch-zynqmp/zynqmp_gqspi.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Xilinx + * + * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller + * driver (master mode only) + */ + +#ifndef _ASM_ARCH_ZYNQMP_GQSPI_H_ +#define _ASM_ARCH_ZYNQMP_GQSPI_H_ + +#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) +#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) +#define GQSPI_CONFIG_DMA_MODE (2 << 30) +#define GQSPI_CONFIG_CPHA_MASK BIT(2) +#define GQSPI_CONFIG_CPOL_MASK BIT(1) + +/* QSPI MIO's count for different connection topologies */ +#define GQSPI_MIO_NUM_QSPI06 +#define GQSPI_MIO_NUM_QSPI15 +#define GQSPI_MIO_NUM_QSPI1_CS 1 + +/* + * QSPI Interrupt Registers bit Masks + * + * All the four interrupt registers (Status/Mask/Enable/Disable) have the same + * bit definitions. + */ +#define GQSPI_IXR_TXNFULL_MASK 0x0004 /* QSPI TX FIFO Overflow */ +#define GQSPI_IXR_TXFULL_MASK 0x0008 /* QSPI TX FIFO is full */ +#define GQSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX FIFO Not Empty */ +#define GQSPI_IXR_GFEMTY_MASK 0x0080 /* QSPI Generic FIFO Empty */ +#define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \ + GQSPI_IXR_RXNEMTY_MASK) + +/* + * QSPI Enable Register bit Masks + * + * This register is used to enable or disable the QSPI controller + */ +#define GQSPI_ENABLE_ENABLE_MASK 0x0001 /* QSPI Enable Bit Mask */ + +#define GQSPI_GFIFO_LOW_BUSBIT(14) +#define GQSPI_GFIFO_CS_LOWER BIT(12) +#define GQSPI_GFIFO_UP_BUS BIT(15) +#define GQSPI_GFIFO_CS_UPPER BIT(13) +#define GQSPI_SPI_MODE_QSPI(3 << 10) +#define GQSPI_SPI_MODE_SPI BIT(10) +#define GQSPI_SPI_MODE_DUAL_SPI(2 << 10) +#define GQSPI_IMD_DATA_CS_ASSERT 5 +#define GQSPI_IMD_DATA_CS_DEASSERT 5 +#define GQSPI_GFIFO_TX BIT(16) +#define GQSPI_GFIFO_RX BIT(17) +#define GQSPI_GFIFO_STRIPE_MASKBIT(18) +#define GQSPI_GFIFO_IMD_MASK 0xFF +#define GQSPI_GFIFO_EXP_MASK BIT(9) +#define GQSPI_GFIFO_DATA_XFR_MASK BIT(8) +#define GQSPI_STRT_GEN_FIFOBIT(28) +#define GQSPI_GEN_FIFO_STRT_MODBIT(29) +#define GQSPI_GFIFO_WP_HOLDBIT(19) +#define GQSPI_BAUD_DIV_MASK(7 << 3) +#define GQSPI_DFLT_BAUD_RATE_DIV BIT(3) +#define GQSPI_GFIFO_ALL_INT_MASK 0xFBE +#define GQSPI_DMA_DST_I_STS_DONE BIT(1) +#define GQSPI_DMA_DST_I_STS_MASK 0xFE +#define MODEBITS 0x6 + +#define QUAD_OUT_READ_CMD 0x6B +#define QUAD_PAGE_PROGRAM_CMD 0x32 +#define DUAL_OUTPUT_FASTRD_CMD 0x3B + +#define GQSPI_GFIFO_SELECT BIT(0) + +#define GQSPI_FIFO_THRESHOLD 1 + +#define SPI_XFER_ON_BOTH 0 +#define SPI_XFER_ON_LOWER 1 +#define SPI_XFER_ON_UPPER 2 + +#define GQSPI_DMA_ALIGN0x4 +#define GQSPI_MAX_BAUD_RATE_VAL7 +#define GQSPI_DFLT_BAUD_RATE_VAL 2 + +#define GQSPI_TIMEOUT 1 + +#define GQSPI_BAUD_DIV_SHIFT 2 +#define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 +#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2 +#define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3 +#define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3 +#define GQSPI_USE_DATA_DLY 0x1 +#define GQSPI_USE_DATA_DLY_SHIFT 31 +#define GQSPI_DATA_DLY_ADJ_VALUE 0x2 +#define GQSPI_DATA_DLY_ADJ_SHIFT 28 +#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1 +#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 +#define GQSPI_DATA_DLY_ADJ_OFST0x01F8 +#define IOU_TAPDLY_BYPASS_OFST 0xFF180390 +#define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x0020 +#define GQSPI_FREQ_40MHZ 4000 +#define GQSPI_FREQ_100MHZ 1 +#define GQSPI_FREQ_150MHZ 15000 +#define IOU_TAPDLY_BYPASS_MASK 0x7 + +#define
[U-Boot] [PATCH v3 2/2] zynqmp: zcu102: Add qspi driver support for ZynqMP zcu102 boards
This patch adds qspi driver support for all ZynqMP ZCU102 boards. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.palad...@xilinx.com> --- Changes for v3: - Changed as per latest changes in 1/2 Changes for v2: - Rebased on top of latest master and enabled qspi for all zcu102 boards. --- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 5 + configs/xilinx_zynqmp_zcu102_revA_defconfig | 5 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 5 + 3 files changed, 15 insertions(+) diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 68da9dc..51f4669 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -64,6 +65,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -87,6 +89,9 @@ CONFIG_DEBUG_UART_BASE=0xff00 CONFIG_DEBUG_UART_CLOCK=1 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 2adba61..2ae1a0b 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -64,6 +65,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -87,6 +89,9 @@ CONFIG_DEBUG_UART_BASE=0xff00 CONFIG_DEBUG_UART_CLOCK=1 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 2310fa8..6f79a68 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -64,6 +65,7 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -87,6 +89,9 @@ CONFIG_DEBUG_UART_BASE=0xff00 CONFIG_DEBUG_UART_CLOCK=1 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -- 2.7.4 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
