Hi Fabio,
On 20.08.2014 23:24, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Adjust it accordingly.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- Avoid too many
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 2928ac1..2610e0a 100644
---
The IMX6 MMDC calibration registers depend on propagation delay and capacitive
loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the
board layout varies little in trace-lengths such that propagation delays are
irrelevant thus we can simply things by using calibration values
The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as:
* 2x MiniPCIe sockets
* 2x USB host sockets
* 2x i210 GigE
* HDMI out
* digital I/O expansion
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/eeprom.c | 3 ++
Benoît,
On Wed, Aug 20, 2014 at 12:47 PM, Benoît Thébaudeau
benoit.thebaudeau@gmail.com wrote:
On Wed, Aug 20, 2014 at 9:21 AM, Christian Riesch
christian.rie...@omicron.at wrote:
On Tue, Aug 19, 2014 at 8:35 PM, Benoît Thébaudeau
benoit.thebaudeau@gmail.com wrote:
Commit 41623c9
On Thu, Aug 7, 2014 at 10:49 PM, Tim Harvey thar...@gateworks.com wrote:
Many of the Gateworks Ventana boards have a PLX PCIe switch where GPIO
on the switch is used as the PERST# of the downstream ports. In the Linux
kernel there is a PCI fixup that asserts these properly when the upstream
On Fri, Aug 8, 2014 at 7:41 AM, Tim Harvey thar...@gateworks.com wrote:
Two patches to add Intel i210 support to the e1000 driver.
Marek Vasut (2):
e1000: Implement dcache support
e1000: add i210 support
drivers/net/e1000.c | 266
++--
On Thursday, August 21, 2014 at 08:40:14 AM, Tim Harvey wrote:
On Fri, Aug 8, 2014 at 7:41 AM, Tim Harvey thar...@gateworks.com wrote:
Two patches to add Intel i210 support to the e1000 driver.
Marek Vasut (2):
e1000: Implement dcache support
e1000: add i210 support
Hi Stefano Babic,
On 8/20/2014 5:44 PM, Stefano Babic wrote:
Hi Ye,
On 20/08/2014 10:55, Ye.Li wrote:
From: Ye.Li ye...@freescale.com
The load region size of EIM-NOR are defined to 0. For this case,
the parameter imximage_init_loadsize must be calculated.
The imximage tool implements the
From: Angelo Dureghello ang...@sysam.it
Signed-off-by: Angelo Dureghello ang...@sysam.it
Cc: Tom Rini tr...@ti.com
---
This patch adds support for Sysam AMCORE mcf5307-based board
Changes for v2:
- fix patch email sending issues
Changes for v3:
- fix code format issues
Changes for v4:
From: Angelo Dureghello ang...@sysam.it
Add support for Freescale Coldfire mcf5307 cpu.
Signed-off-by: Angelo Dureghello ang...@sysam.it
Cc: Jason Jin jason@freescale.com
---
Changes for v2:
- add MAINTAINERS entry
- add boards.cfg entry
Changes for v3:
- fix code format issues
Hi,
On 21/08/2014 07:02, Marek Vasut wrote:
On Thursday, August 21, 2014 at 06:11:16 AM, Ye Li wrote:
The TDAR bit is set when the descriptors are all out from TX ring, but the
descriptor properly is in transmitting not READY.
I don't quite understand this, can you please rephrase ?
Hi Felipe,
On Wed, Aug 20, 2014 at 09:34:13AM +0200, Lukasz Majewski wrote:
Hi Felipe,
On Tue, Aug 19, 2014 at 09:08:00PM +0530, Kishon Vijay Abraham I
wrote:
On Monday 18 August 2014 08:26 PM, Lukasz Majewski wrote:
Hi Kishon,
Explicity set the max
Hi Fabio,
On 20/08/2014 23:24, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Adjust it accordingly.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- Avoid too
On 8/21/2014 3:57 PM, Stefano Babic wrote:
Hi,
On 21/08/2014 07:02, Marek Vasut wrote:
On Thursday, August 21, 2014 at 06:11:16 AM, Ye Li wrote:
The TDAR bit is set when the descriptors are all out from TX ring, but the
descriptor properly is in transmitting not READY.
I don't quite
Hello,
On 20 August 2014 21:19, TooMeeK Admin m...@toomeek.waw.pl wrote:
Hello,
I'm getting some troubles booting FreeBSD on Banana Pi.
I wrote simple script that creates bootable SD card image for FreeBSD OS.
#!/bin/bash
cd /root/banana
rm /root/banana/banana.img
truncate -s 940M
This patch implements the generic board init as described in
doc/README.generic-board.
Signed-off-by: Thomas Chou tho...@wytron.com.tw
Signed-off-by: Scott McNutt smcn...@psyent.com
---
arch/nios2/config.mk|2 +
arch/nios2/cpu/cpu.c| 12 +++-
arch/nios2/cpu/start.S
This patch implements the generic board init as described in
doc/README.generic-board.
Signed-off-by: Thomas Chou tho...@wytron.com.tw
Signed-off-by: Scott McNutt smcn...@psyent.com
---
arch/nios2/config.mk|2 +
arch/nios2/cpu/cpu.c| 12 +++-
arch/nios2/cpu/start.S
Hello
I am trying to disable the memory management unit on my sabreLite board, but i
don't find what i should do. I also want to change the mapping of the MMU, but
i don't know where it is.
Do you know which file i have to edit?
Sorry for my english, it's not my mother tongue.
Regards
On 21.08.2014 10:53, Thomas Chou wrote:
This patch implements the generic board init as described in
doc/README.generic-board.
Good idea. Please find below a few comments, mostly coding style related.
snip
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index e0dcbc2..4714171
Hi Alexandre,
On 21/08/2014 11:08, Alexandre Delove wrote:
Hello
I am trying to disable the memory management unit on my sabreLite board, but
i don't find what i should do. I also want to change the mapping of the MMU,
but i don't know where it is.
MMU is off in U-Boot. It is turned on
Hi Andreas,
The toolchain from kernel.org indeed works fine.
Thank you very much for your help!
Best regards,
Vasili
On Wed, Aug 20, 2014 at 11:38 PM, Andreas Bießmann
andreas.de...@googlemail.com wrote:
Hi Vasili,
On 20.08.14 18:10, Vasili Galka wrote:
Hi Andreas,
I'm trying to verify
Hi Nobuhiro,
I'm trying to verify the correct build of all SH boards in U-Boot. What is
the recommended toolchain to use?
I tried the one from kernel.org [1], but it does not work for all the boards,
I get build errors like this one:
Building rsk7203 board...
sh4-linux-gcc: error: command line
Hi Albert,
First, I don't like full-quoting as Wolfgang also mentioned before:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/52214/focus=52252
Since this patch is very long, I might miss some of your comments.
If I did not overlook, my comments are below:
On Wed, 20 Aug 2014
On Thursday, August 21, 2014 at 09:57:23 AM, Stefano Babic wrote:
Hi,
On 21/08/2014 07:02, Marek Vasut wrote:
On Thursday, August 21, 2014 at 06:11:16 AM, Ye Li wrote:
The TDAR bit is set when the descriptors are all out from TX ring, but
the descriptor properly is in transmitting not
Hi,
I would like to replace 'fatload' and 'ext2load' commands by 'load' command in
default env settings such as loadbootscript, loaduimage, etc. for all boards.
That way, the load commands are independent from the filesystem used.
Is there any objection?
If everyone is ok, I could submit a
On Thu, Aug 21, 2014 at 5:01 AM, Stefano Babic sba...@denx.de wrote:
I go just a bit further according to Otavio's comment. In this way, we
do not remove #ifdef, we have only moved. What about using is_cpu_type()
instead of this ? If you do not want to add the macro for not mx6 socs
On Thu, Aug 21, 2014 at 3:03 AM, Stefan Roese s...@denx.de wrote:
Why don't you just use the bigger value (64) for all SoC versions? Shouldn't
hurt, right. And would keep the source clean.
I think this should work fine. Thanks for the suggestion, Stefan.
This patch implements the generic board init as described in
doc/README.generic-board.
Signed-off-by: Thomas Chou tho...@wytron.com.tw
Signed-off-by: Scott McNutt smcn...@psyent.com
Reviewed-by: Stefan Roese s...@denx.de
---
Changes in v2:
- Coding style clean up
arch/nios2/config.mk
LIODN entry for B4860/B4420 mentions USB controller as mph
insread of dr. This results in PAMU not permitting bus
transactions for USB DR controller on B4860 resulting in
USB function failure. Replacing fsl-usb2-mph with
fsl-usb2-dr allows USB DR controller bus transactions
Signed-off-by: Poonam
Hi,
I have prepared a patch to add EXT filesystem support to SPL, but I have some
questions to make a good patch.
Currently, we have : MMCSD_MODE_FAT for FAT boot. Should we add MMCSD_MODE_EXT
or just rename it to MMCSD_MODE_FS (or something else) to be filesystem generic?
Then, some vars
Currently mx6dlsabresd shares the same DCD settings with the nitrogen board.
Provide a DCD configuration file specific to mx6dlsabresd with the settings
recommended by the Freescale hardware team.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Commit 41623c9 'arm: move exception handling out of start.S files' missed some
linker scripts. Hence, some boards no longer had exception handling linked since
this commit. Restore the original behavior by adding the .vectors section to
these linker scripts.
Signed-off-by: Benoît Thébaudeau
Hi York,
I have mostly minor comments this time; this is looking pretty good.
On Tue, Aug 19, 2014 at 09:28:00PM +0100, York Sun wrote:
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table
On Thu, Aug 21, 2014 at 10:00:46AM +0200, Lukasz Majewski wrote:
Hi Felipe,
On Wed, Aug 20, 2014 at 09:34:13AM +0200, Lukasz Majewski wrote:
Hi Felipe,
On Tue, Aug 19, 2014 at 09:08:00PM +0530, Kishon Vijay Abraham I
wrote:
On Monday 18 August 2014 08:26 PM,
On Wed, Aug 20, 2014 at 01:12:20PM -0600, Stephen Warren wrote:
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
This series attempts to fix a long-standing problem in the rtl8169 driver
(though the same problem may exist in other drivers as well). Let me
On Wed, Aug 20, 2014 at 01:23:13PM -0600, Stephen Warren wrote:
On 08/18/2014 02:00 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Implement an API that can be used by drivers to allocate memory from a
poll that is mapped uncached. This is useful if drivers would otherwise
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by:
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is set in the last BD, which causes
FEC transmission to fail.
As explained by Ye Li:
The TDAR bit is set when the descriptors are all out from TX ring, but the
descriptor properly
On Thursday, August 21, 2014 at 06:12:08 PM, Fabio Estevam wrote:
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
which addresses the needs
On Thursday, August 21, 2014 at 06:12:09 PM, Fabio Estevam wrote:
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is set in the last BD, which causes
FEC transmission to fail.
As explained by Ye Li:
The TDAR bit is set
On Thu, Aug 21, 2014 at 1:21 PM, Marek Vasut ma...@denx.de wrote:
Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't there
something completely else broken on MX6SX ?
Thanks for the review, Marek.
Inspecting this further I think the correct fix would be:
Hey,
So as I migrate scripts over to buildman, one issue I have is that
today warning and errors are treated the same:
u-boot (master)$ ./tools/buildman/buildman -b master -c 1 -ve -T 1 -j 9
'arc|blackfin|microblaze|m68k|nds32|sparc|x86|aarch64|sandbox|mips' -s
Summary of 1 commit for 128 boards
On Thursday, August 21, 2014 at 06:41:26 PM, Fabio Estevam wrote:
On Thu, Aug 21, 2014 at 1:21 PM, Marek Vasut ma...@denx.de wrote:
Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't
there something completely else broken on MX6SX ?
Thanks for the review, Marek.
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is set in the last BD, which causes
FEC transmission to fail.
As explained by Ye Li:
The TDAR bit is set when the descriptors are all out from TX ring, but the
descriptor properly
mx6 is an armv7 which has 64-byte cacheline size.
Without this fix we are not able to get the FEC driver to work on mx6solox.
64-byte cacheline is also used by the kernel on ARMv7, so fix it accordingly.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Hey Tom,
The following changes since commit e49f14af1349eef94e41b636320bbfcace7403b5:
patman: Only use git's --no-decorate when available (2014-08-13 08:34:16
-0600)
are available in the git repository at:
git://git.denx.de/u-boot-staging.git ag...@denx.de
for you to fetch changes up to
On Thursday, August 21, 2014 at 07:10:32 PM, Fabio Estevam wrote:
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is set in the last BD, which causes
FEC transmission to fail.
As explained by Ye Li:
The TDAR bit is set
On Thursday, August 21, 2014 at 07:10:02 PM, Fabio Estevam wrote:
mx6 is an armv7 which has 64-byte cacheline size.
Without this fix we are not able to get the FEC driver to work on mx6solox.
64-byte cacheline is also used by the kernel on ARMv7, so fix it
accordingly.
It's not a kernel
On Thu, Aug 21, 2014 at 2:14 PM, Marek Vasut ma...@denx.de wrote:
On Thursday, August 21, 2014 at 07:10:02 PM, Fabio Estevam wrote:
mx6 is an armv7 which has 64-byte cacheline size.
Without this fix we are not able to get the FEC driver to work on mx6solox.
64-byte cacheline is also used by
On Tue, Aug 19, 2014 at 09:44:20PM +0530, Kishon Vijay Abraham I wrote:
On Tuesday 19 August 2014 01:58 PM, Lukasz Majewski wrote:
Hi Kishon,
Implemented __weak functions for board_usb_cleanup,
board_usb_gadget_handle_interrupts and usb_gadget_handle_interrupts
to get of compiler
On 08/21/2014 06:47 AM, Mark Rutland wrote:
Hi York,
I have mostly minor comments this time; this is looking pretty good.
On Tue, Aug 19, 2014 at 09:28:00PM +0100, York Sun wrote:
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot
On Thu, Aug 21, 2014 at 12:53:42PM -0400, Tom Rini wrote:
Hey,
So as I migrate scripts over to buildman, one issue I have is that
today warning and errors are treated the same:
u-boot (master)$ ./tools/buildman/buildman -b master -c 1 -ve -T 1 -j 9
Hi Mark,
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
On Behalf Of York Sun
Sent: Friday, August 22, 2014 12:03 AM
To: Mark Rutland; Basu Arnab-B45036
Cc: tr...@ti.com; u-boot@lists.denx.de; Wood Scott-B07421
Subject: Re: [U-Boot]
On Thu, Aug 21, 2014 at 2:14 PM, Marek Vasut ma...@denx.de wrote:
On Thursday, August 21, 2014 at 07:10:02 PM, Fabio Estevam wrote:
mx6 is an armv7 which has 64-byte cacheline size.
Without this fix we are not able to get the FEC driver to work on mx6solox.
64-byte cacheline is also used by
On Thu, Aug 21, 2014 at 8:36 AM, Christian Riesch
christian.rie...@omicron.at wrote:
Benoît,
On Wed, Aug 20, 2014 at 12:47 PM, Benoît Thébaudeau
benoit.thebaudeau@gmail.com wrote:
On Wed, Aug 20, 2014 at 9:21 AM, Christian Riesch
christian.rie...@omicron.at wrote:
On Tue, Aug 19, 2014
On Wed, 2014-08-20 at 14:37 +0900, FUKAUMI Naoki wrote:
This patch adds support for Olimex A20-OLinuXino-LIME board.
Signed-off-by: FUKAUMI Naoki nao...@gmail.com
I think this looks like a pretty straight import from the linux-sunxi
u-boot fork, massaged for changes from upstream, is that
Hi Fabio,
On Thu, Aug 21, 2014 at 9:11 PM, Fabio Estevam feste...@gmail.com wrote:
On Thu, Aug 21, 2014 at 2:14 PM, Marek Vasut ma...@denx.de wrote:
On Thursday, August 21, 2014 at 07:10:02 PM, Fabio Estevam wrote:
mx6 is an armv7 which has 64-byte cacheline size.
Without this fix we are not
Hi Benoît,
On Thu, Aug 21, 2014 at 5:13 PM, Benoît Thébaudeau
benoit.thebaudeau@gmail.com wrote:
Yes, it's always 32 bytes for Cortex-A9. But does mx6solox really have
a standard Cortex-A9 core like all the currently released i.MX6 SoCs
(which seems to be the case according to
On Thu, 2014-08-21 at 10:48 +0200, Michal Suchanek wrote:
Hello,
On 20 August 2014 21:19, TooMeeK Admin m...@toomeek.waw.pl wrote:
Hello,
I'm getting some troubles booting FreeBSD on Banana Pi.
I wrote simple script that creates bootable SD card image for FreeBSD OS.
#!/bin/bash
On 14 Aug 2014, ste...@agner.ch wrote:
This adds initial support for Freescale NFC (NAND Flash
Controller) found in ARM Vybrid SoC's, Power Architecture MPC5125
and others. However, this driver is only tested on Vybrid.
On Wed, 2014-08-13 at 22:32, Scott Wood wrote:
raw_writel() is
The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.
Signed-off-by: York Sun york...@freescale.com
---
drivers/ddr/fsl/ctrl_regs.c | 28
Hi Marek,
On 8/22/2014 1:18 AM, Marek Vasut wrote:
On Thursday, August 21, 2014 at 07:10:32 PM, Fabio Estevam wrote:
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is set in the last BD, which causes
FEC transmission to
Signed-off-by: Thomas Chou tho...@wytron.com.tw
---
arch/nios2/Kconfig |8 --
board/psyent/common/AMDLV065D.c | 170
board/psyent/pci5441/Kconfig | 15 ---
board/psyent/pci5441/MAINTAINERS |6 -
board/psyent/pci5441/Makefile|8 --
Hi Detlev,
I'd like to have a presentation at U-Boot mini summit 2014.
8---
Kbuild and Kconfig for U-Boot
Abstract:
U-Boot has had big changes on its build system in the past year.
Kbuild and Kconfig provide us a lot of benefites;
Wolfgang Denk wd at denx.de writes:
Dear PHIL.EDWORTHY at renesas.com,
In message OF460D0558.A844A780-ONC12578AE.0047905C-802578AE.00482EFA at
eu.necel.com you wrote:
U-boot is typically stored in flash and one of the first things it
does when executed is relocate to ram.
I guess some developers are already getting sick of this tool
because it generally takes a few minites to generate the boards.cfg
on a reasonable computer.
This commit makes it about 4 times faster.
You might still not be satisfied, but better than doing nothing.
Signed-off-by: Masahiro Yamada
This patch fixes a minor problem:
If a block without F: configs/*_defconfig is followed by another
block with F: configs/*_defconfig, the maintainers from the
former block are squashed into the latter.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
tools/genboardscfg.py | 2 +-
Fix following issues in USB device-tree fixup:
- returns when either dr_mode or phy_type not defined.
This was terminating fix-up when only either property
was defined in hwconfig string
- updates dr_mode_type or dr_phy_type with junk value when
their
This series depends on the feature introduced by this commit:
http://patchwork.ozlabs.org/patch/381622/
Masahiro Yamada (2):
MAKEALL: run genboardscfg.py all the time
buildman: run genboardscfg.py all the time
MAKEALL | 11 ---
tools/buildman/control.py | 10
This commit makes sure boards.cfg is up to date before starting
the build tests. tools/genboardscfg.py exits immediately printing
boards.cfg is up to date. Nothing to do. when boards.cfg is
already new.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
tools/buildman/control.py | 10
This commit makes sure boards.cfg is up to date before starting
the build tests. tools/genboardscfg.py exits immediately printing
boards.cfg is up to date. Nothing to do. when boards.cfg is
already new.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
MAKEALL | 11 ---
1
72 matches
Mail list logo
