On 2 July 2015 07:50:59 CEST, Marek Vasut ma...@denx.de wrote:
On Thursday, July 02, 2015 at 01:04:47 AM, Marcel Ziswiler wrote:
Hi!
[...]
@@ -64,8 +67,14 @@
AX_MEDIUM_AC | AX_MEDIUM_RE)
/* AX88772 AX88178 RX_CTL values */
+#define AX_RX_CTL_RH2M 0x0200 /*
Dear Daniel,
In message 55947a25.5020...@gmail.com you wrote:
CONFIG_USE_PRIVATE_LIBGCC should be removed. If an architecture supports
a private libgcc, then it should always use it. I think for U-Boot it is
better and safer to have all code under control instead of pulling in
external code
On 15-07-02 09:26:04, Stefano Babic wrote:
Hi Sanchayan,
I merge it.
Thanks Stefano.
- Sanchayan.
On 02/07/2015 07:56, maitysancha...@gmail.com wrote:
Hello,
Another ping?
- Sanchayan.
On 15-06-08 12:40:41, Sanchayan Maity wrote:
Increase console IO buffer size to 1024
On 2 July 2015 at 06:50, Masahiro Yamada yamada.masah...@socionext.com wrote:
2015-07-02 2:08 GMT+09:00 Jagan Teki jt...@openedev.com:
On 29 June 2015 at 14:33, Jagan Teki jt...@openedev.com wrote:
This commit moves:
- CONFIG_OF_CONTROL
- SPL_DISABLE_OF_CONTROL
from zynq_*_defconfig files
On 1 July 2015 at 02:38, Simon Glass s...@chromium.org wrote:
Hi Tom,
On 30 June 2015 at 14:31, Tom Rini tr...@konsulko.com wrote:
On Tue, Jun 30, 2015 at 01:10:45PM -0700, York Sun wrote:
On 06/30/2015 12:01 PM, Tom Rini wrote:
On Tue, Jun 30, 2015 at 11:42:41AM -0700, York Sun wrote:
Hi Sanchayan,
I merge it.
On 02/07/2015 07:56, maitysancha...@gmail.com wrote:
Hello,
Another ping?
- Sanchayan.
On 15-06-08 12:40:41, Sanchayan Maity wrote:
Increase console IO buffer size to 1024 from the previous value of 256.
The previous value was too short for editing
Hello all,
Is anyone building / using altera_spi.c module ?
Which board currently is using this driver ?
I could not find any defconfig file using it.
Can someone provide the details of building it...
Thanks in advance.
Regards,
Chakra Divi
___
Polling of TX conf frames is not a mandatory option.
Packets can be transferred via WRIOP without TX conf frame.
Configure ldpaa_eth driver to use TX path without confirmation frame
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Joe Hershberger joe.hershber...@ni.com
---
Change infinite loop mechanism to timer based polling for QBMAN release in
ldpaa_eth_rx.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset
Changes for v3: Squashed with other patch
Changes for v4: reverted the squash and only have rx path
From: Stuart Yoder stuart.yo...@freescale.com
Stream IDs on ls2085a devices are not hardwired and are
programmed by sw. There are a limited number of stream IDs
available, and the partitioning of them is scenario dependent.
This header defines the partitioning between legacy, PCI,
and DPAA2
Volatile command does not return frame immidiately, need to wait till a frame
is available in DQRR. Ideally it should be a blocking call.
Add timeout handling for DQRR frame instead of retry counter.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Joe Hershberger
From: Stuart Yoder stuart.yo...@freescale.com
delete any existing ICID pools in the DPC and create
a new one based on the stream ID partitioning for
the SoC
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2:
Do not immediately return if the enqueue function returns -EBUSY; re-try
mulitple times.
if timeout occures, release the buffer.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset
Changes for v3: Incorporated Joe Hershberger's comments
From: Stuart Yoder stuart.yo...@freescale.com
This patch adds the infrastructure to update device
tree nodes to convey SMMU stream IDs in the device
tree. Fixups are implemented for PCI controllers
initially.
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
Signed-off-by: Prabhakar
Flush buffer before releasing to BMan after TX_conf to ensure, the core does
not have any cachelines that the WRIOP will DMA to.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset
Changes for v3: Sending as it is for patchset
Changes for
On 2 July 2015 07:46:19 CEST, Marek Vasut ma...@denx.de wrote:
So this behaves like read(2) now, right ?
Exactly for convenient use in U-Boot scripts.
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
___
U-Boot mailing list
Hello feng...@phytium.com.cn,
On Tue, 3 Feb 2015 17:19:35 +0800, feng...@phytium.com.cn
feng...@phytium.com.cn wrote:
From: David Feng feng...@phytium.com.cn
This patch add Kconfig to armv8.
Signed-off-by: David Feng feng...@phytium.com.cn
---
arch/arm/Kconfig | 16
Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects
Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in
dpio_attr. These are now offsets from the SoC QBMan portals base.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: Prabhakar
From: J. German Rivera german.riv...@freescale.com
Make it easier for the user to notice when the MC firmware
had problems booting.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for
Update qbman driver
- As per latest available qbman driver
- Use of atomic APIs
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
CC: Geoff Thorpe geoff.tho...@freescale.com
CC: Haiying Wang haiying.w...@freescale.com
CC: Roy Pledge roy.ple...@freescale.com
---
Changes for v2: Sending
From: J. German Rivera german.riv...@freescale.com
Load AIOP image from NOR flash into DDR so that the MC firmware
the MC fw can start it at boot time
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending
Management complex major version should match to the firmware present in flash.
Return error during mismatch of major version.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2: Sending as it is for patchset
Changes for v3: Incorporated Joe Hershberger's comments
Hello,
Another ping?
- Sanchayan.
On 15-06-08 12:40:41, Sanchayan Maity wrote:
Increase console IO buffer size to 1024 from the previous value of 256.
The previous value was too short for editing environment variables like
ubiboot from the console.
Signed-off-by: Sanchayan Maity
-fdelete-null-pointer-checks flag controls global dataflow analyses and
eliminate useless checks for null pointers; It assume that if a pointer is
checked after it has already been dereferenced, it cannot be null.
This flag is enabled by default.
gcc v4.9 has more optimizations added to this
Dear Albert,
In message 20150702000427.562195b4@lilith you wrote:
CONFIG_USE_PRIVATE_LIBGCC should only be an emergency-opt-in, but
never ever a default setting.
Well then, should we not revisit commits c3dd823 and 7bfd5ee, which
enable CONFIG_USE_PRIVATE_LIBGCC for sh and mips
On 2 July 2015 at 13:24, Chakra D cd...@openedev.com wrote:
Hello all,
Is anyone building / using altera_spi.c module ?
Which board currently is using this driver ?
I could not find any defconfig file using it.
Can someone provide the details of building it...
You need to search it on
Hi Joe,
-Original Message-
From: Joe Hershberger [mailto:joe.hershber...@gmail.com]
Sent: Wednesday, July 01, 2015 1:50 AM
To: Ciubotariu Codrin Constantin-B43658
Cc: u-boot; Joe Hershberger; Sun York-R58495
Subject: Re: [U-Boot] [PATCH 07/11 v2] drivers/net/vsc9953: Add commands to
On 07/02/2015 08:11 AM, Jagan Teki wrote:
On 2 July 2015 at 06:50, Masahiro Yamada yamada.masah...@socionext.com
wrote:
2015-07-02 2:08 GMT+09:00 Jagan Teki jt...@openedev.com:
On 29 June 2015 at 14:33, Jagan Teki jt...@openedev.com wrote:
This commit moves:
- CONFIG_OF_CONTROL
-
Hi Tom,
please pull two bugfixes for MIPS
The following changes since commit 891b487098ee2169a16b1bbb354aaef28aa90630:
Merge branch 'master' of git://git.denx.de/u-boot-spi (2015-07-01
15:38:12 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-mips.git master
for
On 07/02/2015 11:19 AM, Jagan Teki wrote:
On 2 July 2015 at 14:11, Michal Simek michal.si...@xilinx.com wrote:
On 07/02/2015 08:11 AM, Jagan Teki wrote:
On 2 July 2015 at 06:50, Masahiro Yamada yamada.masah...@socionext.com
wrote:
2015-07-02 2:08 GMT+09:00 Jagan Teki jt...@openedev.com:
On
Add USDHC, I2C, UART, 74LV, USB, QSPI support.
Boot Log:
U-Boot 2015.07-rc2-00085-gb5dc629 (Jul 02 2015 - 18:47:15 +0800)
CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
Reset cause: POR
Board: MX6UL 14x14 EVK
I2C: ready
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning -
PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 6)
Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---
arch/arm/include/asm/imx-common/iomux-v3.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h
ddr for i.MX6UL starts from 0x8000
Signed-off-by: Peng Fan peng@freescale.com
---
include/configs/mx6_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 6808674..ccb2d04 100644
---
Dear Tom,
In message 20150629215122.GA28577@bill-the-cat you wrote:
I've pushed v2015.04-rc3 out to the repository and tarballs should exist
soon.
Sorry for the delay, tarballs are now both in the ACD [1] (whole
U-Boot directory at [2]) and on the FTP server [3]
[1]
Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
drivers/mtd/spi/sf_dataflash.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 3111f4f..f83f994 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++
Some old dataflash chips don't have device ID,
we should identif them using bits in the flash status byte.
Add a variable status_byte in struct flash_info,
and assign correct value for above old chips.
Add those chips to the supported flash chip table
and identify them through the new variable
On 2 July 2015 at 14:11, Michal Simek michal.si...@xilinx.com wrote:
On 07/02/2015 08:11 AM, Jagan Teki wrote:
On 2 July 2015 at 06:50, Masahiro Yamada yamada.masah...@socionext.com
wrote:
2015-07-02 2:08 GMT+09:00 Jagan Teki jt...@openedev.com:
On 29 June 2015 at 14:33, Jagan Teki
Hi Marek,
On 29.06.2015 17:22, Marek Vasut wrote:
On Monday, June 29, 2015 at 02:58:15 PM, Stefan Roese wrote:
This patch adds USB EHCI host support for the common mvebu platform.
Including the Armada 38x.
Tested on DB-88F6280-GP eval board.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Marek
syscounter exists on i.MX6UL and i.MX7D, so implement the driver
in imx-common.
If want to use syscounter, define CONFIG_SYSCOUNTER_TIMER; if
still want to use GPT timer, #define CONFIG_GPT_TIMER.
Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---
Update imx register base address for i.MX6UL
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
---
arch/arm/include/asm/arch-mx6/imx-regs.h | 60 ++--
1 file changed, 41 insertions(+), 19 deletions(-)
diff --git
Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose.
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
---
arch/arm/include/asm/arch-mx6/mx6-pins.h |2 +
arch/arm/include/asm/arch-mx6/mx6ul_pins.h | 1065
Add MX6UL in Kconfig, default select SYS_L2CACHE_OFF.
update WDOG settings. No need to gate/ungate all PFDs for i.MX6UL.
Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---
arch/arm/cpu/armv7/mx6/Kconfig | 4
arch/arm/cpu/armv7/mx6/soc.c | 4 ++--
Since i.MX6UL use A7 core, but not A9 core, we do not need
the erratas for i.MX6UL. Also use syscounter for i.MX6UL.
Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---
include/configs/mx6_common.h | 8 +++-
1 file changed, 7 insertions(+), 1
Add enet, uart, i2c, ipg clock support.
Correct get_periph_clk, should account for MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
Refactor get_mmdc_ch0_clk to make all i.MX6 share one function, but not 'ifdef'
Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
Use CONFIG_PCIE_IMX for
Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime.
The 0x64 is defined as i.MX6UL CPU type value in Reference mannual,
but the value has been occupied by i.MX6D as a dummy CPU type.
So we also change i.MX6D to value 0x67.
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by:
Add i.MX 6UltraLite support and include mx6ul_14x14_evk basic board support
i.MX 6UltraLite is a high performance, ultra-efficient processor family
featuring an advanced implementation of a single Cortex-A7 core.
This patch set is based on:
https://patchwork.ozlabs.org/patch/489977/
i.MX6UL does not have GPIO6/7, so do not include them for i.MX6UL.
Signed-off-by: Peng Fan peng@freescale.com
---
drivers/gpio/mxc_gpio.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 2012f99..57a650f 100644
---
Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
drivers/mtd/spi/sf_dataflash.c | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 6bf628b..648f3ca 100644
---
Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
drivers/mtd/spi/sf_dataflash.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 8f91527..6bf628b 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++
Add error handler when write/erase flash fail.
Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
drivers/mtd/spi/sf_dataflash.c | 30 ++
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_dataflash.c
Hi Vikas,
On 01.07.2015 00:57, Vikas MANOCHA wrote:
+Cadence QSPI controller device tree bindings
+
+
+Required properties:
+- compatible : should be cadence,qspi.
+- reg : 1.Physical base address and size of SPI registers
Am 02.07.2015 um 09:39 schrieb Wolfgang Denk:
Dear Daniel,
In message 55947a25.5020...@gmail.com you wrote:
CONFIG_USE_PRIVATE_LIBGCC should be removed. If an architecture supports
a private libgcc, then it should always use it. I think for U-Boot it is
better and safer to have all code
Hello Masahiro,
On Thu, 2 Jul 2015 21:21:12 +0900, Masahiro Yamada
yamada.masah...@socionext.com wrote:
Hi Albert,
2015-07-02 6:21 GMT+09:00 Albert ARIBAUD albert.u.b...@aribaud.net:
On Thu, 16 Apr 2015 11:21:44 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hello Masahiro,
2015-07-02 21:43 GMT+09:00 Albert ARIBAUD albert.u.b...@aribaud.net:
Hello Masahiro,
On Thu, 2 Jul 2015 21:21:12 +0900, Masahiro Yamada
yamada.masah...@socionext.com wrote:
Hi Albert,
2015-07-02 6:21 GMT+09:00 Albert ARIBAUD albert.u.b...@aribaud.net:
On Thu, 16 Apr 2015 11:21:44 +0200,
2015-07-02 16:39 GMT+09:00 Wolfgang Denk w...@denx.de:
Dear Daniel,
In message 55947a25.5020...@gmail.com you wrote:
CONFIG_USE_PRIVATE_LIBGCC should be removed. If an architecture supports
a private libgcc, then it should always use it. I think for U-Boot it is
better and safer to have all
Hi Albert,
2015-07-02 6:21 GMT+09:00 Albert ARIBAUD albert.u.b...@aribaud.net:
On Thu, 16 Apr 2015 11:21:44 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hello Masahiro,
Your patch clashes with Pavel's already committed
break-if-private-libgcc-and-thumb, causing many boards to
2015-07-02 21:18 GMT+09:00 Masahiro Yamada yamada.masah...@socionext.com:
2015-07-02 8:39 GMT+09:00 Daniel Schwierzeck daniel.schwierz...@gmail.com:
Am 02.07.2015 um 00:04 schrieb Albert ARIBAUD:
Hello Wolfgang,
On Wed, 01 Jul 2015 23:50:17 +0200, Wolfgang Denk w...@denx.de wrote:
Hello Masahiro,
On Thu, 2 Jul 2015 21:54:44 +0900, Masahiro Yamada
yamada.masah...@socionext.com wrote:
2015-07-02 21:43 GMT+09:00 Albert ARIBAUD albert.u.b...@aribaud.net:
If you think we should take our time for this discussion,
will you send a pull-request with currently applied change
On Thu, Jul 2, 2015 at 8:03 AM, Peng Fan peng@freescale.com wrote:
+#if defined(CONFIG_MX6UL_EVK_EMMC_REWORK)
Why do we need this config option?
When should a user select it? Please explain it.
Regards,
Fabio Estevam
___
U-Boot mailing list
2015-07-02 8:39 GMT+09:00 Daniel Schwierzeck daniel.schwierz...@gmail.com:
Am 02.07.2015 um 00:04 schrieb Albert ARIBAUD:
Hello Wolfgang,
On Wed, 01 Jul 2015 23:50:17 +0200, Wolfgang Denk w...@denx.de wrote:
Actually I think it is inherently wrong to enable
CONFIG_USE_PRIVATE_LIBGCC by
Hi Peng,
On Thu, Jul 2, 2015 at 8:03 AM, Peng Fan peng@freescale.com wrote:
Add MX6UL in Kconfig, default select SYS_L2CACHE_OFF.
Could you tell us more about this? Why L2 cache needs to be disabled?
Regards,
Fabio Estevam
___
U-Boot mailing
Hi Wolfgang,
2015-07-02 16:34 GMT+09:00 Wolfgang Denk w...@denx.de:
Dear Albert,
In message 20150702000427.562195b4@lilith you wrote:
CONFIG_USE_PRIVATE_LIBGCC should only be an emergency-opt-in, but
never ever a default setting.
Well then, should we not revisit commits c3dd823 and
Hi Joe,
-#define CONFIG_VSC9953_PORT_ENA0x3a00
Why is this value changing? Was it just wrong before?
Sorry, I missed this comment. Yes, the correct value that only enables the port
is 0x2000. The rest of the bits are set to 1 because they are reserved and
default
From: Ulises Cardenas ulises.carde...@freescale.com
hab_status command returns a memory dump of the hab event log. But the
raw data is not human-readable. Parsing such data into readable event
will help to minimize debbuging time.
Signed-off-by: Ulises Cardenas ulises.carde...@freescale.com
---
Hi
On Jul 2, 2015 10:47 PM, Ulises.
@freescale.com wrote:
From: Ulises Cardenas ulises.carde...@freescale.com
hab_status command returns a memory dump of the hab event log. But the
raw data is not human-readable. Parsing such data into readable event
will help to minimize debbuging time.
Add a driver to support the special LDO access used by spring. This is a
custom method in the cros_ec protocol - it does not use an I2C
pass-through.
There are two implementation choices:
1. Write a special LDO driver which can talk across the EC. Duplicate all
the logic from TPS65090 for
This is not needed with driver mode. Remove it.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/misc/cros_ec.c | 268 +
include/cros_ec.h | 14 ---
2 files changed, 1 insertion(+), 281 deletions(-)
diff --git
While the AP can access the main PMIC on snow, it must coordinate with the
EC which also wants access. Drop the old definition, which can in principle
generate collision errors. We will use the new arbitration driver instead.
Signed-off-by: Simon Glass s...@chromium.org
---
Now that most exynos5250 boards can use the generic exynos5 code, switch
over to it and remove the old code.
Signed-off-by: Simon Glass s...@chromium.org
---
board/samsung/smdk5250/Makefile | 4 -
board/samsung/smdk5250/exynos5-dt.c | 306
Add support for all BUCK regulators, now that the correct register is
accessed for each.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/power/regulator/max77686.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/power/regulator/max77686.c
The kernel uses upper case for I2C unit addresses. Follow the same
convention to reduce differences.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/dts/exynos5.dtsi | 34 -
arch/arm/dts/exynos5250-arndale.dts | 16
This function should return 0 on success, not 1. Fix it.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/mmc/s5p_sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index 8e1968a..522eab9 100644
---
Many options are duplicated on the exynos5 boards. Move these to the common
files. Also some options are not used so can be removed.
Tidy this up to make the files easier to maintain.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/arndale.h | 14 ++
Add a description of the snow memory layer to assist flashing tools which
want to be able to deal with any exynos image.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/dts/exynos5250-snow.dts | 53
1 file changed, 53 insertions(+)
diff --git
This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The
driver supports probing and basic register access. It supports the standard
device tree binding and supports driver model. A regulator driver can be
provided also.
Signed-off-by: Simon Glass s...@chromium.org
---
Since the timeout is reported through normal channels, and is sometimes
expected (e.g. if the bus is being probed for a non-existent device),
don't display the message in the driver.
In general, drivers should not write to the console as this limits their
usefulness in error conditions.
When driver model is not used the current code does not correctly select
the pinmux for the I2C bus. This bug was introduced by this commit:
8dfcbaa dm: i2c: s3c24x0: adjust to dm-i2c api
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/i2c/s3c24x0_i2c.c | 2 +-
1 file changed, 1
The existing TPS65090 driver does not support driver model. Add a new one
that does. This can be used as a base for a regulator driver also. It uses
the standard device tree binding.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/power/pmic/Kconfig| 9 +
The driver name should not have a space in it. Also the regulator names
should match the case of the device tree. Fix these problems.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/power/pmic/max77686.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
The existing driver model implementation uses the old non-driver-model code
to operate, but has become impossibly tangled as a result. The actual
algorithm is quite simple.
Also the normal-speed and high-speed buses are quite different and it
doesn't seem that useful to put them in the same
As a debugging aid, allow UART3 to be used as a debug UART in SPL. This
is a precursor to proper UART support, which requires a substantial
refactor.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 5 +
drivers/serial/serial_s5p.c |
This patch does all the board configurations required to use the qspi
controller attached spi flash memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4:
- Moved SPI configs in arch/arm/Kconfig
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
arch/arm/Kconfig
stv0991 has cadence qspi controller for flash interfacing, this
patch configures the device pads clock for the controller.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: none
Changes in v3: Rebased to spi-next-dev
Changes in v2:
- removed checkpatch.pl error.
This patchset adds support to get controller sram size from device tree, fix to
support different FIFO widths adds dt binding doc.
Also this patchset enables cadence qspi controller for stv0991 soc, saves
environment in spi flash moves CONFIG_OF in the defconfig file.
Changes in v4:
- Moved
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes in v4: None
Changes in v3: Rebased to
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read half for write once at initialization.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes
This patch adds the device tree binding doc for the cadence qspi controller
also removes the not needed properties from the stv0991 device tree.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: removed changes done in socfpga dts/dtsi
Changes in v3: added new
This patch add the device tree entry for qspi controller spi flash
memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4:
- removed not needed properties from stv0991 device tree file for qspi
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Tested-by: Stefan Roese s...@denx.de
---
Changes in v4: none
Changes in v3: Rebased to spi-next-dev
Changes in v2: Fixed the
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: None
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
configs/stv0991_defconfig |1 +
include/configs/stv0991.h |1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/stv0991_defconfig
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: none
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
configs/stv0991_defconfig |1 -
include/configs/stv0991.h |4 +++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git
CONFIG_OF_SEPARATE is default define with CONFIG_OF_CONTROL, removing
this define from the board file to avoid multiple definition warning.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
Changes in v4: None
Changes in v3: Rebased to spi-next-dev
Changes in v2: None
We always use device tree on exynos, so remove the unused code.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/include/asm/arch-exynos/dp_info.h | 2 --
drivers/video/exynos_dp.c | 22 --
2 files changed, 24 deletions(-)
diff --git
This has moved to driver model so we can drop the fdtdec support.
Signed-off-by: Simon Glass s...@chromium.org
---
include/fdtdec.h | 1 -
lib/fdtdec.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 0d85d6d..95fbede 100644
---
At present the driver model GPIO API does not support pull-up/pull-down on
input GPIOs. This is required in some cases.
Add this feature to the API with two new methods that drivers can optionally
implement.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/gpio/gpio-uclass.c | 31
Hi Marek,
On Thu, Jul 02, 2015 at 08:31:37PM +0200, Marek Vasut wrote:
On Thursday, July 02, 2015 at 01:03:01 PM, Peng Fan wrote:
syscounter exists on i.MX6UL and i.MX7D, so implement the driver
in imx-common.
If want to use syscounter, define CONFIG_SYSCOUNTER_TIMER; if
still want to use GPT
We have a new one which uses driver model and device tree configuration.
Remove the old one.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/video/Makefile | 1 -
drivers/video/parade.c | 231
include/configs/peach-pi.h | 2 -
The new driver supports driver model and configuration via device tree. Add
a node for pit, which needs this driver.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/dts/exynos5420-peach-pit.dts | 128 --
1 file changed, 123 insertions(+), 5 deletions(-)
The TPS65090 has 7 FETs which are modelled as regulators. This allows them
to be controlled by drivers easier, accessed through the 'regulator' command
and used by other drivers.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/power/regulator/Kconfig | 10 ++
When a regulator command cannot honour the requested voltage, display the
limits to try to be helpful.
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_regulator.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/common/cmd_regulator.c b/common/cmd_regulator.c
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