[U-Boot] [PATCH v1 0/2] sunxi: MUSB support for the sun50i (A64)

The A64 has 3 USB controllers and 2 USB PHYs, but a somewhat odd (actually it's wasteful, as there's no way to use the 2 PHYs and the HSIC output concurrently) muxing scheme between those: * PHY 0 is multiplexed to either MUSB (dual-role) or HCI0 * PHY 1 is dedicated to HCI1 This changeset

[U-Boot] [PATCH v1] cmd: sspi: Add an additional argument to set the bus frequency

Signed-off-by: Philipp Tomsich --- cmd/spi.c | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/cmd/spi.c b/cmd/spi.c index f16ef9a..b495b87 100644 --- a/cmd/spi.c +++ b/cmd/spi.c @@ -36,51 +36,52 @@ static unsigned int

[U-Boot] [PATCH v1 1/2] sunxi (sun50i): Set CONFIG_SUNXI_USB_PHYS to 2 (the A64 has 2 PHYs)

The sun50i platform (e.g. the A64/sun50iw1p1) integrates 2 USB PHYs which are connected as follows: PHY#0 is shared between the OTG controller (MUSB) [at 01C19000] and the USB-OTG-HCI [at 01C1A000] PHY#1 is dedicated to USB-HCI0 [at 01C1B000] and can be bypassed when connecting

[U-Boot] [PATCH v2 2/3] x86: zImage: add Intel MID platforms support

From: Vincent Tinelli Intel MID platform boards have special treatment, such as boot parameter setting. Assign hardware_subarch accordingly if CONFIG_INTEL_MID is set. Reviewed-by: Bin Meng Reviewed-by: Simon Glass

[U-Boot] [PATCH v2 1/3] x86: Introduce INTEL_MID quirk option

Intel Mobile Internet Device (MID) platforms have special treatment in some cases, such as CPU enumeration or boot parameters configuration. Besides that several drivers are specifically developed for the IP blocks found on Intel MID platforms. Those drivers will be dependent to this option.

[U-Boot] [PATCH v2 3/3] x86: Intel MID platforms has no microcode update

There is no microcode update available for SoCs used on Intel MID platforms. Use conditional to bypass it. Reviewed-by: Simon Glass Signed-off-by: Andy Shevchenko --- arch/x86/cpu/mp_init.c | 2 +- 1 file changed, 1 insertion(+), 1

[U-Boot] [PATCH v1] sunxi: improve throughput in the sunxi_mmc driver

Throughput tests have shown the sunxi_mmc driver to take over 10s to read 10MB from a fast eMMC device due to excessive delays in polling loops. This commit restructures the main polling loops to use get_timer(...) to determine whether a (millisecond) timeout has expired. We choose not to use

[U-Boot] [PATCH v1 2/2] sun8i_emac: remove unnecessary bit-masking for mdio_read/write

The MDIO read/write builds up the MII_CMD register from scratch (starting with a value of 0). No need to mask out any fields before writing the new values. Signed-off-by: Philipp Tomsich --- drivers/net/sun8i_emac.c | 8 1 file changed, 8

[U-Boot] [PATCH v2] cmd: sspi: Add an additional argument to set the bus frequency

The spi command is rather useful for board verification, bring-up and software testing. One use in our lab is the testing of the clock code, which requires the ability to send data at different SPI clocks. The changeset adds an additional (optional) positional argument to the 'spi' command that

[U-Boot] [PATCH v1 0/2] sun8i_emac: set MDC divider for MDIO read/write

To ensure compatibility with all PHYs, we need to keep the MDIO clock (MDC) below 2.5MHz (the guaranteed operating limit from IEEE 802.3), even if some PHYs will tolerate higher speeds. This changeset also cleans up the MDIO read/write functions by removing pointless bit-masking in a variable

[U-Boot] [PATCH v1] armv8: spl: Call spl_relocate_stack_gd for ARMv8

As part of the startup process for boards using the SPL, we need to call spl_relocate_stack_gd. This is needed to set up malloc with its DRAM buffer. Signed-off-by: Philipp Tomsich --- arch/arm/lib/crt0_64.S | 8 +++- 1 file changed, 7 insertions(+), 1

Re: [U-Boot] Veyron-speedy u-boot

On 17 February 2017 at 10:18, Riley Baird wrote: > Hi Tomeu and Simon, > > Thanks for giving me pointers on how the system works and how to get > u-boot onto it. I'll try and get it working over the next couple of > days. > > I'm very glad that it's possible to chainload

[U-Boot] [PATCH v1 0/2] sunxi: A64: support I2C and R_I2C

This changeset adds the necessary defines and pin-config to enable I2C and R_I2C on the sun50iw1p1 (A64). Tested on the A64-uQ7. Philipp Tomsich (2): sunxi (sun50i): support i2c on A64 (pin-config, clocking) sunxi (sun50i): support R_I2C on A64 (pin-config, clocking)

[U-Boot] [PATCH v1 1/2] sunxi (sun50i): support i2c on A64 (pin-config, clocking)

Signed-off-by: Philipp Tomsich --- arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ arch/arm/mach-sunxi/clock.c| 2 ++ board/sunxi/board.c| 18 ++ 3 files changed, 23 insertions(+) diff --git

[U-Boot] [PATCH v1 2/2] sunxi (sun50i): support R_I2C on A64 (pin-config, clocking)

Signed-off-by: Philipp Tomsich --- arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/clock.c| 2 -- board/sunxi/board.c| 11 ++- 4 files changed, 12

[U-Boot] [PATCH v1 2/2] sunxi (sun50i): improved USB support for sun50i (A64)

These changes add support for MUSB (OTG) and HCI1 on sun50i (A64) and try to improve documentation: * adds support for the shared PHY (MUSB and OTG-EHCI/OTG-OHCI) on sun50i (A64) in musb-new/sunxi.c to automatically change the PHY routing when opening/closing MUSB * sets up the

[U-Boot] [PATCH v1 06/11] sunxi: add clock driver (UCLASS_CLK) support for sunxi

When CONFIG_CLK is defined, we now provide support for the basic clock configuration of peripherals on sunxi: * clk-sunxi-mod.c implements support for module clocks, which performs parent selection (determined via the device-tree) and determines/configures a pre-divider and divider when

[U-Boot] [PATCH v1] env_mmc: configure environment offsets via device tree

This introduces the ability to override the environment offets from the device tree by setting the following nodes in '/config': 'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET 'u-boot,mmc-env-offset-redundant' - overrides

[U-Boot] [PATCH v1 1/2] part_efi: support padding between the GPT header and partition entries

Some architectures require their SPL loader at a fixed address within the first 16KB of the disk. To avoid an overlap with the partition entries of the EFI partition table, the first safe offset (in bytes, from the start of the device) for the entries can be set through

[U-Boot] [PATCH v1 2/2] sunxi-common: add EFI_PARTITION_ENTRIES_OFF, CONFIG_RANDOM_UUID and CONFIG_CMD_GPT

Signed-off-by: Philipp Tomsich --- include/configs/sunxi-common.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 4f61452..e8e26a5 100644 ---

[U-Boot] [PATCH v1 0/2] disk: efi: allow gap before partition entries

Motivated by the the SPL layout for SD/MMC devices on Allwinner SoCs (the SPL code needs to reside an 8K offset into the device), we add support for leaving a gap between the MBR (LBA#0), GPT header (LBA#1) and GPT partition entries (linked from field in the GPT header). Note that this affects

[U-Boot] [PATCH v1] dtoc: make ScanTree recurse into subnodes

Previously, dtoc could only process the top-level nodes which led to device nodes in hierarchical trees to be ignored. E.g. the mmc0 node in the following example would be ignored, as only the soc node was processed: / { soc { mmc0 { /* ... */

[U-Boot] [PATCH v1] sun8i_emac: configure PHY reset GPIO via DM

This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. For easier migration for the Designware driver, the prefix of DTB entries has simply been changed from 'snps,' to 'allwinner,': i.e.

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

On Wed, 2017-02-15 at 18:53 -0800, Dalon Westergreen wrote: > On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote: > > > > On 02/15/2017 10:48 PM, Dalon Westergreen wrote: > > > > > > > > > On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote: > > > > > > > > > > > > On 02/14/2017 07:28 PM,

[U-Boot] [PATCH v1 1/2] sun8i_emac: Set MDC divider for MDIO read/write

The IEEE 802.3 standard guarantees operation of the MDIO signals at up to 2.5MHz (anything above this is a vendor-specific feature, although most PHYs work at higher frequencies). With the EMAC being fed by a (typically) 300MHz clock (e.g. on the A64 this is AHB2, which should be kept at 300MHz

Re: [U-Boot] ARMv7 EFI loader broken?

On 17 February 2017 at 11:26, Misha Komarovskiy wrote: > Hello Michal, > > On Fri, Feb 17, 2017 at 1:38 AM, Michal Suchanek wrote: >> On 14 February 2017 at 15:50, Michal Suchanek wrote: >>> Hello, >>> >>> I tired to build u-boot master

Re: [U-Boot] [PATCH v3] armv7m: Add SysTick timer driver

Hi, > -Original Message- > From: Phil Edworthy [mailto:phil.edwor...@renesas.com] > Sent: Friday, February 17, 2017 12:22 AM > To: Albert Aribaud > Cc: Albert Aribaud ; Tom Rini ; > Vikas MANOCHA

Re: [U-Boot] [PATCH v1] cmd: sspi: Add an additional argument to set the bus frequency

On Fri, Feb 17, 2017 at 06:27:28PM +0100, Philipp Tomsich wrote: > Signed-off-by: Philipp Tomsich Please add a bit more information here as to why you need this, in the commit message. [snip] > + if (argc >= 5) > + hz =

Re: [U-Boot] [PATCH v6 3/3] Kconfig: Disable non-FIT SPL loading for TI secure devices

On Thu, Feb 16, 2017 at 11:18:40AM -0600, Andrew F. Davis wrote: > Non-FIT SPL image loading support should be disabled for TI secure > devices as the image handlers for those image types do not follow > our secure boot flow. > > Signed-off-by: Andrew F. Davis Reviewed-by: Tom

Re: [U-Boot] [PATCH v6 2/3] spl: Add option to enable SPL Legacy image support

On Thu, Feb 16, 2017 at 11:18:39AM -0600, Andrew F. Davis wrote: > Add a Kconfig option that enables Legacy image support, this allows > boards to explicitly disable this, for instance when needed for > security reasons. > > Signed-off-by: Andrew F. Davis > Reviewed-by: Simon Glass

Re: [U-Boot] [PATCH v6 1/3] spl: Convert CONFIG_SPL_ABORT_ON_RAW_IMAGE into a positive option

On Thu, Feb 16, 2017 at 11:18:38AM -0600, Andrew F. Davis wrote: > CONFIG_SPL_ABORT_ON_RAW_IMAGE causes SPL to abort and move on when it > encounters RAW images, express this same functionality as a positive > option enabling support for RAW images: CONFIG_SPL_RAW_IMAGE_SUPPORT > > Also move

Re: [U-Boot] Veyron-speedy u-boot

Hi Riley, On 16 February 2017 at 21:44, Simon Glass wrote: > Hi Riley, > > On 15 February 2017 at 17:31, Riley Baird wrote: > >> 3. Do I just have to sign u-boot-dtb.img with vbutil_kernel before >> dd-ing it onto a USB, or do I have to do something

Re: [U-Boot] [PATCH] dm: rtc: Add 16-bit read/write support

Hi Bin, On 17.02.2017 06:24, Bin Meng wrote: At present there are only 8-bit and 32-bit read/write routines in the rtc uclass driver. This adds the 16-bit support. Signed-off-by: Bin Meng --- drivers/rtc/rtc-uclass.c | 30 ++ include/rtc.h

Re: [U-Boot] [PATCH v4 26/28] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

On Mon, Jan 23, 2017 at 12:19 PM, Marek Vasut wrote: > On 01/10/2017 06:20 AM, Chee Tien Fong wrote: >> From: Tien Fong Chee >> >> Signed-off-by: Tien Fong Chee >> Cc: Marek Vasut >> Cc: Dinh Nguyen

Re: [U-Boot] [PATCH v4 11/28] arm: socfpga: wrap system manager functions for A5/C5 devices

On Mon, Jan 23, 2017 at 11:53 AM, Marek Vasut wrote: > On 01/10/2017 06:20 AM, Chee Tien Fong wrote: >> From: Tien Fong Chee >> >> The system manager on Arria10 is not used for pin muxing duties, so wrap >> these functions for GEN5 devices only. >> >>

Re: [U-Boot] ARMv7 EFI loader broken?

Hello Michal, On Fri, Feb 17, 2017 at 1:38 AM, Michal Suchanek wrote: > On 14 February 2017 at 15:50, Michal Suchanek wrote: >> Hello, >> >> I tired to build u-boot master for Snow board, install grub, chainload grub. >> >> In short, it fails. >> >>

Re: [U-Boot] [PATCH v4 02/28] arm: socfpga: arria10: add sdram defines for Arria10

On Mon, Jan 23, 2017 at 11:40 AM, Marek Vasut wrote: > On 01/10/2017 06:20 AM, Chee Tien Fong wrote: >> From: Tien Fong Chee >> >> Add the structures for the SDRAM controller on Arria10. >> >> Signed-off-by: Dinh Nguyen >>

Re: [U-Boot] [PATCH v4 06/28] arm: socfpga: arria10: add socfpga_arria10_socdk config

On Mon, Jan 23, 2017 at 11:46 AM, Marek Vasut wrote: > On 01/10/2017 06:20 AM, Chee Tien Fong wrote: >> From: Tien Fong Chee >> >> Add config for the Arria10 SoC Development Kit. >> >> Signed-off-by: Dinh Nguyen >>

Re: [U-Boot] [PATCH v4 15/28] arm: socfpga: combine clrbits/setbits into a single clrsetbits

On Fri, Feb 17, 2017 at 3:54 PM, Marek Vasut wrote: > On 02/16/2017 04:34 AM, Ley Foon Tan wrote: >> Hi Marek >> >> On Mon, Jan 23, 2017 at 11:58 AM, Marek Vasut wrote: >>> >>> On 01/10/2017 06:20 AM, Chee Tien Fong wrote: From: Tien Fong Chee

Re: [U-Boot] Veyron-speedy u-boot

Hi Tomeu and Simon, Thanks for giving me pointers on how the system works and how to get u-boot onto it. I'll try and get it working over the next couple of days. I'm very glad that it's possible to chainload and the output comes out on the laptop screen, because I got a spreadsheet to work out

Re: [U-Boot] [PATCH v4 15/28] arm: socfpga: combine clrbits/setbits into a single clrsetbits

On 02/16/2017 04:34 AM, Ley Foon Tan wrote: > Hi Marek > > On Mon, Jan 23, 2017 at 11:58 AM, Marek Vasut wrote: >> >> On 01/10/2017 06:20 AM, Chee Tien Fong wrote: >>> From: Tien Fong Chee >>> >>> There is no dependency on doing a separate clrbits first

[U-Boot] [PATCH 1/7] arm64: dts: add support for Rockchip rk3328 soc

Add dts binding header for rk3328, files origin from kernel. Signed-off-by: William Zhang Signed-off-by: Kever Yang --- arch/arm/dts/Makefile |1 + arch/arm/dts/rk3328-evb.dts| 45 +

[U-Boot] [PATCH 5/7] sysreset: add support for rockchip rk3328 soc

Add rk3328 sysreset driver. Signed-off-by: William Zhang Signed-off-by: Kever Yang --- drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_rk3328.c | 45 ++ 2 files changed, 46

[U-Boot] [PATCH 6/7] board: rockchip: add support for rk3328 evb

evb-rk3328 is an evb from Rockchip based on rk3328 SoC: - 2 USB2.0 Host port; - 1 USB3.0 Host port; - 1 HDMI port; - 2 10/100M eth port; - 2GB ddr; - 16GB eMMC; - UART to USB debug port; Signed-off-by: William Zhang Signed-off-by: Kever Yang

[U-Boot] [PATCH 7/7] config: add support for evb-rk3328

Enable board config for evb-rk3328. SDcard and eMMC boot is OK in this initial version, USB and EMAC function is not available now, will comes later. Signed-off-by: William Zhang Signed-off-by: Kever Yang ---

[U-Boot] [PATCH 4/7] pinctrl: rockchip: add support for rk3328

Add rk3328 pinctrl driver and grf/iomux structure definition. Signed-off-by: William Zhang Signed-off-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 134 drivers/pinctrl/Kconfig |

[U-Boot] [PATCH 3/7] clk: rockchip: add support for rk3328

Add rk3328 clock driver and cru structure definition. Signed-off-by: William Zhang Signed-off-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 65 +++ drivers/clk/rockchip/Makefile | 1 +

[U-Boot] [PATCH 2/7] ARM64: rockchip: add support for rk3328 SoC

RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang Signed-off-by:

[U-Boot] [PATCH v3] armv7m: Add SysTick timer driver

The SysTick is a 24-bit down counter that is found on all ARM Cortex M3, M4, M7 devices and is always located at a fixed address. The number of reference clock ticks that correspond to 10ms is normally defined in the SysTick Calibration register's TENMS field. However, on some devices this is

Re: [U-Boot] [PATCH] sunxi: Add defconfig for Allwinner A23 EVB

On Thu, Feb 16, 2017 at 11:46:42AM +0100, Florent Jacquet wrote: > This enables the support for the Allwinner A23 Evaluation Board (EVB), > that already had a device tree (from Linux) but no defconfig. > > This board has an AXP223 PMIC, some NAND, Audio out and in plugs, an > accelerometer and

Re: [U-Boot] [PATCH v4 25/28] arm: socfpga: arria10: Added drivers for Arria10 clock manager

On Mon, Jan 23, 2017 at 12:18 PM, Marek Vasut wrote: > On 01/10/2017 06:20 AM, Chee Tien Fong wrote: >> From: Tien Fong Chee >> >> The drivers is restructured such common functions, gen5 functions, and >> arria10 functions are moved to clock_manager.c,

Re: [U-Boot] [PATCH v2 00/10] zynq: clk: Move zynq platform to clock framework

On 17.2.2017 08:33, stefan.herbrechtsme...@weidmueller.com wrote: > Hi Michal, > >> -Ursprüngliche Nachricht- >> Von: Michal Simek [mailto:michal.si...@xilinx.com] >>> >> Hi Stefan, >> >> On 6.2.2017 11:14, stefan.herbrechtsme...@weidmueller.com wrote: >>> Hi Michal, >>>

[U-Boot] x86: SecureBoot: Bay Trail

Hi, i'm implementing Secure Boot with U-Boot on a Intel Atom E3800 Series (Bay Trail) based Plattform. I did manage to get the first boot stage (Initial Boot Block) verified by the Trusted Execution Engine, next i need to verify the "ramstage" as they call it.  Intel provides a manual on how to

Re: [U-Boot] [PATCH v2] Add single register pin controller driver

Hi All, I have been following this work. Masahiro, perhaps have another look at pinctrl_select_state_simple (drivers/pinctrl/pinctrl-uclass.c) as this could be where the confusion lies. This function calls set_state_simple operation with the pinctrl node as the first 'dev' parameter, and the

[U-Boot] [PATCH 0/7] add support for rk3328 SoC

This patchset is to support rk3328 Soc, including some basic driver like clock, pinctrl, sysreset and etc. This version enables eMMC and sd-card boot, USB and MAC driver is not ready. RK3328 is a quad-core cortex-A53 SoC, it needs ATF support, so I would like to send the U-Boot driver without

[U-Boot] U-boot FIT Signature

Good morning, I am working with FIT image in U-Boot 2013.07. I have configured the image verification with signed image and kernel boots fine so, I would like to know if I can store my public key in an external device (like crypto-memory or an i2c device) because I am storing the key in DBT

Re: [U-Boot] [PATCH v2 00/10] zynq: clk: Move zynq platform to clock framework

> -Ursprüngliche Nachricht- > Von: Michal Simek [mailto:michal.si...@xilinx.com] > > On 17.2.2017 10:21, Michal Simek wrote: > > On 17.2.2017 08:33, stefan.herbrechtsme...@weidmueller.com wrote: > >> Hi Michal, > >> > >>> -Ursprüngliche Nachricht- > >>> Von: Michal Simek

Re: [U-Boot] [PATCH] tools: kwbimage: Fix unchecked return value and fd leak

On 13.02.2017 10:11, Mario Six wrote: The return value of fstat was not checked in kwbimage, and in the case of an error, the already open file was not closed. Fix both errors. Reported-by: Coverity (CID: 155971) Reported-by: Coverity (CID: 155969) Signed-off-by: Mario Six

Re: [U-Boot] x86: SecureBoot: Bay Trail

Hi Markus, On Fri, Feb 17, 2017 at 5:26 PM, Markus Valentin wrote: > Hi, > > i'm implementing Secure Boot with U-Boot on a Intel Atom E3800 Series (Bay > Trail) based Plattform. > > I did manage to get the first boot stage (Initial Boot Block) verified by the > Trusted Execution

Re: [U-Boot] [PATCH v2 00/10] zynq: clk: Move zynq platform to clock framework

On 17.2.2017 12:51, stefan.herbrechtsme...@weidmueller.com wrote: >> -Ursprüngliche Nachricht- >> Von: Michal Simek [mailto:michal.si...@xilinx.com] >> >> On 17.2.2017 10:21, Michal Simek wrote: >>> On 17.2.2017 08:33, stefan.herbrechtsme...@weidmueller.com wrote: Hi Michal,

[U-Boot] Please pull u-boot-marvell/master

Hi Tom, please pull the following fixes for MVEBU. Currently, I've not planned to send anything else for the upcoming release. Thanks, Stefan The following changes since commit 85d0bea153c76f4a3912b5683222885bfd37c769: Prepare v2017.03-rc2 (2017-02-13 11:47:45 -0500) are available in the

Re: [U-Boot] [PATCH] tools: kwboot: don't adjust destaddr when patching the image

On 15.02.2017 03:34, Chris Packham wrote: Commit 94084eea3bd3 ("tools: kwbimage: Fix dest addr") changed kwbimage to do this adjustment. So now the adjustment in kwboot is not needed (and would prevent UART booting for images generated by the new kwbimage). Remove the destaddr adjustment in

Re: [U-Boot] [PATCH v2 00/10] zynq: clk: Move zynq platform to clock framework

On 17.2.2017 10:21, Michal Simek wrote: > On 17.2.2017 08:33, stefan.herbrechtsme...@weidmueller.com wrote: >> Hi Michal, >> >>> -Ursprüngliche Nachricht- >>> Von: Michal Simek [mailto:michal.si...@xilinx.com] >>> Hi Stefan, >>> >>> On 6.2.2017 11:14,

Re: [U-Boot] [PATCH v1] cmd: itest: correct calculus for long format

On Fri, Feb 10, 2017 at 8:38 PM, Simon Glass wrote: > On 10 February 2017 at 05:59, Andy Shevchenko > wrote: >> From: Sebastien Colleur >> >> itest shell command doesn't work correctly in long format when >>

Re: [U-Boot] [PATCH v1] cmd: itest: correct calculus for long format

On 17.02.2017 13:57, Andy Shevchenko wrote: On Fri, Feb 10, 2017 at 8:38 PM, Simon Glass wrote: On 10 February 2017 at 05:59, Andy Shevchenko wrote: From: Sebastien Colleur itest shell command doesn't work

[U-Boot] [PATCH v2 1/2] mmc: pci: Add CONFIG_MMC_PCI

From: Felipe Balbi We don't want pci_mmc to compile every time x86 compiles, only when there's a platform that needs it. For that reason, we're adding a new CONFIG_MMC_PCI which platforms can choose to enable. Suggested-by: Jaehoon Chung

[U-Boot] [PATCH v2 2/2] mmc: tangier: Add Intel Tangier eMMC/SDHCI driver

From: Felipe Balbi This patch adds Intel Tangier eMMC/SDHCI driver. Signed-off-by: Vincent Tinelli Signed-off-by: Felipe Balbi Signed-off-by: Andy Shevchenko ---

Re: [U-Boot] [PATCH v1] cmd: itest: correct calculus for long format

On Fri, Feb 17, 2017 at 3:00 PM, Stefan Roese wrote: > On 17.02.2017 13:57, Andy Shevchenko wrote: >> To whom should I send this to get it applied? Or just wait when >> maintainers pick this up? > As this patch doesn't fall into a special custodian responsibility, Tom > usually

Re: [U-Boot] [PATCH v1 3/3] x86: Intel MID platforms has no microcode update

On Fri, Feb 17, 2017 at 3:22 AM, Bin Meng wrote: > On Wed, Feb 15, 2017 at 5:52 PM, Andy Shevchenko > wrote: >> On Wed, 2017-02-15 at 11:10 +0800, Bin Meng wrote: >>> On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko >>>