Marek Vasut schrieb am Mi., 9. Okt. 2019, 23:01:
> On 10/9/19 8:06 PM, Simon Goldschmidt wrote:
> [...]
> >>> Based on my understand through this register
> >>> fpga_mgr_fpgamgrdata
> >>> address map (0xFFCFE400-0xFFCFE7FF) on pg. 207 , the 256 bytes
> >>> of
> >>> FIFO
>
Hi Simon,
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
>
> The Primary-to-Sideband bus (P2SB) is used to access various peripherals
> through memory-mapped I/O in a large chunk of PCI space. The space is
> segmented into different channels and peripherals are accessed by
> device-specific
Hi Peter,
On 2019/10/9 下午8:01, Peter Robinson wrote:
On Wed, Oct 9, 2019 at 11:08 AM Kever Yang wrote:
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now
On Thu, Oct 10, 2019 at 2:42 AM Simon Goldschmidt
wrote:
>
> Am 02.10.2019 um 11:23 schrieb Simon Goldschmidt:
> > On Wed, Oct 2, 2019 at 10:13 AM Ley Foon Tan wrote:
> >>
> >> On Wed, Sep 18, 2019 at 12:23 PM Simon Goldschmidt
> >> wrote:
> >>>
> >>>
> >>>
> >>> Ley Foon Tan schrieb am Mi.,
Enable HBMC and HyperFlash in A72 SPL and A72 U-Boot
Signed-off-by: Vignesh Raghavendra
---
configs/j721e_evm_a72_defconfig | 12
1 file changed, 12 insertions(+)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 5cb933d87886..7ddf85fea743 100644
This series adds support for HyperBus Memory Controller of TI's J721e
and AM654 SoCs.
Vignesh Raghavendra (6):
mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined
mtd: Add TI HyperBus Memory Controller driver
arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node
arm: dts:
AM654/J721e has HyperBus Memory Controller that supports HyperFlash and
HyperRAM devices. It provides a memory mapped interface to interact with
these devices. Add a driver to support the same.
Driver calibrates the controller, setups up for MMIO access and probes
HyperFlash child node.
Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build
error when CONFIG_SYS_MONITOR_BASE is not defined.
Signed-off-by: Vignesh Raghavendra
---
v2:
Make macro check consistent as pointed out by Stefan
drivers/mtd/cfi_flash.c | 6 --
1 file changed, 4 insertions(+), 2
Hi Simon,
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
>
> This models some sort of interrupt thingy but there are so many
> abreviations that I cannot find out what it stands for. It is something
> to do with interrupts.
>
After I read the ApolloLake datasheet, the ITSS contains the
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> The write functions do actually change the contents of memory so it is not
> correct to use 'const'. Remove it.
>
> Signed-off-by: Simon Glass
> ---
>
> common/iotrace.c | 6 +++---
> include/iotrace.h | 13 ++---
> 2 files
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
>
> Move the code to determine the size of a cache record into a function so
> we can use it elsewhere in this file.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/lib/mrccache.c | 15 ---
> 1 file changed, 8 insertions(+), 7
On Wed, Oct 09, 2019 at 07:41:40PM +0200, Heinrich Schuchardt wrote:
> On 10/9/19 9:19 AM, AKASHI Takahiro wrote:
> >There is no practical reason to set a maxmum length of text either for
> >file path or whole device path in device path-to-text conversion.
> >
> >Signed-off-by: AKASHI Takahiro
>
Hi Simon,
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
>
> At present the records are 4KB in size. This is unnecessarily large when
> the SPI-flash erase size is 256 bytes. Reduce it so it will be more
But this will break for SPI-flash erase size that is not 256 bytes?
> efficient with
Define CONFIG_SYS_MAX_FLASH_BANKS_DETECT so that number of flash banks
are automatically detected by CFI flash driver
Signed-off-by: Vignesh Raghavendra
---
include/configs/j721e_evm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/configs/j721e_evm.h
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node for the
same.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/dts/k3-j721e-som-p0.dtsi | 34 +++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi
Add DT node for HyperBus Memory Controller in the FSS. On J721e, its not
possible to use OSPI0 and HBMC simultaneously as they are muxed within
the Flash Subsystem hence disable HBMC by default as keep OSPI enabled.
Bootloader will fixup DT when it detects HyperFlash instead of OSPI.
On Wed, Oct 09, 2019 at 07:56:04PM +0200, Heinrich Schuchardt wrote:
> On 10/9/19 7:30 AM, AKASHI Takahiro wrote:
> >This function, and hence rsa_verify(), will perform RSA verification
> >with two essential parameters for a RSA public key in contract of
> >rsa_verify_with_keynode(), which
Hi Simon,
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> Intel x86 SoCs have a power manager/controller which handles several
> power-related aspects of the platform. Add a uclass for this, with a few
> useful operations.
>
I don't like to create another x86 specific uclass for this
> Subject: [PATCH 3/3] video: mxsfb: set gd->fb_base
>
> Set gd->fb_base so it can be shown with bdinfo command.
>
> Signed-off-by: Sébastien Szymanski
> ---
> drivers/video/mxsfb.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index
>
> Subject: [PATCH 1/3] imx6ul: opos6ul: migrate to DM_ETH
>
> Migrate to DM_ETH and remove code that is no longer necessary.
>
> Signed-off-by: Sébastien Szymanski
> ---
> arch/arm/mach-imx/mx6/opos6ul.c | 76 +++--
> configs/opos6uldev_defconfig| 2 +
>
On Wed, 9 Oct 2019 06:30:36 +
Peng Fan peng@nxp.com wrote:
...
> > + gd->fb_base = fb_start;
>
> Should this be gd->fb_base = plat->base?
yes, please use plat->base here.
--
Anatolij
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> Subject: [PATCH 2/3] opos6uldev: migrate to DM_VIDEO
>
> Migrate to DM_VIDEO, update the device tree and remove code that is no
> longer necessary.
>
> Signed-off-by: Sébastien Szymanski
> ---
> arch/arm/dts/imx6ul-opos6uldev-u-boot.dtsi | 10 ++
> arch/arm/dts/imx6ul-opos6uldev.dts
Hi Stefan,
On 10/09/19 10:40 AM, Vignesh Raghavendra wrote:
> This series adds support for HyperBus Memory Controller of TI's J721e
> and AM654 SoCs.
>
> Vignesh Raghavendra (6):
> mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined
> mtd: Add TI HyperBus Memory Controller driver
Dear Tom,
> From: Mans Rullgard
>
> This fixes a wrongly indented block of code.
>
> Signed-off-by: Mans Rullgard
> [lukma: Make the commit message more verbose]
> Signed-off-by: Lukasz Majewski
>
Tom, are there any issues preventing this patch from being applied to
-master?
> ---
>
>
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x4 instead of 0x1000,
so that the SPL can have 0x4000 as code
Hello,
I have an NXP i.MX8MQ and I am attempting to build u-boot to boot off a
SD card. NXP provides a demo image that I can flash on to a SD and it
boots without an issue, printing the following info to the serial console:
U-Boot 2018.03-imx_v2018.03_4.14.98_2.0.0_ga+g87a19df (Apr 11 2019 -
Dear Tom,
> From: Mans Rullgard
>
> This change allows setting pre-defined eMMC boot partition for SPL
> eMMC booting. It is necessary in the case when one wants to boot
> (through falcon boot) from eMMC after loading SPL from other memory
> (like SPI-NOR).
>
> Signed-off-by: Mans Rullgard
>
efi_dp_from_name() uses a fixed length (32) of buffer, and so it cannot
handle a long file path name. This patch set lifts the upper limit
as well as other limitations regarding file paths.
For example, without this patch set,
=> efi boot add 1 TEST scsi 1:1
This patch will lift the upper limit of maximum path length.
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_device_path.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index
Somehow EMSDP & IoT DK boards were skipped on ARC boads conversion
to DM MMC. So doing it now.
Signed-off-by: Alexey Brodkin
---
Changes v2 -> v3:
* Fixed SDIO bus interface unit clock (BIU)
According to the documentation SDIO BIU clock is just "apb_clk"
which is 50 MHz by default while
Dear Tom,
In message <20191007211543.GQ6716@bill-the-cat> you wrote:
>
> It's release day and while we've once again had some last minute
> regression fixes, I feel things are as stable as they are likely to get
> so I've tagged and released v2019.07 and I would like to thank all of
> our
Dear Tom,
> This define indicates if DM_SPI shall be supported in SPL. This allows
> proper operation of DM converted SPI drivers in SPL, which use
> #if !CONFIG_IS_ENABLED(DM_SPI) to also support not yet DM/DTS
> converted boards.
>
> Signed-off-by: Lukasz Majewski
Tom, are there any issues
On 07/10/2019 18:02, Tom Rini wrote:
On Mon, Oct 07, 2019 at 11:43:07AM +0200, Jean-Jacques Hiblot wrote:
On 06/10/2019 19:12, Tom Rini wrote:
On Sun, Oct 06, 2019 at 04:57:29PM +, Auer, Lukas wrote:
Hi Jean-Jacques,
On Fri, 2019-09-20 at 17:28 +0200, Jean-Jacques Hiblot wrote:
To
From: Faiz Abbas
Enable configs for supporting SPL_DFU bootmode.
Signed-off-by: Faiz Abbas
Signed-off-by: Jean-Jacques Hiblot
---
configs/dra7xx_evm_defconfig| 6 ++
configs/dra7xx_hs_evm_defconfig | 6 ++
2 files changed, 12 insertions(+)
diff --git
Hi Vignesh,
sorry for the late review.
On 10.09.19 07:10, Vignesh Raghavendra wrote:
Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build
error when CONFIG_SYS_MONITOR_BASE is not defined.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/cfi_flash.c | 5 -
1 file
Back in the day on early board samples built-in Digilent JTAG probe
was not functional so we used externally attached Ashling Opella-XD
probe. But now with production units everything works as expected and
so we anybody may enjoy readily avaialble built-in JTAG probe so
we specify Digilent oprion
On 10/8/19 7:25 PM, Igor Opaniuk wrote:
> Hi Marek,
Hi,
[...]
>> drivers/usb/host/ehci-mx6.c | 37 +
>> 1 file changed, 37 insertions(+)
>>
>> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
>> index 33abfeada0..e9e6ed596d 100644
>>
17:14:02 -0400)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
tags/u-boot-imx-20191009
for you to fetch changes up to 9fb50c68daa696056c7842989e5f7fae1d326b34:
ARM: imx6q_logic: Fix MMC2 booting (2019-10-08 16:36:37 +0200
Dear Tom,
> This define indicates if DM_GPIO shall be supported in SPL. This
> allows proper operation of DM converted GPIO drivers in SPL, which use
> boards.
>
> Signed-off-by: Lukasz Majewski
> ---
>
> Changes in v2:
> - Add dependency on DM_GPIO
>
Tom, are there any issues preventing
From: Eugen Hristev
The Microchip Flexcom is just a wrapper which embeds a SPI controller,
an I2C controller and an USART.
Only one function can be used at a time and is chosen at boot time according
to the device tree.
The bindings are kept as in Linux.
The driver registers to MISC_UCLASS.
From: Eugen Hristev
enable driver model for i2c, eeprom for mac retrieval from eeprom i2c memory,
and microchip_flexcom driver.
Signed-off-by: Eugen Hristev
---
configs/sam9x60ek_mmc_defconfig | 7 +++
configs/sam9x60ek_nandflash_defconfig | 7 +++
From: Eugen Hristev
Add node for Flexcom0.
Signed-off-by: Eugen Hristev
---
arch/arm/dts/sam9x60.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index e01539e..41ac1f1 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++
From: Faiz Abbas
Expand SPL_MULTI_DTB_FIT to accommodate usb peripheral nodes being
added to support SPL_DFU bootmode.
Signed-off-by: Faiz Abbas
Signed-off-by: Jean-Jacques Hiblot
---
configs/dra7xx_evm_defconfig| 2 +-
configs/dra7xx_hs_evm_defconfig | 2 +-
2 files changed, 2
The purpose of this series is to provide the SPL with ability to boot
u-boot from DFU.
The DRA7x can download the SPL over the USB1 port when configured in
the USB peripheral boot mode. Details on how this can be acheived with
the EVMs can found here http://www.ti.com/lit/an/sprac33/sprac33.pdf
From: Faiz Abbas
Add usb peripheral and usb phy nodes in spl to enable SPL_DFU bootmode.
Signed-off-by: Faiz Abbas
Signed-off-by: Jean-Jacques Hiblot
---
arch/arm/dts/dra7-evm-u-boot.dtsi | 17 +
arch/arm/dts/dra71-evm-u-boot.dtsi | 17 +
Hi Simon,
On 01/10/19 11:58 AM, Simon Goldschmidt wrote:
> On Tue, Oct 1, 2019 at 6:58 AM wrote:
>>
>>
>>
>> On 09/27/2019 07:43 AM, Vignesh Raghavendra wrote:
>>> External E-Mail
>>>
>>>
>>> Older variants of n25q256* and n25q512* do not support 4 Byte stateless
>>
>> nit: drop "older variants
Hi Vignesh,
On Wed, Oct 9, 2019 at 12:58 PM Vignesh Raghavendra wrote:
>
> Hi Simon,
>
> On 01/10/19 11:58 AM, Simon Goldschmidt wrote:
> > On Tue, Oct 1, 2019 at 6:58 AM wrote:
> >>
> >>
> >>
> >> On 09/27/2019 07:43 AM, Vignesh Raghavendra wrote:
> >>> External E-Mail
> >>>
> >>>
> >>> Older
There is no practical reason to set a maxmum length of text either for
file path or whole device path in device path-to-text conversion.
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_device_path_to_text.c | 90 +---
1 file changed, 80 insertions(+), 10 deletions(-)
device_path strcuture has 2 bytes of "length" field, and so
file path length should not exceed this limit, 65535.
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_device_path.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/lib/efi_loader/efi_device_path.c
From: Eugen Hristev
Add microchip flexcom driver to at91.
Signed-off-by: Eugen Hristev
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c536566..628fa6e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -245,6 +245,7 @@ S: Maintained
T: git
From: Eugen Hristev
Add i2c0 bus as subnode to flx0.
Add eeprom memory as slave device to i2c0.
Signed-off-by: Eugen Hristev
---
arch/arm/dts/sam9x60ek.dts | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/dts/sam9x60ek.dts
From: Eugen Hristev
Retrieve mac address from i2c eeprom at boot time.
Signed-off-by: Eugen Hristev
---
board/atmel/sam9x60ek/sam9x60ek.c | 12
1 file changed, 12 insertions(+)
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c
b/board/atmel/sam9x60ek/sam9x60ek.c
index
Hi Stefan,
On 09/10/19 12:46 PM, Stefan Roese wrote:
> Hi Vignesh,
>
> sorry for the late review.
>
> On 10.09.19 07:10, Vignesh Raghavendra wrote:
>> Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build
>> error when CONFIG_SYS_MONITOR_BASE is not defined.
>>
>>
Hi Tom,
please pull the following changes to your tree. I have also included
trivial patch for apalis board. Networking stuff have been assigned to
me in patchwork that's why I am also including them.
Gitlab CI failed but it is related to file path we discussed already.
From: Andreas Färber
Values imported from Linux driver, but in correct numeric order.
Khadas VIM3 prints: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
Cc: Christian Hewitt
Signed-off-by: Andreas Färber
Signed-off-by: Neil Armstrong
---
arch/arm/mach-meson/board-info.c | 1 +
1 file
Hi Andreas,
This is a resend from v2 with first patch resync'ed on v5.4-rc2.
This mini-series adds initial support for Amlogic A311D based Khadas VIM3.
v2 fixes an oversight and adds some cleanups.
v2 -> v3:
* Resync patch 1 on v5.4-rc2
* Removed bad signeoff of Julien Masson in patch 3
v1 ->
From: Andreas Färber
Write SoC instead of Soc. The Linux driver is not affected.
Fixes: f41d723b9f ("ARM: meson: display Amlogic SoC Information")
Signed-off-by: Andreas Färber
Signed-off-by: Neil Armstrong
---
arch/arm/mach-meson/board-info.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Andreas Färber
Derived from odroid-n2_defconfig and README.odroid-n2.
Reviewed-by: Neil Armstrong
Signed-off-by: Andreas Färber
Signed-off-by: Neil Armstrong
---
board/amlogic/w400/MAINTAINERS| 1 +
board/amlogic/w400/README.khadas-vim3 | 132 ++
Hi Eugeniy,
On 07/10/19 8:16 PM, Eugeniy Paltsev wrote:
> Hi Vignesh,
>
> I've tested your "[U-Boot,RFT,v2,0/3] spi-nor: spi-nor-ids: Fix 4 Byte
> addressing " series
> applies on the latest master (879396a2405).
> 'axs103_defconfig' was used without changes.
> > Probe/read/write/erase work for
hi
I am a bit confused about two things
1) is the "ide" (disk read/write/boot) module intended to be PCI-MEM
"memory-mapped" oriented concerning the harddrive? or is it PCI_IO
oriented? there are too many layers of code and this makes me confused
2) what is the philosophy about initializing the
Hi Tudor,
On 01/10/19 2:29 PM, tudor.amba...@microchip.com wrote:
> From: Tudor Ambarus
>
> JESD216 allow vendors to define their own SFDP tables.
>
> Add Microchip SFDP parser. The vendor table is allocated using
> resource-managed kmalloc - the table will be freed on driver detach.
> It will
On Sat, 2019-10-05 at 21:41 +0200, Simon Goldschmidt wrote:
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
> > From: Dalon Westergreen
> > CONFIG_OF_EMBED was primarily enabled to support the stratix10spl hex file
> > requirements. Since this option now produces awarning during build, and
On Sun, Oct 06, 2019 at 11:13:21PM +0200, Heinrich Schuchardt wrote:
> The following changes since commit dac51e9aaf6fd38298007b266feb6a80e9ec91ee:
>
> Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-10-05
> 20:06:58 -0400)
>
> are available in the Git repository at:
>
>
On Tue, Oct 08, 2019 at 04:28:33PM +0800, Bin Meng wrote:
> Hi Tom,
>
> This PR includes the following changes for v2020.01:
>
> - Rename existing FSP code to fsp1
> - Add fsp2 directory in preparation to support FSP 2.0
> - Various x86 platform codes update
> - Various bug fixes and updates in
On Wed, Oct 9, 2019 at 2:56 PM Dalon L Westergreen
wrote:
>
> On Sat, 2019-10-05 at 21:41 +0200, Simon Goldschmidt wrote:
>
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
>
> From: Dalon Westergreen <
>
> dalon.westergr...@intel.com
>
> >
>
>
> CONFIG_OF_EMBED was primarily enabled to
Hi Simon,
On Wed, Sep 25, 2019 at 10:12 PM Simon Glass wrote:
>
> On x86 platforms the SPI flash can be mapped into memory so that the
> contents can be read with normal memory accesses.
>
> Add a new SPI flash method to find the location of the SPI flash in
> memory. This differs from the
Hi Simon,
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> The x86 power unit handles power management. Support initing this device
> which is modelled as a new type of system controller since there are no
> operations needed.
>
> Signed-off-by: Simon Glass
> ---
>
>
Hi Simon,
On Wed, Sep 25, 2019 at 10:12 PM Simon Glass wrote:
>
> At present SPI-flash testing relies on a sandbox driver which emulates the
> SPI bus and implements a flash chip behind that emulated bus.
>
> This provides good coverage but can only implement features supported by
> the SPI bus.
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> At present when these fail to boot there is no message, just a hang. Add a
> panic so it is obvious that something when wrong.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/lib/spl.c | 2 +-
> arch/x86/lib/tpl.c | 2 +-
> 2 files
The SPL is now running at SDRAM, and 0x1 is used by BL31,
and the ARM SPL do not support relocate now, we need reserved
0x5 so that it won't overwrite the code when we load the
bl31 to target space.
We should remove this after we enable the relocate feature.
The SPL need malloc 0x9000 for
On Sat, 2019-10-05 at 21:40 +0200, Simon Goldschmidt wrote:
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
> > From: Dalon Westergreen
> > Stratix10 requires a hex image of the spl plus spl devicetree offset tothe
> > Stratix10 onchip memory located at SPL_TEXT_BASE. This patch addsa target
Hi Simon,
On Wed, Sep 25, 2019 at 10:12 PM Simon Glass wrote:
>
> This provides access to SPI flash both through a read-only memory map and
> with operations to erase and write flash. It supports 4KB or 64KB erase
> sizes.
>
I read the SPI controller chapter in the datasheet of apollolake as
Signed-off-by: liuhao
---
MAINTAINERS | 6 +++
arch/arm/Kconfig | 8
arch/arm/dts/Makefile| 2 +
arch/arm/dts/phytium-ft2004.dts | 33 ++
board/phytium/ft2004/Kconfig | 12 +
board/phytium/ft2004/MAINTAINERS | 8
On Wed, Oct 9, 2019 at 11:08 AM Kever Yang wrote:
>
> We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
> and when we introduce the TPL, the SPL space is in DRAM, we reserve
> space to avoid SPL text overlap with ATF bl31.
>
> Now we decide to move ATF entry point to 0x4
On Tue, Oct 08, 2019 at 12:38:57PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the following watchdog related patches:
>
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Oct 08, 2019 at 06:56:05AM +, eugen.hris...@microchip.com wrote:
> Hello Tom,
>
> Please pull tag u-boot-atmel-2020.01-a , the first set of new features
> for the 2020.01 release
>
> The feature set includes support for two new boards from Microchip AT91:
> The sama5d27_wlsom1_ek
On Wed, Oct 9, 2019 at 2:57 PM Dalon L Westergreen
wrote:
>
> On Sat, 2019-10-05 at 21:40 +0200, Simon Goldschmidt wrote:
>
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
>
> From: Dalon Westergreen <
>
> dalon.westergr...@intel.com
>
> >
>
>
> Stratix10 requires a hex image of the spl plus
From: Zumeng Chen
This patch is to build the coresight topology structure of zynq-7000
series according to the docs of coresight and userguide of zynq-7000.
Signed-off-by: Zumeng Chen
Signed-off-by: Quanyang Wang
Signed-off-by: Michal Simek
---
arch/arm/boot/dts/zynq-7000.dtsi | 158
Build the keystone 3 platforms with the keystone 2 platforms, in order
to get back more room in the "catch-all" build jobs.
Signed-off-by: Tom Rini
---
.travis.yml | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index
As both "catch-all" ARM jobs are nearing their time limit, move all of
the bcm SoC boards into a single job.
Signed-off-by: Tom Rini
---
.travis.yml | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index c48b711659e9..ebe849f9909c 100644
---
On Tue, Oct 8, 2019 at 7:50 PM Peng Fan wrote:
>
> > > +
> > > +Build U-Boot
> > > +
> > > +$ export CROSS_COMPILE=aarch64-poky-linux- $ make
> > > +imx8mm_evk_defconfig $ export ATF_LOAD_ADDR=0x92 $ make
> > flash.bin
> >
> > Build fails due to default_serial_console undefined.
Add rproc_elf_load_rsc_table(), which searches for a resource table in
an elf64/elf32 image, and if found, copies it to device memory.
Add also the elf32 and elf64 variants of this API.
Add a test for this.
Signed-off-by: Fabien Dessenne
---
drivers/remoteproc/rproc-elf-loader.c | 269
Use the backup register #17 as coprocessor resource table address.
Signed-off-by: Fabien Dessenne
---
arch/arm/mach-stm32mp/include/mach/stm32.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h
b/arch/arm/mach-stm32mp/include/mach/stm32.h
index
On Wed, Oct 9, 2019 at 10:23 AM Walter Lozano
wrote:
>
> Hi Adam
>
> On Tuesday, October 08, 2019 15:31 -03, Adam Ford wrote:
>
> > The pfuze100 is the PMIC connected to the I2C bus. Currently,
> > the I2C driver is disabled which prevents the PMIC from operating.
> >
> > This patch enables the
Hi, Vignesh,
On 10/09/2019 03:04 PM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
> Hi Tudor,
>
> On 01/10/19 2:29 PM, tudor.amba...@microchip.com wrote:
>> From: Tudor Ambarus
>>
>> JESD216 allow vendors to define their own SFDP tables.
>>
>> Add Microchip SFDP parser. The vendor table
On 09-Oct-19 9:20 PM, tudor.amba...@microchip.com wrote:
> Hi, Vignesh,
>
> On 10/09/2019 03:04 PM, Vignesh Raghavendra wrote:
>> External E-Mail
>>
>>
>> Hi Tudor,
>>
>> On 01/10/19 2:29 PM, tudor.amba...@microchip.com wrote:
>>> From: Tudor Ambarus
>>>
>>> JESD216 allow vendors to define
Hi,
On 02/10/19 15:39, Michal Simek wrote:
> From: Ibai Erkiaga
>
> zynqmp-power driver for ZynqMP to handle the communication with the PMU
> firmware. Firmware driver just probes subnodes and power driver handles
> communication with PMU using the IPI mailbox driver.
>
> Signed-off-by: Ibai
Hi Ibai, Michal,
I had half-written a review of this patch and patch 4. Unfortunately I
didn't finish them before they got applied. I'll send them now anyway,
they are mostly nitpicking but you might consider them for a future
improvement. Sorry for the inconvenience.
On 02/10/19 15:39, Michal
Hi Fabio and Stefano,
On 9/29/19 9:40 PM, Fabio Estevam wrote:
We try to use DM in U-Boot proper as much as possible, but using DM in
SPL is currently not a requirement, especially due to internal RAM
size constraints.
IOMUXC and LPUART(using 24Mhz clock) work correctly using DM.
About clk
Hi Giulio,
On Wed, Oct 9, 2019 at 12:59 PM Giulio Benetti
wrote:
>
> Hi Fabio and Stefano,
>
> On 9/29/19 9:40 PM, Fabio Estevam wrote:
> > We try to use DM in U-Boot proper as much as possible, but using DM in
> > SPL is currently not a requirement, especially due to internal RAM
> > size
Hi, Vignesh,
On 10/01/2019 11:59 AM, Tudor Ambarus - M18064 wrote:
> @@ -1892,6 +1921,12 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
> dev_info(dev, "non-uniform erase sector maps are not
> supported yet.\n");
> break;
>
> +
Hi Simon,
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> In TPL we try to minimise code size so do not include the PCI subsystem.
> We can use fixed BARs and drivers can directly program the devices that
> they need.
>
> However we do need to bind the devices on the PCI bus and without
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> Add a field to the PCI emulator per-device data which records which device
> is being emulated. This is useful when the emulator needs to check the
> device for something.
>
> Signed-off-by: Simon Glass
> ---
>
>
Hi Anatolij,
Gentle ping, did you have time to review this patchset ?
Thanks,
Neil
On 30/08/2019 14:09, Neil Armstrong wrote:
> Synchronize the Amlogic Meson Video driver back with the latest
> DRM misc tree, adding G12A platform support, from the latest commit:
> 528a25d040bc ("drm: meson: use
Add some helpers that can be called by the drivers to load the firmware
resource table from an elf32 / elf64 image.
The stm32 remoteproc driver makes use of it, to load the resource table before
the elf image itself.
This series applies on top of the "remoteproc: Add support for R5F and DSP
When the coprocessor has been started, provide the context to Linux
kernel so it can handle it:
- update the coprocessor node of kernel DeviceTree with the
"early-booted" property.
- write the resource table address in a dedicated backup register.
Signed-off-by: Fabien Dessenne
---
Load the optional resource table from the firmware, and write its
address in the dedicated backup register.
Signed-off-by: Fabien Dessenne
---
drivers/remoteproc/stm32_copro.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/remoteproc/stm32_copro.c
The .is_running() ops expects a return value of 0 if the processor is
running, 1 if not running : align to this.
Signed-off-by: Fabien Dessenne
---
drivers/remoteproc/stm32_copro.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/remoteproc/stm32_copro.c
On Tue, Oct 08, 2019 at 10:48:39AM +0200, Michal Simek wrote:
> Hi Tom,
>
> On 19. 09. 19 15:28, Michal Simek wrote:
> > On 13. 09. 19 17:09, Tom Rini wrote:
> >> On Wed, Sep 11, 2019 at 03:39:53PM +0200, Michal Simek wrote:
> >>
> >>> From: T Karthik Reddy
> >>>
> >>> This patch uses auto
On 10/09/2019 07:25 PM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
>
> On 09-Oct-19 9:20 PM, tudor.amba...@microchip.com wrote:
>> Hi, Vignesh,
>>
>> On 10/09/2019 03:04 PM, Vignesh Raghavendra wrote:
>>> External E-Mail
>>>
>>>
>>> Hi Tudor,
>>>
>>> On 01/10/19 2:29 PM,
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