The revision is different for these, add the additional check as in
xhci-dwc3 core_init code.
Signed-off-by: Caleb Connolly
---
drivers/usb/dwc3/core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index
If a button device fails to probe, it will still be added to the uclass
device list, and therefore will still be iterated over in
button_read_keys() resulting in a UAF on the buttons private data.
Resolve this by unbinding button devices that aren't active after
probing, and print a warning so
On 4/11/24 04:37, Heinrich Schuchardt wrote:
On 11.04.24 05:13, Sean Anderson wrote:
On 2/16/24 11:35, Heinrich Schuchardt wrote:
If multiple messages are written, line-feeds improve the readability.
Fixes: c40b6df87fc0 ("clk: Add SiFive FU540 PRCI clock driver")
Signed-off-by: Heinrich
On Thu, 04 Jan 2024 08:10:35 -0700, Simon Glass wrote:
> This little series reprises the EFI-video fix, fixes a USB problem and
> enables a boot script for coreboot.
>
> It also moves to truetype fonts for coreboot and qemu-x86, since the
> menus look much better and there are no strong size
On Thu, Jan 04, 2024 at 08:11:33AM -0700, Simon Glass wrote:
> U-Boot provides support for editing settings with an 'expo', as well as
> reading and writing settings to CMOS RAM.
>
> This series integrates expo functionality with coreboot, using the
> sysinfo table to get a list of settings,
On Wed, 10 Apr 2024 at 14:29, Heinrich Schuchardt wrote:
>
> On 10.04.24 14:19, Weizhao Ouyang wrote:
> > Improve error message for UEFI SCT tests.
> >
> > Signed-off-by: Weizhao Ouyang
> > ---
> > lib/efi_loader/efi_variable.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git
NFIG_BAUDRATE);
>
> - err = fdt_setprop(fdt, chosenoff, "linux,stdout-path", tmp, len);
> + err = fdt_setprop(fdt, chosenoff, "linux,stdout-path", tmp, len + 1);
> if (err < 0)
> printf("WARNING: could not set linux,stdout-p
Hi
I will review tomorrow, I need have a time window to test even on my board
Mihcael
On Thu, Apr 11, 2024 at 6:09 PM Alexey Romanov
wrote:
>
> Hello! Ping.
>
> On Thu, Apr 04, 2024 at 01:58:10PM +0300, Alexey Romanov wrote:
> > Hello!
> >
> > This series adds support for the mtdblock device,
The README.trace has been moved and converted to rst in commit dce26c7d56ed
("doc: move README.trace to HTML documentation"); fix all the remaining
references to this file.
Signed-off-by: Vincent Stehlé
Cc: Tom Rini
Cc: Simon Glass
Cc: Heinrich Schuchardt
---
cmd/Kconfig |
On Tue, 9 Apr 2024 at 23:33, Caleb Connolly wrote:
>
> The V4 and V5 controllers have quite varied register layouts. Inherit
> the register offsets and naming from the Linux driver. More version
> specific offsets can be inherited from Linux as needed.
>
> Fixes: 364c22a ("mmc: msm_sdhci: Add
On Tue, 9 Apr 2024 at 20:05, Heinrich Schuchardt
wrote:
>
> The month is stored in 5 - 8. We need to shift it by 5 bits.
>
> Cf. Microsoft FAT Specification, 2005-08-30
>
> Fixes: 13c11c665320 ("fs: fat: add file attributes to struct fs_dirent")
> Signed-off-by: Heinrich Schuchardt
> ---
>
On Wed, Apr 03, 2024 at 06:18:01PM +0530, Chintan Vankar wrote:
>
>
> On 22/01/24 10:11, Siddharth Vadapalli wrote:
> >
> >
> > On 20/01/24 22:11, Tom Rini wrote:
> > > On Mon, Jan 15, 2024 at 01:42:51PM +0530, Siddharth Vadapalli wrote:
> > > > Hello Tom,
> > > >
> > > > On 12/01/24 18:56,
From: Ian Roberts
Implement the spi-mem calibration hook for high speed flash operation for
use on the SC59x SOCs. The Cadence controller IP has support for the DQS
signal and a PHY mode that facilitates speeds greater than 50MHz.
At high speeds, the IO lines must be calibrated for signal
From: Ian Roberts
On the SC59x platform, the Cadence SPI IP block can use memory DMA
channels to execute transactions. Existing Cadence DMA support attempts
appears to be SOC specific and not generic. Thus, framework to use the
DMA subsystem was added. On the SC59x, DMA to the Cadence SPI block
From: Ian Roberts
On some SOCs (eg sc59x), attempting to use too high of a Read
Delay Capture value can cause the controller DMA to lock up. Thus,
add a device tree configuration property to allow controlling
the max Read Delay Capture value.
Co-developed-by: Nathan Barrett-Morrison
From: Ian Roberts
cadence_spi_mem_supports_op() already checks that every memory operation
either has all DTR booleans set or cleared. Thus, there is no need to
store a cached dtr value. The command DTR state can be used since it is
not optional like the other fields.
Co-developed-by: Nathan
From: Ian Roberts
In addition to the given reason for the conditional disable
of this feature for DTR:
Theoretically, some flashes have their WIP bit in different
bit positions or have a different bit polarity. spi-nor
currently does not have an interface in place to dictate
this information to
From: Ian Roberts
It is not possible to configure the Cadence SPI IP block to use a zero
length address in DMA read or write commands.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
From: Nathan Barrett-Morrison
This adds support for the SC5XX clock trees which are required for reading
clock speeds on the SoCs. This is largely a port of the same support for
Linux, which has not yet been submitted upstream.
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
From: Nathan Barrett-Morrison
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Nathan Barrett-Morrison
---
Hello! Ping.
On Thu, Apr 04, 2024 at 01:58:10PM +0300, Alexey Romanov wrote:
> Hello!
>
> This series adds support for the mtdblock device, which
> allows to read/write data block by block. For example,
> it can now be used for BCB or Android AB command:
>
> $ bcb load mtd 0 part_name
>
>
Mattijs Korpershoek writes:
> Hi Jonathan,
>
> Thank you for the patch.
>
> On lun., avril 08, 2024 at 17:31, Jonathan Humphreys
> wrote:
>
>> Signed-off-by: Jonathan Humphreys
>
> Please consider adding a commit message body.
Got it. thanks.
BTW, the next version of this series will drop
This series introduces support for DTR mode for the Cadence QSPI/OSPI
IP. We have been developing it against the SC594/SC598 from ADI, so
there are some limitations specific to our hardware's capabilities.
Ideally this series could be enhanced with features introduced in a
patch series submitted
On Wed, Apr 03, 2024 at 10:00:09PM -0500, Adam Ford wrote:
> The da850-evm can remove the U-Boot device trees if migrated
> to OF_UPSTREAM. This means pointing the device trees to the
> ti/davinci directory.
>
> Signed-off-by: Adam Ford
This series leads to failure to build for omapl138_lcdk
asm/spl.h | 1 +
> arch/sandbox/include/asm/spl.h| 1 +
> common/spl/Kconfig| 21 ++
> common/spl/spl_ubi.c | 49 -
> include/nand.h| 3 +
> 11 files changed, 354 insertions(+), 107 deletions(-)
> ---
> base-commit: 777c28460947371ada40868dc994dfe8537d7115
> change-id: 20240411-spinand-eb7d8319813b
>
> Best regards,
> --
> John Watts
>
On Thu, Apr 11, 2024 at 03:53:51PM -0600, Sam Edwards wrote:
> Hi John,
Hi Sam,
> Ahh I see the problem. In U-Boot, `ubi` isn't actually a block device:
> it's implemented as a stub in the block layer, and the filesystem
> layer redirects `ubi` accesses to the currently-mounted ubifs instead.
>
On Thu, Apr 11, 2024 at 07:37:27PM -0400, Greg Malysa wrote:
>
> This series adds support for the ADI SC5xx machine type and includes two
> core drivers that are required for being able to boot any board--a UART
> driver and the clock tree driver. Our corresponding Linux support relies
> on
On Thu, Apr 11, 2024 at 07:37:28PM -0400, Greg Malysa wrote:
> From: Nathan Barrett-Morrison
>
> Add support for the SC5xx machine type from Analog Devices. This
> includes support for the SC57x, SC58x, SC59x, and SC59x-64 SoCs, which
> have many common features such as common ADI IP blocks,
On Thu, Apr 11, 2024 at 1:40 AM John Watts wrote:
>
> On Thu, Apr 11, 2024 at 12:52:14AM -0600, Sam Edwards wrote:
> > Hi John,
> >
> > This patch was developed against (and used very heavily on) the Turing
> > Pi 2, which has an Allwinner T113-s3 SoC. Likely it should work for
> > any T113/D1
On Thu, Apr 11, 2024 at 05:27:08PM -0600, Sam Edwards wrote:
> Hi John,
>
> It doesn't look like I was sent the whole series (only 00 and 01), but
> I was able to find it on Patchwork and sift through it. A few general
> comments follow:
>
> The introduction of `SUNXI_BOOTED_FROM_SPINAND` is the
On Thu, Apr 11, 2024 at 01:37:38PM +0100, Andre Przywara wrote:
> Hi John,
>
> > The T113 supports UART1 and UART2 on PG and PD pins respectively.
> > Add support for these in U-Boot so we can use them.
>
> So those bits are just for the *debug* UARTs. Traditionally this is UART0,
> with some
On Thu, Apr 11, 2024 at 05:11:46PM +0200, Mark Kettenis wrote:
> You probably should fix this by making sure the device tree you're
> using has the appropriate stdout-path node. Because I think the
> functionality you're trying to use here is deprecated:
Hi Mark,
Interesting, I'll go with that
From: Ian Roberts
High speed SPI flash chip operation, such as speeds greater than 50MHz,
require a calibration of the data lines to determine the correct signal
propagation delay. This calibration delay will vary based on flash chip,
operating frequency, board trace length, and board
From: Ian Roberts
ISSI IS25*x series SPIflash chips are capable of Octal IO and DDR.
Add spi-nor support to enable and operate in these modes.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
From: Ian Roberts
The Cadence octal SPI IP read instruction register requires a bit to be
set to indicate if the read opcode is a compliant DDR read command.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
From: Ian Roberts
Some flash chips use dual opcodes in other modes. For example, the
Macronix MX66 requires dual opcodes for STR octal operation. Thus,
enable opcode extension based on the length of the command instead
of the DTR mode of the controller.
Co-developed-by: Nathan Barrett-Morrison
From: Ian Roberts
The spi-nor subsystem issues the write enable command manually. So
this automatic feature sends duplicate commands and also introduces
the possibility of erroneous writes.
Disable the automatic write enable feature by default.
Co-developed-by: Nathan Barrett-Morrison
From: Nathan Barrett-Morrison
Add support for the SC5xx machine type from Analog Devices. This
includes support for the SC57x, SC58x, SC59x, and SC59x-64 SoCs, which
have many common features such as common ADI IP blocks, and SHARC DSP
cores. This commit introduces core functionality required
This series adds support for the ADI SC5xx machine type and includes two
core drivers that are required for being able to boot any board--a UART
driver and the clock tree driver. Our corresponding Linux support relies
on u-boot configuring the clocks correctly before booting, so it is not
On Tue, 26 Mar 2024 23:13:11 +0100, Marek Vasut wrote:
> Change type of ulong env_get_bootm_low() to phys_addr_t env_get_bootm_low().
> The PPC/LS systems already treat env_get_bootm_low() result as phys_addr_t,
> while the function itself still returns ulong. This is potentially dangerous
> on
On Thu, Apr 11, 2024 at 1:29 AM Florian Klink wrote:
>
> On 23-12-14 18:46:47, Joshua Riek wrote:
> >The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines.
> >
> >Specifications:
> >
> >Rockchip RK3588 SoC
> >4x ARM Cortex-A76, 4x ARM Cortex-A55
> >8/16/32GB memory
Hey Sam,
On 24-04-11 16:35:57, Sam Edwards wrote:
On Thu, Apr 11, 2024 at 1:29 AM Florian Klink wrote:
On 23-12-14 18:46:47, Joshua Riek wrote:
>The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines.
>
>Specifications:
>
>Rockchip RK3588 SoC
>4x ARM Cortex-A76, 4x ARM
On Tue, 19 Mar 2024 13:43:43 -0500, Judith Mendez wrote:
> Enable MMC_SPEED_MODE_SET config option in defconfig to enable
> mmc rescan for various Sitara devices.
>
>
Applied to u-boot/master, thanks!
--
Tom
On Wed, 20 Mar 2024 09:16:30 -0300, Joao Paulo Goncalves wrote:
> From: Joao Paulo Goncalves
>
> This series introduces a method to dynamically set the AM62 A53 CPU frequency
> based on its speed grade. It adds a new function to retrieve the A53 frequency
> value by reading the speed grade from
On Tue, 26 Mar 2024 13:37:06 +0530, Manorit Chawdhry wrote:
> To debug using jtag, ROM needs to unlock jtag debugging on HS devices
> and it does that looking at this debug extension.
>
> Add the debug extension and enable it by default.
>
>
Applied to u-boot/master, thanks!
--
Tom
On Tue, 26 Mar 2024 14:26:33 +, Martyn Welch wrote:
> With the current config for tha SK-AM62, fdtfile isn't set in the U-Boot
> environment. When using bootflow to boot from a block device, where the
> extlinux.conf file specifies `fdtdir`, a fallback device tree is being
> constructed from
On Thu, 28 Mar 2024 10:05:48 +, Vitor Soares wrote:
> During the boot, the EFI loader maps the memory from ram_top to ram_end
> as EFI_BOOT_SERVICES_DATA. When LMB does boot_fdt_add_mem_rsv_regions()
> to OPTEE, TFA, R5, and M4F DMA/memory "no-map" for the kernel it produces
> the following
On Tue, 26 Mar 2024 10:39:34 +0100, Michael Walle wrote:
> When there is a lint error the user gets the following cryptic message:
>
> binman: Node '/path/to/some/node': Yamllint error: 18: comments
>
> This isn't very helpful. Improve the message to tell the user that the
> number is
On Wed, 03 Apr 2024 16:31:55 +0200, Michael Walle wrote:
> The device name is a concatenation of the device node name of the cpsw
> device and of the device node name of the port. In my case that is
>
> ethernet@800
> port@1
>
> First the buffer is really too small, but more
Hi Michael
On 05/04/24 13:12, Michael Walle wrote:
Hi,
On Thu Apr 4, 2024 at 11:10 AM CEST, Neha Malcom Francis wrote:
But again in the interest of time... this would mean this cleaning up effort be
kept on hold. If we can agree to move to using the generator later as the final
solution, can
Hi Tom,
Thanks for the quick feedback. I'll go through our patches and review
the #include usage as part of preparing for v2, and we'll work out
switching to the plain text environment as well. I'll drop the custom
compiler options and make sure we weren't actually relying on
them--possibly it
I'm afraid I have to admit I don't know. I'll work with our IT team to
make sure we can run CI locally, and when v2 comes around the answer
will be yes.
On Thu, Apr 11, 2024 at 7:52 PM Tom Rini wrote:
>
> On Thu, Apr 11, 2024 at 07:37:27PM -0400, Greg Malysa wrote:
> >
> > This series adds
On Sun, Dec 31, 2023 at 03:38:37PM -0500, Aren Moynihan wrote:
> Add support for building the sunxi-musb driver with DM_USB_GADGET
> including adding a separate IRQ handling function and registering the
> driver with the musb system differently.
Hi there,
Were you aware of this similar patch?
Michael Trimarchi
> base-commit: 777c28460947371ada40868dc994dfe8537d7115
> change-id: 20240411-mtd-d2e811e17cc8
>
> Best regards,
> --
> John Watts
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
Hi there,
I've tested this patch and it seems to support the gadget model, but I'm having
a lot of USB errors. What device did you test this on?
John.
On Thu, Jun 08, 2023 at 01:56:29PM -0600, Sam Edwards wrote:
> Happy Thursday, U-Boot list!
>
> Here is attempt 2 at making this USB controller
Boards which have for example MAC address in eeprom but not in Xilinx
format (legacy or FRU) could reference it via nvmem cells.
For example:
{
nvmem-cells = <>;
nvmem-cell-names = "mac-address";
};
{
#address-cells = <1>;
#size-cells = <1>;
mac:
On 11/Apr/2024 Heinrich Schuchardt wrote:
> method_flags may be passed uninitialized to bootflow_iter_set_dev()
> if dev is not NULL.
>
> Always initialize method_flags.
>
> Addresses-Coverity-ID: 467057 Uninitialized scalar variable
> Signed-off-by: Heinrich Schuchardt
Reviewed-by: Nam Cao
On 10/04/2024 19:52, Caleb Connolly wrote:
Introduce pinctrl drivers for three new SoCs and enable them.
Signed-off-by: Caleb Connolly
---
Changes in v2:
- Fix a few formatting issues
- Link to v1:
https://lore.kernel.org/r/20240408-b4-qcom-rbx-soc-v1-0-900db37b8...@linaro.org
---
Caleb
Hi Maxim,
On 4/10/24 23:21, Maxim Moskalets wrote:
From: Maxim Moskalets
Some operating systems (e.g. seL4) and embedded applications are ELF
images. It is convenient to use FIT-images to implement trusted boot.
Added "elf" image type for booting using bootm command.
Signed-off-by: Maxim
From: Maxim Moskalets
Some operating systems (e.g. seL4) and embedded applications are ELF
images. It is convenient to use FIT-images to implement trusted boot.
Added "elf" image type for booting using bootm command.
Signed-off-by: Maxim Moskalets
---
boot/bootm_os.c | 24
From: Maxim Moskalets
Some operating systems (e.g. seL4) and embedded applications are ELF
images. It is convenient to use FIT-images to implement trusted boot.
Added "elf" image type for booting using bootm command.
Signed-off-by: Maxim Moskalets
---
boot/bootm_os.c | 24
On 11.04.24 05:13, Sean Anderson wrote:
On 2/16/24 11:35, Heinrich Schuchardt wrote:
If multiple messages are written, line-feeds improve the readability.
Fixes: c40b6df87fc0 ("clk: Add SiFive FU540 PRCI clock driver")
Signed-off-by: Heinrich Schuchardt
---
From: Maxim Moskalets
Some operating systems (e.g. seL4) and embedded applications are ELF
images. It is convenient to use FIT-images to implement trusted boot.
Added "elf" image type for booting using bootm command.
Signed-off-by: Maxim Moskalets
---
boot/bootm_os.c | 23
On 23-12-14 18:46:47, Joshua Riek wrote:
The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines.
Specifications:
Rockchip RK3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
8/16/32GB memory LPDDR4x
Mali G610MC4 GPU
32GB eMMC HS400
2x USB 2.0, 2x USB 3.0
2x MIPI
Hi Jonathan,
Thank you for the patch.
On lun., avril 08, 2024 at 17:31, Jonathan Humphreys wrote:
> Signed-off-by: Jonathan Humphreys
Please consider adding a commit message body.
On the TI vendor tree, there is a similar patch with a commit message:
On Thu, 11 Apr 2024 at 00:50, Heinrich Schuchardt
wrote:
>
> The length of the variable name typically is not 1.
> Neither the length of the variable name nor the size of the appended
> data is known in the include.
>
> * Define the size of element variable_name as variable.
> * Remove the
Hi Maxim,
On 4/11/24 10:32, Maxim Moskalets wrote:
From: Maxim Moskalets
Some operating systems (e.g. seL4) and embedded applications are ELF
images. It is convenient to use FIT-images to implement trusted boot.
Added "elf" image type for booting using bootm command.
Signed-off-by: Maxim
On 11.04.24 10:57, Maxim Moskalets wrote:
From: Maxim Moskalets
Some operating systems (e.g. seL4) and embedded applications are ELF
images. It is convenient to use FIT-images to implement trusted boot.
Added "elf" image type for booting using bootm command.
Signed-off-by: Maxim Moskalets
The instruction and data cache line sizes of Andes core
are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so
the SYS_CACHELINE_SIZE is enabled with a default value.
Signed-off-by: Yu Chien Peter Lin
---
arch/riscv/cpu/andesv5/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
Qcom SoCs derived boards can come from various OEMs/ODMs and not just
Qcom itself. So allow CONFIG_SYS_VENDOR to be set correctly
corressponding to the actual board vendor.
Suggested-by: Stephan Gerhold
Signed-off-by: Sumit Garg
---
arch/arm/mach-snapdragon/Kconfig | 15 +--
On Wed, 10 Apr 2024 at 21:31, Neil Armstrong wrote:
>
> Add support for the new Qualcomm Synopsys eUSB2 PHY found in the
> SM8550 and SM8650 SoCs.
>
> Finally enable the driver in the Qualcomm defconfig.
>
> Signed-off-by: Neil Armstrong
> ---
> Changes in v2:
> - fixed driver build failure due
On Wed, 10 Apr 2024 at 23:23, Caleb Connolly wrote:
>
> Introduce pinctrl drivers for three new SoCs and enable them.
>
> Signed-off-by: Caleb Connolly
> ---
> Changes in v2:
> - Fix a few formatting issues
> - Link to v1:
>
Hi Sumit,
On 11/04/2024 13:51, Sumit Garg wrote:
Qcom SoCs derived boards can come from various OEMs/ODMs and not just
Qcom itself. So allow CONFIG_SYS_VENDOR to be set correctly
corressponding to the actual board vendor.
Suggested-by: Stephan Gerhold
Signed-off-by: Sumit Garg
---
Qcom SoCs derived boards can come from various OEMs/ODMs and not just
Qcom itself. So allow CONFIG_SYS_VENDOR to be set correctly
corressponding to the actual board vendor.
Suggested-by: Stephan Gerhold
Reviewed-by: Caleb Connolly
Signed-off-by: Sumit Garg
---
Changes in v2:
- Retained
t; 2 files changed, 8 insertions(+), 2 deletions(-)
> ---
> base-commit: 777c28460947371ada40868dc994dfe8537d7115
> change-id: 20240411-t113serial-a6e9ca8d8848
>
> Best regards,
On 05/04/2024 10:21, Neil Armstrong wrote:
First, fix version 5 support by using the right ch_offset in
then msm_spmi_write() reg accesses.
Then:
- properly format command by importing helpers from Linux driver and
use a switch/case to handle all versions in msm_spmi_write/read() command.
On Fri, 05 Apr 2024 10:15:09 +0200, Neil Armstrong wrote:
> Add pinctrl driver for the TLMM block found in the SM8550 & SM8650 SoCs.
>
> This driver only handles the gpio and qup debug uart pinmux, and makes sure
> the pinconf applies on SDC2 pins.
>
> Finally enable both drivers in the
On Wed, 10 Apr 2024 18:01:11 +0200, Neil Armstrong wrote:
> Add support for the new Qualcomm Synopsys eUSB2 PHY found in the
> SM8550 and SM8650 SoCs.
>
> Finally enable the driver in the Qualcomm defconfig.
>
>
Applied, thanks!
[1/2] phy: qcom: add Synopsys eUSB2 PHY driver
commit:
On Tue, 09 Apr 2024 20:02:59 +0200, Caleb Connolly wrote:
> This series does some long overdue cleanup to the msm_sdhci driver,
> fixes v5 support, and adds the necessary clock configuration to get the
> sdcard up and running on the RB3.
>
Applied, thanks!
[1/7] mmc: msm_sdhci: correct
On Thu, 11 Apr 2024 18:07:26 +0530, Sumit Garg wrote:
> Qcom SoCs derived boards can come from various OEMs/ODMs and not just
> Qcom itself. So allow CONFIG_SYS_VENDOR to be set correctly
> corressponding to the actual board vendor.
>
>
Applied, thanks!
[1/1] mach-snapdragon: Allow other
On Tue, 09 Apr 2024 17:02:51 +0200, Caleb Connolly wrote:
> Add the newly created u-boot-qcom mailing list to keep track of Qualcomm
> patches.
>
> Additionally, link to the U-Boot Snapdragon custodian tree.
>
>
Applied, thanks!
[1/1] MAINTAINERS: add Qualcomm mailing list
commit:
On Mon, 08 Apr 2024 15:06:48 +0200, Caleb Connolly wrote:
> Introduce clock drivers for three new SoCs and enable them. This allows
> for configuring UART and USB on all three as well as controlling
> relevant resets and power domains.
>
>
Applied, thanks!
[1/4] clk/qcom: add driver for
On Wed, 10 Apr 2024 17:59:42 +0200, Neil Armstrong wrote:
> First add PMIC gpio variant on pm8550-gpio, then rework the
> qcom-pmic button driver to support data structs for each PMIC
> variant and finally add the data for the pmk8350 button configs.
>
>
Applied, thanks!
[1/3] gpio:
On Thu, 11 Apr 2024 14:31:02 +1000
John Watts wrote:
Hi,
> Hi there,
>
> I've been using my own independent implementation of this patch but
> today I gave this one a test in my tree and found out it works.
>
> The code looks fine in comparison, so here's a Tested-by and a
> Reviewed-by.
>
>
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