Re: [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus

2017-03-25 Thread york sun
On 02/23/2017 02:27 AM, Ashish Kumar wrote: > CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which > provides full cache coherency between two clusters of multi-core > CPUs and I/O coherency for devices and I/O masters. > > This patch add new CONFIG defination and move existing register

Re: [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus

2017-03-25 Thread york sun
On 02/23/2017 02:27 AM, Ashish Kumar wrote: > CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which > provides full cache coherency between two clusters of multi-core > CPUs and I/O coherency for devices and I/O masters. > > This patch add new CONFIG defination and move existing register