Re: [U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support
I don't know the protocol for revisiting broken patches that have already been integrated, but the patched offered by NXP for their ls1046a RDB is wrong. original patch: http://lists.denx.de/pipermail/u-boot/2016-September/265974.html The main error is this patch defines CONFIG_SPI_FLASH_BAR which enables use of a bank address register to access flash addresses beyond 16M. +/* QSPI device */ +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 26) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SPI_FLASH_BAR +#endif However the Cypress S25FS512S part used on the LS1046A RDB does not implement any bank address related commands. See section 1.2.2.9 of http://www.cypress.com/file/216376/download This configuration error means that any attempt to access beyond the first 16MB of flash will silently wrap around to the beginning of the flash. This is in addition to the bugs in flash erase on this platform previously noted - http://lists.denx.de/pipermail/u-boot/2016-December/276032.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support
> -Original Message-
> From: york sun
> Sent: Saturday, September 17, 2016 4:14 AM
> To: Q.Y. Gong ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Mingkai Hu
> ; S.H. Xie ; Z.Q. Hou
> ; Wenbin Song ;
> Shengzhou Liu
> Subject: Re: [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board
> support
>
> On 09/07/2016 03:08 AM, Gong Qianyu wrote:
> > From: Mingkai Hu
> >
> > LS1046ARDB Specification:
> > -
> > Memory subsystem:
> > * 8GByte DDR4 SDRAM (64bit bus)
> > * 512 Mbyte NAND flash
> > * Two 64 Mbyte high-speed SPI flash
> > * SD connector to interface with the SD memory card
> > * On-board 4G eMMC
> >
> > Ethernet:
> > * Two XFI 10G ports
> > * Two SGMII ports
> > * Two RGMII ports
> >
> > PCIe:
> > * PCIe1 (SerDes2 Lane0) to miniPCIe slot
> > * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
> > * PCIe3 (SerDes2 Lane2) to x4 PCIe slot
>
> Why don't you enable PCIe in the config file?
>
A follow up patch will enable PCIe support which will use the SVR to
differentiate some memory map differences
for different silicon.
>
> > diff --git a/board/freescale/ls1046ardb/ddr.c
> > b/board/freescale/ls1046ardb/ddr.c
> > new file mode 100644
> > index 000..a9b7dbd
> > --- /dev/null
> > +++ b/board/freescale/ls1046ardb/ddr.c
> > @@ -0,0 +1,140 @@
> > +/*
> > + * Copyright 2016 Freescale Semiconductor, Inc.
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include "ddr.h"
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +#include
> > +#endif
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +void fsl_ddr_board_options(memctl_options_t *popts,
> > + dimm_params_t *pdimm,
> > + unsigned int ctrl_num)
> > +{
> > + const struct board_specific_parameters *pbsp, *pbsp_highest =
> NULL;
> > + ulong ddr_freq;
> > +
> > + if (ctrl_num > 1) {
> > + printf("Not supported controller number %d\n", ctrl_num);
> > + return;
> > + }
> > + if (!pdimm->n_ranks)
> > + return;
> > +
> > + pbsp = udimms[0];
> > +
> > + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
> > +* freqency and n_banks specified in board_specific_parameters
> table.
> > +*/
> > + ddr_freq = get_ddr_freq(0) / 100;
> > + while (pbsp->datarate_mhz_high) {
> > + if (pbsp->n_ranks == pdimm->n_ranks) {
> > + if (ddr_freq <= pbsp->datarate_mhz_high) {
> > + popts->clk_adjust = pbsp->clk_adjust;
> > + popts->wrlvl_start = pbsp->wrlvl_start;
> > + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> > + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> > + goto found;
> > + }
> > + pbsp_highest = pbsp;
> > + }
> > + pbsp++;
> > + }
> > +
> > + if (pbsp_highest) {
> > + printf("Error: board specific timing not found for %lu MT/s\n",
> > + ddr_freq);
> > + printf("Trying to use the highest speed (%u) parameters\n",
> > + pbsp_highest->datarate_mhz_high);
> > + popts->clk_adjust = pbsp_highest->clk_adjust;
> > + popts->wrlvl_start = pbsp_highest->wrlvl_start;
> > + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> > + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> > + } else {
> > + panic("DIMM is not supported by this board");
> > + }
> > +found:
> > + debug("Found timing match: n_ranks %d, data rate %d,
> rank_gb %d\n",
> > + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
> > +
> > + popts->data_bus_width = 0; /* 64-bit data bus */
> > + popts->otf_burst_chop_en = 0;
> > + popts->burst_length = DDR_BL8;
>
> You don't need to set these options unless you specifically want to disable on
> the fly burst chop. Do you?
>
No, will remove it.
Thanks,
Mingkai
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support
Hi York,
PCIe couldn't work on ls1046a as the driver code is not updated yet.
So I removed the configs from board files. And Minghuan has been
working on the PCIe driver patch.
Hi Mingkai and Shengzhou,
Could you please help on the DDR option question? Thanks.
Regards,
Qianyu
> -Original Message-
> From: york sun
> Sent: Saturday, September 17, 2016 4:14 AM
> To: Q.Y. Gong ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Mingkai Hu
> ; S.H. Xie ; Z.Q. Hou
> ; Wenbin Song ; Shengzhou Liu
>
> Subject: Re: [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support
>
> On 09/07/2016 03:08 AM, Gong Qianyu wrote:
> > From: Mingkai Hu
> >
> > LS1046ARDB Specification:
> > -
> > Memory subsystem:
> > * 8GByte DDR4 SDRAM (64bit bus)
> > * 512 Mbyte NAND flash
> > * Two 64 Mbyte high-speed SPI flash
> > * SD connector to interface with the SD memory card
> > * On-board 4G eMMC
> >
> > Ethernet:
> > * Two XFI 10G ports
> > * Two SGMII ports
> > * Two RGMII ports
> >
> > PCIe:
> > * PCIe1 (SerDes2 Lane0) to miniPCIe slot
> > * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
> > * PCIe3 (SerDes2 Lane2) to x4 PCIe slot
>
> Why don't you enable PCIe in the config file?
>
>
>
> > diff --git a/board/freescale/ls1046ardb/ddr.c
> > b/board/freescale/ls1046ardb/ddr.c
> > new file mode 100644
> > index 000..a9b7dbd
> > --- /dev/null
> > +++ b/board/freescale/ls1046ardb/ddr.c
> > @@ -0,0 +1,140 @@
> > +/*
> > + * Copyright 2016 Freescale Semiconductor, Inc.
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include "ddr.h"
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +#include
> > +#endif
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +void fsl_ddr_board_options(memctl_options_t *popts,
> > + dimm_params_t *pdimm,
> > + unsigned int ctrl_num)
> > +{
> > + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
> > + ulong ddr_freq;
> > +
> > + if (ctrl_num > 1) {
> > + printf("Not supported controller number %d\n", ctrl_num);
> > + return;
> > + }
> > + if (!pdimm->n_ranks)
> > + return;
> > +
> > + pbsp = udimms[0];
> > +
> > + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
> > +* freqency and n_banks specified in board_specific_parameters table.
> > +*/
> > + ddr_freq = get_ddr_freq(0) / 100;
> > + while (pbsp->datarate_mhz_high) {
> > + if (pbsp->n_ranks == pdimm->n_ranks) {
> > + if (ddr_freq <= pbsp->datarate_mhz_high) {
> > + popts->clk_adjust = pbsp->clk_adjust;
> > + popts->wrlvl_start = pbsp->wrlvl_start;
> > + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> > + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> > + goto found;
> > + }
> > + pbsp_highest = pbsp;
> > + }
> > + pbsp++;
> > + }
> > +
> > + if (pbsp_highest) {
> > + printf("Error: board specific timing not found for %lu MT/s\n",
> > + ddr_freq);
> > + printf("Trying to use the highest speed (%u) parameters\n",
> > + pbsp_highest->datarate_mhz_high);
> > + popts->clk_adjust = pbsp_highest->clk_adjust;
> > + popts->wrlvl_start = pbsp_highest->wrlvl_start;
> > + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> > + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> > + } else {
> > + panic("DIMM is not supported by this board");
> > + }
> > +found:
> > + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
> > + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
> > +
> > + popts->data_bus_width = 0; /* 64-bit data bus */
> > + popts->otf_burst_chop_en = 0;
> > + popts->burst_length = DDR_BL8;
>
> You don't need to set these options unless you specifically want to disable
> on the
> fly burst chop. Do you?
>
> York
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support
On 09/21/2016 12:46 AM, Mingkai Hu wrote: > > >> -Original Message- >> From: york sun >> Sent: Saturday, September 17, 2016 4:14 AM >> To: Q.Y. Gong ; u-boot@lists.denx.de >> Cc: Prabhakar Kushwaha ; Mingkai Hu >> ; S.H. Xie ; Z.Q. Hou >> ; Wenbin Song ; >> Shengzhou Liu >> Subject: Re: [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board >> support >> >> On 09/07/2016 03:08 AM, Gong Qianyu wrote: >>> From: Mingkai Hu >>> >>> LS1046ARDB Specification: >>> - >>> Memory subsystem: >>> * 8GByte DDR4 SDRAM (64bit bus) >>> * 512 Mbyte NAND flash >>> * Two 64 Mbyte high-speed SPI flash >>> * SD connector to interface with the SD memory card >>> * On-board 4G eMMC >>> >>> Ethernet: >>> * Two XFI 10G ports >>> * Two SGMII ports >>> * Two RGMII ports >>> >>> PCIe: >>> * PCIe1 (SerDes2 Lane0) to miniPCIe slot >>> * PCIe2 (SerDes2 Lane1) to x2 PCIe slot >>> * PCIe3 (SerDes2 Lane2) to x4 PCIe slot >> >> Why don't you enable PCIe in the config file? >> > > A follow up patch will enable PCIe support which will use the SVR to > differentiate some memory map differences > for different silicon. OK. Thanks. Please note, even I accepted this patch set, it has not been merged due to some upstream changes (specifically ad-hoc config ban). I am working to get them merged. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support
On 09/07/2016 03:08 AM, Gong Qianyu wrote:
> From: Mingkai Hu
>
> LS1046ARDB Specification:
> -
> Memory subsystem:
> * 8GByte DDR4 SDRAM (64bit bus)
> * 512 Mbyte NAND flash
> * Two 64 Mbyte high-speed SPI flash
> * SD connector to interface with the SD memory card
> * On-board 4G eMMC
>
> Ethernet:
> * Two XFI 10G ports
> * Two SGMII ports
> * Two RGMII ports
>
> PCIe:
> * PCIe1 (SerDes2 Lane0) to miniPCIe slot
> * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
> * PCIe3 (SerDes2 Lane2) to x4 PCIe slot
Why don't you enable PCIe in the config file?
> diff --git a/board/freescale/ls1046ardb/ddr.c
> b/board/freescale/ls1046ardb/ddr.c
> new file mode 100644
> index 000..a9b7dbd
> --- /dev/null
> +++ b/board/freescale/ls1046ardb/ddr.c
> @@ -0,0 +1,140 @@
> +/*
> + * Copyright 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include "ddr.h"
> +#ifdef CONFIG_FSL_DEEP_SLEEP
> +#include
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void fsl_ddr_board_options(memctl_options_t *popts,
> +dimm_params_t *pdimm,
> +unsigned int ctrl_num)
> +{
> + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
> + ulong ddr_freq;
> +
> + if (ctrl_num > 1) {
> + printf("Not supported controller number %d\n", ctrl_num);
> + return;
> + }
> + if (!pdimm->n_ranks)
> + return;
> +
> + pbsp = udimms[0];
> +
> + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
> + * freqency and n_banks specified in board_specific_parameters table.
> + */
> + ddr_freq = get_ddr_freq(0) / 100;
> + while (pbsp->datarate_mhz_high) {
> + if (pbsp->n_ranks == pdimm->n_ranks) {
> + if (ddr_freq <= pbsp->datarate_mhz_high) {
> + popts->clk_adjust = pbsp->clk_adjust;
> + popts->wrlvl_start = pbsp->wrlvl_start;
> + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> + goto found;
> + }
> + pbsp_highest = pbsp;
> + }
> + pbsp++;
> + }
> +
> + if (pbsp_highest) {
> + printf("Error: board specific timing not found for %lu MT/s\n",
> +ddr_freq);
> + printf("Trying to use the highest speed (%u) parameters\n",
> +pbsp_highest->datarate_mhz_high);
> + popts->clk_adjust = pbsp_highest->clk_adjust;
> + popts->wrlvl_start = pbsp_highest->wrlvl_start;
> + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> + } else {
> + panic("DIMM is not supported by this board");
> + }
> +found:
> + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
> + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
> +
> + popts->data_bus_width = 0; /* 64-bit data bus */
> + popts->otf_burst_chop_en = 0;
> + popts->burst_length = DDR_BL8;
You don't need to set these options unless you specifically want to
disable on the fly burst chop. Do you?
York
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support
On 09/08/2016 05:07 PM, Prabhakar Kushwaha wrote: >>> UART: supports two UARTs up to 115200 bps for console >> >> The board specification doesn't belong to commit message. Instead, you >> can add what features have been supported, such as boot source, any >> important commands, special care to prepare the image, etc. >> > > As such there is no guideline about what should be in commit message of a > board support. > I request you to guide us with about required things in board support commit > message. > > It will help future board support patches. > Good idea. I will write an internal memo. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support
Hi York, > -Original Message- > From: york sun > Sent: Thursday, September 08, 2016 10:51 PM > To: Q.Y. Gong ; u-boot@lists.denx.de > Cc: Prabhakar Kushwaha ; Vincent Hu > ; S.H. Xie ; Z.Q. Hou > ; Wenbin Song ; Shengzhou > Liu > Subject: Re: [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support > > On 09/07/2016 03:08 AM, Gong Qianyu wrote: > > From: Mingkai Hu > > > > LS1046ARDB Specification: > > - > > Memory subsystem: > > * 8GByte DDR4 SDRAM (64bit bus) > > * 512 Mbyte NAND flash > > * Two 64 Mbyte high-speed SPI flash > > * SD connector to interface with the SD memory card > > * On-board 4G eMMC > > > > Ethernet: > > * Two XFI 10G ports > > * Two SGMII ports > > * Two RGMII ports > > > > PCIe: > > * PCIe1 (SerDes2 Lane0) to miniPCIe slot > > * PCIe2 (SerDes2 Lane1) to x2 PCIe slot > > * PCIe3 (SerDes2 Lane2) to x4 PCIe slot > > > > SATA: > > * SerDes2 Lane3 to SATA port > > > > USB 3.0: one super speed USB 3.0 type A port > > one Micro-AB port > > > > UART: supports two UARTs up to 115200 bps for console > > The board specification doesn't belong to commit message. Instead, you > can add what features have been supported, such as boot source, any > important commands, special care to prepare the image, etc. > As such there is no guideline about what should be in commit message of a board support. I request you to guide us with about required things in board support commit message. It will help future board support patches. --prabhakar ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support
On 09/07/2016 03:08 AM, Gong Qianyu wrote: > From: Mingkai Hu > > LS1046ARDB Specification: > - > Memory subsystem: > * 8GByte DDR4 SDRAM (64bit bus) > * 512 Mbyte NAND flash > * Two 64 Mbyte high-speed SPI flash > * SD connector to interface with the SD memory card > * On-board 4G eMMC > > Ethernet: > * Two XFI 10G ports > * Two SGMII ports > * Two RGMII ports > > PCIe: > * PCIe1 (SerDes2 Lane0) to miniPCIe slot > * PCIe2 (SerDes2 Lane1) to x2 PCIe slot > * PCIe3 (SerDes2 Lane2) to x4 PCIe slot > > SATA: > * SerDes2 Lane3 to SATA port > > USB 3.0: one super speed USB 3.0 type A port >one Micro-AB port > > UART: supports two UARTs up to 115200 bps for console The board specification doesn't belong to commit message. Instead, you can add what features have been supported, such as boot source, any important commands, special care to prepare the image, etc. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
