Re: [USRP-users] Starting with USRP210N

2018-05-20 Thread Neel Pandeya via USRP-users
Hello Akram: Many of the books on the Suggested Reading page cover digital communications and probability. There are several introductory books, and I'd suggest these senior- or graduate-level books. Digital Communications: Fundamentals and Applications (2nd Edition) by Bernard Sklar Digital

Re: [USRP-users] Starting with USRP210N

2018-05-20 Thread whoppix_tn whoppix via USRP-users
Thanks Neel! I will start with that. Anything about digital transmission and probability? Regards, Akram > On May 21, 2018, at 04:24, Neel Pandeya wrote: > > I'm not sure exactly what you're looking for, but there are a bunch of > resources on the Knowledge Base (KB)

Re: [USRP-users] Starting with USRP210N

2018-05-20 Thread Neel Pandeya via USRP-users
I'm not sure exactly what you're looking for, but there are a bunch of resources on the Knowledge Base (KB) that should help get started. https://kb.ettus.com/N200/N210 https://kb.ettus.com/WBX https://kb.ettus.com/USRP_N_Series_Quick_Start_(Daughterboard_Installation)

[USRP-users] Starting with USRP210N

2018-05-20 Thread whoppix_tn whoppix via USRP-users
Hi All, I bought a USRP N210 with WBX daughter card, and I would need some guidance to start playing with it. I guess I would need to start with some reading about digital transmission, probability, and then some Python and C++ tutorial (since I didn’t play with this for more than 15 years).

Re: [USRP-users] DC power supply for E313

2018-05-20 Thread liu Jong via USRP-users
Thank you,Neel 2018-05-20 2:52 GMT+08:00 Neel Pandeya : > Hello Jong: > > I think Robin answered this in a separate thread with you, so I'm just > responding to conclude this thread. > > The behavior that you describe is a result of a corrupted bit in the AVR > EEPROM

Re: [USRP-users] Build E310_sg3.bit problem

2018-05-20 Thread Nicolas Cuervo via USRP-users
Hello Artyom, Unfortunately, this is something we are aware of and has to do with the high utilization that the DDCs and DUC blocks are taking. We are actively working on reducing the FPGA utilization of these blocks in order to make this build possible. Regards, - Nicolas On Sun, May 20, 2018

Re: [USRP-users] Build E310_sg3.bit problem

2018-05-20 Thread Artyom Asadchy via USRP-users
2017.4 вс, 20 мая 2018 г., 17:25 Marcus Müller : > Interesting! > What's your Vivado version? > > On 20 May 2018 13:44:28 GMT+02:00, Artyom Asadchy > wrote: >> >> Hello, Marcus. >> Yes. this is the unmodified image. I clone it from

Re: [USRP-users] Build E310_sg3.bit problem

2018-05-20 Thread Marcus Müller via USRP-users
Interesting! What's your Vivado version? On 20 May 2018 13:44:28 GMT+02:00, Artyom Asadchy wrote: >Hello, Marcus. >Yes. this is the unmodified image. I clone it from >https://github.com/EttusResearch/fpga, checkout to rfnoc-devel (in my >case >commit

Re: [USRP-users] Adding IP to RFNoC-OOT

2018-05-20 Thread Matthias Schraml via USRP-users
Hi Nicolas, thank you for your answer. I will have a look at the OOT example and try to adapt the file names to my project. However, I am not able to find any Makefile.inc in an OOT created by the rfnocmodtool. I have recently cloned the master branch of gr-ettus. So I really appreciate

Re: [USRP-users] Build E310_sg3.bit problem

2018-05-20 Thread Artyom Asadchy via USRP-users
Hello, Marcus. Yes. this is the unmodified image. I clone it from https://github.com/EttusResearch/fpga, checkout to rfnoc-devel (in my case commit d1d683bcd87bd3cea56f9654152b53e4830db612), than navigate to "usrp3/top/e300", run "source setupenv.sh" and "make E310_sg3". Best regards, Artyom.

Re: [USRP-users] Adding IP to RFNoC-OOT

2018-05-20 Thread Nicolas Cuervo via USRP-users
Hello Matthias, thanks for the feedback. We are planning to add such file structure near in the future. Please have a look at this example [1] which you can adapt to your OOT module in order to add the IP. Keep in mind that rfnocmodtool as of now generates both the Makefile.srcs and the

Re: [USRP-users] Rx streaming to alternate destination

2018-05-20 Thread Marcus Müller via USRP-users
Hi Rob, Often you can get around a complex solution with a little hack: I presume you want a "thin connection, lesser CPU" computer ("Smarts") to control the USRP, while you want a beefy machine ("Beef") to capture the stream. At least for the X310, it works to use a static route on Smarts

Re: [USRP-users] Build E310_sg3.bit problem

2018-05-20 Thread Marcus Müller via USRP-users
Hello Artjom, Is this the unmodified image? The error basically complains about too much logic to put on the FPGA, and that doesn't happen with our stock images. How are you building this? Best regards, Marcus On 19 May 2018 20:16:40 GMT+02:00, "Артем Асадчий via USRP-users"