Hi Ashish,
10GBASE-LR is preferred in my project. 1GbE copper is a workaround if 10GbE
fiber is not available at certain site. The only thing is that I need long
distance fiber (2km-10km). So I could not use the first one you
recommended.
When using HG image, do I need to disconnect SFP0 so that
>
> You can try using the "num_recv_frames" option in the device argument--I'd
> suggest trying 128 and 256.
>
I get tons of errors right after seeing [INFO] [B200] Operating over
USB 3. Would
this explain why I can't seem to stream fast?
Here's what I get for 128
Creating the usrp device with: n
Hi Rob,
Thanks, I just tested FS SFP-10GLR-31 on HG image (I connected to SFP1) but
unfortunately it does not work. Maybe I should do some more test.
That module actually work for my Dell switch.
Which FPGA image did you use? Are you connecting fiber to SFP0 or SFP1 or
both? Is that 10Gb Ethernet
On 07/24/2018 11:42 PM, RizThon via USRP-users wrote:
I have used the b2x0 radios for some applications myself, we have
had no luck sampling much higher than 30MS/s. I think real-world
USB3 speeds max out around 100MB/s.
Will
Thanks Will, that matches my experience. At 28MS/s i
>
> I have used the b2x0 radios for some applications myself, we have had no
> luck sampling much higher than 30MS/s. I think real-world USB3 speeds max
> out around 100MB/s.
>
> Will
Thanks Will, that matches my experience. At 28MS/s it tells me I need to
stream at 112MB/s.
You cannot stream f
I've just made
https://raw.githubusercontent.com/EttusResearch/uhd/master/host/examples/rx_samples_to_file.cpp
work yesterday on VS2017, compiled in *Release* x86 (Debug version does not
work, probably because we mix Debug and Release files), here's what I wrote
down
- Unpack UHD somewhere
http://
Hi all,
We have now finalized, tagged and released UHD 3.13.0.0. We found a
number of issues during testing, but not enough to warrant a second
release candidate. As with other minor releases, you might not want to
upgrade because you are fine with the 3.12.0.0 feature set. If this is
the case, th
On 06/25/2018 07:20 AM, Andreas Bauer via USRP-users wrote:
> Hello,
>
>
> we are currently working with a USRP X310 with a Twin RX daughter board.
> We are interested on more information about the CHDR protocol.
>
>
> The documentation on https://files.ettus.com/manual/page_rtp.html seems
> to
Link should be:
https://github.com/EttusResearch/fpga/blob/f27926410328883a315d5230146936d2d782bd09/usrp3/top/e300/e310_core.v#L319
On 07/24/2018 02:20 PM, Martin Braun wrote:
> I think you might be fine changing this line:
>
> https://github.com/EttusResearch/fpgadev/blob/f27926410328883a315d52
On 06/28/2018 05:09 AM, Fabian Schwartau via USRP-users wrote:
> Hi everyone,
>
> I am still working on the synchronization of my two USRP X310. Both get
> the same 10 MHz, 1 PPS and LO signals. I made a small piece of code to
> toggle one of the GPIOs at the Aux I/O of each USRP in a timed manner
On 07/18/2018 05:40 AM, Massimo Bastianon via USRP-users wrote:
> I'm struggling with an easy task: get USRP B200mini working with my code.
>
> I'm using windows 10 x64 and visual studio 2017, I downloded and
> compiled boost 1.67.0 (both 32 and 64 bit). I used udh.dll from UHD
> 3.12.0.0 and GNUR
I think you might be fine changing this line:
https://github.com/EttusResearch/fpgadev/blob/f27926410328883a315d5230146936d2d782bd09/usrp3/top/e300/e310_core.v#L319
...but it's untested and unsupported.
Cheers,
Martin
On 07/22/2018 04:02 AM, carry chen via USRP-users wrote:
> Hi,
>
> list,
>
Jason,
this is a tough one. I have no ideas, other than 'throw in a couple of
ILAs and see where it's stuck'.
-- M
On 07/23/2018 12:03 PM, Jason Matusiak via USRP-users wrote:
> I have a flowgraph with a custom RFNoC block in the middle. That block
> has 2 inputs and 2 outputs. Just to get sta
On 07/23/2018 03:17 PM, Erik Malone via USRP-users wrote:
> Hi
>
> I'm looking for a way to log all signals when simulating an RFNoC design
> in batch mode. This would help me to run longer tests and then bring up
> a waveform whenever an error occurred. Preferably, I'd like to keep
> within Et
Hm, thanks for updating! We won't be supplying any 3.12 fixes any more,
but 3.13 is almost ready to go and it's good that it fixes your issue.
Cheers,
Martin
On 07/24/2018 01:57 PM, Keith k wrote:
> Hello Martin
>
> I just noticed I had some library issues and 3.13 was not being used.
> After do
On 07/24/2018 01:59 PM, Martin Braun wrote:
> Rob,
>
> two more comments: The git hash of the FPGA source gets baked into the
> image, and you can read /mboards/0/fpga_version_hash to identify the image.
...and uhd_usrp_probe prints that, too.
-- M
__
Rob,
two more comments: The git hash of the FPGA source gets baked into the
image, and you can read /mboards/0/fpga_version_hash to identify the image.
As for logging, sure, go use UHD. It was designed to make it easy to
distinguish the source of logging messages. I sometimes run UHD in
high-verb
Hello Martin
I just noticed I had some library issues and 3.13 was not being used. After
double checking, 3.13 is working correctly, but 3.12 did not. I'm not
dependent on running 3.12 though, I'm just having another issue I'm trying
to diagnose and was trying different versions.
On Tue, Jul 24,
FYI, we fixed a couple of sc12/8 related issues on our latest master
branch. As Marcus says, if you're doing dual channel on the B210, you
can only go to 30.72 Msps though.
-- M
On 07/24/2018 12:06 PM, Marcus D. Leech via USRP-users wrote:
> On 07/24/2018 03:18 AM, RizThon via USRP-users wrote:
We can't speed up Vivado, unfortunately. Maybe if we design an RFNoC
block that does place and route
So, there's not much you can do. You might be able to use design
checkpoints, but that's an advanced Vivado feature and we don't have
support out of the box for that. You need to know what you
Hello Martin
Im using "tx_subdev" : "A:A" in my config.
On Tue, Jul 24, 2018 at 2:16 PM, Martin Braun via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Keith,
>
> what's the subdev spec you're using?
>
> There shouldn't have been any issues, and we do test releases using the
> N200, but mayb
Keith,
what's the subdev spec you're using?
There shouldn't have been any issues, and we do test releases using the
N200, but maybe we missed a case here.
-- M
On 07/24/2018 12:42 PM, Keith k via USRP-users wrote:
> Hello all
>
> My multiusrp application will run using 3.11 and below, but when
I am not an FPGA or Vivado expert, but I tried to do the same thing. I
believe Vivado is limited to 4 cores, so sadly, it seems like your best bet
is to get a quad-core with the fastest clock you can find. I think AWS just
released a "frequency-optimized" instance family. Maybe take a look at that.
Hello all
My multiusrp application will run using 3.11 and below, but when I switch
to any version about 3.12, I now get the following error:
Error: LookupError: IndexError: multi_usrp: TX channel 140737160875440 out
of range for configured TX frontends
Did something change in the way that chann
On 07/24/2018 03:18 AM, RizThon via USRP-users wrote:
Hi all,
I'm still having issues with a B210 with sample rates greater than
28MS/s. At 28 I get a few overruns out of a million blocks of 1024
samples, but as I sample faster, the number of overruns grow fast.
I have an AMD Ryzen 7 2700 (8
I know Vivado build times are dependent on how optimized you want things and
how utilized the FPGA is, but is there a way to speed up the build times?
I started doing my builds on a server thinking it would be a huge boost from my
PC, but I am not really seeing a difference. It has 64 cores an
Hello Mr Munir,
Yes, GNU Radio will work with a 12 core CPU. Problems with the audio sink
are usually a clock crossing issue. Your sound card is running at a
slightly different sample rate than whatever the source of your samples is.
Do you have a throttle block or a piece of hardware such as a ra
Hello Andreas,
The digital frequency offset is handled in the DUC block which does not run
in the same clock domain as the Radio block. The phase accumulator register
will only increment when samples are being processed. The simplest way to
cause the phase accumulator to continuously run (from the
I tried using directly the UHD interface. I reused the code example from
https://raw.githubusercontent.com/EttusResearch/uhd/master/host/examples/rx_samples_to_file.cpp
, I just added
fprintf(f, "%11.9lf\n", md.time_spec.get_real_secs());
after reading each block of samples to simply store all ti
Rob,
Addressing your first question, I would modify (or add) one setting_reg in
your modified NoC Block, and instantiate the parameter "at_reset" (which is
usually not included in the instantiation) with a known value (such as a
localparam defined previously in the file or in an include file).
Ch
Hi,
I'll add a few thoughts since I've looked into this a bit...
> Although rfnoc supports different number of inputs and outputs uhd does
not and you'll get all sorts of issues trying to address this.
To clarify what I've seen in behavior and in the code, there are some
places in UHD software t
Hi Jorge,
The N310 requires that one of the SFP+ connections is used, not just the
RJ45 GigE connection. Info on setting up those connections is here in the
Getting Started guide.
https://kb.ettus.com/N300/N310_Getting_Started_Guides#Setting_Up_a_Streaming_Connection
Regards,
Derek
On Tue, Jul 2
Hi guys,
Although rfnoc supports different number of inputs and outputs uhd does not and
you'll get all sorts of issues trying to address this.
This is the reason why adder block also has a subtract output...
Another issue is that loopback within fpga does not work. This means that
signals in a c
Please, any help?? :( :( :(
2018-07-12 19:13 GMT+02:00 Brassard, Sean M. :
> We never received any help from Ettus on this and never got past the
> problem.
>
>
>
> Sean
>
>
>
> *From:* Carlos Alberto Ruiz Naranjo [mailto:carlosruiznara...@gmail.com]
> *Sent:* Thursday, July 12, 2018 2:42 AM
> *T
Hi USRP Users
I got the new N310, and followed the online Getting Started Guides step by
step,
and I'm able to run the rx_ascii_art_dft and some example programs on
Ubuntu.
However, while I tried it on Windows OS,
I can ping the address (192.168.10.2) and find it using
uhd_find_devices.exe, bu
Hi all,
I'm still having issues with a B210 with sample rates greater than 28MS/s.
At 28 I get a few overruns out of a million blocks of 1024 samples, but as
I sample faster, the number of overruns grow fast.
I have an AMD Ryzen 7 2700 (8 physical cores @ 3.2GHz), 16GB RAM, Gigabyte
GA-AB350N, Wi
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