[USRP-users] Using both TX/RX and RX2 ports on the same daughter board to receive signal simultaneously

Hi, I'm trying to using both TX/RX and RX2 ports on the same daughter board of X310 to receive signal at the same time. On the host side, I tried to create a new recv_to_file thread inside the main thread(which will execute another recv_to_file). However, the terminal will show the error

Re: [USRP-users] N210 - pure (real) 50MHz sine output

Hi Alex, your application sounds cool :) So, amplitude stability over ten seconds isn't usually a design goal – how strong are these amplitude modulations? Also, I'd have a standard visualization that I'd usually share here: offset tuning $f_\text{RF}$ is the frequency of the actual

Re: [USRP-users] RFNoC:Delay block?

I made one for a project, but can't share it as it's customer work. It's a little bit tricky and I never got it 100% right, but it works well enough for what it needs to do. The tricky parts are preserving or reconstituting packet boundaries, and being able to advance and delay the stream without

[USRP-users] N210 - pure (real) 50MHz sine output

​Hello - I'm attempting to use my N210 in a somewhat unconventional application that requires a pure (real) sine wave output, with some frequency modulation around 50MHz. This signal will be used to resonate a physical device within a small band around 50MHz. H​owever, I'm finding when the

Re: [USRP-users] C++ --> GRC(Socket PDU ---> QT Frequency GUI)

Hi Jack, PDUs are not just samples one after the other – they contain metadata. I can't really imagine what your flow graph looks like, so I'd be grateful for a screenshot (File->Screen Capture). Anyway, there'd be no obvious reason your UDP detour would make things faster – maybe the

Re: [USRP-users] Support with UHD C++ API

For minimum data loss at 50MSps, you have to use a 10G cable , Data rate with 1G is limited to ~33 MSps which rounds off to 28 MSps (integral decimation). Karan Suri University of Michigan On Aug 2, 2017 3:56 PM, "Derek Kozel via USRP-users" < usrp-users@lists.ettus.com> wrote: > Hello

[USRP-users] RFNoC:Delay block?

Hi, I am wondering if there is some type of variable delay block available in RFNoC. I see that there is a Delay block available in gnu-radio, but I need it to be in the FPGA. Thanks, Jim ___ USRP-users mailing list USRP-users@lists.ettus.com

[USRP-users] C++ --> GRC(Socket PDU ---> QT Frequency GUI)

Hi, I've been having some difficulty getting reliable data flow from my USRP X310 with a GRC flowgraph, so I'm trying out writing my system in C++ with the UHD driver API. My first step has been to retrieve samples from the X310, forward them to a UDP port and then pick them up with a GRC Socket

Re: [USRP-users] Support with UHD C++ API

Hello Snehasish, The UHD examples contain all the code to receive a stream of samples at that rate. What have you tried? We may be able to help better if you explain what is not working. 50 MS/s is not too high of a load so most recent computers should have no problem receiving that much data

[USRP-users] Support with UHD C++ API

Hello I am trying to receive the entire 25MHz gsm signal using usrp x310 at an sample rate of 50MSPS, which i need to receive in the host and send to the GPU for demodulation. Please help me how to implement this with minimum data loss. BR Snehasish

Re: [USRP-users] Brench Maint and Master of UHD

Hi Daniele, Generally speaking, 'maint' should be stable. If you need an absolutely stable version, it is recommended to use a tagged release, such as 'release_003_010_002_000' (UHD 3.10.2.0) or 'release_003_009_007' (UHD 3.9.7). We perform release testing on every tagged version of UHD.

[USRP-users] doubts about burst tranmission using tag SOB and EOB

Dear all, I tried to achieve burst transmission on usrp X310, the brief tx flowgraph is in the below: message_burst_source -> signal processing blocks --> usrp_sink New message will be inserted into the message queue of message_burst_source. Since message_burst_source will attach SOB and EOB

Re: [USRP-users] Using Aurora enabled FPGA Image

Hi, I am trying to do the following, 1) Is it possible to use one of the HA/XA firmwares on the X310 in order to allow UHD configuration via the ethernet SFP+ port and streaming via the aurora SFP+ port directly to an FPGA which has aurora IP already working? 2) If so, then is the process

Re: [USRP-users] PPS sync with USRP E310 timeout error

Hello Derek, I thought the “set_time_unknown_pps” checks to confirm that the time is correctly set? If that doesn’t, how do I know that the sync is set correctly without using a spectrum analyzer? Thanks From: Derek Kozel [mailto:derek.ko...@ettus.com] Sent: Wednesday, August 2, 2017 7:33 AM

Re: [USRP-users] Trying to verify Rx MIMO operation of x310

Hi Mark, I've added back on the list, it's useful to keep everyone in sync with progress. The WX FFT only takes one input but the QT Frequency Sync has a configurable number of inputs. In general the QT GUIs are being promoted over WX. Regards, Derek On Tue, Aug 1, 2017 at 7:40 PM, Mark

Re: [USRP-users] PPS sync with USRP E310 timeout error

Hello Daniel, There is no check in your code to confirm that the time is correctly set. The 1PPS signal should be a square wave rather than a sine wave. It is a logic signal rather than an RF one and the sync port is designed to handle it.

Re: [USRP-users] FPGA Build problem

Hi Nauman, I'm guessing you're building FPGA for the X300 series.. Typically this is a problem with setting the environment correctly. In the build directory (uhd-fpga/usrp3/top/x300), first run "source setupenv.sh". This calls uhd-fpga/usrp3/tools/scripts/setupenv_base.sh, which populates the

Re: [USRP-users] what do fc64 and sc16 stand for?

I guess it is: f = float s = signed integer c = complex Claudio On 08/02/2017 12:47 PM, Ali The GREAT! via USRP-users wrote: > Hi all, > I wonder what fc64, fc32, sc16 and sc8 stand for. > I know that fc64 = complex and so on. > I just want to know the abbreviations. > Thanks > > love > ali >

[USRP-users] FPGA Build problem

Hi, I am getting this error while I am trying to build the project from makefile. I have vivado paths already set. source /home/workspace/fpga/usrp3/tools/scripts/viv_generate_ip.tcl # set xci_file $::env(XCI_FILE) ; # set part_name$::env(PART_NAME)