On 07/31/2018 11:40 AM, Sirkin, Joshua F. via USRP-users wrote:
> Has sc8 capability been added to the X310? I know it the past it hasn't but
> this page seems to indicate sc8 is generally implemented
> https://files.ettus.com/manual/structuhd_1_1stream__args__t.html. We have an
> X310 with a
On 08/07/2018 12:22 PM, Jay Kuhn via USRP-users wrote:
> Error: RuntimeError: FPGA component `DDC' is revision 1 and UHD supports
> revision 2. Please either upgrade the FPGA image (recommended) or
> downgrade UHD.
Jay,
this means you upgraded the FPGA, but not to the correct version. Please
make
On 08/15/2018 11:46 AM, Rob Kossler via USRP-users wrote:
> Anyone know the cause & solution to the following startup error? This
> just started today after a cascade of problems which ultimately required
> me to reflash the SD card.
>
> $ uhd_usrp_probe --args="addr=192.168.61.2"
> [INFO] [UHD]
The actual AXI interface is pretty fast, but for all practical purposes,
if you want to stream samples, you're in the 1-2 Msps range.
You can run benchmark_rate on the device to get an idea. It will top out
at around 12.5 Msps, and you can push it a little if you use taskset to
nail it to one core
On 08/09/2018 02:31 PM, Rob Kossler via USRP-users wrote:
> When I first started using MPM 3.13, I was pleased to see the fast
> initialization times compared to previous versions. Now, after spending
> the better part of a couple of days troubleshooting issues, I am much
> less thrilled with this
On 08/09/2018 08:50 AM, Philip Balister via USRP-users wrote:
> On 08/08/2018 11:49 PM, Walter Maguire via USRP-users wrote:
>> Hi all,
>>
>> The readme file at https://github.com/EttusResearch/meta-ettus seems to
>> be out of date with the current sumo release of poky. meta-ettus seems
>> to requi
ow
> as soon as we have a fix.
>
> Regards,
> Michael
>
>
> On Wed, Aug 15, 2018 at 3:52 PM, Martin Braun via USRP-users
> mailto:usrp-users@lists.ettus.com>> wrote:
>
> On 08/09/2018 02:31 PM, Rob Kossler via USRP-users wrote:
> > When I first start
On 08/24/2018 10:14 AM, Tom McDermott via USRP-users wrote:
> I installed and built gnuradio and UHD some time ago from the SBRAC script.
>
> I am at the head of gnuradio maint-3.7, and am on uhd maint. My
> version of uhd is 3.10.2.0 and my FPGA
> images are also 3.10.2. There appears to be 3
Andreas,
you *should* be able to use the .bit file. Does this happen when you
build from master branch? The Vivado version is correct.
-- M
On 08/23/2018 02:11 AM, Sylvain Munaut via USRP-users wrote:
> Hi,
>
>> Just for curiosity:
>> The .bit-file is exactly the same as the .bin-file, except t
On 09/03/2018 07:50 PM, Marcus D. Leech via USRP-users wrote:
> On 09/03/2018 12:15 AM, Marcus D. Leech via USRP-users wrote:
>> On 09/03/2018 12:11 AM, RizThon wrote:
>>> Thanks, I'll try to run it on some intel hardware ("Ettus Research
>>> recommends using the Intel Series 7, 8, and 9 USB contro
On 09/03/2018 08:21 PM, Chintan Patel via USRP-users wrote:
> Hello,
>
> I have defined a new readback register in the FPGA in the b205_core
> file, adjacent to the lock state register. What is the least invasive
> function call/method in the UHD driver/software to be able to read this
> newly def
On Mon, Sep 03, 2018 at 11:39:56AM +, Peng Wang via USRP-users wrote:
>Hi all,
>
>I have couple of USRP X310 and also the PCIe connectivity kit. However, I
>found that the driver [1] says that it can only support up to kernel
>version 4.2.x. Since I am using ubuntu 18.04 with m
On Fri, Aug 31, 2018 at 10:14:27AM -0400, Marcus D. Leech via USRP-users wrote:
> On 08/31/2018 09:26 AM, Flo A. via USRP-users wrote:
> >Hei!
> >
> >I have a very general question regarding the function of the digital mixer
> >as part of the USRP motherboard-DDC:
> >
> >Since the RF signal is alre
On Fri, Aug 17, 2018 at 03:53:56PM -0700, Andrew Danowitz via USRP-users wrote:
> Hi,
> I generated an rfnoc fpga image using the latest UHD-fpga tools on the
> rfnoc-devel branch. When I go to run it with the latest UHD on the
> rfnoc-devel branch, I get RuntimeError: RuntimeError: FPGA component
On Fri, Aug 17, 2018 at 01:02:28PM -0400, Daryl Lee via USRP-users wrote:
> In November of 2016, I cross-compiled UHD (git-cloned) on my Ubuntu 16.04
> development host targeting a Zynq chip with Linux built with Petalinux
> 2016.3. Life has passed me by and now I need to re-build the library usin
/Xilinx/. Although I have modified
>uhd-fpga/usrp3/tools/scripts/setupenv_base.sh for path to VIvado, 'make
>xsim' doesn't seem to touch it when running.
Did you try running setup_env.sh --vivado-path=?
-- M
>Tien
>On Fri, Feb 9, 2018 at 11:05 AM, Marti
On Wed, Sep 05, 2018 at 11:01:18AM -0400, Marcus D. Leech wrote:
> I also tried benchmark_rate. In random mode, I have no overflow in sc8,
> but in sc16 I have lots of overflows and error messages. Without the
> random mode, I can go up to 36MS/s in sc16, and 56MS/s in sc12! So for
>
You can do this, as long as you have 2 separate streamers. The master
clock rate will be the same on both, so you can only have different
decimations/interpolations. For example, you could have 10 Msps on one
and 20 Msps on the other if your MCR is 200 MHz (which is the default).
-- M
On 09/07/20
Dear friends and fans of software defined radio and free/open source
radio topics in general,
next year's FOSDEM (the free and open source developer's meeting in
Brussels, Europe) will, once again, feature a track on Software Defined
Radio and other radio-related topics. To better capture the broa
Thanks for reporting this back to us! I'm glad this resolved your issues.
-- M
On Fri, Nov 2, 2018 at 2:16 PM Ali Dormiani via USRP-users <
usrp-users@lists.ettus.com> wrote:
> I can second Daniel. Mr. West has troubleshooted our N310's and came to
> the same conclusion. Our N310 units (hardware
Note that we are working on a revised filesystem for E310 which we
anticipate to ship around the end of the year; it will include a much more
recent kernel and gcc version.
-- M
On Fri, Nov 2, 2018 at 12:52 PM Philip Balister via USRP-users <
usrp-users@lists.ettus.com> wrote:
> On 11/01/2018 04
On Wed, Oct 24, 2018 at 3:02 PM EJ Kreinar via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi All,
>
> I've been working with the N3xx series for a week or so and I've hit a few
> issues in the "operational" side of things that are either not addressed in
> the manual or work differently tha
I would recommend not modifying the radio, but to add an RFNoC block of
your own. Take a look at our RFNoC resources on the Knowledge Base (
kb.ettus.com).
-- M
On Thu, Nov 1, 2018 at 6:46 AM carry chen via USRP-users <
usrp-users@lists.ettus.com> wrote:
> hi,
> this days I make some modify in
Tobias,
you would provide multiple addrs in the device args (e.g.,
addr0=192.168.40.2,addr1=192.168.40.3) but you would have a single device3
block.
-- M
On Tue, Oct 30, 2018 at 6:07 AM Mitterer, Tobias via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hello,
>
>
>
> We couldn’t find any ex
You have two options:
1. Burst both TX and RX. To do that, you call send() on the TX streamer
with the EOB flag set in the metadata, and you use issue_stream_command()
on the RX streamer to request fixed number of samples. In both cases, you
would also provide a timestamp.
2. Permanently RX, and
Varala,
you only need to add a logging backend if you want the log message to go
somewhere other than stderr or a log file.
The 'console logger' means 'stderr'. So, just grab your stderr output if
you want to have those log messages. You can control the console log level
with the UHD_LOG_LEVEL an
Emanuel,
the TwinRX only works with 200e6 clock rate. The analog filtering is not
designed for other rates. So if you have even one TwinRX, you need 200e6.
I'll make sure we update our manual to clarify that.
-- M
On Fri, Jan 11, 2019 at 4:51 AM Emanuel via USRP-users <
usrp-users@lists.ettus.co
That is correct, and that will also allow you to run said example.
-- Martin
On Thu, Jan 10, 2019 at 10:27 AM Xingjian Chen via USRP-users <
usrp-users@lists.ettus.com> wrote:
> It works by setting tx-blockid to 0/Radio_0 and tx-chan to 1. I think
> there is only one radio in E312 but two chann
On Wed, Feb 13, 2019 at 11:58:41AM -0800, Nick Foster wrote:
>Any plans to update to the latest API? Won't compile with anything after
>17.05.
UHD only works with DPDK 17.11. DPDK changes APIs quite often, so we've
decided to lock it down.
-- M
>
>On Wed, Feb 13, 2019, 11:33 AM Micha
Rob,
yes, you can query UHD_RFNOC_FOUND. Check out this example:
https://github.com/EttusResearch/gr-ettus/blob/dcb780b77a114a265bb355fdba4f24033c3412c4/CMakeLists.txt#L138-L141
-- M
On Wed, Feb 20, 2019 at 8:52 AM Rob Kossler via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi,
> I have a
You can feed the OctoClock from the X310, and then use the OctoClock's
output to drive the N210. All devices will be synchronized, in frequency,
and the N210s will be synchronized in time, but the X310 and N210s will not
be synchronized in time. However, that timing offset you might able to
calibra
This pokes a register in the STC3. It'll pull the FPGA into reset. You then
need to wait a bit before the FPGA is back up.
-- M
On Fri, Feb 22, 2019 at 10:21 AM Brian Padalino via USRP-users <
usrp-users@lists.ettus.com> wrote:
> On Wed, Feb 20, 2019 at 7:45 PM Jonathon Pendlum <
> jonathon.pend
Armin,
I'd like to learn a little more about this failure. Here's a couple of
questions:
- How many USRPs are you running at once? Does this also happen with a
single USRP?
- Does this also happen when using a vanilla UHD example? Since you're
running a custom RFNOC block, it would be good to elim
Make sure the driver is running:
$ lsmod | grep niusrp
niusrpriok421888 0
nistreamk 139264 2 niusrpriok,NiRioSrv
nibds 57344 2 niusrpriok,NiRioSrv
nikal 118784 4 niusrpriok,nibds,NiRioSrv,nistreamk
If not, check the output of niusrprio_
Janos,
the purpose of the the API call is to configure analog filters, and not the
sampling rate. If your analog bandwidth is lower than the sampling rate,
there's nothing wrong with that. In fact, for the AD9361-based devices,
this is not unusual, since the analog bandwidth is 56 MHz, but the max
Half-Bands are very flat in the passband, and somewhat efficient to
implement because every second tap is zero. The CIC on the other hand, is
super efficient, but has a horrible frequency response.
So, you want to use the half-bands for decimation whenever possible. You
will have fewer aliases, th
No, you can do FPGA dev on the B200 series. However, you can't do RFNoC on
the B200 series. The manual has a few comments on it:
http://files.ettus.com/manual/page_usrp_b200.html#b200_customfpga
We expose a register interface (meaning you might not also have to modify
UHD), and there's a scratch s
Is this with vanilla code, or your own custom code?
On Thu, Sep 26, 2019 at 5:49 PM Jeff S via USRP-users <
usrp-users@lists.ettus.com> wrote:
> I'm trying to take what I learned from GRCon2019 from Neel and company's
> workshop, and I'm trying to perform the uhd_image_builder_gui.py script. It
>
Ishai,
it's a bit hard to tell from this snippet, since we're missing the
definitions of random_word and s. Which one is wrong, is it random_word, or
readback?
-- M
On Thu, Oct 3, 2019 at 12:56 AM ishai alouche via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi,
>
> I work with X310 and I
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