Re: [USRP-users] IQ baseband fade?

Try disabling automatic DC offset removal, or performing an offset tuning operation. Brian On Wed, May 23, 2018 at 3:50 PM Martin K via USRP-users < usrp-users@lists.ettus.com> wrote: > BPSK modulated RF at 2.2 GHz, -15dBm, feeding a power splitter >> | >> (A) --> -9dB pad --> B210 >> (B) -->

Re: [USRP-users] Multiple Output RFNoC Block

Hey EJ, On Tue, May 29, 2018 at 11:10 AM EJ Kreinar wrote: > Hi Brian, > > Fascinating question! I'm not sure many have considered this possibility > (1-input, 4-output RFNoC block), though I agree I'd like to see RFNoC > support this use-case... > > Looks to me like this for loop in

[USRP-users] Multiple Output RFNoC Block

I've got a single input, 4-output RFNoC block that I am trying to hook up to a C++ testbench, but I'm having some trouble. Referencing the unaligned output version from gr-ettus: https://github.com/EttusResearch/gr-ettus/blob/master/lib/rfnoc_block_impl.cc My graph is Radio -> DDC -> Custom

Re: [USRP-users] RFNoC On B210

On Sat, Jun 30, 2018 at 5:05 AM Peter Sanchez via USRP-users < usrp-users@lists.ettus.com> wrote: > Appreciate the feedback. Marcus, we have a project using RFNoC blocks on > the X310 to run this workflow, 2x Rx --> Splitstream for each RX --> DDC > for each split stream out --> FFT Sink. We

Re: [USRP-users] RFNoC FPGA clear_tx_seqnum behavior

Hi Ashish, On Wed, May 2, 2018 at 2:45 PM Ashish Chaudhari <ashish.chaudh...@ettus.com> wrote: > On Wed, May 2, 2018 at 8:20 AM, Brian Padalino via USRP-users > <usrp-users@lists.ettus.com> wrote: > > I had some blocks that worked just fine with the old rfnoc-devel

[USRP-users] RFNoC FPGA clear_tx_seqnum behavior

I had some blocks that worked just fine with the old rfnoc-devel branch using 2015.4, but when this latest change to 2017.4 came in, my blocks stopped working. I've found that a significant change was how clear_tx_seqnum seems to now work. I've noticed that clear_tx_seqnum will be set while

Re: [USRP-users] RFNoC FPGA clear_tx_seqnum behavior

Hey Ashish, On Wed, May 2, 2018 at 7:02 PM Ashish Chaudhari wrote: > Hi Brian, > > >> > Moreover, it seems like axi_wrapper.v uses clear_tx_seqnum to pass out > >> > config bus messages, so now that clear_tx_seqnum is set I am not able > to > >> > use > >> > the

[USRP-users] RFNoC FPGA OOT Xilinx IP Addition

Hi, I'm trying to add a piece of Xilinx IP using an .xci file, similar to how the normal flow for the FPGA build goes, but I want to keep it associated with my OOT source, and not change the main FPGA repository. I haven't found any instructions on how to do this, so I figure I'd ask here. Is

Re: [USRP-users] UHD API

On Thu, Aug 2, 2018 at 10:46 AM TIMMEN Koen via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello all, > > > > I am working on a custom RFNoC based signal generator module on the X310 > using UBX daughterboards. I have created a custom signal generator NoC > block, that generates IQ samples

Re: [USRP-users] Possible to enable via RFNoC block via RFNoC

On Mon, Jul 30, 2018 at 3:14 PM Jason Matusiak via USRP-users < usrp-users@lists.ettus.com> wrote: > I am curious if it is possible to enable an RFNoC block from another RFNoC > block? An example would be, turning on the siggen when another RFNoC block > decides that it should run. > Not sure I

Re: [USRP-users] UHD API

On Fri, Aug 3, 2018 at 3:19 AM TIMMEN Koen < koen.tim...@thalesaleniaspace.com> wrote: > > > *De :* Brian Padalino [mailto:bpadal...@gmail.com] > *Envoyé :* jeudi 2 août 2018 16:57 > *À :* TIMMEN Koen > *Cc :* USRP-users@lists.ettus.com > *Objet :* Re: [USRP-users] UHD API > > > > > > First, let

Re: [USRP-users] About CHDR packet size

On Wed, Aug 1, 2018 at 3:59 PM Nick Foster via USRP-users < usrp-users@lists.ettus.com> wrote: > That's the MTU of your network interface limiting the CHDR packet size. > Can't break up CHDR packets over multiple network packets. > Is the last statement that CHDR can't break over multiple

Re: [USRP-users] Custom OOT RFNOC modules no longer simulating or running on E310 after upgrade to latest UHD

On Wed, Aug 1, 2018 at 3:10 PM Andrew Danowitz via USRP-users < usrp-users@lists.ettus.com> wrote: > I recently upgraded to the newest versions of the development tools (fresh > pybombs installs of recipes rfnoc-e3xx for cross-compiling, and rfnoc for > local test and development). Since that

Re: [USRP-users] RFNOC transmission setup

On Fri, Aug 10, 2018 at 5:03 PM Anton Schlegel via USRP-users < usrp-users@lists.ettus.com> wrote: > I am having trouble setting up the transmission chain with RFNOC on an > X310. I was able to transmit and receive using multi_usrp on B205. > > For transmission, I understand that the RFNOC

Re: [USRP-users] UHD API

On Mon, Aug 6, 2018 at 3:37 AM TIMMEN Koen < koen.tim...@thalesaleniaspace.com> wrote: > Brian, > > > > I am not sure if I have stated my problem clearly. So I will reformulate: > My HDL module which I have verified using testbenches needs to be > controlled from the UHD API. However, I have

Re: [USRP-users] Transmit Thread Stuck Receiving Tx Flow Control Packets

On Tue, Aug 28, 2018 at 4:02 PM Alan Conrad via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi All, > > > > I’ve been working on an application that requires two receive streams and > two transmit streams, written using the C++ API. I have run into a problem > when transmitting packets and

Re: [USRP-users] RFNoC fifo filling up

On Wed, Aug 22, 2018 at 5:32 PM Jason Matusiak < ja...@gardettoengineering.com> wrote: > Brian, I really only want to send data when appropriate. I don't have the > code in front if me at the moment, but I can have tvalid high while I wait > for tready, right. So I don't see why it would be an

Re: [USRP-users] RFNoC fifo filling up

On Wed, Aug 22, 2018 at 3:53 PM Jason Matusiak via USRP-users < usrp-users@lists.ettus.com> wrote: > This is a long shot, but I have been fighting with my rfnoc block the last > few days trying to figure out why it won't work. I am basically combining > the threshold block and the siggen block

[USRP-users] RFNoC Software Emulation

I have a software model which performs the exact task I want done in RFNoC. I want to be able to integrate it into my UHD application in the RFNoC flow and be able to switch between the slow software model and the real RFNoC block in an FPGA. Is there a way I can create a software process

Re: [USRP-users] RFNoC Software Emulation

Hey Dario, On Sun, Jul 22, 2018 at 11:20 AM Dario Pennisi wrote: > Hi Brian, > It really depends on what you want to achieve. If you just want to perform > validation then you can use simulation which is already set up and > straightforward if you follow the examples. Also it would allow you to

Re: [USRP-users] RFNoC Software Emulation

Hey Dario, On Sun, Jul 22, 2018 at 3:55 AM Dario Pennisi wrote: > Hi Brian, > Don't think what you want to do is feasible. While the streaming data part > is easy as it's basically just an oot block, emulating register writes is > not possible because they go through APIs that send commands

Re: [USRP-users] RFNoC Software Emulation

Hi Dario, On Sun, Jul 22, 2018 at 1:57 PM Dario Pennisi wrote: > Hi Brian, > I think I understand where you're going but I still think you may have > more trouble than solutions. One for all is bandwidth. 10g Ethernet is just > able to support one channel at 200 msps. Unless you're downsampling

Re: [USRP-users] RFNoC DMA FIFO

On Thu, Jul 19, 2018 at 11:37 AM Jason Matusiak via USRP-users < usrp-users@lists.ettus.com> wrote: > I have a silly question. How do I add the axi_dma_fifo to my build? > > It looks like we can't add it to the uhd_image_builder command line, so I > am not sure the way to do it manually. Is

Re: [USRP-users] Use same RFNoC block twice

On Fri, Aug 31, 2018 at 2:54 PM Leandro Echevarría via USRP-users < usrp-users@lists.ettus.com> wrote: > Hey everybody, > > I've got a question. I have a RFNoC block that has a unique NoC ID as a > parameter, but is instantiated twice in my design (same situation as the > Radio Cores or DDC/DUC

Re: [USRP-users] FPGA Repository and Stability

On Tue, Sep 4, 2018 at 6:55 PM Ashish Chaudhari wrote: > On Tue, Sep 4, 2018 at 8:07 AM, Brian Padalino via USRP-users > wrote: > > Recently there was a significant change to the noc_block_vector_iir > > (specifically the vector_iir): > > > > > > > https

Re: [USRP-users] Phase Representation: Using Xilinx CORDIC IP with RFNoC

On Tue, Sep 4, 2018 at 9:15 AM Jon Pendlum via USRP-users < usrp-users@lists.ettus.com> wrote: > Hey Steve, > > The complex_to_mag_phase 32-bit output is a concatenation: [31:16] phase, > [15:0] magnitude. There is also complex_to_magphase_int16_int24 if you want > 24-bit phase, mag. The phase

Re: [USRP-users] FM Spectrum Capture, to many zeros?

On Tue, Sep 4, 2018 at 11:28 AM Jeremy Foran via USRP-users < usrp-users@lists.ettus.com> wrote: > Thanks Fabian, > > I have tried a few different values for timeout as per your recommendation > and none seem to have an affect: > 2.0 > 1.0 > 0.5 > 0.25 > 0.001 > > All have about the same result

[USRP-users] FPGA Repository and Stability

Recently there was a significant change to the noc_block_vector_iir (specifically the vector_iir): https://github.com/EttusResearch/fpga/commit/05ca30fe91330d54dcd005a3af4aeaa0dc26c8f8#diff-4b21f52231ba9f82bf132f633d594187 It's a pretty significant re-write of the block, and this behavior has

Re: [USRP-users] RFNOC: AXI Wrapper Configuration busses

On Thu, Sep 6, 2018 at 2:43 PM Pratik Chatterjee via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > Can anyone please provide some insight on the use of configuration buses > in the axi wrapper - why and when would we want to use them? Do they > complement the axis stream signals

Re: [USRP-users] RFNoC FPGA OOT Xilinx IP Addition

Hey EJ, On Tue, Feb 27, 2018 at 6:27 AM, EJ Kreinar wrote: > Hi Brian, > > There's a supported method to include OOT repos that can build and include > xilinx IP (or basically any other IP that you need, including HLS. I've yet > to try it with sysgen blocks, but that would

Re: [USRP-users] RFNoC block timeouts

On Thu, Mar 15, 2018 at 2:20 PM, EJ Kreinar via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi Sebastian, > > > Does RFNoC assume that a block always has to output samples within a > certain time limit? Can someone explain to me, where the timeout is checked > and raised? > > You can find

Re: [USRP-users] About RFNoC development

Hey Leo, On Thu, Apr 5, 2018 at 3:01 PM, Leandro Echevarría via USRP-users < usrp-users@lists.ettus.com> wrote: > Hey everybody, > > I've begun working on an X310 board, and I need to make modifications to > the Verilog code to include my own code. My strength is on HDL design, but > I lack

[USRP-users] Updated rfnoc-devel Branches

I tried re-building the FPGA and host code for rfnoc-devel last night, and I received an error about a major compat number being too low in UHD for the DDC. I linked it to commit d588005fd87dd2594adb29dbbdcf948bbb0ab0c1, cherry picked it, and the message went away. Unfortunately, my simple radio

Re: [USRP-users] RFNoC FPGA clear_tx_seqnum behavior

Hey Jason, On Thu, Jun 28, 2018 at 3:31 PM Jason Matusiak via USRP-users < usrp-users@lists.ettus.com> wrote: > I know this is an older thread, but I too am struggling to bring a block that > someone else designed for us in 2015.4 to work in 2017.4. I dug around but I > don't see any of our

Re: [USRP-users] RFNoC FPGA clear_tx_seqnum behavior

On Fri, Jun 29, 2018 at 9:57 AM Jason Matusiak < ja...@gardettoengineering.com> wrote: > I missed that, thanks for the heads up. I replaced the > two chdr_deframer_2clk functions with the old chdr_deframer, but that > didn't seem to fix things for me. Guess I will have to do a deep dive into >

Re: [USRP-users] Transmit Thread Stuck Receiving Tx Flow Control Packets

I have rebuilt the FPGA using Juan Francisco's suggestion in the DMA FIFO, and since then I haven't run into the problem using UHD v3.13.0.1. His patch was: OUTPUT2: begin // Replicated write logic to break a read timing critical path for read_count read_count <= (output_page_boundry <

Re: [USRP-users] X300 TX Pulse odd behavior

Maybe ramp up time for the transmitter? If you send 2.5us worth of 0's before your 1000 samples, do you see the appropriate number of pulse burst length? This method would be a compromise between the two methods you described. Does that work for you? Brian On Tue, Oct 16, 2018 at 6:19 PM Ryan

Re: [USRP-users] X300 TX Pulse odd behavior

It would depend on the daughterboard being used with the X300 I believe. Which daughterboard are you using? Brian On Tue, Oct 16, 2018 at 7:23 PM Ryan Marlow wrote: > Hey Brian, > Thanks for the suggestion. I think that idea should work for me. Is there > anywhere that documents the X300 TX

Re: [USRP-users] Ettus x310 shutoff delay when using low sample rate

On Tue, Oct 30, 2018 at 11:25 AM Marcus D. Leech via USRP-users < usrp-users@lists.ettus.com> wrote: > On 10/30/2018 10:42 AM, Daniel May via USRP-users wrote: > > Is there a way to query the amount of data in the FIFO so that I can wait > until it clears? > > I don't believe so. > There's a

[USRP-users] DMA FIFO Resizing

I noticed that the dma_fifo_block_ctrl.hpp file isn't included in the installation of UHD as of current master: https://github.com/EttusResearch/uhd/blob/6af6ac32c30d2dc0efa6eab61e4a3920649e3e62/host/include/uhd/rfnoc/CMakeLists.txt It seems like this is just a simple oversight, so I modified

Re: [USRP-users] DMA FIFO Resizing

Hey Marcus, On Mon, Sep 24, 2018 at 5:22 PM Marcus Müller wrote: > Hello Brian, > > so, the power-of-two FIFO sizes pretty much happen because you can only > divide addresses by full bit prefixes. That seems to be reflected in > noc_shell.v; not quite sure how deep the changes would have to go

Re: [USRP-users] RFNoC loopback

On Wed, Sep 26, 2018 at 10:36 AM Daniel Rauschen via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi all, > > I have a question regarding a RFNoC loopback in plain UHD. > > I am familiar with [1] and I have a working solution with gr-ettus and > python. The problem is, I can not figure out

Re: [USRP-users] Faster way to send asynchronous data to RFNoC block

On Wed, Dec 19, 2018 at 12:53 PM J M via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > I'm trying to load a RAM inside an RFNoC block, and doing this via > register writes takes about a minute and half. > > So, looking for a quicker way to load up the data from the RAM, thought >

Re: [USRP-users] N310 Band Pass filter frequencies

On Fri, Dec 21, 2018 at 7:51 AM David Bengtson via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi- > > The N310 receiver has a set of switchable bandpass filters on the > receiver inputs. I've looked through the N310 knowledge base, and > haven't come across any documentation on these

Re: [USRP-users] N310 Band Pass filter frequencies

On Fri, Dec 21, 2018 at 11:49 AM David Bengtson wrote: > So I dug into this (On a 10k piece of equipment?) and came up with the > following bands > > 1: 3000 to 6000 > 2: 2200 to 2800 > 3: 1650 to 2200 > 4: 1400 to 1575 > 5: 700 to 1000 > 6: 500 to 530 > plus 1 unfiltered path. > Also looks

Re: [USRP-users] rfnoc problem with custom DDC inputs.

Hey Carlos, The attached patch is what I used applied to 3.13.0.1 I want to say. You get the idea. To get the controller, I use get_block_ctrl(uhd::rfnoc::block_id_t(0, "NAME", 0)) since there is only one instance, for me, in my radio. When setting up the uhd::device_addr_t, I populate:

Re: [USRP-users] Is there any method for X310 to support 122.88M Sampling rate?

On Fri, Nov 30, 2018 at 11:29 AM Marcus Müller via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi J. Jeffson, > > to answer quickly: see below. > On Fri, 2018-11-30 at 11:36 +0800, 蒋逸凡 via USRP-users wrote: > > Hi all > > I'm trying to use USRP X Series (2943/2954) in my project. I

Re: [USRP-users] X310's sample rate

On Tue, Dec 4, 2018 at 10:35 AM Jason Matusiak via USRP-users < usrp-users@lists.ettus.com> wrote: > I have a X310 with a pair of CBX-130s installed and am running RFNoC. The > flowraph looks like this: > > > Radio (running at 200MHz) -> DDC (200MHz down to 50MHz) -> splitter -> > off to some

Re: [USRP-users] rfnoc problem with custom DDC inputs.

Hey Carlos, On Tue, Dec 4, 2018 at 1:16 PM Carlos Alberto Ruiz Naranjo < carlosruiznara...@gmail.com> wrote: > Hi Brian, > > I have finished the DDC block 1:8 and it works perfectly!! :) :) > Congratulations! > > Now I am in my final step, a 2:16 DDC block: > - Channels 0:7 connected to input

Re: [USRP-users] Replay Block: Stream using both channels to different radios simultaneously

On Wed, Dec 5, 2018 at 4:13 PM Max Thomas via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > When attempting to stream different waveforms using both channels of the > replay block simultaneously to two radios on the same USRP (X310) there are > under-runs. Any ideas why this is

Re: [USRP-users] Can I use chained DDCs?

On Mon, Dec 3, 2018 at 11:32 AM Jason Matusiak via USRP-users < usrp-users@lists.ettus.com> wrote: > Actually, upon further review, I can get this to happen with the stock XG > image and as simple flowgraph as possible. > > If I run the stock image as non-RFNoC seems to be fine, so it has >

Re: [USRP-users] Can I use chained DDCs?

Hey Jason, On Mon, Dec 3, 2018 at 11:50 AM Jason Matusiak < ja...@gardettoengineering.com> wrote: > Brian, > > I am not sure what the issue is here. I don't think it is the chained DDC > anymore as I can see the issue with the single DDC using multiple different > bitfiles. > > I wasn't

Re: [USRP-users] rfnoc problem with custom DDC inputs.

Hey Carlos, On Tue, Nov 27, 2018 at 6:18 PM Carlos Alberto Ruiz Naranjo < carlosruiznara...@gmail.com> wrote: > Hello Brian, > > Thank you very much for answering, I am spending a lot of time on this and > I do not see the way out. > > I am following your advice, I have removed the 3 inputs of

Re: [USRP-users] rfnoc problem with custom DDC inputs.

On Wed, Nov 28, 2018 at 9:43 AM Carlos Alberto Ruiz Naranjo < carlosruiznara...@gmail.com> wrote: > Thank you! I already have enough work to continue :) > > One last thing. In the split_stream module, did you concat tuser with > m_axis_data_tuser with m_axis_data_tdata? > No tuser at that point.

Re: [USRP-users] RFNoC FFT block scaling

On Mon, Nov 19, 2018 at 2:47 PM Rob Kossler via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > Can anyone offer advice regarding the RFNoC FFT scaling argument? It is > not clear to me if this argument should always be left alone or if it > should be adjusted as needed by the user for

Re: [USRP-users] rfnoc problem with custom DDC inputs.

On Mon, Nov 26, 2018 at 12:14 PM Carlos Alberto Ruiz Naranjo via USRP-users wrote: > Hello, > > I have customized the rfnoc DDC. I have: > > - 4 inputs (0,1,2,3). > - 4 outputs (0,1,2,3). > - 4 independently tunable DDCs. > - Input 0 connected to outputs 0,1,2,3. > - Input 1,2,3 disconnected. >

Re: [USRP-users] Faster way to send asynchronous data to RFNoC block

On Wed, Dec 19, 2018 at 4:24 PM J M wrote: > Potentially, yes the full 200 MHz > Ah, yes. Then you'd need 2 connections to the crossbar. If you didn't need all 200MHz, then you could get away with 2 ports off the same crossbar connection as well. I think you would just have each connection

Re: [USRP-users] Faster way to send asynchronous data to RFNoC block

On Wed, Dec 19, 2018 at 4:06 PM J M wrote: > The block is performing some signal processing on incoming samples > streaming from a radio block, but the signal processing is based on the > data stored in the ram. It would be ideal to be able to swap out the RAM > while the block is streaming,

Re: [USRP-users] Faster way to send asynchronous data to RFNoC block

On Wed, Dec 19, 2018 at 6:22 PM J M wrote: > Some of that makes sense to me. Do you know of an open source example > where something similar to this is done? > No, but it shouldn't be too bad to try and simulate. Make a top block with 2 sets of AXI streaming associated with bus_clk, then

Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

On Tue, Feb 19, 2019 at 5:42 AM Armin Schmidt via USRP-users < usrp-users@lists.ettus.com> wrote: > Hallo, > We're about to migrate from multi-usrp-application with UHD 3.9 and > custome FPGA to UHD 3.14 with RFNoC. We are using the USRP x310 with > daughterboards ubx-160. Everything seems to

Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

On Wed, Feb 20, 2019 at 7:45 PM Jonathon Pendlum wrote: > Hi Armin, > > You can reset X3x0 series devices via a register write with the following > command (this is in to your UHD src directory): > firmware/usrp3/x300/x300_debug.py --addr 192.168.40.2 --poke=0x00100058 > --data=1. > Can you

Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

On Fri, Feb 22, 2019 at 6:19 PM Martin Braun wrote: > This pokes a register in the STC3. It'll pull the FPGA into reset. You > then need to wait a bit before the FPGA is back up. > So it's a forced reload of the FPGA from the onboard image. To use this in software, I'd issue the command, then

Re: [USRP-users] [Discuss-gnuradio] continous Tx voice transmission

On Wed, Mar 6, 2019 at 3:12 PM Marcus Müller wrote: > I've had rather longish discussions on how to solve this; essentially: > for something that actually *solves* the issue (instead of postponing > it), as Ian said, you'd need to have clock domain crossing ability. > Could message passing from

Re: [USRP-users] Problem with usrp-2900 and GNU Radio

On Sat, Mar 9, 2019 at 1:45 PM Thomas Lavarenne via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello, > I'm new here and pretty new with usrp. I'm trying to use usrp-2900 with > GNU Radio and Ubuntu 18.04, but i have this problem (latest driver uhd from > source): > > ''' > linux; GNU C++

Re: [USRP-users] Problem with usrp-2900 and GNU Radio

You've got a dual-install issue here. On Sat, Mar 9, 2019 at 2:35 PM Thomas Lavarenne via USRP-users < usrp-users@lists.ettus.com> wrote: > uhd_probe seems good, but same error in GNU Radio.. (RuntimeError: > RuntimeError: Expected FPGA compatibility number 14, but got 16:) > > $ uhd_usrp_probe

Re: [USRP-users] RFNoC DDC/Radio block/port restrictions

On Tue, Mar 19, 2019 at 1:52 PM Rob Kossler via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > Are there restrictions regarding which DDC ports must be connected to > which Radio ports. I am using an X310/UBX with a custom C++ rfnoc > application and would like to do the following: >

Re: [USRP-users] X300 REF OUT drive capability

Check U530 on page 11, A1: https://files.ettus.com/schematics/x300/x3xx.pdf It's a FIN1002 LVDS receiver. Datasheet says 16mA max: http://www.mouser.com/ds/2/149/FIN1002-108110.pdf Brian On Tue, Feb 12, 2019 at 11:16 AM Jason Roehm via USRP-users < usrp-users@lists.ettus.com> wrote: >

Re: [USRP-users] USRP x310 with multi_usrp and RFNoC

On Tue, Feb 19, 2019 at 12:07 PM Armin Schmidt wrote: > Thanks for your replay! Hm, yes I've thought also about to use > STREAM_MODE_STOP_CONTINUOUS, but I would like to be able to restart my app > also after a crash. Ok, it should never happen, but one can never guarantee > that case. Do you

Re: [USRP-users] 2 DMAfifo blocks?

On Mon, Jan 28, 2019 at 3:42 PM Jason Matusiak via USRP-users < usrp-users@lists.ettus.com> wrote: > Is it possible to have two different DMAFifo RFNoC blocks on an X310? I > am not worried about the resources so much as how to implement it (I know > that I cannot add it to the uhd_image_builder

Re: [USRP-users] Propagation delay in TxStreamer X310 3.14.0.0

On Tue, Apr 9, 2019 at 12:13 PM Tillson, Bob (US) via USRP-users < usrp-users@lists.ettus.com> wrote: > I see this a lot with short waveforms as it is much more impactful. > > When you submit samples, there are previous samples within the buffer > (there always are) and the "entire" waveform

Re: [USRP-users] Relationship between IQ values, gain and noise on B205mini transmitter

On Thu, May 9, 2019 at 1:03 PM Michael Deacon wrote: > I hope this is what you are looking for. Would clipping here be an > indication of saturation? > Not quite. You may be able to look at the CCDF of the output and see if it hits a brick wall versus the "good" picture. I'd much prefer to

Re: [USRP-users] Relationship between IQ values, gain and noise on B205mini transmitter

On Wed, May 8, 2019 at 7:28 PM Michael Deacon via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello, > > > > I have a simple transmitter consisting of a file source connected to a > USRP sink (attached image radio.png). The file contains interleaved > floating point IQ representing a few

Re: [USRP-users] Relationship between IQ values, gain and noise on B205mini transmitter

What does the signal look like in the time domain? Is it driving the amplifier on the B205mini into saturation? Brian On Wed, May 8, 2019 at 7:57 PM Michael Deacon wrote: > I added some attenuation. The overload is gone but the condition persists. > > > > Thanks, > > > > Mike > > > > *From:*

Re: [USRP-users] Writing and reading from ddr3 in usrp x310

On Sun, May 12, 2019 at 6:34 AM Daniel Ozer via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello, > Im trying to write and read data from the ddr3 ram in the usrp x310 using > the fpga. > I wasn't able to find if there is any other blocks that use the ram (in > the defualt image ) . >

Re: [USRP-users] 9361 Sample Rate question

On Fri, Apr 26, 2019 at 6:09 AM Chintan Patel via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > On the B210 devices which use the AD9361, what is the granularity on the > sample rate supported? I know the max sample rate is 61.44MHz, and that the > BBPLL that drives the ADC sample

Re: [USRP-users] Vivado versions for RFNoC

2017.4 is the latest version that is supported I believe. Brian On Sun, May 5, 2019 at 6:36 AM Sam mite via USRP-users < usrp-users@lists.ettus.com> wrote: > I want to know what are the current supported vivado versions for X300 and > X310 and also for E310 and E320 for generating RFNoC images?

Re: [USRP-users] B210 mini I/Q imbalance?

Since it's AM, try shifting your center frequency by a little bit. Extract the envelope the same way, though. My thought is the DC cancellation circuitry in the 9361 is killing your AM waveform, so use a low-IF approach instead. Brian On Sun, May 5, 2019 at 1:05 PM franz kurniawan via

Re: [USRP-users] how can i receive 2 different signals with the USRP B210

On Wed, May 8, 2019 at 5:43 AM Marwa Boukhari via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > I want to send and receive a Signal at the frequency 900MHz with the > Channel 0 , and want to receive another Signal from the generator at the > frequency 5,68GHz with the other channel. >

Re: [USRP-users] get_time_now() blocking?

On Tue, Apr 23, 2019 at 2:06 PM Fabian Schwartau via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi everyone, > > I just found another strange thing. Can get_time_now() be in any case > blocking? Like long blocking? It takes more than 1 second to return! > I am heavily using timed commands,

Re: [USRP-users] Propagation delay in TxStreamer X310 3.14.0.0

On Tue, Apr 9, 2019 at 11:35 AM Michael R. Freedman via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello, > > > I am doing timed streaming. It appears to me that there are several > "zero" samples getting to the DAC prior to my waveform and as a result, > my waveform is being truncated.

Re: [USRP-users] Propagation delay in TxStreamer X310 3.14.0.0

On Tue, Apr 9, 2019 at 11:46 AM Michael R. Freedman wrote: > I'm generating samples at 2MHz. > What Ettus radio are you using? Brian ___ USRP-users mailing list USRP-users@lists.ettus.com

Re: [USRP-users] RFNoC Testbench for custom block with AXI_CONFIG_BUS

On Mon, Jul 22, 2019 at 5:18 PM Brian Padalino wrote: > On Mon, Jul 22, 2019 at 5:12 PM Brian Padalino > wrote: > >> You just need to write_reg() and use an address of SR_AXI_CONFIG for >> everything other than the last value, and use SR_AXI_CONFIG_TLAST for the >> last one. >> >> That should

Re: [USRP-users] RFNoC Testbench for custom block with AXI_CONFIG_BUS

On Mon, Jul 22, 2019 at 5:12 PM Brian Padalino wrote: > You just need to write_reg() and use an address of SR_AXI_CONFIG for > everything other than the last value, and use SR_AXI_CONFIG_TLAST for the > last one. > > That should push the valid high on the config line for each write you do, > and

Re: [USRP-users] RFNoC Testbench for custom block with AXI_CONFIG_BUS

You just need to write_reg() and use an address of SR_AXI_CONFIG for everything other than the last value, and use SR_AXI_CONFIG_TLAST for the last one. That should push the valid high on the config line for each write you do, and then on the last write both valid and tlast will be held. Brian

Re: [USRP-users] UHD not showing USB version through which my X310 is connected

On Wed, Jul 24, 2019 at 8:11 AM Rodolphe Bertolini via USRP-users < usrp-users@lists.ettus.com> wrote: > I apologize if this is a duplicated email. > > Hello community, > > uhd_usrp_probe (and all the others commands) doesn't log the USB version > to which the USRP is operating. > > Instead it

Re: [USRP-users] RFNoC Crossbar and Block data rates

On Thu, Sep 19, 2019 at 11:18 AM Felix Greiwe wrote: > Hi Brian, > > thank you for your help. > > I have on question left. You say the crossbar is non blocking. Does that > mean it can supply multiply RFNoC Blocks with input data at once at its > full bus_clk speed? Or does it switch between the

Re: [USRP-users] RFNoC Crossbar and Block data rates

On Thu, Sep 19, 2019 at 9:39 AM Felix Greiwe via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello together, > > I have some questions concerning clock speeds and the corresponding data > rates on a USRP x310 (FPGA). As far as I know, there are two different > clock speeds on the FPGA, the

Re: [USRP-users] Issues with RFNoC Component Test Bench

On Wed, Nov 13, 2019 at 10:54 AM Jonathan Lockhart via USRP-users < usrp-users@lists.ettus.com> wrote: > Greetings USRP Users, > > I am having another issue with the UHD-3.14 build I can't seem to shake > down. I have been going through this guide on the KB to learn how to use > the rfnocmodtool

Re: [USRP-users] Issues with RFNoC Component Test Bench

Hey Jon, On Wed, Nov 13, 2019 at 11:17 AM Jonathan Lockhart wrote: > Greetings Brian, > > I had noticed that the script was set to use the X300 after I sent the > email. I switched in the CMakeList.txt file to use the e300 repo, which is > using the Zynq-7020, which is included in the webpack

Re: [USRP-users] IQ-sample with a magnitude larger than 1.0

On Thu, Nov 21, 2019 at 2:49 PM Lindstedt, Ralf via USRP-users < usrp-users@lists.ettus.com> wrote: > We are transmitting samples in bursts of 15360 samples(1ms @ > 15.36Msamples/s). When the magnitudes of the transmitted samples are mostly > larger than 1.0, the received signal, especially the

Re: [USRP-users] IQ-sample with a magnitude larger than 1.0

On Tue, Dec 3, 2019 at 1:53 PM Jeff S wrote: > I'm fairly new to GNURadio, so I may have (most likely) missed it, but I > had the same problem that was fixed by multiplying the complex number going > into my sink by 0.25 to get my QPSK modulation to work on my X310. Since > doing that, I have

Re: [USRP-users] Run time issue with 3.14.1.1 (X300 with UBX)

On Mon, Jan 13, 2020 at 5:23 AM voonna santosh via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi Sam, >I have managed to reproduce this issue and when it happens, here is the > info you have asked for: > > > 1: lo: mtu 65536 qdisc noqueue state UNKNOWN group > default qlen 1000 >

Re: [USRP-users] Measuring TDOA for Localization

On Thu, Jan 9, 2020 at 12:14 PM Richard Bell via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello, > > I'm working on a TDOA based localization platform using 3 USRP X300's as > receivers. I have them synchronized with a 10 MHz ref and PPS signal > generated by an OctoClock. However, I'm

Re: [USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found

On Wed, Jan 8, 2020 at 8:00 AM Felix Greiwe via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi EJ, > > thank you for your answer! To make my error more traceable, I created a > new OOT Module and added the default gain block from rfnoc getting > started. > > I also took your advice and

Re: [USRP-users] Measuring TDOA for Localization

On Thu, Jan 9, 2020 at 6:45 PM Richard Bell wrote: > No I don't need to know phase information. I'm cross correlating the pairs > of receivers and the location of the peak gives me the TDOA. If the > hardware chains across different radios introduce different delays, that > would invalidate the

Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers

On Thu, Jan 2, 2020 at 11:48 AM Jerrid Plymale wrote: > I am trying to generate a custom RFNoC FPGA Image using this version of > UHD. > OK. So you've checked out fde2a94eb7231af859653db8caaf777ae2b66199 and you're trying to build a regular image with Vivado 2018.3. Correct? Brian >

Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers

On Thu, Jan 2, 2020 at 11:24 AM Jerrid Plymale via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello Marcus, > > So I tried cleaning the uhd-fpga folder as you suggested, however I ended > up getting the same errors and the image still failed to build. I have > attached the build log again

Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers

On Thu, Jan 2, 2020 at 11:42 AM Jerrid Plymale wrote: > Hello Brian, > > > > I have installed UHD 3.15.0.0-124-geb448043 > And this is what you're trying to build? Brian > ___ USRP-users mailing list USRP-users@lists.ettus.com

Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers

On Fri, Jan 3, 2020 at 1:14 PM Cherif Diouf via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi Jerrid, > > > > Some hints, for info, I am working with the X310 device, but you can > take the big picture. > > > I previously met such issues, those were related to signal re-definitions. > >

Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers

On Fri, Jan 3, 2020 at 1:41 PM Cherif Diouf wrote: > I have this version UHD 3.15.0.git-84-g164d76dc > > but the lines are there whenever you use the ./uhd_image_builder.py > scripts. > Ah, I see it now:

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