On Wed, Dec 19, 2018 at 6:22 PM J M <[email protected]> wrote: > Some of that makes sense to me. Do you know of an open source example > where something similar to this is done? >
No, but it shouldn't be too bad to try and simulate. Make a top block with 2 sets of AXI streaming associated with bus_clk, then instantiate a noc_shell for each port each with their own ID to it. Then the one port can be associated with RAM initialization, and the other port can be for streaming data. I'm sure it'll potentially expose some strange interactions between things, but one problem at a time, right? Brian >
_______________________________________________ USRP-users mailing list [email protected] http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
