Hi!
I have an error with fosphor_display:
Generating: '/home/cruiz/repositorios/sample_rfnoc.py'
Executing: /usr/bin/python -u /home/cruiz/repositorios/sample_rfnoc.py
File "/home/cruiz/repositorios/sample_rfnoc.py", line 147
self.uhd_rfnoc_fosphor_display = Template error: #set $win =
Hey Jon,
Is it possible to connect this block to an RFNoC port and not use it? Use
others.
2018-07-31 4:49 GMT+02:00 Jon Pendlum via USRP-users <
usrp-users@lists.ettus.com>:
> Hey Jason,
>
> The block is functionally complete, in fact I think it was the first
> block ever made. There is a UHD
Hello,
how can I connect in RFNoC a port to a null source in GNURadio?
Thank you.
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I have the same problem, any help? ^^
2017-06-06 13:45 GMT+02:00 Barker, Douglas W. via USRP-users <
usrp-users@lists.ettus.com>:
> Hello,
>
>
>
> Is there any update on our issue?
>
>
>
> Thanks
>
> Doug
>
>
>
> *From:* Jonathon Pendlum [mailto:jonathon.pend...@ettus.com]
> *Sent:* Monday, May
Ok! Thank you :)
El jue., 13 dic. 2018 a las 20:26, Marcus D. Leech ()
escribió:
> On 12/13/2018 02:24 PM, Carlos Alberto Ruiz Naranjo wrote:
> > My problem is that I use the USRPX310 with: default blocks + 1 custom
> > rfnoc blocks.
> >
> > And I am sharing the USRP with a co-worker who uses
Thanks for the reply.
If I add a rfnoc block but keep the others, could I use UHD python API?
El jue., 13 dic. 2018 a las 19:37, Marcus D. Leech via USRP-users (<
usrp-users@lists.ettus.com>) escribió:
> On 12/13/2018 01:21 PM, Carlos Alberto Ruiz Naranjo via USRP-users wrote:
My problem is that I use the USRPX310 with: default blocks + 1 custom rfnoc
blocks.
And I am sharing the USRP with a co-worker who uses the python API with
defautl blocks.
Could we share the same custom FPGA image?
Thank you.
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Hello,
I have found a USRP1 and I am playing with it. I have this error:
carlos@carlos-pc:~$ sudo uhd_usrp_probe --args="type=usrp1"
[INFO] [UHD] linux; GNU C++ version 7.3.0; Boost_106501;
UHD_4.0.0.rfnoc-devel-702-geec24d7b
[INFO] [USRP1] Opening a USRP1 device...
[INFO] [USRP1] Using FPGA
Any idea?
Thank you.
El mar., 11 dic. 2018 a las 22:42, Marcus D. Leech via USRP-users (<
usrp-users@lists.ettus.com>) escribió:
> On 12/11/2018 04:36 PM, Carlos Alberto Ruiz Naranjo via USRP-users wrote:
> > Hello,
> >
> > I have found a USRP1 and I am playing with
t by hand.
>
>
>
> Robin Coxe | Chief R Program Manager, SDR | Santa Clara, CA |
> 408.610.6363
>
> --
> *From:* USRP-users on behalf of
> Carlos Alberto Ruiz Naranjo via USRP-users
> *Sent:* Wednesday, December 12, 2018 4:17 AM
> *To:*
Hello,
it is posible use UHD python API with a custom USRP X310 image?
Thank you.
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Hi Brian,
I have finished the DDC block 1:8 and it works perfectly!! :) :)
Now I am in my final step, a 2:16 DDC block:
- Channels 0:7 connected to input 0.
- Channels 8:15 connected to input 1.
The verilog module works, but I have a problem with the UHD driver. I have
timeout on chan
Hello Brian,
thanks for your answer! I have returned today and I am testing your changes.
I am using grc and I have the error:
*thread[thread-per-block[0]: ]: LookupError:
KeyError: [0/Radio_0] sr_write(): No such port: 18446744073709551615*
I assume the error is in the configuration of
Ok, I had a problem with *radio_block_port. *I had a signed number... :(
I think now it runs. I will pass to 1:8 DCC and later with 2:16 DDC. I
continue... :)
El lun., 3 dic. 2018 a las 16:09, Carlos Alberto Ruiz Naranjo (<
carlosruiznara...@gmail.com>) escribió:
> Hello Brian,
>
> thanks for
Hello Brian,
I have finished the FPGA code. I got a DDC 1:2 but I have problems with
1:8. I think I have your same problems: /
*thread[thread-per-block[0]: ]: LookupError:
KeyError: [0/Radio_0] sr_write(): No such port: 2*
In rfnoc code:
*std::vector >
upstream_radio_nodes =
26, 2018 at 12:14 PM Carlos Alberto Ruiz Naranjo via
> USRP-users wrote:
>
>> Hello,
>>
>> I have customized the rfnoc DDC. I have:
>>
>> - 4 inputs (0,1,2,3).
>> - 4 outputs (0,1,2,3).
>> - 4 independently tunable DDCs.
>> - Input 0 co
Ok! Thank you :)
El mié., 28 nov. 2018 a las 16:13, Brian Padalino ()
escribió:
> On Wed, Nov 28, 2018 at 9:43 AM Carlos Alberto Ruiz Naranjo <
> carlosruiznara...@gmail.com> wrote:
>
>> Thank you! I already have enough work to continue :)
>>
>> One last thing. In the split_stream module, did
Hello,
I have customized the rfnoc DDC. I have:
- 4 inputs (0,1,2,3).
- 4 outputs (0,1,2,3).
- 4 independently tunable DDCs.
- Input 0 connected to outputs 0,1,2,3.
- Input 1,2,3 disconnected.
I attach a diagram.
But I do not know how to connect inputs 1,2,3 to a null source for . Any
ideas?
Hello,
I'm using the USRP X310 with CBX-120. I set the radio sample rate to 184.32
MHz but I have the following message:
[WARNING] [X300 RADIO] Requesting invalid sampling rate from device: 184.32
MHz. Actual rate is: 200 MHz.
Isn't it possible to set it to that sample rate?
Thank you.
Thank you Brian! It runs fine :)
El lun., 11 may. 2020 a las 17:08, Brian Padalino ()
escribió:
> On Mon, May 11, 2020 at 6:20 AM Carlos Alberto Ruiz Naranjo via USRP-users
> wrote:
>
>> Hello,
>>
>> I'm using the USRP X310 with CBX-120. I set the radio sample rate
Then I will try with 4 ports in DmaFIFO.
Later maybe I will need to add more ports, does anyone have any ideas? 2
DmaFIFO, big FIFO_LOOPBACK? The throughput is about 11MSamples. I would
like to know the complex about that, because maybe it doesn't be possible
for my project.
El jue., 21 may. 2020
Hi Rob,
I'm using UHD-3.15.LTS and I have developed a custom DUC with N inputs and
1 output. I have done the same with the DDC (1:N) and it works fine. But
with the DUC I have the problem with the DMA_FIFO, I need one DMA_FIFO
channel per DUC channel. I have thought about some solutions and I
Thank you for the response Brian :)
The throughput is about 11MSamples.
What about to use the AXI_FIFO_LOOPBACK?
El jue., 21 may. 2020 a las 20:17, Brian Padalino ()
escribió:
> On Thu, May 21, 2020 at 1:55 PM Carlos Alberto Ruiz Naranjo via USRP-users
> wrote:
>
>> Hello,
>&
Hello,
Is it possible to instance multiple DMA_FIFO blocks? I suppose I have to do
it manually in the x300_core.v. Is there any limitation?
Could I increase the size of the AXI_FIFO_LOOPBACK block and replace it by
DMA_FIFO in a configuration? Host -> DMA_FIFO -> DUC -> Radio
Thank you.
Hi,
I'm customizing the DUC block to do it 2input:1output
input 0 ---> DUC --->
add ---> output
input 1 ---> DUC --->
I have added an addsub module between dds_timed and axi_wrapper. Apparently
it works fine. I can see two tones in the output if the
This is the code for the adder (between dds_timed and axi_wrapper):
assign s_axis_data_tvalid2[0] = s_axis_data_tvalid[1] & s_axis_data_tvalid[0
];
assign s_axis_data_tvalid2[1] = s_axis_data_tvalid[1] & s_axis_data_tvalid[0
];
assign s_axis_data_tuser2 = s_axis_data_tuser;
assign
Hi,
I have modified the DUC block to do it 2inputs-1outputs. The output is
duc_0 + duc_1.
input_0 ---> duc_0 --->
cadd ---> output
input_1 ---> duc_1 --->
Apparently it works fine, but after 1 second I have timeout problems and
the output is weird.
ode does not assert tready for
> either input until the tvalid is asserted for both inputs.
>
> On Wed, Jun 3, 2020 at 6:06 AM Carlos Alberto Ruiz Naranjo via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hi,
>>
>> I have modified the DUC block to do i
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