[USRP-users] Addsub HLS Block Error

2019-09-03 Thread Quadri,Adnan via USRP-users
Hello, We are trying to run the RFNoC addsub HLS block. I was able to build the FPGA Image and made sure in the noc_block verilog code to point to the HLS implementation for addsub block on RFNoC as opposed to the verilog/VHDL implementation. But when we run the example Flowgraph with two

Re: [USRP-users] Addsub HLS Block Error

2019-09-03 Thread Quadri,Adnan via USRP-users
ug. Nick On Tue, Sep 3, 2019 at 1:48 PM Quadri,Adnan via USRP-users mailto:usrp-users@lists.ettus.com>> wrote: Hello, We are trying to run the RFNoC addsub HLS block. I was able to build the FPGA Image and made sure in the noc_block verilog code to point to the HLS implementation

Re: [USRP-users] Addsub HLS Block Error

2019-09-03 Thread Quadri,Adnan via USRP-users
hat it wasn't like this last time I checked (which was more than a year ago), so maybe it should be filed as a bug. Nick On Tue, Sep 3, 2019 at 1:48 PM Quadri,Adnan via USRP-users mailto:usrp-users@lists.ettus.com>> wrote: Hello, We are trying to run the RFNoC addsub HLS block. I was a

[USRP-users] RFNoC SVD Block

2019-09-06 Thread Quadri,Adnan via USRP-users
Hello, We are trying to perform singular vector decomposition. The idea is to work on an RFNoC block that takes in summation of samples from the Radio source and will perform SVD. Is anybody working on something similar? Currently, the RFNoC OFDM synchronizer block has timing constraint issues

Re: [USRP-users] RFNoC SVD Block

2019-09-11 Thread Quadri,Adnan via USRP-users
way of computing things, and your memory requirements might be much larger. Depending on the size of SVD you're planning to do, that might or might not be an issue. Best regards, Marcus On Fri, 2019-09-06 at 19:05 +0000, Quadri,Adnan via USRP-users wrote: > Hello, > > We are trying to perf

Re: [USRP-users] RFNoC SVD Block

2019-09-11 Thread Quadri,Adnan via USRP-users
e much larger. > Depending on the size of SVD you're planning to do, that might or > might > not be an issue. > > Best regards, > Marcus > > On Fri, 2019-09-06 at 19:05 +, Quadri,Adnan via USRP-users wrote: > > Hello, > > > > We are trying to perform sing

[USRP-users] Expected FPGA compatibility number mismatch

2019-09-11 Thread Quadri,Adnan via USRP-users
Hello, We were working on the Schimdl Cox and OFDM Equalizer blocks. We updated to the recent version of UHD and did the installation manually. There is a rfnoc installation as well, done earlier. (UHD in rfnoc is 4.0 but the new one is 3.14) With the newly installed UHD and few changes, we