Ehh, I dont think that's an accurate description of what's going on...
Take a look at the 32-bit floating point definition:
https://en.wikipedia.org/wiki/Single-precision_floating-point_format The
wikipedia definition seems to be essentially what's going on here, with the
added twist that the out
Hi EJ,
Thanks for the pointers. Ok, I think I see now that float_to_iq module is
fixed point. Am I interpreting these lines of code correctly that put an
8-bit bound on the mantissa with a 2's complement sign bit, leaving the
remaining 8-bits for radix:
assign shift_val = (in[30:23] > 127)? (in[
Hi Andrew,
As far as I can tell, that particular verilog block implements a 32-bit
floating point to 16-bit fixed point conversion. The name may be a misnomer
because it does not actually break the input into I/Q channels.
For floating to fixed conversion in software, I usually refer to this
wiki
EJ,
I spent some time wrestling with the 32-bit to 16-bit conversion in my
verilog noc block then realized doing the conversion in the C++ control
block driver might be more straightforward. I'm trying to digest the
following:
https://raw.githubusercontent.com/EttusResearch/fpga/b108e88865ee0fa68
Hi Andrew,
The OOT module .xml file definition currently only supports writing scalar
registers, so you need a custom C++ driver. The int_vector option has not
been implemented, and honestly I'm not sure if it would even make sense
because there's many different ways the HDL could implement a "vec
Typo, the 3rd to last paragraph should read:
Or I could hack *rfnoc_fir_cci()*. I started this by replacing int vectors
with std::complex vectors everywhere FIR taps were referenced in the
in-tree module's C++ library but I stopped when it traced up to block.h
because that may affect other modules
