Gilles Chanteperdrix wrote:
> Sebastian Smolorz wrote:
> > Gilles Chanteperdrix wrote:
> >>You can avoid this problem by adding LATCH or
> >>__ipipe_mach_ticks_per_jiffy to the current value of the match register
> >>in the timer interrupt, as it is done for the SA and PXA architectures.
> >
> > Un
Sebastian Smolorz wrote:
> Gilles Chanteperdrix wrote:
>>You can avoid this problem by adding LATCH or
>>__ipipe_mach_ticks_per_jiffy to the current value of the match register
>>in the timer interrupt, as it is done for the SA and PXA architectures.
>
>
> Unfortunately, this solution is not appl
Gilles Chanteperdrix wrote:
> Sebastian Smolorz wrote:
> > Gilles Chanteperdrix wrote:
> >>Sebastian Smolorz wrote:
> >>>Hi,
> >>>
> >>>here's a proposal for a minor change in the I-pipe implementation for
> >>>ARM. Since it is required for my S3C24xx patch not to call
> >>>__ipipe_mach_set_dec dir
Sebastian Smolorz wrote:
> Gilles Chanteperdrix wrote:
>
>>Sebastian Smolorz wrote:
>>
>>>Hi,
>>>
>>>here's a proposal for a minor change in the I-pipe implementation for
>>>ARM. Since it is required for my S3C24xx patch not to call
>>>__ipipe_mach_set_dec directly when the timer is released by th
Gilles Chanteperdrix wrote:
> Sebastian Smolorz wrote:
> > Hi,
> >
> > here's a proposal for a minor change in the I-pipe implementation for
> > ARM. Since it is required for my S3C24xx patch not to call
> > __ipipe_mach_set_dec directly when the timer is released by the Xenomai
> > domain I sugges
Sebastian Smolorz wrote:
> Hi,
>
> here's a proposal for a minor change in the I-pipe implementation for ARM.
> Since it is required for my S3C24xx patch not to call __ipipe_mach_set_dec
> directly when the timer is released by the Xenomai domain I suggest the
> following changes. The patch com
