Dear zaurus developers!
I used to delve into zaurus code for awhile ago. There are some local changes
left from that time.
One thing is the change to pxa pcmcia timings.
Here's the original code from 2.6.16:
static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
To reduce LCD dma interruption (i.e. LCD artifacts during pcmcia transfers) we
can raise it's priority
by means of LCSBSCNTR and ARB_CNTRL registers.
I used the following values on c3000:
LCDBSCNTR = 2
ARB_CNTRL = 0x01800f11
Those registers can be set in spitc.c/common_init, but I guess that the
kirill wrote:
> To reduce LCD dma interruption (i.e. LCD artifacts during pcmcia transfers)
> we can raise it's priority
> by means of LCSBSCNTR and ARB_CNTRL registers.
> I used the following values on c3000:
> LCDBSCNTR = 2
> ARB_CNTRL = 0x01800f11
>
> Those re
> Yes, patch would be nice. I am currently debugging some PCMCIA
> problems... Question: is/was there situation where your version worked
> but old one did not?
No.
> Does it provide faster data rates?
Yes, it does.
As I recall, pcmcia spec doesn't provide "fomula" to calculate cycle timings.
It d
Pavel Machek wrote:
> On Thu 2010-09-02 19:01:05, kirill wrote:
>> kirill wrote:
>>> To reduce LCD dma interruption (i.e. LCD artifacts during pcmcia transfers)
>>> we can raise it's priority
>>> by means of LCSBSCNTR and ARB_CNTRL registers.
kirill wrote:
>> Yes, patch would be nice.
Here's the patch. I didn't test it on 2.6.35, however the affected
functions are not changed from 2.6.1x. So it should work...
Note pcmcia_cycle_ns in original code. AFAIK it's not pcmcia cyce ns. See my
FIXME below.
diff -ru linu
Hi!
Recently I've upgraded internal cf on my c3000. So now I have a better idea of
what
cf storage performance you can get with c3000 hardwire.
Benchmark results (2.6.19 kernel, dd if=/dev/hda of=/dev/null):
1) unmodified kernel: ~ 2MB/sec
2) optimized timings, 250ns io cycle: ~ 3MB/sec
3) optim
Well, I tried your patch from the list on 2.6.26-RP.
I see 2.33 MB/sec -> 2.63MB/sec improvement on 6 years old 40x card.
In my experience, the speed in pcmcia mode is not related to card's
maximum speed.
I don't think that 6 year old CF supports advanced timing mode.
You may check it with hdp
19:46:44.0 +0400
@@ -0,0 +1,430 @@
+/*
+ * Support for "virtual" DMA transfers using the DMA controller of pxa2xx processors.
+ * Currently this code is only tested on PXA270 processor.
+ *
+ * Copyright 2006 Kirill Kornilov
+ *
+ */
+
+#include
+#include
+#include
+#include
+#inc
