Hi,

On Wed, Apr 24, 2013 at 12:42 PM, Joel Holdsworth
<[email protected]> wrote:
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> On 24/04/13 11:34, Bert Vermeulen wrote:
>> On 04/23/2013 03:21 PM, Iztok Jeras wrote:
>>> Hi,
>>>
>>> I am offering my help for writing RTL, bench code in Verilog. I
>>> have experience writing code which is portable across various
>>> vendors (Altera, Xilinx, Lattice should also work). I should be
>>> able to read the Wiki on the weekend. As far as I was looking
>>> into various FPGA based logic analyzers, the main issue is not
>>> the FPGA code but the various devices used to interface to USB. I
>>> also have some spare FPGA boards, but not really logic analyzers
>>> specific board, so I am not sure if they fit.
>>
>> Iztok,
>>
>> That's great to hear. As a way to get started with a portable
>> source base, would porting the demon core be a good start? It's
>> what we have already, after all.

I agree the demon core is a good start. I am already running:
svn2git http://gadgetforge.gadgetfactory.net/svn/butterflylogic
If there are no issues I will push it to Github, for now it seems slow
(already running for 8min).

>
> Right now I would say yes, we should just adopt the demon core and
> start hacking on it. Does someone want to import the SVN repo? I can
> do it if noone else wants to - but only as far as github.
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